Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h         |  3 +++
 target/mips/mod-msa32.decode    |  4 ++++
 target/mips/mod-msa64.decode    | 17 +++++++++++++++++
 target/mips/mod-msa_translate.c | 15 +++++++++++++++
 target/mips/translate.c         |  5 +++++
 target/mips/meson.build         |  5 +++++
 6 files changed, 49 insertions(+)
 create mode 100644 target/mips/mod-msa64.decode

diff --git a/target/mips/translate.h b/target/mips/translate.h
index 4eb218e2c9f..00601232b97 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -97,5 +97,8 @@ void msa_translate_init(void);
 
 /* decodetree generated */
 bool decode_msa32(DisasContext *ctx, uint32_t insn);
+#if defined(TARGET_MIPS64)
+bool decode_msa64(DisasContext *ctx, uint32_t insn);
+#endif
 
 #endif
diff --git a/target/mips/mod-msa32.decode b/target/mips/mod-msa32.decode
index d69675132b8..0b2f0863251 100644
--- a/target/mips/mod-msa32.decode
+++ b/target/mips/mod-msa32.decode
@@ -10,11 +10,15 @@
 #       (Document Number: MD00866-2B-MSA32-AFP-01.12)
 #
 
+&lsa                rd rt rs sa
 &msa_bz             df wt s16
 
+@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &lsa
 @bz                 ...... ... ..   wt:5 s16:16             &msa_bz df=3
 @bz_df              ...... ... df:2 wt:5 s16:16             &msa_bz
 
+LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
+
 BZ_V                010001 01011  ..... ................    @bz
 BNZ_V               010001 01111  ..... ................    @bz
 
diff --git a/target/mips/mod-msa64.decode b/target/mips/mod-msa64.decode
new file mode 100644
index 00000000000..8dcbbcd8538
--- /dev/null
+++ b/target/mips/mod-msa64.decode
@@ -0,0 +1,17 @@
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020  Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+#       MIPS Architecture for Programmers Volume IV-j
+#       The MIPS64 SIMD Architecture Module, Revision 1.12
+#       (Document Number: MD00868-1D-MSA64-AFP-01.12)
+#
+
+&lsa                rd rt rs sa !extern
+
+@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &lsa
+
+DLSA                 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/mod-msa_translate.c b/target/mips/mod-msa_translate.c
index 7e7fc0644ff..7af0c2fd657 100644
--- a/target/mips/mod-msa_translate.c
+++ b/target/mips/mod-msa_translate.c
@@ -20,6 +20,9 @@
 
 /* Include the auto-generated decoder.  */
 #include "decode-mod-msa32.c.inc"
+#if defined(TARGET_MIPS64)
+#include "decode-mod-msa64.c.inc"
+#endif /* TARGET_MIPS64 */
 
 #define OPC_MSA (0x1E << 26)
 
@@ -2268,3 +2271,15 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
 
     return true;
 }
+
+static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
+{
+    return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+#if defined(TARGET_MIPS64)
+static bool trans_DLSA(DisasContext *ctx, arg_LSA *a)
+{
+    return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+#endif /* TARGET_MIPS64 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 752a06afa21..b3c45d6211a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28311,6 +28311,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     /* Transition to the auto-generated decoder.  */
 
     /* ISA Extensions */
+#if defined(TARGET_MIPS64)
+    if (ase_msa_available(env) && decode_msa64(ctx, ctx->opcode)) {
+        return;
+    }
+#endif /* TARGET_MIPS64 */
     if (ase_msa_available(env) && decode_msa32(ctx, ctx->opcode)) {
         return;
     }
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 9e42c341a90..124b5f7d49d 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,6 +1,9 @@
 gen = [
   decodetree.process('mod-msa32.decode', extra_args: [ '--decode=decode_msa32' ]),
 ]
+gen64 = [
+  decodetree.process('mod-msa64.decode', extra_args: [ '--decode=decode_msa64' ]),
+]
 
 mips_ss = ss.source_set()
 mips_ss.add(gen)
@@ -18,6 +21,8 @@
   'translate_addr_const.c',
   'mod-msa_translate.c',
 ))
+mips_ss.add(when: 'TARGET_MIPS64', if_true: gen64)
+
 mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
 
 mips_softmmu_ss = ss.source_set()
-- 
2.26.2

On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
>      /* ISA Extensions */
> +#if defined(TARGET_MIPS64)
> +    if (ase_msa_available(env) && decode_msa64(ctx, ctx->opcode)) {
> +        return;
> +    }
> +#endif /* TARGET_MIPS64 */
>      if (ase_msa_available(env) && decode_msa32(ctx, ctx->opcode)) {
>          return;
>      }

Can we reduce the number of ifdefs involved?  Perhaps to zero?

    if (ase_msa) {
       if (TARGET_LONG_BITS == 64 && decode_msa64()) {
           return;
       }
       if (decode_msa32()) {
           return;
       }
    }

I realize this means extra decodetree invocations for mips32, but... does that
really matter?

I suppose some of the tcg expansions could not work for TCGv = TCGv_i32, which
wouldn't help the cause...


r~

On 12/8/20 2:36 PM, Philippe Mathieu-Daudé wrote:
> Add the LSA opcode to the MSA32 decodetree config, add DLSA
> to a new config for the MSA64 ASE, and call decode_msa64()
> in the main decode_opc() loop.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.h         |  3 +++
>  target/mips/mod-msa32.decode    |  4 ++++
>  target/mips/mod-msa64.decode    | 17 +++++++++++++++++
>  target/mips/mod-msa_translate.c | 15 +++++++++++++++
>  target/mips/translate.c         |  5 +++++
>  target/mips/meson.build         |  5 +++++
>  6 files changed, 49 insertions(+)
>  create mode 100644 target/mips/mod-msa64.decode

Assuming nothing better can be done about the ifdefs,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~