target/mips: Add some CP0/MMU missing definitions

[PATCH 0/3] target/mips: Add some CP0/MMU missing definitions

Philippe Mathieu-Daudé posted 3 patches 4 years, 11 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20201201132817.2863301-1-f4bug@amsat.org

Maintainers: Aurelien Jarno <aurelien@aurel32.net>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, "Philippe Mathieu-Daudé" <f4bug@amsat.org>, Jiaxun Yang <jiaxun.yang@flygoat.com>

target/mips/cpu.h                | 11 +++++++++--
target/mips/internal.h           |  9 +++++----
target/mips/translate_init.c.inc | 14 ++++++++------
3 files changed, 22 insertions(+), 12 deletions(-)

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[PATCH 0/3] target/mips: Add some CP0/MMU missing definitions

Posted by Philippe Mathieu-Daudé 4 years, 11 months ago

Add some MIPS3 and R6 definitions to ease code review.

Philippe Mathieu-Daudé (3):
  target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
  target/mips: Replace CP0_Config0 magic values by proper definitions
  target/mips: Explicit Release 6 MMU types

 target/mips/cpu.h                | 11 +++++++++--
 target/mips/internal.h           |  9 +++++----
 target/mips/translate_init.c.inc | 14 ++++++++------
 3 files changed, 22 insertions(+), 12 deletions(-)

-- 
2.26.2

Re: [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions

Posted by Richard Henderson 4 years, 11 months ago

On 12/1/20 7:28 AM, Philippe Mathieu-Daudé wrote:
> Add some MIPS3 and R6 definitions to ease code review.
> 
> Philippe Mathieu-Daudé (3):
>   target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
>   target/mips: Replace CP0_Config0 magic values by proper definitions
>   target/mips: Explicit Release 6 MMU types

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 0/3] target/mips: Add some CP0/MMU missing definitions

Posted by Philippe Mathieu-Daudé 4 years, 11 months ago

On 12/1/20 2:28 PM, Philippe Mathieu-Daudé wrote:
> Add some MIPS3 and R6 definitions to ease code review.
> 
> Philippe Mathieu-Daudé (3):
>   target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
>   target/mips: Replace CP0_Config0 magic values by proper definitions
>   target/mips: Explicit Release 6 MMU types
> 
>  target/mips/cpu.h                | 11 +++++++++--
>  target/mips/internal.h           |  9 +++++----
>  target/mips/translate_init.c.inc | 14 ++++++++------
>  3 files changed, 22 insertions(+), 12 deletions(-)

Thanks, applied to mips-next.