hvf: x86: Remove unused definitions

hvf: Introduce hvf vcpu struct

target/arm/kvm_arm.h | 2 -

Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>

Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>

---

v1 -> v2:

- Make safe to ctrl-C

v3 -> v4:

- Remove unused exe_full variable

- Reuse exe_name variable

The hvf i386 has a few struct and cpp definitions that are never

used. Remove them.

Suggested-by: Roman Bolshakov <r.bolshakov@yadro.com>

Signed-off-by: Alexander Graf <agraf@csgraf.de>

Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>

Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>

---

target/i386/hvf/hvf-i386.h | 16 ----------------

1 file changed, 16 deletions(-)

diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/hvf-i386.h

+++ b/target/i386/hvf/hvf-i386.h

@@ -XXX,XX +XXX,XX @@

#include "cpu.h"

#include "x86.h"

-#define HVF_MAX_VCPU 0x10

-

-extern struct hvf_state hvf_global;

-

-struct hvf_vm {

- int id;

- struct hvf_vcpu_state *vcpus[HVF_MAX_VCPU];

-};

-

-struct hvf_state {

- uint32_t version;

- struct hvf_vm *vm;

- uint64_t mem_quota;

-};

-

/* hvf_slot flags */

#define HVF_SLOT_LOG (1 << 0)

@@ -XXX,XX +XXX,XX @@ hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t);

/* Host specific functions */

int hvf_inject_interrupt(CPUArchState *env, int vector);

-int hvf_vcpu_run(struct hvf_vcpu_state *vcpu);

#endif

#endif

--

2.24.3 (Apple Git-128)

Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>

Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>

---

v3 -> v4:

- Use hv.h instead of Hypervisor.h for 10.15 compat

- Remove manual inclusion of Hypervisor.h in common .c files

We will need more than a single field for hvf going forward. To keep

the global vcpu struct uncluttered, let's allocate a special hvf vcpu

struct, similar to how hax does it.

Signed-off-by: Alexander Graf <agraf@csgraf.de>

Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>

Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

---

v4 -> v5:

- Use g_free() on destroy

---

accel/hvf/hvf-cpus.c | 8 +-

include/hw/core/cpu.h | 3 +-

include/sysemu/hvf_int.h | 4 +

target/i386/hvf/hvf.c | 102 +++++++++---------

target/i386/hvf/vmx.h | 24 +++--

target/i386/hvf/x86.c | 28 ++---

target/i386/hvf/x86_descr.c | 26 ++---

target/i386/hvf/x86_emu.c | 62 +++++------

target/i386/hvf/x86_mmu.c | 4 +-

target/i386/hvf/x86_task.c | 12 +--

target/i386/hvf/x86hvf.c | 210 ++++++++++++++++++------------------

11 files changed, 247 insertions(+), 236 deletions(-)

diff --git a/accel/hvf/hvf-cpus.c b/accel/hvf/hvf-cpus.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/hvf/hvf-cpus.c

+++ b/accel/hvf/hvf-cpus.c

@@ -XXX,XX +XXX,XX @@ static void hvf_cpu_synchronize_pre_loadvm(CPUState *cpu)

static void hvf_vcpu_destroy(CPUState *cpu)

{

- hv_return_t ret = hv_vcpu_destroy(cpu->hvf_fd);

+ hv_return_t ret = hv_vcpu_destroy(cpu->hvf->fd);

assert_hvf_ok(ret);

hvf_arch_vcpu_destroy(cpu);

+ g_free(cpu->hvf);

+ cpu->hvf = NULL;

}

static void dummy_signal(int sig)

@@ -XXX,XX +XXX,XX @@ static int hvf_init_vcpu(CPUState *cpu)

{

int r;

+ cpu->hvf = g_malloc0(sizeof(*cpu->hvf));

+

/* init cpu signals */

sigset_t set;

struct sigaction sigact;

@@ -XXX,XX +XXX,XX @@ static int hvf_init_vcpu(CPUState *cpu)

pthread_sigmask(SIG_BLOCK, NULL, &set);

sigdelset(&set, SIG_IPI);

- r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT);

+ r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf->fd, HV_VCPU_DEFAULT);

cpu->vcpu_dirty = 1;

assert_hvf_ok(r);

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/core/cpu.h

+++ b/include/hw/core/cpu.h

@@ -XXX,XX +XXX,XX @@ struct KVMState;

struct kvm_run;

struct hax_vcpu_state;

+struct hvf_vcpu_state;

#define TB_JMP_CACHE_BITS 12

#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)

@@ -XXX,XX +XXX,XX @@ struct CPUState {

struct hax_vcpu_state *hax_vcpu;

- int hvf_fd;

+ struct hvf_vcpu_state *hvf;

/* track IOMMUs whose translations we've cached in the TCG TLB */

GArray *iommu_notifiers;

diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h

index XXXXXXX..XXXXXXX 100644

--- a/include/sysemu/hvf_int.h

+++ b/include/sysemu/hvf_int.h

@@ -XXX,XX +XXX,XX @@ struct HVFState {

};

extern HVFState *hvf_state;

+struct hvf_vcpu_state {

+ int fd;

+};

+

void assert_hvf_ok(hv_return_t ret);

int hvf_get_registers(CPUState *cpu);

int hvf_put_registers(CPUState *cpu);

diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/hvf.c

+++ b/target/i386/hvf/hvf.c

@@ -XXX,XX +XXX,XX @@ void vmx_update_tpr(CPUState *cpu)

int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4;

int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);

- wreg(cpu->hvf_fd, HV_X86_TPR, tpr);

+ wreg(cpu->hvf->fd, HV_X86_TPR, tpr);

if (irr == -1) {

- wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);

+ wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0);

} else {

- wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 :

+ wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 :

irr >> 4);

}

}

@@ -XXX,XX +XXX,XX @@ void vmx_update_tpr(CPUState *cpu)

static void update_apic_tpr(CPUState *cpu)

{

X86CPU *x86_cpu = X86_CPU(cpu);

- int tpr = rreg(cpu->hvf_fd, HV_X86_TPR) >> 4;

+ int tpr = rreg(cpu->hvf->fd, HV_X86_TPR) >> 4;

cpu_set_apic_tpr(x86_cpu->apic_state, tpr);

}

@@ -XXX,XX +XXX,XX @@ int hvf_arch_init_vcpu(CPUState *cpu)

}

/* set VMCS control fields */

- wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS,

+ wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS,

cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased,

VMCS_PIN_BASED_CTLS_EXTINT |

VMCS_PIN_BASED_CTLS_NMI |

VMCS_PIN_BASED_CTLS_VNMI));

- wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS,

+ wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS,

cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,

VMCS_PRI_PROC_BASED_CTLS_HLT |

VMCS_PRI_PROC_BASED_CTLS_MWAIT |

VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |

VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |

VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);

- wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,

+ wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS,

cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2,

VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));

- wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,

+ wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,

0));

- wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */

+ wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */

- wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);

+ wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0);

x86cpu = X86_CPU(cpu);

x86cpu->env.xsave_buf = qemu_memalign(4096, 4096);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_STAR, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_LSTAR, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_CSTAR, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FMASK, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FSBASE, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1);

- hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1);

+ hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1);

return 0;

}

@@ -XXX,XX +XXX,XX @@ static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_in

}

if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) {

env->has_error_code = true;

- env->error_code = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_ERROR);

+ env->error_code = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERROR);

}

}

- if ((rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &

+ if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) &

VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) {

env->hflags2 |= HF2_NMI_MASK;

} else {

env->hflags2 &= ~HF2_NMI_MASK;

}

- if (rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &

+ if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) &

(VMCS_INTERRUPTIBILITY_STI_BLOCKING |

VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {

env->hflags |= HF_INHIBIT_IRQ_MASK;

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

return EXCP_HLT;

}

- hv_return_t r = hv_vcpu_run(cpu->hvf_fd);

+ hv_return_t r = hv_vcpu_run(cpu->hvf->fd);

assert_hvf_ok(r);

/* handle VMEXIT */

- uint64_t exit_reason = rvmcs(cpu->hvf_fd, VMCS_EXIT_REASON);

- uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION);

- uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd,

+ uint64_t exit_reason = rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON);

+ uint64_t exit_qual = rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION);

+ uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf->fd,

VMCS_EXIT_INSTRUCTION_LENGTH);

- uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);

+ uint64_t idtvec_info = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO);

hvf_store_events(cpu, ins_len, idtvec_info);

- rip = rreg(cpu->hvf_fd, HV_X86_RIP);

- env->eflags = rreg(cpu->hvf_fd, HV_X86_RFLAGS);

+ rip = rreg(cpu->hvf->fd, HV_X86_RIP);

+ env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS);

qemu_mutex_lock_iothread();

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

case EXIT_REASON_EPT_FAULT:

{

hvf_slot *slot;

- uint64_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);

+ uint64_t gpa = rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRESS);

if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) &&

((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) {

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

store_regs(cpu);

break;

} else if (!string && !in) {

- RAX(env) = rreg(cpu->hvf_fd, HV_X86_RAX);

+ RAX(env) = rreg(cpu->hvf->fd, HV_X86_RAX);

hvf_handle_io(env, port, &RAX(env), 1, size, 1);

macvm_set_rip(cpu, rip + ins_len);

break;

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

break;

}

case EXIT_REASON_CPUID: {

- uint32_t rax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);

- uint32_t rbx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX);

- uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);

- uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);

+ uint32_t rax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX);

+ uint32_t rbx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX);

+ uint32_t rcx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX);

+ uint32_t rdx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX);

cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx);

- wreg(cpu->hvf_fd, HV_X86_RAX, rax);

- wreg(cpu->hvf_fd, HV_X86_RBX, rbx);

- wreg(cpu->hvf_fd, HV_X86_RCX, rcx);

- wreg(cpu->hvf_fd, HV_X86_RDX, rdx);

+ wreg(cpu->hvf->fd, HV_X86_RAX, rax);

+ wreg(cpu->hvf->fd, HV_X86_RBX, rbx);

+ wreg(cpu->hvf->fd, HV_X86_RCX, rcx);

+ wreg(cpu->hvf->fd, HV_X86_RDX, rdx);

macvm_set_rip(cpu, rip + ins_len);

break;

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

case EXIT_REASON_XSETBV: {

X86CPU *x86_cpu = X86_CPU(cpu);

CPUX86State *env = &x86_cpu->env;

- uint32_t eax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);

- uint32_t ecx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);

- uint32_t edx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);

+ uint32_t eax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX);

+ uint32_t ecx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX);

+ uint32_t edx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX);

if (ecx) {

macvm_set_rip(cpu, rip + ins_len);

break;

}

env->xcr0 = ((uint64_t)edx << 32) | eax;

- wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1);

+ wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1);

macvm_set_rip(cpu, rip + ins_len);

break;

}

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

switch (cr) {

case 0x0: {

- macvm_set_cr0(cpu->hvf_fd, RRX(env, reg));

+ macvm_set_cr0(cpu->hvf->fd, RRX(env, reg));

break;

}

case 4: {

- macvm_set_cr4(cpu->hvf_fd, RRX(env, reg));

+ macvm_set_cr4(cpu->hvf->fd, RRX(env, reg));

break;

}

case 8: {

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

break;

}

case EXIT_REASON_TASK_SWITCH: {

- uint64_t vinfo = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);

+ uint64_t vinfo = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO);

x68_segment_selector sel = {.sel = exit_qual & 0xffff};

vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,

vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo

@@ -XXX,XX +XXX,XX @@ int hvf_vcpu_exec(CPUState *cpu)

break;

}

case EXIT_REASON_RDPMC:

- wreg(cpu->hvf_fd, HV_X86_RAX, 0);

- wreg(cpu->hvf_fd, HV_X86_RDX, 0);

+ wreg(cpu->hvf->fd, HV_X86_RAX, 0);

+ wreg(cpu->hvf->fd, HV_X86_RDX, 0);

macvm_set_rip(cpu, rip + ins_len);

break;

case VMX_REASON_VMCALL:

diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/vmx.h

+++ b/target/i386/hvf/vmx.h

@@ -XXX,XX +XXX,XX @@

#include "vmcs.h"

#include "cpu.h"

#include "x86.h"

+#include "sysemu/hvf.h"

+#include "sysemu/hvf_int.h"

#include "exec/address-spaces.h"

@@ -XXX,XX +XXX,XX @@ static inline void macvm_set_rip(CPUState *cpu, uint64_t rip)

uint64_t val;

/* BUG, should take considering overlap.. */

- wreg(cpu->hvf_fd, HV_X86_RIP, rip);

+ wreg(cpu->hvf->fd, HV_X86_RIP, rip);

env->eip = rip;

/* after moving forward in rip, we need to clean INTERRUPTABILITY */

- val = rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);

+ val = rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);

if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING |

VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {

env->hflags &= ~HF_INHIBIT_IRQ_MASK;

- wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY,

+ wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY,

val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING |

VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));

}

@@ -XXX,XX +XXX,XX @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu)

CPUX86State *env = &x86_cpu->env;

env->hflags2 &= ~HF2_NMI_MASK;

- uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);

+ uint32_t gi = (uint32_t) rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);

gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;

- wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);

+ wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi);

}

static inline void vmx_set_nmi_blocking(CPUState *cpu)

@@ -XXX,XX +XXX,XX @@ static inline void vmx_set_nmi_blocking(CPUState *cpu)

CPUX86State *env = &x86_cpu->env;

env->hflags2 |= HF2_NMI_MASK;

- uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);

+ uint32_t gi = (uint32_t)rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY);

gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;

- wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);

+ wvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY, gi);

}

static inline void vmx_set_nmi_window_exiting(CPUState *cpu)

{

uint64_t val;

- val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);

- wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val |

+ val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);

+ wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val |

VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);

}

@@ -XXX,XX +XXX,XX @@ static inline void vmx_clear_nmi_window_exiting(CPUState *cpu)

{

uint64_t val;

- val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);

- wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val &

+ val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);

+ wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val &

~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);

}

diff --git a/target/i386/hvf/x86.c b/target/i386/hvf/x86.c

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/x86.c

+++ b/target/i386/hvf/x86.c

@@ -XXX,XX +XXX,XX @@ bool x86_read_segment_descriptor(struct CPUState *cpu,

}

if (GDT_SEL == sel.ti) {

- base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE);

- limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT);

+ base = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE);

+ limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT);

} else {

- base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE);

- limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT);

+ base = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE);

+ limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT);

}

if (sel.index * 8 >= limit) {

@@ -XXX,XX +XXX,XX @@ bool x86_write_segment_descriptor(struct CPUState *cpu,

uint32_t limit;

if (GDT_SEL == sel.ti) {

- base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE);

- limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT);

+ base = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_BASE);

+ limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_GDTR_LIMIT);

} else {

- base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE);

- limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT);

+ base = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_BASE);

+ limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_LDTR_LIMIT);

}

if (sel.index * 8 >= limit) {

@@ -XXX,XX +XXX,XX @@ bool x86_write_segment_descriptor(struct CPUState *cpu,

bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,

int gate)

{

- target_ulong base = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE);

- uint32_t limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT);

+ target_ulong base = rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_BASE);

+ uint32_t limit = rvmcs(cpu->hvf->fd, VMCS_GUEST_IDTR_LIMIT);

memset(idt_desc, 0, sizeof(*idt_desc));

if (gate * 8 >= limit) {

@@ -XXX,XX +XXX,XX @@ bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,

bool x86_is_protected(struct CPUState *cpu)

{

- uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);

+ uint64_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);

return cr0 & CR0_PE;

}

@@ -XXX,XX +XXX,XX @@ bool x86_is_v8086(struct CPUState *cpu)

bool x86_is_long_mode(struct CPUState *cpu)

{

- return rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA;

+ return rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER) & MSR_EFER_LMA;

}

bool x86_is_long64_mode(struct CPUState *cpu)

@@ -XXX,XX +XXX,XX @@ bool x86_is_long64_mode(struct CPUState *cpu)

bool x86_is_paging_mode(struct CPUState *cpu)

{

- uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);

+ uint64_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);

return cr0 & CR0_PG;

}

bool x86_is_pae_enabled(struct CPUState *cpu)

{

- uint64_t cr4 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4);

+ uint64_t cr4 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4);

return cr4 & CR4_PAE;

}

diff --git a/target/i386/hvf/x86_descr.c b/target/i386/hvf/x86_descr.c

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/x86_descr.c

+++ b/target/i386/hvf/x86_descr.c

@@ -XXX,XX +XXX,XX @@ static const struct vmx_segment_field {

uint32_t vmx_read_segment_limit(CPUState *cpu, X86Seg seg)

{

- return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit);

+ return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit);

}

uint32_t vmx_read_segment_ar(CPUState *cpu, X86Seg seg)

{

- return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes);

+ return (uint32_t)rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes);

}

uint64_t vmx_read_segment_base(CPUState *cpu, X86Seg seg)

{

- return rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base);

+ return rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base);

}

x68_segment_selector vmx_read_segment_selector(CPUState *cpu, X86Seg seg)

{

x68_segment_selector sel;

- sel.sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector);

+ sel.sel = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector);

return sel;

}

void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, X86Seg seg)

{

- wvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector, selector.sel);

+ wvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector, selector.sel);

}

void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, X86Seg seg)

{

- desc->sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector);

- desc->base = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base);

- desc->limit = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit);

- desc->ar = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes);

+ desc->sel = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].selector);

+ desc->base = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].base);

+ desc->limit = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].limit);

+ desc->ar = rvmcs(cpu->hvf->fd, vmx_segment_fields[seg].ar_bytes);

}

void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, X86Seg seg)

{

const struct vmx_segment_field *sf = &vmx_segment_fields[seg];

- wvmcs(cpu->hvf_fd, sf->base, desc->base);

- wvmcs(cpu->hvf_fd, sf->limit, desc->limit);

- wvmcs(cpu->hvf_fd, sf->selector, desc->sel);

- wvmcs(cpu->hvf_fd, sf->ar_bytes, desc->ar);

+ wvmcs(cpu->hvf->fd, sf->base, desc->base);

+ wvmcs(cpu->hvf->fd, sf->limit, desc->limit);

+ wvmcs(cpu->hvf->fd, sf->selector, desc->sel);

+ wvmcs(cpu->hvf->fd, sf->ar_bytes, desc->ar);

}

void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc)

diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/x86_emu.c

+++ b/target/i386/hvf/x86_emu.c

@@ -XXX,XX +XXX,XX @@ void simulate_rdmsr(struct CPUState *cpu)

switch (msr) {

case MSR_IA32_TSC:

- val = rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET);

+ val = rdtscp() + rvmcs(cpu->hvf->fd, VMCS_TSC_OFFSET);

break;

case MSR_IA32_APICBASE:

val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);

@@ -XXX,XX +XXX,XX @@ void simulate_rdmsr(struct CPUState *cpu)

val = x86_cpu->ucode_rev;

break;

case MSR_EFER:

- val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);

+ val = rvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER);

break;

case MSR_FSBASE:

- val = rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE);

+ val = rvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE);

break;

case MSR_GSBASE:

- val = rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE);

+ val = rvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE);

break;

case MSR_KERNELGSBASE:

- val = rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE);

+ val = rvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE);

break;

case MSR_STAR:

abort();

@@ -XXX,XX +XXX,XX @@ void simulate_wrmsr(struct CPUState *cpu)

cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);

break;

case MSR_FSBASE:

- wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data);

+ wvmcs(cpu->hvf->fd, VMCS_GUEST_FS_BASE, data);

break;

case MSR_GSBASE:

- wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data);

+ wvmcs(cpu->hvf->fd, VMCS_GUEST_GS_BASE, data);

break;

case MSR_KERNELGSBASE:

- wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data);

+ wvmcs(cpu->hvf->fd, VMCS_HOST_FS_BASE, data);

break;

case MSR_STAR:

abort();

@@ -XXX,XX +XXX,XX @@ void simulate_wrmsr(struct CPUState *cpu)

break;

case MSR_EFER:

/*printf("new efer %llx\n", EFER(cpu));*/

- wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data);

+ wvmcs(cpu->hvf->fd, VMCS_GUEST_IA32_EFER, data);

if (data & MSR_EFER_NXE) {

- hv_vcpu_invalidate_tlb(cpu->hvf_fd);

+ hv_vcpu_invalidate_tlb(cpu->hvf->fd);

}

break;

case MSR_MTRRphysBase(0):

@@ -XXX,XX +XXX,XX @@ void load_regs(struct CPUState *cpu)

CPUX86State *env = &x86_cpu->env;

int i = 0;

- RRX(env, R_EAX) = rreg(cpu->hvf_fd, HV_X86_RAX);

- RRX(env, R_EBX) = rreg(cpu->hvf_fd, HV_X86_RBX);

- RRX(env, R_ECX) = rreg(cpu->hvf_fd, HV_X86_RCX);

- RRX(env, R_EDX) = rreg(cpu->hvf_fd, HV_X86_RDX);

- RRX(env, R_ESI) = rreg(cpu->hvf_fd, HV_X86_RSI);

- RRX(env, R_EDI) = rreg(cpu->hvf_fd, HV_X86_RDI);

- RRX(env, R_ESP) = rreg(cpu->hvf_fd, HV_X86_RSP);

- RRX(env, R_EBP) = rreg(cpu->hvf_fd, HV_X86_RBP);

+ RRX(env, R_EAX) = rreg(cpu->hvf->fd, HV_X86_RAX);

+ RRX(env, R_EBX) = rreg(cpu->hvf->fd, HV_X86_RBX);

+ RRX(env, R_ECX) = rreg(cpu->hvf->fd, HV_X86_RCX);

+ RRX(env, R_EDX) = rreg(cpu->hvf->fd, HV_X86_RDX);

+ RRX(env, R_ESI) = rreg(cpu->hvf->fd, HV_X86_RSI);

+ RRX(env, R_EDI) = rreg(cpu->hvf->fd, HV_X86_RDI);

+ RRX(env, R_ESP) = rreg(cpu->hvf->fd, HV_X86_RSP);

+ RRX(env, R_EBP) = rreg(cpu->hvf->fd, HV_X86_RBP);

for (i = 8; i < 16; i++) {

- RRX(env, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i);

+ RRX(env, i) = rreg(cpu->hvf->fd, HV_X86_RAX + i);

}

- env->eflags = rreg(cpu->hvf_fd, HV_X86_RFLAGS);

+ env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS);

rflags_to_lflags(env);

- env->eip = rreg(cpu->hvf_fd, HV_X86_RIP);

+ env->eip = rreg(cpu->hvf->fd, HV_X86_RIP);

}

void store_regs(struct CPUState *cpu)

@@ -XXX,XX +XXX,XX @@ void store_regs(struct CPUState *cpu)

CPUX86State *env = &x86_cpu->env;

int i = 0;

- wreg(cpu->hvf_fd, HV_X86_RAX, RAX(env));

- wreg(cpu->hvf_fd, HV_X86_RBX, RBX(env));

- wreg(cpu->hvf_fd, HV_X86_RCX, RCX(env));

- wreg(cpu->hvf_fd, HV_X86_RDX, RDX(env));

- wreg(cpu->hvf_fd, HV_X86_RSI, RSI(env));

- wreg(cpu->hvf_fd, HV_X86_RDI, RDI(env));

- wreg(cpu->hvf_fd, HV_X86_RBP, RBP(env));

- wreg(cpu->hvf_fd, HV_X86_RSP, RSP(env));

+ wreg(cpu->hvf->fd, HV_X86_RAX, RAX(env));

+ wreg(cpu->hvf->fd, HV_X86_RBX, RBX(env));

+ wreg(cpu->hvf->fd, HV_X86_RCX, RCX(env));

+ wreg(cpu->hvf->fd, HV_X86_RDX, RDX(env));

+ wreg(cpu->hvf->fd, HV_X86_RSI, RSI(env));

+ wreg(cpu->hvf->fd, HV_X86_RDI, RDI(env));

+ wreg(cpu->hvf->fd, HV_X86_RBP, RBP(env));

+ wreg(cpu->hvf->fd, HV_X86_RSP, RSP(env));

for (i = 8; i < 16; i++) {

- wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(env, i));

+ wreg(cpu->hvf->fd, HV_X86_RAX + i, RRX(env, i));

}

lflags_to_rflags(env);

- wreg(cpu->hvf_fd, HV_X86_RFLAGS, env->eflags);

+ wreg(cpu->hvf->fd, HV_X86_RFLAGS, env->eflags);

macvm_set_rip(cpu, env->eip);

}

diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/x86_mmu.c

+++ b/target/i386/hvf/x86_mmu.c

@@ -XXX,XX +XXX,XX @@ static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,

pt->err_code |= MMU_PAGE_PT;

}

- uint32_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);

+ uint32_t cr0 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0);

/* check protection */

if (cr0 & CR0_WP) {

if (pt->write_access && !pte_write_access(pte)) {

@@ -XXX,XX +XXX,XX @@ static bool walk_gpt(struct CPUState *cpu, target_ulong addr, int err_code,

{

int top_level, level;

bool is_large = false;

- target_ulong cr3 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR3);

+ target_ulong cr3 = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR3);

uint64_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;

memset(pt, 0, sizeof(*pt));

diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/x86_task.c

+++ b/target/i386/hvf/x86_task.c

@@ -XXX,XX +XXX,XX @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)

X86CPU *x86_cpu = X86_CPU(cpu);

CPUX86State *env = &x86_cpu->env;

- wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3);

+ wvmcs(cpu->hvf->fd, VMCS_GUEST_CR3, tss->cr3);

env->eip = tss->eip;

env->eflags = tss->eflags | 2;

@@ -XXX,XX +XXX,XX @@ static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segme

void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)

{

- uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP);

+ uint64_t rip = rreg(cpu->hvf->fd, HV_X86_RIP);

if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&

gate_type != VMCS_INTR_T_HWINTR &&

gate_type != VMCS_INTR_T_NMI)) {

- int ins_len = rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);

+ int ins_len = rvmcs(cpu->hvf->fd, VMCS_EXIT_INSTRUCTION_LENGTH);

macvm_set_rip(cpu, rip + ins_len);

return;

}

@@ -XXX,XX +XXX,XX @@ void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int rea

//ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);

VM_PANIC("task_switch_16");

- macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS);

+ macvm_set_cr0(cpu->hvf->fd, rvmcs(cpu->hvf->fd, VMCS_GUEST_CR0) | CR0_TS);

x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);

vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR);

store_regs(cpu);

- hv_vcpu_invalidate_tlb(cpu->hvf_fd);

- hv_vcpu_flush(cpu->hvf_fd);

+ hv_vcpu_invalidate_tlb(cpu->hvf->fd);

+ hv_vcpu_flush(cpu->hvf->fd);

}

diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c

index XXXXXXX..XXXXXXX 100644

--- a/target/i386/hvf/x86hvf.c

+++ b/target/i386/hvf/x86hvf.c

@@ -XXX,XX +XXX,XX @@ void hvf_put_xsave(CPUState *cpu_state)

x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave);

- if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, (void*)xsave, 4096)) {

+ if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, (void*)xsave, 4096)) {

abort();

}

}

@@ -XXX,XX +XXX,XX @@ void hvf_put_segments(CPUState *cpu_state)

CPUX86State *env = &X86_CPU(cpu_state)->env;

struct vmx_segment seg;

- wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);

- wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE, env->idt.base);

+ wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);

+ wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base);

- wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);

- wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);

+ wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);

+ wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);

- /* wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]); */

- wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3, env->cr[3]);

+ /* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */

+ wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]);

vmx_update_tpr(cpu_state);

- wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER, env->efer);

+ wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer);

- macvm_set_cr4(cpu_state->hvf_fd, env->cr[4]);

- macvm_set_cr0(cpu_state->hvf_fd, env->cr[0]);

+ macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]);

+ macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]);

hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false);

vmx_write_segment_descriptor(cpu_state, &seg, R_CS);

@@ -XXX,XX +XXX,XX @@ void hvf_put_segments(CPUState *cpu_state)

hvf_set_segment(cpu_state, &seg, &env->ldt, false);

vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR);

- hv_vcpu_flush(cpu_state->hvf_fd);

+ hv_vcpu_flush(cpu_state->hvf->fd);

}

void hvf_put_msrs(CPUState *cpu_state)

{

CPUX86State *env = &X86_CPU(cpu_state)->env;

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS,

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS,

env->sysenter_cs);

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP,

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP,

env->sysenter_esp);

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP,

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP,

env->sysenter_eip);

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_STAR, env->star);

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star);

#ifdef TARGET_X86_64

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_CSTAR, env->cstar);

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, env->kernelgsbase);

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FMASK, env->fmask);

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_LSTAR, env->lstar);

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar);

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase);

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask);

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar);

#endif

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base);

- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base);

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base);

+ hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base);

}

@@ -XXX,XX +XXX,XX @@ void hvf_get_xsave(CPUState *cpu_state)

xsave = X86_CPU(cpu_state)->env.xsave_buf;

- if (hv_vcpu_read_fpstate(cpu_state->hvf_fd, (void*)xsave, 4096)) {

+ if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, (void*)xsave, 4096)) {

abort();

}

@@ -XXX,XX +XXX,XX @@ void hvf_get_segments(CPUState *cpu_state)

vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR);

hvf_get_segment(&env->ldt, &seg);

- env->idt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT);

- env->idt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE);

- env->gdt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT);

- env->gdt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE);

+ env->idt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT);

+ env->idt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE);

+ env->gdt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT);

+ env->gdt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE);

- env->cr[0] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR0);

+ env->cr[0] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0);

env->cr[2] = 0;

- env->cr[3] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3);

- env->cr[4] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR4);

+ env->cr[3] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3);

+ env->cr[4] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4);

- env->efer = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER);

+ env->efer = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER);

}

void hvf_get_msrs(CPUState *cpu_state)

@@ -XXX,XX +XXX,XX @@ void hvf_get_msrs(CPUState *cpu_state)

CPUX86State *env = &X86_CPU(cpu_state)->env;

uint64_t tmp;

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, &tmp);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp);

env->sysenter_cs = tmp;

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, &tmp);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp);

env->sysenter_esp = tmp;

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, &tmp);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp);

env->sysenter_eip = tmp;

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_STAR, &env->star);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star);

#ifdef TARGET_X86_64

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_CSTAR, &env->cstar);

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, &env->kernelgsbase);

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_FMASK, &env->fmask);

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_LSTAR, &env->lstar);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar);

#endif

- hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_APICBASE, &tmp);

+ hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp);

- env->tsc = rdtscp() + rvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET);

+ env->tsc = rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET);

}

int hvf_put_registers(CPUState *cpu_state)

@@ -XXX,XX +XXX,XX @@ int hvf_put_registers(CPUState *cpu_state)

X86CPU *x86cpu = X86_CPU(cpu_state);

CPUX86State *env = &x86cpu->env;

- wreg(cpu_state->hvf_fd, HV_X86_RAX, env->regs[R_EAX]);

- wreg(cpu_state->hvf_fd, HV_X86_RBX, env->regs[R_EBX]);

- wreg(cpu_state->hvf_fd, HV_X86_RCX, env->regs[R_ECX]);

- wreg(cpu_state->hvf_fd, HV_X86_RDX, env->regs[R_EDX]);

- wreg(cpu_state->hvf_fd, HV_X86_RBP, env->regs[R_EBP]);

- wreg(cpu_state->hvf_fd, HV_X86_RSP, env->regs[R_ESP]);

- wreg(cpu_state->hvf_fd, HV_X86_RSI, env->regs[R_ESI]);

- wreg(cpu_state->hvf_fd, HV_X86_RDI, env->regs[R_EDI]);

- wreg(cpu_state->hvf_fd, HV_X86_R8, env->regs[8]);

- wreg(cpu_state->hvf_fd, HV_X86_R9, env->regs[9]);

- wreg(cpu_state->hvf_fd, HV_X86_R10, env->regs[10]);

- wreg(cpu_state->hvf_fd, HV_X86_R11, env->regs[11]);

- wreg(cpu_state->hvf_fd, HV_X86_R12, env->regs[12]);