1 | Arm queue; bugfixes only. | 1 | Hi; here's a relatively small target-arm queue, pretty much all |
---|---|---|---|
2 | bug fixes. (There are a few non-arm patches that I've thrown in | ||
3 | there too for my convenience :-)) | ||
2 | 4 | ||
3 | thanks | 5 | thanks |
4 | -- PMM | 6 | -- PMM |
5 | 7 | ||
6 | The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739: | 8 | The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1: |
7 | 9 | ||
8 | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000) | 10 | Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into staging (2023-05-11 11:44:23 +0100) |
9 | 11 | ||
10 | are available in the Git repository at: | 12 | are available in the Git repository at: |
11 | 13 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230512 |
13 | 15 | ||
14 | for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42: | 16 | for you to fetch changes up to 478dccbb99db0bf8f00537dd0b4d0de88d5cb537: |
15 | 17 | ||
16 | tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000) | 18 | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check (2023-05-12 16:01:25 +0100) |
17 | 19 | ||
18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
19 | target-arm queue: | 21 | target-arm queue: |
20 | * hw/arm/virt: ARM_VIRT must select ARM_GIC | 22 | * More refactoring of files into tcg/ |
21 | * exynos: Fix bad printf format specifiers | 23 | * Don't allow stage 2 page table walks to downgrade to NS |
22 | * hw/input/ps2.c: Remove remnants of printf debug | 24 | * Fix handling of SW and NSW bits for stage 2 walks |
23 | * target/openrisc: Remove dead code attempting to check "is timer disabled" | 25 | * MAINTAINERS: Update Akihiko Odaki's email address |
24 | * register: Remove unnecessary NULL check | 26 | * ui: Fix pixel colour channel order for PNG screenshots |
25 | * util/cutils: Fix Coverity array overrun in freq_to_str() | 27 | * docs: Remove unused weirdly-named cross-reference targets |
26 | * configure: Make "does libgio work" test pull in some actual functions | 28 | * hw/mips/malta: Fix minor dead code issue |
27 | * tmp105: reset the T_low and T_High registers | 29 | * Fixes for the "allow CONFIG_TCG=n" changes |
28 | * tmp105: Correct handling of temperature limit checks | 30 | * tests/qtest: Don't run cdrom boot tests if no accelerator is present |
31 | * target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check | ||
29 | 32 | ||
30 | ---------------------------------------------------------------- | 33 | ---------------------------------------------------------------- |
31 | Alex Chen (1): | 34 | Akihiko Odaki (1): |
32 | exynos: Fix bad printf format specifiers | 35 | MAINTAINERS: Update Akihiko Odaki's email address |
33 | 36 | ||
34 | Alistair Francis (1): | 37 | Fabiano Rosas (3): |
35 | register: Remove unnecessary NULL check | 38 | target/arm: Select SEMIHOSTING when using TCG |
39 | target/arm: Select CONFIG_ARM_V7M when TCG is enabled | ||
40 | tests/qtest: Don't run cdrom boot tests if no accelerator is present | ||
36 | 41 | ||
37 | Andrew Jones (1): | 42 | Peter Maydell (6): |
38 | hw/arm/virt: ARM_VIRT must select ARM_GIC | 43 | target/arm: Don't allow stage 2 page table walks to downgrade to NS |
44 | target/arm: Fix handling of SW and NSW bits for stage 2 walks | ||
45 | ui: Fix pixel colour channel order for PNG screenshots | ||
46 | docs: Remove unused weirdly-named cross-reference targets | ||
47 | hw/mips/malta: Fix minor dead code issue | ||
48 | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check | ||
39 | 49 | ||
40 | Peter Maydell (5): | 50 | Richard Henderson (2): |
41 | hw/input/ps2.c: Remove remnants of printf debug | 51 | target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ |
42 | target/openrisc: Remove dead code attempting to check "is timer disabled" | 52 | target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ |
43 | configure: Make "does libgio work" test pull in some actual functions | ||
44 | hw/misc/tmp105: reset the T_low and T_High registers | ||
45 | tmp105: Correct handling of temperature limit checks | ||
46 | 53 | ||
47 | Philippe Mathieu-Daudé (1): | 54 | MAINTAINERS | 4 +- |
48 | util/cutils: Fix Coverity array overrun in freq_to_str() | 55 | docs/system/devices/igb.rst | 2 +- |
49 | 56 | docs/system/devices/ivshmem.rst | 2 - | |
50 | configure | 11 +++++-- | 57 | docs/system/devices/net.rst | 2 +- |
51 | hw/misc/tmp105.h | 7 +++++ | 58 | docs/system/devices/usb.rst | 2 - |
52 | hw/core/register.c | 4 --- | 59 | docs/system/keys.rst | 2 +- |
53 | hw/input/ps2.c | 9 ------ | 60 | docs/system/linuxboot.rst | 2 +- |
54 | hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------ | 61 | docs/system/target-i386.rst | 4 -- |
55 | hw/timer/exynos4210_mct.c | 4 +-- | 62 | target/arm/helper.h | 8 +-- |
56 | hw/timer/exynos4210_pwm.c | 8 ++--- | 63 | target/arm/internals.h | 12 +++- |
57 | target/openrisc/sys_helper.c | 3 -- | 64 | target/arm/{ => tcg}/arm_ldst.h | 0 |
58 | util/cutils.c | 3 +- | 65 | target/arm/{ => tcg}/helper-a64.h | 0 |
59 | hw/arm/Kconfig | 1 + | 66 | target/arm/{ => tcg}/helper-mve.h | 0 |
60 | 10 files changed, 89 insertions(+), 34 deletions(-) | 67 | target/arm/{ => tcg}/helper-sme.h | 0 |
61 | 68 | target/arm/{ => tcg}/helper-sve.h | 0 | |
69 | target/arm/{ => tcg}/sve_ldst_internal.h | 0 | ||
70 | target/arm/{ => tcg}/translate-a32.h | 0 | ||
71 | hw/mips/malta.c | 5 +- | ||
72 | target/arm/gdbstub64.c | 2 +- | ||
73 | target/arm/helper.c | 15 ++++- | ||
74 | target/arm/ptw.c | 95 +++++++++++++++++++------------- | ||
75 | target/arm/tcg/pauth_helper.c | 6 +- | ||
76 | tests/qtest/cdrom-test.c | 10 ++++ | ||
77 | ui/console.c | 4 +- | ||
78 | target/arm/Kconfig | 9 +-- | ||
79 | 25 files changed, 109 insertions(+), 77 deletions(-) | ||
80 | rename target/arm/{ => tcg}/arm_ldst.h (100%) | ||
81 | rename target/arm/{ => tcg}/helper-a64.h (100%) | ||
82 | rename target/arm/{ => tcg}/helper-mve.h (100%) | ||
83 | rename target/arm/{ => tcg}/helper-sme.h (100%) | ||
84 | rename target/arm/{ => tcg}/helper-sve.h (100%) | ||
85 | rename target/arm/{ => tcg}/sve_ldst_internal.h (100%) | ||
86 | rename target/arm/{ => tcg}/translate-a32.h (100%) | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN): | 3 | These files got missed when populating tcg/. |
4 | Because they are included with "", no change to the users required. | ||
4 | 5 | ||
5 | >>> Overrunning array "suffixes" of 7 8-byte elements at element | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | index 7 (byte offset 63) using index "idx" (which evaluates to 7). | 7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
7 | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | |
8 | Note, the biggest input value freq_to_str() can accept is UINT64_MAX, | 9 | Message-id: 20230504110412.1892411-2-richard.henderson@linaro.org |
9 | which is ~18.446 EHz, less than 1000 EHz. | ||
10 | |||
11 | Reported-by: Eduardo Habkost <ehabkost@redhat.com> | ||
12 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> | ||
15 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
16 | Message-id: 20201101215755.2021421-1-f4bug@amsat.org | ||
17 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | --- | 11 | --- |
21 | util/cutils.c | 3 ++- | 12 | target/arm/{ => tcg}/arm_ldst.h | 0 |
22 | 1 file changed, 2 insertions(+), 1 deletion(-) | 13 | target/arm/{ => tcg}/sve_ldst_internal.h | 0 |
14 | target/arm/{ => tcg}/translate-a32.h | 0 | ||
15 | 3 files changed, 0 insertions(+), 0 deletions(-) | ||
16 | rename target/arm/{ => tcg}/arm_ldst.h (100%) | ||
17 | rename target/arm/{ => tcg}/sve_ldst_internal.h (100%) | ||
18 | rename target/arm/{ => tcg}/translate-a32.h (100%) | ||
23 | 19 | ||
24 | diff --git a/util/cutils.c b/util/cutils.c | 20 | diff --git a/target/arm/arm_ldst.h b/target/arm/tcg/arm_ldst.h |
25 | index XXXXXXX..XXXXXXX 100644 | 21 | similarity index 100% |
26 | --- a/util/cutils.c | 22 | rename from target/arm/arm_ldst.h |
27 | +++ b/util/cutils.c | 23 | rename to target/arm/tcg/arm_ldst.h |
28 | @@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz) | 24 | diff --git a/target/arm/sve_ldst_internal.h b/target/arm/tcg/sve_ldst_internal.h |
29 | double freq = freq_hz; | 25 | similarity index 100% |
30 | size_t idx = 0; | 26 | rename from target/arm/sve_ldst_internal.h |
31 | 27 | rename to target/arm/tcg/sve_ldst_internal.h | |
32 | - while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) { | 28 | diff --git a/target/arm/translate-a32.h b/target/arm/tcg/translate-a32.h |
33 | + while (freq >= 1000.0) { | 29 | similarity index 100% |
34 | freq /= 1000.0; | 30 | rename from target/arm/translate-a32.h |
35 | idx++; | 31 | rename to target/arm/tcg/translate-a32.h |
36 | } | ||
37 | + assert(idx < ARRAY_SIZE(suffixes)); | ||
38 | |||
39 | return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]); | ||
40 | } | ||
41 | -- | 32 | -- |
42 | 2.20.1 | 33 | 2.34.1 |
43 | 34 | ||
44 | 35 | diff view generated by jsdifflib |
1 | From: Alex Chen <alex.chen@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We should use printf format specifier "%u" instead of "%d" for | 3 | While we cannot move the main "helper.h" out of target/arm/, |
4 | argument of type "unsigned int". | 4 | due to usage by generic code, we can move the sub-includes. |
5 | 5 | ||
6 | Reported-by: Euler Robot <euler.robot@huawei.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | 7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
8 | Message-id: 20201111073651.72804-1-alex.chen@huawei.com | 8 | Message-id: 20230504110412.1892411-3-richard.henderson@linaro.org |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | hw/timer/exynos4210_mct.c | 4 ++-- | 12 | target/arm/helper.h | 8 ++++---- |
13 | hw/timer/exynos4210_pwm.c | 8 ++++---- | 13 | target/arm/{ => tcg}/helper-a64.h | 0 |
14 | 2 files changed, 6 insertions(+), 6 deletions(-) | 14 | target/arm/{ => tcg}/helper-mve.h | 0 |
15 | target/arm/{ => tcg}/helper-sme.h | 0 | ||
16 | target/arm/{ => tcg}/helper-sve.h | 0 | ||
17 | 5 files changed, 4 insertions(+), 4 deletions(-) | ||
18 | rename target/arm/{ => tcg}/helper-a64.h (100%) | ||
19 | rename target/arm/{ => tcg}/helper-mve.h (100%) | ||
20 | rename target/arm/{ => tcg}/helper-sme.h (100%) | ||
21 | rename target/arm/{ => tcg}/helper-sve.h (100%) | ||
15 | 22 | ||
16 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 23 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
17 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/timer/exynos4210_mct.c | 25 | --- a/target/arm/helper.h |
19 | +++ b/hw/timer/exynos4210_mct.c | 26 | +++ b/target/arm/helper.h |
20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id) | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, |
21 | /* If CSTAT is pending and IRQ is enabled */ | 28 | void, ptr, ptr, ptr, ptr, i32) |
22 | if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) && | 29 | |
23 | (s->reg.int_enb & G_INT_ENABLE(id))) { | 30 | #ifdef TARGET_AARCH64 |
24 | - DPRINTF("gcmp timer[%d] IRQ\n", id); | 31 | -#include "helper-a64.h" |
25 | + DPRINTF("gcmp timer[%u] IRQ\n", id); | 32 | -#include "helper-sve.h" |
26 | qemu_irq_raise(s->irq[id]); | 33 | -#include "helper-sme.h" |
27 | } | 34 | +#include "tcg/helper-a64.h" |
28 | } | 35 | +#include "tcg/helper-sve.h" |
29 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | 36 | +#include "tcg/helper-sme.h" |
30 | MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); | 37 | #endif |
31 | 38 | ||
32 | if (freq != s->freq) { | 39 | -#include "helper-mve.h" |
33 | - DPRINTF("freq=%dHz\n", s->freq); | 40 | +#include "tcg/helper-mve.h" |
34 | + DPRINTF("freq=%uHz\n", s->freq); | 41 | diff --git a/target/arm/helper-a64.h b/target/arm/tcg/helper-a64.h |
35 | 42 | similarity index 100% | |
36 | /* global timer */ | 43 | rename from target/arm/helper-a64.h |
37 | tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | 44 | rename to target/arm/tcg/helper-a64.h |
38 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | 45 | diff --git a/target/arm/helper-mve.h b/target/arm/tcg/helper-mve.h |
39 | index XXXXXXX..XXXXXXX 100644 | 46 | similarity index 100% |
40 | --- a/hw/timer/exynos4210_pwm.c | 47 | rename from target/arm/helper-mve.h |
41 | +++ b/hw/timer/exynos4210_pwm.c | 48 | rename to target/arm/tcg/helper-mve.h |
42 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) | 49 | diff --git a/target/arm/helper-sme.h b/target/arm/tcg/helper-sme.h |
43 | 50 | similarity index 100% | |
44 | if (freq != s->timer[id].freq) { | 51 | rename from target/arm/helper-sme.h |
45 | ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); | 52 | rename to target/arm/tcg/helper-sme.h |
46 | - DPRINTF("freq=%dHz\n", s->timer[id].freq); | 53 | diff --git a/target/arm/helper-sve.h b/target/arm/tcg/helper-sve.h |
47 | + DPRINTF("freq=%uHz\n", s->timer[id].freq); | 54 | similarity index 100% |
48 | } | 55 | rename from target/arm/helper-sve.h |
49 | } | 56 | rename to target/arm/tcg/helper-sve.h |
50 | |||
51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) | ||
52 | uint32_t id = s->id; | ||
53 | bool cmp; | ||
54 | |||
55 | - DPRINTF("timer %d tick\n", id); | ||
56 | + DPRINTF("timer %u tick\n", id); | ||
57 | |||
58 | /* set irq status */ | ||
59 | p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); | ||
60 | |||
61 | /* raise IRQ */ | ||
62 | if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { | ||
63 | - DPRINTF("timer %d IRQ\n", id); | ||
64 | + DPRINTF("timer %u IRQ\n", id); | ||
65 | qemu_irq_raise(p->timer[id].irq); | ||
66 | } | ||
67 | |||
68 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) | ||
69 | } | ||
70 | |||
71 | if (cmp) { | ||
72 | - DPRINTF("auto reload timer %d count to %x\n", id, | ||
73 | + DPRINTF("auto reload timer %u count to %x\n", id, | ||
74 | p->timer[id].reg_tcntb); | ||
75 | ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); | ||
76 | ptimer_run(p->timer[id].ptimer, 1); | ||
77 | -- | 57 | -- |
78 | 2.20.1 | 58 | 2.34.1 |
79 | 59 | ||
80 | 60 | diff view generated by jsdifflib |
1 | In commit 76346b6264a9b01979 we tried to add a configure check that | 1 | Bit 63 in a Table descriptor is only the NSTable bit for stage 1 |
---|---|---|---|
2 | the libgio pkg-config data was correct, which builds an executable | 2 | translations; in stage 2 it is RES0. We were incorrectly looking at |
3 | linked against it. Unfortunately this doesn't catch the problem | 3 | it all the time. |
4 | (missing static library dependency info), because a "do nothing" test | ||
5 | source file doesn't have any symbol references that cause the linker | ||
6 | to pull in .o files from libgio.a, and so we don't see the "missing | ||
7 | symbols from libmount" error that a full QEMU link triggers. | ||
8 | 4 | ||
9 | (The ineffective test went unnoticed because of a typo that | 5 | This causes problems if: |
10 | effectively disabled libgio unconditionally, but after commit | 6 | * the stage 2 table descriptor was incorrectly setting the RES0 bit |
11 | 3569a5dfc11f2 fixed that, a static link of the system emulator on | 7 | * we are doing a stage 2 translation in Secure address space for |
12 | Ubuntu stopped working again.) | 8 | a NonSecure stage 1 regime -- in this case we would incorrectly |
9 | do an immediate downgrade to NonSecure | ||
13 | 10 | ||
14 | Improve the gio test by having the test source fragment reference a | 11 | A bug elsewhere in the code currently prevents us from getting |
15 | g_dbus function (which is what is indirectly causing us to end up | 12 | to the second situation, but when we fix that it will be possible. |
16 | wanting functions from libmount). | ||
17 | 13 | ||
14 | Cc: qemu-stable@nongnu.org | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
20 | Message-id: 20201116104617.18333-1-peter.maydell@linaro.org | 17 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
18 | Message-id: 20230504135425.2748672-2-peter.maydell@linaro.org | ||
21 | --- | 19 | --- |
22 | configure | 11 +++++++++-- | 20 | target/arm/ptw.c | 5 +++-- |
23 | 1 file changed, 9 insertions(+), 2 deletions(-) | 21 | 1 file changed, 3 insertions(+), 2 deletions(-) |
24 | 22 | ||
25 | diff --git a/configure b/configure | 23 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
26 | index XXXXXXX..XXXXXXX 100755 | 24 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/configure | 25 | --- a/target/arm/ptw.c |
28 | +++ b/configure | 26 | +++ b/target/arm/ptw.c |
29 | @@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then | 27 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
30 | # Check that the libraries actually work -- Ubuntu 18.04 ships | 28 | descaddrmask &= ~indexmask_grainsize; |
31 | # with pkg-config --static --libs data for gio-2.0 that is missing | 29 | |
32 | # -lblkid and will give a link error. | 30 | /* |
33 | - write_c_skeleton | 31 | - * Secure accesses start with the page table in secure memory and |
34 | - if compile_prog "" "$gio_libs" ; then | 32 | + * Secure stage 1 accesses start with the page table in secure memory and |
35 | + cat > $TMPC <<EOF | 33 | * can be downgraded to non-secure at any step. Non-secure accesses |
36 | +#include <gio/gio.h> | 34 | * remain non-secure. We implement this by just ORing in the NSTable/NS |
37 | +int main(void) | 35 | * bits at each step. |
38 | +{ | 36 | + * Stage 2 never gets this kind of downgrade. |
39 | + g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0); | 37 | */ |
40 | + return 0; | 38 | tableattrs = is_secure ? 0 : (1 << 4); |
41 | +} | 39 | |
42 | +EOF | 40 | next_level: |
43 | + if compile_prog "$gio_cflags" "$gio_libs" ; then | 41 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
44 | gio=yes | 42 | descaddr &= ~7ULL; |
45 | else | 43 | - nstable = extract32(tableattrs, 4, 1); |
46 | gio=no | 44 | + nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); |
45 | if (nstable) { | ||
46 | /* | ||
47 | * Stage2_S -> Stage2 or Phys_S -> Phys_NS | ||
47 | -- | 48 | -- |
48 | 2.20.1 | 49 | 2.34.1 |
49 | 50 | ||
50 | 51 | diff view generated by jsdifflib |
1 | The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device | 1 | We currently don't correctly handle the VSTCR_EL2.SW and VTCR_EL2.NSW |
---|---|---|---|
2 | signals an alert when the temperature equals or exceeds the T_high value and | 2 | configuration bits. These allow configuration of whether the stage 2 |
3 | then remains high until a device register is read or the device responds to | 3 | page table walks for Secure IPA and NonSecure IPA should do their |
4 | the SMBUS Alert Response address, or the device is put into Shutdown Mode. | 4 | descriptor reads from Secure or NonSecure physical addresses. (This |
5 | Thereafter the Alert pin will only be re-signalled when temperature falls | 5 | is separate from how the translation table base address and other |
6 | below T_low; alert can then be cleared in the same set of ways, and the | 6 | parameters are set: an NS IPA always uses VTTBR_EL2 and VTCR_EL2 |
7 | device returns to its initial "alert when temperature goes above T_high" | 7 | for its base address and walk parameters, regardless of the NSW bit, |
8 | mode. (If this textual description is confusing, see figure 3 in the | 8 | and similarly for Secure.) |
9 | TI datasheet at https://www.ti.com/lit/gpn/tmp105 .) | ||
10 | 9 | ||
11 | We were misimplementing this as a simple "always alert if temperature is | 10 | Provide a new function ptw_idx_for_stage_2() which returns the |
12 | above T_high or below T_low" condition, which gives a spurious alert on | 11 | MMU index to use for descriptor reads, and use it to set up |
13 | startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset | 12 | the .in_ptw_idx wherever we call get_phys_addr_lpae(). |
14 | limit values. | ||
15 | 13 | ||
16 | Implement the correct (hysteresis) behaviour by tracking whether we | 14 | For a stage 2 walk, wherever we call get_phys_addr_lpae(): |
17 | are currently looking for the temperature to rise over T_high or | 15 | * .in_ptw_idx should be ptw_idx_for_stage_2() of the .in_mmu_idx |
18 | for it to fall below T_low. Our implementation of the comparator | 16 | * .in_secure should be true if .in_mmu_idx is Stage2_S |
19 | mode (TM==0) wasn't wrong, but rephrase it to match the way that | ||
20 | interrupt mode is now handled for clarity. | ||
21 | 17 | ||
18 | This allows us to correct S1_ptw_translate() so that it consistently | ||
19 | always sets its (out_secure, out_phys) to the result it gets from the | ||
20 | S2 walk (either by calling get_phys_addr_lpae() or by TLB lookup). | ||
21 | This makes better conceptual sense because the S2 walk should return | ||
22 | us an (address space, address) tuple, not an address that we then | ||
23 | randomly assign to S or NS. | ||
24 | |||
25 | Our previous handling of SW and NSW was broken, so guest code | ||
26 | trying to use these bits to put the s2 page tables in the "other" | ||
27 | address space wouldn't work correctly. | ||
28 | |||
29 | Cc: qemu-stable@nongnu.org | ||
30 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1600 | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 31 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 32 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
24 | Message-id: 20201110150023.25533-3-peter.maydell@linaro.org | 33 | Message-id: 20230504135425.2748672-3-peter.maydell@linaro.org |
25 | --- | 34 | --- |
26 | hw/misc/tmp105.h | 7 +++++ | 35 | target/arm/ptw.c | 76 ++++++++++++++++++++++++++++++++---------------- |
27 | hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++------- | 36 | 1 file changed, 51 insertions(+), 25 deletions(-) |
28 | 2 files changed, 68 insertions(+), 9 deletions(-) | ||
29 | 37 | ||
30 | diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h | 38 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
31 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/misc/tmp105.h | 40 | --- a/target/arm/ptw.c |
33 | +++ b/hw/misc/tmp105.h | 41 | +++ b/target/arm/ptw.c |
34 | @@ -XXX,XX +XXX,XX @@ struct TMP105State { | 42 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) |
35 | int16_t limit[2]; | 43 | return stage_1_mmu_idx(arm_mmu_idx(env)); |
36 | int faults; | ||
37 | uint8_t alarm; | ||
38 | + /* | ||
39 | + * The TMP105 initially looks for a temperature rising above T_high; | ||
40 | + * once this is detected, the condition it looks for next is the | ||
41 | + * temperature falling below T_low. This flag is false when initially | ||
42 | + * looking for T_high, true when looking for T_low. | ||
43 | + */ | ||
44 | + bool detect_falling; | ||
45 | }; | ||
46 | |||
47 | #endif | ||
48 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/misc/tmp105.c | ||
51 | +++ b/hw/misc/tmp105.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s) | ||
53 | return; | ||
54 | } | ||
55 | |||
56 | - if ((s->config >> 1) & 1) { /* TM */ | ||
57 | - if (s->temperature >= s->limit[1]) | ||
58 | - s->alarm = 1; | ||
59 | - else if (s->temperature < s->limit[0]) | ||
60 | - s->alarm = 1; | ||
61 | + if (s->config >> 1 & 1) { | ||
62 | + /* | ||
63 | + * TM == 1 : Interrupt mode. We signal Alert when the | ||
64 | + * temperature rises above T_high, and expect the guest to clear | ||
65 | + * it (eg by reading a device register). | ||
66 | + */ | ||
67 | + if (s->detect_falling) { | ||
68 | + if (s->temperature < s->limit[0]) { | ||
69 | + s->alarm = 1; | ||
70 | + s->detect_falling = false; | ||
71 | + } | ||
72 | + } else { | ||
73 | + if (s->temperature >= s->limit[1]) { | ||
74 | + s->alarm = 1; | ||
75 | + s->detect_falling = true; | ||
76 | + } | ||
77 | + } | ||
78 | } else { | ||
79 | - if (s->temperature >= s->limit[1]) | ||
80 | - s->alarm = 1; | ||
81 | - else if (s->temperature < s->limit[0]) | ||
82 | - s->alarm = 0; | ||
83 | + /* | ||
84 | + * TM == 0 : Comparator mode. We signal Alert when the temperature | ||
85 | + * rises above T_high, and stop signalling it when the temperature | ||
86 | + * falls below T_low. | ||
87 | + */ | ||
88 | + if (s->detect_falling) { | ||
89 | + if (s->temperature < s->limit[0]) { | ||
90 | + s->alarm = 0; | ||
91 | + s->detect_falling = false; | ||
92 | + } | ||
93 | + } else { | ||
94 | + if (s->temperature >= s->limit[1]) { | ||
95 | + s->alarm = 1; | ||
96 | + s->detect_falling = true; | ||
97 | + } | ||
98 | + } | ||
99 | } | ||
100 | |||
101 | tmp105_interrupt_update(s); | ||
102 | @@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id) | ||
103 | return 0; | ||
104 | } | 44 | } |
105 | 45 | ||
106 | +static bool detect_falling_needed(void *opaque) | 46 | +/* |
47 | + * Return where we should do ptw loads from for a stage 2 walk. | ||
48 | + * This depends on whether the address we are looking up is a | ||
49 | + * Secure IPA or a NonSecure IPA, which we know from whether this is | ||
50 | + * Stage2 or Stage2_S. | ||
51 | + * If this is the Secure EL1&0 regime we need to check the NSW and SW bits. | ||
52 | + */ | ||
53 | +static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx) | ||
107 | +{ | 54 | +{ |
108 | + TMP105State *s = opaque; | 55 | + bool s2walk_secure; |
109 | + | 56 | + |
110 | + /* | 57 | + /* |
111 | + * We only need to migrate the detect_falling bool if it's set; | 58 | + * We're OK to check the current state of the CPU here because |
112 | + * for migration from older machines we assume that it is false | 59 | + * (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes |
113 | + * (ie temperature is not out of range). | 60 | + * (2) there's no way to do a lookup that cares about Stage 2 for a |
61 | + * different security state to the current one for AArch64, and AArch32 | ||
62 | + * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do | ||
63 | + * an NS stage 1+2 lookup while the NS bit is 0.) | ||
114 | + */ | 64 | + */ |
115 | + return s->detect_falling; | 65 | + if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) { |
66 | + return ARMMMUIdx_Phys_NS; | ||
67 | + } | ||
68 | + if (stage2idx == ARMMMUIdx_Stage2_S) { | ||
69 | + s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); | ||
70 | + } else { | ||
71 | + s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); | ||
72 | + } | ||
73 | + return s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; | ||
74 | + | ||
116 | +} | 75 | +} |
117 | + | 76 | + |
118 | +static const VMStateDescription vmstate_tmp105_detect_falling = { | 77 | static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) |
119 | + .name = "TMP105/detect-falling", | 78 | { |
120 | + .version_id = 1, | 79 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; |
121 | + .minimum_version_id = 1, | 80 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
122 | + .needed = detect_falling_needed, | 81 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
123 | + .fields = (VMStateField[]) { | 82 | ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; |
124 | + VMSTATE_BOOL(detect_falling, TMP105State), | 83 | uint8_t pte_attrs; |
125 | + VMSTATE_END_OF_LIST() | 84 | - bool pte_secure; |
126 | + } | 85 | |
127 | +}; | 86 | ptw->out_virt = addr; |
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
89 | if (regime_is_stage2(s2_mmu_idx)) { | ||
90 | S1Translate s2ptw = { | ||
91 | .in_mmu_idx = s2_mmu_idx, | ||
92 | - .in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS, | ||
93 | - .in_secure = is_secure, | ||
94 | + .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), | ||
95 | + .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, | ||
96 | .in_debug = true, | ||
97 | }; | ||
98 | GetPhysAddrResult s2 = { }; | ||
99 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
100 | } | ||
101 | ptw->out_phys = s2.f.phys_addr; | ||
102 | pte_attrs = s2.cacheattrs.attrs; | ||
103 | - pte_secure = s2.f.attrs.secure; | ||
104 | + ptw->out_secure = s2.f.attrs.secure; | ||
105 | } else { | ||
106 | /* Regime is physical. */ | ||
107 | ptw->out_phys = addr; | ||
108 | pte_attrs = 0; | ||
109 | - pte_secure = is_secure; | ||
110 | + ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; | ||
111 | } | ||
112 | ptw->out_host = NULL; | ||
113 | ptw->out_rw = false; | ||
114 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
115 | ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); | ||
116 | ptw->out_rw = full->prot & PAGE_WRITE; | ||
117 | pte_attrs = full->pte_attrs; | ||
118 | - pte_secure = full->attrs.secure; | ||
119 | + ptw->out_secure = full->attrs.secure; | ||
120 | #else | ||
121 | g_assert_not_reached(); | ||
122 | #endif | ||
123 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
124 | } | ||
125 | } | ||
126 | |||
127 | - /* Check if page table walk is to secure or non-secure PA space. */ | ||
128 | - ptw->out_secure = (is_secure | ||
129 | - && !(pte_secure | ||
130 | - ? env->cp15.vstcr_el2 & VSTCR_SW | ||
131 | - : env->cp15.vtcr_el2 & VTCR_NSW)); | ||
132 | ptw->out_be = regime_translation_big_endian(env, mmu_idx); | ||
133 | return true; | ||
134 | |||
135 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
136 | hwaddr ipa; | ||
137 | int s1_prot, s1_lgpgsz; | ||
138 | bool is_secure = ptw->in_secure; | ||
139 | - bool ret, ipa_secure, s2walk_secure; | ||
140 | + bool ret, ipa_secure; | ||
141 | ARMCacheAttrs cacheattrs1; | ||
142 | bool is_el0; | ||
143 | uint64_t hcr; | ||
144 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
145 | |||
146 | ipa = result->f.phys_addr; | ||
147 | ipa_secure = result->f.attrs.secure; | ||
148 | - if (is_secure) { | ||
149 | - /* Select TCR based on the NS bit from the S1 walk. */ | ||
150 | - s2walk_secure = !(ipa_secure | ||
151 | - ? env->cp15.vstcr_el2 & VSTCR_SW | ||
152 | - : env->cp15.vtcr_el2 & VTCR_NSW); | ||
153 | - } else { | ||
154 | - assert(!ipa_secure); | ||
155 | - s2walk_secure = false; | ||
156 | - } | ||
157 | |||
158 | is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; | ||
159 | - ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
160 | - ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; | ||
161 | - ptw->in_secure = s2walk_secure; | ||
162 | + ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
163 | + ptw->in_secure = ipa_secure; | ||
164 | + ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); | ||
165 | |||
166 | /* | ||
167 | * S1 is done, now do S2 translation. | ||
168 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
169 | ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
170 | break; | ||
171 | |||
172 | + case ARMMMUIdx_Stage2: | ||
173 | + case ARMMMUIdx_Stage2_S: | ||
174 | + /* | ||
175 | + * Second stage lookup uses physical for ptw; whether this is S or | ||
176 | + * NS may depend on the SW/NSW bits if this is a stage 2 lookup for | ||
177 | + * the Secure EL2&0 regime. | ||
178 | + */ | ||
179 | + ptw->in_ptw_idx = ptw_idx_for_stage_2(env, mmu_idx); | ||
180 | + break; | ||
128 | + | 181 | + |
129 | static const VMStateDescription vmstate_tmp105 = { | 182 | case ARMMMUIdx_E10_0: |
130 | .name = "TMP105", | 183 | s1_mmu_idx = ARMMMUIdx_Stage1_E0; |
131 | .version_id = 0, | 184 | goto do_twostage; |
132 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = { | 185 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
133 | VMSTATE_UINT8(alarm, TMP105State), | 186 | /* fall through */ |
134 | VMSTATE_I2C_SLAVE(i2c, TMP105State), | 187 | |
135 | VMSTATE_END_OF_LIST() | 188 | default: |
136 | + }, | 189 | - /* Single stage and second stage uses physical for ptw. */ |
137 | + .subsections = (const VMStateDescription*[]) { | 190 | + /* Single stage uses physical for ptw. */ |
138 | + &vmstate_tmp105_detect_falling, | 191 | ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; |
139 | + NULL | 192 | break; |
140 | } | 193 | } |
141 | }; | ||
142 | |||
143 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) | ||
144 | s->config = 0; | ||
145 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; | ||
146 | s->alarm = 0; | ||
147 | + s->detect_falling = false; | ||
148 | |||
149 | s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ | ||
150 | s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ | ||
151 | -- | 194 | -- |
152 | 2.20.1 | 195 | 2.34.1 |
153 | |||
154 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair.francis@wdc.com> | 1 | From: Akihiko Odaki <akihiko.odaki@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | This patch fixes CID 1432800 by removing an unnecessary check. | 3 | I am now employed by Daynix. Although my role as a reviewer of |
4 | macOS-related change is not very relevant to the employment, I decided | ||
5 | to use the company email address to avoid confusions from different | ||
6 | addresses. | ||
4 | 7 | ||
5 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 8 | Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Message-id: 20230506072333.32510-1-akihiko.odaki@daynix.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 13 | --- |
9 | hw/core/register.c | 4 ---- | 14 | MAINTAINERS | 4 ++-- |
10 | 1 file changed, 4 deletions(-) | 15 | 1 file changed, 2 insertions(+), 2 deletions(-) |
11 | 16 | ||
12 | diff --git a/hw/core/register.c b/hw/core/register.c | 17 | diff --git a/MAINTAINERS b/MAINTAINERS |
13 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/core/register.c | 19 | --- a/MAINTAINERS |
15 | +++ b/hw/core/register.c | 20 | +++ b/MAINTAINERS |
16 | @@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner, | 21 | @@ -XXX,XX +XXX,XX @@ Core Audio framework backend |
17 | int index = rae[i].addr / data_size; | 22 | M: Gerd Hoffmann <kraxel@redhat.com> |
18 | RegisterInfo *r = &ri[index]; | 23 | M: Philippe Mathieu-Daudé <philmd@linaro.org> |
19 | 24 | R: Christian Schoenebeck <qemu_oss@crudebyte.com> | |
20 | - if (data + data_size * index == 0 || !&rae[i]) { | 25 | -R: Akihiko Odaki <akihiko.odaki@gmail.com> |
21 | - continue; | 26 | +R: Akihiko Odaki <akihiko.odaki@daynix.com> |
22 | - } | 27 | S: Odd Fixes |
23 | - | 28 | F: audio/coreaudio.c |
24 | /* Init the register, this will zero it. */ | 29 | |
25 | object_initialize((void *)r, sizeof(*r), TYPE_REGISTER); | 30 | @@ -XXX,XX +XXX,XX @@ F: docs/devel/ui.rst |
31 | Cocoa graphics | ||
32 | M: Peter Maydell <peter.maydell@linaro.org> | ||
33 | M: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
34 | -R: Akihiko Odaki <akihiko.odaki@gmail.com> | ||
35 | +R: Akihiko Odaki <akihiko.odaki@daynix.com> | ||
36 | S: Odd Fixes | ||
37 | F: ui/cocoa.m | ||
26 | 38 | ||
27 | -- | 39 | -- |
28 | 2.20.1 | 40 | 2.34.1 |
29 | 41 | ||
30 | 42 | diff view generated by jsdifflib |
1 | In the mtspr helper we attempt to check for "is the timer disabled" | 1 | When we take a PNG screenshot the ordering of the colour channels in |
---|---|---|---|
2 | with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE | 2 | the data is not correct, resulting in the image having weird |
3 | is zero and the condition is always false (Coverity complains about | 3 | colouring compared to the actual display. (Specifically, on a |
4 | the dead code.) | 4 | little-endian host the blue and red channels are swapped; on |
5 | big-endian everything is wrong.) | ||
5 | 6 | ||
6 | The correct check would be to test whether the TTMR_M field in the | 7 | This happens because the pixman idea of the pixel data and the libpng |
7 | register is equal to TIMER_NONE instead. However, the | 8 | idea differ. PIXMAN_a8r8g8b8 defines that pixels are 32-bit values, |
8 | cpu_openrisc_timer_update() function checks whether the timer is | 9 | with A in bits 24-31, R in bits 16-23, G in bits 8-15 and B in bits |
9 | enabled (it looks at cpu->env.is_counting, which is set to 0 via | 10 | 0-7. This means that on little-endian systems the bytes in memory |
10 | cpu_openrisc_count_stop() when the TTMR_M field is set to | 11 | are |
11 | TIMER_NONE), so there's no need to check for "timer disabled" in the | 12 | B G R A |
12 | target/openrisc code. Instead, simply remove the dead code. | 13 | and on big-endian systems they are |
14 | A R G B | ||
13 | 15 | ||
14 | Fixes: Coverity CID 1005812 | 16 | libpng, on the other hand, thinks of pixels as being a series of |
17 | values for each channel, so its format PNG_COLOR_TYPE_RGB_ALPHA | ||
18 | always wants bytes in the order | ||
19 | R G B A | ||
20 | |||
21 | This isn't the same as the pixman order for either big or little | ||
22 | endian hosts. | ||
23 | |||
24 | The alpha channel is also unnecessary bulk in the output PNG file, | ||
25 | because there is no alpha information in a screenshot. | ||
26 | |||
27 | To handle the endianness issue, we already define in ui/qemu-pixman.h | ||
28 | various PIXMAN_BE_* and PIXMAN_LE_* values that give consistent | ||
29 | byte-order pixel channel formats. So we can use PIXMAN_BE_r8g8b8 and | ||
30 | PNG_COLOR_TYPE_RGB, which both have an in-memory byte order of | ||
31 | R G B | ||
32 | and 3 bytes per pixel. | ||
33 | |||
34 | (PPM format screenshots get this right; they already use the | ||
35 | PIXMAN_BE_r8g8b8 format.) | ||
36 | |||
37 | Cc: qemu-stable@nongnu.org | ||
38 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1622 | ||
39 | Fixes: 9a0a119a382867 ("Added parameter to take screenshot with screendump as PNG") | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 40 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Acked-by: Stafford Horne <shorne@gmail.com> | 41 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
17 | Message-id: 20201103114654.18540-1-peter.maydell@linaro.org | 42 | Message-id: 20230502135548.2451309-1-peter.maydell@linaro.org |
18 | --- | 43 | --- |
19 | target/openrisc/sys_helper.c | 3 --- | 44 | ui/console.c | 4 ++-- |
20 | 1 file changed, 3 deletions(-) | 45 | 1 file changed, 2 insertions(+), 2 deletions(-) |
21 | 46 | ||
22 | diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c | 47 | diff --git a/ui/console.c b/ui/console.c |
23 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/openrisc/sys_helper.c | 49 | --- a/ui/console.c |
25 | +++ b/target/openrisc/sys_helper.c | 50 | +++ b/ui/console.c |
26 | @@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) | 51 | @@ -XXX,XX +XXX,XX @@ static bool png_save(int fd, pixman_image_t *image, Error **errp) |
27 | 52 | png_struct *png_ptr; | |
28 | case TO_SPR(10, 1): /* TTCR */ | 53 | png_info *info_ptr; |
29 | cpu_openrisc_count_set(cpu, rb); | 54 | g_autoptr(pixman_image_t) linebuf = |
30 | - if (env->ttmr & TIMER_NONE) { | 55 | - qemu_pixman_linebuf_create(PIXMAN_a8r8g8b8, width); |
31 | - return; | 56 | + qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); |
32 | - } | 57 | uint8_t *buf = (uint8_t *)pixman_image_get_data(linebuf); |
33 | cpu_openrisc_timer_update(cpu); | 58 | FILE *f = fdopen(fd, "wb"); |
34 | break; | 59 | int y; |
35 | #endif | 60 | @@ -XXX,XX +XXX,XX @@ static bool png_save(int fd, pixman_image_t *image, Error **errp) |
61 | png_init_io(png_ptr, f); | ||
62 | |||
63 | png_set_IHDR(png_ptr, info_ptr, width, height, 8, | ||
64 | - PNG_COLOR_TYPE_RGB_ALPHA, PNG_INTERLACE_NONE, | ||
65 | + PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE, | ||
66 | PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE); | ||
67 | |||
68 | png_write_info(png_ptr, info_ptr); | ||
36 | -- | 69 | -- |
37 | 2.20.1 | 70 | 2.34.1 |
38 | 71 | ||
39 | 72 | diff view generated by jsdifflib |
1 | The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the | 1 | In the doc sources, we have a few cross-reference targets with odd |
---|---|---|---|
2 | power-up reset values for the T_low and T_high registers are 80 degrees C | 2 | names "pcsys_005fxyz". These are the legacy of the semi-automated |
3 | and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These | 3 | conversion of the old info docs to rST (the '005f' is because ASCII |
4 | values are then shifted right by four bits to give the register reset | 4 | 0x5f is '_' and the old info link names had underscores in them). |
5 | values, since both registers store the 12 bits of temperature data in bits | ||
6 | [15..4] of a 16 bit register. | ||
7 | 5 | ||
8 | We were resetting these registers to zero, which is problematic for Linux | 6 | Remove the targets which nothing links to, and rename the two targets |
9 | guests which enable the alert interrupt and then immediately take an | 7 | which are used to something a bit more descriptive. |
10 | unexpected overtemperature alert because the current temperature is above | ||
11 | freezing... | ||
12 | 8 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 10 | Message-id: 20230421163642.1151904-1-peter.maydell@linaro.org |
15 | Message-id: 20201110150023.25533-2-peter.maydell@linaro.org | 11 | Reviewed-by: Markus Armbruster <armbru@redhat.com> |
16 | --- | 12 | --- |
17 | hw/misc/tmp105.c | 3 +++ | 13 | docs/system/devices/igb.rst | 2 +- |
18 | 1 file changed, 3 insertions(+) | 14 | docs/system/devices/ivshmem.rst | 2 -- |
15 | docs/system/devices/net.rst | 2 +- | ||
16 | docs/system/devices/usb.rst | 2 -- | ||
17 | docs/system/keys.rst | 2 +- | ||
18 | docs/system/linuxboot.rst | 2 +- | ||
19 | docs/system/target-i386.rst | 4 ---- | ||
20 | 7 files changed, 4 insertions(+), 12 deletions(-) | ||
19 | 21 | ||
20 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c | 22 | diff --git a/docs/system/devices/igb.rst b/docs/system/devices/igb.rst |
21 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/misc/tmp105.c | 24 | --- a/docs/system/devices/igb.rst |
23 | +++ b/hw/misc/tmp105.c | 25 | +++ b/docs/system/devices/igb.rst |
24 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) | 26 | @@ -XXX,XX +XXX,XX @@ Using igb |
25 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; | 27 | ========= |
26 | s->alarm = 0; | 28 | |
27 | 29 | Using igb should be nothing different from using another network device. See | |
28 | + s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ | 30 | -:ref:`pcsys_005fnetwork` in general. |
29 | + s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ | 31 | +:ref:`Network_emulation` in general. |
30 | + | 32 | |
31 | tmp105_interrupt_update(s); | 33 | However, you may also need to perform additional steps to activate SR-IOV |
32 | } | 34 | feature on your guest. For Linux, refer to [4]_. |
35 | diff --git a/docs/system/devices/ivshmem.rst b/docs/system/devices/ivshmem.rst | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/docs/system/devices/ivshmem.rst | ||
38 | +++ b/docs/system/devices/ivshmem.rst | ||
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | -.. _pcsys_005fivshmem: | ||
41 | - | ||
42 | Inter-VM Shared Memory device | ||
43 | ----------------------------- | ||
44 | |||
45 | diff --git a/docs/system/devices/net.rst b/docs/system/devices/net.rst | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/docs/system/devices/net.rst | ||
48 | +++ b/docs/system/devices/net.rst | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | -.. _pcsys_005fnetwork: | ||
51 | +.. _Network_Emulation: | ||
52 | |||
53 | Network emulation | ||
54 | ----------------- | ||
55 | diff --git a/docs/system/devices/usb.rst b/docs/system/devices/usb.rst | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/docs/system/devices/usb.rst | ||
58 | +++ b/docs/system/devices/usb.rst | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | -.. _pcsys_005fusb: | ||
61 | - | ||
62 | USB emulation | ||
63 | ------------- | ||
64 | |||
65 | diff --git a/docs/system/keys.rst b/docs/system/keys.rst | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/docs/system/keys.rst | ||
68 | +++ b/docs/system/keys.rst | ||
69 | @@ -XXX,XX +XXX,XX @@ | ||
70 | -.. _pcsys_005fkeys: | ||
71 | +.. _GUI_keys: | ||
72 | |||
73 | Keys in the graphical frontends | ||
74 | ------------------------------- | ||
75 | diff --git a/docs/system/linuxboot.rst b/docs/system/linuxboot.rst | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/docs/system/linuxboot.rst | ||
78 | +++ b/docs/system/linuxboot.rst | ||
79 | @@ -XXX,XX +XXX,XX @@ virtual serial port and the QEMU monitor to the console with the | ||
80 | -append "root=/dev/hda console=ttyS0" -nographic | ||
81 | |||
82 | Use Ctrl-a c to switch between the serial console and the monitor (see | ||
83 | -:ref:`pcsys_005fkeys`). | ||
84 | +:ref:`GUI_keys`). | ||
85 | diff --git a/docs/system/target-i386.rst b/docs/system/target-i386.rst | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/docs/system/target-i386.rst | ||
88 | +++ b/docs/system/target-i386.rst | ||
89 | @@ -XXX,XX +XXX,XX @@ | ||
90 | x86 System emulator | ||
91 | ------------------- | ||
92 | |||
93 | -.. _pcsys_005fdevices: | ||
94 | - | ||
95 | Board-specific documentation | ||
96 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
97 | |||
98 | @@ -XXX,XX +XXX,XX @@ Architectural features | ||
99 | i386/sgx | ||
100 | i386/amd-memory-encryption | ||
101 | |||
102 | -.. _pcsys_005freq: | ||
103 | - | ||
104 | OS requirements | ||
105 | ~~~~~~~~~~~~~~~ | ||
33 | 106 | ||
34 | -- | 107 | -- |
35 | 2.20.1 | 108 | 2.34.1 |
36 | |||
37 | diff view generated by jsdifflib |
1 | In commit 5edab03d4040 we added tracepoints to the ps2 keyboard | 1 | Coverity points out (in CID 1508390) that write_bootloader has |
---|---|---|---|
2 | and mouse emulation. However we didn't remove all the debug-by-printf | 2 | some dead code, where we assign to 'p' and then in the following |
3 | support. In fact there is only one printf() remaining, and it is | 3 | line assign to it again. This happened as a result of the |
4 | redundant with the trace_ps2_write_mouse() event next to it. | 4 | refactoring in commit cd5066f8618b. |
5 | Remove the printf() and the now-unused DEBUG* macros. | 5 | |
6 | Fix the dead code by removing the 'void *v' variable entirely and | ||
7 | instead adding a cast when calling bl_setup_gt64120_jump_kernel(), as | ||
8 | we do at its other callsite in write_bootloader_nanomips(). | ||
6 | 9 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> | ||
10 | Message-id: 20201101133258.4240-1-peter.maydell@linaro.org | ||
11 | --- | 12 | --- |
12 | hw/input/ps2.c | 9 --------- | 13 | hw/mips/malta.c | 5 +---- |
13 | 1 file changed, 9 deletions(-) | 14 | 1 file changed, 1 insertion(+), 4 deletions(-) |
14 | 15 | ||
15 | diff --git a/hw/input/ps2.c b/hw/input/ps2.c | 16 | diff --git a/hw/mips/malta.c b/hw/mips/malta.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/input/ps2.c | 18 | --- a/hw/mips/malta.c |
18 | +++ b/hw/input/ps2.c | 19 | +++ b/hw/mips/malta.c |
19 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, |
20 | 21 | uint64_t kernel_entry) | |
21 | #include "trace.h" | 22 | { |
22 | 23 | uint32_t *p; | |
23 | -/* debug PC keyboard */ | 24 | - void *v; |
24 | -//#define DEBUG_KBD | 25 | |
25 | - | 26 | /* Small bootloader */ |
26 | -/* debug PC keyboard : only mouse */ | 27 | p = (uint32_t *)base; |
27 | -//#define DEBUG_MOUSE | 28 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, |
28 | - | 29 | * |
29 | /* Keyboard Commands */ | 30 | */ |
30 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ | 31 | |
31 | #define KBD_CMD_ECHO 0xEE | 32 | - v = p; |
32 | @@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val) | 33 | - bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry); |
33 | PS2MouseState *s = (PS2MouseState *)opaque; | 34 | - p = v; |
34 | 35 | + bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); | |
35 | trace_ps2_write_mouse(opaque, val); | 36 | |
36 | -#ifdef DEBUG_MOUSE | 37 | /* YAMON subroutines */ |
37 | - printf("kbd: write mouse 0x%02x\n", val); | 38 | p = (uint32_t *) (base + 0x800); |
38 | -#endif | ||
39 | switch(s->common.write_cmd) { | ||
40 | default: | ||
41 | case -1: | ||
42 | -- | 39 | -- |
43 | 2.20.1 | 40 | 2.34.1 |
44 | 41 | ||
45 | 42 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | Semihosting has been made a 'default y' entry in Kconfig, which does | ||
4 | not work because when building --without-default-devices, the | ||
5 | semihosting code would not be available. | ||
6 | |||
7 | Make semihosting unconditional when TCG is present. | ||
8 | |||
9 | Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only build") | ||
10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20230508181611.2621-2-farosas@suse.de | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/Kconfig | 8 +------- | ||
16 | 1 file changed, 1 insertion(+), 7 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/Kconfig b/target/arm/Kconfig | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/Kconfig | ||
21 | +++ b/target/arm/Kconfig | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | config ARM | ||
24 | bool | ||
25 | + select ARM_COMPATIBLE_SEMIHOSTING if TCG | ||
26 | |||
27 | config AARCH64 | ||
28 | bool | ||
29 | select ARM | ||
30 | - | ||
31 | -# This config exists just so we can make SEMIHOSTING default when TCG | ||
32 | -# is selected without also changing it for other architectures. | ||
33 | -config ARM_SEMIHOSTING | ||
34 | - bool | ||
35 | - default y if TCG && ARM | ||
36 | - select ARM_COMPATIBLE_SEMIHOSTING | ||
37 | -- | ||
38 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | The removal of the selection of A15MPCORE from ARM_VIRT also | 3 | We cannot allow this config to be disabled at the moment as not all of |
4 | removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC. | 4 | the relevant code is protected by it. |
5 | 5 | ||
6 | Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals") | 6 | Commit 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a |
7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> | 7 | KVM-only build") moved the CONFIGs of several boards to Kconfig, so it |
8 | Signed-off-by: Andrew Jones <drjones@redhat.com> | 8 | is now possible that nothing selects ARM_V7M (e.g. when doing a |
9 | Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com> | 9 | --without-default-devices build). |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | |
11 | Message-id: 20201111143440.112763-1-drjones@redhat.com | 11 | Return the CONFIG_ARM_V7M entry to a state where it is always selected |
12 | whenever TCG is available. | ||
13 | |||
14 | Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only build") | ||
15 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
17 | Message-id: 20230508181611.2621-3-farosas@suse.de | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 19 | --- |
14 | hw/arm/Kconfig | 1 + | 20 | target/arm/Kconfig | 1 + |
15 | 1 file changed, 1 insertion(+) | 21 | 1 file changed, 1 insertion(+) |
16 | 22 | ||
17 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 23 | diff --git a/target/arm/Kconfig b/target/arm/Kconfig |
18 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/Kconfig | 25 | --- a/target/arm/Kconfig |
20 | +++ b/hw/arm/Kconfig | 26 | +++ b/target/arm/Kconfig |
21 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT | 27 | @@ -XXX,XX +XXX,XX @@ |
22 | imply VFIO_PLATFORM | 28 | config ARM |
23 | imply VFIO_XGMAC | 29 | bool |
24 | imply TPM_TIS_SYSBUS | 30 | select ARM_COMPATIBLE_SEMIHOSTING if TCG |
25 | + select ARM_GIC | 31 | + select ARM_V7M if TCG |
26 | select ACPI | 32 | |
27 | select ARM_SMMUV3 | 33 | config AARCH64 |
28 | select GPIO_KEY | 34 | bool |
29 | -- | 35 | -- |
30 | 2.20.1 | 36 | 2.34.1 |
31 | |||
32 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | On a build configured with: --disable-tcg --enable-xen it is possible | ||
4 | to produce a QEMU binary with no TCG nor KVM support. Skip the cdrom | ||
5 | boot tests if that's the case. | ||
6 | |||
7 | Fixes: 0c1ae3ff9d ("tests/qtest: Fix tests when no KVM or TCG are present") | ||
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
9 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
10 | Message-id: 20230508181611.2621-4-farosas@suse.de | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | tests/qtest/cdrom-test.c | 10 ++++++++++ | ||
14 | 1 file changed, 10 insertions(+) | ||
15 | |||
16 | diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/tests/qtest/cdrom-test.c | ||
19 | +++ b/tests/qtest/cdrom-test.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static void test_cdboot(gconstpointer data) | ||
21 | |||
22 | static void add_x86_tests(void) | ||
23 | { | ||
24 | + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) { | ||
25 | + g_test_skip("No KVM or TCG accelerator available, skipping boot tests"); | ||
26 | + return; | ||
27 | + } | ||
28 | + | ||
29 | qtest_add_data_func("cdrom/boot/default", "-cdrom ", test_cdboot); | ||
30 | qtest_add_data_func("cdrom/boot/virtio-scsi", | ||
31 | "-device virtio-scsi -device scsi-cd,drive=cdr " | ||
32 | @@ -XXX,XX +XXX,XX @@ static void add_x86_tests(void) | ||
33 | |||
34 | static void add_s390x_tests(void) | ||
35 | { | ||
36 | + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) { | ||
37 | + g_test_skip("No KVM or TCG accelerator available, skipping boot tests"); | ||
38 | + return; | ||
39 | + } | ||
40 | + | ||
41 | qtest_add_data_func("cdrom/boot/default", "-cdrom ", test_cdboot); | ||
42 | qtest_add_data_func("cdrom/boot/virtio-scsi", | ||
43 | "-device virtio-scsi -device scsi-cd,drive=cdr " | ||
44 | -- | ||
45 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In check_s2_mmu_setup() we have a check that is attempting to | ||
2 | implement the part of AArch64.S2MinTxSZ that is specific to when EL1 | ||
3 | is AArch32: | ||
1 | 4 | ||
5 | if !s1aarch64 then | ||
6 | // EL1 is AArch32 | ||
7 | min_txsz = Min(min_txsz, 24); | ||
8 | |||
9 | Unfortunately we got this wrong in two ways: | ||
10 | |||
11 | (1) The minimum txsz corresponds to a maximum inputsize, but we got | ||
12 | the sense of the comparison wrong and were faulting for all | ||
13 | inputsizes less than 40 bits | ||
14 | |||
15 | (2) We try to implement this as an extra check that happens after | ||
16 | we've done the same txsz checks we would do for an AArch64 EL1, but | ||
17 | in fact the pseudocode is *loosening* the requirements, so that txsz | ||
18 | values that would fault for an AArch64 EL1 do not fault for AArch32 | ||
19 | EL1, because it does Min(old_min, 24), not Max(old_min, 24). | ||
20 | |||
21 | You can see this also in the text of the Arm ARM in table D8-8, which | ||
22 | shows that where the implemented PA size is less than 40 bits an | ||
23 | AArch32 EL1 is still OK with a configured stage2 T0SZ for a 40 bit | ||
24 | IPA, whereas if EL1 is AArch64 then the T0SZ must be big enough to | ||
25 | constrain the IPA to the implemented PA size. | ||
26 | |||
27 | Because of part (2), we can't do this as a separate check, but | ||
28 | have to integrate it into aa64_va_parameters(). Add a new argument | ||
29 | to that function to indicate that EL1 is 32-bit. All the existing | ||
30 | callsites except the one in get_phys_addr_lpae() can pass 'false', | ||
31 | because they are either doing a lookup for a stage 1 regime or | ||
32 | else they don't care about the tsz/tsz_oob fields. | ||
33 | |||
34 | Cc: qemu-stable@nongnu.org | ||
35 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1627 | ||
36 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
37 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
38 | Message-id: 20230509092059.3176487-1-peter.maydell@linaro.org | ||
39 | --- | ||
40 | target/arm/internals.h | 12 +++++++++++- | ||
41 | target/arm/gdbstub64.c | 2 +- | ||
42 | target/arm/helper.c | 15 +++++++++++++-- | ||
43 | target/arm/ptw.c | 14 ++------------ | ||
44 | target/arm/tcg/pauth_helper.c | 6 +++--- | ||
45 | 5 files changed, 30 insertions(+), 19 deletions(-) | ||
46 | |||
47 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/internals.h | ||
50 | +++ b/target/arm/internals.h | ||
51 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters { | ||
52 | ARMGranuleSize gran : 2; | ||
53 | } ARMVAParameters; | ||
54 | |||
55 | +/** | ||
56 | + * aa64_va_parameters: Return parameters for an AArch64 virtual address | ||
57 | + * @env: CPU | ||
58 | + * @va: virtual address to look up | ||
59 | + * @mmu_idx: determines translation regime to use | ||
60 | + * @data: true if this is a data access | ||
61 | + * @el1_is_aa32: true if we are asking about stage 2 when EL1 is AArch32 | ||
62 | + * (ignored if @mmu_idx is for a stage 1 regime; only affects tsz/tsz_oob) | ||
63 | + */ | ||
64 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
65 | - ARMMMUIdx mmu_idx, bool data); | ||
66 | + ARMMMUIdx mmu_idx, bool data, | ||
67 | + bool el1_is_aa32); | ||
68 | |||
69 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); | ||
70 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); | ||
71 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/arm/gdbstub64.c | ||
74 | +++ b/target/arm/gdbstub64.c | ||
75 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
76 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
77 | ARMVAParameters param; | ||
78 | |||
79 | - param = aa64_va_parameters(env, -is_high, mmu_idx, is_data); | ||
80 | + param = aa64_va_parameters(env, -is_high, mmu_idx, is_data, false); | ||
81 | return gdb_get_reg64(buf, pauth_ptr_mask(param)); | ||
82 | } | ||
83 | default: | ||
84 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/target/arm/helper.c | ||
87 | +++ b/target/arm/helper.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, | ||
89 | unsigned int page_size_granule, page_shift, num, scale, exponent; | ||
90 | /* Extract one bit to represent the va selector in use. */ | ||
91 | uint64_t select = sextract64(value, 36, 1); | ||
92 | - ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); | ||
93 | + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true, false); | ||
94 | TLBIRange ret = { }; | ||
95 | ARMGranuleSize gran; | ||
96 | |||
97 | @@ -XXX,XX +XXX,XX @@ static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, | ||
98 | } | ||
99 | |||
100 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
101 | - ARMMMUIdx mmu_idx, bool data) | ||
102 | + ARMMMUIdx mmu_idx, bool data, | ||
103 | + bool el1_is_aa32) | ||
104 | { | ||
105 | uint64_t tcr = regime_tcr(env, mmu_idx); | ||
106 | bool epd, hpd, tsz_oob, ds, ha, hd; | ||
107 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
108 | } | ||
109 | } | ||
110 | |||
111 | + if (stage2 && el1_is_aa32) { | ||
112 | + /* | ||
113 | + * For AArch32 EL1 the min txsz (and thus max IPA size) requirements | ||
114 | + * are loosened: a configured IPA of 40 bits is permitted even if | ||
115 | + * the implemented PA is less than that (and so a 40 bit IPA would | ||
116 | + * fault for an AArch64 EL1). See R_DTLMN. | ||
117 | + */ | ||
118 | + min_tsz = MIN(min_tsz, 24); | ||
119 | + } | ||
120 | + | ||
121 | if (tsz > max_tsz) { | ||
122 | tsz = max_tsz; | ||
123 | tsz_oob = true; | ||
124 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
125 | index XXXXXXX..XXXXXXX 100644 | ||
126 | --- a/target/arm/ptw.c | ||
127 | +++ b/target/arm/ptw.c | ||
128 | @@ -XXX,XX +XXX,XX @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, | ||
129 | |||
130 | sl0 = extract32(tcr, 6, 2); | ||
131 | if (is_aa64) { | ||
132 | - /* | ||
133 | - * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of | ||
134 | - * get_phys_addr_lpae, that used aa64_va_parameters which apply | ||
135 | - * to aarch64. If Stage1 is aarch32, the min_txsz is larger. | ||
136 | - * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to | ||
137 | - * inputsize is 64 - 24 = 40. | ||
138 | - */ | ||
139 | - if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { | ||
140 | - goto fail; | ||
141 | - } | ||
142 | - | ||
143 | /* | ||
144 | * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, | ||
145 | * so interleave AArch64.S2StartLevel. | ||
146 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
147 | int ps; | ||
148 | |||
149 | param = aa64_va_parameters(env, address, mmu_idx, | ||
150 | - access_type != MMU_INST_FETCH); | ||
151 | + access_type != MMU_INST_FETCH, | ||
152 | + !arm_el_is_aa64(env, 1)); | ||
153 | level = 0; | ||
154 | |||
155 | /* | ||
156 | diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c | ||
157 | index XXXXXXX..XXXXXXX 100644 | ||
158 | --- a/target/arm/tcg/pauth_helper.c | ||
159 | +++ b/target/arm/tcg/pauth_helper.c | ||
160 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
161 | ARMPACKey *key, bool data) | ||
162 | { | ||
163 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
164 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); | ||
165 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); | ||
166 | uint64_t pac, ext_ptr, ext, test; | ||
167 | int bot_bit, top_bit; | ||
168 | |||
169 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
170 | ARMPACKey *key, bool data, int keynumber) | ||
171 | { | ||
172 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
173 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); | ||
174 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); | ||
175 | int bot_bit, top_bit; | ||
176 | uint64_t pac, orig_ptr, test; | ||
177 | |||
178 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
179 | static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) | ||
180 | { | ||
181 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
182 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); | ||
183 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); | ||
184 | |||
185 | return pauth_original_ptr(ptr, param); | ||
186 | } | ||
187 | -- | ||
188 | 2.34.1 | diff view generated by jsdifflib |