1
Arm queue; bugfixes only.
1
Hi; not so many patches in this one, but notably it includes the
2
fix for various Avocado CI tests failing (incorrectly reported by
3
Avocado as a timeout, but really a QEMU exit-with-error).
2
4
3
thanks
5
thanks
4
-- PMM
6
-- PMM
5
7
6
The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739:
8
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
7
9
8
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000)
10
Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)
9
11
10
are available in the Git repository at:
12
are available in the Git repository at:
11
13
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930
13
15
14
for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42:
16
for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:
15
17
16
tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000)
18
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)
17
19
18
----------------------------------------------------------------
20
----------------------------------------------------------------
19
target-arm queue:
21
target-arm queue:
20
* hw/arm/virt: ARM_VIRT must select ARM_GIC
22
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
21
* exynos: Fix bad printf format specifiers
23
PMCNTENSET_EL0 or PMCNTENCLR_EL0
22
* hw/input/ps2.c: Remove remnants of printf debug
24
* Make writes to MDCR_EL3 use PMU start/finish calls
23
* target/openrisc: Remove dead code attempting to check "is timer disabled"
25
* Let AArch32 write to SDCR.SCCD
24
* register: Remove unnecessary NULL check
26
* Rearrange cpu64.c so all the CPU initfns are together
25
* util/cutils: Fix Coverity array overrun in freq_to_str()
27
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
26
* configure: Make "does libgio work" test pull in some actual functions
28
* hw/arm/virt: fix some minor issues with generated device tree
27
* tmp105: reset the T_low and T_High registers
29
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
28
* tmp105: Correct handling of temperature limit checks
29
30
30
----------------------------------------------------------------
31
----------------------------------------------------------------
31
Alex Chen (1):
32
Francisco Iglesias (1):
32
exynos: Fix bad printf format specifiers
33
hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
33
34
34
Alistair Francis (1):
35
Jean-Philippe Brucker (4):
35
register: Remove unnecessary NULL check
36
hw/arm/virt: Fix devicetree warning about the root node
37
hw/arm/virt: Fix devicetree warning about the GIC node
38
hw/arm/virt: Use "msi-map" devicetree property for PCI
39
hw/arm/virt: Fix devicetree warning about the SMMU node
36
40
37
Andrew Jones (1):
41
Jerome Forissier (1):
38
hw/arm/virt: ARM_VIRT must select ARM_GIC
42
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
39
43
40
Peter Maydell (5):
44
Peter Maydell (4):
41
hw/input/ps2.c: Remove remnants of printf debug
45
target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
42
target/openrisc: Remove dead code attempting to check "is timer disabled"
46
target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
43
configure: Make "does libgio work" test pull in some actual functions
47
target/arm: Update SDCR_VALID_MASK to include SCCD
44
hw/misc/tmp105: reset the T_low and T_High registers
48
target/arm: Rearrange cpu64.c so all the CPU initfns are together
45
tmp105: Correct handling of temperature limit checks
46
49
47
Philippe Mathieu-Daudé (1):
50
include/hw/arm/xlnx-zynqmp.h | 3 +
48
util/cutils: Fix Coverity array overrun in freq_to_str()
51
target/arm/cpu.h | 8 +-
49
52
hw/arm/virt.c | 8 +-
50
configure | 11 +++++--
53
hw/arm/xlnx-zynqmp.c | 36 +++
51
hw/misc/tmp105.h | 7 +++++
54
target/arm/cpu64.c | 712 +++++++++++++++++++++----------------------
52
hw/core/register.c | 4 ---
55
target/arm/helper.c | 32 +-
53
hw/input/ps2.c | 9 ------
56
6 files changed, 427 insertions(+), 372 deletions(-)
54
hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------
55
hw/timer/exynos4210_mct.c | 4 +--
56
hw/timer/exynos4210_pwm.c | 8 ++---
57
target/openrisc/sys_helper.c | 3 --
58
util/cutils.c | 3 +-
59
hw/arm/Kconfig | 1 +
60
10 files changed, 89 insertions(+), 34 deletions(-)
61
diff view generated by jsdifflib
New patch
1
In commit 01765386a888 we made some system register write functions
2
call pmu_op_start()/pmu_op_finish(). This means that they now touch
3
timers, so for icount to work these registers must have the ARM_CP_IO
4
flag set.
1
5
6
This fixes a bug where when icount is enabled a guest that touches
7
MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
8
QEMU to print an error message and exit, for example:
9
10
[ 2.495971] TCP: Hash tables configured (established 1024 bind 1024)
11
[ 2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
12
[ 2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
13
[ 2.496917] NET: Registered protocol family 1
14
qemu-system-aarch64: Bad icount read
15
16
Reported-by: Thomas Huth <thuth@redhat.com>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
20
---
21
target/arm/helper.c | 12 ++++++------
22
1 file changed, 6 insertions(+), 6 deletions(-)
23
24
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/helper.c
27
+++ b/target/arm/helper.c
28
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
29
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
30
*/
31
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
32
- .access = PL0_RW, .type = ARM_CP_ALIAS,
33
+ .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
34
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
35
.writefn = pmcntenset_write,
36
.accessfn = pmreg_access,
37
.raw_writefn = raw_write },
38
- { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
39
+ { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
40
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
41
.access = PL0_RW, .accessfn = pmreg_access,
42
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
44
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
45
.accessfn = pmreg_access,
46
.writefn = pmcntenclr_write,
47
- .type = ARM_CP_ALIAS },
48
+ .type = ARM_CP_ALIAS | ARM_CP_IO },
49
{ .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
50
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
51
.access = PL0_RW, .accessfn = pmreg_access,
52
- .type = ARM_CP_ALIAS,
53
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
54
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
55
.writefn = pmcntenclr_write },
56
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
57
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
58
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
59
.resetvalue = 0,
60
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
61
- { .name = "SDCR", .type = ARM_CP_ALIAS,
62
+ { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
63
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
64
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
65
.writefn = sdcr_write,
66
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
67
* value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
68
*/
69
ARMCPRegInfo mdcr_el2 = {
70
- .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
71
+ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
72
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
73
.writefn = mdcr_el2_write,
74
.access = PL2_RW, .resetvalue = pmu_num_counters(env),
75
--
76
2.25.1
diff view generated by jsdifflib
1
The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device
1
In commit 01765386a88868 we fixed a bug where we weren't correctly
2
signals an alert when the temperature equals or exceeds the T_high value and
2
bracketing changes to some registers with pmu_op_start() and
3
then remains high until a device register is read or the device responds to
3
pmu_op_finish() calls for changes which affect whether the PMU
4
the SMBUS Alert Response address, or the device is put into Shutdown Mode.
4
counters might be enabled. However, we missed the case of writes to
5
Thereafter the Alert pin will only be re-signalled when temperature falls
5
the AArch64 MDCR_EL3 register, because (unlike its AArch32
6
below T_low; alert can then be cleared in the same set of ways, and the
6
counterpart) they are currently done directly to the CPU state struct
7
device returns to its initial "alert when temperature goes above T_high"
7
without going through the sdcr_write() function.
8
mode. (If this textual description is confusing, see figure 3 in the
9
TI datasheet at https://www.ti.com/lit/gpn/tmp105 .)
10
8
11
We were misimplementing this as a simple "always alert if temperature is
9
Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
12
above T_high or below T_low" condition, which gives a spurious alert on
10
The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
13
startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset
11
masking off the bits which don't exist in the AArch32 register".
14
limit values.
15
16
Implement the correct (hysteresis) behaviour by tracking whether we
17
are currently looking for the temperature to rise over T_high or
18
for it to fall below T_low. Our implementation of the comparator
19
mode (TM==0) wasn't wrong, but rephrase it to match the way that
20
interrupt mode is now handled for clarity.
21
12
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Cédric Le Goater <clg@kaod.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
24
Message-id: 20201110150023.25533-3-peter.maydell@linaro.org
15
Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
25
---
16
---
26
hw/misc/tmp105.h | 7 +++++
17
target/arm/helper.c | 18 ++++++++++++++----
27
hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++-------
18
1 file changed, 14 insertions(+), 4 deletions(-)
28
2 files changed, 68 insertions(+), 9 deletions(-)
29
19
30
diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/misc/tmp105.h
22
--- a/target/arm/helper.c
33
+++ b/hw/misc/tmp105.h
23
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ struct TMP105State {
24
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
35
int16_t limit[2];
36
int faults;
37
uint8_t alarm;
38
+ /*
39
+ * The TMP105 initially looks for a temperature rising above T_high;
40
+ * once this is detected, the condition it looks for next is the
41
+ * temperature falling below T_low. This flag is false when initially
42
+ * looking for T_high, true when looking for T_low.
43
+ */
44
+ bool detect_falling;
45
};
46
47
#endif
48
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/misc/tmp105.c
51
+++ b/hw/misc/tmp105.c
52
@@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s)
53
return;
54
}
25
}
55
26
}
56
- if ((s->config >> 1) & 1) {                    /* TM */
27
57
- if (s->temperature >= s->limit[1])
28
-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
58
- s->alarm = 1;
29
- uint64_t value)
59
- else if (s->temperature < s->limit[0])
30
+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
60
- s->alarm = 1;
31
+ uint64_t value)
61
+ if (s->config >> 1 & 1) {
32
{
62
+ /*
33
/*
63
+ * TM == 1 : Interrupt mode. We signal Alert when the
34
* Some MDCR_EL3 bits affect whether PMU counters are running:
64
+ * temperature rises above T_high, and expect the guest to clear
35
@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
65
+ * it (eg by reading a device register).
36
if (pmu_op) {
66
+ */
37
pmu_op_start(env);
67
+ if (s->detect_falling) {
68
+ if (s->temperature < s->limit[0]) {
69
+ s->alarm = 1;
70
+ s->detect_falling = false;
71
+ }
72
+ } else {
73
+ if (s->temperature >= s->limit[1]) {
74
+ s->alarm = 1;
75
+ s->detect_falling = true;
76
+ }
77
+ }
78
} else {
79
- if (s->temperature >= s->limit[1])
80
- s->alarm = 1;
81
- else if (s->temperature < s->limit[0])
82
- s->alarm = 0;
83
+ /*
84
+ * TM == 0 : Comparator mode. We signal Alert when the temperature
85
+ * rises above T_high, and stop signalling it when the temperature
86
+ * falls below T_low.
87
+ */
88
+ if (s->detect_falling) {
89
+ if (s->temperature < s->limit[0]) {
90
+ s->alarm = 0;
91
+ s->detect_falling = false;
92
+ }
93
+ } else {
94
+ if (s->temperature >= s->limit[1]) {
95
+ s->alarm = 1;
96
+ s->detect_falling = true;
97
+ }
98
+ }
99
}
38
}
100
39
- env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
101
tmp105_interrupt_update(s);
40
+ env->cp15.mdcr_el3 = value;
102
@@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id)
41
if (pmu_op) {
103
return 0;
42
pmu_op_finish(env);
43
}
104
}
44
}
105
45
106
+static bool detect_falling_needed(void *opaque)
46
+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
47
+ uint64_t value)
107
+{
48
+{
108
+ TMP105State *s = opaque;
49
+ /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
109
+
50
+ mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
110
+ /*
111
+ * We only need to migrate the detect_falling bool if it's set;
112
+ * for migration from older machines we assume that it is false
113
+ * (ie temperature is not out of range).
114
+ */
115
+ return s->detect_falling;
116
+}
51
+}
117
+
52
+
118
+static const VMStateDescription vmstate_tmp105_detect_falling = {
53
static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
119
+ .name = "TMP105/detect-falling",
54
uint64_t value)
120
+ .version_id = 1,
55
{
121
+ .minimum_version_id = 1,
56
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
122
+ .needed = detect_falling_needed,
57
.access = PL2_RW,
123
+ .fields = (VMStateField[]) {
58
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
124
+ VMSTATE_BOOL(detect_falling, TMP105State),
59
{ .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
125
+ VMSTATE_END_OF_LIST()
60
+ .type = ARM_CP_IO,
126
+ }
61
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
127
+};
62
.resetvalue = 0,
128
+
63
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
129
static const VMStateDescription vmstate_tmp105 = {
64
+ .access = PL3_RW,
130
.name = "TMP105",
65
+ .writefn = mdcr_el3_write,
131
.version_id = 0,
66
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
132
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = {
67
{ .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
133
VMSTATE_UINT8(alarm, TMP105State),
68
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
134
VMSTATE_I2C_SLAVE(i2c, TMP105State),
69
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
135
VMSTATE_END_OF_LIST()
136
+ },
137
+ .subsections = (const VMStateDescription*[]) {
138
+ &vmstate_tmp105_detect_falling,
139
+ NULL
140
}
141
};
142
143
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
144
s->config = 0;
145
s->faults = tmp105_faultq[(s->config >> 3) & 3];
146
s->alarm = 0;
147
+ s->detect_falling = false;
148
149
s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
150
s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
151
--
70
--
152
2.20.1
71
2.25.1
153
154
diff view generated by jsdifflib
1
In commit 76346b6264a9b01979 we tried to add a configure check that
1
Our SDCR_VALID_MASK doesn't include all of the bits which are defined
2
the libgio pkg-config data was correct, which builds an executable
2
by the current architecture. In particular in commit 0b42f4fab9d3 we
3
linked against it. Unfortunately this doesn't catch the problem
3
forgot to add SCCD, which meant that an AArch32 guest couldn't
4
(missing static library dependency info), because a "do nothing" test
4
actually use the SCCD bit to disable counting in Secure state.
5
source file doesn't have any symbol references that cause the linker
6
to pull in .o files from libgio.a, and so we don't see the "missing
7
symbols from libmount" error that a full QEMU link triggers.
8
5
9
(The ineffective test went unnoticed because of a typo that
6
Add all the currently defined bits; we don't implement all of them,
10
effectively disabled libgio unconditionally, but after commit
7
but this makes them be reads-as-written, which is architecturally
11
3569a5dfc11f2 fixed that, a static link of the system emulator on
8
valid and matches how we currently handle most of the others in the
12
Ubuntu stopped working again.)
9
mask.
13
14
Improve the gio test by having the test source fragment reference a
15
g_dbus function (which is what is indirectly causing us to end up
16
wanting functions from libmount).
17
10
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20201116104617.18333-1-peter.maydell@linaro.org
13
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
21
---
14
---
22
configure | 11 +++++++++--
15
target/arm/cpu.h | 8 +++++++-
23
1 file changed, 9 insertions(+), 2 deletions(-)
16
1 file changed, 7 insertions(+), 1 deletion(-)
24
17
25
diff --git a/configure b/configure
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
26
index XXXXXXX..XXXXXXX 100755
19
index XXXXXXX..XXXXXXX 100644
27
--- a/configure
20
--- a/target/arm/cpu.h
28
+++ b/configure
21
+++ b/target/arm/cpu.h
29
@@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
22
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
30
# Check that the libraries actually work -- Ubuntu 18.04 ships
23
FIELD(CPTR_EL3, TAM, 30, 1)
31
# with pkg-config --static --libs data for gio-2.0 that is missing
24
FIELD(CPTR_EL3, TCPAC, 31, 1)
32
# -lblkid and will give a link error.
25
33
- write_c_skeleton
26
+#define MDCR_MTPME (1U << 28)
34
- if compile_prog "" "$gio_libs" ; then
27
+#define MDCR_TDCC (1U << 27)
35
+ cat > $TMPC <<EOF
28
#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
36
+#include <gio/gio.h>
29
#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
37
+int main(void)
30
#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
38
+{
31
#define MDCR_EPMAD (1U << 21)
39
+ g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0);
32
#define MDCR_EDAD (1U << 20)
40
+ return 0;
33
+#define MDCR_TTRF (1U << 19)
41
+}
34
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
42
+EOF
35
#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
43
+ if compile_prog "$gio_cflags" "$gio_libs" ; then
36
#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
44
gio=yes
37
#define MDCR_SDD (1U << 16)
45
else
38
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
46
gio=no
39
#define MDCR_HPMN (0x1fU)
40
41
/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
42
-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
43
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
44
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
45
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
46
47
#define CPSR_M (0x1fU)
48
#define CPSR_T (1U << 5)
47
--
49
--
48
2.20.1
50
2.25.1
49
50
diff view generated by jsdifflib
1
The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the
1
cpu64.c has ended up in a slightly odd order -- it starts with the
2
power-up reset values for the T_low and T_high registers are 80 degrees C
2
initfns for most of the models-real-hardware CPUs; after that comes a
3
and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These
3
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
4
values are then shifted right by four bits to give the register reset
4
come the initfns for the 'host' and 'max' CPU types, and then after
5
values, since both registers store the 12 bits of temperature data in bits
5
that one more models-real-hardware CPU initfn, for a64fx. (This
6
[15..4] of a 16 bit register.
6
ordering is partly historical and partly required because a64fx needs
7
the SVE properties.)
7
8
8
We were resetting these registers to zero, which is problematic for Linux
9
Reorder the file into:
9
guests which enable the alert interrupt and then immediately take an
10
* CPU property support functions
10
unexpected overtemperature alert because the current temperature is above
11
* initfns for real hardware CPUs
11
freezing...
12
* initfns for host and max
13
* class boilerplate
12
14
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20201110150023.25533-2-peter.maydell@linaro.org
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
---
18
---
17
hw/misc/tmp105.c | 3 +++
19
target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
18
1 file changed, 3 insertions(+)
20
1 file changed, 356 insertions(+), 356 deletions(-)
19
21
20
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
22
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
21
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/misc/tmp105.c
24
--- a/target/arm/cpu64.c
23
+++ b/hw/misc/tmp105.c
25
+++ b/target/arm/cpu64.c
24
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
26
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
25
s->faults = tmp105_faultq[(s->config >> 3) & 3];
27
define_cortex_a72_a57_a53_cp_reginfo(cpu);
26
s->alarm = 0;
27
28
+ s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
29
+ s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
30
+
31
tmp105_interrupt_update(s);
32
}
28
}
33
29
30
-static void aarch64_a57_initfn(Object *obj)
31
-{
32
- ARMCPU *cpu = ARM_CPU(obj);
33
-
34
- cpu->dtb_compatible = "arm,cortex-a57";
35
- set_feature(&cpu->env, ARM_FEATURE_V8);
36
- set_feature(&cpu->env, ARM_FEATURE_NEON);
37
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
38
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
39
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
40
- set_feature(&cpu->env, ARM_FEATURE_EL2);
41
- set_feature(&cpu->env, ARM_FEATURE_EL3);
42
- set_feature(&cpu->env, ARM_FEATURE_PMU);
43
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
44
- cpu->midr = 0x411fd070;
45
- cpu->revidr = 0x00000000;
46
- cpu->reset_fpsid = 0x41034070;
47
- cpu->isar.mvfr0 = 0x10110222;
48
- cpu->isar.mvfr1 = 0x12111111;
49
- cpu->isar.mvfr2 = 0x00000043;
50
- cpu->ctr = 0x8444c004;
51
- cpu->reset_sctlr = 0x00c50838;
52
- cpu->isar.id_pfr0 = 0x00000131;
53
- cpu->isar.id_pfr1 = 0x00011011;
54
- cpu->isar.id_dfr0 = 0x03010066;
55
- cpu->id_afr0 = 0x00000000;
56
- cpu->isar.id_mmfr0 = 0x10101105;
57
- cpu->isar.id_mmfr1 = 0x40000000;
58
- cpu->isar.id_mmfr2 = 0x01260000;
59
- cpu->isar.id_mmfr3 = 0x02102211;
60
- cpu->isar.id_isar0 = 0x02101110;
61
- cpu->isar.id_isar1 = 0x13112111;
62
- cpu->isar.id_isar2 = 0x21232042;
63
- cpu->isar.id_isar3 = 0x01112131;
64
- cpu->isar.id_isar4 = 0x00011142;
65
- cpu->isar.id_isar5 = 0x00011121;
66
- cpu->isar.id_isar6 = 0;
67
- cpu->isar.id_aa64pfr0 = 0x00002222;
68
- cpu->isar.id_aa64dfr0 = 0x10305106;
69
- cpu->isar.id_aa64isar0 = 0x00011120;
70
- cpu->isar.id_aa64mmfr0 = 0x00001124;
71
- cpu->isar.dbgdidr = 0x3516d000;
72
- cpu->isar.dbgdevid = 0x01110f13;
73
- cpu->isar.dbgdevid1 = 0x2;
74
- cpu->isar.reset_pmcr_el0 = 0x41013000;
75
- cpu->clidr = 0x0a200023;
76
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
77
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
78
- cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
79
- cpu->dcz_blocksize = 4; /* 64 bytes */
80
- cpu->gic_num_lrs = 4;
81
- cpu->gic_vpribits = 5;
82
- cpu->gic_vprebits = 5;
83
- cpu->gic_pribits = 5;
84
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
85
-}
86
-
87
-static void aarch64_a53_initfn(Object *obj)
88
-{
89
- ARMCPU *cpu = ARM_CPU(obj);
90
-
91
- cpu->dtb_compatible = "arm,cortex-a53";
92
- set_feature(&cpu->env, ARM_FEATURE_V8);
93
- set_feature(&cpu->env, ARM_FEATURE_NEON);
94
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
95
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
96
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
97
- set_feature(&cpu->env, ARM_FEATURE_EL2);
98
- set_feature(&cpu->env, ARM_FEATURE_EL3);
99
- set_feature(&cpu->env, ARM_FEATURE_PMU);
100
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
101
- cpu->midr = 0x410fd034;
102
- cpu->revidr = 0x00000000;
103
- cpu->reset_fpsid = 0x41034070;
104
- cpu->isar.mvfr0 = 0x10110222;
105
- cpu->isar.mvfr1 = 0x12111111;
106
- cpu->isar.mvfr2 = 0x00000043;
107
- cpu->ctr = 0x84448004; /* L1Ip = VIPT */
108
- cpu->reset_sctlr = 0x00c50838;
109
- cpu->isar.id_pfr0 = 0x00000131;
110
- cpu->isar.id_pfr1 = 0x00011011;
111
- cpu->isar.id_dfr0 = 0x03010066;
112
- cpu->id_afr0 = 0x00000000;
113
- cpu->isar.id_mmfr0 = 0x10101105;
114
- cpu->isar.id_mmfr1 = 0x40000000;
115
- cpu->isar.id_mmfr2 = 0x01260000;
116
- cpu->isar.id_mmfr3 = 0x02102211;
117
- cpu->isar.id_isar0 = 0x02101110;
118
- cpu->isar.id_isar1 = 0x13112111;
119
- cpu->isar.id_isar2 = 0x21232042;
120
- cpu->isar.id_isar3 = 0x01112131;
121
- cpu->isar.id_isar4 = 0x00011142;
122
- cpu->isar.id_isar5 = 0x00011121;
123
- cpu->isar.id_isar6 = 0;
124
- cpu->isar.id_aa64pfr0 = 0x00002222;
125
- cpu->isar.id_aa64dfr0 = 0x10305106;
126
- cpu->isar.id_aa64isar0 = 0x00011120;
127
- cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
128
- cpu->isar.dbgdidr = 0x3516d000;
129
- cpu->isar.dbgdevid = 0x00110f13;
130
- cpu->isar.dbgdevid1 = 0x1;
131
- cpu->isar.reset_pmcr_el0 = 0x41033000;
132
- cpu->clidr = 0x0a200023;
133
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
134
- cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
135
- cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
136
- cpu->dcz_blocksize = 4; /* 64 bytes */
137
- cpu->gic_num_lrs = 4;
138
- cpu->gic_vpribits = 5;
139
- cpu->gic_vprebits = 5;
140
- cpu->gic_pribits = 5;
141
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
142
-}
143
-
144
-static void aarch64_a72_initfn(Object *obj)
145
-{
146
- ARMCPU *cpu = ARM_CPU(obj);
147
-
148
- cpu->dtb_compatible = "arm,cortex-a72";
149
- set_feature(&cpu->env, ARM_FEATURE_V8);
150
- set_feature(&cpu->env, ARM_FEATURE_NEON);
151
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
152
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
153
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
154
- set_feature(&cpu->env, ARM_FEATURE_EL2);
155
- set_feature(&cpu->env, ARM_FEATURE_EL3);
156
- set_feature(&cpu->env, ARM_FEATURE_PMU);
157
- cpu->midr = 0x410fd083;
158
- cpu->revidr = 0x00000000;
159
- cpu->reset_fpsid = 0x41034080;
160
- cpu->isar.mvfr0 = 0x10110222;
161
- cpu->isar.mvfr1 = 0x12111111;
162
- cpu->isar.mvfr2 = 0x00000043;
163
- cpu->ctr = 0x8444c004;
164
- cpu->reset_sctlr = 0x00c50838;
165
- cpu->isar.id_pfr0 = 0x00000131;
166
- cpu->isar.id_pfr1 = 0x00011011;
167
- cpu->isar.id_dfr0 = 0x03010066;
168
- cpu->id_afr0 = 0x00000000;
169
- cpu->isar.id_mmfr0 = 0x10201105;
170
- cpu->isar.id_mmfr1 = 0x40000000;
171
- cpu->isar.id_mmfr2 = 0x01260000;
172
- cpu->isar.id_mmfr3 = 0x02102211;
173
- cpu->isar.id_isar0 = 0x02101110;
174
- cpu->isar.id_isar1 = 0x13112111;
175
- cpu->isar.id_isar2 = 0x21232042;
176
- cpu->isar.id_isar3 = 0x01112131;
177
- cpu->isar.id_isar4 = 0x00011142;
178
- cpu->isar.id_isar5 = 0x00011121;
179
- cpu->isar.id_aa64pfr0 = 0x00002222;
180
- cpu->isar.id_aa64dfr0 = 0x10305106;
181
- cpu->isar.id_aa64isar0 = 0x00011120;
182
- cpu->isar.id_aa64mmfr0 = 0x00001124;
183
- cpu->isar.dbgdidr = 0x3516d000;
184
- cpu->isar.dbgdevid = 0x01110f13;
185
- cpu->isar.dbgdevid1 = 0x2;
186
- cpu->isar.reset_pmcr_el0 = 0x41023000;
187
- cpu->clidr = 0x0a200023;
188
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
189
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
190
- cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
191
- cpu->dcz_blocksize = 4; /* 64 bytes */
192
- cpu->gic_num_lrs = 4;
193
- cpu->gic_vpribits = 5;
194
- cpu->gic_vprebits = 5;
195
- cpu->gic_pribits = 5;
196
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
197
-}
198
-
199
-static void aarch64_a76_initfn(Object *obj)
200
-{
201
- ARMCPU *cpu = ARM_CPU(obj);
202
-
203
- cpu->dtb_compatible = "arm,cortex-a76";
204
- set_feature(&cpu->env, ARM_FEATURE_V8);
205
- set_feature(&cpu->env, ARM_FEATURE_NEON);
206
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
207
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
208
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
209
- set_feature(&cpu->env, ARM_FEATURE_EL2);
210
- set_feature(&cpu->env, ARM_FEATURE_EL3);
211
- set_feature(&cpu->env, ARM_FEATURE_PMU);
212
-
213
- /* Ordered by B2.4 AArch64 registers by functional group */
214
- cpu->clidr = 0x82000023;
215
- cpu->ctr = 0x8444C004;
216
- cpu->dcz_blocksize = 4;
217
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
218
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
219
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
220
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
221
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
222
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
223
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
224
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
225
- cpu->id_afr0 = 0x00000000;
226
- cpu->isar.id_dfr0 = 0x04010088;
227
- cpu->isar.id_isar0 = 0x02101110;
228
- cpu->isar.id_isar1 = 0x13112111;
229
- cpu->isar.id_isar2 = 0x21232042;
230
- cpu->isar.id_isar3 = 0x01112131;
231
- cpu->isar.id_isar4 = 0x00010142;
232
- cpu->isar.id_isar5 = 0x01011121;
233
- cpu->isar.id_isar6 = 0x00000010;
234
- cpu->isar.id_mmfr0 = 0x10201105;
235
- cpu->isar.id_mmfr1 = 0x40000000;
236
- cpu->isar.id_mmfr2 = 0x01260000;
237
- cpu->isar.id_mmfr3 = 0x02122211;
238
- cpu->isar.id_mmfr4 = 0x00021110;
239
- cpu->isar.id_pfr0 = 0x10010131;
240
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
241
- cpu->isar.id_pfr2 = 0x00000011;
242
- cpu->midr = 0x414fd0b1; /* r4p1 */
243
- cpu->revidr = 0;
244
-
245
- /* From B2.18 CCSIDR_EL1 */
246
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
247
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
248
- cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
249
-
250
- /* From B2.93 SCTLR_EL3 */
251
- cpu->reset_sctlr = 0x30c50838;
252
-
253
- /* From B4.23 ICH_VTR_EL2 */
254
- cpu->gic_num_lrs = 4;
255
- cpu->gic_vpribits = 5;
256
- cpu->gic_vprebits = 5;
257
- cpu->gic_pribits = 5;
258
-
259
- /* From B5.1 AdvSIMD AArch64 register summary */
260
- cpu->isar.mvfr0 = 0x10110222;
261
- cpu->isar.mvfr1 = 0x13211111;
262
- cpu->isar.mvfr2 = 0x00000043;
263
-
264
- /* From D5.1 AArch64 PMU register summary */
265
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
266
-}
267
-
268
-static void aarch64_neoverse_n1_initfn(Object *obj)
269
-{
270
- ARMCPU *cpu = ARM_CPU(obj);
271
-
272
- cpu->dtb_compatible = "arm,neoverse-n1";
273
- set_feature(&cpu->env, ARM_FEATURE_V8);
274
- set_feature(&cpu->env, ARM_FEATURE_NEON);
275
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
276
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
277
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
278
- set_feature(&cpu->env, ARM_FEATURE_EL2);
279
- set_feature(&cpu->env, ARM_FEATURE_EL3);
280
- set_feature(&cpu->env, ARM_FEATURE_PMU);
281
-
282
- /* Ordered by B2.4 AArch64 registers by functional group */
283
- cpu->clidr = 0x82000023;
284
- cpu->ctr = 0x8444c004;
285
- cpu->dcz_blocksize = 4;
286
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
287
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
288
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
289
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
290
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
291
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
292
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
293
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
294
- cpu->id_afr0 = 0x00000000;
295
- cpu->isar.id_dfr0 = 0x04010088;
296
- cpu->isar.id_isar0 = 0x02101110;
297
- cpu->isar.id_isar1 = 0x13112111;
298
- cpu->isar.id_isar2 = 0x21232042;
299
- cpu->isar.id_isar3 = 0x01112131;
300
- cpu->isar.id_isar4 = 0x00010142;
301
- cpu->isar.id_isar5 = 0x01011121;
302
- cpu->isar.id_isar6 = 0x00000010;
303
- cpu->isar.id_mmfr0 = 0x10201105;
304
- cpu->isar.id_mmfr1 = 0x40000000;
305
- cpu->isar.id_mmfr2 = 0x01260000;
306
- cpu->isar.id_mmfr3 = 0x02122211;
307
- cpu->isar.id_mmfr4 = 0x00021110;
308
- cpu->isar.id_pfr0 = 0x10010131;
309
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
310
- cpu->isar.id_pfr2 = 0x00000011;
311
- cpu->midr = 0x414fd0c1; /* r4p1 */
312
- cpu->revidr = 0;
313
-
314
- /* From B2.23 CCSIDR_EL1 */
315
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
316
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
317
- cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
318
-
319
- /* From B2.98 SCTLR_EL3 */
320
- cpu->reset_sctlr = 0x30c50838;
321
-
322
- /* From B4.23 ICH_VTR_EL2 */
323
- cpu->gic_num_lrs = 4;
324
- cpu->gic_vpribits = 5;
325
- cpu->gic_vprebits = 5;
326
- cpu->gic_pribits = 5;
327
-
328
- /* From B5.1 AdvSIMD AArch64 register summary */
329
- cpu->isar.mvfr0 = 0x10110222;
330
- cpu->isar.mvfr1 = 0x13211111;
331
- cpu->isar.mvfr2 = 0x00000043;
332
-
333
- /* From D5.1 AArch64 PMU register summary */
334
- cpu->isar.reset_pmcr_el0 = 0x410c3000;
335
-}
336
-
337
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
338
{
339
/*
340
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
341
cpu->isar.id_aa64mmfr0 = t;
342
}
343
344
+static void aarch64_a57_initfn(Object *obj)
345
+{
346
+ ARMCPU *cpu = ARM_CPU(obj);
347
+
348
+ cpu->dtb_compatible = "arm,cortex-a57";
349
+ set_feature(&cpu->env, ARM_FEATURE_V8);
350
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
351
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
352
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
353
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
354
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
355
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
356
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
357
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
358
+ cpu->midr = 0x411fd070;
359
+ cpu->revidr = 0x00000000;
360
+ cpu->reset_fpsid = 0x41034070;
361
+ cpu->isar.mvfr0 = 0x10110222;
362
+ cpu->isar.mvfr1 = 0x12111111;
363
+ cpu->isar.mvfr2 = 0x00000043;
364
+ cpu->ctr = 0x8444c004;
365
+ cpu->reset_sctlr = 0x00c50838;
366
+ cpu->isar.id_pfr0 = 0x00000131;
367
+ cpu->isar.id_pfr1 = 0x00011011;
368
+ cpu->isar.id_dfr0 = 0x03010066;
369
+ cpu->id_afr0 = 0x00000000;
370
+ cpu->isar.id_mmfr0 = 0x10101105;
371
+ cpu->isar.id_mmfr1 = 0x40000000;
372
+ cpu->isar.id_mmfr2 = 0x01260000;
373
+ cpu->isar.id_mmfr3 = 0x02102211;
374
+ cpu->isar.id_isar0 = 0x02101110;
375
+ cpu->isar.id_isar1 = 0x13112111;
376
+ cpu->isar.id_isar2 = 0x21232042;
377
+ cpu->isar.id_isar3 = 0x01112131;
378
+ cpu->isar.id_isar4 = 0x00011142;
379
+ cpu->isar.id_isar5 = 0x00011121;
380
+ cpu->isar.id_isar6 = 0;
381
+ cpu->isar.id_aa64pfr0 = 0x00002222;
382
+ cpu->isar.id_aa64dfr0 = 0x10305106;
383
+ cpu->isar.id_aa64isar0 = 0x00011120;
384
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
385
+ cpu->isar.dbgdidr = 0x3516d000;
386
+ cpu->isar.dbgdevid = 0x01110f13;
387
+ cpu->isar.dbgdevid1 = 0x2;
388
+ cpu->isar.reset_pmcr_el0 = 0x41013000;
389
+ cpu->clidr = 0x0a200023;
390
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
391
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
392
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
393
+ cpu->dcz_blocksize = 4; /* 64 bytes */
394
+ cpu->gic_num_lrs = 4;
395
+ cpu->gic_vpribits = 5;
396
+ cpu->gic_vprebits = 5;
397
+ cpu->gic_pribits = 5;
398
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
399
+}
400
+
401
+static void aarch64_a53_initfn(Object *obj)
402
+{
403
+ ARMCPU *cpu = ARM_CPU(obj);
404
+
405
+ cpu->dtb_compatible = "arm,cortex-a53";
406
+ set_feature(&cpu->env, ARM_FEATURE_V8);
407
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
408
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
409
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
410
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
411
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
412
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
413
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
414
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
415
+ cpu->midr = 0x410fd034;
416
+ cpu->revidr = 0x00000000;
417
+ cpu->reset_fpsid = 0x41034070;
418
+ cpu->isar.mvfr0 = 0x10110222;
419
+ cpu->isar.mvfr1 = 0x12111111;
420
+ cpu->isar.mvfr2 = 0x00000043;
421
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
422
+ cpu->reset_sctlr = 0x00c50838;
423
+ cpu->isar.id_pfr0 = 0x00000131;
424
+ cpu->isar.id_pfr1 = 0x00011011;
425
+ cpu->isar.id_dfr0 = 0x03010066;
426
+ cpu->id_afr0 = 0x00000000;
427
+ cpu->isar.id_mmfr0 = 0x10101105;
428
+ cpu->isar.id_mmfr1 = 0x40000000;
429
+ cpu->isar.id_mmfr2 = 0x01260000;
430
+ cpu->isar.id_mmfr3 = 0x02102211;
431
+ cpu->isar.id_isar0 = 0x02101110;
432
+ cpu->isar.id_isar1 = 0x13112111;
433
+ cpu->isar.id_isar2 = 0x21232042;
434
+ cpu->isar.id_isar3 = 0x01112131;
435
+ cpu->isar.id_isar4 = 0x00011142;
436
+ cpu->isar.id_isar5 = 0x00011121;
437
+ cpu->isar.id_isar6 = 0;
438
+ cpu->isar.id_aa64pfr0 = 0x00002222;
439
+ cpu->isar.id_aa64dfr0 = 0x10305106;
440
+ cpu->isar.id_aa64isar0 = 0x00011120;
441
+ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
442
+ cpu->isar.dbgdidr = 0x3516d000;
443
+ cpu->isar.dbgdevid = 0x00110f13;
444
+ cpu->isar.dbgdevid1 = 0x1;
445
+ cpu->isar.reset_pmcr_el0 = 0x41033000;
446
+ cpu->clidr = 0x0a200023;
447
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
448
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
449
+ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
450
+ cpu->dcz_blocksize = 4; /* 64 bytes */
451
+ cpu->gic_num_lrs = 4;
452
+ cpu->gic_vpribits = 5;
453
+ cpu->gic_vprebits = 5;
454
+ cpu->gic_pribits = 5;
455
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
456
+}
457
+
458
+static void aarch64_a72_initfn(Object *obj)
459
+{
460
+ ARMCPU *cpu = ARM_CPU(obj);
461
+
462
+ cpu->dtb_compatible = "arm,cortex-a72";
463
+ set_feature(&cpu->env, ARM_FEATURE_V8);
464
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
465
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
466
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
467
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
468
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
469
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
470
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
471
+ cpu->midr = 0x410fd083;
472
+ cpu->revidr = 0x00000000;
473
+ cpu->reset_fpsid = 0x41034080;
474
+ cpu->isar.mvfr0 = 0x10110222;
475
+ cpu->isar.mvfr1 = 0x12111111;
476
+ cpu->isar.mvfr2 = 0x00000043;
477
+ cpu->ctr = 0x8444c004;
478
+ cpu->reset_sctlr = 0x00c50838;
479
+ cpu->isar.id_pfr0 = 0x00000131;
480
+ cpu->isar.id_pfr1 = 0x00011011;
481
+ cpu->isar.id_dfr0 = 0x03010066;
482
+ cpu->id_afr0 = 0x00000000;
483
+ cpu->isar.id_mmfr0 = 0x10201105;
484
+ cpu->isar.id_mmfr1 = 0x40000000;
485
+ cpu->isar.id_mmfr2 = 0x01260000;
486
+ cpu->isar.id_mmfr3 = 0x02102211;
487
+ cpu->isar.id_isar0 = 0x02101110;
488
+ cpu->isar.id_isar1 = 0x13112111;
489
+ cpu->isar.id_isar2 = 0x21232042;
490
+ cpu->isar.id_isar3 = 0x01112131;
491
+ cpu->isar.id_isar4 = 0x00011142;
492
+ cpu->isar.id_isar5 = 0x00011121;
493
+ cpu->isar.id_aa64pfr0 = 0x00002222;
494
+ cpu->isar.id_aa64dfr0 = 0x10305106;
495
+ cpu->isar.id_aa64isar0 = 0x00011120;
496
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
497
+ cpu->isar.dbgdidr = 0x3516d000;
498
+ cpu->isar.dbgdevid = 0x01110f13;
499
+ cpu->isar.dbgdevid1 = 0x2;
500
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
501
+ cpu->clidr = 0x0a200023;
502
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
503
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
504
+ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
505
+ cpu->dcz_blocksize = 4; /* 64 bytes */
506
+ cpu->gic_num_lrs = 4;
507
+ cpu->gic_vpribits = 5;
508
+ cpu->gic_vprebits = 5;
509
+ cpu->gic_pribits = 5;
510
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
511
+}
512
+
513
+static void aarch64_a76_initfn(Object *obj)
514
+{
515
+ ARMCPU *cpu = ARM_CPU(obj);
516
+
517
+ cpu->dtb_compatible = "arm,cortex-a76";
518
+ set_feature(&cpu->env, ARM_FEATURE_V8);
519
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
520
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
521
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
522
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
523
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
524
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
525
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
526
+
527
+ /* Ordered by B2.4 AArch64 registers by functional group */
528
+ cpu->clidr = 0x82000023;
529
+ cpu->ctr = 0x8444C004;
530
+ cpu->dcz_blocksize = 4;
531
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
532
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
533
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
534
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
535
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
536
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
537
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
538
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
539
+ cpu->id_afr0 = 0x00000000;
540
+ cpu->isar.id_dfr0 = 0x04010088;
541
+ cpu->isar.id_isar0 = 0x02101110;
542
+ cpu->isar.id_isar1 = 0x13112111;
543
+ cpu->isar.id_isar2 = 0x21232042;
544
+ cpu->isar.id_isar3 = 0x01112131;
545
+ cpu->isar.id_isar4 = 0x00010142;
546
+ cpu->isar.id_isar5 = 0x01011121;
547
+ cpu->isar.id_isar6 = 0x00000010;
548
+ cpu->isar.id_mmfr0 = 0x10201105;
549
+ cpu->isar.id_mmfr1 = 0x40000000;
550
+ cpu->isar.id_mmfr2 = 0x01260000;
551
+ cpu->isar.id_mmfr3 = 0x02122211;
552
+ cpu->isar.id_mmfr4 = 0x00021110;
553
+ cpu->isar.id_pfr0 = 0x10010131;
554
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
555
+ cpu->isar.id_pfr2 = 0x00000011;
556
+ cpu->midr = 0x414fd0b1; /* r4p1 */
557
+ cpu->revidr = 0;
558
+
559
+ /* From B2.18 CCSIDR_EL1 */
560
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
561
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
562
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
563
+
564
+ /* From B2.93 SCTLR_EL3 */
565
+ cpu->reset_sctlr = 0x30c50838;
566
+
567
+ /* From B4.23 ICH_VTR_EL2 */
568
+ cpu->gic_num_lrs = 4;
569
+ cpu->gic_vpribits = 5;
570
+ cpu->gic_vprebits = 5;
571
+ cpu->gic_pribits = 5;
572
+
573
+ /* From B5.1 AdvSIMD AArch64 register summary */
574
+ cpu->isar.mvfr0 = 0x10110222;
575
+ cpu->isar.mvfr1 = 0x13211111;
576
+ cpu->isar.mvfr2 = 0x00000043;
577
+
578
+ /* From D5.1 AArch64 PMU register summary */
579
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
580
+}
581
+
582
+static void aarch64_a64fx_initfn(Object *obj)
583
+{
584
+ ARMCPU *cpu = ARM_CPU(obj);
585
+
586
+ cpu->dtb_compatible = "arm,a64fx";
587
+ set_feature(&cpu->env, ARM_FEATURE_V8);
588
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
589
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
590
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
591
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
592
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
593
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
594
+ cpu->midr = 0x461f0010;
595
+ cpu->revidr = 0x00000000;
596
+ cpu->ctr = 0x86668006;
597
+ cpu->reset_sctlr = 0x30000180;
598
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
599
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
600
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
601
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
602
+ cpu->id_aa64afr0 = 0x0000000000000000;
603
+ cpu->id_aa64afr1 = 0x0000000000000000;
604
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
605
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
606
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
607
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
608
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
609
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
610
+ cpu->clidr = 0x0000000080000023;
611
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
612
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
613
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
614
+ cpu->dcz_blocksize = 6; /* 256 bytes */
615
+ cpu->gic_num_lrs = 4;
616
+ cpu->gic_vpribits = 5;
617
+ cpu->gic_vprebits = 5;
618
+ cpu->gic_pribits = 5;
619
+
620
+ /* The A64FX supports only 128, 256 and 512 bit vector lengths */
621
+ aarch64_add_sve_properties(obj);
622
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
623
+ | (1 << 1) /* 256bit */
624
+ | (1 << 3); /* 512bit */
625
+
626
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
627
+
628
+ /* TODO: Add A64FX specific HPC extension registers */
629
+}
630
+
631
+static void aarch64_neoverse_n1_initfn(Object *obj)
632
+{
633
+ ARMCPU *cpu = ARM_CPU(obj);
634
+
635
+ cpu->dtb_compatible = "arm,neoverse-n1";
636
+ set_feature(&cpu->env, ARM_FEATURE_V8);
637
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
638
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
639
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
640
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
641
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
642
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
643
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
644
+
645
+ /* Ordered by B2.4 AArch64 registers by functional group */
646
+ cpu->clidr = 0x82000023;
647
+ cpu->ctr = 0x8444c004;
648
+ cpu->dcz_blocksize = 4;
649
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
650
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
651
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
652
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
653
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
654
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
655
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
656
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
657
+ cpu->id_afr0 = 0x00000000;
658
+ cpu->isar.id_dfr0 = 0x04010088;
659
+ cpu->isar.id_isar0 = 0x02101110;
660
+ cpu->isar.id_isar1 = 0x13112111;
661
+ cpu->isar.id_isar2 = 0x21232042;
662
+ cpu->isar.id_isar3 = 0x01112131;
663
+ cpu->isar.id_isar4 = 0x00010142;
664
+ cpu->isar.id_isar5 = 0x01011121;
665
+ cpu->isar.id_isar6 = 0x00000010;
666
+ cpu->isar.id_mmfr0 = 0x10201105;
667
+ cpu->isar.id_mmfr1 = 0x40000000;
668
+ cpu->isar.id_mmfr2 = 0x01260000;
669
+ cpu->isar.id_mmfr3 = 0x02122211;
670
+ cpu->isar.id_mmfr4 = 0x00021110;
671
+ cpu->isar.id_pfr0 = 0x10010131;
672
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
673
+ cpu->isar.id_pfr2 = 0x00000011;
674
+ cpu->midr = 0x414fd0c1; /* r4p1 */
675
+ cpu->revidr = 0;
676
+
677
+ /* From B2.23 CCSIDR_EL1 */
678
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
679
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
680
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
681
+
682
+ /* From B2.98 SCTLR_EL3 */
683
+ cpu->reset_sctlr = 0x30c50838;
684
+
685
+ /* From B4.23 ICH_VTR_EL2 */
686
+ cpu->gic_num_lrs = 4;
687
+ cpu->gic_vpribits = 5;
688
+ cpu->gic_vprebits = 5;
689
+ cpu->gic_pribits = 5;
690
+
691
+ /* From B5.1 AdvSIMD AArch64 register summary */
692
+ cpu->isar.mvfr0 = 0x10110222;
693
+ cpu->isar.mvfr1 = 0x13211111;
694
+ cpu->isar.mvfr2 = 0x00000043;
695
+
696
+ /* From D5.1 AArch64 PMU register summary */
697
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
698
+}
699
+
700
static void aarch64_host_initfn(Object *obj)
701
{
702
#if defined(CONFIG_KVM)
703
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
704
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
705
}
706
707
-static void aarch64_a64fx_initfn(Object *obj)
708
-{
709
- ARMCPU *cpu = ARM_CPU(obj);
710
-
711
- cpu->dtb_compatible = "arm,a64fx";
712
- set_feature(&cpu->env, ARM_FEATURE_V8);
713
- set_feature(&cpu->env, ARM_FEATURE_NEON);
714
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
715
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
716
- set_feature(&cpu->env, ARM_FEATURE_EL2);
717
- set_feature(&cpu->env, ARM_FEATURE_EL3);
718
- set_feature(&cpu->env, ARM_FEATURE_PMU);
719
- cpu->midr = 0x461f0010;
720
- cpu->revidr = 0x00000000;
721
- cpu->ctr = 0x86668006;
722
- cpu->reset_sctlr = 0x30000180;
723
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
724
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
725
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
726
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
727
- cpu->id_aa64afr0 = 0x0000000000000000;
728
- cpu->id_aa64afr1 = 0x0000000000000000;
729
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
730
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
731
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
732
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
733
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
734
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
735
- cpu->clidr = 0x0000000080000023;
736
- cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
737
- cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
738
- cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
739
- cpu->dcz_blocksize = 6; /* 256 bytes */
740
- cpu->gic_num_lrs = 4;
741
- cpu->gic_vpribits = 5;
742
- cpu->gic_vprebits = 5;
743
- cpu->gic_pribits = 5;
744
-
745
- /* The A64FX supports only 128, 256 and 512 bit vector lengths */
746
- aarch64_add_sve_properties(obj);
747
- cpu->sve_vq.supported = (1 << 0) /* 128bit */
748
- | (1 << 1) /* 256bit */
749
- | (1 << 3); /* 512bit */
750
-
751
- cpu->isar.reset_pmcr_el0 = 0x46014040;
752
-
753
- /* TODO: Add A64FX specific HPC extension registers */
754
-}
755
-
756
static const ARMCPUInfo aarch64_cpus[] = {
757
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
758
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
34
--
759
--
35
2.20.1
760
2.25.1
36
761
37
762
diff view generated by jsdifflib
1
From: Alex Chen <alex.chen@huawei.com>
1
From: Francisco Iglesias <francisco.iglesias@amd.com>
2
2
3
We should use printf format specifier "%u" instead of "%d" for
3
Connect ZynqMP's USB controllers.
4
argument of type "unsigned int".
5
4
6
Reported-by: Euler Robot <euler.robot@huawei.com>
5
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20201111073651.72804-1-alex.chen@huawei.com
7
Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/timer/exynos4210_mct.c | 4 ++--
11
include/hw/arm/xlnx-zynqmp.h | 3 +++
13
hw/timer/exynos4210_pwm.c | 8 ++++----
12
hw/arm/xlnx-zynqmp.c | 36 ++++++++++++++++++++++++++++++++++++
14
2 files changed, 6 insertions(+), 6 deletions(-)
13
2 files changed, 39 insertions(+)
15
14
16
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
15
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/exynos4210_mct.c
17
--- a/include/hw/arm/xlnx-zynqmp.h
19
+++ b/hw/timer/exynos4210_mct.c
18
+++ b/include/hw/arm/xlnx-zynqmp.h
20
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
19
@@ -XXX,XX +XXX,XX @@
21
/* If CSTAT is pending and IRQ is enabled */
20
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
22
if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
21
#include "hw/misc/xlnx-zynqmp-crf.h"
23
(s->reg.int_enb & G_INT_ENABLE(id))) {
22
#include "hw/timer/cadence_ttc.h"
24
- DPRINTF("gcmp timer[%d] IRQ\n", id);
23
+#include "hw/usb/hcd-dwc3.h"
25
+ DPRINTF("gcmp timer[%u] IRQ\n", id);
24
26
qemu_irq_raise(s->irq[id]);
25
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
26
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
27
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
28
#define XLNX_ZYNQMP_NUM_SPIS 2
29
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
30
#define XLNX_ZYNQMP_NUM_ADMA_CH 8
31
+#define XLNX_ZYNQMP_NUM_USB 2
32
33
#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
34
#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
35
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
36
XlnxZynqMPAPUCtrl apu_ctrl;
37
XlnxZynqMPCRF crf;
38
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
39
+ USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
40
41
char *boot_cpu;
42
ARMCPU *boot_cpu_ptr;
43
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/xlnx-zynqmp.c
46
+++ b/hw/arm/xlnx-zynqmp.c
47
@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
48
77, 78, 79, 80, 81, 82, 83, 84
49
};
50
51
+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
52
+ 0xFE200000, 0xFE300000
53
+};
54
+
55
+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
56
+ 65, 70
57
+};
58
+
59
typedef struct XlnxZynqMPGICRegion {
60
int region_index;
61
uint32_t address;
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
63
object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
64
object_initialize_child(obj, "qspi-irq-orgate",
65
&s->qspi_irq_orgate, TYPE_OR_IRQ);
66
+
67
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
68
+ object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
69
+ }
70
}
71
72
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
73
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
74
object_property_add_alias(OBJECT(s), bus_name,
75
OBJECT(&s->qspi), target_bus);
27
}
76
}
77
+
78
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
79
+ if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
80
+ OBJECT(system_memory), errp)) {
81
+ return;
82
+ }
83
+
84
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
85
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
86
+
87
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
88
+ return;
89
+ }
90
+
91
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
92
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
93
+ gic_spi[usb_intr[i]]);
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
95
+ gic_spi[usb_intr[i] + 1]);
96
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
97
+ gic_spi[usb_intr[i] + 2]);
98
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
99
+ gic_spi[usb_intr[i] + 3]);
100
+ }
28
}
101
}
29
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
102
30
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
103
static Property xlnx_zynqmp_props[] = {
31
32
if (freq != s->freq) {
33
- DPRINTF("freq=%dHz\n", s->freq);
34
+ DPRINTF("freq=%uHz\n", s->freq);
35
36
/* global timer */
37
tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
38
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/timer/exynos4210_pwm.c
41
+++ b/hw/timer/exynos4210_pwm.c
42
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
43
44
if (freq != s->timer[id].freq) {
45
ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
46
- DPRINTF("freq=%dHz\n", s->timer[id].freq);
47
+ DPRINTF("freq=%uHz\n", s->timer[id].freq);
48
}
49
}
50
51
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
52
uint32_t id = s->id;
53
bool cmp;
54
55
- DPRINTF("timer %d tick\n", id);
56
+ DPRINTF("timer %u tick\n", id);
57
58
/* set irq status */
59
p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
60
61
/* raise IRQ */
62
if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
63
- DPRINTF("timer %d IRQ\n", id);
64
+ DPRINTF("timer %u IRQ\n", id);
65
qemu_irq_raise(p->timer[id].irq);
66
}
67
68
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
69
}
70
71
if (cmp) {
72
- DPRINTF("auto reload timer %d count to %x\n", id,
73
+ DPRINTF("auto reload timer %u count to %x\n", id,
74
p->timer[id].reg_tcntb);
75
ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
76
ptimer_run(p->timer[id].ptimer, 1);
77
--
104
--
78
2.20.1
105
2.25.1
79
80
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN):
3
The devicetree specification requires a 'model' property in the root
4
node. Fix the corresponding dt-validate warning:
4
5
5
>>> Overrunning array "suffixes" of 7 8-byte elements at element
6
/: 'model' is a required property
6
index 7 (byte offset 63) using index "idx" (which evaluates to 7).
7
From schema: dtschema/schemas/root-node.yaml
7
8
8
Note, the biggest input value freq_to_str() can accept is UINT64_MAX,
9
Use the same name for model as for compatible. The specification
9
which is ~18.446 EHz, less than 1000 EHz.
10
recommends that 'compatible' follows the format 'manufacturer,model' and
11
'model' follows the format 'manufacturer,model-number'. Since our
12
'compatible' doesn't observe this, 'model' doesn't really need to
13
either.
10
14
11
Reported-by: Eduardo Habkost <ehabkost@redhat.com>
15
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
18
Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
16
Message-id: 20201101215755.2021421-1-f4bug@amsat.org
17
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
20
---
21
util/cutils.c | 3 ++-
21
hw/arm/virt.c | 1 +
22
1 file changed, 2 insertions(+), 1 deletion(-)
22
1 file changed, 1 insertion(+)
23
23
24
diff --git a/util/cutils.c b/util/cutils.c
24
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
25
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
26
--- a/util/cutils.c
26
--- a/hw/arm/virt.c
27
+++ b/util/cutils.c
27
+++ b/hw/arm/virt.c
28
@@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz)
28
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
29
double freq = freq_hz;
29
qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
30
size_t idx = 0;
30
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
31
31
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
32
- while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) {
32
+ qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
33
+ while (freq >= 1000.0) {
33
34
freq /= 1000.0;
34
/* /chosen must exist for load_dtb to fill in necessary properties later */
35
idx++;
35
qemu_fdt_add_subnode(fdt, "/chosen");
36
}
37
+ assert(idx < ARRAY_SIZE(suffixes));
38
39
return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]);
40
}
41
--
36
--
42
2.20.1
37
2.25.1
43
44
diff view generated by jsdifflib
1
From: Andrew Jones <drjones@redhat.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
The removal of the selection of A15MPCORE from ARM_VIRT also
3
The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
4
removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC.
4
the corresponding dt-validate warning:
5
5
6
Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals")
6
interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
7
From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
9
Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com>
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20201111143440.112763-1-drjones@redhat.com
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
---
14
hw/arm/Kconfig | 1 +
15
hw/arm/virt.c | 1 +
15
1 file changed, 1 insertion(+)
16
1 file changed, 1 insertion(+)
16
17
17
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/Kconfig
20
--- a/hw/arm/virt.c
20
+++ b/hw/arm/Kconfig
21
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
22
@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
22
imply VFIO_PLATFORM
23
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
23
imply VFIO_XGMAC
24
"arm,gic-v3-its");
24
imply TPM_TIS_SYSBUS
25
qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
25
+ select ARM_GIC
26
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
26
select ACPI
27
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
27
select ARM_SMMUV3
28
2, vms->memmap[VIRT_GIC_ITS].base,
28
select GPIO_KEY
29
2, vms->memmap[VIRT_GIC_ITS].size);
29
--
30
--
30
2.20.1
31
2.25.1
31
32
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
This patch fixes CID 1432800 by removing an unnecessary check.
3
The "msi-parent" property can be used on the PCI node when MSIs do not
4
contain sideband data (device IDs) [1]. In QEMU, MSI transactions
5
contain the requester ID, so the PCI node should use the "msi-map"
6
property instead of "msi-parent". In our case the property describes an
7
identity map between requester ID and sideband data.
4
8
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
This fixes a warning when passing the DTB generated by QEMU to dtc,
10
following a recent change to the GICv3 node:
11
12
Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1
13
14
[1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt
15
16
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Eric Auger <eric.auger@redhat.com>
19
Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
21
---
9
hw/core/register.c | 4 ----
22
hw/arm/virt.c | 4 ++--
10
1 file changed, 4 deletions(-)
23
1 file changed, 2 insertions(+), 2 deletions(-)
11
24
12
diff --git a/hw/core/register.c b/hw/core/register.c
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
13
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/core/register.c
27
--- a/hw/arm/virt.c
15
+++ b/hw/core/register.c
28
+++ b/hw/arm/virt.c
16
@@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner,
29
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
17
int index = rae[i].addr / data_size;
30
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
18
RegisterInfo *r = &ri[index];
31
19
32
if (vms->msi_phandle) {
20
- if (data + data_size * index == 0 || !&rae[i]) {
33
- qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
21
- continue;
34
- vms->msi_phandle);
22
- }
35
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
23
-
36
+ 0, vms->msi_phandle, 0, 0x10000);
24
/* Init the register, this will zero it. */
37
}
25
object_initialize((void *)r, sizeof(*r), TYPE_REGISTER);
38
26
39
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
27
--
40
--
28
2.20.1
41
2.25.1
29
30
diff view generated by jsdifflib
1
In the mtspr helper we attempt to check for "is the timer disabled"
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE
3
is zero and the condition is always false (Coverity complains about
4
the dead code.)
5
2
6
The correct check would be to test whether the TTMR_M field in the
3
The SMMUv3 node isn't expected to have clock properties
7
register is equal to TIMER_NONE instead. However, the
4
(unlike the SMMUv2). Fix the corresponding dt-validate warning:
8
cpu_openrisc_timer_update() function checks whether the timer is
9
enabled (it looks at cpu->env.is_counting, which is set to 0 via
10
cpu_openrisc_count_stop() when the TTMR_M field is set to
11
TIMER_NONE), so there's no need to check for "timer disabled" in the
12
target/openrisc code. Instead, simply remove the dead code.
13
5
14
Fixes: Coverity CID 1005812
6
smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
7
From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
8
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: tweaked commit message as suggested by Eric]
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Acked-by: Stafford Horne <shorne@gmail.com>
17
Message-id: 20201103114654.18540-1-peter.maydell@linaro.org
18
---
15
---
19
target/openrisc/sys_helper.c | 3 ---
16
hw/arm/virt.c | 2 --
20
1 file changed, 3 deletions(-)
17
1 file changed, 2 deletions(-)
21
18
22
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
23
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
24
--- a/target/openrisc/sys_helper.c
21
--- a/hw/arm/virt.c
25
+++ b/target/openrisc/sys_helper.c
22
+++ b/hw/arm/virt.c
26
@@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
23
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
27
24
qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
28
case TO_SPR(10, 1): /* TTCR */
25
sizeof(irq_names));
29
cpu_openrisc_count_set(cpu, rb);
26
30
- if (env->ttmr & TIMER_NONE) {
27
- qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
31
- return;
28
- qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
32
- }
29
qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
33
cpu_openrisc_timer_update(cpu);
30
34
break;
31
qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
35
#endif
36
--
32
--
37
2.20.1
33
2.25.1
38
39
diff view generated by jsdifflib
1
In commit 5edab03d4040 we added tracepoints to the ps2 keyboard
1
From: Jerome Forissier <jerome.forissier@linaro.org>
2
and mouse emulation. However we didn't remove all the debug-by-printf
3
support. In fact there is only one printf() remaining, and it is
4
redundant with the trace_ps2_write_mouse() event next to it.
5
Remove the printf() and the now-unused DEBUG* macros.
6
2
3
SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
4
it with ARM_CP_EL3_NO_EL2_KEEP.
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
8
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
10
Message-id: 20201101133258.4240-1-peter.maydell@linaro.org
11
---
12
---
12
hw/input/ps2.c | 9 ---------
13
target/arm/helper.c | 2 +-
13
1 file changed, 9 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/input/ps2.c
18
--- a/target/arm/helper.c
18
+++ b/hw/input/ps2.c
19
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
20
21
.fieldoffset = offsetof(CPUARMState, sp_el[0]) },
21
#include "trace.h"
22
{ .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
22
23
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
23
-/* debug PC keyboard */
24
- .access = PL2_RW, .type = ARM_CP_ALIAS,
24
-//#define DEBUG_KBD
25
+ .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
25
-
26
.fieldoffset = offsetof(CPUARMState, sp_el[1]) },
26
-/* debug PC keyboard : only mouse */
27
{ .name = "SPSel", .state = ARM_CP_STATE_AA64,
27
-//#define DEBUG_MOUSE
28
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
28
-
29
/* Keyboard Commands */
30
#define KBD_CMD_SET_LEDS    0xED    /* Set keyboard leds */
31
#define KBD_CMD_ECHO     0xEE
32
@@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val)
33
PS2MouseState *s = (PS2MouseState *)opaque;
34
35
trace_ps2_write_mouse(opaque, val);
36
-#ifdef DEBUG_MOUSE
37
- printf("kbd: write mouse 0x%02x\n", val);
38
-#endif
39
switch(s->common.write_cmd) {
40
default:
41
case -1:
42
--
29
--
43
2.20.1
30
2.25.1
44
45
diff view generated by jsdifflib