| 1 | Arm queue; bugfixes only. | 1 | This pullreq has: |
|---|---|---|---|
| 2 | * two arm bug fixes which fix some "Linux fails to boot" bugs | ||
| 3 | * a docs typo-fixing patch | ||
| 4 | * a couple of compile failure/warning issues | ||
| 5 | |||
| 6 | I think they're all pretty safe and worth having in rc3. | ||
| 2 | 7 | ||
| 3 | thanks | 8 | thanks |
| 4 | -- PMM | 9 | -- PMM |
| 5 | 10 | ||
| 6 | The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739: | 11 | The following changes since commit a6b1c53e79d08a99a28cc3e67a3e1a7c34102d6b: |
| 7 | 12 | ||
| 8 | Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000) | 13 | Merge tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-08-10 10:26:57 -0700) |
| 9 | 14 | ||
| 10 | are available in the Git repository at: | 15 | are available in the Git repository at: |
| 11 | 16 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117 | 17 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220812 |
| 13 | 18 | ||
| 14 | for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42: | 19 | for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65: |
| 15 | 20 | ||
| 16 | tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000) | 21 | cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100) |
| 17 | 22 | ||
| 18 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 24 | target-arm queue: |
| 20 | * hw/arm/virt: ARM_VIRT must select ARM_GIC | 25 | * Don't report Statistical Profiling Extension in ID registers |
| 21 | * exynos: Fix bad printf format specifiers | 26 | * virt ACPI tables: Present the GICR structure properly for GICv4 |
| 22 | * hw/input/ps2.c: Remove remnants of printf debug | 27 | * Fix some typos in documentation |
| 23 | * target/openrisc: Remove dead code attempting to check "is timer disabled" | 28 | * tests/unit: fix a -Wformat-truncation warning |
| 24 | * register: Remove unnecessary NULL check | 29 | * cutils: Add missing dyld(3) include on macOS |
| 25 | * util/cutils: Fix Coverity array overrun in freq_to_str() | ||
| 26 | * configure: Make "does libgio work" test pull in some actual functions | ||
| 27 | * tmp105: reset the T_low and T_High registers | ||
| 28 | * tmp105: Correct handling of temperature limit checks | ||
| 29 | 30 | ||
| 30 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
| 31 | Alex Chen (1): | 32 | Marc-André Lureau (1): |
| 32 | exynos: Fix bad printf format specifiers | 33 | tests/unit: fix a -Wformat-truncation warning |
| 33 | 34 | ||
| 34 | Alistair Francis (1): | 35 | Peter Maydell (1): |
| 35 | register: Remove unnecessary NULL check | 36 | target/arm: Don't report Statistical Profiling Extension in ID registers |
| 36 | |||
| 37 | Andrew Jones (1): | ||
| 38 | hw/arm/virt: ARM_VIRT must select ARM_GIC | ||
| 39 | |||
| 40 | Peter Maydell (5): | ||
| 41 | hw/input/ps2.c: Remove remnants of printf debug | ||
| 42 | target/openrisc: Remove dead code attempting to check "is timer disabled" | ||
| 43 | configure: Make "does libgio work" test pull in some actual functions | ||
| 44 | hw/misc/tmp105: reset the T_low and T_High registers | ||
| 45 | tmp105: Correct handling of temperature limit checks | ||
| 46 | 37 | ||
| 47 | Philippe Mathieu-Daudé (1): | 38 | Philippe Mathieu-Daudé (1): |
| 48 | util/cutils: Fix Coverity array overrun in freq_to_str() | 39 | cutils: Add missing dyld(3) include on macOS |
| 49 | 40 | ||
| 50 | configure | 11 +++++-- | 41 | Stefan Weil (1): |
| 51 | hw/misc/tmp105.h | 7 +++++ | 42 | Fix some typos in documentation (most of them found by codespell) |
| 52 | hw/core/register.c | 4 --- | ||
| 53 | hw/input/ps2.c | 9 ------ | ||
| 54 | hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------ | ||
| 55 | hw/timer/exynos4210_mct.c | 4 +-- | ||
| 56 | hw/timer/exynos4210_pwm.c | 8 ++--- | ||
| 57 | target/openrisc/sys_helper.c | 3 -- | ||
| 58 | util/cutils.c | 3 +- | ||
| 59 | hw/arm/Kconfig | 1 + | ||
| 60 | 10 files changed, 89 insertions(+), 34 deletions(-) | ||
| 61 | 43 | ||
| 44 | Zenghui Yu (1): | ||
| 45 | hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4 | ||
| 46 | |||
| 47 | docs/about/deprecated.rst | 2 +- | ||
| 48 | docs/specs/acpi_erst.rst | 4 ++-- | ||
| 49 | docs/system/devices/canokey.rst | 8 ++++---- | ||
| 50 | docs/system/devices/cxl.rst | 12 ++++++------ | ||
| 51 | hw/arm/virt-acpi-build.c | 4 ++-- | ||
| 52 | target/arm/cpu.c | 11 +++++++++++ | ||
| 53 | tests/unit/test-qobject-input-visitor.c | 3 +-- | ||
| 54 | util/cutils.c | 4 ++++ | ||
| 55 | util/oslib-posix.c | 4 ---- | ||
| 56 | 9 files changed, 31 insertions(+), 21 deletions(-) | ||
| 57 | diff view generated by jsdifflib |
| 1 | The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device | 1 | The newly added neoverse-n1 CPU has ID register values which indicate |
|---|---|---|---|
| 2 | signals an alert when the temperature equals or exceeds the T_high value and | 2 | the presence of the Statistical Profiling Extension, because the real |
| 3 | then remains high until a device register is read or the device responds to | 3 | hardware has this feature. QEMU's TCG emulation does not yet |
| 4 | the SMBUS Alert Response address, or the device is put into Shutdown Mode. | 4 | implement SPE, though (not even as a minimal stub implementation), so |
| 5 | Thereafter the Alert pin will only be re-signalled when temperature falls | 5 | guests will crash if they try to use it because the SPE system |
| 6 | below T_low; alert can then be cleared in the same set of ways, and the | 6 | registers don't exist. |
| 7 | device returns to its initial "alert when temperature goes above T_high" | ||
| 8 | mode. (If this textual description is confusing, see figure 3 in the | ||
| 9 | TI datasheet at https://www.ti.com/lit/gpn/tmp105 .) | ||
| 10 | 7 | ||
| 11 | We were misimplementing this as a simple "always alert if temperature is | 8 | Force ID_AA64DFR0_EL1.PMSVer to 0 in CPU realize for TCG, so that |
| 12 | above T_high or below T_low" condition, which gives a spurious alert on | 9 | we don't advertise to the guest a feature that doesn't exist. |
| 13 | startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset | ||
| 14 | limit values. | ||
| 15 | 10 | ||
| 16 | Implement the correct (hysteresis) behaviour by tracking whether we | 11 | (We could alternatively do this by editing the value that |
| 17 | are currently looking for the temperature to rise over T_high or | 12 | aarch64_neoverse_n1_initfn() sets for this ID register, but |
| 18 | for it to fall below T_low. Our implementation of the comparator | 13 | suppressing the field in realize means we won't re-introduce this bug |
| 19 | mode (TM==0) wasn't wrong, but rephrase it to match the way that | 14 | when we add other CPUs that have SPE in hardware, such as the |
| 20 | interrupt mode is now handled for clarity. | 15 | Neoverse-V1.) |
| 21 | 16 | ||
| 17 | An example of a non-booting guest is current mainline Linux (5.19), | ||
| 18 | when booting in EL2 on the virt board (ie with -machine | ||
| 19 | virtualization=on). | ||
| 20 | |||
| 21 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 23 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 23 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 24 | Message-id: 20201110150023.25533-3-peter.maydell@linaro.org | 24 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| 25 | Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 26 | Message-id: 20220811131127.947334-1-peter.maydell@linaro.org | ||
| 25 | --- | 27 | --- |
| 26 | hw/misc/tmp105.h | 7 +++++ | 28 | target/arm/cpu.c | 11 +++++++++++ |
| 27 | hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++------- | 29 | 1 file changed, 11 insertions(+) |
| 28 | 2 files changed, 68 insertions(+), 9 deletions(-) | ||
| 29 | 30 | ||
| 30 | diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h | 31 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
| 31 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
| 32 | --- a/hw/misc/tmp105.h | 33 | --- a/target/arm/cpu.c |
| 33 | +++ b/hw/misc/tmp105.h | 34 | +++ b/target/arm/cpu.c |
| 34 | @@ -XXX,XX +XXX,XX @@ struct TMP105State { | 35 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
| 35 | int16_t limit[2]; | 36 | } |
| 36 | int faults; | ||
| 37 | uint8_t alarm; | ||
| 38 | + /* | ||
| 39 | + * The TMP105 initially looks for a temperature rising above T_high; | ||
| 40 | + * once this is detected, the condition it looks for next is the | ||
| 41 | + * temperature falling below T_low. This flag is false when initially | ||
| 42 | + * looking for T_high, true when looking for T_low. | ||
| 43 | + */ | ||
| 44 | + bool detect_falling; | ||
| 45 | }; | ||
| 46 | |||
| 47 | #endif | 37 | #endif |
| 48 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c | 38 | |
| 49 | index XXXXXXX..XXXXXXX 100644 | 39 | + if (tcg_enabled()) { |
| 50 | --- a/hw/misc/tmp105.c | ||
| 51 | +++ b/hw/misc/tmp105.c | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s) | ||
| 53 | return; | ||
| 54 | } | ||
| 55 | |||
| 56 | - if ((s->config >> 1) & 1) { /* TM */ | ||
| 57 | - if (s->temperature >= s->limit[1]) | ||
| 58 | - s->alarm = 1; | ||
| 59 | - else if (s->temperature < s->limit[0]) | ||
| 60 | - s->alarm = 1; | ||
| 61 | + if (s->config >> 1 & 1) { | ||
| 62 | + /* | 40 | + /* |
| 63 | + * TM == 1 : Interrupt mode. We signal Alert when the | 41 | + * Don't report the Statistical Profiling Extension in the ID |
| 64 | + * temperature rises above T_high, and expect the guest to clear | 42 | + * registers, because TCG doesn't implement it yet (not even a |
| 65 | + * it (eg by reading a device register). | 43 | + * minimal stub version) and guests will fall over when they |
| 44 | + * try to access the non-existent system registers for it. | ||
| 66 | + */ | 45 | + */ |
| 67 | + if (s->detect_falling) { | 46 | + cpu->isar.id_aa64dfr0 = |
| 68 | + if (s->temperature < s->limit[0]) { | 47 | + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); |
| 69 | + s->alarm = 1; | 48 | + } |
| 70 | + s->detect_falling = false; | ||
| 71 | + } | ||
| 72 | + } else { | ||
| 73 | + if (s->temperature >= s->limit[1]) { | ||
| 74 | + s->alarm = 1; | ||
| 75 | + s->detect_falling = true; | ||
| 76 | + } | ||
| 77 | + } | ||
| 78 | } else { | ||
| 79 | - if (s->temperature >= s->limit[1]) | ||
| 80 | - s->alarm = 1; | ||
| 81 | - else if (s->temperature < s->limit[0]) | ||
| 82 | - s->alarm = 0; | ||
| 83 | + /* | ||
| 84 | + * TM == 0 : Comparator mode. We signal Alert when the temperature | ||
| 85 | + * rises above T_high, and stop signalling it when the temperature | ||
| 86 | + * falls below T_low. | ||
| 87 | + */ | ||
| 88 | + if (s->detect_falling) { | ||
| 89 | + if (s->temperature < s->limit[0]) { | ||
| 90 | + s->alarm = 0; | ||
| 91 | + s->detect_falling = false; | ||
| 92 | + } | ||
| 93 | + } else { | ||
| 94 | + if (s->temperature >= s->limit[1]) { | ||
| 95 | + s->alarm = 1; | ||
| 96 | + s->detect_falling = true; | ||
| 97 | + } | ||
| 98 | + } | ||
| 99 | } | ||
| 100 | |||
| 101 | tmp105_interrupt_update(s); | ||
| 102 | @@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id) | ||
| 103 | return 0; | ||
| 104 | } | ||
| 105 | |||
| 106 | +static bool detect_falling_needed(void *opaque) | ||
| 107 | +{ | ||
| 108 | + TMP105State *s = opaque; | ||
| 109 | + | 49 | + |
| 110 | + /* | 50 | /* MPU can be configured out of a PMSA CPU either by setting has-mpu |
| 111 | + * We only need to migrate the detect_falling bool if it's set; | 51 | * to false or by setting pmsav7-dregion to 0. |
| 112 | + * for migration from older machines we assume that it is false | 52 | */ |
| 113 | + * (ie temperature is not out of range). | ||
| 114 | + */ | ||
| 115 | + return s->detect_falling; | ||
| 116 | +} | ||
| 117 | + | ||
| 118 | +static const VMStateDescription vmstate_tmp105_detect_falling = { | ||
| 119 | + .name = "TMP105/detect-falling", | ||
| 120 | + .version_id = 1, | ||
| 121 | + .minimum_version_id = 1, | ||
| 122 | + .needed = detect_falling_needed, | ||
| 123 | + .fields = (VMStateField[]) { | ||
| 124 | + VMSTATE_BOOL(detect_falling, TMP105State), | ||
| 125 | + VMSTATE_END_OF_LIST() | ||
| 126 | + } | ||
| 127 | +}; | ||
| 128 | + | ||
| 129 | static const VMStateDescription vmstate_tmp105 = { | ||
| 130 | .name = "TMP105", | ||
| 131 | .version_id = 0, | ||
| 132 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = { | ||
| 133 | VMSTATE_UINT8(alarm, TMP105State), | ||
| 134 | VMSTATE_I2C_SLAVE(i2c, TMP105State), | ||
| 135 | VMSTATE_END_OF_LIST() | ||
| 136 | + }, | ||
| 137 | + .subsections = (const VMStateDescription*[]) { | ||
| 138 | + &vmstate_tmp105_detect_falling, | ||
| 139 | + NULL | ||
| 140 | } | ||
| 141 | }; | ||
| 142 | |||
| 143 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) | ||
| 144 | s->config = 0; | ||
| 145 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; | ||
| 146 | s->alarm = 0; | ||
| 147 | + s->detect_falling = false; | ||
| 148 | |||
| 149 | s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ | ||
| 150 | s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ | ||
| 151 | -- | 53 | -- |
| 152 | 2.20.1 | 54 | 2.25.1 |
| 153 | 55 | ||
| 154 | 56 | diff view generated by jsdifflib |
| 1 | From: Alex Chen <alex.chen@huawei.com> | 1 | From: Stefan Weil <sw@weilnetz.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | We should use printf format specifier "%u" instead of "%d" for | 3 | Signed-off-by: Stefan Weil <sw@weilnetz.de> |
| 4 | argument of type "unsigned int". | 4 | Reviewed-by: Hongren (Zenithal) Zheng <i@zenithal.me> |
| 5 | 5 | Message-id: 20220812075642.1200578-1-sw@weilnetz.de | |
| 6 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
| 7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | ||
| 8 | Message-id: 20201111073651.72804-1-alex.chen@huawei.com | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 8 | --- |
| 12 | hw/timer/exynos4210_mct.c | 4 ++-- | 9 | docs/about/deprecated.rst | 2 +- |
| 13 | hw/timer/exynos4210_pwm.c | 8 ++++---- | 10 | docs/specs/acpi_erst.rst | 4 ++-- |
| 14 | 2 files changed, 6 insertions(+), 6 deletions(-) | 11 | docs/system/devices/canokey.rst | 8 ++++---- |
| 12 | docs/system/devices/cxl.rst | 12 ++++++------ | ||
| 13 | 4 files changed, 13 insertions(+), 13 deletions(-) | ||
| 15 | 14 | ||
| 16 | diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c | 15 | diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst |
| 17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/hw/timer/exynos4210_mct.c | 17 | --- a/docs/about/deprecated.rst |
| 19 | +++ b/hw/timer/exynos4210_mct.c | 18 | +++ b/docs/about/deprecated.rst |
| 20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id) | 19 | @@ -XXX,XX +XXX,XX @@ by using ``-machine graphics=off``. |
| 21 | /* If CSTAT is pending and IRQ is enabled */ | 20 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 22 | if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) && | 21 | |
| 23 | (s->reg.int_enb & G_INT_ENABLE(id))) { | 22 | In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64 |
| 24 | - DPRINTF("gcmp timer[%d] IRQ\n", id); | 23 | -identifer that is not globally unique. If an EUI-64 identifer is required, the |
| 25 | + DPRINTF("gcmp timer[%u] IRQ\n", id); | 24 | +identifier that is not globally unique. If an EUI-64 identifier is required, the |
| 26 | qemu_irq_raise(s->irq[id]); | 25 | user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``. |
| 27 | } | 26 | |
| 28 | } | 27 | ``-device nvme,use-intel-id=on|off`` (since 7.1) |
| 29 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s) | 28 | diff --git a/docs/specs/acpi_erst.rst b/docs/specs/acpi_erst.rst |
| 30 | MCT_CFG_GET_DIVIDER(s->reg_mct_cfg)); | ||
| 31 | |||
| 32 | if (freq != s->freq) { | ||
| 33 | - DPRINTF("freq=%dHz\n", s->freq); | ||
| 34 | + DPRINTF("freq=%uHz\n", s->freq); | ||
| 35 | |||
| 36 | /* global timer */ | ||
| 37 | tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq); | ||
| 38 | diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
| 40 | --- a/hw/timer/exynos4210_pwm.c | 30 | --- a/docs/specs/acpi_erst.rst |
| 41 | +++ b/hw/timer/exynos4210_pwm.c | 31 | +++ b/docs/specs/acpi_erst.rst |
| 42 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) | 32 | @@ -XXX,XX +XXX,XX @@ Slot 0 contains a backend storage header that identifies the contents |
| 43 | 33 | as ERST and also facilitates efficient access to the records. | |
| 44 | if (freq != s->timer[id].freq) { | 34 | Depending upon the size of the backend storage, additional slots will |
| 45 | ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); | 35 | be designated to be a part of the slot 0 header. For example, at 8KiB, |
| 46 | - DPRINTF("freq=%dHz\n", s->timer[id].freq); | 36 | -the slot 0 header can accomodate 1021 records. Thus a storage size |
| 47 | + DPRINTF("freq=%uHz\n", s->timer[id].freq); | 37 | +the slot 0 header can accommodate 1021 records. Thus a storage size |
| 48 | } | 38 | of 8MiB (8KiB * 1024) requires an additional slot for use by the |
| 49 | } | 39 | header. In this scenario, slot 0 and slot 1 form the backend storage |
| 50 | 40 | header, and records can be stored starting at slot 2. | |
| 51 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) | 41 | @@ -XXX,XX +XXX,XX @@ References |
| 52 | uint32_t id = s->id; | 42 | [2] "Unified Extensible Firmware Interface Specification", |
| 53 | bool cmp; | 43 | version 2.1, October 2008. |
| 54 | 44 | ||
| 55 | - DPRINTF("timer %d tick\n", id); | 45 | -[3] "Windows Hardware Error Architecture", specfically |
| 56 | + DPRINTF("timer %u tick\n", id); | 46 | +[3] "Windows Hardware Error Architecture", specifically |
| 57 | 47 | "Error Record Persistence Mechanism". | |
| 58 | /* set irq status */ | 48 | diff --git a/docs/system/devices/canokey.rst b/docs/system/devices/canokey.rst |
| 59 | p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); | 49 | index XXXXXXX..XXXXXXX 100644 |
| 60 | 50 | --- a/docs/system/devices/canokey.rst | |
| 61 | /* raise IRQ */ | 51 | +++ b/docs/system/devices/canokey.rst |
| 62 | if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { | 52 | @@ -XXX,XX +XXX,XX @@ With the same software configuration as a hardware key, |
| 63 | - DPRINTF("timer %d IRQ\n", id); | 53 | the guest OS can use all the functionalities of a secure key as if |
| 64 | + DPRINTF("timer %u IRQ\n", id); | 54 | there was actually an hardware key plugged in. |
| 65 | qemu_irq_raise(p->timer[id].irq); | 55 | |
| 66 | } | 56 | -CanoKey QEMU provides much convenience for debuging: |
| 67 | 57 | +CanoKey QEMU provides much convenience for debugging: | |
| 68 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque) | 58 | |
| 69 | } | 59 | -* libcanokey-qemu supports debuging output thus developers can |
| 70 | 60 | +* libcanokey-qemu supports debugging output thus developers can | |
| 71 | if (cmp) { | 61 | inspect what happens inside a secure key |
| 72 | - DPRINTF("auto reload timer %d count to %x\n", id, | 62 | * CanoKey QEMU supports trace event thus event |
| 73 | + DPRINTF("auto reload timer %u count to %x\n", id, | 63 | * QEMU USB stack supports pcap thus USB packet between the guest |
| 74 | p->timer[id].reg_tcntb); | 64 | @@ -XXX,XX +XXX,XX @@ and find CanoKey QEMU there: |
| 75 | ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); | 65 | |
| 76 | ptimer_run(p->timer[id].ptimer, 1); | 66 | You may setup the key as guided in [6]_. The console for the key is at [7]_. |
| 67 | |||
| 68 | -Debuging | ||
| 69 | -======== | ||
| 70 | +Debugging | ||
| 71 | +========= | ||
| 72 | |||
| 73 | CanoKey QEMU consists of two parts, ``libcanokey-qemu.so`` and ``canokey.c``, | ||
| 74 | the latter of which resides in QEMU. The former provides core functionality | ||
| 75 | diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst | ||
| 76 | index XXXXXXX..XXXXXXX 100644 | ||
| 77 | --- a/docs/system/devices/cxl.rst | ||
| 78 | +++ b/docs/system/devices/cxl.rst | ||
| 79 | @@ -XXX,XX +XXX,XX @@ CXL Fixed Memory Windows (CFMW) | ||
| 80 | A CFMW consists of a particular range of Host Physical Address space | ||
| 81 | which is routed to particular CXL Host Bridges. At time of generic | ||
| 82 | software initialization it will have a particularly interleaving | ||
| 83 | -configuration and associated Quality of Serice Throtling Group (QTG). | ||
| 84 | +configuration and associated Quality of Service Throttling Group (QTG). | ||
| 85 | This information is available to system software, when making | ||
| 86 | decisions about how to configure interleave across available CXL | ||
| 87 | memory devices. It is provide as CFMW Structures (CFMWS) in | ||
| 88 | @@ -XXX,XX +XXX,XX @@ specification defined register interface called CXL Host Bridge | ||
| 89 | Component Registers (CHBCR). The location of this CHBCR MMIO | ||
| 90 | space is described to system software via a CXL Host Bridge | ||
| 91 | Structure (CHBS) in the CEDT ACPI table. The actual interfaces | ||
| 92 | -are identical to those used for other parts of the CXL heirarchy | ||
| 93 | +are identical to those used for other parts of the CXL hierarchy | ||
| 94 | as CXL Component Registers in PCI BARs. | ||
| 95 | |||
| 96 | Interfaces provided include: | ||
| 97 | @@ -XXX,XX +XXX,XX @@ CXL Memory Devices - Type 3 | ||
| 98 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
| 99 | CXL type 3 devices use a PCI class code and are intended to be supported | ||
| 100 | by a generic operating system driver. They have HDM decoders | ||
| 101 | -though in these EP devices, the decoder is reponsible not for | ||
| 102 | +though in these EP devices, the decoder is responsible not for | ||
| 103 | routing but for translation of the incoming host physical address (HPA) | ||
| 104 | into a Device Physical Address (DPA). | ||
| 105 | |||
| 106 | @@ -XXX,XX +XXX,XX @@ Notes: | ||
| 107 | ranges of the system physical address map. Each CFMW has | ||
| 108 | particular interleave setup across the CXL Host Bridges (HB) | ||
| 109 | CFMW0 provides uninterleaved access to HB0, CFW2 provides | ||
| 110 | - uninterleaved acess to HB1. CFW1 provides interleaved memory access | ||
| 111 | + uninterleaved access to HB1. CFW1 provides interleaved memory access | ||
| 112 | across HB0 and HB1. | ||
| 113 | |||
| 114 | (2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and | ||
| 115 | @@ -XXX,XX +XXX,XX @@ Example topology involving a switch:: | ||
| 116 | --------------------------------------------------- | ||
| 117 | | Switch 0 USP as PCI 0d:00.0 | | ||
| 118 | | USP has HDM decoder which direct traffic to | | ||
| 119 | - | appropiate downstream port | | ||
| 120 | + | appropriate downstream port | | ||
| 121 | | Switch BUS appears as 0e | | ||
| 122 | |x__________________________________________________| | ||
| 123 | | | | | | ||
| 124 | @@ -XXX,XX +XXX,XX @@ An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:: | ||
| 125 | Kernel Configuration Options | ||
| 126 | ---------------------------- | ||
| 127 | |||
| 128 | -In Linux 5.18 the followings options are necessary to make use of | ||
| 129 | +In Linux 5.18 the following options are necessary to make use of | ||
| 130 | OS management of CXL memory devices as described here. | ||
| 131 | |||
| 132 | * CONFIG_CXL_BUS | ||
| 77 | -- | 133 | -- |
| 78 | 2.20.1 | 134 | 2.25.1 |
| 79 | |||
| 80 | diff view generated by jsdifflib |
| 1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Marc-André Lureau <marcandre.lureau@redhat.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The removal of the selection of A15MPCORE from ARM_VIRT also | 3 | ../tests/test-qobject-input-visitor.c: In function ‘test_visitor_in_list’: |
| 4 | removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC. | 4 | ../tests/test-qobject-input-visitor.c:454:49: warning: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size 6 [-Wformat-truncation=] |
| 5 | 454 | snprintf(string, sizeof(string), "string%d", i); | ||
| 6 | | ^~ | ||
| 7 | ../tests/test-qobject-input-visitor.c:454:42: note: directive argument in the range [0, 2147483606] | ||
| 8 | 454 | snprintf(string, sizeof(string), "string%d", i); | ||
| 9 | | ^~~~~~~~~~ | ||
| 10 | ../tests/test-qobject-input-visitor.c:454:9: note: ‘snprintf’ output between 8 and 17 bytes into a destination of size 12 | ||
| 11 | 454 | snprintf(string, sizeof(string), "string%d", i); | ||
| 12 | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
| 5 | 13 | ||
| 6 | Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals") | 14 | Rather than trying to be clever, since this is called 3 times during |
| 7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> | 15 | tests, let's simply use g_strdup_printf(). |
| 8 | Signed-off-by: Andrew Jones <drjones@redhat.com> | 16 | |
| 9 | Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com> | 17 | Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
| 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 18 | Reviewed-by: Markus Armbruster <armbru@redhat.com> |
| 11 | Message-id: 20201111143440.112763-1-drjones@redhat.com | 19 | Message-id: 20220810121513.1356081-1-marcandre.lureau@redhat.com |
| 20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 21 | [PMM: fixed commit message typos] | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | --- | 23 | --- |
| 14 | hw/arm/Kconfig | 1 + | 24 | tests/unit/test-qobject-input-visitor.c | 3 +-- |
| 15 | 1 file changed, 1 insertion(+) | 25 | 1 file changed, 1 insertion(+), 2 deletions(-) |
| 16 | 26 | ||
| 17 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 27 | diff --git a/tests/unit/test-qobject-input-visitor.c b/tests/unit/test-qobject-input-visitor.c |
| 18 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/hw/arm/Kconfig | 29 | --- a/tests/unit/test-qobject-input-visitor.c |
| 20 | +++ b/hw/arm/Kconfig | 30 | +++ b/tests/unit/test-qobject-input-visitor.c |
| 21 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT | 31 | @@ -XXX,XX +XXX,XX @@ static void test_visitor_in_list(TestInputVisitorData *data, |
| 22 | imply VFIO_PLATFORM | 32 | g_assert(head != NULL); |
| 23 | imply VFIO_XGMAC | 33 | |
| 24 | imply TPM_TIS_SYSBUS | 34 | for (i = 0, item = head; item; item = item->next, i++) { |
| 25 | + select ARM_GIC | 35 | - char string[12]; |
| 26 | select ACPI | 36 | + g_autofree char *string = g_strdup_printf("string%d", i); |
| 27 | select ARM_SMMUV3 | 37 | |
| 28 | select GPIO_KEY | 38 | - snprintf(string, sizeof(string), "string%d", i); |
| 39 | g_assert_cmpstr(item->value->string, ==, string); | ||
| 40 | g_assert_cmpint(item->value->integer, ==, 42 + i); | ||
| 41 | } | ||
| 29 | -- | 42 | -- |
| 30 | 2.20.1 | 43 | 2.25.1 |
| 31 | 44 | ||
| 32 | 45 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In commit 5edab03d4040 we added tracepoints to the ps2 keyboard | ||
| 2 | and mouse emulation. However we didn't remove all the debug-by-printf | ||
| 3 | support. In fact there is only one printf() remaining, and it is | ||
| 4 | redundant with the trace_ps2_write_mouse() event next to it. | ||
| 5 | Remove the printf() and the now-unused DEBUG* macros. | ||
| 6 | 1 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 9 | Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> | ||
| 10 | Message-id: 20201101133258.4240-1-peter.maydell@linaro.org | ||
| 11 | --- | ||
| 12 | hw/input/ps2.c | 9 --------- | ||
| 13 | 1 file changed, 9 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/hw/input/ps2.c b/hw/input/ps2.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/input/ps2.c | ||
| 18 | +++ b/hw/input/ps2.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ | ||
| 20 | |||
| 21 | #include "trace.h" | ||
| 22 | |||
| 23 | -/* debug PC keyboard */ | ||
| 24 | -//#define DEBUG_KBD | ||
| 25 | - | ||
| 26 | -/* debug PC keyboard : only mouse */ | ||
| 27 | -//#define DEBUG_MOUSE | ||
| 28 | - | ||
| 29 | /* Keyboard Commands */ | ||
| 30 | #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */ | ||
| 31 | #define KBD_CMD_ECHO 0xEE | ||
| 32 | @@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val) | ||
| 33 | PS2MouseState *s = (PS2MouseState *)opaque; | ||
| 34 | |||
| 35 | trace_ps2_write_mouse(opaque, val); | ||
| 36 | -#ifdef DEBUG_MOUSE | ||
| 37 | - printf("kbd: write mouse 0x%02x\n", val); | ||
| 38 | -#endif | ||
| 39 | switch(s->common.write_cmd) { | ||
| 40 | default: | ||
| 41 | case -1: | ||
| 42 | -- | ||
| 43 | 2.20.1 | ||
| 44 | |||
| 45 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In the mtspr helper we attempt to check for "is the timer disabled" | ||
| 2 | with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE | ||
| 3 | is zero and the condition is always false (Coverity complains about | ||
| 4 | the dead code.) | ||
| 5 | 1 | ||
| 6 | The correct check would be to test whether the TTMR_M field in the | ||
| 7 | register is equal to TIMER_NONE instead. However, the | ||
| 8 | cpu_openrisc_timer_update() function checks whether the timer is | ||
| 9 | enabled (it looks at cpu->env.is_counting, which is set to 0 via | ||
| 10 | cpu_openrisc_count_stop() when the TTMR_M field is set to | ||
| 11 | TIMER_NONE), so there's no need to check for "timer disabled" in the | ||
| 12 | target/openrisc code. Instead, simply remove the dead code. | ||
| 13 | |||
| 14 | Fixes: Coverity CID 1005812 | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | Acked-by: Stafford Horne <shorne@gmail.com> | ||
| 17 | Message-id: 20201103114654.18540-1-peter.maydell@linaro.org | ||
| 18 | --- | ||
| 19 | target/openrisc/sys_helper.c | 3 --- | ||
| 20 | 1 file changed, 3 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/target/openrisc/sys_helper.c | ||
| 25 | +++ b/target/openrisc/sys_helper.c | ||
| 26 | @@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) | ||
| 27 | |||
| 28 | case TO_SPR(10, 1): /* TTCR */ | ||
| 29 | cpu_openrisc_count_set(cpu, rb); | ||
| 30 | - if (env->ttmr & TIMER_NONE) { | ||
| 31 | - return; | ||
| 32 | - } | ||
| 33 | cpu_openrisc_timer_update(cpu); | ||
| 34 | break; | ||
| 35 | #endif | ||
| 36 | -- | ||
| 37 | 2.20.1 | ||
| 38 | |||
| 39 | diff view generated by jsdifflib |
| 1 | From: Alistair Francis <alistair.francis@wdc.com> | 1 | From: Zenghui Yu <yuzenghui@huawei.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | This patch fixes CID 1432800 by removing an unnecessary check. | 3 | With the introduction of the new TCG GICv4, build_madt() is badly broken |
| 4 | as we do not present any GIC Redistributor structure in MADT for GICv4 | ||
| 5 | guests, so that they have no idea about where the Redistributor | ||
| 6 | register frames are. This fixes a Linux guest crash at boot time with | ||
| 7 | ACPI enabled and '-machine gic-version=4'. | ||
| 4 | 8 | ||
| 5 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 9 | While at it, let's convert the remaining hard coded gic_version into |
| 10 | enumeration VIRT_GIC_VERSION_2 for consistency. | ||
| 11 | |||
| 12 | Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> | ||
| 13 | Message-id: 20220812022018.1069-1-yuzenghui@huawei.com | ||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | --- | 16 | --- |
| 9 | hw/core/register.c | 4 ---- | 17 | hw/arm/virt-acpi-build.c | 4 ++-- |
| 10 | 1 file changed, 4 deletions(-) | 18 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 11 | 19 | ||
| 12 | diff --git a/hw/core/register.c b/hw/core/register.c | 20 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c |
| 13 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/hw/core/register.c | 22 | --- a/hw/arm/virt-acpi-build.c |
| 15 | +++ b/hw/core/register.c | 23 | +++ b/hw/arm/virt-acpi-build.c |
| 16 | @@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner, | 24 | @@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
| 17 | int index = rae[i].addr / data_size; | 25 | uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ? |
| 18 | RegisterInfo *r = &ri[index]; | 26 | PPI(VIRTUAL_PMU_IRQ) : 0; |
| 19 | 27 | ||
| 20 | - if (data + data_size * index == 0 || !&rae[i]) { | 28 | - if (vms->gic_version == 2) { |
| 21 | - continue; | 29 | + if (vms->gic_version == VIRT_GIC_VERSION_2) { |
| 22 | - } | 30 | physical_base_address = memmap[VIRT_GIC_CPU].base; |
| 23 | - | 31 | gicv = memmap[VIRT_GIC_VCPU].base; |
| 24 | /* Init the register, this will zero it. */ | 32 | gich = memmap[VIRT_GIC_HYP].base; |
| 25 | object_initialize((void *)r, sizeof(*r), TYPE_REGISTER); | 33 | @@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
| 26 | 34 | build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); | |
| 35 | } | ||
| 36 | |||
| 37 | - if (vms->gic_version == 3) { | ||
| 38 | + if (vms->gic_version != VIRT_GIC_VERSION_2) { | ||
| 39 | build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base, | ||
| 40 | memmap[VIRT_GIC_REDIST].size); | ||
| 41 | if (virt_gicv3_redist_region_count(vms) == 2) { | ||
| 27 | -- | 42 | -- |
| 28 | 2.20.1 | 43 | 2.25.1 |
| 29 | |||
| 30 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN): | 3 | Commit 06680b15b4 moved qemu_*_exec_dir() to cutils but forgot |
| 4 | to move the macOS dyld(3) include, resulting in the following | ||
| 5 | error (when building with Homebrew GCC on macOS Monterey 12.4): | ||
| 4 | 6 | ||
| 5 | >>> Overrunning array "suffixes" of 7 8-byte elements at element | 7 | [313/1197] Compiling C object libqemuutil.a.p/util_cutils.c.o |
| 6 | index 7 (byte offset 63) using index "idx" (which evaluates to 7). | 8 | FAILED: libqemuutil.a.p/util_cutils.c.o |
| 9 | ../../util/cutils.c:1039:13: error: implicit declaration of function '_NSGetExecutablePath' [-Werror=implicit-function-declaration] | ||
| 10 | 1039 | if (_NSGetExecutablePath(fpath, &len) == 0) { | ||
| 11 | | ^~~~~~~~~~~~~~~~~~~~ | ||
| 12 | ../../util/cutils.c:1039:13: error: nested extern declaration of '_NSGetExecutablePath' [-Werror=nested-externs] | ||
| 7 | 13 | ||
| 8 | Note, the biggest input value freq_to_str() can accept is UINT64_MAX, | 14 | Fix by moving the include line to cutils. |
| 9 | which is ~18.446 EHz, less than 1000 EHz. | ||
| 10 | 15 | ||
| 11 | Reported-by: Eduardo Habkost <ehabkost@redhat.com> | 16 | Fixes: 06680b15b4 ("include: move qemu_*_exec_dir() to cutils") |
| 12 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 17 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| 18 | Message-id: 20220809222046.30812-1-f4bug@amsat.org | ||
| 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> | ||
| 15 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
| 16 | Message-id: 20201101215755.2021421-1-f4bug@amsat.org | ||
| 17 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 20 | --- | 21 | --- |
| 21 | util/cutils.c | 3 ++- | 22 | util/cutils.c | 4 ++++ |
| 22 | 1 file changed, 2 insertions(+), 1 deletion(-) | 23 | util/oslib-posix.c | 4 ---- |
| 24 | 2 files changed, 4 insertions(+), 4 deletions(-) | ||
| 23 | 25 | ||
| 24 | diff --git a/util/cutils.c b/util/cutils.c | 26 | diff --git a/util/cutils.c b/util/cutils.c |
| 25 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
| 26 | --- a/util/cutils.c | 28 | --- a/util/cutils.c |
| 27 | +++ b/util/cutils.c | 29 | +++ b/util/cutils.c |
| 28 | @@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz) | 30 | @@ -XXX,XX +XXX,XX @@ |
| 29 | double freq = freq_hz; | 31 | #include <kernel/image.h> |
| 30 | size_t idx = 0; | 32 | #endif |
| 31 | 33 | ||
| 32 | - while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) { | 34 | +#ifdef __APPLE__ |
| 33 | + while (freq >= 1000.0) { | 35 | +#include <mach-o/dyld.h> |
| 34 | freq /= 1000.0; | 36 | +#endif |
| 35 | idx++; | 37 | + |
| 36 | } | 38 | #ifdef G_OS_WIN32 |
| 37 | + assert(idx < ARRAY_SIZE(suffixes)); | 39 | #include <pathcch.h> |
| 38 | 40 | #include <wchar.h> | |
| 39 | return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]); | 41 | diff --git a/util/oslib-posix.c b/util/oslib-posix.c |
| 40 | } | 42 | index XXXXXXX..XXXXXXX 100644 |
| 43 | --- a/util/oslib-posix.c | ||
| 44 | +++ b/util/oslib-posix.c | ||
| 45 | @@ -XXX,XX +XXX,XX @@ | ||
| 46 | #include <lwp.h> | ||
| 47 | #endif | ||
| 48 | |||
| 49 | -#ifdef __APPLE__ | ||
| 50 | -#include <mach-o/dyld.h> | ||
| 51 | -#endif | ||
| 52 | - | ||
| 53 | #include "qemu/mmap-alloc.h" | ||
| 54 | |||
| 55 | #ifdef CONFIG_DEBUG_STACK_USAGE | ||
| 41 | -- | 56 | -- |
| 42 | 2.20.1 | 57 | 2.25.1 |
| 43 | 58 | ||
| 44 | 59 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In commit 76346b6264a9b01979 we tried to add a configure check that | ||
| 2 | the libgio pkg-config data was correct, which builds an executable | ||
| 3 | linked against it. Unfortunately this doesn't catch the problem | ||
| 4 | (missing static library dependency info), because a "do nothing" test | ||
| 5 | source file doesn't have any symbol references that cause the linker | ||
| 6 | to pull in .o files from libgio.a, and so we don't see the "missing | ||
| 7 | symbols from libmount" error that a full QEMU link triggers. | ||
| 8 | 1 | ||
| 9 | (The ineffective test went unnoticed because of a typo that | ||
| 10 | effectively disabled libgio unconditionally, but after commit | ||
| 11 | 3569a5dfc11f2 fixed that, a static link of the system emulator on | ||
| 12 | Ubuntu stopped working again.) | ||
| 13 | |||
| 14 | Improve the gio test by having the test source fragment reference a | ||
| 15 | g_dbus function (which is what is indirectly causing us to end up | ||
| 16 | wanting functions from libmount). | ||
| 17 | |||
| 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 19 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
| 20 | Message-id: 20201116104617.18333-1-peter.maydell@linaro.org | ||
| 21 | --- | ||
| 22 | configure | 11 +++++++++-- | ||
| 23 | 1 file changed, 9 insertions(+), 2 deletions(-) | ||
| 24 | |||
| 25 | diff --git a/configure b/configure | ||
| 26 | index XXXXXXX..XXXXXXX 100755 | ||
| 27 | --- a/configure | ||
| 28 | +++ b/configure | ||
| 29 | @@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then | ||
| 30 | # Check that the libraries actually work -- Ubuntu 18.04 ships | ||
| 31 | # with pkg-config --static --libs data for gio-2.0 that is missing | ||
| 32 | # -lblkid and will give a link error. | ||
| 33 | - write_c_skeleton | ||
| 34 | - if compile_prog "" "$gio_libs" ; then | ||
| 35 | + cat > $TMPC <<EOF | ||
| 36 | +#include <gio/gio.h> | ||
| 37 | +int main(void) | ||
| 38 | +{ | ||
| 39 | + g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0); | ||
| 40 | + return 0; | ||
| 41 | +} | ||
| 42 | +EOF | ||
| 43 | + if compile_prog "$gio_cflags" "$gio_libs" ; then | ||
| 44 | gio=yes | ||
| 45 | else | ||
| 46 | gio=no | ||
| 47 | -- | ||
| 48 | 2.20.1 | ||
| 49 | |||
| 50 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the | ||
| 2 | power-up reset values for the T_low and T_high registers are 80 degrees C | ||
| 3 | and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These | ||
| 4 | values are then shifted right by four bits to give the register reset | ||
| 5 | values, since both registers store the 12 bits of temperature data in bits | ||
| 6 | [15..4] of a 16 bit register. | ||
| 7 | 1 | ||
| 8 | We were resetting these registers to zero, which is problematic for Linux | ||
| 9 | guests which enable the alert interrupt and then immediately take an | ||
| 10 | unexpected overtemperature alert because the current temperature is above | ||
| 11 | freezing... | ||
| 12 | |||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
| 15 | Message-id: 20201110150023.25533-2-peter.maydell@linaro.org | ||
| 16 | --- | ||
| 17 | hw/misc/tmp105.c | 3 +++ | ||
| 18 | 1 file changed, 3 insertions(+) | ||
| 19 | |||
| 20 | diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/hw/misc/tmp105.c | ||
| 23 | +++ b/hw/misc/tmp105.c | ||
| 24 | @@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c) | ||
| 25 | s->faults = tmp105_faultq[(s->config >> 3) & 3]; | ||
| 26 | s->alarm = 0; | ||
| 27 | |||
| 28 | + s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */ | ||
| 29 | + s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */ | ||
| 30 | + | ||
| 31 | tmp105_interrupt_update(s); | ||
| 32 | } | ||
| 33 | |||
| 34 | -- | ||
| 35 | 2.20.1 | ||
| 36 | |||
| 37 | diff view generated by jsdifflib |