Series comparison

-[PULL 0/9] target-arm queue
+[PULL 00/28] target-arm queue
-Arm queue; bugfixes only.
+Just flushing my target-arm queue since I won't be working next week :-)
-thanks
 -- PMM
-The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739:
+The following changes since commit b3cd3b5a66f0dddfe3d5ba2bef13cd4f5b89cde9:
-  Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000)
+  Merge tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu into staging (2022-06-09 22:08:27 -0700)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220610
-for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42:
+for you to fetch changes up to 90c072e063737e9e8f431489bbd334452f89056e:
-  tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000)
+  semihosting/config: Merge --semihosting-config option groups (2022-06-10 14:32:36 +0100)
 ----------------------------------------------------------------
-target-arm queue:
+ * refactor exception routing code
- * hw/arm/virt: ARM_VIRT must select ARM_GIC
+ * fix SCR_EL3 RAO/RAZ bits
- * exynos: Fix bad printf format specifiers
+ * gdbstub: Don't use GDB syscalls if no GDB is attached
- * hw/input/ps2.c: Remove remnants of printf debug
+ * semihosting/config: Merge --semihosting-config option groups
- * target/openrisc: Remove dead code attempting to check "is timer disabled"
+ * tests/qtest: Reduce npcm7xx_sdhci test image size
  * register: Remove unnecessary NULL check
  * util/cutils: Fix Coverity array overrun in freq_to_str()
  * configure: Make "does libgio work" test pull in some actual functions
  * tmp105: reset the T_low and T_High registers
  * tmp105: Correct handling of temperature limit checks
 ----------------------------------------------------------------
-Alex Chen (1):
+Hao Wu (1):
-      exynos: Fix bad printf format specifiers
+      tests/qtest: Reduce npcm7xx_sdhci test image size
-Alistair Francis (1):
+Peter Maydell (2):
-      register: Remove unnecessary NULL check
+      gdbstub: Don't use GDB syscalls if no GDB is attached
       semihosting/config: Merge --semihosting-config option groups
-Andrew Jones (1):
+Richard Henderson (25):
-      hw/arm/virt: ARM_VIRT must select ARM_GIC
+      target/arm: Mark exception helpers as noreturn
       target/arm: Add coproc parameter to syn_fp_access_trap
       target/arm: Move exception_target_el out of line
       target/arm: Move arm_singlestep_active out of line
       target/arm: Move arm_generate_debug_exceptions out of line
       target/arm: Use is_a64 in arm_generate_debug_exceptions
       target/arm: Move exception_bkpt_insn to debug_helper.c
       target/arm: Move arm_debug_exception_fsr to debug_helper.c
       target/arm: Rename helper_exception_with_syndrome
       target/arm: Introduce gen_exception_insn_el_v
       target/arm: Rename gen_exception_insn to gen_exception_insn_el
       target/arm: Introduce gen_exception_insn
       target/arm: Create helper_exception_swstep
       target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL
       target/arm: Move gen_exception to translate.c
       target/arm: Rename gen_exception to gen_exception_el
       target/arm: Introduce gen_exception
       target/arm: Introduce gen_exception_el_v
       target/arm: Introduce helper_exception_with_syndrome
       target/arm: Remove default_exception_el
       target/arm: Create raise_exception_debug
       target/arm: Move arm_debug_target_el to debug_helper.c
       target/arm: Fix Secure PL1 tests in fp_exception_el
       target/arm: Adjust format test in scr_write
       target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]
-Peter Maydell (5):
+ target/arm/cpu.h                 | 133 ++---------------------
-      hw/input/ps2.c: Remove remnants of printf debug
+ target/arm/helper.h              |   8 +-
-      target/openrisc: Remove dead code attempting to check "is timer disabled"
+ target/arm/internals.h           |  43 +-------
-      configure: Make "does libgio work" test pull in some actual functions
+ target/arm/syndrome.h            |   7 +-
-      hw/misc/tmp105: reset the T_low and T_High registers
+ target/arm/translate.h           |  43 ++------
-      tmp105: Correct handling of temperature limit checks
+ gdbstub.c                        |  14 ++-
+ semihosting/config.c             |   1 +
-Philippe Mathieu-Daudé (1):
+ target/arm/debug_helper.c        | 220 +++++++++++++++++++++++++++++++++++++--
-      util/cutils: Fix Coverity array overrun in freq_to_str()
+ target/arm/helper.c              |  53 ++++------
+ target/arm/op_helper.c           |  52 +++++----
- configure                    | 11 +++++--
+ target/arm/translate-a64.c       |  34 +++---
- hw/misc/tmp105.h             |  7 +++++
+ target/arm/translate-m-nocp.c    |  15 ++-
- hw/core/register.c           |  4 ---
+ target/arm/translate-mve.c       |   3 +-
- hw/input/ps2.c               |  9 ------
+ target/arm/translate-vfp.c       |  18 +++-
- hw/misc/tmp105.c             | 73 ++++++++++++++++++++++++++++++++++++++------
+ target/arm/translate.c           | 106 ++++++++++---------
- hw/timer/exynos4210_mct.c    |  4 +--
+ tests/qtest/npcm7xx_sdhci-test.c |   2 +-
- hw/timer/exynos4210_pwm.c    |  8 ++---
+files changed, 390 insertions(+), 362 deletions(-)
  target/openrisc/sys_helper.c |  3 --
  util/cutils.c                |  3 +-
  hw/arm/Kconfig               |  1 +
 files changed, 89 insertions(+), 34 deletions(-)

-New patch
+[PULL 01/28] target/arm: Mark exception helpers as noreturn
+From: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-2-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.h | 6 +++---
+file changed, 3 insertions(+), 3 deletions(-)
+diff --git a/target/arm/helper.h b/target/arm/helper.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.h
++++ b/target/arm/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
+                    i32, i32, i32, i32)
+-DEF_HELPER_2(exception_internal, void, env, i32)
+-DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
+-DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
++DEF_HELPER_2(exception_internal, noreturn, env, i32)
++DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32)
++DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32)
+ DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
+ DEF_HELPER_1(setend, void, env)
+ DEF_HELPER_2(wfi, void, env, i32)
+--
+.25.1

-New patch
+[PULL 02/28] target/arm: Add coproc parameter to syn_fp_access_trap
+From: Richard Henderson <richard.henderson@linaro.org>
+With ARMv8, this field is always RES0.
+With ARMv7, targeting EL2 and TA=0, it is always 0xA.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-3-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/syndrome.h      |  7 ++++---
+ target/arm/translate-a64.c |  3 ++-
+ target/arm/translate-vfp.c | 14 ++++++++++++--
+files changed, 18 insertions(+), 6 deletions(-)
+diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/syndrome.h
++++ b/target/arm/syndrome.h
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
+         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
+ }
+-static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
++static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,
++                                          int coproc)
+ {
+-    /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */
++    /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */
+     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
+         | (is_16bit ? 0 : ARM_EL_IL)
+-        | (cv << 24) | (cond << 20) | 0xa;
++        | (cv << 24) | (cond << 20) | coproc;
+ }
+ static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-a64.c
++++ b/target/arm/translate-a64.c
+@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
+         s->fp_access_checked = true;
+         gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+-                           syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
++                           syn_fp_access_trap(1, 0xe, false, 0),
++                           s->fp_excp_el);
+         return false;
+     }
+     s->fp_access_checked = true;
+diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-vfp.c
++++ b/target/arm/translate-vfp.c
+@@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s)
+ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
+ {
+     if (s->fp_excp_el) {
+-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+-                           syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
++        /*
++         * The full syndrome is only used for HSR when HCPTR traps:
++         * For v8, when TA==0, coproc is RES0.
++         * For v7, any use of a Floating-point instruction or access
++         * to a Floating-point Extension register that is trapped to
++         * Hyp mode because of a trap configured in the HCPTR sets
++         * this field to 0xA.
++         */
++        int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
++        uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
++
++        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
+         return false;
+     }
+--
+.25.1

-New patch
+[PULL 03/28] target/arm: Move exception_target_el out of line
+From: Richard Henderson <richard.henderson@linaro.org>
+Move the function to op_helper.c, near raise_exception.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-4-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h | 16 +---------------
+ target/arm/op_helper.c | 15 +++++++++++++++
+files changed, 16 insertions(+), 15 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
+ int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
+ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
+-static inline int exception_target_el(CPUARMState *env)
+-{
+-    int target_el = MAX(1, arm_current_el(env));
+-
+-    /*
+-     * No such thing as secure EL1 if EL3 is aarch32,
+-     * so update the target EL to EL3 in this case.
+-     */
+-    if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
+-        target_el = 3;
+-    }
+-
+-    return target_el;
+-}
+-
+ /* Determine if allocation tags are available.  */
+ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
+                                                  uint64_t sctlr)
+@@ -XXX,XX +XXX,XX @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+ bool el_is_in_host(CPUARMState *env, int el);
+ void aa32_max_features(ARMCPU *cpu);
++int exception_target_el(CPUARMState *env);
+ /* Powers of 2 for sve_vq_map et al. */
+ #define SVE_VQ_POW2_MAP                                 \
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/op_helper.c
++++ b/target/arm/op_helper.c
+@@ -XXX,XX +XXX,XX @@
+ #define SIGNBIT (uint32_t)0x80000000
+ #define SIGNBIT64 ((uint64_t)1 << 63)
++int exception_target_el(CPUARMState *env)
++{
++    int target_el = MAX(1, arm_current_el(env));
++
++    /*
++     * No such thing as secure EL1 if EL3 is aarch32,
++     * so update the target EL to EL3 in this case.
++     */
++    if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
++        target_el = 3;
++    }
++
++    return target_el;
++}
++
+ void raise_exception(CPUARMState *env, uint32_t excp,
+                      uint32_t syndrome, uint32_t target_el)
+ {
+--
+.25.1

-New patch
+[PULL 04/28] target/arm: Move arm_singlestep_active out of line
+From: Richard Henderson <richard.henderson@linaro.org>
+Move the function to debug_helper.c, and the
+declaration to internals.h.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-5-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h          | 10 ----------
+ target/arm/internals.h    |  1 +
+ target/arm/debug_helper.c | 12 ++++++++++++
+files changed, 13 insertions(+), 10 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline bool arm_generate_debug_exceptions(CPUARMState *env)
+     }
+ }
+-/* Is single-stepping active? (Note that the "is EL_D AArch64?" check
+- * implicitly means this always returns false in pre-v8 CPUs.)
+- */
+-static inline bool arm_singlestep_active(CPUARMState *env)
+-{
+-    return extract32(env->cp15.mdscr_el1, 0, 1)
+-        && arm_el_is_aa64(env, arm_debug_target_el(env))
+-        && arm_generate_debug_exceptions(env);
+-}
+-
+ static inline bool arm_sctlr_b(CPUARMState *env)
+ {
+     return
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el);
+ void aa32_max_features(ARMCPU *cpu);
+ int exception_target_el(CPUARMState *env);
++bool arm_singlestep_active(CPUARMState *env);
+ /* Powers of 2 for sve_vq_map et al. */
+ #define SVE_VQ_POW2_MAP                                 \
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/debug_helper.c
++++ b/target/arm/debug_helper.c
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/exec-all.h"
+ #include "exec/helper-proto.h"
++
++/*
++ * Is single-stepping active? (Note that the "is EL_D AArch64?" check
++ * implicitly means this always returns false in pre-v8 CPUs.)
++ */
++bool arm_singlestep_active(CPUARMState *env)
++{
++    return extract32(env->cp15.mdscr_el1, 0, 1)
++        && arm_el_is_aa64(env, arm_debug_target_el(env))
++        && arm_generate_debug_exceptions(env);
++}
++
+ /* Return true if the linked breakpoint entry lbn passes its checks */
+ static bool linked_bp_matches(ARMCPU *cpu, int lbn)
+ {
+--
+.25.1

-New patch
+[PULL 05/28] target/arm: Move arm_generate_debug_exceptions out of line
+From: Richard Henderson <richard.henderson@linaro.org>
+Move arm_generate_debug_exceptions and its two subroutines,
+{aa32,aa64}_generate_debug_exceptions into debug_helper.c,
+and the one interface declaration to internals.h.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-6-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h          | 91 -------------------------------------
+ target/arm/internals.h    |  1 +
+ target/arm/debug_helper.c | 94 +++++++++++++++++++++++++++++++++++++++
+files changed, 95 insertions(+), 91 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
+     return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
+ }
+-/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
+-static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
+-{
+-    int cur_el = arm_current_el(env);
+-    int debug_el;
+-
+-    if (cur_el == 3) {
+-        return false;
+-    }
+-
+-    /* MDCR_EL3.SDD disables debug events from Secure state */
+-    if (arm_is_secure_below_el3(env)
+-        && extract32(env->cp15.mdcr_el3, 16, 1)) {
+-        return false;
+-    }
+-
+-    /*
+-     * Same EL to same EL debug exceptions need MDSCR_KDE enabled
+-     * while not masking the (D)ebug bit in DAIF.
+-     */
+-    debug_el = arm_debug_target_el(env);
+-
+-    if (cur_el == debug_el) {
+-        return extract32(env->cp15.mdscr_el1, 13, 1)
+-            && !(env->daif & PSTATE_D);
+-    }
+-
+-    /* Otherwise the debug target needs to be a higher EL */
+-    return debug_el > cur_el;
+-}
+-
+-static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
+-{
+-    int el = arm_current_el(env);
+-
+-    if (el == 0 && arm_el_is_aa64(env, 1)) {
+-        return aa64_generate_debug_exceptions(env);
+-    }
+-
+-    if (arm_is_secure(env)) {
+-        int spd;
+-
+-        if (el == 0 && (env->cp15.sder & 1)) {
+-            /* SDER.SUIDEN means debug exceptions from Secure EL0
+-             * are always enabled. Otherwise they are controlled by
+-             * SDCR.SPD like those from other Secure ELs.
+-             */
+-            return true;
+-        }
+-
+-        spd = extract32(env->cp15.mdcr_el3, 14, 2);
+-        switch (spd) {
+-        case 1:
+-            /* SPD == 0b01 is reserved, but behaves as 0b00. */
+-        case 0:
+-            /* For 0b00 we return true if external secure invasive debug
+-             * is enabled. On real hardware this is controlled by external
+-             * signals to the core. QEMU always permits debug, and behaves
+-             * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
+-             */
+-            return true;
+-        case 2:
+-            return false;
+-        case 3:
+-            return true;
+-        }
+-    }
+-
+-    return el != 2;
+-}
+-
+-/* Return true if debugging exceptions are currently enabled.
+- * This corresponds to what in ARM ARM pseudocode would be
+- *    if UsingAArch32() then
+- *        return AArch32.GenerateDebugExceptions()
+- *    else
+- *        return AArch64.GenerateDebugExceptions()
+- * We choose to push the if() down into this function for clarity,
+- * since the pseudocode has it at all callsites except for the one in
+- * CheckSoftwareStep(), where it is elided because both branches would
+- * always return the same value.
+- */
+-static inline bool arm_generate_debug_exceptions(CPUARMState *env)
+-{
+-    if (env->aarch64) {
+-        return aa64_generate_debug_exceptions(env);
+-    } else {
+-        return aa32_generate_debug_exceptions(env);
+-    }
+-}
+-
+ static inline bool arm_sctlr_b(CPUARMState *env)
+ {
+     return
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el);
+ void aa32_max_features(ARMCPU *cpu);
+ int exception_target_el(CPUARMState *env);
+ bool arm_singlestep_active(CPUARMState *env);
++bool arm_generate_debug_exceptions(CPUARMState *env);
+ /* Powers of 2 for sve_vq_map et al. */
+ #define SVE_VQ_POW2_MAP                                 \
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/debug_helper.c
++++ b/target/arm/debug_helper.c
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/helper-proto.h"
++/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
++static bool aa64_generate_debug_exceptions(CPUARMState *env)
++{
++    int cur_el = arm_current_el(env);
++    int debug_el;
++
++    if (cur_el == 3) {
++        return false;
++    }
++
++    /* MDCR_EL3.SDD disables debug events from Secure state */
++    if (arm_is_secure_below_el3(env)
++        && extract32(env->cp15.mdcr_el3, 16, 1)) {
++        return false;
++    }
++
++    /*
++     * Same EL to same EL debug exceptions need MDSCR_KDE enabled
++     * while not masking the (D)ebug bit in DAIF.
++     */
++    debug_el = arm_debug_target_el(env);
++
++    if (cur_el == debug_el) {
++        return extract32(env->cp15.mdscr_el1, 13, 1)
++            && !(env->daif & PSTATE_D);
++    }
++
++    /* Otherwise the debug target needs to be a higher EL */
++    return debug_el > cur_el;
++}
++
++static bool aa32_generate_debug_exceptions(CPUARMState *env)
++{
++    int el = arm_current_el(env);
++
++    if (el == 0 && arm_el_is_aa64(env, 1)) {
++        return aa64_generate_debug_exceptions(env);
++    }
++
++    if (arm_is_secure(env)) {
++        int spd;
++
++        if (el == 0 && (env->cp15.sder & 1)) {
++            /*
++             * SDER.SUIDEN means debug exceptions from Secure EL0
++             * are always enabled. Otherwise they are controlled by
++             * SDCR.SPD like those from other Secure ELs.
++             */
++            return true;
++        }
++
++        spd = extract32(env->cp15.mdcr_el3, 14, 2);
++        switch (spd) {
++        case 1:
++            /* SPD == 0b01 is reserved, but behaves as 0b00. */
++        case 0:
++            /*
++             * For 0b00 we return true if external secure invasive debug
++             * is enabled. On real hardware this is controlled by external
++             * signals to the core. QEMU always permits debug, and behaves
++             * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
++             */
++            return true;
++        case 2:
++            return false;
++        case 3:
++            return true;
++        }
++    }
++
++    return el != 2;
++}
++
++/*
++ * Return true if debugging exceptions are currently enabled.
++ * This corresponds to what in ARM ARM pseudocode would be
++ *    if UsingAArch32() then
++ *        return AArch32.GenerateDebugExceptions()
++ *    else
++ *        return AArch64.GenerateDebugExceptions()
++ * We choose to push the if() down into this function for clarity,
++ * since the pseudocode has it at all callsites except for the one in
++ * CheckSoftwareStep(), where it is elided because both branches would
++ * always return the same value.
++ */
++bool arm_generate_debug_exceptions(CPUARMState *env)
++{
++    if (env->aarch64) {
++        return aa64_generate_debug_exceptions(env);
++    } else {
++        return aa32_generate_debug_exceptions(env);
++    }
++}
++
+ /*
+  * Is single-stepping active? (Note that the "is EL_D AArch64?" check
+  * implicitly means this always returns false in pre-v8 CPUs.)
+--
+.25.1

-New patch
+[PULL 06/28] target/arm: Use is_a64 in arm_generate_debug_exceptions
+From: Richard Henderson <richard.henderson@linaro.org>
+Use the accessor rather than the raw structure member.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-7-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/debug_helper.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/debug_helper.c
++++ b/target/arm/debug_helper.c
+@@ -XXX,XX +XXX,XX @@ static bool aa32_generate_debug_exceptions(CPUARMState *env)
+  */
+ bool arm_generate_debug_exceptions(CPUARMState *env)
+ {
+-    if (env->aarch64) {
++    if (is_a64(env)) {
+         return aa64_generate_debug_exceptions(env);
+     } else {
+         return aa32_generate_debug_exceptions(env);
+--
+.25.1

-New patch
+[PULL 07/28] target/arm: Move exception_bkpt_insn to debug_helper.c
+From: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/debug_helper.c | 31 +++++++++++++++++++++++++++++++
+ target/arm/op_helper.c    | 29 -----------------------------
+files changed, 31 insertions(+), 29 deletions(-)
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/debug_helper.c
++++ b/target/arm/debug_helper.c
+@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
+     }
+ }
++/*
++ * Raise an EXCP_BKPT with the specified syndrome register value,
++ * targeting the correct exception level for debug exceptions.
++ */
++void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
++{
++    int debug_el = arm_debug_target_el(env);
++    int cur_el = arm_current_el(env);
++
++    /* FSR will only be used if the debug target EL is AArch32. */
++    env->exception.fsr = arm_debug_exception_fsr(env);
++    /*
++     * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
++     * values to the guest that it shouldn't be able to see at its
++     * exception/security level.
++     */
++    env->exception.vaddress = 0;
++    /*
++     * Other kinds of architectural debug exception are ignored if
++     * they target an exception level below the current one (in QEMU
++     * this is checked by arm_generate_debug_exceptions()). Breakpoint
++     * instructions are special because they always generate an exception
++     * to somewhere: if they can't go to the configured debug exception
++     * level they are taken to the current exception level.
++     */
++    if (debug_el < cur_el) {
++        debug_el = cur_el;
++    }
++    raise_exception(env, EXCP_BKPT, syndrome, debug_el);
++}
++
+ #if !defined(CONFIG_USER_ONLY)
+ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/op_helper.c
++++ b/target/arm/op_helper.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
+     raise_exception(env, excp, syndrome, target_el);
+ }
+-/* Raise an EXCP_BKPT with the specified syndrome register value,
+- * targeting the correct exception level for debug exceptions.
+- */
+-void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
+-{
+-    int debug_el = arm_debug_target_el(env);
+-    int cur_el = arm_current_el(env);
+-
+-    /* FSR will only be used if the debug target EL is AArch32. */
+-    env->exception.fsr = arm_debug_exception_fsr(env);
+-    /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
+-     * values to the guest that it shouldn't be able to see at its
+-     * exception/security level.
+-     */
+-    env->exception.vaddress = 0;
+-    /*
+-     * Other kinds of architectural debug exception are ignored if
+-     * they target an exception level below the current one (in QEMU
+-     * this is checked by arm_generate_debug_exceptions()). Breakpoint
+-     * instructions are special because they always generate an exception
+-     * to somewhere: if they can't go to the configured debug exception
+-     * level they are taken to the current exception level.
+-     */
+-    if (debug_el < cur_el) {
+-        debug_el = cur_el;
+-    }
+-    raise_exception(env, EXCP_BKPT, syndrome, debug_el);
+-}
+-
+ uint32_t HELPER(cpsr_read)(CPUARMState *env)
+ {
+     return cpsr_read(env) & ~CPSR_EXEC;
+--
+.25.1

-New patch
+[PULL 08/28] target/arm: Move arm_debug_exception_fsr to debug_helper.c
+From: Richard Henderson <richard.henderson@linaro.org>
+This function now now only used in debug_helper.c, so there is
+no reason to have a declaration in a header.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-9-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h    | 25 -------------------------
+ target/arm/debug_helper.c | 26 ++++++++++++++++++++++++++
+files changed, 26 insertions(+), 25 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
+     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
+ }
+-/* Return the FSR value for a debug exception (watchpoint, hardware
+- * breakpoint or BKPT insn) targeting the specified exception level.
+- */
+-static inline uint32_t arm_debug_exception_fsr(CPUARMState *env)
+-{
+-    ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
+-    int target_el = arm_debug_target_el(env);
+-    bool using_lpae = false;
+-
+-    if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
+-        using_lpae = true;
+-    } else {
+-        if (arm_feature(env, ARM_FEATURE_LPAE) &&
+-            (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) {
+-            using_lpae = true;
+-        }
+-    }
+-
+-    if (using_lpae) {
+-        return arm_fi_to_lfsc(&fi);
+-    } else {
+-        return arm_fi_to_sfsc(&fi);
+-    }
+-}
+-
+ /**
+  * arm_num_brps: Return number of implemented breakpoints.
+  * Note that the ID register BRPS field is "number of bps - 1",
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/debug_helper.c
++++ b/target/arm/debug_helper.c
+@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
+     return check_watchpoints(cpu);
+ }
++/*
++ * Return the FSR value for a debug exception (watchpoint, hardware
++ * breakpoint or BKPT insn) targeting the specified exception level.
++ */
++static uint32_t arm_debug_exception_fsr(CPUARMState *env)
++{
++    ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
++    int target_el = arm_debug_target_el(env);
++    bool using_lpae = false;
++
++    if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
++        using_lpae = true;
++    } else {
++        if (arm_feature(env, ARM_FEATURE_LPAE) &&
++            (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) {
++            using_lpae = true;
++        }
++    }
++
++    if (using_lpae) {
++        return arm_fi_to_lfsc(&fi);
++    } else {
++        return arm_fi_to_sfsc(&fi);
++    }
++}
++
+ void arm_debug_excp_handler(CPUState *cs)
+ {
+     /*
+--
+.25.1

-New patch
+[PULL 09/28] target/arm: Rename helper_exception_with_syndrome
+From: Richard Henderson <richard.henderson@linaro.org>
+Rename to helper_exception_with_syndrome_el, to emphasize
+that the target el is a parameter.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-10-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.h    | 2 +-
+ target/arm/translate.h | 6 +++---
+ target/arm/op_helper.c | 6 +++---
+ target/arm/translate.c | 6 +++---
+files changed, 10 insertions(+), 10 deletions(-)
+diff --git a/target/arm/helper.h b/target/arm/helper.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.h
++++ b/target/arm/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
+                    i32, i32, i32, i32)
+ DEF_HELPER_2(exception_internal, noreturn, env, i32)
+-DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32)
++DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32)
+ DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32)
+ DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
+ DEF_HELPER_1(setend, void, env)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.h
++++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s)
+ static inline void gen_exception(int excp, uint32_t syndrome,
+                                  uint32_t target_el)
+ {
+-    gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp),
+-                                       tcg_constant_i32(syndrome),
+-                                       tcg_constant_i32(target_el));
++    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
++                                          tcg_constant_i32(syndrome),
++                                          tcg_constant_i32(target_el));
+ }
+ /* Generate an architectural singlestep exception */
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/op_helper.c
++++ b/target/arm/op_helper.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(yield)(CPUARMState *env)
+  * those EXCP values which are special cases for QEMU to interrupt
+  * execution and not to be used for exceptions which are passed to
+  * the guest (those must all have syndrome information and thus should
+- * use exception_with_syndrome).
++ * use exception_with_syndrome*).
+  */
+ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
+ {
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
+ }
+ /* Raise an exception with the specified syndrome register value */
+-void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
+-                                     uint32_t syndrome, uint32_t target_el)
++void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp,
++                                        uint32_t syndrome, uint32_t target_el)
+ {
+     raise_exception(env, excp, syndrome, target_el);
+ }
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
+ {
+     gen_set_condexec(s);
+     gen_set_pc_im(s, s->pc_curr);
+-    gen_helper_exception_with_syndrome(cpu_env,
+-                                       tcg_constant_i32(excp),
+-                                       tcg_constant_i32(syn), tcg_el);
++    gen_helper_exception_with_syndrome_el(cpu_env,
++                                          tcg_constant_i32(excp),
++                                          tcg_constant_i32(syn), tcg_el);
+     s->base.is_jmp = DISAS_NORETURN;
+ }
+--
+.25.1

-New patch
+[PULL 10/28] target/arm: Introduce gen_exception_insn_el_v
+From: Richard Henderson <richard.henderson@linaro.org>
+Create a function below gen_exception_insn that takes
+the target_el as a TCGv_i32, replacing gen_exception_el.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/translate.c | 27 ++++++++++++---------------
+file changed, 12 insertions(+), 15 deletions(-)
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
+     s->base.is_jmp = DISAS_NORETURN;
+ }
+-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
+-                        uint32_t syn, uint32_t target_el)
++static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
++                                    uint32_t syn, TCGv_i32 tcg_el)
+ {
+     if (s->aarch64) {
+         gen_a64_set_pc_im(pc);
+@@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
+         gen_set_condexec(s);
+         gen_set_pc_im(s, pc);
+     }
+-    gen_exception(excp, syn, target_el);
++    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
++                                          tcg_constant_i32(syn), tcg_el);
+     s->base.is_jmp = DISAS_NORETURN;
+ }
++void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
++                        uint32_t syn, uint32_t target_el)
++{
++    gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
++}
++
+ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
+ {
+     gen_set_condexec(s);
+@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s)
+                        default_exception_el(s));
+ }
+-static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
+-                             TCGv_i32 tcg_el)
+-{
+-    gen_set_condexec(s);
+-    gen_set_pc_im(s, s->pc_curr);
+-    gen_helper_exception_with_syndrome_el(cpu_env,
+-                                          tcg_constant_i32(excp),
+-                                          tcg_constant_i32(syn), tcg_el);
+-    s->base.is_jmp = DISAS_NORETURN;
+-}
+-
+ /* Force a TB lookup after an instruction that changes the CPU state.  */
+ void gen_lookup_tb(DisasContext *s)
+ {
+@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
+                 tcg_el = tcg_constant_i32(3);
+             }
+-            gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
++            gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF,
++                                    syn_uncategorized(), tcg_el);
+             tcg_temp_free_i32(tcg_el);
+             return false;
+         }
+--
+.25.1

-New patch
+[PULL 11/28] target/arm: Rename gen_exception_insn to gen_exception_insn_el
+From: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-12-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/translate.h        |  4 ++--
+ target/arm/translate-a64.c    | 36 ++++++++++++++++----------------
+ target/arm/translate-m-nocp.c | 16 +++++++-------
+ target/arm/translate-mve.c    |  4 ++--
+ target/arm/translate-vfp.c    |  6 +++---
+ target/arm/translate.c        | 39 ++++++++++++++++++-----------------
+files changed, 53 insertions(+), 52 deletions(-)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.h
++++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
+ void arm_gen_test_cc(int cc, TCGLabel *label);
+ MemOp pow2_align(unsigned i);
+ void unallocated_encoding(DisasContext *s);
+-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
+-                        uint32_t syn, uint32_t target_el);
++void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
++                           uint32_t syn, uint32_t target_el);
+ /* Return state of Alternate Half-precision flag, caller frees result */
+ static inline TCGv_i32 get_ahp_flag(void)
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-a64.c
++++ b/target/arm/translate-a64.c
+@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
+         assert(!s->fp_access_checked);
+         s->fp_access_checked = true;
+-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+-                           syn_fp_access_trap(1, 0xe, false, 0),
+-                           s->fp_excp_el);
++        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
++                              syn_fp_access_trap(1, 0xe, false, 0),
++                              s->fp_excp_el);
+         return false;
+     }
+     s->fp_access_checked = true;
+@@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s)
+         assert(!s->sve_access_checked);
+         s->sve_access_checked = true;
+-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+-                           syn_sve_access_trap(), s->sve_excp_el);
++        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
++                              syn_sve_access_trap(), s->sve_excp_el);
+         return false;
+     }
+     s->sve_access_checked = true;
+@@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
+     } else {
+         syndrome = syn_uncategorized();
+     }
+-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome,
+-                       default_exception_el(s));
++    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome,
++                          default_exception_el(s));
+ }
+ /* MRS - move from system register
+@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
+         switch (op2_ll) {
+         case 1:                                                     /* SVC */
+             gen_ss_advance(s);
+-            gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
+-                               syn_aa64_svc(imm16), default_exception_el(s));
++            gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI,
++                                  syn_aa64_svc(imm16), default_exception_el(s));
+             break;
+         case 2:                                                     /* HVC */
+             if (s->current_el == 0) {
+@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
+             gen_a64_set_pc_im(s->pc_curr);
+             gen_helper_pre_hvc(cpu_env);
+             gen_ss_advance(s);
+-            gen_exception_insn(s, s->base.pc_next, EXCP_HVC,
+-                               syn_aa64_hvc(imm16), 2);
++            gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
++                                  syn_aa64_hvc(imm16), 2);
+             break;
+         case 3:                                                     /* SMC */
+             if (s->current_el == 0) {
+@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
+             gen_a64_set_pc_im(s->pc_curr);
+             gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
+             gen_ss_advance(s);
+-            gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
+-                               syn_aa64_smc(imm16), 3);
++            gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
++                                  syn_aa64_smc(imm16), 3);
+             break;
+         default:
+             unallocated_encoding(s);
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+          * Illegal execution state. This has priority over BTI
+          * exceptions, but comes after instruction abort exceptions.
+          */
+-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+-                           syn_illegalstate(), default_exception_el(s));
++        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
++                              syn_illegalstate(), default_exception_el(s));
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+             if (s->btype != 0
+                 && s->guarded_page
+                 && !btype_destination_ok(insn, s->bt, s->btype)) {
+-                gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+-                                   syn_btitrap(s->btype),
+-                                   default_exception_el(s));
++                gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
++                                      syn_btitrap(s->btype),
++                                      default_exception_el(s));
+                 return;
+             }
+         } else {
+diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-m-nocp.c
++++ b/target/arm/translate-m-nocp.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
+     tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
+     if (s->fp_excp_el != 0) {
+-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+-                           syn_uncategorized(), s->fp_excp_el);
++        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
++                              syn_uncategorized(), s->fp_excp_el);
+         return true;
+     }
+@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
+         if (!vfp_access_check_m(s, true)) {
+             /*
+              * This was only a conditional exception, so override
+-             * gen_exception_insn()'s default to DISAS_NORETURN
++             * gen_exception_insn_el()'s default to DISAS_NORETURN
+              */
+             s->base.is_jmp = DISAS_NEXT;
+             break;
+@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
+         if (!vfp_access_check_m(s, true)) {
+             /*
+              * This was only a conditional exception, so override
+-             * gen_exception_insn()'s default to DISAS_NORETURN
++             * gen_exception_insn_el()'s default to DISAS_NORETURN
+              */
+             s->base.is_jmp = DISAS_NEXT;
+             break;
+@@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
+     }
+     if (a->cp != 10) {
+-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+-                           syn_uncategorized(), default_exception_el(s));
++        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
++                              syn_uncategorized(), default_exception_el(s));
+         return true;
+     }
+     if (s->fp_excp_el != 0) {
+-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+-                           syn_uncategorized(), s->fp_excp_el);
++        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
++                              syn_uncategorized(), s->fp_excp_el);
+         return true;
+     }
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s)
+         return true;
+     default:
+         /* Reserved value: INVSTATE UsageFault */
+-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+-                           default_exception_el(s));
++        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
++                              default_exception_el(s));
+         return false;
+     }
+ }
+diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-vfp.c
++++ b/target/arm/translate-vfp.c
+@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
+         int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
+         uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
+-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
++        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
+         return false;
+     }
+@@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update)
+          * the encoding space handled by the patterns in m-nocp.decode,
+          * and for them we may need to raise NOCP here.
+          */
+-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+-                           syn_uncategorized(), s->fp_excp_el);
++        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
++                              syn_uncategorized(), s->fp_excp_el);
+         return false;
+     }
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
+     s->base.is_jmp = DISAS_NORETURN;
+ }
+-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
+-                        uint32_t syn, uint32_t target_el)
++void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
++                           uint32_t syn, uint32_t target_el)
+ {
+     gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
+ void unallocated_encoding(DisasContext *s)
+ {
+     /* Unallocated and reserved encodings are uncategorized */
+-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
+-                       default_exception_el(s));
++    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
++                          default_exception_el(s));
+ }
+ /* Force a TB lookup after an instruction that changes the CPU state.  */
+@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
+ undef:
+     /* If we get here then some access check did not pass */
+-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+-                       syn_uncategorized(), exc_target);
++    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
++                          syn_uncategorized(), exc_target);
+     return false;
+ }
+@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
+      * For the UNPREDICTABLE cases we choose to UNDEF.
+      */
+     if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
+-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3);
++        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
++                              syn_uncategorized(), 3);
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
+          * Do the check-and-raise-exception by hand.
+          */
+         if (s->fp_excp_el) {
+-            gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+-                               syn_uncategorized(), s->fp_excp_el);
++            gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
++                                  syn_uncategorized(), s->fp_excp_el);
+             return true;
+         }
+     }
+@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
+         tmp = load_cpu_field(v7m.ltpsize);
+         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
+         tcg_temp_free_i32(tmp);
+-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+-                           default_exception_el(s));
++        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
++                              default_exception_el(s));
+         gen_set_label(skipexc);
+     }
+@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+      * UsageFault exception.
+      */
+     if (arm_dc_feature(s, ARM_FEATURE_M)) {
+-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+-                           default_exception_el(s));
++        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
++                              default_exception_el(s));
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+          * Illegal execution state. This has priority over BTI
+          * exceptions, but comes after instruction abort exceptions.
+          */
+-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+-                           syn_illegalstate(), default_exception_el(s));
++        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
++                              syn_illegalstate(), default_exception_el(s));
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+          * Illegal execution state. This has priority over BTI
+          * exceptions, but comes after instruction abort exceptions.
+          */
+-        gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF,
+-                           syn_illegalstate(), default_exception_el(dc));
++        gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF,
++                              syn_illegalstate(), default_exception_el(dc));
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+          */
+         tcg_remove_ops_after(dc->insn_eci_rewind);
+         dc->condjmp = 0;
+-        gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+-                           default_exception_el(dc));
++        gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
++                              default_exception_el(dc));
+     }
+     arm_post_translate_insn(dc);
+--
+.25.1

-New patch
+[PULL 12/28] target/arm: Introduce gen_exception_insn
+From: Richard Henderson <richard.henderson@linaro.org>
+Create a new wrapper function that passes the default
+exception target to gen_exception_insn_el.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-13-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/translate.h        |  1 +
+ target/arm/translate-a64.c    | 15 ++++++---------
+ target/arm/translate-m-nocp.c |  3 +--
+ target/arm/translate-mve.c    |  3 +--
+ target/arm/translate.c        | 29 +++++++++++++----------------
+files changed, 22 insertions(+), 29 deletions(-)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.h
++++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ MemOp pow2_align(unsigned i);
+ void unallocated_encoding(DisasContext *s);
+ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
+                            uint32_t syn, uint32_t target_el);
++void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn);
+ /* Return state of Alternate Half-precision flag, caller frees result */
+ static inline TCGv_i32 get_ahp_flag(void)
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-a64.c
++++ b/target/arm/translate-a64.c
+@@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
+     } else {
+         syndrome = syn_uncategorized();
+     }
+-    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome,
+-                          default_exception_el(s));
++    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome);
+ }
+ /* MRS - move from system register
+@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
+         switch (op2_ll) {
+         case 1:                                                     /* SVC */
+             gen_ss_advance(s);
+-            gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI,
+-                                  syn_aa64_svc(imm16), default_exception_el(s));
++            gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
++                               syn_aa64_svc(imm16));
+             break;
+         case 2:                                                     /* HVC */
+             if (s->current_el == 0) {
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+          * Illegal execution state. This has priority over BTI
+          * exceptions, but comes after instruction abort exceptions.
+          */
+-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+-                              syn_illegalstate(), default_exception_el(s));
++        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+             if (s->btype != 0
+                 && s->guarded_page
+                 && !btype_destination_ok(insn, s->bt, s->btype)) {
+-                gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+-                                      syn_btitrap(s->btype),
+-                                      default_exception_el(s));
++                gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
++                                   syn_btitrap(s->btype));
+                 return;
+             }
+         } else {
+diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-m-nocp.c
++++ b/target/arm/translate-m-nocp.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
+     }
+     if (a->cp != 10) {
+-        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+-                              syn_uncategorized(), default_exception_el(s));
++        gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized());
+         return true;
+     }
+diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-mve.c
++++ b/target/arm/translate-mve.c
+@@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s)
+         return true;
+     default:
+         /* Reserved value: INVSTATE UsageFault */
+-        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+-                              default_exception_el(s));
++        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
+         return false;
+     }
+ }
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
+     gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
+ }
++void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
++{
++    gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s));
++}
++
+ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
+ {
+     gen_set_condexec(s);
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
+ void unallocated_encoding(DisasContext *s)
+ {
+     /* Unallocated and reserved encodings are uncategorized */
+-    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
+-                          default_exception_el(s));
++    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
+ }
+ /* Force a TB lookup after an instruction that changes the CPU state.  */
+@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
+      * an exception and return false. Otherwise it will return true,
+      * and set *tgtmode and *regno appropriately.
+      */
+-    int exc_target = default_exception_el(s);
+-
+     /* These instructions are present only in ARMv8, or in ARMv7 with the
+      * Virtualization Extensions.
+      */
+@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
+ undef:
+     /* If we get here then some access check did not pass */
+-    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+-                          syn_uncategorized(), exc_target);
++    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
+     return false;
+ }
+@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
+         tmp = load_cpu_field(v7m.ltpsize);
+         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
+         tcg_temp_free_i32(tmp);
+-        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+-                              default_exception_el(s));
++        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
+         gen_set_label(skipexc);
+     }
+@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+      * UsageFault exception.
+      */
+     if (arm_dc_feature(s, ARM_FEATURE_M)) {
+-        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+-                              default_exception_el(s));
++        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+          * Illegal execution state. This has priority over BTI
+          * exceptions, but comes after instruction abort exceptions.
+          */
+-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+-                              syn_illegalstate(), default_exception_el(s));
++        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+          * Illegal execution state. This has priority over BTI
+          * exceptions, but comes after instruction abort exceptions.
+          */
+-        gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF,
+-                              syn_illegalstate(), default_exception_el(dc));
++        gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate());
+         return;
+     }
+@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+          */
+         tcg_remove_ops_after(dc->insn_eci_rewind);
+         dc->condjmp = 0;
+-        gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+-                              default_exception_el(dc));
++        gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE,
++                           syn_uncategorized());
+     }
+     arm_post_translate_insn(dc);
+--
+.25.1

-[PULL 9/9] tmp105: Correct handling of temperature limit checks
+[PULL 13/28] target/arm: Create helper_exception_swstep
-The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device
+From: Richard Henderson <richard.henderson@linaro.org>
 signals an alert when the temperature equals or exceeds the T_high value and
 then remains high until a device register is read or the device responds to
 the SMBUS Alert Response address, or the device is put into Shutdown Mode.
 Thereafter the Alert pin will only be re-signalled when temperature falls
 below T_low; alert can then be cleared in the same set of ways, and the
 device returns to its initial "alert when temperature goes above T_high"
 mode. (If this textual description is confusing, see figure 3 in the
 TI datasheet at https://www.ti.com/lit/gpn/tmp105 .)
-We were misimplementing this as a simple "always alert if temperature is
+Move the computation from gen_swstep_exception into a helper.
 above T_high or below T_low" condition, which gives a spurious alert on
 startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset
 limit values.
-Implement the correct (hysteresis) behaviour by tracking whether we
+This fixes a bug when:
-are currently looking for the temperature to rise over T_high or
+  - MDSCR_EL1.KDE == 1 to enable debug exceptions within EL_D itself
-for it to fall below T_low. Our implementation of the comparator
+  - we singlestep an ERET from EL_D to some lower EL
 mode (TM==0) wasn't wrong, but rephrase it to match the way that
 interrupt mode is now handled for clarity.
+Previously we were computing 'same el' based on the EL which
+executed the ERET instruction, whereas it ought to be computed
+based on the EL to which ERET returned.  This happens naturally
+with the new helper, which runs after EL has been changed.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-14-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20201110150023.25533-3-peter.maydell@linaro.org
 ---
- hw/misc/tmp105.h |  7 +++++
+ target/arm/helper.h       |  1 +
- hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++-------
+ target/arm/translate.h    | 12 +++---------
-files changed, 68 insertions(+), 9 deletions(-)
+ target/arm/debug_helper.c | 16 ++++++++++++++++
 files changed, 20 insertions(+), 9 deletions(-)
-diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h
+diff --git a/target/arm/helper.h b/target/arm/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/tmp105.h
+--- a/target/arm/helper.h
-+++ b/hw/misc/tmp105.h
++++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ struct TMP105State {
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
-     int16_t limit[2];
+ DEF_HELPER_2(exception_internal, noreturn, env, i32)
-     int faults;
+ DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32)
-     uint8_t alarm;
+ DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32)
-+    /*
++DEF_HELPER_2(exception_swstep, noreturn, env, i32)
-+     * The TMP105 initially looks for a temperature rising above T_high;
+ DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
-+     * once this is detected, the condition it looks for next is the
+ DEF_HELPER_1(setend, void, env)
-+     * temperature falling below T_low. This flag is false when initially
+ DEF_HELPER_2(wfi, void, env, i32)
-+     * looking for T_high, true when looking for T_low.
+diff --git a/target/arm/translate.h b/target/arm/translate.h
 +     */
 +    bool detect_falling;
  };
  #endif
 diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/tmp105.c
+--- a/target/arm/translate.h
-+++ b/hw/misc/tmp105.c
++++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s)
+@@ -XXX,XX +XXX,XX @@ static inline void gen_exception(int excp, uint32_t syndrome,
-             return;
+ /* Generate an architectural singlestep exception */
-     }
+ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
+ {
--    if ((s->config >> 1) & 1) {                    /* TM */
+-    bool same_el = (s->debug_target_el == s->current_el);
--        if (s->temperature >= s->limit[1])
+-
--            s->alarm = 1;
+-    /*
--        else if (s->temperature < s->limit[0])
+-     * If singlestep is targeting a lower EL than the current one,
--            s->alarm = 1;
+-     * then s->ss_active must be false and we can never get here.
-+    if (s->config >> 1 & 1) {
+-     */
-+        /*
+-    assert(s->debug_target_el >= s->current_el);
-+         * TM == 1 : Interrupt mode. We signal Alert when the
+-
-+         * temperature rises above T_high, and expect the guest to clear
+-    gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
-+         * it (eg by reading a device register).
++    /* Fill in the same_el field of the syndrome in the helper. */
-+         */
++    uint32_t syn = syn_swstep(false, isv, ex);
-+        if (s->detect_falling) {
++    gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn));
 +            if (s->temperature < s->limit[0]) {
 +                s->alarm = 1;
 +                s->detect_falling = false;
 +            }
 +        } else {
 +            if (s->temperature >= s->limit[1]) {
 +                s->alarm = 1;
 +                s->detect_falling = true;
 +            }
 +        }
      } else {
 -        if (s->temperature >= s->limit[1])
 -            s->alarm = 1;
 -        else if (s->temperature < s->limit[0])
 -            s->alarm = 0;
 +        /*
 +         * TM == 0 : Comparator mode. We signal Alert when the temperature
 +         * rises above T_high, and stop signalling it when the temperature
 +         * falls below T_low.
 +         */
 +        if (s->detect_falling) {
 +            if (s->temperature < s->limit[0]) {
 +                s->alarm = 0;
 +                s->detect_falling = false;
 +            }
 +        } else {
 +            if (s->temperature >= s->limit[1]) {
 +                s->alarm = 1;
 +                s->detect_falling = true;
 +            }
 +        }
      }
      tmp105_interrupt_update(s);
@@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id)
      return 0;
  }
-+static bool detect_falling_needed(void *opaque)
+ /*
 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/debug_helper.c
 +++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
      raise_exception(env, EXCP_BKPT, syndrome, debug_el);
  }
 +void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
 +{
-+    TMP105State *s = opaque;
++    int debug_el = arm_debug_target_el(env);
 +    int cur_el = arm_current_el(env);
 +
 +    /*
-+     * We only need to migrate the detect_falling bool if it's set;
++     * If singlestep is targeting a lower EL than the current one, then
-+     * for migration from older machines we assume that it is false
++     * DisasContext.ss_active must be false and we can never get here.
 +     * (ie temperature is not out of range).
 +     */
-+    return s->detect_falling;
++    assert(debug_el >= cur_el);
 +    if (debug_el == cur_el) {
 +        syndrome |= 1 << ARM_EL_EC_SHIFT;
 +    }
 +    raise_exception(env, EXCP_UDEF, syndrome, debug_el);
 +}
 +
-+static const VMStateDescription vmstate_tmp105_detect_falling = {
+ #if !defined(CONFIG_USER_ONLY)
-+    .name = "TMP105/detect-falling",
-+    .version_id = 1,
+ vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
 +    .minimum_version_id = 1,
 +    .needed = detect_falling_needed,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_BOOL(detect_falling, TMP105State),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
  static const VMStateDescription vmstate_tmp105 = {
      .name = "TMP105",
      .version_id = 0,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = {
          VMSTATE_UINT8(alarm, TMP105State),
          VMSTATE_I2C_SLAVE(i2c, TMP105State),
          VMSTATE_END_OF_LIST()
 +    },
 +    .subsections = (const VMStateDescription*[]) {
 +        &vmstate_tmp105_detect_falling,
 +        NULL
      }
  };
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
      s->config = 0;
      s->faults = tmp105_faultq[(s->config >> 3) & 3];
      s->alarm = 0;
 +    s->detect_falling = false;
      s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
      s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
 --
-.20.1
+.25.1

-New patch
+[PULL 14/28] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL
+From: Richard Henderson <richard.henderson@linaro.org>
+We no longer need this value during translation,
+as it is now handled within the helpers.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-15-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h           |  6 ++----
+ target/arm/translate.h     |  2 --
+ target/arm/helper.c        | 12 ++----------
+ target/arm/translate-a64.c |  1 -
+ target/arm/translate.c     |  1 -
+files changed, 4 insertions(+), 18 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
+ FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
+ /* Target EL if we take a floating-point-disabled exception */
+ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
+-/* For A-profile only, target EL for debug exceptions.  */
+-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
+ /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
+-FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1)
+-FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1)
++FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
++FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
+ /*
+  * Bit usage when in AArch32 state, both A- and M-profile.
+diff --git a/target/arm/translate.h b/target/arm/translate.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.h
++++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+      */
+     uint32_t svc_imm;
+     int current_el;
+-    /* Debug target exception level for single-step exceptions */
+-    int debug_target_el;
+     GHashTable *cp_regs;
+     uint64_t features; /* CPU features bits */
+     bool aarch64;
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
+     return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
+ }
+-static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env)
+-{
+-    CPUARMTBFlags flags = {};
+-
+-    DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env));
+-    return flags;
+-}
+-
+ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
+                                         ARMMMUIdx mmu_idx)
+ {
+-    CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
++    CPUARMTBFlags flags = {};
+     int el = arm_current_el(env);
+     if (arm_sctlr(env, el) & SCTLR_A) {
+@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
+ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
+                                         ARMMMUIdx mmu_idx)
+ {
+-    CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
++    CPUARMTBFlags flags = {};
+     ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
+     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
+     uint64_t sctlr;
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-a64.c
++++ b/target/arm/translate-a64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
+     dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE);
+     dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS);
+     dc->is_ldex = false;
+-    dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
+     /* Bound the number of insns to execute to those left on the page.  */
+     bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+         dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT);
+         dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED);
+     } else {
+-        dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
+         dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B);
+         dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE);
+         dc->ns = EX_TBFLAG_A32(tb_flags, NS);
+--
+.25.1

-New patch
+[PULL 15/28] target/arm: Move gen_exception to translate.c
+From: Richard Henderson <richard.henderson@linaro.org>
+This function is not required by any other translation file.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-16-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/translate.h | 8 --------
+ target/arm/translate.c | 7 +++++++
+files changed, 7 insertions(+), 8 deletions(-)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.h
++++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s)
+     }
+ }
+-static inline void gen_exception(int excp, uint32_t syndrome,
+-                                 uint32_t target_el)
+-{
+-    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
+-                                          tcg_constant_i32(syndrome),
+-                                          tcg_constant_i32(target_el));
+-}
+-
+ /* Generate an architectural singlestep exception */
+ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
+ {
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
+     s->base.is_jmp = DISAS_NORETURN;
+ }
++static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
++{
++    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
++                                          tcg_constant_i32(syndrome),
++                                          tcg_constant_i32(target_el));
++}
++
+ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
+                                     uint32_t syn, TCGv_i32 tcg_el)
+ {
+--
+.25.1

-New patch
+[PULL 16/28] target/arm: Rename gen_exception to gen_exception_el
+From: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-17-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/translate.c | 18 +++++++++---------
+file changed, 9 insertions(+), 9 deletions(-)
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
+     s->base.is_jmp = DISAS_NORETURN;
+ }
+-static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
++static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
+ {
+     gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
+                                           tcg_constant_i32(syndrome),
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+         switch (dc->base.is_jmp) {
+         case DISAS_SWI:
+             gen_ss_advance(dc);
+-            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
+-                          default_exception_el(dc));
++            gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
++                             default_exception_el(dc));
+             break;
+         case DISAS_HVC:
+             gen_ss_advance(dc);
+-            gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
++            gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
+             break;
+         case DISAS_SMC:
+             gen_ss_advance(dc);
+-            gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
++            gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3);
+             break;
+         case DISAS_NEXT:
+         case DISAS_TOO_MANY:
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+             gen_helper_yield(cpu_env);
+             break;
+         case DISAS_SWI:
+-            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
+-                          default_exception_el(dc));
++            gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
++                             default_exception_el(dc));
+             break;
+         case DISAS_HVC:
+-            gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
++            gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
+             break;
+         case DISAS_SMC:
+-            gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
++            gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3);
+             break;
+         }
+     }
+--
+.25.1

-New patch
+[PULL 17/28] target/arm: Introduce gen_exception
+From: Richard Henderson <richard.henderson@linaro.org>
+Create a new wrapper function that passes the default
+exception target to gen_exception_el.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-18-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/translate.c | 11 +++++++----
+file changed, 7 insertions(+), 4 deletions(-)
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
+                                           tcg_constant_i32(target_el));
+ }
++static void gen_exception(DisasContext *s, int excp, uint32_t syndrome)
++{
++    gen_exception_el(excp, syndrome, default_exception_el(s));
++}
++
+ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
+                                     uint32_t syn, TCGv_i32 tcg_el)
+ {
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+         switch (dc->base.is_jmp) {
+         case DISAS_SWI:
+             gen_ss_advance(dc);
+-            gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
+-                             default_exception_el(dc));
++            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
+             break;
+         case DISAS_HVC:
+             gen_ss_advance(dc);
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+             gen_helper_yield(cpu_env);
+             break;
+         case DISAS_SWI:
+-            gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
+-                             default_exception_el(dc));
++            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
+             break;
+         case DISAS_HVC:
+             gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
+--
+.25.1

-New patch
+[PULL 18/28] target/arm: Introduce gen_exception_el_v
+From: Richard Henderson <richard.henderson@linaro.org>
+Split out a common helper function for gen_exception_el
+and gen_exception_insn_el_v.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-19-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/translate.c | 13 ++++++++-----
+file changed, 8 insertions(+), 5 deletions(-)
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
+     s->base.is_jmp = DISAS_NORETURN;
+ }
+-static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
++static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_el)
+ {
+     gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
+-                                          tcg_constant_i32(syndrome),
+-                                          tcg_constant_i32(target_el));
++                                          tcg_constant_i32(syndrome), tcg_el);
++}
++
++static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
++{
++    gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el));
+ }
+ static void gen_exception(DisasContext *s, int excp, uint32_t syndrome)
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
+         gen_set_condexec(s);
+         gen_set_pc_im(s, pc);
+     }
+-    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
+-                                          tcg_constant_i32(syn), tcg_el);
++    gen_exception_el_v(excp, syn, tcg_el);
+     s->base.is_jmp = DISAS_NORETURN;
+ }
+--
+.25.1

-New patch
+[PULL 19/28] target/arm: Introduce helper_exception_with_syndrome
+From: Richard Henderson <richard.henderson@linaro.org>
+With the helper we can use exception_target_el at runtime,
+instead of default_exception_el at translate time.
+While we're at it, remove the DisasContext parameter from
+gen_exception, as it is no longer used.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-20-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/helper.h    |  1 +
+ target/arm/op_helper.c | 10 ++++++++++
+ target/arm/translate.c | 18 +++++++++++++-----
+files changed, 24 insertions(+), 5 deletions(-)
+diff --git a/target/arm/helper.h b/target/arm/helper.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.h
++++ b/target/arm/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
+                    i32, i32, i32, i32)
+ DEF_HELPER_2(exception_internal, noreturn, env, i32)
++DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32)
+ DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32)
+ DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32)
+ DEF_HELPER_2(exception_swstep, noreturn, env, i32)
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/op_helper.c
++++ b/target/arm/op_helper.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp,
+     raise_exception(env, excp, syndrome, target_el);
+ }
++/*
++ * Raise an exception with the specified syndrome register value
++ * to the default target el.
++ */
++void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
++                                     uint32_t syndrome)
++{
++    raise_exception(env, excp, syndrome, exception_target_el(env));
++}
++
+ uint32_t HELPER(cpsr_read)(CPUARMState *env)
+ {
+     return cpsr_read(env) & ~CPSR_EXEC;
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
+     gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el));
+ }
+-static void gen_exception(DisasContext *s, int excp, uint32_t syndrome)
++static void gen_exception(int excp, uint32_t syndrome)
+ {
+-    gen_exception_el(excp, syndrome, default_exception_el(s));
++    gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp),
++                                       tcg_constant_i32(syndrome));
+ }
+ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
+@@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
+ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
+ {
+-    gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s));
++    if (s->aarch64) {
++        gen_a64_set_pc_im(pc);
++    } else {
++        gen_set_condexec(s);
++        gen_set_pc_im(s, pc);
++    }
++    gen_exception(excp, syn);
++    s->base.is_jmp = DISAS_NORETURN;
+ }
+ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+         switch (dc->base.is_jmp) {
+         case DISAS_SWI:
+             gen_ss_advance(dc);
+-            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
++            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
+             break;
+         case DISAS_HVC:
+             gen_ss_advance(dc);
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
+             gen_helper_yield(cpu_env);
+             break;
+         case DISAS_SWI:
+-            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
++            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
+             break;
+         case DISAS_HVC:
+             gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
+--
+.25.1

-New patch
+[PULL 20/28] target/arm: Remove default_exception_el
+From: Richard Henderson <richard.henderson@linaro.org>
+This function is no longer used.  At the same time, remove
+DisasContext.secure_routed_to_el3, as it in turn becomes unused.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-21-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/translate.h     | 16 ----------------
+ target/arm/translate-a64.c |  5 -----
+ target/arm/translate.c     |  5 -----
+files changed, 26 deletions(-)
+diff --git a/target/arm/translate.h b/target/arm/translate.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.h
++++ b/target/arm/translate.h
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
+     int fp_excp_el; /* FP exception EL or 0 if enabled */
+     int sve_excp_el; /* SVE exception EL or 0 if enabled */
+     int vl;          /* current vector length in bytes */
+-    /* Flag indicating that exceptions from secure mode are routed to EL3. */
+-    bool secure_routed_to_el3;
+     bool vfp_enabled; /* FP enabled via FPSCR.EN */
+     int vec_len;
+     int vec_stride;
+@@ -XXX,XX +XXX,XX @@ static inline int get_mem_index(DisasContext *s)
+     return arm_to_core_mmu_idx(s->mmu_idx);
+ }
+-/* Function used to determine the target exception EL when otherwise not known
+- * or default.
+- */
+-static inline int default_exception_el(DisasContext *s)
+-{
+-    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
+-     * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
+-     * exceptions can only be routed to ELs above 1, so we target the higher of
+-     * 1 or the current EL.
+-     */
+-    return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
+-            ? 3 : MAX(1, s->current_el);
+-}
+-
+ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
+ {
+     /* We don't need to save all of the syndrome so we mask and shift
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate-a64.c
++++ b/target/arm/translate-a64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
+     dc->condjmp = 0;
+     dc->aarch64 = true;
+-    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
+-     * there is no secure EL1, so we route exceptions to EL3.
+-     */
+-    dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
+-                               !arm_el_is_aa64(env, 3);
+     dc->thumb = false;
+     dc->sctlr_b = 0;
+     dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
+diff --git a/target/arm/translate.c b/target/arm/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+     dc->condjmp = 0;
+     dc->aarch64 = false;
+-    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
+-     * there is no secure EL1, so we route exceptions to EL3.
+-     */
+-    dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
+-                               !arm_el_is_aa64(env, 3);
+     dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB);
+     dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
+     condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC);
+--
+.25.1

-[PULL 2/9] exynos: Fix bad printf format specifiers
+[PULL 21/28] target/arm: Create raise_exception_debug
-From: Alex Chen <alex.chen@huawei.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-We should use printf format specifier "%u" instead of "%d" for
+Handle the debug vs current el exception test in one place.
-argument of type "unsigned int".
+Leave EXCP_BKPT alone, since that treats debug < current differently.
-Reported-by: Euler Robot <euler.robot@huawei.com>
-Signed-off-by: Alex Chen <alex.chen@huawei.com>
-Message-id: 20201111073651.72804-1-alex.chen@huawei.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-22-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/timer/exynos4210_mct.c | 4 ++--
+ target/arm/debug_helper.c | 44 +++++++++++++++++++++------------------
- hw/timer/exynos4210_pwm.c | 8 ++++----
+file changed, 24 insertions(+), 20 deletions(-)
 files changed, 6 insertions(+), 6 deletions(-)
-diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/exynos4210_mct.c
+--- a/target/arm/debug_helper.c
-+++ b/hw/timer/exynos4210_mct.c
++++ b/target/arm/debug_helper.c
-@@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
+@@ -XXX,XX +XXX,XX @@
-     /* If CSTAT is pending and IRQ is enabled */
+ #include "exec/helper-proto.h"
-     if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
-             (s->reg.int_enb & G_INT_ENABLE(id))) {
--        DPRINTF("gcmp timer[%d] IRQ\n", id);
++/*
-+        DPRINTF("gcmp timer[%u] IRQ\n", id);
++ * Raise an exception to the debug target el.
-         qemu_irq_raise(s->irq[id]);
++ * Modify syndrome to indicate when origin and target EL are the same.
 + */
 +G_NORETURN static void
 +raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome)
 +{
 +    int debug_el = arm_debug_target_el(env);
 +    int cur_el = arm_current_el(env);
 +
 +    /*
 +     * If singlestep is targeting a lower EL than the current one, then
 +     * DisasContext.ss_active must be false and we can never get here.
 +     * Similarly for watchpoint and breakpoint matches.
 +     */
 +    assert(debug_el >= cur_el);
 +    syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT;
 +    raise_exception(env, excp, syndrome, debug_el);
 +}
 +
  /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
  static bool aa64_generate_debug_exceptions(CPUARMState *env)
  {
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
      if (wp_hit) {
          if (wp_hit->flags & BP_CPU) {
              bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
 -            bool same_el = arm_debug_target_el(env) == arm_current_el(env);
              cs->watchpoint_hit = NULL;
              env->exception.fsr = arm_debug_exception_fsr(env);
              env->exception.vaddress = wp_hit->hitaddr;
 -            raise_exception(env, EXCP_DATA_ABORT,
 -                    syn_watchpoint(same_el, 0, wnr),
 -                    arm_debug_target_el(env));
 +            raise_exception_debug(env, EXCP_DATA_ABORT,
 +                                  syn_watchpoint(0, 0, wnr));
          }
      } else {
          uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
 -        bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
          /*
           * (1) GDB breakpoints should be handled first.
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
           * exception/security level.
           */
          env->exception.vaddress = 0;
 -        raise_exception(env, EXCP_PREFETCH_ABORT,
 -                        syn_breakpoint(same_el),
 -                        arm_debug_target_el(env));
 +        raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0));
      }
  }
-@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
-                     MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
-     if (freq != s->freq) {
+ void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
--        DPRINTF("freq=%dHz\n", s->freq);
+ {
-+        DPRINTF("freq=%uHz\n", s->freq);
+-    int debug_el = arm_debug_target_el(env);
+-    int cur_el = arm_current_el(env);
-         /* global timer */
+-
-         tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
+-    /*
-diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
+-     * If singlestep is targeting a lower EL than the current one, then
-index XXXXXXX..XXXXXXX 100644
+-     * DisasContext.ss_active must be false and we can never get here.
---- a/hw/timer/exynos4210_pwm.c
+-     */
-+++ b/hw/timer/exynos4210_pwm.c
+-    assert(debug_el >= cur_el);
-@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
+-    if (debug_el == cur_el) {
+-        syndrome |= 1 << ARM_EL_EC_SHIFT;
-     if (freq != s->timer[id].freq) {
+-    }
-         ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
+-    raise_exception(env, EXCP_UDEF, syndrome, debug_el);
--        DPRINTF("freq=%dHz\n", s->timer[id].freq);
++    raise_exception_debug(env, EXCP_UDEF, syndrome);
 +        DPRINTF("freq=%uHz\n", s->timer[id].freq);
      }
  }
-@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
+ #if !defined(CONFIG_USER_ONLY)
      uint32_t id = s->id;
      bool cmp;
 -    DPRINTF("timer %d tick\n", id);
 +    DPRINTF("timer %u tick\n", id);
      /* set irq status */
      p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
      /* raise IRQ */
      if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
 -        DPRINTF("timer %d IRQ\n", id);
 +        DPRINTF("timer %u IRQ\n", id);
          qemu_irq_raise(p->timer[id].irq);
      }
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
      }
      if (cmp) {
 -        DPRINTF("auto reload timer %d count to %x\n", id,
 +        DPRINTF("auto reload timer %u count to %x\n", id,
                  p->timer[id].reg_tcntb);
          ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
          ptimer_run(p->timer[id].ptimer, 1);
 --
-.20.1
+.25.1

-[PULL 7/9] configure: Make "does libgio work" test pull in some actual functions
+[PULL 22/28] target/arm: Move arm_debug_target_el to debug_helper.c
-In commit 76346b6264a9b01979 we tried to add a configure check that
+From: Richard Henderson <richard.henderson@linaro.org>
 the libgio pkg-config data was correct, which builds an executable
 linked against it.  Unfortunately this doesn't catch the problem
 (missing static library dependency info), because a "do nothing" test
 source file doesn't have any symbol references that cause the linker
 to pull in .o files from libgio.a, and so we don't see the "missing
 symbols from libmount" error that a full QEMU link triggers.
-(The ineffective test went unnoticed because of a typo that
+This function is no longer used outside debug_helper.c.
 effectively disabled libgio unconditionally, but after commit
 a5dfc11f2 fixed that, a static link of the system emulator on
 Ubuntu stopped working again.)
-Improve the gio test by having the test source fragment reference a
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-g_dbus function (which is what is indirectly causing us to end up
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-wanting functions from libmount).
+Message-id: 20220609202901.1177572-23-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h          | 21 ---------------------
  target/arm/debug_helper.c | 21 +++++++++++++++++++++
 files changed, 21 insertions(+), 21 deletions(-)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
+index XXXXXXX..XXXXXXX 100644
-Message-id: 20201116104617.18333-1-peter.maydell@linaro.org
+--- a/target/arm/cpu.h
----
++++ b/target/arm/cpu.h
- configure | 11 +++++++++--
+@@ -XXX,XX +XXX,XX @@ typedef enum ARMASIdx {
-file changed, 9 insertions(+), 2 deletions(-)
+     ARMASIdx_TagS = 3,
+ } ARMASIdx;
-diff --git a/configure b/configure
-index XXXXXXX..XXXXXXX 100755
+-/* Return the Exception Level targeted by debug exceptions. */
---- a/configure
+-static inline int arm_debug_target_el(CPUARMState *env)
-+++ b/configure
+-{
-@@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
+-    bool secure = arm_is_secure(env);
-     # Check that the libraries actually work -- Ubuntu 18.04 ships
+-    bool route_to_el2 = false;
-     # with pkg-config --static --libs data for gio-2.0 that is missing
+-
-     # -lblkid and will give a link error.
+-    if (arm_is_el2_enabled(env)) {
--    write_c_skeleton
+-        route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
--    if compile_prog "" "$gio_libs" ; then
+-                       env->cp15.mdcr_el2 & MDCR_TDE;
-+    cat > $TMPC <<EOF
+-    }
-+#include <gio/gio.h>
+-
-+int main(void)
+-    if (route_to_el2) {
 -        return 2;
 -    } else if (arm_feature(env, ARM_FEATURE_EL3) &&
 -               !arm_el_is_aa64(env, 3) && secure) {
 -        return 3;
 -    } else {
 -        return 1;
 -    }
 -}
 -
  static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
  {
      /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/debug_helper.c
 +++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/helper-proto.h"
 +/* Return the Exception Level targeted by debug exceptions. */
 +static int arm_debug_target_el(CPUARMState *env)
 +{
-+    g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0);
++    bool secure = arm_is_secure(env);
-+    return 0;
++    bool route_to_el2 = false;
 +
 +    if (arm_is_el2_enabled(env)) {
 +        route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
 +                       env->cp15.mdcr_el2 & MDCR_TDE;
 +    }
 +
 +    if (route_to_el2) {
 +        return 2;
 +    } else if (arm_feature(env, ARM_FEATURE_EL3) &&
 +               !arm_el_is_aa64(env, 3) && secure) {
 +        return 3;
 +    } else {
 +        return 1;
 +    }
 +}
-+EOF
++
-+    if compile_prog "$gio_cflags" "$gio_libs" ; then
+ /*
-         gio=yes
+  * Raise an exception to the debug target el.
-     else
+  * Modify syndrome to indicate when origin and target EL are the same.
          gio=no
 --
-.20.1
+.25.1

-[PULL 8/9] hw/misc/tmp105: reset the T_low and T_High registers
+[PULL 23/28] target/arm: Fix Secure PL1 tests in fp_exception_el
-The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the
+From: Richard Henderson <richard.henderson@linaro.org>
 power-up reset values for the T_low and T_high registers are 80 degrees C
 and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5.  These
 values are then shifted right by four bits to give the register reset
 values, since both registers store the 12 bits of temperature data in bits
 [15..4] of a 16 bit register.
-We were resetting these registers to zero, which is problematic for Linux
+We were using arm_is_secure and is_a64, which are
-guests which enable the alert interrupt and then immediately take an
+tests against the current EL, as opposed to
-unexpected overtemperature alert because the current temperature is above
+arm_el_is_aa64 and arm_is_secure_below_el3, which
-freezing...
+can be applied to a different EL than current.
 Consolidate the two tests.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220609202901.1177572-24-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20201110150023.25533-2-peter.maydell@linaro.org
 ---
- hw/misc/tmp105.c | 3 +++
+ target/arm/helper.c | 23 +++++++++--------------
-file changed, 3 insertions(+)
+file changed, 9 insertions(+), 14 deletions(-)
-diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/tmp105.c
+--- a/target/arm/helper.c
-+++ b/hw/misc/tmp105.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
+@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
-     s->faults = tmp105_faultq[(s->config >> 3) & 3];
+         int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN);
-     s->alarm = 0;
+         switch (fpen) {
-+    s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
++        case 1:
-+    s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
++            if (cur_el != 0) {
-+
++                break;
-     tmp105_interrupt_update(s);
++            }
- }
++            /* fall through */
          case 0:
          case 2:
 -            if (cur_el == 0 || cur_el == 1) {
 -                /* Trap to PL1, which might be EL1 or EL3 */
 -                if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
 -                    return 3;
 -                }
 -                return 1;
 -            }
 -            if (cur_el == 3 && !is_a64(env)) {
 -                /* Secure PL1 running at EL3 */
 +            /* Trap from Secure PL0 or PL1 to Secure PL1. */
 +            if (!arm_el_is_aa64(env, 3)
 +                && (cur_el == 3 || arm_is_secure_below_el3(env))) {
                  return 3;
              }
 -            break;
 -        case 1:
 -            if (cur_el == 0) {
 +            if (cur_el <= 1) {
                  return 1;
              }
              break;
 -        case 3:
 -            break;
          }
      }
 --
-.20.1
+.25.1

-[PULL 5/9] register: Remove unnecessary NULL check
+[PULL 24/28] tests/qtest: Reduce npcm7xx_sdhci test image size
-From: Alistair Francis <alistair.francis@wdc.com>
+From: Hao Wu <wuhaotsh@google.com>
-This patch fixes CID 1432800 by removing an unnecessary check.
+Creating 1GB image for a simple qtest is unnecessary
 and could lead to failures. We reduce the image size
 to 1MB to reduce the test overhead.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
 Message-id: 20220609214125.4192212-1-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/core/register.c | 4 ----
+ tests/qtest/npcm7xx_sdhci-test.c | 2 +-
-file changed, 4 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/core/register.c b/hw/core/register.c
+diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/core/register.c
+--- a/tests/qtest/npcm7xx_sdhci-test.c
-+++ b/hw/core/register.c
++++ b/tests/qtest/npcm7xx_sdhci-test.c
-@@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner,
+@@ -XXX,XX +XXX,XX @@
-         int index = rae[i].addr / data_size;
+ #define NPCM7XX_REG_SIZE 0x100
-         RegisterInfo *r = &ri[index];
+ #define NPCM7XX_MMC_BA 0xF0842000
+ #define NPCM7XX_BLK_SIZE 512
--        if (data + data_size * index == 0 || !&rae[i]) {
+-#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30)
--            continue;
++#define NPCM7XX_TEST_IMAGE_SIZE (1 << 20)
--        }
--
+ char *sd_path;
          /* Init the register, this will zero it. */
          object_initialize((void *)r, sizeof(*r), TYPE_REGISTER);
 --
-.20.1
+.25.1

-[PULL 6/9] util/cutils: Fix Coverity array overrun in freq_to_str()
+[PULL 25/28] target/arm: Adjust format test in scr_write
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Richard Henderson <richard.henderson@linaro.org>
-Fix Coverity CID 1435957:  Memory - illegal accesses (OVERRUN):
+Because reset always initializes the AA64 version, SCR_EL3,
 test the mode of EL3 instead of the type of the cpreg.
->>> Overrunning array "suffixes" of 7 8-byte elements at element
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-    index 7 (byte offset 63) using index "idx" (which evaluates to 7).
+Message-id: 20220609214657.1217913-2-richard.henderson@linaro.org
 Note, the biggest input value freq_to_str() can accept is UINT64_MAX,
 which is ~18.446 EHz, less than 1000 EHz.
 Reported-by: Eduardo Habkost <ehabkost@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
-Reviewed-by: Luc Michel <luc@lmichel.fr>
-Message-id: 20201101215755.2021421-1-f4bug@amsat.org
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- util/cutils.c | 3 ++-
+ target/arm/helper.c | 14 ++++++++------
-file changed, 2 insertions(+), 1 deletion(-)
+file changed, 8 insertions(+), 6 deletions(-)
-diff --git a/util/cutils.c b/util/cutils.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/util/cutils.c
+--- a/target/arm/helper.c
-+++ b/util/cutils.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz)
+@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
-     double freq = freq_hz;
+     uint32_t valid_mask = 0x3fff;
-     size_t idx = 0;
+     ARMCPU *cpu = env_archcpu(env);
--    while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) {
+-    if (ri->state == ARM_CP_STATE_AA64) {
-+    while (freq >= 1000.0) {
+-        if (arm_feature(env, ARM_FEATURE_AARCH64) &&
-         freq /= 1000.0;
+-            !cpu_isar_feature(aa64_aa32_el1, cpu)) {
-         idx++;
+-                value |= SCR_FW | SCR_AW;   /* these two bits are RES1.  */
-     }
+-        }
-+    assert(idx < ARRAY_SIZE(suffixes));
+-        valid_mask &= ~SCR_NET;
++    /*
-     return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]);
++     * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
- }
++     * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
 +     * Instead, choose the format based on the mode of EL3.
 +     */
 +    if (arm_el_is_aa64(env, 3)) {
 +        value |= SCR_FW | SCR_AW;      /* RES1 */
 +        valid_mask &= ~SCR_NET;        /* RES0 */
          if (cpu_isar_feature(aa64_ras, cpu)) {
              valid_mask |= SCR_TERR;
 --
-.20.1
+.25.1

-[PULL 1/9] hw/arm/virt: ARM_VIRT must select ARM_GIC
+[PULL 26/28] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]
-From: Andrew Jones <drjones@redhat.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-The removal of the selection of A15MPCORE from ARM_VIRT also
+Since DDI0487F.a, the RW bit is RAO/WI.  When specifically
-removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC.
+targeting such a cpu, e.g. cortex-a76, it is legitimate to
 ignore the bit within the secure monitor.
-Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals")
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062
-Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Andrew Jones <drjones@redhat.com>
+Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org
-Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20201111143440.112763-1-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/Kconfig | 1 +
+ target/arm/cpu.h    | 5 +++++
-file changed, 1 insertion(+)
+ target/arm/helper.c | 4 ++++
 files changed, 9 insertions(+)
-diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/Kconfig
+--- a/target/arm/cpu.h
-+++ b/hw/arm/Kconfig
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
+@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
-     imply VFIO_PLATFORM
+     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
-     imply VFIO_XGMAC
+ }
-     imply TPM_TIS_SYSBUS
-+    select ARM_GIC
++static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
-     select ACPI
++{
-     select ARM_SMMUV3
++    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
-     select GPIO_KEY
++}
 +
  static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
  {
      return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
          value |= SCR_FW | SCR_AW;      /* RES1 */
          valid_mask &= ~SCR_NET;        /* RES0 */
 +        if (!cpu_isar_feature(aa64_aa32_el1, cpu) &&
 +            !cpu_isar_feature(aa64_aa32_el2, cpu)) {
 +            value |= SCR_RW;           /* RAO/WI */
 +        }
          if (cpu_isar_feature(aa64_ras, cpu)) {
              valid_mask |= SCR_TERR;
          }
 --
-.20.1
+.25.1

-[PULL 4/9] target/openrisc: Remove dead code attempting to check "is timer disabled"
+[PULL 27/28] gdbstub: Don't use GDB syscalls if no GDB is attached
-In the mtspr helper we attempt to check for "is the timer disabled"
+In two places in gdbstub.c we look at gdbserver_state.init to decide
-with "if (env->ttmr & TIMER_NONE)".  This is wrong because TIMER_NONE
+whether we're going to do a semihosting syscall via the gdb remote
-is zero and the condition is always false (Coverity complains about
+protocol:
-the dead code.)
+ * when setting up, if the user didn't explicitly select either
    native semihosting or gdb semihosting, we autoselect, with the
    intended behaviour "use gdb if gdb is connected"
  * when the semihosting layer attempts to do a syscall via gdb, we
    silently ignore it if the gdbstub wasn't actually set up
-The correct check would be to test whether the TTMR_M field in the
+However, if the user's commandline sets up the gdbstub but tells QEMU
-register is equal to TIMER_NONE instead.  However, the
+to start rather than waiting for a GDB to connect (eg using '-s' but
-cpu_openrisc_timer_update() function checks whether the timer is
+not '-S'), then we will have gdbserver_state.init true but no actual
-enabled (it looks at cpu->env.is_counting, which is set to 0 via
+connection; an attempt to use gdb syscalls will then crash because we
-cpu_openrisc_count_stop() when the TTMR_M field is set to
+try to use gdbserver_state.c_cpu when it hasn't been set up:
 TIMER_NONE), so there's no need to check for "timer disabled" in the
 target/openrisc code.  Instead, simply remove the dead code.
-Fixes: Coverity CID 1005812
+#0  0x00007ffff6803ba8 in qemu_cpu_kick (cpu=0x0) at ../../softmmu/cpus.c:457
 #1  0x00007ffff6c03913 in gdb_do_syscallv (cb=0x7ffff6c19944 <common_semi_cb>,
     fmt=0x7ffff7573b7e "", va=0x7ffff56294c0) at ../../gdbstub.c:2946
 #2  0x00007ffff6c19c3a in common_semi_gdb_syscall (cs=0x7ffff83fe060,
     cb=0x7ffff6c19944 <common_semi_cb>, fmt=0x7ffff7573b75 "isatty,%x")
     at ../../semihosting/arm-compat-semi.c:494
 #3  0x00007ffff6c1a064 in gdb_isattyfn (cs=0x7ffff83fe060, gf=0x7ffff86a3690)
     at ../../semihosting/arm-compat-semi.c:636
 #4  0x00007ffff6c1b20f in do_common_semihosting (cs=0x7ffff83fe060)
     at ../../semihosting/arm-compat-semi.c:967
 #5  0x00007ffff693a037 in handle_semihosting (cs=0x7ffff83fe060)
     at ../../target/arm/helper.c:10316
 You can probably also get into this state via some odd
 corner cases involving connecting a GDB and then telling it
 to detach from all the vCPUs.
 Abstract out the test into a new gdb_attached() function
 which returns true only if there's actually a GDB connected
 to the debug stub and attached to at least one vCPU.
 Reported-by: Liviu Ionescu <ilg@livius.net>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Acked-by: Stafford Horne <shorne@gmail.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20201103114654.18540-1-peter.maydell@linaro.org
+Reviewed-by: Luc Michel <luc@lmichel.fr>
 Message-id: 20220526190053.521505-2-peter.maydell@linaro.org
 ---
- target/openrisc/sys_helper.c | 3 ---
+ gdbstub.c | 14 +++++++++++---
-file changed, 3 deletions(-)
+file changed, 11 insertions(+), 3 deletions(-)
-diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
+diff --git a/gdbstub.c b/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/openrisc/sys_helper.c
+--- a/gdbstub.c
-+++ b/target/openrisc/sys_helper.c
++++ b/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
+@@ -XXX,XX +XXX,XX @@ static int get_char(void)
+ }
      case TO_SPR(10, 1): /* TTCR */
          cpu_openrisc_count_set(cpu, rb);
 -        if (env->ttmr & TIMER_NONE) {
 -            return;
 -        }
          cpu_openrisc_timer_update(cpu);
          break;
  #endif
++/*
++ * Return true if there is a GDB currently connected to the stub
++ * and attached to a CPU
++ */
++static bool gdb_attached(void)
++{
++    return gdbserver_state.init && gdbserver_state.c_cpu;
++}
++
+ static enum {
+     GDB_SYS_UNKNOWN,
+     GDB_SYS_ENABLED,
+@@ -XXX,XX +XXX,XX @@ int use_gdb_syscalls(void)
+     /* -semihosting-config target=auto */
+     /* On the first call check if gdb is connected and remember. */
+     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
+-        gdb_syscall_mode = gdbserver_state.init ?
+-            GDB_SYS_ENABLED : GDB_SYS_DISABLED;
++        gdb_syscall_mode = gdb_attached() ? GDB_SYS_ENABLED : GDB_SYS_DISABLED;
+     }
+     return gdb_syscall_mode == GDB_SYS_ENABLED;
+ }
+@@ -XXX,XX +XXX,XX @@ void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va)
+     target_ulong addr;
+     uint64_t i64;
+-    if (!gdbserver_state.init) {
++    if (!gdb_attached()) {
+         return;
+     }
 --
-.20.1
+.25.1

-[PULL 3/9] hw/input/ps2.c: Remove remnants of printf debug
+[PULL 28/28] semihosting/config: Merge --semihosting-config option groups
-In commit 5edab03d4040 we added tracepoints to the ps2 keyboard
+Currently we mishandle the --semihosting-config option if the
-and mouse emulation. However we didn't remove all the debug-by-printf
+user specifies it on the command line more than once. For
-support. In fact there is only one printf() remaining, and it is
+example with:
-redundant with the trace_ps2_write_mouse() event next to it.
+ --semihosting-config target=gdb --semihosting-config arg=foo,arg=bar
-Remove the printf() and the now-unused DEBUG* macros.
 the function qemu_semihosting_config_options() is called twice, once
 for each argument.  But that function expects to be called only once,
 and it always unconditionally sets the semihosting.enabled,
 semihost_chardev and semihosting.target variables.  This means that
 if any of those options were set anywhere except the last
 --semihosting-config option on the command line, those settings are
 ignored.  In the example above, 'target=gdb' in the first option is
 overridden by an implied default 'target=auto' in the second.
 The QemuOptsList machinery has a flag for handling this kind of
 "option group is setting global state": by setting
  .merge_lists = true;
 we make the machinery merge all the --semihosting-config arguments
 the user passes into a single set of options and call our
 qemu_semihosting_config_options() just once.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Luc Michel <luc@lmichel.fr>
-Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
+Message-id: 20220526190053.521505-3-peter.maydell@linaro.org
 Message-id: 20201101133258.4240-1-peter.maydell@linaro.org
 ---
- hw/input/ps2.c | 9 ---------
+ semihosting/config.c | 1 +
-file changed, 9 deletions(-)
+file changed, 1 insertion(+)
-diff --git a/hw/input/ps2.c b/hw/input/ps2.c
+diff --git a/semihosting/config.c b/semihosting/config.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/input/ps2.c
+--- a/semihosting/config.c
-+++ b/hw/input/ps2.c
++++ b/semihosting/config.c
 @@ -XXX,XX +XXX,XX @@
- #include "trace.h"
+ QemuOptsList qemu_semihosting_config_opts = {
+     .name = "semihosting-config",
--/* debug PC keyboard */
++    .merge_lists = true,
--//#define DEBUG_KBD
+     .implied_opt_name = "enable",
--
+     .head = QTAILQ_HEAD_INITIALIZER(qemu_semihosting_config_opts.head),
--/* debug PC keyboard : only mouse */
+     .desc = {
 -//#define DEBUG_MOUSE
 -
  /* Keyboard Commands */
  #define KBD_CMD_SET_LEDS    0xED    /* Set keyboard leds */
  #define KBD_CMD_ECHO         0xEE
@@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val)
      PS2MouseState *s = (PS2MouseState *)opaque;
      trace_ps2_write_mouse(opaque, val);
 -#ifdef DEBUG_MOUSE
 -    printf("kbd: write mouse 0x%02x\n", val);
 -#endif
      switch(s->common.write_cmd) {
      default:
      case -1:
 --
-.20.1
+.25.1

Arm queue; bugfixes only.

thanks
-- PMM

The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739:

Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117

for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42:

tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/virt: ARM_VIRT must select ARM_GIC
 * exynos: Fix bad printf format specifiers
 * hw/input/ps2.c: Remove remnants of printf debug
 * target/openrisc: Remove dead code attempting to check "is timer disabled"
 * register: Remove unnecessary NULL check
 * util/cutils: Fix Coverity array overrun in freq_to_str()
 * configure: Make "does libgio work" test pull in some actual functions
 * tmp105: reset the T_low and T_High registers
 * tmp105: Correct handling of temperature limit checks

----------------------------------------------------------------
Alex Chen (1):
      exynos: Fix bad printf format specifiers

Alistair Francis (1):
      register: Remove unnecessary NULL check

Andrew Jones (1):
      hw/arm/virt: ARM_VIRT must select ARM_GIC

Peter Maydell (5):
      hw/input/ps2.c: Remove remnants of printf debug
      target/openrisc: Remove dead code attempting to check "is timer disabled"
      configure: Make "does libgio work" test pull in some actual functions
      hw/misc/tmp105: reset the T_low and T_High registers
      tmp105: Correct handling of temperature limit checks

Philippe Mathieu-Daudé (1):
      util/cutils: Fix Coverity array overrun in freq_to_str()

From: Alex Chen <alex.chen@huawei.com>

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201111073651.72804-1-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/exynos4210_mct.c | 4 ++--
 hw/timer/exynos4210_pwm.c | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
     /* If CSTAT is pending and IRQ is enabled */
     if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
             (s->reg.int_enb & G_INT_ENABLE(id))) {
-        DPRINTF("gcmp timer[%d] IRQ\n", id);
+        DPRINTF("gcmp timer[%u] IRQ\n", id);
         qemu_irq_raise(s->irq[id]);
     }
 }
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
                     MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
 
     if (freq != s->freq) {
-        DPRINTF("freq=%dHz\n", s->freq);
+        DPRINTF("freq=%uHz\n", s->freq);
 
         /* global timer */
         tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/exynos4210_pwm.c
+++ b/hw/timer/exynos4210_pwm.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
 
     if (freq != s->timer[id].freq) {
         ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
-        DPRINTF("freq=%dHz\n", s->timer[id].freq);
+        DPRINTF("freq=%uHz\n", s->timer[id].freq);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
     uint32_t id = s->id;
     bool cmp;
 
-    DPRINTF("timer %d tick\n", id);
+    DPRINTF("timer %u tick\n", id);
 
     /* set irq status */
     p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
 
     /* raise IRQ */
     if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
-        DPRINTF("timer %d IRQ\n", id);
+        DPRINTF("timer %u IRQ\n", id);
         qemu_irq_raise(p->timer[id].irq);
     }
 
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
     }
 
     if (cmp) {
-        DPRINTF("auto reload timer %d count to %x\n", id,
+        DPRINTF("auto reload timer %u count to %x\n", id,
                 p->timer[id].reg_tcntb);
         ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
         ptimer_run(p->timer[id].ptimer, 1);
-- 
2.20.1

In commit 5edab03d4040 we added tracepoints to the ps2 keyboard
and mouse emulation. However we didn't remove all the debug-by-printf
support. In fact there is only one printf() remaining, and it is
redundant with the trace_ps2_write_mouse() event next to it.
Remove the printf() and the now-unused DEBUG* macros.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-id: 20201101133258.4240-1-peter.maydell@linaro.org
---
 hw/input/ps2.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/hw/input/ps2.c b/hw/input/ps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/input/ps2.c
+++ b/hw/input/ps2.c
@@ -XXX,XX +XXX,XX @@
 
 #include "trace.h"
 
-/* debug PC keyboard */
-//#define DEBUG_KBD
-
-/* debug PC keyboard : only mouse */
-//#define DEBUG_MOUSE
-
 /* Keyboard Commands */
 #define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
 #define KBD_CMD_ECHO     	0xEE
@@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val)
     PS2MouseState *s = (PS2MouseState *)opaque;
 
     trace_ps2_write_mouse(opaque, val);
-#ifdef DEBUG_MOUSE
-    printf("kbd: write mouse 0x%02x\n", val);
-#endif
     switch(s->common.write_cmd) {
     default:
     case -1:
-- 
2.20.1

In the mtspr helper we attempt to check for "is the timer disabled"
with "if (env->ttmr & TIMER_NONE)".  This is wrong because TIMER_NONE
is zero and the condition is always false (Coverity complains about
the dead code.)

The correct check would be to test whether the TTMR_M field in the
register is equal to TIMER_NONE instead.  However, the
cpu_openrisc_timer_update() function checks whether the timer is
enabled (it looks at cpu->env.is_counting, which is set to 0 via
cpu_openrisc_count_stop() when the TTMR_M field is set to
TIMER_NONE), so there's no need to check for "timer disabled" in the
target/openrisc code.  Instead, simply remove the dead code.

Fixes: Coverity CID 1005812
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Stafford Horne <shorne@gmail.com>
Message-id: 20201103114654.18540-1-peter.maydell@linaro.org
---
 target/openrisc/sys_helper.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
 
     case TO_SPR(10, 1): /* TTCR */
         cpu_openrisc_count_set(cpu, rb);
-        if (env->ttmr & TIMER_NONE) {
-            return;
-        }
         cpu_openrisc_timer_update(cpu);
         break;
 #endif
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Fix Coverity CID 1435957:  Memory - illegal accesses (OVERRUN):

>>> Overrunning array "suffixes" of 7 8-byte elements at element
    index 7 (byte offset 63) using index "idx" (which evaluates to 7).

Note, the biggest input value freq_to_str() can accept is UINT64_MAX,
which is ~18.446 EHz, less than 1000 EHz.

Reported-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20201101215755.2021421-1-f4bug@amsat.org
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 util/cutils.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/util/cutils.c b/util/cutils.c
index XXXXXXX..XXXXXXX 100644
--- a/util/cutils.c
+++ b/util/cutils.c
@@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz)
     double freq = freq_hz;
     size_t idx = 0;
 
-    while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) {
+    while (freq >= 1000.0) {
         freq /= 1000.0;
         idx++;
     }
+    assert(idx < ARRAY_SIZE(suffixes));
 
     return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]);
 }
-- 
2.20.1

In commit 76346b6264a9b01979 we tried to add a configure check that
the libgio pkg-config data was correct, which builds an executable
linked against it.  Unfortunately this doesn't catch the problem
(missing static library dependency info), because a "do nothing" test
source file doesn't have any symbol references that cause the linker
to pull in .o files from libgio.a, and so we don't see the "missing
symbols from libmount" error that a full QEMU link triggers.

(The ineffective test went unnoticed because of a typo that
effectively disabled libgio unconditionally, but after commit
3569a5dfc11f2 fixed that, a static link of the system emulator on
Ubuntu stopped working again.)

Improve the gio test by having the test source fragment reference a
g_dbus function (which is what is indirectly causing us to end up
wanting functions from libmount).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20201116104617.18333-1-peter.maydell@linaro.org
---
 configure | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/configure b/configure
index XXXXXXX..XXXXXXX 100755
--- a/configure
+++ b/configure
@@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
     # Check that the libraries actually work -- Ubuntu 18.04 ships
     # with pkg-config --static --libs data for gio-2.0 that is missing
     # -lblkid and will give a link error.
-    write_c_skeleton
-    if compile_prog "" "$gio_libs" ; then
+    cat > $TMPC <<EOF
+#include <gio/gio.h>
+int main(void)
+{
+    g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0);
+    return 0;
+}
+EOF
+    if compile_prog "$gio_cflags" "$gio_libs" ; then
         gio=yes
     else
         gio=no
-- 
2.20.1

The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the
power-up reset values for the T_low and T_high registers are 80 degrees C
and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5.  These
values are then shifted right by four bits to give the register reset
values, since both registers store the 12 bits of temperature data in bits
[15..4] of a 16 bit register.

We were resetting these registers to zero, which is problematic for Linux
guests which enable the alert interrupt and then immediately take an
unexpected overtemperature alert because the current temperature is above
freezing...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20201110150023.25533-2-peter.maydell@linaro.org
---
 hw/misc/tmp105.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/tmp105.c
+++ b/hw/misc/tmp105.c
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
     s->faults = tmp105_faultq[(s->config >> 3) & 3];
     s->alarm = 0;
 
+    s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
+    s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
+
     tmp105_interrupt_update(s);
 }
 
-- 
2.20.1

The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device
signals an alert when the temperature equals or exceeds the T_high value and
then remains high until a device register is read or the device responds to
the SMBUS Alert Response address, or the device is put into Shutdown Mode.
Thereafter the Alert pin will only be re-signalled when temperature falls
below T_low; alert can then be cleared in the same set of ways, and the
device returns to its initial "alert when temperature goes above T_high"
mode. (If this textual description is confusing, see figure 3 in the
TI datasheet at https://www.ti.com/lit/gpn/tmp105 .)

We were misimplementing this as a simple "always alert if temperature is
above T_high or below T_low" condition, which gives a spurious alert on
startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset
limit values.

Implement the correct (hysteresis) behaviour by tracking whether we
are currently looking for the temperature to rise over T_high or
for it to fall below T_low. Our implementation of the comparator
mode (TM==0) wasn't wrong, but rephrase it to match the way that
interrupt mode is now handled for clarity.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20201110150023.25533-3-peter.maydell@linaro.org
---
 hw/misc/tmp105.h |  7 +++++
 hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++-------
 2 files changed, 68 insertions(+), 9 deletions(-)

diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/tmp105.h
+++ b/hw/misc/tmp105.h
@@ -XXX,XX +XXX,XX @@ struct TMP105State {
     int16_t limit[2];
     int faults;
     uint8_t alarm;
+    /*
+     * The TMP105 initially looks for a temperature rising above T_high;
+     * once this is detected, the condition it looks for next is the
+     * temperature falling below T_low. This flag is false when initially
+     * looking for T_high, true when looking for T_low.
+     */
+    bool detect_falling;
 };
 
 #endif
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/tmp105.c
+++ b/hw/misc/tmp105.c
@@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s)
             return;
     }
 
-    if ((s->config >> 1) & 1) {					/* TM */
-        if (s->temperature >= s->limit[1])
-            s->alarm = 1;
-        else if (s->temperature < s->limit[0])
-            s->alarm = 1;
+    if (s->config >> 1 & 1) {
+        /*
+         * TM == 1 : Interrupt mode. We signal Alert when the
+         * temperature rises above T_high, and expect the guest to clear
+         * it (eg by reading a device register).
+         */
+        if (s->detect_falling) {
+            if (s->temperature < s->limit[0]) {
+                s->alarm = 1;
+                s->detect_falling = false;
+            }
+        } else {
+            if (s->temperature >= s->limit[1]) {
+                s->alarm = 1;
+                s->detect_falling = true;
+            }
+        }
     } else {
-        if (s->temperature >= s->limit[1])
-            s->alarm = 1;
-        else if (s->temperature < s->limit[0])
-            s->alarm = 0;
+        /*
+         * TM == 0 : Comparator mode. We signal Alert when the temperature
+         * rises above T_high, and stop signalling it when the temperature
+         * falls below T_low.
+         */
+        if (s->detect_falling) {
+            if (s->temperature < s->limit[0]) {
+                s->alarm = 0;
+                s->detect_falling = false;
+            }
+        } else {
+            if (s->temperature >= s->limit[1]) {
+                s->alarm = 1;
+                s->detect_falling = true;
+            }
+        }
     }
 
     tmp105_interrupt_update(s);
@@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id)
     return 0;
 }
 
+static bool detect_falling_needed(void *opaque)
+{
+    TMP105State *s = opaque;
+
+    /*
+     * We only need to migrate the detect_falling bool if it's set;
+     * for migration from older machines we assume that it is false
+     * (ie temperature is not out of range).
+     */
+    return s->detect_falling;
+}
+
+static const VMStateDescription vmstate_tmp105_detect_falling = {
+    .name = "TMP105/detect-falling",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = detect_falling_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_BOOL(detect_falling, TMP105State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_tmp105 = {
     .name = "TMP105",
     .version_id = 0,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = {
         VMSTATE_UINT8(alarm, TMP105State),
         VMSTATE_I2C_SLAVE(i2c, TMP105State),
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription*[]) {
+        &vmstate_tmp105_detect_falling,
+        NULL
     }
 };
 
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
     s->config = 0;
     s->faults = tmp105_faultq[(s->config >> 3) & 3];
     s->alarm = 0;
+    s->detect_falling = false;
 
     s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
     s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
-- 
2.20.1

Just flushing my target-arm queue since I won't be working next week :-)

-- PMM

The following changes since commit b3cd3b5a66f0dddfe3d5ba2bef13cd4f5b89cde9:

Merge tag 'pull-riscv-to-apply-20220610' of github.com:alistair23/qemu into staging (2022-06-09 22:08:27 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220610

for you to fetch changes up to 90c072e063737e9e8f431489bbd334452f89056e:

semihosting/config: Merge --semihosting-config option groups (2022-06-10 14:32:36 +0100)

----------------------------------------------------------------
 * refactor exception routing code
 * fix SCR_EL3 RAO/RAZ bits
 * gdbstub: Don't use GDB syscalls if no GDB is attached
 * semihosting/config: Merge --semihosting-config option groups
 * tests/qtest: Reduce npcm7xx_sdhci test image size

----------------------------------------------------------------
Hao Wu (1):
      tests/qtest: Reduce npcm7xx_sdhci test image size

Peter Maydell (2):
      gdbstub: Don't use GDB syscalls if no GDB is attached
      semihosting/config: Merge --semihosting-config option groups

Richard Henderson (25):
      target/arm: Mark exception helpers as noreturn
      target/arm: Add coproc parameter to syn_fp_access_trap
      target/arm: Move exception_target_el out of line
      target/arm: Move arm_singlestep_active out of line
      target/arm: Move arm_generate_debug_exceptions out of line
      target/arm: Use is_a64 in arm_generate_debug_exceptions
      target/arm: Move exception_bkpt_insn to debug_helper.c
      target/arm: Move arm_debug_exception_fsr to debug_helper.c
      target/arm: Rename helper_exception_with_syndrome
      target/arm: Introduce gen_exception_insn_el_v
      target/arm: Rename gen_exception_insn to gen_exception_insn_el
      target/arm: Introduce gen_exception_insn
      target/arm: Create helper_exception_swstep
      target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL
      target/arm: Move gen_exception to translate.c
      target/arm: Rename gen_exception to gen_exception_el
      target/arm: Introduce gen_exception
      target/arm: Introduce gen_exception_el_v
      target/arm: Introduce helper_exception_with_syndrome
      target/arm: Remove default_exception_el
      target/arm: Create raise_exception_debug
      target/arm: Move arm_debug_target_el to debug_helper.c
      target/arm: Fix Secure PL1 tests in fp_exception_el
      target/arm: Adjust format test in scr_write
      target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12]

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

With ARMv8, this field is always RES0.
With ARMv7, targeting EL2 and TA=0, it is always 0xA.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/syndrome.h      |  7 ++++---
 target/arm/translate-a64.c |  3 ++-
 target/arm/translate-vfp.c | 14 ++++++++++++--
 3 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
         | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
 }
 
-static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
+static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,
+                                          int coproc)
 {
-    /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */
+    /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */
     return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
         | (is_16bit ? 0 : ARM_EL_IL)
-        | (cv << 24) | (cond << 20) | 0xa;
+        | (cv << 24) | (cond << 20) | coproc;
 }
 
 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
         s->fp_access_checked = true;
 
         gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
+                           syn_fp_access_trap(1, 0xe, false, 0),
+                           s->fp_excp_el);
         return false;
     }
     s->fp_access_checked = true;
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s)
 static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
 {
     if (s->fp_excp_el) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
+        /*
+         * The full syndrome is only used for HSR when HCPTR traps:
+         * For v8, when TA==0, coproc is RES0.
+         * For v7, any use of a Floating-point instruction or access
+         * to a Floating-point Extension register that is trapped to
+         * Hyp mode because of a trap configured in the HCPTR sets
+         * this field to 0xA.
+         */
+        int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
+        uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
+
+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
         return false;
     }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the function to op_helper.c, near raise_exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 16 +---------------
 target/arm/op_helper.c | 15 +++++++++++++++
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
 int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx);
 int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx);
 
-static inline int exception_target_el(CPUARMState *env)
-{
-    int target_el = MAX(1, arm_current_el(env));
-
-    /*
-     * No such thing as secure EL1 if EL3 is aarch32,
-     * so update the target EL to EL3 in this case.
-     */
-    if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
-        target_el = 3;
-    }
-
-    return target_el;
-}
-
 /* Determine if allocation tags are available.  */
 static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
                                                  uint64_t sctlr)
@@ -XXX,XX +XXX,XX @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 bool el_is_in_host(CPUARMState *env, int el);
 
 void aa32_max_features(ARMCPU *cpu);
+int exception_target_el(CPUARMState *env);
 
 /* Powers of 2 for sve_vq_map et al. */
 #define SVE_VQ_POW2_MAP                                 \
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@
 #define SIGNBIT (uint32_t)0x80000000
 #define SIGNBIT64 ((uint64_t)1 << 63)
 
+int exception_target_el(CPUARMState *env)
+{
+    int target_el = MAX(1, arm_current_el(env));
+
+    /*
+     * No such thing as secure EL1 if EL3 is aarch32,
+     * so update the target EL to EL3 in this case.
+     */
+    if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
+        target_el = 3;
+    }
+
+    return target_el;
+}
+
 void raise_exception(CPUARMState *env, uint32_t excp,
                      uint32_t syndrome, uint32_t target_el)
 {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the function to debug_helper.c, and the
declaration to internals.h.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h          | 10 ----------
 target/arm/internals.h    |  1 +
 target/arm/debug_helper.c | 12 ++++++++++++
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool arm_generate_debug_exceptions(CPUARMState *env)
     }
 }
 
-/* Is single-stepping active? (Note that the "is EL_D AArch64?" check
- * implicitly means this always returns false in pre-v8 CPUs.)
- */
-static inline bool arm_singlestep_active(CPUARMState *env)
-{
-    return extract32(env->cp15.mdscr_el1, 0, 1)
-        && arm_el_is_aa64(env, arm_debug_target_el(env))
-        && arm_generate_debug_exceptions(env);
-}
-
 static inline bool arm_sctlr_b(CPUARMState *env)
 {
     return
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el);
 
 void aa32_max_features(ARMCPU *cpu);
 int exception_target_el(CPUARMState *env);
+bool arm_singlestep_active(CPUARMState *env);
 
 /* Powers of 2 for sve_vq_map et al. */
 #define SVE_VQ_POW2_MAP                                 \
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 
+
+/*
+ * Is single-stepping active? (Note that the "is EL_D AArch64?" check
+ * implicitly means this always returns false in pre-v8 CPUs.)
+ */
+bool arm_singlestep_active(CPUARMState *env)
+{
+    return extract32(env->cp15.mdscr_el1, 0, 1)
+        && arm_el_is_aa64(env, arm_debug_target_el(env))
+        && arm_generate_debug_exceptions(env);
+}
+
 /* Return true if the linked breakpoint entry lbn passes its checks */
 static bool linked_bp_matches(ARMCPU *cpu, int lbn)
 {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move arm_generate_debug_exceptions and its two subroutines,
{aa32,aa64}_generate_debug_exceptions into debug_helper.c,
and the one interface declaration to internals.h.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h          | 91 -------------------------------------
 target/arm/internals.h    |  1 +
 target/arm/debug_helper.c | 94 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 95 insertions(+), 91 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
     return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
 }
 
-/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
-static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
-{
-    int cur_el = arm_current_el(env);
-    int debug_el;
-
-    if (cur_el == 3) {
-        return false;
-    }
-
-    /* MDCR_EL3.SDD disables debug events from Secure state */
-    if (arm_is_secure_below_el3(env)
-        && extract32(env->cp15.mdcr_el3, 16, 1)) {
-        return false;
-    }
-
-    /*
-     * Same EL to same EL debug exceptions need MDSCR_KDE enabled
-     * while not masking the (D)ebug bit in DAIF.
-     */
-    debug_el = arm_debug_target_el(env);
-
-    if (cur_el == debug_el) {
-        return extract32(env->cp15.mdscr_el1, 13, 1)
-            && !(env->daif & PSTATE_D);
-    }
-
-    /* Otherwise the debug target needs to be a higher EL */
-    return debug_el > cur_el;
-}
-
-static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
-{
-    int el = arm_current_el(env);
-
-    if (el == 0 && arm_el_is_aa64(env, 1)) {
-        return aa64_generate_debug_exceptions(env);
-    }
-
-    if (arm_is_secure(env)) {
-        int spd;
-
-        if (el == 0 && (env->cp15.sder & 1)) {
-            /* SDER.SUIDEN means debug exceptions from Secure EL0
-             * are always enabled. Otherwise they are controlled by
-             * SDCR.SPD like those from other Secure ELs.
-             */
-            return true;
-        }
-
-        spd = extract32(env->cp15.mdcr_el3, 14, 2);
-        switch (spd) {
-        case 1:
-            /* SPD == 0b01 is reserved, but behaves as 0b00. */
-        case 0:
-            /* For 0b00 we return true if external secure invasive debug
-             * is enabled. On real hardware this is controlled by external
-             * signals to the core. QEMU always permits debug, and behaves
-             * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
-             */
-            return true;
-        case 2:
-            return false;
-        case 3:
-            return true;
-        }
-    }
-
-    return el != 2;
-}
-
-/* Return true if debugging exceptions are currently enabled.
- * This corresponds to what in ARM ARM pseudocode would be
- *    if UsingAArch32() then
- *        return AArch32.GenerateDebugExceptions()
- *    else
- *        return AArch64.GenerateDebugExceptions()
- * We choose to push the if() down into this function for clarity,
- * since the pseudocode has it at all callsites except for the one in
- * CheckSoftwareStep(), where it is elided because both branches would
- * always return the same value.
- */
-static inline bool arm_generate_debug_exceptions(CPUARMState *env)
-{
-    if (env->aarch64) {
-        return aa64_generate_debug_exceptions(env);
-    } else {
-        return aa32_generate_debug_exceptions(env);
-    }
-}
-
 static inline bool arm_sctlr_b(CPUARMState *env)
 {
     return
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el);
 void aa32_max_features(ARMCPU *cpu);
 int exception_target_el(CPUARMState *env);
 bool arm_singlestep_active(CPUARMState *env);
+bool arm_generate_debug_exceptions(CPUARMState *env);
 
 /* Powers of 2 for sve_vq_map et al. */
 #define SVE_VQ_POW2_MAP                                 \
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 
 
+/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
+static bool aa64_generate_debug_exceptions(CPUARMState *env)
+{
+    int cur_el = arm_current_el(env);
+    int debug_el;
+
+    if (cur_el == 3) {
+        return false;
+    }
+
+    /* MDCR_EL3.SDD disables debug events from Secure state */
+    if (arm_is_secure_below_el3(env)
+        && extract32(env->cp15.mdcr_el3, 16, 1)) {
+        return false;
+    }
+
+    /*
+     * Same EL to same EL debug exceptions need MDSCR_KDE enabled
+     * while not masking the (D)ebug bit in DAIF.
+     */
+    debug_el = arm_debug_target_el(env);
+
+    if (cur_el == debug_el) {
+        return extract32(env->cp15.mdscr_el1, 13, 1)
+            && !(env->daif & PSTATE_D);
+    }
+
+    /* Otherwise the debug target needs to be a higher EL */
+    return debug_el > cur_el;
+}
+
+static bool aa32_generate_debug_exceptions(CPUARMState *env)
+{
+    int el = arm_current_el(env);
+
+    if (el == 0 && arm_el_is_aa64(env, 1)) {
+        return aa64_generate_debug_exceptions(env);
+    }
+
+    if (arm_is_secure(env)) {
+        int spd;
+
+        if (el == 0 && (env->cp15.sder & 1)) {
+            /*
+             * SDER.SUIDEN means debug exceptions from Secure EL0
+             * are always enabled. Otherwise they are controlled by
+             * SDCR.SPD like those from other Secure ELs.
+             */
+            return true;
+        }
+
+        spd = extract32(env->cp15.mdcr_el3, 14, 2);
+        switch (spd) {
+        case 1:
+            /* SPD == 0b01 is reserved, but behaves as 0b00. */
+        case 0:
+            /*
+             * For 0b00 we return true if external secure invasive debug
+             * is enabled. On real hardware this is controlled by external
+             * signals to the core. QEMU always permits debug, and behaves
+             * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
+             */
+            return true;
+        case 2:
+            return false;
+        case 3:
+            return true;
+        }
+    }
+
+    return el != 2;
+}
+
+/*
+ * Return true if debugging exceptions are currently enabled.
+ * This corresponds to what in ARM ARM pseudocode would be
+ *    if UsingAArch32() then
+ *        return AArch32.GenerateDebugExceptions()
+ *    else
+ *        return AArch64.GenerateDebugExceptions()
+ * We choose to push the if() down into this function for clarity,
+ * since the pseudocode has it at all callsites except for the one in
+ * CheckSoftwareStep(), where it is elided because both branches would
+ * always return the same value.
+ */
+bool arm_generate_debug_exceptions(CPUARMState *env)
+{
+    if (env->aarch64) {
+        return aa64_generate_debug_exceptions(env);
+    } else {
+        return aa32_generate_debug_exceptions(env);
+    }
+}
+
 /*
  * Is single-stepping active? (Note that the "is EL_D AArch64?" check
  * implicitly means this always returns false in pre-v8 CPUs.)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/debug_helper.c | 31 +++++++++++++++++++++++++++++++
 target/arm/op_helper.c    | 29 -----------------------------
 2 files changed, 31 insertions(+), 29 deletions(-)

diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
     }
 }
 
+/*
+ * Raise an EXCP_BKPT with the specified syndrome register value,
+ * targeting the correct exception level for debug exceptions.
+ */
+void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
+{
+    int debug_el = arm_debug_target_el(env);
+    int cur_el = arm_current_el(env);
+
+    /* FSR will only be used if the debug target EL is AArch32. */
+    env->exception.fsr = arm_debug_exception_fsr(env);
+    /*
+     * FAR is UNKNOWN: clear vaddress to avoid potentially exposing
+     * values to the guest that it shouldn't be able to see at its
+     * exception/security level.
+     */
+    env->exception.vaddress = 0;
+    /*
+     * Other kinds of architectural debug exception are ignored if
+     * they target an exception level below the current one (in QEMU
+     * this is checked by arm_generate_debug_exceptions()). Breakpoint
+     * instructions are special because they always generate an exception
+     * to somewhere: if they can't go to the configured debug exception
+     * level they are taken to the current exception level.
+     */
+    if (debug_el < cur_el) {
+        debug_el = cur_el;
+    }
+    raise_exception(env, EXCP_BKPT, syndrome, debug_el);
+}
+
 #if !defined(CONFIG_USER_ONLY)
 
 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
     raise_exception(env, excp, syndrome, target_el);
 }
 
-/* Raise an EXCP_BKPT with the specified syndrome register value,
- * targeting the correct exception level for debug exceptions.
- */
-void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
-{
-    int debug_el = arm_debug_target_el(env);
-    int cur_el = arm_current_el(env);
-
-    /* FSR will only be used if the debug target EL is AArch32. */
-    env->exception.fsr = arm_debug_exception_fsr(env);
-    /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
-     * values to the guest that it shouldn't be able to see at its
-     * exception/security level.
-     */
-    env->exception.vaddress = 0;
-    /*
-     * Other kinds of architectural debug exception are ignored if
-     * they target an exception level below the current one (in QEMU
-     * this is checked by arm_generate_debug_exceptions()). Breakpoint
-     * instructions are special because they always generate an exception
-     * to somewhere: if they can't go to the configured debug exception
-     * level they are taken to the current exception level.
-     */
-    if (debug_el < cur_el) {
-        debug_el = cur_el;
-    }
-    raise_exception(env, EXCP_BKPT, syndrome, debug_el);
-}
-
 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 {
     return cpsr_read(env) & ~CPSR_EXEC;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This function now now only used in debug_helper.c, so there is
no reason to have a declaration in a header.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h    | 25 -------------------------
 target/arm/debug_helper.c | 26 ++++++++++++++++++++++++++
 2 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
 }
 
-/* Return the FSR value for a debug exception (watchpoint, hardware
- * breakpoint or BKPT insn) targeting the specified exception level.
- */
-static inline uint32_t arm_debug_exception_fsr(CPUARMState *env)
-{
-    ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
-    int target_el = arm_debug_target_el(env);
-    bool using_lpae = false;
-
-    if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
-        using_lpae = true;
-    } else {
-        if (arm_feature(env, ARM_FEATURE_LPAE) &&
-            (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) {
-            using_lpae = true;
-        }
-    }
-
-    if (using_lpae) {
-        return arm_fi_to_lfsc(&fi);
-    } else {
-        return arm_fi_to_sfsc(&fi);
-    }
-}
-
 /**
  * arm_num_brps: Return number of implemented breakpoints.
  * Note that the ID register BRPS field is "number of bps - 1",
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
     return check_watchpoints(cpu);
 }
 
+/*
+ * Return the FSR value for a debug exception (watchpoint, hardware
+ * breakpoint or BKPT insn) targeting the specified exception level.
+ */
+static uint32_t arm_debug_exception_fsr(CPUARMState *env)
+{
+    ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
+    int target_el = arm_debug_target_el(env);
+    bool using_lpae = false;
+
+    if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
+        using_lpae = true;
+    } else {
+        if (arm_feature(env, ARM_FEATURE_LPAE) &&
+            (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) {
+            using_lpae = true;
+        }
+    }
+
+    if (using_lpae) {
+        return arm_fi_to_lfsc(&fi);
+    } else {
+        return arm_fi_to_sfsc(&fi);
+    }
+}
+
 void arm_debug_excp_handler(CPUState *cs)
 {
     /*
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Rename to helper_exception_with_syndrome_el, to emphasize
that the target el is a parameter.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h    | 2 +-
 target/arm/translate.h | 6 +++---
 target/arm/op_helper.c | 6 +++---
 target/arm/translate.c | 6 +++---
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
                    i32, i32, i32, i32)
 DEF_HELPER_2(exception_internal, noreturn, env, i32)
-DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32)
+DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32)
 DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32)
 DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
 DEF_HELPER_1(setend, void, env)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s)
 static inline void gen_exception(int excp, uint32_t syndrome,
                                  uint32_t target_el)
 {
-    gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp),
-                                       tcg_constant_i32(syndrome),
-                                       tcg_constant_i32(target_el));
+    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
+                                          tcg_constant_i32(syndrome),
+                                          tcg_constant_i32(target_el));
 }
 
 /* Generate an architectural singlestep exception */
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(yield)(CPUARMState *env)
  * those EXCP values which are special cases for QEMU to interrupt
  * execution and not to be used for exceptions which are passed to
  * the guest (those must all have syndrome information and thus should
- * use exception_with_syndrome).
+ * use exception_with_syndrome*).
  */
 void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
 {
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
 }
 
 /* Raise an exception with the specified syndrome register value */
-void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
-                                     uint32_t syndrome, uint32_t target_el)
+void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp,
+                                        uint32_t syndrome, uint32_t target_el)
 {
     raise_exception(env, excp, syndrome, target_el);
 }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
 {
     gen_set_condexec(s);
     gen_set_pc_im(s, s->pc_curr);
-    gen_helper_exception_with_syndrome(cpu_env,
-                                       tcg_constant_i32(excp),
-                                       tcg_constant_i32(syn), tcg_el);
+    gen_helper_exception_with_syndrome_el(cpu_env,
+                                          tcg_constant_i32(excp),
+                                          tcg_constant_i32(syn), tcg_el);
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a function below gen_exception_insn that takes
the target_el as a TCGv_i32, replacing gen_exception_el.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 27 ++++++++++++---------------
 1 file changed, 12 insertions(+), 15 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
-                        uint32_t syn, uint32_t target_el)
+static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
+                                    uint32_t syn, TCGv_i32 tcg_el)
 {
     if (s->aarch64) {
         gen_a64_set_pc_im(pc);
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
         gen_set_condexec(s);
         gen_set_pc_im(s, pc);
     }
-    gen_exception(excp, syn, target_el);
+    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
+                                          tcg_constant_i32(syn), tcg_el);
     s->base.is_jmp = DISAS_NORETURN;
 }
 
+void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
+                        uint32_t syn, uint32_t target_el)
+{
+    gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
+}
+
 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
 {
     gen_set_condexec(s);
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s)
                        default_exception_el(s));
 }
 
-static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
-                             TCGv_i32 tcg_el)
-{
-    gen_set_condexec(s);
-    gen_set_pc_im(s, s->pc_curr);
-    gen_helper_exception_with_syndrome_el(cpu_env,
-                                          tcg_constant_i32(excp),
-                                          tcg_constant_i32(syn), tcg_el);
-    s->base.is_jmp = DISAS_NORETURN;
-}
-
 /* Force a TB lookup after an instruction that changes the CPU state.  */
 void gen_lookup_tb(DisasContext *s)
 {
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
                 tcg_el = tcg_constant_i32(3);
             }
 
-            gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
+            gen_exception_insn_el_v(s, s->pc_curr, EXCP_UDEF,
+                                    syn_uncategorized(), tcg_el);
             tcg_temp_free_i32(tcg_el);
             return false;
         }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.h        |  4 ++--
 target/arm/translate-a64.c    | 36 ++++++++++++++++----------------
 target/arm/translate-m-nocp.c | 16 +++++++-------
 target/arm/translate-mve.c    |  4 ++--
 target/arm/translate-vfp.c    |  6 +++---
 target/arm/translate.c        | 39 ++++++++++++++++++-----------------
 6 files changed, 53 insertions(+), 52 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 void arm_gen_test_cc(int cc, TCGLabel *label);
 MemOp pow2_align(unsigned i);
 void unallocated_encoding(DisasContext *s);
-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
-                        uint32_t syn, uint32_t target_el);
+void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
+                           uint32_t syn, uint32_t target_el);
 
 /* Return state of Alternate Half-precision flag, caller frees result */
 static inline TCGv_i32 get_ahp_flag(void)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check(DisasContext *s)
         assert(!s->fp_access_checked);
         s->fp_access_checked = true;
 
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_fp_access_trap(1, 0xe, false, 0),
-                           s->fp_excp_el);
+        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+                              syn_fp_access_trap(1, 0xe, false, 0),
+                              s->fp_excp_el);
         return false;
     }
     s->fp_access_checked = true;
@@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s)
         assert(!s->sve_access_checked);
         s->sve_access_checked = true;
 
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_sve_access_trap(), s->sve_excp_el);
+        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+                              syn_sve_access_trap(), s->sve_excp_el);
         return false;
     }
     s->sve_access_checked = true;
@@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
     } else {
         syndrome = syn_uncategorized();
     }
-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome,
-                       default_exception_el(s));
+    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome,
+                          default_exception_el(s));
 }
 
 /* MRS - move from system register
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
         switch (op2_ll) {
         case 1:                                                     /* SVC */
             gen_ss_advance(s);
-            gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
-                               syn_aa64_svc(imm16), default_exception_el(s));
+            gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI,
+                                  syn_aa64_svc(imm16), default_exception_el(s));
             break;
         case 2:                                                     /* HVC */
             if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
             gen_a64_set_pc_im(s->pc_curr);
             gen_helper_pre_hvc(cpu_env);
             gen_ss_advance(s);
-            gen_exception_insn(s, s->base.pc_next, EXCP_HVC,
-                               syn_aa64_hvc(imm16), 2);
+            gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
+                                  syn_aa64_hvc(imm16), 2);
             break;
         case 3:                                                     /* SMC */
             if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
             gen_a64_set_pc_im(s->pc_curr);
             gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
             gen_ss_advance(s);
-            gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
-                               syn_aa64_smc(imm16), 3);
+            gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
+                                  syn_aa64_smc(imm16), 3);
             break;
         default:
             unallocated_encoding(s);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_illegalstate(), default_exception_el(s));
+        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+                              syn_illegalstate(), default_exception_el(s));
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
             if (s->btype != 0
                 && s->guarded_page
                 && !btype_destination_ok(insn, s->bt, s->btype)) {
-                gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                                   syn_btitrap(s->btype),
-                                   default_exception_el(s));
+                gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+                                      syn_btitrap(s->btype),
+                                      default_exception_el(s));
                 return;
             }
         } else {
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-m-nocp.c
+++ b/target/arm/translate-m-nocp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
     tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
 
     if (s->fp_excp_el != 0) {
-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
-                           syn_uncategorized(), s->fp_excp_el);
+        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+                              syn_uncategorized(), s->fp_excp_el);
         return true;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
         if (!vfp_access_check_m(s, true)) {
             /*
              * This was only a conditional exception, so override
-             * gen_exception_insn()'s default to DISAS_NORETURN
+             * gen_exception_insn_el()'s default to DISAS_NORETURN
              */
             s->base.is_jmp = DISAS_NEXT;
             break;
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
         if (!vfp_access_check_m(s, true)) {
             /*
              * This was only a conditional exception, so override
-             * gen_exception_insn()'s default to DISAS_NORETURN
+             * gen_exception_insn_el()'s default to DISAS_NORETURN
              */
             s->base.is_jmp = DISAS_NEXT;
             break;
@@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
     }
 
     if (a->cp != 10) {
-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
-                           syn_uncategorized(), default_exception_el(s));
+        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+                              syn_uncategorized(), default_exception_el(s));
         return true;
     }
 
     if (s->fp_excp_el != 0) {
-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
-                           syn_uncategorized(), s->fp_excp_el);
+        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+                              syn_uncategorized(), s->fp_excp_el);
         return true;
     }
 
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s)
         return true;
     default:
         /* Reserved value: INVSTATE UsageFault */
-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
-                           default_exception_el(s));
+        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+                              default_exception_el(s));
         return false;
     }
 }
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
         int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
         uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
 
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
+        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ bool vfp_access_check_m(DisasContext *s, bool skip_context_update)
          * the encoding space handled by the patterns in m-nocp.decode,
          * and for them we may need to raise NOCP here.
          */
-        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
-                           syn_uncategorized(), s->fp_excp_el);
+        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+                              syn_uncategorized(), s->fp_excp_el);
         return false;
     }
 
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
-                        uint32_t syn, uint32_t target_el)
+void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
+                           uint32_t syn, uint32_t target_el)
 {
     gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
 }
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
 void unallocated_encoding(DisasContext *s)
 {
     /* Unallocated and reserved encodings are uncategorized */
-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
-                       default_exception_el(s));
+    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
+                          default_exception_el(s));
 }
 
 /* Force a TB lookup after an instruction that changes the CPU state.  */
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
 
 undef:
     /* If we get here then some access check did not pass */
-    gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                       syn_uncategorized(), exc_target);
+    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+                          syn_uncategorized(), exc_target);
     return false;
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
      * For the UNPREDICTABLE cases we choose to UNDEF.
      */
     if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3);
+        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+                              syn_uncategorized(), 3);
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_WLS(DisasContext *s, arg_WLS *a)
          * Do the check-and-raise-exception by hand.
          */
         if (s->fp_excp_el) {
-            gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
-                               syn_uncategorized(), s->fp_excp_el);
+            gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
+                                  syn_uncategorized(), s->fp_excp_el);
             return true;
         }
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
         tmp = load_cpu_field(v7m.ltpsize);
         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
         tcg_temp_free_i32(tmp);
-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
-                           default_exception_el(s));
+        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+                              default_exception_el(s));
         gen_set_label(skipexc);
     }
 
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
      * UsageFault exception.
      */
     if (arm_dc_feature(s, ARM_FEATURE_M)) {
-        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
-                           default_exception_el(s));
+        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+                              default_exception_el(s));
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_illegalstate(), default_exception_el(s));
+        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
+                              syn_illegalstate(), default_exception_el(s));
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF,
-                           syn_illegalstate(), default_exception_el(dc));
+        gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF,
+                              syn_illegalstate(), default_exception_el(dc));
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          */
         tcg_remove_ops_after(dc->insn_eci_rewind);
         dc->condjmp = 0;
-        gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
-                           default_exception_el(dc));
+        gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
+                              default_exception_el(dc));
     }
 
     arm_post_translate_insn(dc);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a new wrapper function that passes the default
exception target to gen_exception_insn_el.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.h        |  1 +
 target/arm/translate-a64.c    | 15 ++++++---------
 target/arm/translate-m-nocp.c |  3 +--
 target/arm/translate-mve.c    |  3 +--
 target/arm/translate.c        | 29 +++++++++++++----------------
 5 files changed, 22 insertions(+), 29 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ MemOp pow2_align(unsigned i);
 void unallocated_encoding(DisasContext *s);
 void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
                            uint32_t syn, uint32_t target_el);
+void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn);
 
 /* Return state of Alternate Half-precision flag, caller frees result */
 static inline TCGv_i32 get_ahp_flag(void)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void gen_sysreg_undef(DisasContext *s, bool isread,
     } else {
         syndrome = syn_uncategorized();
     }
-    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syndrome,
-                          default_exception_el(s));
+    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome);
 }
 
 /* MRS - move from system register
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
         switch (op2_ll) {
         case 1:                                                     /* SVC */
             gen_ss_advance(s);
-            gen_exception_insn_el(s, s->base.pc_next, EXCP_SWI,
-                                  syn_aa64_svc(imm16), default_exception_el(s));
+            gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
+                               syn_aa64_svc(imm16));
             break;
         case 2:                                                     /* HVC */
             if (s->current_el == 0) {
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
-                              syn_illegalstate(), default_exception_el(s));
+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
             if (s->btype != 0
                 && s->guarded_page
                 && !btype_destination_ok(insn, s->bt, s->btype)) {
-                gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
-                                      syn_btitrap(s->btype),
-                                      default_exception_el(s));
+                gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
+                                   syn_btitrap(s->btype));
                 return;
             }
         } else {
diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-m-nocp.c
+++ b/target/arm/translate-m-nocp.c
@@ -XXX,XX +XXX,XX @@ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
     }
 
     if (a->cp != 10) {
-        gen_exception_insn_el(s, s->pc_curr, EXCP_NOCP,
-                              syn_uncategorized(), default_exception_el(s));
+        gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized());
         return true;
     }
 
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -XXX,XX +XXX,XX @@ bool mve_eci_check(DisasContext *s)
         return true;
     default:
         /* Reserved value: INVSTATE UsageFault */
-        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
-                              default_exception_el(s));
+        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
         return false;
     }
 }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
     gen_exception_insn_el_v(s, pc, excp, syn, tcg_constant_i32(target_el));
 }
 
+void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
+{
+    gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s));
+}
+
 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
 {
     gen_set_condexec(s);
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
 void unallocated_encoding(DisasContext *s)
 {
     /* Unallocated and reserved encodings are uncategorized */
-    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
-                          default_exception_el(s));
+    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
 }
 
 /* Force a TB lookup after an instruction that changes the CPU state.  */
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
      * an exception and return false. Otherwise it will return true,
      * and set *tgtmode and *regno appropriately.
      */
-    int exc_target = default_exception_el(s);
-
     /* These instructions are present only in ARMv8, or in ARMv7 with the
      * Virtualization Extensions.
      */
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
 
 undef:
     /* If we get here then some access check did not pass */
-    gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
-                          syn_uncategorized(), exc_target);
+    gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized());
     return false;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_LE(DisasContext *s, arg_LE *a)
         tmp = load_cpu_field(v7m.ltpsize);
         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc);
         tcg_temp_free_i32(tmp);
-        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
-                              default_exception_el(s));
+        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
         gen_set_label(skipexc);
     }
 
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
      * UsageFault exception.
      */
     if (arm_dc_feature(s, ARM_FEATURE_M)) {
-        gen_exception_insn_el(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
-                              default_exception_el(s));
+        gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized());
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn_el(s, s->pc_curr, EXCP_UDEF,
-                              syn_illegalstate(), default_exception_el(s));
+        gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_illegalstate());
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          * Illegal execution state. This has priority over BTI
          * exceptions, but comes after instruction abort exceptions.
          */
-        gen_exception_insn_el(dc, dc->pc_curr, EXCP_UDEF,
-                              syn_illegalstate(), default_exception_el(dc));
+        gen_exception_insn(dc, dc->pc_curr, EXCP_UDEF, syn_illegalstate());
         return;
     }
 
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
          */
         tcg_remove_ops_after(dc->insn_eci_rewind);
         dc->condjmp = 0;
-        gen_exception_insn_el(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
-                              default_exception_el(dc));
+        gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE,
+                           syn_uncategorized());
     }
 
     arm_post_translate_insn(dc);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the computation from gen_swstep_exception into a helper.

This fixes a bug when:
  - MDSCR_EL1.KDE == 1 to enable debug exceptions within EL_D itself
  - we singlestep an ERET from EL_D to some lower EL

Previously we were computing 'same el' based on the EL which
executed the ERET instruction, whereas it ought to be computed
based on the EL to which ERET returned.  This happens naturally
with the new helper, which runs after EL has been changed.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h       |  1 +
 target/arm/translate.h    | 12 +++---------
 target/arm/debug_helper.c | 16 ++++++++++++++++
 3 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
 DEF_HELPER_2(exception_internal, noreturn, env, i32)
 DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32)
 DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32)
+DEF_HELPER_2(exception_swstep, noreturn, env, i32)
 DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
 DEF_HELPER_1(setend, void, env)
 DEF_HELPER_2(wfi, void, env, i32)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline void gen_exception(int excp, uint32_t syndrome,
 /* Generate an architectural singlestep exception */
 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
 {
-    bool same_el = (s->debug_target_el == s->current_el);
-
-    /*
-     * If singlestep is targeting a lower EL than the current one,
-     * then s->ss_active must be false and we can never get here.
-     */
-    assert(s->debug_target_el >= s->current_el);
-
-    gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
+    /* Fill in the same_el field of the syndrome in the helper. */
+    uint32_t syn = syn_swstep(false, isv, ex);
+    gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn));
 }
 
 /*
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
     raise_exception(env, EXCP_BKPT, syndrome, debug_el);
 }
 
+void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
+{
+    int debug_el = arm_debug_target_el(env);
+    int cur_el = arm_current_el(env);
+
+    /*
+     * If singlestep is targeting a lower EL than the current one, then
+     * DisasContext.ss_active must be false and we can never get here.
+     */
+    assert(debug_el >= cur_el);
+    if (debug_el == cur_el) {
+        syndrome |= 1 << ARM_EL_EC_SHIFT;
+    }
+    raise_exception(env, EXCP_UDEF, syndrome, debug_el);
+}
+
 #if !defined(CONFIG_USER_ONLY)
 
 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We no longer need this value during translation,
as it is now handled within the helpers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h           |  6 ++----
 target/arm/translate.h     |  2 --
 target/arm/helper.c        | 12 ++----------
 target/arm/translate-a64.c |  1 -
 target/arm/translate.c     |  1 -
 5 files changed, 4 insertions(+), 18 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
 FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
 /* Target EL if we take a floating-point-disabled exception */
 FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
-/* For A-profile only, target EL for debug exceptions.  */
-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
 /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
-FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1)
-FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1)
+FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
+FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
 
 /*
  * Bit usage when in AArch32 state, both A- and M-profile.
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      */
     uint32_t svc_imm;
     int current_el;
-    /* Debug target exception level for single-step exceptions */
-    int debug_target_el;
     GHashTable *cp_regs;
     uint64_t features; /* CPU features bits */
     bool aarch64;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
     return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
 }
 
-static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env)
-{
-    CPUARMTBFlags flags = {};
-
-    DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env));
-    return flags;
-}
-
 static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
                                         ARMMMUIdx mmu_idx)
 {
-    CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
+    CPUARMTBFlags flags = {};
     int el = arm_current_el(env);
 
     if (arm_sctlr(env, el) & SCTLR_A) {
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
 static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
                                         ARMMMUIdx mmu_idx)
 {
-    CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
+    CPUARMTBFlags flags = {};
     ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
     uint64_t sctlr;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE);
     dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS);
     dc->is_ldex = false;
-    dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
 
     /* Bound the number of insns to execute to those left on the page.  */
     bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
         dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT);
         dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED);
     } else {
-        dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
         dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B);
         dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE);
         dc->ns = EX_TBFLAG_A32(tb_flags, NS);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This function is not required by any other translation file.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.h | 8 --------
 target/arm/translate.c | 7 +++++++
 2 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s)
     }
 }
 
-static inline void gen_exception(int excp, uint32_t syndrome,
-                                 uint32_t target_el)
-{
-    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
-                                          tcg_constant_i32(syndrome),
-                                          tcg_constant_i32(target_el));
-}
-
 /* Generate an architectural singlestep exception */
 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
 {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
     s->base.is_jmp = DISAS_NORETURN;
 }
 
+static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
+{
+    gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
+                                          tcg_constant_i32(syndrome),
+                                          tcg_constant_i32(target_el));
+}
+
 static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
                                     uint32_t syn, TCGv_i32 tcg_el)
 {
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
     s->base.is_jmp = DISAS_NORETURN;
 }
 
-static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
+static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
 {
     gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp),
                                           tcg_constant_i32(syndrome),
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         switch (dc->base.is_jmp) {
         case DISAS_SWI:
             gen_ss_advance(dc);
-            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
-                          default_exception_el(dc));
+            gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
+                             default_exception_el(dc));
             break;
         case DISAS_HVC:
             gen_ss_advance(dc);
-            gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
+            gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
             break;
         case DISAS_SMC:
             gen_ss_advance(dc);
-            gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
+            gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3);
             break;
         case DISAS_NEXT:
         case DISAS_TOO_MANY:
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             gen_helper_yield(cpu_env);
             break;
         case DISAS_SWI:
-            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
-                          default_exception_el(dc));
+            gen_exception_el(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
+                             default_exception_el(dc));
             break;
         case DISAS_HVC:
-            gen_exception(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
+            gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
             break;
         case DISAS_SMC:
-            gen_exception(EXCP_SMC, syn_aa32_smc(), 3);
+            gen_exception_el(EXCP_SMC, syn_aa32_smc(), 3);
             break;
         }
     }
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Create a new wrapper function that passes the default
exception target to gen_exception_el.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

Split out a common helper function for gen_exception_el
and gen_exception_insn_el_v.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

With the helper we can use exception_target_el at runtime,
instead of default_exception_el at translate time.
While we're at it, remove the DisasContext parameter from
gen_exception, as it is no longer used.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h    |  1 +
 target/arm/op_helper.c | 10 ++++++++++
 target/arm/translate.c | 18 +++++++++++++-----
 3 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
                    i32, i32, i32, i32)
 DEF_HELPER_2(exception_internal, noreturn, env, i32)
+DEF_HELPER_3(exception_with_syndrome, noreturn, env, i32, i32)
 DEF_HELPER_4(exception_with_syndrome_el, noreturn, env, i32, i32, i32)
 DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32)
 DEF_HELPER_2(exception_swstep, noreturn, env, i32)
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_with_syndrome_el)(CPUARMState *env, uint32_t excp,
     raise_exception(env, excp, syndrome, target_el);
 }
 
+/*
+ * Raise an exception with the specified syndrome register value
+ * to the default target el.
+ */
+void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
+                                     uint32_t syndrome)
+{
+    raise_exception(env, excp, syndrome, exception_target_el(env));
+}
+
 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 {
     return cpsr_read(env) & ~CPSR_EXEC;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_exception_el(int excp, uint32_t syndrome, uint32_t target_el)
     gen_exception_el_v(excp, syndrome, tcg_constant_i32(target_el));
 }
 
-static void gen_exception(DisasContext *s, int excp, uint32_t syndrome)
+static void gen_exception(int excp, uint32_t syndrome)
 {
-    gen_exception_el(excp, syndrome, default_exception_el(s));
+    gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp),
+                                       tcg_constant_i32(syndrome));
 }
 
 static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
@@ -XXX,XX +XXX,XX @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
 
 void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
 {
-    gen_exception_insn_el(s, pc, excp, syn, default_exception_el(s));
+    if (s->aarch64) {
+        gen_a64_set_pc_im(pc);
+    } else {
+        gen_set_condexec(s);
+        gen_set_pc_im(s, pc);
+    }
+    gen_exception(excp, syn);
+    s->base.is_jmp = DISAS_NORETURN;
 }
 
 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
         switch (dc->base.is_jmp) {
         case DISAS_SWI:
             gen_ss_advance(dc);
-            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
+            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
             break;
         case DISAS_HVC:
             gen_ss_advance(dc);
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             gen_helper_yield(cpu_env);
             break;
         case DISAS_SWI:
-            gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
+            gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));
             break;
         case DISAS_HVC:
             gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This function is no longer used.  At the same time, remove
DisasContext.secure_routed_to_el3, as it in turn becomes unused.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.h     | 16 ----------------
 target/arm/translate-a64.c |  5 -----
 target/arm/translate.c     |  5 -----
 3 files changed, 26 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     int fp_excp_el; /* FP exception EL or 0 if enabled */
     int sve_excp_el; /* SVE exception EL or 0 if enabled */
     int vl;          /* current vector length in bytes */
-    /* Flag indicating that exceptions from secure mode are routed to EL3. */
-    bool secure_routed_to_el3;
     bool vfp_enabled; /* FP enabled via FPSCR.EN */
     int vec_len;
     int vec_stride;
@@ -XXX,XX +XXX,XX @@ static inline int get_mem_index(DisasContext *s)
     return arm_to_core_mmu_idx(s->mmu_idx);
 }
 
-/* Function used to determine the target exception EL when otherwise not known
- * or default.
- */
-static inline int default_exception_el(DisasContext *s)
-{
-    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
-     * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
-     * exceptions can only be routed to ELs above 1, so we target the higher of
-     * 1 or the current EL.
-     */
-    return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
-            ? 3 : MAX(1, s->current_el);
-}
-
 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 {
     /* We don't need to save all of the syndrome so we mask and shift
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->condjmp = 0;
 
     dc->aarch64 = true;
-    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
-     * there is no secure EL1, so we route exceptions to EL3.
-     */
-    dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
-                               !arm_el_is_aa64(env, 3);
     dc->thumb = false;
     dc->sctlr_b = 0;
     dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     dc->condjmp = 0;
 
     dc->aarch64 = false;
-    /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
-     * there is no secure EL1, so we route exceptions to EL3.
-     */
-    dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
-                               !arm_el_is_aa64(env, 3);
     dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB);
     dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
     condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Handle the debug vs current el exception test in one place.
Leave EXCP_BKPT alone, since that treats debug < current differently.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/debug_helper.c | 44 +++++++++++++++++++++------------------
 1 file changed, 24 insertions(+), 20 deletions(-)

diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 
 
+/*
+ * Raise an exception to the debug target el.
+ * Modify syndrome to indicate when origin and target EL are the same.
+ */
+G_NORETURN static void
+raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome)
+{
+    int debug_el = arm_debug_target_el(env);
+    int cur_el = arm_current_el(env);
+
+    /*
+     * If singlestep is targeting a lower EL than the current one, then
+     * DisasContext.ss_active must be false and we can never get here.
+     * Similarly for watchpoint and breakpoint matches.
+     */
+    assert(debug_el >= cur_el);
+    syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT;
+    raise_exception(env, excp, syndrome, debug_el);
+}
+
 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
 static bool aa64_generate_debug_exceptions(CPUARMState *env)
 {
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
     if (wp_hit) {
         if (wp_hit->flags & BP_CPU) {
             bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
-            bool same_el = arm_debug_target_el(env) == arm_current_el(env);
 
             cs->watchpoint_hit = NULL;
 
             env->exception.fsr = arm_debug_exception_fsr(env);
             env->exception.vaddress = wp_hit->hitaddr;
-            raise_exception(env, EXCP_DATA_ABORT,
-                    syn_watchpoint(same_el, 0, wnr),
-                    arm_debug_target_el(env));
+            raise_exception_debug(env, EXCP_DATA_ABORT,
+                                  syn_watchpoint(0, 0, wnr));
         }
     } else {
         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
-        bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
 
         /*
          * (1) GDB breakpoints should be handled first.
@@ -XXX,XX +XXX,XX @@ void arm_debug_excp_handler(CPUState *cs)
          * exception/security level.
          */
         env->exception.vaddress = 0;
-        raise_exception(env, EXCP_PREFETCH_ABORT,
-                        syn_breakpoint(same_el),
-                        arm_debug_target_el(env));
+        raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0));
     }
 }
 
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
 
 void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome)
 {
-    int debug_el = arm_debug_target_el(env);
-    int cur_el = arm_current_el(env);
-
-    /*
-     * If singlestep is targeting a lower EL than the current one, then
-     * DisasContext.ss_active must be false and we can never get here.
-     */
-    assert(debug_el >= cur_el);
-    if (debug_el == cur_el) {
-        syndrome |= 1 << ARM_EL_EC_SHIFT;
-    }
-    raise_exception(env, EXCP_UDEF, syndrome, debug_el);
+    raise_exception_debug(env, EXCP_UDEF, syndrome);
 }
 
 #if !defined(CONFIG_USER_ONLY)
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

This function is no longer used outside debug_helper.c.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h          | 21 ---------------------
 target/arm/debug_helper.c | 21 +++++++++++++++++++++
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef enum ARMASIdx {
     ARMASIdx_TagS = 3,
 } ARMASIdx;
 
-/* Return the Exception Level targeted by debug exceptions. */
-static inline int arm_debug_target_el(CPUARMState *env)
-{
-    bool secure = arm_is_secure(env);
-    bool route_to_el2 = false;
-
-    if (arm_is_el2_enabled(env)) {
-        route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
-                       env->cp15.mdcr_el2 & MDCR_TDE;
-    }
-
-    if (route_to_el2) {
-        return 2;
-    } else if (arm_feature(env, ARM_FEATURE_EL3) &&
-               !arm_el_is_aa64(env, 3) && secure) {
-        return 3;
-    } else {
-        return 1;
-    }
-}
-
 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
 {
     /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-proto.h"
 
 
+/* Return the Exception Level targeted by debug exceptions. */
+static int arm_debug_target_el(CPUARMState *env)
+{
+    bool secure = arm_is_secure(env);
+    bool route_to_el2 = false;
+
+    if (arm_is_el2_enabled(env)) {
+        route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
+                       env->cp15.mdcr_el2 & MDCR_TDE;
+    }
+
+    if (route_to_el2) {
+        return 2;
+    } else if (arm_feature(env, ARM_FEATURE_EL3) &&
+               !arm_el_is_aa64(env, 3) && secure) {
+        return 3;
+    } else {
+        return 1;
+    }
+}
+
 /*
  * Raise an exception to the debug target el.
  * Modify syndrome to indicate when origin and target EL are the same.
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

We were using arm_is_secure and is_a64, which are
tests against the current EL, as opposed to
arm_el_is_aa64 and arm_is_secure_below_el3, which
can be applied to a different EL than current.
Consolidate the two tests.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 23 +++++++++--------------
 1 file changed, 9 insertions(+), 14 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
         int fpen = FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN);
 
         switch (fpen) {
+        case 1:
+            if (cur_el != 0) {
+                break;
+            }
+            /* fall through */
         case 0:
         case 2:
-            if (cur_el == 0 || cur_el == 1) {
-                /* Trap to PL1, which might be EL1 or EL3 */
-                if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
-                    return 3;
-                }
-                return 1;
-            }
-            if (cur_el == 3 && !is_a64(env)) {
-                /* Secure PL1 running at EL3 */
+            /* Trap from Secure PL0 or PL1 to Secure PL1. */
+            if (!arm_el_is_aa64(env, 3)
+                && (cur_el == 3 || arm_is_secure_below_el3(env))) {
                 return 3;
             }
-            break;
-        case 1:
-            if (cur_el == 0) {
+            if (cur_el <= 1) {
                 return 1;
             }
             break;
-        case 3:
-            break;
         }
     }
 
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Because reset always initializes the AA64 version, SCR_EL3,
test the mode of EL3 instead of the type of the cpreg.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609214657.1217913-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
     uint32_t valid_mask = 0x3fff;
     ARMCPU *cpu = env_archcpu(env);
 
-    if (ri->state == ARM_CP_STATE_AA64) {
-        if (arm_feature(env, ARM_FEATURE_AARCH64) &&
-            !cpu_isar_feature(aa64_aa32_el1, cpu)) {
-                value |= SCR_FW | SCR_AW;   /* these two bits are RES1.  */
-        }
-        valid_mask &= ~SCR_NET;
+    /*
+     * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
+     * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
+     * Instead, choose the format based on the mode of EL3.
+     */
+    if (arm_el_is_aa64(env, 3)) {
+        value |= SCR_FW | SCR_AW;      /* RES1 */
+        valid_mask &= ~SCR_NET;        /* RES0 */
 
         if (cpu_isar_feature(aa64_ras, cpu)) {
             valid_mask |= SCR_TERR;
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Since DDI0487F.a, the RW bit is RAO/WI.  When specifically
targeting such a cpu, e.g. cortex-a76, it is legitimate to
ignore the bit within the secure monitor.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609214657.1217913-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    | 5 +++++
 target/arm/helper.c | 4 ++++
 2 files changed, 9 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
 }
 
+static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
+}
+
 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         value |= SCR_FW | SCR_AW;      /* RES1 */
         valid_mask &= ~SCR_NET;        /* RES0 */
 
+        if (!cpu_isar_feature(aa64_aa32_el1, cpu) &&
+            !cpu_isar_feature(aa64_aa32_el2, cpu)) {
+            value |= SCR_RW;           /* RAO/WI */
+        }
         if (cpu_isar_feature(aa64_ras, cpu)) {
             valid_mask |= SCR_TERR;
         }
-- 
2.25.1

In two places in gdbstub.c we look at gdbserver_state.init to decide
whether we're going to do a semihosting syscall via the gdb remote
protocol:
 * when setting up, if the user didn't explicitly select either
   native semihosting or gdb semihosting, we autoselect, with the
   intended behaviour "use gdb if gdb is connected"
 * when the semihosting layer attempts to do a syscall via gdb, we
   silently ignore it if the gdbstub wasn't actually set up

However, if the user's commandline sets up the gdbstub but tells QEMU
to start rather than waiting for a GDB to connect (eg using '-s' but
not '-S'), then we will have gdbserver_state.init true but no actual
connection; an attempt to use gdb syscalls will then crash because we
try to use gdbserver_state.c_cpu when it hasn't been set up:

#0  0x00007ffff6803ba8 in qemu_cpu_kick (cpu=0x0) at ../../softmmu/cpus.c:457
#1  0x00007ffff6c03913 in gdb_do_syscallv (cb=0x7ffff6c19944 <common_semi_cb>,
    fmt=0x7ffff7573b7e "", va=0x7ffff56294c0) at ../../gdbstub.c:2946
#2  0x00007ffff6c19c3a in common_semi_gdb_syscall (cs=0x7ffff83fe060,
    cb=0x7ffff6c19944 <common_semi_cb>, fmt=0x7ffff7573b75 "isatty,%x")
    at ../../semihosting/arm-compat-semi.c:494
#3  0x00007ffff6c1a064 in gdb_isattyfn (cs=0x7ffff83fe060, gf=0x7ffff86a3690)
    at ../../semihosting/arm-compat-semi.c:636
#4  0x00007ffff6c1b20f in do_common_semihosting (cs=0x7ffff83fe060)
    at ../../semihosting/arm-compat-semi.c:967
#5  0x00007ffff693a037 in handle_semihosting (cs=0x7ffff83fe060)
    at ../../target/arm/helper.c:10316

You can probably also get into this state via some odd
corner cases involving connecting a GDB and then telling it
to detach from all the vCPUs.

Abstract out the test into a new gdb_attached() function
which returns true only if there's actually a GDB connected
to the debug stub and attached to at least one vCPU.

Reported-by: Liviu Ionescu <ilg@livius.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220526190053.521505-2-peter.maydell@linaro.org
---
 gdbstub.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/gdbstub.c b/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int get_char(void)
 }
 #endif
 
+/*
+ * Return true if there is a GDB currently connected to the stub
+ * and attached to a CPU
+ */
+static bool gdb_attached(void)
+{
+    return gdbserver_state.init && gdbserver_state.c_cpu;
+}
+
 static enum {
     GDB_SYS_UNKNOWN,
     GDB_SYS_ENABLED,
@@ -XXX,XX +XXX,XX @@ int use_gdb_syscalls(void)
     /* -semihosting-config target=auto */
     /* On the first call check if gdb is connected and remember. */
     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
-        gdb_syscall_mode = gdbserver_state.init ?
-            GDB_SYS_ENABLED : GDB_SYS_DISABLED;
+        gdb_syscall_mode = gdb_attached() ? GDB_SYS_ENABLED : GDB_SYS_DISABLED;
     }
     return gdb_syscall_mode == GDB_SYS_ENABLED;
 }
@@ -XXX,XX +XXX,XX @@ void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va)
     target_ulong addr;
     uint64_t i64;
 
-    if (!gdbserver_state.init) {
+    if (!gdb_attached()) {
         return;
     }
 
-- 
2.25.1

Currently we mishandle the --semihosting-config option if the
user specifies it on the command line more than once. For
example with:
 --semihosting-config target=gdb --semihosting-config arg=foo,arg=bar

the function qemu_semihosting_config_options() is called twice, once
for each argument.  But that function expects to be called only once,
and it always unconditionally sets the semihosting.enabled,
semihost_chardev and semihosting.target variables.  This means that
if any of those options were set anywhere except the last
--semihosting-config option on the command line, those settings are
ignored.  In the example above, 'target=gdb' in the first option is
overridden by an implied default 'target=auto' in the second.

The QemuOptsList machinery has a flag for handling this kind of
"option group is setting global state": by setting
 .merge_lists = true;
we make the machinery merge all the --semihosting-config arguments
the user passes into a single set of options and call our
qemu_semihosting_config_options() just once.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220526190053.521505-3-peter.maydell@linaro.org
---
 semihosting/config.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/semihosting/config.c b/semihosting/config.c
index XXXXXXX..XXXXXXX 100644
--- a/semihosting/config.c
+++ b/semihosting/config.c
@@ -XXX,XX +XXX,XX @@
 
 QemuOptsList qemu_semihosting_config_opts = {
     .name = "semihosting-config",
+    .merge_lists = true,
     .implied_opt_name = "enable",
     .head = QTAILQ_HEAD_INITIALIZER(qemu_semihosting_config_opts.head),
     .desc = {
-- 
2.25.1