1
Arm queue; bugfixes only.
1
Hi; this is a collection of mostly GIC related patches for rc3.
2
The "Update cached state after LPI state changes" fix is important
3
and fixes what would otherwise be a regression since we enable the
4
ITS by default in the virt board now. The others are not regressions
5
but I think are OK for rc3 as they're fairly self contained (and two
6
of them are fixes to new-in-6.2 functionality).
2
7
3
thanks
8
thanks
4
-- PMM
9
-- PMM
5
10
6
The following changes since commit 48aa8f0ac536db3550a35c295ff7de94e4c33739:
11
The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a:
7
12
8
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2020-11-16' into staging (2020-11-17 11:07:00 +0000)
13
Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100)
9
14
10
are available in the Git repository at:
15
are available in the Git repository at:
11
16
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201117
17
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211129
13
18
14
for you to fetch changes up to ab135622cf478585bdfcb68b85e4a817d74a0c42:
19
for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9:
15
20
16
tmp105: Correct handling of temperature limit checks (2020-11-17 12:56:33 +0000)
21
hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29 10:10:21 +0000)
17
22
18
----------------------------------------------------------------
23
----------------------------------------------------------------
19
target-arm queue:
24
target-arm queue:
20
* hw/arm/virt: ARM_VIRT must select ARM_GIC
25
* virt: Diagnose attempts to enable MTE or virt when using HVF accelerator
21
* exynos: Fix bad printf format specifiers
26
* GICv3 ITS: Allow clearing of ITS CTLR Enabled bit
22
* hw/input/ps2.c: Remove remnants of printf debug
27
* GICv3: Update cached state after LPI state changes
23
* target/openrisc: Remove dead code attempting to check "is timer disabled"
28
* GICv3: Fix handling of LPIs in list registers
24
* register: Remove unnecessary NULL check
25
* util/cutils: Fix Coverity array overrun in freq_to_str()
26
* configure: Make "does libgio work" test pull in some actual functions
27
* tmp105: reset the T_low and T_High registers
28
* tmp105: Correct handling of temperature limit checks
29
29
30
----------------------------------------------------------------
30
----------------------------------------------------------------
31
Alex Chen (1):
31
Alexander Graf (1):
32
exynos: Fix bad printf format specifiers
32
hw/arm/virt: Extend nested and mte checks to hvf
33
33
34
Alistair Francis (1):
34
Peter Maydell (3):
35
register: Remove unnecessary NULL check
35
hw/intc/arm_gicv3: Update cached state after LPI state changes
36
hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
37
hw/intc/arm_gicv3: fix handling of LPIs in list registers
36
38
37
Andrew Jones (1):
39
Shashi Mallela (1):
38
hw/arm/virt: ARM_VIRT must select ARM_GIC
40
hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
39
41
40
Peter Maydell (5):
42
hw/intc/gicv3_internal.h | 30 ++++++++++++++++++++++++++++++
41
hw/input/ps2.c: Remove remnants of printf debug
43
hw/arm/virt.c | 15 +++++++++------
42
target/openrisc: Remove dead code attempting to check "is timer disabled"
44
hw/intc/arm_gicv3.c | 6 ++++--
43
configure: Make "does libgio work" test pull in some actual functions
45
hw/intc/arm_gicv3_cpuif.c | 9 ++++-----
44
hw/misc/tmp105: reset the T_low and T_High registers
46
hw/intc/arm_gicv3_its.c | 7 ++++---
45
tmp105: Correct handling of temperature limit checks
47
hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
48
6 files changed, 61 insertions(+), 20 deletions(-)
46
49
47
Philippe Mathieu-Daudé (1):
48
util/cutils: Fix Coverity array overrun in freq_to_str()
49
50
configure | 11 +++++--
51
hw/misc/tmp105.h | 7 +++++
52
hw/core/register.c | 4 ---
53
hw/input/ps2.c | 9 ------
54
hw/misc/tmp105.c | 73 ++++++++++++++++++++++++++++++++++++++------
55
hw/timer/exynos4210_mct.c | 4 +--
56
hw/timer/exynos4210_pwm.c | 8 ++---
57
target/openrisc/sys_helper.c | 3 --
58
util/cutils.c | 3 +-
59
hw/arm/Kconfig | 1 +
60
10 files changed, 89 insertions(+), 34 deletions(-)
61
diff view generated by jsdifflib
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
The removal of the selection of A15MPCORE from ARM_VIRT also
4
removed what A15MPCORE selects, ARM_GIC. We still need ARM_GIC.
5
6
Fixes: bec3c97e0cf9 ("hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals")
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20201111143440.112763-1-drjones@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/Kconfig | 1 +
15
1 file changed, 1 insertion(+)
16
17
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/Kconfig
20
+++ b/hw/arm/Kconfig
21
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
22
imply VFIO_PLATFORM
23
imply VFIO_XGMAC
24
imply TPM_TIS_SYSBUS
25
+ select ARM_GIC
26
select ACPI
27
select ARM_SMMUV3
28
select GPIO_KEY
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Alexander Graf <agraf@csgraf.de>
2
2
3
This patch fixes CID 1432800 by removing an unnecessary check.
3
The virt machine has properties to enable MTE and Nested Virtualization
4
support. However, its check to ensure the backing accel implementation
5
supports it today only looks for KVM and bails out if it finds it.
4
6
5
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Extend the checks to HVF as well as it does not support either today.
8
This will cause QEMU to print a useful error message rather than
9
silently ignoring the attempt by the user to enable either MTE or
10
the Virtualization extensions.
11
12
Reported-by: saar amar <saaramar5@gmail.com>
13
Signed-off-by: Alexander Graf <agraf@csgraf.de>
14
Message-id: 20211123122859.22452-1-agraf@csgraf.de
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
17
---
9
hw/core/register.c | 4 ----
18
hw/arm/virt.c | 15 +++++++++------
10
1 file changed, 4 deletions(-)
19
1 file changed, 9 insertions(+), 6 deletions(-)
11
20
12
diff --git a/hw/core/register.c b/hw/core/register.c
21
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
13
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/core/register.c
23
--- a/hw/arm/virt.c
15
+++ b/hw/core/register.c
24
+++ b/hw/arm/virt.c
16
@@ -XXX,XX +XXX,XX @@ static RegisterInfoArray *register_init_block(DeviceState *owner,
25
@@ -XXX,XX +XXX,XX @@
17
int index = rae[i].addr / data_size;
26
#include "sysemu/runstate.h"
18
RegisterInfo *r = &ri[index];
27
#include "sysemu/tpm.h"
19
28
#include "sysemu/kvm.h"
20
- if (data + data_size * index == 0 || !&rae[i]) {
29
+#include "sysemu/hvf.h"
21
- continue;
30
#include "hw/loader.h"
22
- }
31
#include "qapi/error.h"
23
-
32
#include "qemu/bitops.h"
24
/* Init the register, this will zero it. */
33
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
25
object_initialize((void *)r, sizeof(*r), TYPE_REGISTER);
34
exit(1);
35
}
36
37
- if (vms->virt && kvm_enabled()) {
38
- error_report("mach-virt: KVM does not support providing "
39
- "Virtualization extensions to the guest CPU");
40
+ if (vms->virt && (kvm_enabled() || hvf_enabled())) {
41
+ error_report("mach-virt: %s does not support providing "
42
+ "Virtualization extensions to the guest CPU",
43
+ kvm_enabled() ? "KVM" : "HVF");
44
exit(1);
45
}
46
47
- if (vms->mte && kvm_enabled()) {
48
- error_report("mach-virt: KVM does not support providing "
49
- "MTE to the guest CPU");
50
+ if (vms->mte && (kvm_enabled() || hvf_enabled())) {
51
+ error_report("mach-virt: %s does not support providing "
52
+ "MTE to the guest CPU",
53
+ kvm_enabled() ? "KVM" : "HVF");
54
exit(1);
55
}
26
56
27
--
57
--
28
2.20.1
58
2.25.1
29
59
30
60
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Shashi Mallela <shashi.mallela@linaro.org>
2
2
3
Fix Coverity CID 1435957: Memory - illegal accesses (OVERRUN):
3
When Enabled bit is cleared in GITS_CTLR,ITS feature continues
4
to be enabled.This patch fixes the issue.
4
5
5
>>> Overrunning array "suffixes" of 7 8-byte elements at element
6
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
6
index 7 (byte offset 63) using index "idx" (which evaluates to 7).
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
8
Note, the biggest input value freq_to_str() can accept is UINT64_MAX,
9
which is ~18.446 EHz, less than 1000 EHz.
10
11
Reported-by: Eduardo Habkost <ehabkost@redhat.com>
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
9
Message-id: 20211124182246.67691-1-shashi.mallela@linaro.org
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
16
Message-id: 20201101215755.2021421-1-f4bug@amsat.org
17
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
11
---
21
util/cutils.c | 3 ++-
12
hw/intc/arm_gicv3_its.c | 7 ++++---
22
1 file changed, 2 insertions(+), 1 deletion(-)
13
1 file changed, 4 insertions(+), 3 deletions(-)
23
14
24
diff --git a/util/cutils.c b/util/cutils.c
15
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/util/cutils.c
17
--- a/hw/intc/arm_gicv3_its.c
27
+++ b/util/cutils.c
18
+++ b/hw/intc/arm_gicv3_its.c
28
@@ -XXX,XX +XXX,XX @@ char *freq_to_str(uint64_t freq_hz)
19
@@ -XXX,XX +XXX,XX @@ static bool its_writel(GICv3ITSState *s, hwaddr offset,
29
double freq = freq_hz;
20
30
size_t idx = 0;
21
switch (offset) {
31
22
case GITS_CTLR:
32
- while (freq >= 1000.0 && idx < ARRAY_SIZE(suffixes)) {
23
- s->ctlr |= (value & ~(s->ctlr));
33
+ while (freq >= 1000.0) {
24
-
34
freq /= 1000.0;
25
- if (s->ctlr & ITS_CTLR_ENABLED) {
35
idx++;
26
+ if (value & R_GITS_CTLR_ENABLED_MASK) {
36
}
27
+ s->ctlr |= ITS_CTLR_ENABLED;
37
+ assert(idx < ARRAY_SIZE(suffixes));
28
extract_table_params(s);
38
29
extract_cmdq_params(s);
39
return g_strdup_printf("%0.3g %sHz", freq, suffixes[idx]);
30
s->creadr = 0;
40
}
31
process_cmdq(s);
32
+ } else {
33
+ s->ctlr &= ~ITS_CTLR_ENABLED;
34
}
35
break;
36
case GITS_CBASER:
41
--
37
--
42
2.20.1
38
2.25.1
43
39
44
40
diff view generated by jsdifflib
1
The TMP105 datasheet says that in Interrupt Mode (when TM==1) the device
1
The logic of gicv3_redist_update() is as follows:
2
signals an alert when the temperature equals or exceeds the T_high value and
2
* it must be called in any code path that changes the state of
3
then remains high until a device register is read or the device responds to
3
(only) redistributor interrupts
4
the SMBUS Alert Response address, or the device is put into Shutdown Mode.
4
* if it finds a redistributor interrupt that is (now) higher
5
Thereafter the Alert pin will only be re-signalled when temperature falls
5
priority than the previous highest-priority pending interrupt,
6
below T_low; alert can then be cleared in the same set of ways, and the
6
then this must be the new highest-priority pending interrupt
7
device returns to its initial "alert when temperature goes above T_high"
7
* if it does *not* find a better redistributor interrupt, then:
8
mode. (If this textual description is confusing, see figure 3 in the
8
- if the previous state was "no interrupts pending" then
9
TI datasheet at https://www.ti.com/lit/gpn/tmp105 .)
9
the new state is still "no interrupts pending"
10
- if the previous best interrupt was not a redistributor
11
interrupt then that remains the best interrupt
12
- if the previous best interrupt *was* a redistributor interrupt,
13
then the new best interrupt must be some non-redistributor
14
interrupt, but we don't know which so must do a full scan
10
15
11
We were misimplementing this as a simple "always alert if temperature is
16
In commit 17fb5e36aabd4b2c125 we effectively added the LPI interrupts
12
above T_high or below T_low" condition, which gives a spurious alert on
17
as a kind of "redistributor interrupt" for this purpose, by adding
13
startup if using the "T_high = 80 degrees C, T_low = 75 degrees C" reset
18
cs->hpplpi to the set of things that gicv3_redist_update() considers
14
limit values.
19
before it gives up and decides to do a full scan of distributor
20
interrupts. However we didn't quite get this right:
21
* the condition check for "was the previous best interrupt a
22
redistributor interrupt" must be updated to include LPIs
23
in what it considers to be redistributor interrupts
24
* every code path which updates the LPI state which
25
gicv3_redist_update() checks must also call gicv3_redist_update():
26
this is cs->hpplpi and the GICR_CTLR ENABLE_LPIS bit
15
27
16
Implement the correct (hysteresis) behaviour by tracking whether we
28
This commit fixes this by:
17
are currently looking for the temperature to rise over T_high or
29
* correcting the test on cs->hppi.irq in gicv3_redist_update()
18
for it to fall below T_low. Our implementation of the comparator
30
* making gicv3_redist_update_lpi() always call gicv3_redist_update()
19
mode (TM==0) wasn't wrong, but rephrase it to match the way that
31
* introducing a new gicv3_redist_update_lpi_only() for the one
20
interrupt mode is now handled for clarity.
32
callsite (the post-load hook) which must not call
33
gicv3_redist_update()
34
* making gicv3_redist_lpi_pending() always call gicv3_redist_update(),
35
either directly or via gicv3_redist_update_lpi()
36
* removing a couple of now-unnecessary calls to gicv3_redist_update()
37
from some callers of those two functions
38
* calling gicv3_redist_update() when the GICR_CTLR ENABLE_LPIS
39
bit is cleared
40
41
(This means that the not-file-local gicv3_redist_* LPI related
42
functions now all take care of the updates of internally cached
43
GICv3 information, in the same way the older functions
44
gicv3_redist_set_irq() and gicv3_redist_send_sgi() do.)
45
46
The visible effect of this bug was that when the guest acknowledged
47
an LPI by reading ICC_IAR1_EL1, we marked it as not pending in the
48
LPI data structure but still left it in cs->hppi so we would offer it
49
to the guest again. In particular for setups using an emulated GICv3
50
and ITS and using devices which use LPIs (ie PCI devices) a Linux
51
guest would complain "irq 54: nobody cared" and then hang. (The hang
52
was intermittent, presumably depending on the timing between
53
different interrupts arriving and being completed.)
21
54
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Cédric Le Goater <clg@kaod.org>
56
Tested-by: Alex Bennée <alex.bennee@linaro.org>
24
Message-id: 20201110150023.25533-3-peter.maydell@linaro.org
57
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
58
Message-id: 20211124202005.989935-1-peter.maydell@linaro.org
25
---
59
---
26
hw/misc/tmp105.h | 7 +++++
60
hw/intc/gicv3_internal.h | 17 +++++++++++++++++
27
hw/misc/tmp105.c | 70 +++++++++++++++++++++++++++++++++++++++++-------
61
hw/intc/arm_gicv3.c | 6 ++++--
28
2 files changed, 68 insertions(+), 9 deletions(-)
62
hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
63
3 files changed, 31 insertions(+), 6 deletions(-)
29
64
30
diff --git a/hw/misc/tmp105.h b/hw/misc/tmp105.h
65
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
31
index XXXXXXX..XXXXXXX 100644
66
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/misc/tmp105.h
67
--- a/hw/intc/gicv3_internal.h
33
+++ b/hw/misc/tmp105.h
68
+++ b/hw/intc/gicv3_internal.h
34
@@ -XXX,XX +XXX,XX @@ struct TMP105State {
69
@@ -XXX,XX +XXX,XX @@ void gicv3_dist_set_irq(GICv3State *s, int irq, int level);
35
int16_t limit[2];
70
void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level);
36
int faults;
71
void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level);
37
uint8_t alarm;
72
void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level);
38
+ /*
73
+/**
39
+ * The TMP105 initially looks for a temperature rising above T_high;
74
+ * gicv3_redist_update_lpi:
40
+ * once this is detected, the condition it looks for next is the
75
+ * @cs: GICv3CPUState
41
+ * temperature falling below T_low. This flag is false when initially
76
+ *
42
+ * looking for T_high, true when looking for T_low.
77
+ * Scan the LPI pending table and recalculate the highest priority
43
+ */
78
+ * pending LPI and also the overall highest priority pending interrupt.
44
+ bool detect_falling;
79
+ */
45
};
80
void gicv3_redist_update_lpi(GICv3CPUState *cs);
46
81
+/**
47
#endif
82
+ * gicv3_redist_update_lpi_only:
48
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
83
+ * @cs: GICv3CPUState
84
+ *
85
+ * Scan the LPI pending table and recalculate cs->hpplpi only,
86
+ * without calling gicv3_redist_update() to recalculate the overall
87
+ * highest priority pending interrupt. This should be called after
88
+ * an incoming migration has loaded new state.
89
+ */
90
+void gicv3_redist_update_lpi_only(GICv3CPUState *cs);
91
void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns);
92
void gicv3_init_cpuif(GICv3State *s);
93
94
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
49
index XXXXXXX..XXXXXXX 100644
95
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/misc/tmp105.c
96
--- a/hw/intc/arm_gicv3.c
51
+++ b/hw/misc/tmp105.c
97
+++ b/hw/intc/arm_gicv3.c
52
@@ -XXX,XX +XXX,XX @@ static void tmp105_alarm_update(TMP105State *s)
98
@@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
53
return;
99
* interrupt has reduced in priority and any other interrupt could
100
* now be the new best one).
101
*/
102
- if (!seenbetter && cs->hppi.prio != 0xff && cs->hppi.irq < GIC_INTERNAL) {
103
+ if (!seenbetter && cs->hppi.prio != 0xff &&
104
+ (cs->hppi.irq < GIC_INTERNAL ||
105
+ cs->hppi.irq >= GICV3_LPI_INTID_START)) {
106
gicv3_full_update_noirqset(cs->gic);
54
}
107
}
55
108
}
56
- if ((s->config >> 1) & 1) {                    /* TM */
109
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_post_load(GICv3State *s)
57
- if (s->temperature >= s->limit[1])
110
* pending interrupt, but don't set IRQ or FIQ lines.
58
- s->alarm = 1;
111
*/
59
- else if (s->temperature < s->limit[0])
112
for (i = 0; i < s->num_cpu; i++) {
60
- s->alarm = 1;
113
- gicv3_redist_update_lpi(&s->cpu[i]);
61
+ if (s->config >> 1 & 1) {
114
+ gicv3_redist_update_lpi_only(&s->cpu[i]);
62
+ /*
63
+ * TM == 1 : Interrupt mode. We signal Alert when the
64
+ * temperature rises above T_high, and expect the guest to clear
65
+ * it (eg by reading a device register).
66
+ */
67
+ if (s->detect_falling) {
68
+ if (s->temperature < s->limit[0]) {
69
+ s->alarm = 1;
70
+ s->detect_falling = false;
71
+ }
72
+ } else {
73
+ if (s->temperature >= s->limit[1]) {
74
+ s->alarm = 1;
75
+ s->detect_falling = true;
76
+ }
77
+ }
78
} else {
79
- if (s->temperature >= s->limit[1])
80
- s->alarm = 1;
81
- else if (s->temperature < s->limit[0])
82
- s->alarm = 0;
83
+ /*
84
+ * TM == 0 : Comparator mode. We signal Alert when the temperature
85
+ * rises above T_high, and stop signalling it when the temperature
86
+ * falls below T_low.
87
+ */
88
+ if (s->detect_falling) {
89
+ if (s->temperature < s->limit[0]) {
90
+ s->alarm = 0;
91
+ s->detect_falling = false;
92
+ }
93
+ } else {
94
+ if (s->temperature >= s->limit[1]) {
95
+ s->alarm = 1;
96
+ s->detect_falling = true;
97
+ }
98
+ }
99
}
115
}
100
116
gicv3_full_update_noirqset(s);
101
tmp105_interrupt_update(s);
117
/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
102
@@ -XXX,XX +XXX,XX @@ static int tmp105_post_load(void *opaque, int version_id)
118
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
103
return 0;
119
index XXXXXXX..XXXXXXX 100644
120
--- a/hw/intc/arm_gicv3_redist.c
121
+++ b/hw/intc/arm_gicv3_redist.c
122
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
123
cs->gicr_ctlr |= GICR_CTLR_ENABLE_LPIS;
124
/* Check for any pending interr in pending table */
125
gicv3_redist_update_lpi(cs);
126
- gicv3_redist_update(cs);
127
} else {
128
cs->gicr_ctlr &= ~GICR_CTLR_ENABLE_LPIS;
129
+ /* cs->hppi might have been an LPI; recalculate */
130
+ gicv3_redist_update(cs);
131
}
132
}
133
return MEMTX_OK;
134
@@ -XXX,XX +XXX,XX @@ static void gicv3_redist_check_lpi_priority(GICv3CPUState *cs, int irq)
135
}
104
}
136
}
105
137
106
+static bool detect_falling_needed(void *opaque)
138
-void gicv3_redist_update_lpi(GICv3CPUState *cs)
139
+void gicv3_redist_update_lpi_only(GICv3CPUState *cs)
140
{
141
/*
142
* This function scans the LPI pending table and for each pending
143
@@ -XXX,XX +XXX,XX @@ void gicv3_redist_update_lpi(GICv3CPUState *cs)
144
}
145
}
146
147
+void gicv3_redist_update_lpi(GICv3CPUState *cs)
107
+{
148
+{
108
+ TMP105State *s = opaque;
149
+ gicv3_redist_update_lpi_only(cs);
109
+
150
+ gicv3_redist_update(cs);
110
+ /*
111
+ * We only need to migrate the detect_falling bool if it's set;
112
+ * for migration from older machines we assume that it is false
113
+ * (ie temperature is not out of range).
114
+ */
115
+ return s->detect_falling;
116
+}
151
+}
117
+
152
+
118
+static const VMStateDescription vmstate_tmp105_detect_falling = {
153
void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level)
119
+ .name = "TMP105/detect-falling",
154
{
120
+ .version_id = 1,
155
/*
121
+ .minimum_version_id = 1,
156
@@ -XXX,XX +XXX,XX @@ void gicv3_redist_lpi_pending(GICv3CPUState *cs, int irq, int level)
122
+ .needed = detect_falling_needed,
157
*/
123
+ .fields = (VMStateField[]) {
158
if (level) {
124
+ VMSTATE_BOOL(detect_falling, TMP105State),
159
gicv3_redist_check_lpi_priority(cs, irq);
125
+ VMSTATE_END_OF_LIST()
160
+ gicv3_redist_update(cs);
126
+ }
161
} else {
127
+};
162
if (irq == cs->hpplpi.irq) {
128
+
163
gicv3_redist_update_lpi(cs);
129
static const VMStateDescription vmstate_tmp105 = {
164
@@ -XXX,XX +XXX,XX @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level)
130
.name = "TMP105",
165
131
.version_id = 0,
166
/* set/clear the pending bit for this irq */
132
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_tmp105 = {
167
gicv3_redist_lpi_pending(cs, irq, level);
133
VMSTATE_UINT8(alarm, TMP105State),
168
-
134
VMSTATE_I2C_SLAVE(i2c, TMP105State),
169
- gicv3_redist_update(cs);
135
VMSTATE_END_OF_LIST()
170
}
136
+ },
171
137
+ .subsections = (const VMStateDescription*[]) {
172
void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level)
138
+ &vmstate_tmp105_detect_falling,
139
+ NULL
140
}
141
};
142
143
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
144
s->config = 0;
145
s->faults = tmp105_faultq[(s->config >> 3) & 3];
146
s->alarm = 0;
147
+ s->detect_falling = false;
148
149
s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
150
s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
151
--
173
--
152
2.20.1
174
2.25.1
153
175
154
176
diff view generated by jsdifflib
1
From: Alex Chen <alex.chen@huawei.com>
1
The GICv3/v4 pseudocode has a function IsSpecial() which returns true
2
if passed a "special" interrupt ID number (anything between 1020 and
3
1023 inclusive). We open-code this condition in a couple of places,
4
so abstract it out into a new function gicv3_intid_is_special().
2
5
3
We should use printf format specifier "%u" instead of "%d" for
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
argument of type "unsigned int".
7
Reviewed-by: Marc Zyngier <maz@kernel.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
---
10
hw/intc/gicv3_internal.h | 13 +++++++++++++
11
hw/intc/arm_gicv3_cpuif.c | 4 ++--
12
2 files changed, 15 insertions(+), 2 deletions(-)
5
13
6
Reported-by: Euler Robot <euler.robot@huawei.com>
14
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20201111073651.72804-1-alex.chen@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/timer/exynos4210_mct.c | 4 ++--
13
hw/timer/exynos4210_pwm.c | 8 ++++----
14
2 files changed, 6 insertions(+), 6 deletions(-)
15
16
diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/exynos4210_mct.c
16
--- a/hw/intc/gicv3_internal.h
19
+++ b/hw/timer/exynos4210_mct.c
17
+++ b/hw/intc/gicv3_internal.h
20
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gcomp_raise_irq(void *opaque, uint32_t id)
18
@@ -XXX,XX +XXX,XX @@ FIELD(MAPC, RDBASE, 16, 32)
21
/* If CSTAT is pending and IRQ is enabled */
19
22
if ((s->reg.int_cstat & G_INT_CSTAT_COMP(id)) &&
20
/* Functions internal to the emulated GICv3 */
23
(s->reg.int_enb & G_INT_ENABLE(id))) {
21
24
- DPRINTF("gcmp timer[%d] IRQ\n", id);
22
+/**
25
+ DPRINTF("gcmp timer[%u] IRQ\n", id);
23
+ * gicv3_intid_is_special:
26
qemu_irq_raise(s->irq[id]);
24
+ * @intid: interrupt ID
25
+ *
26
+ * Return true if @intid is a special interrupt ID (1020 to
27
+ * 1023 inclusive). This corresponds to the GIC spec pseudocode
28
+ * IsSpecial() function.
29
+ */
30
+static inline bool gicv3_intid_is_special(int intid)
31
+{
32
+ return intid >= INTID_SECURE && intid <= INTID_SPURIOUS;
33
+}
34
+
35
/**
36
* gicv3_redist_update:
37
* @cs: GICv3CPUState for this redistributor
38
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/intc/arm_gicv3_cpuif.c
41
+++ b/hw/intc/arm_gicv3_cpuif.c
42
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri)
43
intid = icc_hppir0_value(cs, env);
27
}
44
}
28
}
45
29
@@ -XXX,XX +XXX,XX @@ static void exynos4210_mct_update_freq(Exynos4210MCTState *s)
46
- if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) {
30
MCT_CFG_GET_DIVIDER(s->reg_mct_cfg));
47
+ if (!gicv3_intid_is_special(intid)) {
31
48
icc_activate_irq(cs, intid);
32
if (freq != s->freq) {
33
- DPRINTF("freq=%dHz\n", s->freq);
34
+ DPRINTF("freq=%uHz\n", s->freq);
35
36
/* global timer */
37
tx_ptimer_set_freq(s->g_timer.ptimer_frc, s->freq);
38
diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/timer/exynos4210_pwm.c
41
+++ b/hw/timer/exynos4210_pwm.c
42
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id)
43
44
if (freq != s->timer[id].freq) {
45
ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq);
46
- DPRINTF("freq=%dHz\n", s->timer[id].freq);
47
+ DPRINTF("freq=%uHz\n", s->timer[id].freq);
48
}
49
}
49
}
50
50
51
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
51
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
52
intid = icc_hppir1_value(cs, env);
52
uint32_t id = s->id;
53
bool cmp;
54
55
- DPRINTF("timer %d tick\n", id);
56
+ DPRINTF("timer %u tick\n", id);
57
58
/* set irq status */
59
p->reg_tint_cstat |= TINT_CSTAT_STATUS(id);
60
61
/* raise IRQ */
62
if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) {
63
- DPRINTF("timer %d IRQ\n", id);
64
+ DPRINTF("timer %u IRQ\n", id);
65
qemu_irq_raise(p->timer[id].irq);
66
}
53
}
67
54
68
@@ -XXX,XX +XXX,XX @@ static void exynos4210_pwm_tick(void *opaque)
55
- if (!(intid >= INTID_SECURE && intid <= INTID_SPURIOUS)) {
56
+ if (!gicv3_intid_is_special(intid)) {
57
icc_activate_irq(cs, intid);
69
}
58
}
70
59
71
if (cmp) {
72
- DPRINTF("auto reload timer %d count to %x\n", id,
73
+ DPRINTF("auto reload timer %u count to %x\n", id,
74
p->timer[id].reg_tcntb);
75
ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb);
76
ptimer_run(p->timer[id].ptimer, 1);
77
--
60
--
78
2.20.1
61
2.25.1
79
62
80
63
diff view generated by jsdifflib
Deleted patch
1
In commit 5edab03d4040 we added tracepoints to the ps2 keyboard
2
and mouse emulation. However we didn't remove all the debug-by-printf
3
support. In fact there is only one printf() remaining, and it is
4
redundant with the trace_ps2_write_mouse() event next to it.
5
Remove the printf() and the now-unused DEBUG* macros.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
10
Message-id: 20201101133258.4240-1-peter.maydell@linaro.org
11
---
12
hw/input/ps2.c | 9 ---------
13
1 file changed, 9 deletions(-)
14
15
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/input/ps2.c
18
+++ b/hw/input/ps2.c
19
@@ -XXX,XX +XXX,XX @@
20
21
#include "trace.h"
22
23
-/* debug PC keyboard */
24
-//#define DEBUG_KBD
25
-
26
-/* debug PC keyboard : only mouse */
27
-//#define DEBUG_MOUSE
28
-
29
/* Keyboard Commands */
30
#define KBD_CMD_SET_LEDS    0xED    /* Set keyboard leds */
31
#define KBD_CMD_ECHO     0xEE
32
@@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(void *opaque, int val)
33
PS2MouseState *s = (PS2MouseState *)opaque;
34
35
trace_ps2_write_mouse(opaque, val);
36
-#ifdef DEBUG_MOUSE
37
- printf("kbd: write mouse 0x%02x\n", val);
38
-#endif
39
switch(s->common.write_cmd) {
40
default:
41
case -1:
42
--
43
2.20.1
44
45
diff view generated by jsdifflib
Deleted patch
1
In the mtspr helper we attempt to check for "is the timer disabled"
2
with "if (env->ttmr & TIMER_NONE)". This is wrong because TIMER_NONE
3
is zero and the condition is always false (Coverity complains about
4
the dead code.)
5
1
6
The correct check would be to test whether the TTMR_M field in the
7
register is equal to TIMER_NONE instead. However, the
8
cpu_openrisc_timer_update() function checks whether the timer is
9
enabled (it looks at cpu->env.is_counting, which is set to 0 via
10
cpu_openrisc_count_stop() when the TTMR_M field is set to
11
TIMER_NONE), so there's no need to check for "timer disabled" in the
12
target/openrisc code. Instead, simply remove the dead code.
13
14
Fixes: Coverity CID 1005812
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Acked-by: Stafford Horne <shorne@gmail.com>
17
Message-id: 20201103114654.18540-1-peter.maydell@linaro.org
18
---
19
target/openrisc/sys_helper.c | 3 ---
20
1 file changed, 3 deletions(-)
21
22
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/openrisc/sys_helper.c
25
+++ b/target/openrisc/sys_helper.c
26
@@ -XXX,XX +XXX,XX @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
27
28
case TO_SPR(10, 1): /* TTCR */
29
cpu_openrisc_count_set(cpu, rb);
30
- if (env->ttmr & TIMER_NONE) {
31
- return;
32
- }
33
cpu_openrisc_timer_update(cpu);
34
break;
35
#endif
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
Deleted patch
1
In commit 76346b6264a9b01979 we tried to add a configure check that
2
the libgio pkg-config data was correct, which builds an executable
3
linked against it. Unfortunately this doesn't catch the problem
4
(missing static library dependency info), because a "do nothing" test
5
source file doesn't have any symbol references that cause the linker
6
to pull in .o files from libgio.a, and so we don't see the "missing
7
symbols from libmount" error that a full QEMU link triggers.
8
1
9
(The ineffective test went unnoticed because of a typo that
10
effectively disabled libgio unconditionally, but after commit
11
3569a5dfc11f2 fixed that, a static link of the system emulator on
12
Ubuntu stopped working again.)
13
14
Improve the gio test by having the test source fragment reference a
15
g_dbus function (which is what is indirectly causing us to end up
16
wanting functions from libmount).
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
20
Message-id: 20201116104617.18333-1-peter.maydell@linaro.org
21
---
22
configure | 11 +++++++++--
23
1 file changed, 9 insertions(+), 2 deletions(-)
24
25
diff --git a/configure b/configure
26
index XXXXXXX..XXXXXXX 100755
27
--- a/configure
28
+++ b/configure
29
@@ -XXX,XX +XXX,XX @@ if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
30
# Check that the libraries actually work -- Ubuntu 18.04 ships
31
# with pkg-config --static --libs data for gio-2.0 that is missing
32
# -lblkid and will give a link error.
33
- write_c_skeleton
34
- if compile_prog "" "$gio_libs" ; then
35
+ cat > $TMPC <<EOF
36
+#include <gio/gio.h>
37
+int main(void)
38
+{
39
+ g_dbus_proxy_new_sync(0, 0, 0, 0, 0, 0, 0, 0);
40
+ return 0;
41
+}
42
+EOF
43
+ if compile_prog "$gio_cflags" "$gio_libs" ; then
44
gio=yes
45
else
46
gio=no
47
--
48
2.20.1
49
50
diff view generated by jsdifflib
1
The TMP105 datasheet (https://www.ti.com/lit/gpn/tmp105) says that the
1
It is valid for an OS to put virtual interrupt ID values into the
2
power-up reset values for the T_low and T_high registers are 80 degrees C
2
list registers ICH_LR<n> which are greater than 1023. This
3
and 75 degrees C, which are 0x500 and 0x4B0 hex according to table 5. These
3
corresponds to (for example) KVM using the in-kernel emulated ITS to
4
values are then shifted right by four bits to give the register reset
4
give a (nested) guest an ITS. LPIs are delivered by the L1 kernel to
5
values, since both registers store the 12 bits of temperature data in bits
5
the L2 guest via the list registers in the same way as non-LPI
6
[15..4] of a 16 bit register.
6
interrupts.
7
7
8
We were resetting these registers to zero, which is problematic for Linux
8
QEMU's code for handling writes to ICV_IARn (which happen when the L2
9
guests which enable the alert interrupt and then immediately take an
9
guest acknowledges an interrupt) and to ICV_EOIRn (which happen at
10
unexpected overtemperature alert because the current temperature is above
10
the end of the interrupt) did not consider LPIs, so it would
11
freezing...
11
incorrectly treat interrupt IDs above 1023 as invalid. Fix this by
12
using the correct condition, which is gicv3_intid_is_special().
13
14
Note that the condition in icv_dir_write() is correct -- LPIs
15
are not valid there and so we want to ignore both "special" ID
16
values and LPIs.
17
18
(In the pseudocode this logic is in:
19
- VirtualReadIAR0(), VirtualReadIAR1(), which call IsSpecial()
20
- VirtualWriteEOIR0(), VirtualWriteEOIR1(), which call
21
VirtualIdentifierValid(data, TRUE) meaning "LPIs OK"
22
- VirtualWriteDIR(), which calls VirtualIdentifierValid(data, FALSE)
23
meaning "LPIs not OK")
24
25
This bug doesn't seem to have any visible effect on Linux L2 guests
26
most of the time, because the two bugs cancel each other out: we
27
neither mark the interrupt active nor deactivate it. However it does
28
mean that the L2 vCPU priority while the LPI handler is running will
29
not be correct, so the interrupt handler could be unexpectedly
30
interrupted by a different interrupt.
31
32
(NB: this has nothing to do with using QEMU's emulated ITS.)
12
33
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Cédric Le Goater <clg@kaod.org>
35
Reviewed-by: Marc Zyngier <maz@kernel.org>
15
Message-id: 20201110150023.25533-2-peter.maydell@linaro.org
16
---
36
---
17
hw/misc/tmp105.c | 3 +++
37
hw/intc/arm_gicv3_cpuif.c | 5 ++---
18
1 file changed, 3 insertions(+)
38
1 file changed, 2 insertions(+), 3 deletions(-)
19
39
20
diff --git a/hw/misc/tmp105.c b/hw/misc/tmp105.c
40
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
21
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/misc/tmp105.c
42
--- a/hw/intc/arm_gicv3_cpuif.c
23
+++ b/hw/misc/tmp105.c
43
+++ b/hw/intc/arm_gicv3_cpuif.c
24
@@ -XXX,XX +XXX,XX @@ static void tmp105_reset(I2CSlave *i2c)
44
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
25
s->faults = tmp105_faultq[(s->config >> 3) & 3];
45
26
s->alarm = 0;
46
if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) {
27
47
intid = ich_lr_vintid(lr);
28
+ s->limit[0] = 0x4b00; /* T_LOW, 75 degrees C */
48
- if (intid < INTID_SECURE) {
29
+ s->limit[1] = 0x5000; /* T_HIGH, 80 degrees C */
49
+ if (!gicv3_intid_is_special(intid)) {
30
+
50
icv_activate_irq(cs, idx, grp);
31
tmp105_interrupt_update(s);
51
} else {
32
}
52
/* Interrupt goes from Pending to Invalid */
53
@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
54
trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
55
gicv3_redist_affid(cs), value);
56
57
- if (irq >= GICV3_MAXIRQ) {
58
- /* Also catches special interrupt numbers and LPIs */
59
+ if (gicv3_intid_is_special(irq)) {
60
return;
61
}
33
62
34
--
63
--
35
2.20.1
64
2.25.1
36
65
37
66
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