[PULL 0/2] riscv-to-apply queue
[PULL 00/25] riscv-to-apply queue
1
The following changes since commit 5ececc3a0b0086c6168e12f4d032809477b30fe5:
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20201113' into staging (2020-11-13 13:40:23 +0000)
3
The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:
4
5
Merge tag 'pull-target-arm-20220428' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28 08:34:17 -0700)
4
6
5
are available in the Git repository at:
7
are available in the Git repository at:
6
8
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201113-1
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220429
8
10
9
for you to fetch changes up to deef3d2568a7fbaa62d9bee07708cf3a4dc3ac53:
11
for you to fetch changes up to 325b7c4e7582c229d28c47123c3b986ed948eb84:
10
12
11
intc/ibex_plic: Ensure we don't loose interrupts (2020-11-13 21:43:48 -0800)
13
hw/riscv: Enable TPM backends (2022-04-29 10:48:48 +1000)
12
14
13
----------------------------------------------------------------
15
----------------------------------------------------------------
14
Two small additional fixes for the Ibex PLIC.
16
Second RISC-V PR for QEMU 7.1
17
18
* Improve device tree generation
19
* Support configuarable marchid, mvendorid, mipid CSR values
20
* Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr extensions
21
* Fix incorrect PTE merge in walk_pte
22
* Add TPM support to the virt board
15
23
16
----------------------------------------------------------------
24
----------------------------------------------------------------
17
Alistair Francis (2):
25
Alistair Francis (6):
18
intc/ibex_plic: Fix some typos in the comments
26
hw/riscv: virt: Add a machine done notifier
19
intc/ibex_plic: Ensure we don't loose interrupts
27
hw/core: Move the ARM sysbus-fdt to core
28
hw/riscv: virt: Create a platform bus
29
hw/riscv: virt: Add support for generating platform FDT entries
30
hw/riscv: virt: Add device plug support
31
hw/riscv: Enable TPM backends
20
32
21
include/hw/intc/ibex_plic.h | 1 +
33
Bin Meng (2):
22
hw/intc/ibex_plic.c | 21 ++++++++++++++++++---
34
hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
23
2 files changed, 19 insertions(+), 3 deletions(-)
35
hw/riscv: Don't add empty bootargs to device tree
24
36
37
Frank Chang (1):
38
target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
39
40
Ralf Ramsauer (1):
41
target/riscv: Fix incorrect PTE merge in walk_pte
42
43
Weiwei Li (15):
44
target/riscv: rvk: add cfg properties for zbk* and zk*
45
target/riscv: rvk: add support for zbkb extension
46
target/riscv: rvk: add support for zbkc extension
47
target/riscv: rvk: add support for zbkx extension
48
crypto: move sm4_sbox from target/arm
49
target/riscv: rvk: add support for zknd/zkne extension in RV32
50
target/riscv: rvk: add support for zkne/zknd extension in RV64
51
target/riscv: rvk: add support for sha256 related instructions in zknh extension
52
target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
53
target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
54
target/riscv: rvk: add support for zksed/zksh extension
55
target/riscv: rvk: add CSR support for Zkr
56
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
57
target/riscv: rvk: expose zbk* and zk* properties
58
target/riscv: add scalar crypto related extenstion strings to isa_string
59
60
docs/system/riscv/virt.rst | 20 ++
61
include/crypto/sm4.h | 6 +
62
include/hw/{arm => core}/sysbus-fdt.h | 0
63
include/hw/riscv/virt.h | 8 +-
64
target/riscv/cpu.h | 17 ++
65
target/riscv/cpu_bits.h | 9 +
66
target/riscv/helper.h | 22 ++
67
target/riscv/pmp.h | 8 +-
68
target/riscv/insn32.decode | 97 ++++++--
69
crypto/sm4.c | 49 ++++
70
disas/riscv.c | 173 +++++++++++++-
71
hw/arm/virt.c | 2 +-
72
hw/arm/xlnx-versal-virt.c | 1 -
73
hw/{arm => core}/sysbus-fdt.c | 2 +-
74
hw/riscv/microchip_pfsoc.c | 2 +-
75
hw/riscv/sifive_u.c | 2 +-
76
hw/riscv/spike.c | 7 +-
77
hw/riscv/virt.c | 319 +++++++++++++++++---------
78
target/arm/crypto_helper.c | 36 +--
79
target/riscv/bitmanip_helper.c | 80 +++++++
80
target/riscv/cpu.c | 58 +++++
81
target/riscv/crypto_helper.c | 302 ++++++++++++++++++++++++
82
target/riscv/csr.c | 118 +++++++++-
83
target/riscv/monitor.c | 11 +-
84
target/riscv/op_helper.c | 9 +
85
target/riscv/translate.c | 8 +
86
target/riscv/insn_trans/trans_rvb.c.inc | 116 ++++++++--
87
target/riscv/insn_trans/trans_rvk.c.inc | 391 ++++++++++++++++++++++++++++++++
88
crypto/meson.build | 1 +
89
hw/arm/meson.build | 1 -
90
hw/core/meson.build | 1 +
91
hw/riscv/Kconfig | 2 +
92
target/riscv/meson.build | 3 +-
93
33 files changed, 1682 insertions(+), 199 deletions(-)
94
create mode 100644 include/crypto/sm4.h
95
rename include/hw/{arm => core}/sysbus-fdt.h (100%)
96
create mode 100644 crypto/sm4.c
97
rename hw/{arm => core}/sysbus-fdt.c (99%)
98
create mode 100644 target/riscv/crypto_helper.c
99
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
diff view generated by jsdifflib
New patch
[PULL 01/25] hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
At present the adding '/chosen/stdout-path' property in device tree
4
is determined by whether a kernel command line is provided, which is
5
wrong. It should be added unconditionally.
6
7
Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220421055629.1177285-1-bmeng.cn@gmail.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
hw/riscv/spike.c | 5 +++--
14
1 file changed, 3 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/riscv/spike.c
19
+++ b/hw/riscv/spike.c
20
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
21
22
riscv_socket_fdt_write_distance_matrix(mc, fdt);
23
24
+ qemu_fdt_add_subnode(fdt, "/chosen");
25
+ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
26
+
27
if (cmdline) {
28
- qemu_fdt_add_subnode(fdt, "/chosen");
29
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
30
- qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
31
}
32
}
33
34
--
35
2.35.1
diff view generated by jsdifflib
New patch
[PULL 02/25] hw/riscv: Don't add empty bootargs to device tree
1
From: Bin Meng <bin.meng@windriver.com>
1
2
3
Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
4
tried to avoid adding *NULL* bootargs to device tree, but unfortunately
5
the changes were entirely useless, due to MachineState::kernel_cmdline
6
can't be NULL at all as the default value is given as an empty string.
7
(see hw/core/machine.c::machine_initfn()).
8
9
Note the wording of *NULL* bootargs is wrong. It can't be NULL otherwise
10
a segfault had already been observed by dereferencing the NULL pointer.
11
It should be worded as *empty" bootargs.
12
13
Fixes: 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
14
Signed-off-by: Bin Meng <bin.meng@windriver.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-Id: <20220421055629.1177285-2-bmeng.cn@gmail.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
hw/riscv/microchip_pfsoc.c | 2 +-
20
hw/riscv/sifive_u.c | 2 +-
21
hw/riscv/spike.c | 2 +-
22
hw/riscv/virt.c | 2 +-
23
4 files changed, 4 insertions(+), 4 deletions(-)
24
25
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/riscv/microchip_pfsoc.c
28
+++ b/hw/riscv/microchip_pfsoc.c
29
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
30
"linux,initrd-end", end);
31
}
32
33
- if (machine->kernel_cmdline) {
34
+ if (machine->kernel_cmdline && *machine->kernel_cmdline) {
35
qemu_fdt_setprop_string(machine->fdt, "/chosen",
36
"bootargs", machine->kernel_cmdline);
37
}
38
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/riscv/sifive_u.c
41
+++ b/hw/riscv/sifive_u.c
42
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
43
g_free(nodename);
44
45
update_bootargs:
46
- if (cmdline) {
47
+ if (cmdline && *cmdline) {
48
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
49
}
50
}
51
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/riscv/spike.c
54
+++ b/hw/riscv/spike.c
55
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
56
qemu_fdt_add_subnode(fdt, "/chosen");
57
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif");
58
59
- if (cmdline) {
60
+ if (cmdline && *cmdline) {
61
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
62
}
63
}
64
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/hw/riscv/virt.c
67
+++ b/hw/riscv/virt.c
68
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
69
create_fdt_flash(s, memmap);
70
71
update_bootargs:
72
- if (cmdline) {
73
+ if (cmdline && *cmdline) {
74
qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
75
}
76
}
77
--
78
2.35.1
diff view generated by jsdifflib
New patch
[PULL 03/25] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
1
From: Frank Chang <frank.chang@sifive.com>
1
2
3
Allow user to set core's marchid, mvendorid, mipid CSRs through
4
-cpu command line option.
5
6
The default values of marchid and mipid are built with QEMU's version
7
numbers.
8
9
Signed-off-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Jim Shu <jim.shu@sifive.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
13
Message-Id: <20220422040436.2233-1-frank.chang@sifive.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/cpu.h | 4 ++++
17
target/riscv/cpu.c | 9 +++++++++
18
target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
19
3 files changed, 47 insertions(+), 4 deletions(-)
20
21
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.h
24
+++ b/target/riscv/cpu.h
25
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
26
bool ext_zve32f;
27
bool ext_zve64f;
28
29
+ uint32_t mvendorid;
30
+ uint64_t marchid;
31
+ uint64_t mipid;
32
+
33
/* Vendor-specific custom extensions */
34
bool ext_XVentanaCondOps;
35
36
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/cpu.c
39
+++ b/target/riscv/cpu.c
40
@@ -XXX,XX +XXX,XX @@
41
42
/* RISC-V CPU definitions */
43
44
+#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
45
+ (QEMU_VERSION_MINOR << 8) | \
46
+ (QEMU_VERSION_MICRO))
47
+#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
48
+
49
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
50
51
struct isa_ext_data {
52
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
53
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
54
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
55
56
+ DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
57
+ DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
58
+ DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
59
+
60
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
61
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
62
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
63
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/riscv/csr.c
66
+++ b/target/riscv/csr.c
67
@@ -XXX,XX +XXX,XX @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
68
return RISCV_EXCP_NONE;
69
}
70
71
+static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
72
+ target_ulong *val)
73
+{
74
+ CPUState *cs = env_cpu(env);
75
+ RISCVCPU *cpu = RISCV_CPU(cs);
76
+
77
+ *val = cpu->cfg.mvendorid;
78
+ return RISCV_EXCP_NONE;
79
+}
80
+
81
+static RISCVException read_marchid(CPURISCVState *env, int csrno,
82
+ target_ulong *val)
83
+{
84
+ CPUState *cs = env_cpu(env);
85
+ RISCVCPU *cpu = RISCV_CPU(cs);
86
+
87
+ *val = cpu->cfg.marchid;
88
+ return RISCV_EXCP_NONE;
89
+}
90
+
91
+static RISCVException read_mipid(CPURISCVState *env, int csrno,
92
+ target_ulong *val)
93
+{
94
+ CPUState *cs = env_cpu(env);
95
+ RISCVCPU *cpu = RISCV_CPU(cs);
96
+
97
+ *val = cpu->cfg.mipid;
98
+ return RISCV_EXCP_NONE;
99
+}
100
+
101
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
102
target_ulong *val)
103
{
104
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
105
[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
106
107
/* Machine Information Registers */
108
- [CSR_MVENDORID] = { "mvendorid", any, read_zero },
109
- [CSR_MARCHID] = { "marchid", any, read_zero },
110
- [CSR_MIMPID] = { "mimpid", any, read_zero },
111
- [CSR_MHARTID] = { "mhartid", any, read_mhartid },
112
+ [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
113
+ [CSR_MARCHID] = { "marchid", any, read_marchid },
114
+ [CSR_MIMPID] = { "mimpid", any, read_mipid },
115
+ [CSR_MHARTID] = { "mhartid", any, read_mhartid },
116
117
[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
118
.min_priv_ver = PRIV_VERSION_1_12_0 },
119
--
120
2.35.1
diff view generated by jsdifflib
New patch
[PULL 04/25] target/riscv: rvk: add cfg properties for zbk* and zk*
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
4
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
5
Acked-by: Alistair Francis <alistair.francis@wdc.com>
6
Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn>
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
---
9
target/riscv/cpu.h | 13 +++++++++++++
10
target/riscv/cpu.c | 23 +++++++++++++++++++++++
11
2 files changed, 36 insertions(+)
12
13
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/riscv/cpu.h
16
+++ b/target/riscv/cpu.h
17
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
18
bool ext_zba;
19
bool ext_zbb;
20
bool ext_zbc;
21
+ bool ext_zbkb;
22
+ bool ext_zbkc;
23
+ bool ext_zbkx;
24
bool ext_zbs;
25
+ bool ext_zk;
26
+ bool ext_zkn;
27
+ bool ext_zknd;
28
+ bool ext_zkne;
29
+ bool ext_zknh;
30
+ bool ext_zkr;
31
+ bool ext_zks;
32
+ bool ext_zksed;
33
+ bool ext_zksh;
34
+ bool ext_zkt;
35
bool ext_counters;
36
bool ext_ifencei;
37
bool ext_icsr;
38
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/riscv/cpu.c
41
+++ b/target/riscv/cpu.c
42
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
43
cpu->cfg.ext_zfinx = true;
44
}
45
46
+ if (cpu->cfg.ext_zk) {
47
+ cpu->cfg.ext_zkn = true;
48
+ cpu->cfg.ext_zkr = true;
49
+ cpu->cfg.ext_zkt = true;
50
+ }
51
+
52
+ if (cpu->cfg.ext_zkn) {
53
+ cpu->cfg.ext_zbkb = true;
54
+ cpu->cfg.ext_zbkc = true;
55
+ cpu->cfg.ext_zbkx = true;
56
+ cpu->cfg.ext_zkne = true;
57
+ cpu->cfg.ext_zknd = true;
58
+ cpu->cfg.ext_zknh = true;
59
+ }
60
+
61
+ if (cpu->cfg.ext_zks) {
62
+ cpu->cfg.ext_zbkb = true;
63
+ cpu->cfg.ext_zbkc = true;
64
+ cpu->cfg.ext_zbkx = true;
65
+ cpu->cfg.ext_zksed = true;
66
+ cpu->cfg.ext_zksh = true;
67
+ }
68
+
69
/* Set the ISA extensions, checks should have happened above */
70
if (cpu->cfg.ext_i) {
71
ext |= RVI;
72
--
73
2.35.1
diff view generated by jsdifflib
New patch
[PULL 05/25] target/riscv: rvk: add support for zbkb extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- reuse partial instructions of zbb extension, update extension check for them
4
- add brev8, pack, packh, packw, unzip, zip instructions
5
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220423023510.30794-3-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/helper.h | 3 +
14
target/riscv/insn32.decode | 45 +++++++-----
15
target/riscv/bitmanip_helper.c | 53 ++++++++++++++
16
target/riscv/translate.c | 7 ++
17
target/riscv/insn_trans/trans_rvb.c.inc | 94 +++++++++++++++++++++----
18
5 files changed, 174 insertions(+), 28 deletions(-)
19
20
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/helper.h
23
+++ b/target/riscv/helper.h
24
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64)
25
/* Bitmanip */
26
DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
27
DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
28
+DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
29
+DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
30
+DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
31
32
/* Floating Point - Half Precision */
33
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
34
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/insn32.decode
37
+++ b/target/riscv/insn32.decode
38
@@ -XXX,XX +XXX,XX @@ sh2add_uw 0010000 .......... 100 ..... 0111011 @r
39
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
40
slli_uw 00001 ............ 001 ..... 0011011 @sh
41
42
-# *** RV32 Zbb Standard Extension ***
43
+# *** RV32 Zbb/Zbkb Standard Extension ***
44
andn 0100000 .......... 111 ..... 0110011 @r
45
+rol 0110000 .......... 001 ..... 0110011 @r
46
+ror 0110000 .......... 101 ..... 0110011 @r
47
+rori 01100 ............ 101 ..... 0010011 @sh
48
+# The encoding for rev8 differs between RV32 and RV64.
49
+# rev8_32 denotes the RV32 variant.
50
+rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
51
+# The encoding for zext.h differs between RV32 and RV64.
52
+# zext_h_32 denotes the RV32 variant.
53
+{
54
+ zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
55
+ pack 0000100 ..... ..... 100 ..... 0110011 @r
56
+}
57
+xnor 0100000 .......... 100 ..... 0110011 @r
58
+# *** RV32 extra Zbb Standard Extension ***
59
clz 011000 000000 ..... 001 ..... 0010011 @r2
60
cpop 011000 000010 ..... 001 ..... 0010011 @r2
61
ctz 011000 000001 ..... 001 ..... 0010011 @r2
62
@@ -XXX,XX +XXX,XX @@ min 0000101 .......... 100 ..... 0110011 @r
63
minu 0000101 .......... 101 ..... 0110011 @r
64
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
65
orn 0100000 .......... 110 ..... 0110011 @r
66
-# The encoding for rev8 differs between RV32 and RV64.
67
-# rev8_32 denotes the RV32 variant.
68
-rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
69
-rol 0110000 .......... 001 ..... 0110011 @r
70
-ror 0110000 .......... 101 ..... 0110011 @r
71
-rori 01100 ............ 101 ..... 0010011 @sh
72
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
73
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
74
-xnor 0100000 .......... 100 ..... 0110011 @r
75
-# The encoding for zext.h differs between RV32 and RV64.
76
-# zext_h_32 denotes the RV32 variant.
77
-zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
78
+# *** RV32 extra Zbkb Standard Extension ***
79
+brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
80
+packh 0000100 .......... 111 ..... 0110011 @r
81
+unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
82
+zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
83
84
-# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
85
-clzw 0110000 00000 ..... 001 ..... 0011011 @r2
86
-ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
87
-cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
88
+# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
89
# The encoding for rev8 differs between RV32 and RV64.
90
# When executing on RV64, the encoding used in RV32 is an illegal
91
# instruction, so we use different handler functions to differentiate.
92
@@ -XXX,XX +XXX,XX @@ rorw 0110000 .......... 101 ..... 0111011 @r
93
# The encoding for zext.h differs between RV32 and RV64.
94
# When executing on RV64, the encoding used in RV32 is an illegal
95
# instruction, so we use different handler functions to differentiate.
96
-zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
97
+{
98
+ zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
99
+ packw 0000100 ..... ..... 100 ..... 0111011 @r
100
+}
101
+# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
102
+clzw 0110000 00000 ..... 001 ..... 0011011 @r2
103
+ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
104
+cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
105
106
# *** RV32 Zbc Standard Extension ***
107
clmul 0000101 .......... 001 ..... 0110011 @r
108
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/riscv/bitmanip_helper.c
111
+++ b/target/riscv/bitmanip_helper.c
112
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
113
114
return result;
115
}
116
+
117
+static inline target_ulong do_swap(target_ulong x, uint64_t mask, int shift)
118
+{
119
+ return ((x & mask) << shift) | ((x & ~mask) >> shift);
120
+}
121
+
122
+target_ulong HELPER(brev8)(target_ulong rs1)
123
+{
124
+ target_ulong x = rs1;
125
+
126
+ x = do_swap(x, 0x5555555555555555ull, 1);
127
+ x = do_swap(x, 0x3333333333333333ull, 2);
128
+ x = do_swap(x, 0x0f0f0f0f0f0f0f0full, 4);
129
+ return x;
130
+}
131
+
132
+static const uint64_t shuf_masks[] = {
133
+ dup_const(MO_8, 0x44),
134
+ dup_const(MO_8, 0x30),
135
+ dup_const(MO_16, 0x0f00),
136
+ dup_const(MO_32, 0xff0000)
137
+};
138
+
139
+static inline target_ulong do_shuf_stage(target_ulong src, uint64_t maskL,
140
+ uint64_t maskR, int shift)
141
+{
142
+ target_ulong x = src & ~(maskL | maskR);
143
+
144
+ x |= ((src << shift) & maskL) | ((src >> shift) & maskR);
145
+ return x;
146
+}
147
+
148
+target_ulong HELPER(unzip)(target_ulong rs1)
149
+{
150
+ target_ulong x = rs1;
151
+
152
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
153
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
154
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
155
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
156
+ return x;
157
+}
158
+
159
+target_ulong HELPER(zip)(target_ulong rs1)
160
+{
161
+ target_ulong x = rs1;
162
+
163
+ x = do_shuf_stage(x, shuf_masks[3], shuf_masks[3] >> 8, 8);
164
+ x = do_shuf_stage(x, shuf_masks[2], shuf_masks[2] >> 4, 4);
165
+ x = do_shuf_stage(x, shuf_masks[1], shuf_masks[1] >> 2, 2);
166
+ x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
167
+ return x;
168
+}
169
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
170
index XXXXXXX..XXXXXXX 100644
171
--- a/target/riscv/translate.c
172
+++ b/target/riscv/translate.c
173
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
174
} \
175
} while (0)
176
177
+#define REQUIRE_EITHER_EXT(ctx, A, B) do { \
178
+ if (!ctx->cfg_ptr->ext_##A && \
179
+ !ctx->cfg_ptr->ext_##B) { \
180
+ return false; \
181
+ } \
182
+} while (0)
183
+
184
static int ex_rvc_register(DisasContext *ctx, int reg)
185
{
186
return 8 + reg;
187
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
188
index XXXXXXX..XXXXXXX 100644
189
--- a/target/riscv/insn_trans/trans_rvb.c.inc
190
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
191
@@ -XXX,XX +XXX,XX @@
192
/*
193
- * RISC-V translation routines for the Zb[abcs] Standard Extension.
194
+ * RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
195
*
196
* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
197
* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
198
@@ -XXX,XX +XXX,XX @@
199
} \
200
} while (0)
201
202
+#define REQUIRE_ZBKB(ctx) do { \
203
+ if (!ctx->cfg_ptr->ext_zbkb) { \
204
+ return false; \
205
+ } \
206
+} while (0)
207
+
208
static void gen_clz(TCGv ret, TCGv arg1)
209
{
210
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
211
@@ -XXX,XX +XXX,XX @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
212
213
static bool trans_andn(DisasContext *ctx, arg_andn *a)
214
{
215
- REQUIRE_ZBB(ctx);
216
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
217
return gen_logic(ctx, a, tcg_gen_andc_tl);
218
}
219
220
static bool trans_orn(DisasContext *ctx, arg_orn *a)
221
{
222
- REQUIRE_ZBB(ctx);
223
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
224
return gen_logic(ctx, a, tcg_gen_orc_tl);
225
}
226
227
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
228
{
229
- REQUIRE_ZBB(ctx);
230
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
231
return gen_logic(ctx, a, tcg_gen_eqv_tl);
232
}
233
234
@@ -XXX,XX +XXX,XX @@ static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
235
236
static bool trans_ror(DisasContext *ctx, arg_ror *a)
237
{
238
- REQUIRE_ZBB(ctx);
239
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
240
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
241
}
242
243
@@ -XXX,XX +XXX,XX @@ static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
244
245
static bool trans_rori(DisasContext *ctx, arg_rori *a)
246
{
247
- REQUIRE_ZBB(ctx);
248
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
249
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
250
tcg_gen_rotri_tl, gen_roriw, NULL);
251
}
252
@@ -XXX,XX +XXX,XX @@ static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
253
254
static bool trans_rol(DisasContext *ctx, arg_rol *a)
255
{
256
- REQUIRE_ZBB(ctx);
257
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
258
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
259
}
260
261
@@ -XXX,XX +XXX,XX @@ static void gen_rev8_32(TCGv ret, TCGv src1)
262
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
263
{
264
REQUIRE_32BIT(ctx);
265
- REQUIRE_ZBB(ctx);
266
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
267
return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
268
}
269
270
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
271
{
272
REQUIRE_64BIT(ctx);
273
- REQUIRE_ZBB(ctx);
274
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
275
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
276
}
277
278
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
279
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
280
{
281
REQUIRE_64BIT(ctx);
282
- REQUIRE_ZBB(ctx);
283
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
284
ctx->ol = MXL_RV32;
285
return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
286
}
287
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
288
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
289
{
290
REQUIRE_64BIT(ctx);
291
- REQUIRE_ZBB(ctx);
292
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
293
ctx->ol = MXL_RV32;
294
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
295
}
296
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
297
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
298
{
299
REQUIRE_64BIT(ctx);
300
- REQUIRE_ZBB(ctx);
301
+ REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
302
ctx->ol = MXL_RV32;
303
return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
304
}
305
@@ -XXX,XX +XXX,XX @@ static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
306
REQUIRE_ZBC(ctx);
307
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
308
}
309
+
310
+static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
311
+{
312
+ tcg_gen_deposit_tl(ret, src1, src2,
313
+ TARGET_LONG_BITS / 2,
314
+ TARGET_LONG_BITS / 2);
315
+}
316
+
317
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
318
+{
319
+ TCGv t = tcg_temp_new();
320
+
321
+ tcg_gen_ext8u_tl(t, src2);
322
+ tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
323
+ tcg_temp_free(t);
324
+}
325
+
326
+static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
327
+{
328
+ TCGv t = tcg_temp_new();
329
+
330
+ tcg_gen_ext16s_tl(t, src2);
331
+ tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
332
+ tcg_temp_free(t);
333
+}
334
+
335
+static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
336
+{
337
+ REQUIRE_ZBKB(ctx);
338
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
339
+}
340
+
341
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
342
+{
343
+ REQUIRE_ZBKB(ctx);
344
+ return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
345
+}
346
+
347
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
348
+{
349
+ REQUIRE_ZBKB(ctx);
350
+ return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
351
+}
352
+
353
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
354
+{
355
+ REQUIRE_64BIT(ctx);
356
+ REQUIRE_ZBKB(ctx);
357
+ return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
358
+}
359
+
360
+static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
361
+{
362
+ REQUIRE_32BIT(ctx);
363
+ REQUIRE_ZBKB(ctx);
364
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
365
+}
366
+
367
+static bool trans_zip(DisasContext *ctx, arg_zip *a)
368
+{
369
+ REQUIRE_32BIT(ctx);
370
+ REQUIRE_ZBKB(ctx);
371
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
372
+}
373
--
374
2.35.1
diff view generated by jsdifflib
New patch
[PULL 06/25] target/riscv: rvk: add support for zbkc extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- reuse partial instructions of zbc extension, update extension check for them
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/insn32.decode | 3 ++-
13
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
14
2 files changed, 4 insertions(+), 3 deletions(-)
15
16
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/riscv/insn32.decode
19
+++ b/target/riscv/insn32.decode
20
@@ -XXX,XX +XXX,XX @@ clzw 0110000 00000 ..... 001 ..... 0011011 @r2
21
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
22
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
23
24
-# *** RV32 Zbc Standard Extension ***
25
+# *** RV32 Zbc/Zbkc Standard Extension ***
26
clmul 0000101 .......... 001 ..... 0110011 @r
27
clmulh 0000101 .......... 011 ..... 0110011 @r
28
+# *** RV32 extra Zbc Standard Extension ***
29
clmulr 0000101 .......... 010 ..... 0110011 @r
30
31
# *** RV32 Zbs Standard Extension ***
32
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/riscv/insn_trans/trans_rvb.c.inc
35
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
36
@@ -XXX,XX +XXX,XX @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
37
38
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
39
{
40
- REQUIRE_ZBC(ctx);
41
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
42
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
43
}
44
45
@@ -XXX,XX +XXX,XX @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
46
47
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
48
{
49
- REQUIRE_ZBC(ctx);
50
+ REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
51
return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
52
}
53
54
--
55
2.35.1
diff view generated by jsdifflib
New patch
[PULL 07/25] target/riscv: rvk: add support for zbkx extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add xperm4 and xperm8 instructions
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20220423023510.30794-5-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/helper.h | 2 ++
13
target/riscv/insn32.decode | 4 ++++
14
target/riscv/bitmanip_helper.c | 27 +++++++++++++++++++++++++
15
target/riscv/insn_trans/trans_rvb.c.inc | 18 +++++++++++++++++
16
4 files changed, 51 insertions(+)
17
18
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/riscv/helper.h
21
+++ b/target/riscv/helper.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
23
DEF_HELPER_FLAGS_1(brev8, TCG_CALL_NO_RWG_SE, tl, tl)
24
DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)
25
DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)
26
+DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)
27
+DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)
28
29
/* Floating Point - Half Precision */
30
DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)
31
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/insn32.decode
34
+++ b/target/riscv/insn32.decode
35
@@ -XXX,XX +XXX,XX @@ clmulh 0000101 .......... 011 ..... 0110011 @r
36
# *** RV32 extra Zbc Standard Extension ***
37
clmulr 0000101 .......... 010 ..... 0110011 @r
38
39
+# *** RV32 Zbkx Standard Extension ***
40
+xperm4 0010100 .......... 010 ..... 0110011 @r
41
+xperm8 0010100 .......... 100 ..... 0110011 @r
42
+
43
# *** RV32 Zbs Standard Extension ***
44
bclr 0100100 .......... 001 ..... 0110011 @r
45
bclri 01001. ........... 001 ..... 0010011 @sh
46
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/bitmanip_helper.c
49
+++ b/target/riscv/bitmanip_helper.c
50
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(zip)(target_ulong rs1)
51
x = do_shuf_stage(x, shuf_masks[0], shuf_masks[0] >> 1, 1);
52
return x;
53
}
54
+
55
+static inline target_ulong do_xperm(target_ulong rs1, target_ulong rs2,
56
+ uint32_t sz_log2)
57
+{
58
+ target_ulong r = 0;
59
+ target_ulong sz = 1LL << sz_log2;
60
+ target_ulong mask = (1LL << sz) - 1;
61
+ target_ulong pos;
62
+
63
+ for (int i = 0; i < TARGET_LONG_BITS; i += sz) {
64
+ pos = ((rs2 >> i) & mask) << sz_log2;
65
+ if (pos < sizeof(target_ulong) * 8) {
66
+ r |= ((rs1 >> pos) & mask) << i;
67
+ }
68
+ }
69
+ return r;
70
+}
71
+
72
+target_ulong HELPER(xperm4)(target_ulong rs1, target_ulong rs2)
73
+{
74
+ return do_xperm(rs1, rs2, 2);
75
+}
76
+
77
+target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)
78
+{
79
+ return do_xperm(rs1, rs2, 3);
80
+}
81
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/riscv/insn_trans/trans_rvb.c.inc
84
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
85
@@ -XXX,XX +XXX,XX @@
86
} \
87
} while (0)
88
89
+#define REQUIRE_ZBKX(ctx) do { \
90
+ if (!ctx->cfg_ptr->ext_zbkx) { \
91
+ return false; \
92
+ } \
93
+} while (0)
94
+
95
static void gen_clz(TCGv ret, TCGv arg1)
96
{
97
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
98
@@ -XXX,XX +XXX,XX @@ static bool trans_zip(DisasContext *ctx, arg_zip *a)
99
REQUIRE_ZBKB(ctx);
100
return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
101
}
102
+
103
+static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
104
+{
105
+ REQUIRE_ZBKX(ctx);
106
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
107
+}
108
+
109
+static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
110
+{
111
+ REQUIRE_ZBKX(ctx);
112
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
113
+}
114
--
115
2.35.1
diff view generated by jsdifflib
New patch
[PULL 08/25] crypto: move sm4_sbox from target/arm
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- share it between target/arm and target/riscv
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220423023510.30794-6-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
include/crypto/sm4.h | 6 +++++
14
crypto/sm4.c | 49 ++++++++++++++++++++++++++++++++++++++
15
target/arm/crypto_helper.c | 36 +---------------------------
16
crypto/meson.build | 1 +
17
4 files changed, 57 insertions(+), 35 deletions(-)
18
create mode 100644 include/crypto/sm4.h
19
create mode 100644 crypto/sm4.c
20
21
diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h
22
new file mode 100644
23
index XXXXXXX..XXXXXXX
24
--- /dev/null
25
+++ b/include/crypto/sm4.h
26
@@ -XXX,XX +XXX,XX @@
27
+#ifndef QEMU_SM4_H
28
+#define QEMU_SM4_H
29
+
30
+extern const uint8_t sm4_sbox[256];
31
+
32
+#endif
33
diff --git a/crypto/sm4.c b/crypto/sm4.c
34
new file mode 100644
35
index XXXXXXX..XXXXXXX
36
--- /dev/null
37
+++ b/crypto/sm4.c
38
@@ -XXX,XX +XXX,XX @@
39
+/*
40
+ * QEMU crypto sm4 support
41
+ *
42
+ * Copyright (C) 2013 - 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
43
+ *
44
+ * This library is free software; you can redistribute it and/or
45
+ * modify it under the terms of the GNU Lesser General Public
46
+ * License as published by the Free Software Foundation; either
47
+ * version 2.1 of the License, or (at your option) any later version.
48
+ */
49
+
50
+#include "qemu/osdep.h"
51
+#include "crypto/sm4.h"
52
+
53
+uint8_t const sm4_sbox[] = {
54
+ 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
55
+ 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
56
+ 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
57
+ 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
58
+ 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
59
+ 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
60
+ 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
61
+ 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
62
+ 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
63
+ 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
64
+ 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
65
+ 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
66
+ 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
67
+ 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
68
+ 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
69
+ 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
70
+ 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
71
+ 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
72
+ 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
73
+ 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
74
+ 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
75
+ 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
76
+ 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
77
+ 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
78
+ 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
79
+ 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
80
+ 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
81
+ 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
82
+ 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
83
+ 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
84
+ 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
85
+ 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
86
+};
87
+
88
diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/crypto_helper.c
91
+++ b/target/arm/crypto_helper.c
92
@@ -XXX,XX +XXX,XX @@
93
#include "exec/helper-proto.h"
94
#include "tcg/tcg-gvec-desc.h"
95
#include "crypto/aes.h"
96
+#include "crypto/sm4.h"
97
#include "vec_internal.h"
98
99
union CRYPTO_STATE {
100
@@ -XXX,XX +XXX,XX @@ DO_SM3TT(crypto_sm3tt2b, 3)
101
102
#undef DO_SM3TT
103
104
-static uint8_t const sm4_sbox[] = {
105
- 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
106
- 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
107
- 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
108
- 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
109
- 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
110
- 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
111
- 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
112
- 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
113
- 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
114
- 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
115
- 0x68, 0x6b, 0x81, 0xb2, 0x71, 0x64, 0xda, 0x8b,
116
- 0xf8, 0xeb, 0x0f, 0x4b, 0x70, 0x56, 0x9d, 0x35,
117
- 0x1e, 0x24, 0x0e, 0x5e, 0x63, 0x58, 0xd1, 0xa2,
118
- 0x25, 0x22, 0x7c, 0x3b, 0x01, 0x21, 0x78, 0x87,
119
- 0xd4, 0x00, 0x46, 0x57, 0x9f, 0xd3, 0x27, 0x52,
120
- 0x4c, 0x36, 0x02, 0xe7, 0xa0, 0xc4, 0xc8, 0x9e,
121
- 0xea, 0xbf, 0x8a, 0xd2, 0x40, 0xc7, 0x38, 0xb5,
122
- 0xa3, 0xf7, 0xf2, 0xce, 0xf9, 0x61, 0x15, 0xa1,
123
- 0xe0, 0xae, 0x5d, 0xa4, 0x9b, 0x34, 0x1a, 0x55,
124
- 0xad, 0x93, 0x32, 0x30, 0xf5, 0x8c, 0xb1, 0xe3,
125
- 0x1d, 0xf6, 0xe2, 0x2e, 0x82, 0x66, 0xca, 0x60,
126
- 0xc0, 0x29, 0x23, 0xab, 0x0d, 0x53, 0x4e, 0x6f,
127
- 0xd5, 0xdb, 0x37, 0x45, 0xde, 0xfd, 0x8e, 0x2f,
128
- 0x03, 0xff, 0x6a, 0x72, 0x6d, 0x6c, 0x5b, 0x51,
129
- 0x8d, 0x1b, 0xaf, 0x92, 0xbb, 0xdd, 0xbc, 0x7f,
130
- 0x11, 0xd9, 0x5c, 0x41, 0x1f, 0x10, 0x5a, 0xd8,
131
- 0x0a, 0xc1, 0x31, 0x88, 0xa5, 0xcd, 0x7b, 0xbd,
132
- 0x2d, 0x74, 0xd0, 0x12, 0xb8, 0xe5, 0xb4, 0xb0,
133
- 0x89, 0x69, 0x97, 0x4a, 0x0c, 0x96, 0x77, 0x7e,
134
- 0x65, 0xb9, 0xf1, 0x09, 0xc5, 0x6e, 0xc6, 0x84,
135
- 0x18, 0xf0, 0x7d, 0xec, 0x3a, 0xdc, 0x4d, 0x20,
136
- 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48,
137
-};
138
-
139
static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm)
140
{
141
union CRYPTO_STATE d = { .l = { rn[0], rn[1] } };
142
diff --git a/crypto/meson.build b/crypto/meson.build
143
index XXXXXXX..XXXXXXX 100644
144
--- a/crypto/meson.build
145
+++ b/crypto/meson.build
146
@@ -XXX,XX +XXX,XX @@ if have_afalg
147
endif
148
crypto_ss.add(when: gnutls, if_true: files('tls-cipher-suites.c'))
149
150
+util_ss.add(files('sm4.c'))
151
util_ss.add(files('aes.c'))
152
util_ss.add(files('init.c'))
153
if gnutls.found()
154
--
155
2.35.1
diff view generated by jsdifflib
New patch
[PULL 09/25] target/riscv: rvk: add support for zknd/zkne extension in RV32
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
4
5
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220423023510.30794-7-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/helper.h | 6 ++
14
target/riscv/insn32.decode | 11 +++
15
target/riscv/crypto_helper.c | 105 ++++++++++++++++++++++++
16
target/riscv/translate.c | 1 +
17
target/riscv/insn_trans/trans_rvk.c.inc | 71 ++++++++++++++++
18
target/riscv/meson.build | 3 +-
19
6 files changed, 196 insertions(+), 1 deletion(-)
20
create mode 100644 target/riscv/crypto_helper.c
21
create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc
22
23
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/riscv/helper.h
26
+++ b/target/riscv/helper.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(divu_i128, tl, env, tl, tl, tl, tl)
28
DEF_HELPER_5(divs_i128, tl, env, tl, tl, tl, tl)
29
DEF_HELPER_5(remu_i128, tl, env, tl, tl, tl, tl)
30
DEF_HELPER_5(rems_i128, tl, env, tl, tl, tl, tl)
31
+
32
+/* Crypto functions */
33
+DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
34
+DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
35
+DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
36
+DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
37
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/riscv/insn32.decode
40
+++ b/target/riscv/insn32.decode
41
@@ -XXX,XX +XXX,XX @@
42
%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
43
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
44
%imm_u 12:s20 !function=ex_shift_12
45
+%imm_bs 30:2 !function=ex_shift_3
46
47
# Argument sets:
48
&empty
49
@@ -XXX,XX +XXX,XX @@
50
&rmr vm rd rs2
51
&r2nfvm vm rd rs1 nf
52
&rnfvm vm rd rs1 rs2 nf
53
+&k_aes shamt rs2 rs1 rd
54
55
# Formats 32:
56
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
57
@@ -XXX,XX +XXX,XX @@
58
@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
59
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
60
61
+@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
62
+
63
# Formats 64:
64
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
65
66
@@ -XXX,XX +XXX,XX @@ sfence_w_inval 0001100 00000 00000 000 00000 1110011
67
sfence_inval_ir 0001100 00001 00000 000 00000 1110011
68
hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
69
hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
70
+
71
+# *** RV32 Zknd Standard Extension ***
72
+aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
73
+aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
74
+# *** RV32 Zkne Standard Extension ***
75
+aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
76
+aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
77
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
78
new file mode 100644
79
index XXXXXXX..XXXXXXX
80
--- /dev/null
81
+++ b/target/riscv/crypto_helper.c
82
@@ -XXX,XX +XXX,XX @@
83
+/*
84
+ * RISC-V Crypto Emulation Helpers for QEMU.
85
+ *
86
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
87
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
88
+ *
89
+ * This program is free software; you can redistribute it and/or modify it
90
+ * under the terms and conditions of the GNU General Public License,
91
+ * version 2 or later, as published by the Free Software Foundation.
92
+ *
93
+ * This program is distributed in the hope it will be useful, but WITHOUT
94
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
95
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
96
+ * more details.
97
+ *
98
+ * You should have received a copy of the GNU General Public License along with
99
+ * this program. If not, see <http://www.gnu.org/licenses/>.
100
+ */
101
+
102
+#include "qemu/osdep.h"
103
+#include "cpu.h"
104
+#include "exec/exec-all.h"
105
+#include "exec/helper-proto.h"
106
+#include "crypto/aes.h"
107
+#include "crypto/sm4.h"
108
+
109
+#define AES_XTIME(a) \
110
+ ((a << 1) ^ ((a & 0x80) ? 0x1b : 0))
111
+
112
+#define AES_GFMUL(a, b) (( \
113
+ (((b) & 0x1) ? (a) : 0) ^ \
114
+ (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \
115
+ (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \
116
+ (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF)
117
+
118
+static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd)
119
+{
120
+ uint32_t u;
121
+
122
+ if (fwd) {
123
+ u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) |
124
+ (AES_GFMUL(x, 2) << 0);
125
+ } else {
126
+ u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) |
127
+ (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0);
128
+ }
129
+ return u;
130
+}
131
+
132
+#define sext32_xlen(x) (target_ulong)(int32_t)(x)
133
+
134
+static inline target_ulong aes32_operation(target_ulong shamt,
135
+ target_ulong rs1, target_ulong rs2,
136
+ bool enc, bool mix)
137
+{
138
+ uint8_t si = rs2 >> shamt;
139
+ uint8_t so;
140
+ uint32_t mixed;
141
+ target_ulong res;
142
+
143
+ if (enc) {
144
+ so = AES_sbox[si];
145
+ if (mix) {
146
+ mixed = aes_mixcolumn_byte(so, true);
147
+ } else {
148
+ mixed = so;
149
+ }
150
+ } else {
151
+ so = AES_isbox[si];
152
+ if (mix) {
153
+ mixed = aes_mixcolumn_byte(so, false);
154
+ } else {
155
+ mixed = so;
156
+ }
157
+ }
158
+ mixed = rol32(mixed, shamt);
159
+ res = rs1 ^ mixed;
160
+
161
+ return sext32_xlen(res);
162
+}
163
+
164
+target_ulong HELPER(aes32esmi)(target_ulong rs1, target_ulong rs2,
165
+ target_ulong shamt)
166
+{
167
+ return aes32_operation(shamt, rs1, rs2, true, true);
168
+}
169
+
170
+target_ulong HELPER(aes32esi)(target_ulong rs1, target_ulong rs2,
171
+ target_ulong shamt)
172
+{
173
+ return aes32_operation(shamt, rs1, rs2, true, false);
174
+}
175
+
176
+target_ulong HELPER(aes32dsmi)(target_ulong rs1, target_ulong rs2,
177
+ target_ulong shamt)
178
+{
179
+ return aes32_operation(shamt, rs1, rs2, false, true);
180
+}
181
+
182
+target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
183
+ target_ulong shamt)
184
+{
185
+ return aes32_operation(shamt, rs1, rs2, false, false);
186
+}
187
+#undef sext32_xlen
188
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
189
index XXXXXXX..XXXXXXX 100644
190
--- a/target/riscv/translate.c
191
+++ b/target/riscv/translate.c
192
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
193
#include "insn_trans/trans_rvv.c.inc"
194
#include "insn_trans/trans_rvb.c.inc"
195
#include "insn_trans/trans_rvzfh.c.inc"
196
+#include "insn_trans/trans_rvk.c.inc"
197
#include "insn_trans/trans_privileged.c.inc"
198
#include "insn_trans/trans_svinval.c.inc"
199
#include "insn_trans/trans_xventanacondops.c.inc"
200
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
201
new file mode 100644
202
index XXXXXXX..XXXXXXX
203
--- /dev/null
204
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
205
@@ -XXX,XX +XXX,XX @@
206
+/*
207
+ * RISC-V translation routines for the Zk[nd,ne,nh,sed,sh] Standard Extension.
208
+ *
209
+ * Copyright (c) 2021 Ruibo Lu, luruibo2000@163.com
210
+ * Copyright (c) 2021 Zewen Ye, lustrew@foxmail.com
211
+ *
212
+ * This program is free software; you can redistribute it and/or modify it
213
+ * under the terms and conditions of the GNU General Public License,
214
+ * version 2 or later, as published by the Free Software Foundation.
215
+ *
216
+ * This program is distributed in the hope it will be useful, but WITHOUT
217
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
218
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
219
+ * more details.
220
+ *
221
+ * You should have received a copy of the GNU General Public License along with
222
+ * this program. If not, see <http://www.gnu.org/licenses/>.
223
+ */
224
+
225
+#define REQUIRE_ZKND(ctx) do { \
226
+ if (!ctx->cfg_ptr->ext_zknd) { \
227
+ return false; \
228
+ } \
229
+} while (0)
230
+
231
+#define REQUIRE_ZKNE(ctx) do { \
232
+ if (!ctx->cfg_ptr->ext_zkne) { \
233
+ return false; \
234
+ } \
235
+} while (0)
236
+
237
+static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
238
+ void (*func)(TCGv, TCGv, TCGv, TCGv))
239
+{
240
+ TCGv shamt = tcg_constant_tl(a->shamt);
241
+ TCGv dest = dest_gpr(ctx, a->rd);
242
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
243
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
244
+
245
+ func(dest, src1, src2, shamt);
246
+ gen_set_gpr(ctx, a->rd, dest);
247
+ return true;
248
+}
249
+
250
+static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
251
+{
252
+ REQUIRE_32BIT(ctx);
253
+ REQUIRE_ZKNE(ctx);
254
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32esmi);
255
+}
256
+
257
+static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
258
+{
259
+ REQUIRE_32BIT(ctx);
260
+ REQUIRE_ZKNE(ctx);
261
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32esi);
262
+}
263
+
264
+static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
265
+{
266
+ REQUIRE_32BIT(ctx);
267
+ REQUIRE_ZKND(ctx);
268
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32dsmi);
269
+}
270
+
271
+static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
272
+{
273
+ REQUIRE_32BIT(ctx);
274
+ REQUIRE_ZKND(ctx);
275
+ return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
276
+}
277
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
278
index XXXXXXX..XXXXXXX 100644
279
--- a/target/riscv/meson.build
280
+++ b/target/riscv/meson.build
281
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files(
282
'vector_helper.c',
283
'bitmanip_helper.c',
284
'translate.c',
285
- 'm128_helper.c'
286
+ 'm128_helper.c',
287
+ 'crypto_helper.c'
288
))
289
riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
290
291
--
292
2.35.1
diff view generated by jsdifflib
New patch
[PULL 10/25] target/riscv: rvk: add support for zkne/zknd extension in RV64
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions
4
5
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
6
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
7
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Acked-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20220423023510.30794-8-liweiwei@iscas.ac.cn>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
target/riscv/helper.h | 8 ++
15
target/riscv/insn32.decode | 12 ++
16
target/riscv/crypto_helper.c | 169 ++++++++++++++++++++++++
17
target/riscv/insn_trans/trans_rvk.c.inc | 54 ++++++++
18
4 files changed, 243 insertions(+)
19
20
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/riscv/helper.h
23
+++ b/target/riscv/helper.h
24
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(aes32esmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
25
DEF_HELPER_FLAGS_3(aes32esi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
26
DEF_HELPER_FLAGS_3(aes32dsmi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
27
DEF_HELPER_FLAGS_3(aes32dsi, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
28
+
29
+DEF_HELPER_FLAGS_2(aes64esm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
30
+DEF_HELPER_FLAGS_2(aes64es, TCG_CALL_NO_RWG_SE, tl, tl, tl)
31
+DEF_HELPER_FLAGS_2(aes64ds, TCG_CALL_NO_RWG_SE, tl, tl, tl)
32
+DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
33
+DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
34
+DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
35
+DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
36
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/insn32.decode
39
+++ b/target/riscv/insn32.decode
40
@@ -XXX,XX +XXX,XX @@
41
%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
42
%imm_u 12:s20 !function=ex_shift_12
43
%imm_bs 30:2 !function=ex_shift_3
44
+%imm_rnum 20:4
45
46
# Argument sets:
47
&empty
48
@@ -XXX,XX +XXX,XX @@
49
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
50
51
@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
52
+@i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd
53
54
# Formats 64:
55
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
56
@@ -XXX,XX +XXX,XX @@ hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
57
# *** RV32 Zknd Standard Extension ***
58
aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
59
aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
60
+# *** RV64 Zknd Standard Extension ***
61
+aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
62
+aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
63
+aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
64
# *** RV32 Zkne Standard Extension ***
65
aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
66
aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
67
+# *** RV64 Zkne Standard Extension ***
68
+aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
69
+aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
70
+# *** RV64 Zkne/zknd Standard Extension ***
71
+aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
72
+aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
73
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/riscv/crypto_helper.c
76
+++ b/target/riscv/crypto_helper.c
77
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
78
{
79
return aes32_operation(shamt, rs1, rs2, false, false);
80
}
81
+
82
+#define BY(X, I) ((X >> (8 * I)) & 0xFF)
83
+
84
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
85
+ (((RS1 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
86
+ (((RS2 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
87
+ (((RS2 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
88
+ (((RS1 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
89
+
90
+#define AES_INVSHIFROWS_LO(RS1, RS2) ( \
91
+ (((RS2 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
92
+ (((RS1 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
93
+ (((RS1 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
94
+ (((RS2 >> 40) & 0xFF) << 8) | (((RS1 >> 0) & 0xFF) << 0))
95
+
96
+#define AES_MIXBYTE(COL, B0, B1, B2, B3) ( \
97
+ BY(COL, B3) ^ BY(COL, B2) ^ AES_GFMUL(BY(COL, B1), 3) ^ \
98
+ AES_GFMUL(BY(COL, B0), 2))
99
+
100
+#define AES_MIXCOLUMN(COL) ( \
101
+ AES_MIXBYTE(COL, 3, 0, 1, 2) << 24 | \
102
+ AES_MIXBYTE(COL, 2, 3, 0, 1) << 16 | \
103
+ AES_MIXBYTE(COL, 1, 2, 3, 0) << 8 | AES_MIXBYTE(COL, 0, 1, 2, 3) << 0)
104
+
105
+#define AES_INVMIXBYTE(COL, B0, B1, B2, B3) ( \
106
+ AES_GFMUL(BY(COL, B3), 0x9) ^ AES_GFMUL(BY(COL, B2), 0xd) ^ \
107
+ AES_GFMUL(BY(COL, B1), 0xb) ^ AES_GFMUL(BY(COL, B0), 0xe))
108
+
109
+#define AES_INVMIXCOLUMN(COL) ( \
110
+ AES_INVMIXBYTE(COL, 3, 0, 1, 2) << 24 | \
111
+ AES_INVMIXBYTE(COL, 2, 3, 0, 1) << 16 | \
112
+ AES_INVMIXBYTE(COL, 1, 2, 3, 0) << 8 | \
113
+ AES_INVMIXBYTE(COL, 0, 1, 2, 3) << 0)
114
+
115
+static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
116
+ bool enc, bool mix)
117
+{
118
+ uint64_t RS1 = rs1;
119
+ uint64_t RS2 = rs2;
120
+ uint64_t result;
121
+ uint64_t temp;
122
+ uint32_t col_0;
123
+ uint32_t col_1;
124
+
125
+ if (enc) {
126
+ temp = AES_SHIFROWS_LO(RS1, RS2);
127
+ temp = (((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
128
+ ((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
129
+ ((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
130
+ ((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
131
+ ((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
132
+ ((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
133
+ ((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
134
+ ((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56));
135
+ if (mix) {
136
+ col_0 = temp & 0xFFFFFFFF;
137
+ col_1 = temp >> 32;
138
+
139
+ col_0 = AES_MIXCOLUMN(col_0);
140
+ col_1 = AES_MIXCOLUMN(col_1);
141
+
142
+ result = ((uint64_t)col_1 << 32) | col_0;
143
+ } else {
144
+ result = temp;
145
+ }
146
+ } else {
147
+ temp = AES_INVSHIFROWS_LO(RS1, RS2);
148
+ temp = (((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
149
+ ((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
150
+ ((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
151
+ ((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
152
+ ((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
153
+ ((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
154
+ ((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
155
+ ((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56));
156
+ if (mix) {
157
+ col_0 = temp & 0xFFFFFFFF;
158
+ col_1 = temp >> 32;
159
+
160
+ col_0 = AES_INVMIXCOLUMN(col_0);
161
+ col_1 = AES_INVMIXCOLUMN(col_1);
162
+
163
+ result = ((uint64_t)col_1 << 32) | col_0;
164
+ } else {
165
+ result = temp;
166
+ }
167
+ }
168
+
169
+ return result;
170
+}
171
+
172
+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
173
+{
174
+ return aes64_operation(rs1, rs2, true, true);
175
+}
176
+
177
+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
178
+{
179
+ return aes64_operation(rs1, rs2, true, false);
180
+}
181
+
182
+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
183
+{
184
+ return aes64_operation(rs1, rs2, false, false);
185
+}
186
+
187
+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
188
+{
189
+ return aes64_operation(rs1, rs2, false, true);
190
+}
191
+
192
+target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
193
+{
194
+ uint64_t RS1 = rs1;
195
+ uint64_t RS2 = rs2;
196
+ uint32_t rs1_hi = RS1 >> 32;
197
+ uint32_t rs2_lo = RS2;
198
+ uint32_t rs2_hi = RS2 >> 32;
199
+
200
+ uint32_t r_lo = (rs1_hi ^ rs2_lo);
201
+ uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi);
202
+ target_ulong result = ((uint64_t)r_hi << 32) | r_lo;
203
+
204
+ return result;
205
+}
206
+
207
+target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
208
+{
209
+ uint64_t RS1 = rs1;
210
+ static const uint8_t round_consts[10] = {
211
+ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
212
+ };
213
+
214
+ uint8_t enc_rnum = rnum;
215
+ uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
216
+ uint8_t rcon_ = 0;
217
+ target_ulong result;
218
+
219
+ if (enc_rnum != 0xA) {
220
+ temp = ror32(temp, 8); /* Rotate right by 8 */
221
+ rcon_ = round_consts[enc_rnum];
222
+ }
223
+
224
+ temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
225
+ ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
226
+ ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
227
+ ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
228
+
229
+ temp ^= rcon_;
230
+
231
+ result = ((uint64_t)temp << 32) | temp;
232
+
233
+ return result;
234
+}
235
+
236
+target_ulong HELPER(aes64im)(target_ulong rs1)
237
+{
238
+ uint64_t RS1 = rs1;
239
+ uint32_t col_0 = RS1 & 0xFFFFFFFF;
240
+ uint32_t col_1 = RS1 >> 32;
241
+ target_ulong result;
242
+
243
+ col_0 = AES_INVMIXCOLUMN(col_0);
244
+ col_1 = AES_INVMIXCOLUMN(col_1);
245
+
246
+ result = ((uint64_t)col_1 << 32) | col_0;
247
+
248
+ return result;
249
+}
250
#undef sext32_xlen
251
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
252
index XXXXXXX..XXXXXXX 100644
253
--- a/target/riscv/insn_trans/trans_rvk.c.inc
254
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
255
@@ -XXX,XX +XXX,XX @@ static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
256
REQUIRE_ZKND(ctx);
257
return gen_aes32_sm4(ctx, a, gen_helper_aes32dsi);
258
}
259
+
260
+static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
261
+{
262
+ REQUIRE_64BIT(ctx);
263
+ REQUIRE_ZKNE(ctx);
264
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64es, NULL);
265
+}
266
+
267
+static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
268
+{
269
+ REQUIRE_64BIT(ctx);
270
+ REQUIRE_ZKNE(ctx);
271
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64esm, NULL);
272
+}
273
+
274
+static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
275
+{
276
+ REQUIRE_64BIT(ctx);
277
+ REQUIRE_ZKND(ctx);
278
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ds, NULL);
279
+}
280
+
281
+static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
282
+{
283
+ REQUIRE_64BIT(ctx);
284
+ REQUIRE_ZKND(ctx);
285
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64dsm, NULL);
286
+}
287
+
288
+static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
289
+{
290
+ REQUIRE_64BIT(ctx);
291
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
292
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_aes64ks2, NULL);
293
+}
294
+
295
+static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
296
+{
297
+ REQUIRE_64BIT(ctx);
298
+ REQUIRE_EITHER_EXT(ctx, zknd, zkne);
299
+
300
+ if (a->imm > 0xA) {
301
+ return false;
302
+ }
303
+
304
+ return gen_arith_imm_tl(ctx, a, EXT_NONE, gen_helper_aes64ks1i, NULL);
305
+}
306
+
307
+static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
308
+{
309
+ REQUIRE_64BIT(ctx);
310
+ REQUIRE_ZKND(ctx);
311
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
312
+}
313
--
314
2.35.1
diff view generated by jsdifflib
New patch
[PULL 11/25] target/riscv: rvk: add support for sha256 related instructions in zknh extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
4
5
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220423023510.30794-9-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/insn32.decode | 5 +++
14
target/riscv/insn_trans/trans_rvk.c.inc | 55 +++++++++++++++++++++++++
15
2 files changed, 60 insertions(+)
16
17
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/insn32.decode
20
+++ b/target/riscv/insn32.decode
21
@@ -XXX,XX +XXX,XX @@ aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
22
# *** RV64 Zkne/zknd Standard Extension ***
23
aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
24
aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
25
+# *** RV32 Zknh Standard Extension ***
26
+sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
27
+sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
28
+sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
29
+sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
30
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/riscv/insn_trans/trans_rvk.c.inc
33
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
34
@@ -XXX,XX +XXX,XX @@
35
} \
36
} while (0)
37
38
+#define REQUIRE_ZKNH(ctx) do { \
39
+ if (!ctx->cfg_ptr->ext_zknh) { \
40
+ return false; \
41
+ } \
42
+} while (0)
43
+
44
static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
45
void (*func)(TCGv, TCGv, TCGv, TCGv))
46
{
47
@@ -XXX,XX +XXX,XX @@ static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
48
REQUIRE_ZKND(ctx);
49
return gen_unary(ctx, a, EXT_NONE, gen_helper_aes64im);
50
}
51
+
52
+static bool gen_sha256(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
53
+ void (*func)(TCGv_i32, TCGv_i32, int32_t),
54
+ int32_t num1, int32_t num2, int32_t num3)
55
+{
56
+ TCGv dest = dest_gpr(ctx, a->rd);
57
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
58
+ TCGv_i32 t0 = tcg_temp_new_i32();
59
+ TCGv_i32 t1 = tcg_temp_new_i32();
60
+ TCGv_i32 t2 = tcg_temp_new_i32();
61
+
62
+ tcg_gen_trunc_tl_i32(t0, src1);
63
+ tcg_gen_rotri_i32(t1, t0, num1);
64
+ tcg_gen_rotri_i32(t2, t0, num2);
65
+ tcg_gen_xor_i32(t1, t1, t2);
66
+ func(t2, t0, num3);
67
+ tcg_gen_xor_i32(t1, t1, t2);
68
+ tcg_gen_ext_i32_tl(dest, t1);
69
+
70
+ gen_set_gpr(ctx, a->rd, dest);
71
+ tcg_temp_free_i32(t0);
72
+ tcg_temp_free_i32(t1);
73
+ tcg_temp_free_i32(t2);
74
+ return true;
75
+}
76
+
77
+static bool trans_sha256sig0(DisasContext *ctx, arg_sha256sig0 *a)
78
+{
79
+ REQUIRE_ZKNH(ctx);
80
+ return gen_sha256(ctx, a, EXT_NONE, tcg_gen_shri_i32, 7, 18, 3);
81
+}
82
+
83
+static bool trans_sha256sig1(DisasContext *ctx, arg_sha256sig1 *a)
84
+{
85
+ REQUIRE_ZKNH(ctx);
86
+ return gen_sha256(ctx, a, EXT_NONE, tcg_gen_shri_i32, 17, 19, 10);
87
+}
88
+
89
+static bool trans_sha256sum0(DisasContext *ctx, arg_sha256sum0 *a)
90
+{
91
+ REQUIRE_ZKNH(ctx);
92
+ return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 2, 13, 22);
93
+}
94
+
95
+static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
96
+{
97
+ REQUIRE_ZKNH(ctx);
98
+ return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 6, 11, 25);
99
+}
100
--
101
2.35.1
diff view generated by jsdifflib
New patch
[PULL 12/25] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and sha512sig1h instructions
4
5
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220423023510.30794-10-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/insn32.decode | 6 ++
14
target/riscv/insn_trans/trans_rvk.c.inc | 100 ++++++++++++++++++++++++
15
2 files changed, 106 insertions(+)
16
17
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/insn32.decode
20
+++ b/target/riscv/insn32.decode
21
@@ -XXX,XX +XXX,XX @@ sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
22
sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
23
sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
24
sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
25
+sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
26
+sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
27
+sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
28
+sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
29
+sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
30
+sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
31
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/insn_trans/trans_rvk.c.inc
34
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
35
@@ -XXX,XX +XXX,XX @@ static bool trans_sha256sum1(DisasContext *ctx, arg_sha256sum1 *a)
36
REQUIRE_ZKNH(ctx);
37
return gen_sha256(ctx, a, EXT_NONE, tcg_gen_rotri_i32, 6, 11, 25);
38
}
39
+
40
+static bool gen_sha512_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
41
+ void (*func1)(TCGv_i64, TCGv_i64, int64_t),
42
+ void (*func2)(TCGv_i64, TCGv_i64, int64_t),
43
+ int64_t num1, int64_t num2, int64_t num3)
44
+{
45
+ TCGv dest = dest_gpr(ctx, a->rd);
46
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
47
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
48
+ TCGv_i64 t0 = tcg_temp_new_i64();
49
+ TCGv_i64 t1 = tcg_temp_new_i64();
50
+ TCGv_i64 t2 = tcg_temp_new_i64();
51
+
52
+ tcg_gen_concat_tl_i64(t0, src1, src2);
53
+ func1(t1, t0, num1);
54
+ func2(t2, t0, num2);
55
+ tcg_gen_xor_i64(t1, t1, t2);
56
+ tcg_gen_rotri_i64(t2, t0, num3);
57
+ tcg_gen_xor_i64(t1, t1, t2);
58
+ tcg_gen_trunc_i64_tl(dest, t1);
59
+
60
+ gen_set_gpr(ctx, a->rd, dest);
61
+ tcg_temp_free_i64(t0);
62
+ tcg_temp_free_i64(t1);
63
+ tcg_temp_free_i64(t2);
64
+ return true;
65
+}
66
+
67
+static bool trans_sha512sum0r(DisasContext *ctx, arg_sha512sum0r *a)
68
+{
69
+ REQUIRE_32BIT(ctx);
70
+ REQUIRE_ZKNH(ctx);
71
+ return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
72
+ tcg_gen_rotli_i64, 25, 30, 28);
73
+}
74
+
75
+static bool trans_sha512sum1r(DisasContext *ctx, arg_sha512sum1r *a)
76
+{
77
+ REQUIRE_32BIT(ctx);
78
+ REQUIRE_ZKNH(ctx);
79
+ return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
80
+ tcg_gen_rotri_i64, 23, 14, 18);
81
+}
82
+
83
+static bool trans_sha512sig0l(DisasContext *ctx, arg_sha512sig0l *a)
84
+{
85
+ REQUIRE_32BIT(ctx);
86
+ REQUIRE_ZKNH(ctx);
87
+ return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotri_i64,
88
+ tcg_gen_rotri_i64, 1, 7, 8);
89
+}
90
+
91
+static bool trans_sha512sig1l(DisasContext *ctx, arg_sha512sig1l *a)
92
+{
93
+ REQUIRE_32BIT(ctx);
94
+ REQUIRE_ZKNH(ctx);
95
+ return gen_sha512_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64,
96
+ tcg_gen_rotri_i64, 3, 6, 19);
97
+}
98
+
99
+static bool gen_sha512h_rv32(DisasContext *ctx, arg_r *a, DisasExtend ext,
100
+ void (*func)(TCGv_i64, TCGv_i64, int64_t),
101
+ int64_t num1, int64_t num2, int64_t num3)
102
+{
103
+ TCGv dest = dest_gpr(ctx, a->rd);
104
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
105
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
106
+ TCGv_i64 t0 = tcg_temp_new_i64();
107
+ TCGv_i64 t1 = tcg_temp_new_i64();
108
+ TCGv_i64 t2 = tcg_temp_new_i64();
109
+
110
+ tcg_gen_concat_tl_i64(t0, src1, src2);
111
+ func(t1, t0, num1);
112
+ tcg_gen_ext32u_i64(t2, t0);
113
+ tcg_gen_shri_i64(t2, t2, num2);
114
+ tcg_gen_xor_i64(t1, t1, t2);
115
+ tcg_gen_rotri_i64(t2, t0, num3);
116
+ tcg_gen_xor_i64(t1, t1, t2);
117
+ tcg_gen_trunc_i64_tl(dest, t1);
118
+
119
+ gen_set_gpr(ctx, a->rd, dest);
120
+ tcg_temp_free_i64(t0);
121
+ tcg_temp_free_i64(t1);
122
+ tcg_temp_free_i64(t2);
123
+ return true;
124
+}
125
+
126
+static bool trans_sha512sig0h(DisasContext *ctx, arg_sha512sig0h *a)
127
+{
128
+ REQUIRE_32BIT(ctx);
129
+ REQUIRE_ZKNH(ctx);
130
+ return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 1, 7, 8);
131
+}
132
+
133
+static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a)
134
+{
135
+ REQUIRE_32BIT(ctx);
136
+ REQUIRE_ZKNH(ctx);
137
+ return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19);
138
+}
139
--
140
2.35.1
diff view generated by jsdifflib
New patch
[PULL 13/25] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
4
5
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/insn32.decode | 5 +++
14
target/riscv/insn_trans/trans_rvk.c.inc | 53 +++++++++++++++++++++++++
15
2 files changed, 58 insertions(+)
16
17
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/riscv/insn32.decode
20
+++ b/target/riscv/insn32.decode
21
@@ -XXX,XX +XXX,XX @@ sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
22
sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
23
sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
24
sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
25
+# *** RV64 Zknh Standard Extension ***
26
+sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
27
+sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
28
+sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
29
+sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
30
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/riscv/insn_trans/trans_rvk.c.inc
33
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
34
@@ -XXX,XX +XXX,XX @@ static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a)
35
REQUIRE_ZKNH(ctx);
36
return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19);
37
}
38
+
39
+static bool gen_sha512_rv64(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
40
+ void (*func)(TCGv_i64, TCGv_i64, int64_t),
41
+ int64_t num1, int64_t num2, int64_t num3)
42
+{
43
+ TCGv dest = dest_gpr(ctx, a->rd);
44
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
45
+ TCGv_i64 t0 = tcg_temp_new_i64();
46
+ TCGv_i64 t1 = tcg_temp_new_i64();
47
+ TCGv_i64 t2 = tcg_temp_new_i64();
48
+
49
+ tcg_gen_extu_tl_i64(t0, src1);
50
+ tcg_gen_rotri_i64(t1, t0, num1);
51
+ tcg_gen_rotri_i64(t2, t0, num2);
52
+ tcg_gen_xor_i64(t1, t1, t2);
53
+ func(t2, t0, num3);
54
+ tcg_gen_xor_i64(t1, t1, t2);
55
+ tcg_gen_trunc_i64_tl(dest, t1);
56
+
57
+ gen_set_gpr(ctx, a->rd, dest);
58
+ tcg_temp_free_i64(t0);
59
+ tcg_temp_free_i64(t1);
60
+ tcg_temp_free_i64(t2);
61
+ return true;
62
+}
63
+
64
+static bool trans_sha512sig0(DisasContext *ctx, arg_sha512sig0 *a)
65
+{
66
+ REQUIRE_64BIT(ctx);
67
+ REQUIRE_ZKNH(ctx);
68
+ return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 1, 8, 7);
69
+}
70
+
71
+static bool trans_sha512sig1(DisasContext *ctx, arg_sha512sig1 *a)
72
+{
73
+ REQUIRE_64BIT(ctx);
74
+ REQUIRE_ZKNH(ctx);
75
+ return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 19, 61, 6);
76
+}
77
+
78
+static bool trans_sha512sum0(DisasContext *ctx, arg_sha512sum0 *a)
79
+{
80
+ REQUIRE_64BIT(ctx);
81
+ REQUIRE_ZKNH(ctx);
82
+ return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 28, 34, 39);
83
+}
84
+
85
+static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a)
86
+{
87
+ REQUIRE_64BIT(ctx);
88
+ REQUIRE_ZKNH(ctx);
89
+ return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41);
90
+}
91
--
92
2.35.1
diff view generated by jsdifflib
New patch
[PULL 14/25] target/riscv: rvk: add support for zksed/zksh extension
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
4
5
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-Id: <20220423023510.30794-12-liweiwei@iscas.ac.cn>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
---
13
target/riscv/helper.h | 3 ++
14
target/riscv/insn32.decode | 6 +++
15
target/riscv/crypto_helper.c | 28 ++++++++++++
16
target/riscv/insn_trans/trans_rvk.c.inc | 58 +++++++++++++++++++++++++
17
4 files changed, 95 insertions(+)
18
19
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/riscv/helper.h
22
+++ b/target/riscv/helper.h
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(aes64dsm, TCG_CALL_NO_RWG_SE, tl, tl, tl)
24
DEF_HELPER_FLAGS_2(aes64ks2, TCG_CALL_NO_RWG_SE, tl, tl, tl)
25
DEF_HELPER_FLAGS_2(aes64ks1i, TCG_CALL_NO_RWG_SE, tl, tl, tl)
26
DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl)
27
+
28
+DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
29
+DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
30
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/riscv/insn32.decode
33
+++ b/target/riscv/insn32.decode
34
@@ -XXX,XX +XXX,XX @@ sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
35
sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
36
sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
37
sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
38
+# *** RV32 Zksh Standard Extension ***
39
+sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
40
+sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
41
+# *** RV32 Zksed Standard Extension ***
42
+sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
43
+sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
44
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/riscv/crypto_helper.c
47
+++ b/target/riscv/crypto_helper.c
48
@@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes64im)(target_ulong rs1)
49
50
return result;
51
}
52
+
53
+target_ulong HELPER(sm4ed)(target_ulong rs1, target_ulong rs2,
54
+ target_ulong shamt)
55
+{
56
+ uint32_t sb_in = (uint8_t)(rs2 >> shamt);
57
+ uint32_t sb_out = (uint32_t)sm4_sbox[sb_in];
58
+
59
+ uint32_t x = sb_out ^ (sb_out << 8) ^ (sb_out << 2) ^ (sb_out << 18) ^
60
+ ((sb_out & 0x3f) << 26) ^ ((sb_out & 0xC0) << 10);
61
+
62
+ uint32_t rotl = rol32(x, shamt);
63
+
64
+ return sext32_xlen(rotl ^ (uint32_t)rs1);
65
+}
66
+
67
+target_ulong HELPER(sm4ks)(target_ulong rs1, target_ulong rs2,
68
+ target_ulong shamt)
69
+{
70
+ uint32_t sb_in = (uint8_t)(rs2 >> shamt);
71
+ uint32_t sb_out = sm4_sbox[sb_in];
72
+
73
+ uint32_t x = sb_out ^ ((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^
74
+ ((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13);
75
+
76
+ uint32_t rotl = rol32(x, shamt);
77
+
78
+ return sext32_xlen(rotl ^ (uint32_t)rs1);
79
+}
80
#undef sext32_xlen
81
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/riscv/insn_trans/trans_rvk.c.inc
84
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
85
@@ -XXX,XX +XXX,XX @@
86
} \
87
} while (0)
88
89
+#define REQUIRE_ZKSED(ctx) do { \
90
+ if (!ctx->cfg_ptr->ext_zksed) { \
91
+ return false; \
92
+ } \
93
+} while (0)
94
+
95
+#define REQUIRE_ZKSH(ctx) do { \
96
+ if (!ctx->cfg_ptr->ext_zksh) { \
97
+ return false; \
98
+ } \
99
+} while (0)
100
+
101
static bool gen_aes32_sm4(DisasContext *ctx, arg_k_aes *a,
102
void (*func)(TCGv, TCGv, TCGv, TCGv))
103
{
104
@@ -XXX,XX +XXX,XX @@ static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a)
105
REQUIRE_ZKNH(ctx);
106
return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41);
107
}
108
+
109
+/* SM3 */
110
+static bool gen_sm3(DisasContext *ctx, arg_r2 *a, int32_t b, int32_t c)
111
+{
112
+ TCGv dest = dest_gpr(ctx, a->rd);
113
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
114
+ TCGv_i32 t0 = tcg_temp_new_i32();
115
+ TCGv_i32 t1 = tcg_temp_new_i32();
116
+
117
+ tcg_gen_trunc_tl_i32(t0, src1);
118
+ tcg_gen_rotli_i32(t1, t0, b);
119
+ tcg_gen_xor_i32(t1, t0, t1);
120
+ tcg_gen_rotli_i32(t0, t0, c);
121
+ tcg_gen_xor_i32(t1, t1, t0);
122
+ tcg_gen_ext_i32_tl(dest, t1);
123
+ gen_set_gpr(ctx, a->rd, dest);
124
+
125
+ tcg_temp_free_i32(t0);
126
+ tcg_temp_free_i32(t1);
127
+ return true;
128
+}
129
+
130
+static bool trans_sm3p0(DisasContext *ctx, arg_sm3p0 *a)
131
+{
132
+ REQUIRE_ZKSH(ctx);
133
+ return gen_sm3(ctx, a, 9, 17);
134
+}
135
+
136
+static bool trans_sm3p1(DisasContext *ctx, arg_sm3p1 *a)
137
+{
138
+ REQUIRE_ZKSH(ctx);
139
+ return gen_sm3(ctx, a, 15, 23);
140
+}
141
+
142
+/* SM4 */
143
+static bool trans_sm4ed(DisasContext *ctx, arg_sm4ed *a)
144
+{
145
+ REQUIRE_ZKSED(ctx);
146
+ return gen_aes32_sm4(ctx, a, gen_helper_sm4ed);
147
+}
148
+
149
+static bool trans_sm4ks(DisasContext *ctx, arg_sm4ks *a)
150
+{
151
+ REQUIRE_ZKSED(ctx);
152
+ return gen_aes32_sm4(ctx, a, gen_helper_sm4ks);
153
+}
154
--
155
2.35.1
diff view generated by jsdifflib
New patch
[PULL 15/25] target/riscv: rvk: add CSR support for Zkr
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add SEED CSR which must be accessed with a read-write instruction:
4
A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
5
with uimm=0 will raise an illegal instruction exception.
6
- add USEED, SSEED fields for MSECCFG CSR
7
8
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
9
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
10
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
11
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
15
---
16
target/riscv/cpu_bits.h | 9 +++++
17
target/riscv/pmp.h | 8 ++--
18
target/riscv/csr.c | 80 ++++++++++++++++++++++++++++++++++++++++
19
target/riscv/op_helper.c | 9 +++++
20
4 files changed, 103 insertions(+), 3 deletions(-)
21
22
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu_bits.h
25
+++ b/target/riscv/cpu_bits.h
26
@@ -XXX,XX +XXX,XX @@
27
#define CSR_VSPMMASK 0x2c1
28
#define CSR_VSPMBASE 0x2c2
29
30
+/* Crypto Extension */
31
+#define CSR_SEED 0x015
32
+
33
/* mstatus CSR bits */
34
#define MSTATUS_UIE 0x00000001
35
#define MSTATUS_SIE 0x00000002
36
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
37
#define HVICTL_VALID_MASK \
38
(HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO)
39
40
+/* seed CSR bits */
41
+#define SEED_OPST (0b11 << 30)
42
+#define SEED_OPST_BIST (0b00 << 30)
43
+#define SEED_OPST_WAIT (0b01 << 30)
44
+#define SEED_OPST_ES16 (0b10 << 30)
45
+#define SEED_OPST_DEAD (0b11 << 30)
46
#endif
47
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/riscv/pmp.h
50
+++ b/target/riscv/pmp.h
51
@@ -XXX,XX +XXX,XX @@ typedef enum {
52
} pmp_am_t;
53
54
typedef enum {
55
- MSECCFG_MML = 1 << 0,
56
- MSECCFG_MMWP = 1 << 1,
57
- MSECCFG_RLB = 1 << 2
58
+ MSECCFG_MML = 1 << 0,
59
+ MSECCFG_MMWP = 1 << 1,
60
+ MSECCFG_RLB = 1 << 2,
61
+ MSECCFG_USEED = 1 << 8,
62
+ MSECCFG_SSEED = 1 << 9
63
} mseccfg_field_t;
64
65
typedef struct {
66
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/riscv/csr.c
69
+++ b/target/riscv/csr.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "qemu/main-loop.h"
72
#include "exec/exec-all.h"
73
#include "sysemu/cpu-timers.h"
74
+#include "qemu/guest-random.h"
75
+#include "qapi/error.h"
76
77
/* CSR function table public API */
78
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
79
@@ -XXX,XX +XXX,XX @@ static RISCVException debug(CPURISCVState *env, int csrno)
80
}
81
#endif
82
83
+static RISCVException seed(CPURISCVState *env, int csrno)
84
+{
85
+ RISCVCPU *cpu = env_archcpu(env);
86
+
87
+ if (!cpu->cfg.ext_zkr) {
88
+ return RISCV_EXCP_ILLEGAL_INST;
89
+ }
90
+
91
+#if !defined(CONFIG_USER_ONLY)
92
+ /*
93
+ * With a CSR read-write instruction:
94
+ * 1) The seed CSR is always available in machine mode as normal.
95
+ * 2) Attempted access to seed from virtual modes VS and VU always raises
96
+ * an exception(virtual instruction exception only if mseccfg.sseed=1).
97
+ * 3) Without the corresponding access control bit set to 1, any attempted
98
+ * access to seed from U, S or HS modes will raise an illegal instruction
99
+ * exception.
100
+ */
101
+ if (env->priv == PRV_M) {
102
+ return RISCV_EXCP_NONE;
103
+ } else if (riscv_cpu_virt_enabled(env)) {
104
+ if (env->mseccfg & MSECCFG_SSEED) {
105
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
106
+ } else {
107
+ return RISCV_EXCP_ILLEGAL_INST;
108
+ }
109
+ } else {
110
+ if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) {
111
+ return RISCV_EXCP_NONE;
112
+ } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) {
113
+ return RISCV_EXCP_NONE;
114
+ } else {
115
+ return RISCV_EXCP_ILLEGAL_INST;
116
+ }
117
+ }
118
+#else
119
+ return RISCV_EXCP_NONE;
120
+#endif
121
+}
122
+
123
/* User Floating-Point CSRs */
124
static RISCVException read_fflags(CPURISCVState *env, int csrno,
125
target_ulong *val)
126
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
127
128
#endif
129
130
+/* Crypto Extension */
131
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
132
+ target_ulong *ret_value,
133
+ target_ulong new_value,
134
+ target_ulong write_mask)
135
+{
136
+ uint16_t random_v;
137
+ Error *random_e = NULL;
138
+ int random_r;
139
+ target_ulong rval;
140
+
141
+ random_r = qemu_guest_getrandom(&random_v, 2, &random_e);
142
+ if (unlikely(random_r < 0)) {
143
+ /*
144
+ * Failed, for unknown reasons in the crypto subsystem.
145
+ * The best we can do is log the reason and return a
146
+ * failure indication to the guest. There is no reason
147
+ * we know to expect the failure to be transitory, so
148
+ * indicate DEAD to avoid having the guest spin on WAIT.
149
+ */
150
+ qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s",
151
+ __func__, error_get_pretty(random_e));
152
+ error_free(random_e);
153
+ rval = SEED_OPST_DEAD;
154
+ } else {
155
+ rval = random_v | SEED_OPST_ES16;
156
+ }
157
+
158
+ if (ret_value) {
159
+ *ret_value = rval;
160
+ }
161
+
162
+ return RISCV_EXCP_NONE;
163
+}
164
+
165
/*
166
* riscv_csrrw - read and/or update control and status register
167
*
168
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
169
[CSR_TIME] = { "time", ctr, read_time },
170
[CSR_TIMEH] = { "timeh", ctr32, read_timeh },
171
172
+ /* Crypto Extension */
173
+ [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed },
174
+
175
#if !defined(CONFIG_USER_ONLY)
176
/* Machine Timers and Counters */
177
[CSR_MCYCLE] = { "mcycle", any, read_instret },
178
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
179
index XXXXXXX..XXXXXXX 100644
180
--- a/target/riscv/op_helper.c
181
+++ b/target/riscv/op_helper.c
182
@@ -XXX,XX +XXX,XX @@ void helper_raise_exception(CPURISCVState *env, uint32_t exception)
183
184
target_ulong helper_csrr(CPURISCVState *env, int csr)
185
{
186
+ /*
187
+ * The seed CSR must be accessed with a read-write instruction. A
188
+ * read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/
189
+ * CSRRCI with uimm=0 will raise an illegal instruction exception.
190
+ */
191
+ if (csr == CSR_SEED) {
192
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
193
+ }
194
+
195
target_ulong val = 0;
196
RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
197
198
--
199
2.35.1
diff view generated by jsdifflib
New patch
[PULL 16/25] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Co-authored-by: Ruibo Lu <luruibo2000@163.com>
4
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
disas/riscv.c | 173 +++++++++++++++++++++++++++++++++++++++++++++++++-
12
1 file changed, 172 insertions(+), 1 deletion(-)
13
14
diff --git a/disas/riscv.c b/disas/riscv.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/disas/riscv.c
17
+++ b/disas/riscv.c
18
@@ -XXX,XX +XXX,XX @@ typedef enum {
19
rv_codec_css_swsp,
20
rv_codec_css_sdsp,
21
rv_codec_css_sqsp,
22
+ rv_codec_k_bs,
23
+ rv_codec_k_rnum,
24
} rv_codec;
25
26
typedef enum {
27
@@ -XXX,XX +XXX,XX @@ typedef enum {
28
rv_op_bclr = 359,
29
rv_op_binv = 360,
30
rv_op_bext = 361,
31
+ rv_op_aes32esmi = 362,
32
+ rv_op_aes32esi = 363,
33
+ rv_op_aes32dsmi = 364,
34
+ rv_op_aes32dsi = 365,
35
+ rv_op_aes64ks1i = 366,
36
+ rv_op_aes64ks2 = 367,
37
+ rv_op_aes64im = 368,
38
+ rv_op_aes64esm = 369,
39
+ rv_op_aes64es = 370,
40
+ rv_op_aes64dsm = 371,
41
+ rv_op_aes64ds = 372,
42
+ rv_op_sha256sig0 = 373,
43
+ rv_op_sha256sig1 = 374,
44
+ rv_op_sha256sum0 = 375,
45
+ rv_op_sha256sum1 = 376,
46
+ rv_op_sha512sig0 = 377,
47
+ rv_op_sha512sig1 = 378,
48
+ rv_op_sha512sum0 = 379,
49
+ rv_op_sha512sum1 = 380,
50
+ rv_op_sha512sum0r = 381,
51
+ rv_op_sha512sum1r = 382,
52
+ rv_op_sha512sig0l = 383,
53
+ rv_op_sha512sig0h = 384,
54
+ rv_op_sha512sig1l = 385,
55
+ rv_op_sha512sig1h = 386,
56
+ rv_op_sm3p0 = 387,
57
+ rv_op_sm3p1 = 388,
58
+ rv_op_sm4ed = 389,
59
+ rv_op_sm4ks = 390,
60
+ rv_op_brev8 = 391,
61
+ rv_op_pack = 392,
62
+ rv_op_packh = 393,
63
+ rv_op_packw = 394,
64
+ rv_op_unzip = 395,
65
+ rv_op_zip = 396,
66
+ rv_op_xperm4 = 397,
67
+ rv_op_xperm8 = 398,
68
} rv_op;
69
70
/* structures */
71
@@ -XXX,XX +XXX,XX @@ typedef struct {
72
uint8_t succ;
73
uint8_t aq;
74
uint8_t rl;
75
+ uint8_t bs;
76
+ uint8_t rnum;
77
} rv_decode;
78
79
typedef struct {
80
@@ -XXX,XX +XXX,XX @@ static const char rv_freg_name_sym[32][5] = {
81
#define rv_fmt_rd_rs2 "O\t0,2"
82
#define rv_fmt_rs1_offset "O\t1,o"
83
#define rv_fmt_rs2_offset "O\t2,o"
84
+#define rv_fmt_rs1_rs2_bs "O\t1,2,b"
85
+#define rv_fmt_rd_rs1_rnum "O\t0,1,n"
86
87
/* pseudo-instruction constraints */
88
89
@@ -XXX,XX +XXX,XX @@ static const rv_comp_data rvcp_csrrw[] = {
90
{ rv_op_illegal, NULL }
91
};
92
93
+
94
static const rv_comp_data rvcp_csrrs[] = {
95
{ rv_op_rdcycle, rvcc_rdcycle },
96
{ rv_op_rdtime, rvcc_rdtime },
97
@@ -XXX,XX +XXX,XX @@ const rv_opcode_data opcode_data[] = {
98
{ "bclr", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
99
{ "binv", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
100
{ "bext", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
101
+ { "aes32esmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
102
+ { "aes32esi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
103
+ { "aes32dsmi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
104
+ { "aes32dsi", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
105
+ { "aes64ks1i", rv_codec_k_rnum, rv_fmt_rd_rs1_rnum, NULL, 0, 0, 0 },
106
+ { "aes64ks2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
107
+ { "aes64im", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
108
+ { "aes64esm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
109
+ { "aes64es", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
110
+ { "aes64dsm", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
111
+ { "aes64ds", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
112
+ { "sha256sig0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
113
+ { "sha256sig1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
114
+ { "sha256sum0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
115
+ { "sha256sum1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
116
+ { "sha512sig0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
117
+ { "sha512sig1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
118
+ { "sha512sum0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
119
+ { "sha512sum1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
120
+ { "sha512sum0r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
121
+ { "sha512sum1r", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
122
+ { "sha512sig0l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
123
+ { "sha512sig0h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
124
+ { "sha512sig1l", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
125
+ { "sha512sig1h", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
126
+ { "sm3p0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
127
+ { "sm3p1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
128
+ { "sm4ed", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
129
+ { "sm4ks", rv_codec_k_bs, rv_fmt_rs1_rs2_bs, NULL, 0, 0, 0 },
130
+ { "brev8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
131
+ { "pack", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
132
+ { "packh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
133
+ { "packw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
134
+ { "unzip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
135
+ { "zip", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
136
+ { "xperm4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
137
+ { "xperm8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }
138
};
139
140
/* CSR names */
141
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
142
case 0x0003: return "fcsr";
143
case 0x0004: return "uie";
144
case 0x0005: return "utvec";
145
+ case 0x0015: return "seed";
146
case 0x0040: return "uscratch";
147
case 0x0041: return "uepc";
148
case 0x0042: return "ucause";
149
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
150
case 1:
151
switch (((inst >> 27) & 0b11111)) {
152
case 0b00000: op = rv_op_slli; break;
153
+ case 0b00001:
154
+ switch (((inst >> 20) & 0b1111111)) {
155
+ case 0b0001111: op = rv_op_zip; break;
156
+ }
157
+ break;
158
+ case 0b00010:
159
+ switch (((inst >> 20) & 0b1111111)) {
160
+ case 0b0000000: op = rv_op_sha256sum0; break;
161
+ case 0b0000001: op = rv_op_sha256sum1; break;
162
+ case 0b0000010: op = rv_op_sha256sig0; break;
163
+ case 0b0000011: op = rv_op_sha256sig1; break;
164
+ case 0b0000100: op = rv_op_sha512sum0; break;
165
+ case 0b0000101: op = rv_op_sha512sum1; break;
166
+ case 0b0000110: op = rv_op_sha512sig0; break;
167
+ case 0b0000111: op = rv_op_sha512sig1; break;
168
+ case 0b0001000: op = rv_op_sm3p0; break;
169
+ case 0b0001001: op = rv_op_sm3p1; break;
170
+ }
171
+ break;
172
case 0b00101: op = rv_op_bseti; break;
173
+ case 0b00110:
174
+ switch (((inst >> 20) & 0b1111111)) {
175
+ case 0b0000000: op = rv_op_aes64im; break;
176
+ default:
177
+ if (((inst >> 24) & 0b0111) == 0b001) {
178
+ op = rv_op_aes64ks1i;
179
+ }
180
+ break;
181
+ }
182
+ break;
183
case 0b01001: op = rv_op_bclri; break;
184
case 0b01101: op = rv_op_binvi; break;
185
case 0b01100:
186
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
187
case 5:
188
switch (((inst >> 27) & 0b11111)) {
189
case 0b00000: op = rv_op_srli; break;
190
+ case 0b00001:
191
+ switch (((inst >> 20) & 0b1111111)) {
192
+ case 0b0001111: op = rv_op_unzip; break;
193
+ }
194
+ break;
195
case 0b00101: op = rv_op_orc_b; break;
196
case 0b01000: op = rv_op_srai; break;
197
case 0b01001: op = rv_op_bexti; break;
198
case 0b01100: op = rv_op_rori; break;
199
case 0b01101:
200
switch ((inst >> 20) & 0b1111111) {
201
+ case 0b0011000: op = rv_op_rev8; break;
202
case 0b0111000: op = rv_op_rev8; break;
203
+ case 0b0000111: op = rv_op_brev8; break;
204
}
205
break;
206
}
207
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
208
case 36:
209
switch ((inst >> 20) & 0b11111) {
210
case 0: op = rv_op_zext_h; break;
211
+ default: op = rv_op_pack; break;
212
}
213
break;
214
+ case 39: op = rv_op_packh; break;
215
+
216
case 41: op = rv_op_clmul; break;
217
case 42: op = rv_op_clmulr; break;
218
case 43: op = rv_op_clmulh; break;
219
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
220
case 132: op = rv_op_sh2add; break;
221
case 134: op = rv_op_sh3add; break;
222
case 161: op = rv_op_bset; break;
223
+ case 162: op = rv_op_xperm4; break;
224
+ case 164: op = rv_op_xperm8; break;
225
+ case 200: op = rv_op_aes64es; break;
226
+ case 216: op = rv_op_aes64esm; break;
227
+ case 232: op = rv_op_aes64ds; break;
228
+ case 248: op = rv_op_aes64dsm; break;
229
case 256: op = rv_op_sub; break;
230
case 260: op = rv_op_xnor; break;
231
case 261: op = rv_op_sra; break;
232
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
233
case 263: op = rv_op_andn; break;
234
case 289: op = rv_op_bclr; break;
235
case 293: op = rv_op_bext; break;
236
+ case 320: op = rv_op_sha512sum0r; break;
237
+ case 328: op = rv_op_sha512sum1r; break;
238
+ case 336: op = rv_op_sha512sig0l; break;
239
+ case 344: op = rv_op_sha512sig1l; break;
240
+ case 368: op = rv_op_sha512sig0h; break;
241
+ case 376: op = rv_op_sha512sig1h; break;
242
case 385: op = rv_op_rol; break;
243
- case 386: op = rv_op_ror; break;
244
+ case 389: op = rv_op_ror; break;
245
case 417: op = rv_op_binv; break;
246
+ case 504: op = rv_op_aes64ks2; break;
247
+ }
248
+ switch ((inst >> 25) & 0b0011111) {
249
+ case 17: op = rv_op_aes32esi; break;
250
+ case 19: op = rv_op_aes32esmi; break;
251
+ case 21: op = rv_op_aes32dsi; break;
252
+ case 23: op = rv_op_aes32dsmi; break;
253
+ case 24: op = rv_op_sm4ed; break;
254
+ case 26: op = rv_op_sm4ks; break;
255
}
256
break;
257
case 13: op = rv_op_lui; break;
258
@@ -XXX,XX +XXX,XX @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
259
case 36:
260
switch ((inst >> 20) & 0b11111) {
261
case 0: op = rv_op_zext_h; break;
262
+ default: op = rv_op_packw; break;
263
}
264
break;
265
case 130: op = rv_op_sh1add_uw; break;
266
@@ -XXX,XX +XXX,XX @@ static uint32_t operand_cimmq(rv_inst inst)
267
((inst << 57) >> 62) << 6;
268
}
269
270
+static uint32_t operand_bs(rv_inst inst)
271
+{
272
+ return (inst << 32) >> 62;
273
+}
274
+
275
+static uint32_t operand_rnum(rv_inst inst)
276
+{
277
+ return (inst << 40) >> 60;
278
+}
279
+
280
/* decode operands */
281
282
static void decode_inst_operands(rv_decode *dec)
283
@@ -XXX,XX +XXX,XX @@ static void decode_inst_operands(rv_decode *dec)
284
dec->rs2 = operand_crs2(inst);
285
dec->imm = operand_cimmsqsp(inst);
286
break;
287
+ case rv_codec_k_bs:
288
+ dec->rs1 = operand_rs1(inst);
289
+ dec->rs2 = operand_rs2(inst);
290
+ dec->bs = operand_bs(inst);
291
+ break;
292
+ case rv_codec_k_rnum:
293
+ dec->rd = operand_rd(inst);
294
+ dec->rs1 = operand_rs1(inst);
295
+ dec->rnum = operand_rnum(inst);
296
+ break;
297
};
298
}
299
300
@@ -XXX,XX +XXX,XX @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
301
case ')':
302
append(buf, ")", buflen);
303
break;
304
+ case 'b':
305
+ snprintf(tmp, sizeof(tmp), "%d", dec->bs);
306
+ append(buf, tmp, buflen);
307
+ break;
308
+ case 'n':
309
+ snprintf(tmp, sizeof(tmp), "%d", dec->rnum);
310
+ append(buf, tmp, buflen);
311
+ break;
312
case '0':
313
append(buf, rv_ireg_name_sym[dec->rd], buflen);
314
break;
315
--
316
2.35.1
diff view generated by jsdifflib
New patch
[PULL 17/25] target/riscv: rvk: expose zbk* and zk* properties
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
4
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Message-Id: <20220423023510.30794-15-liweiwei@iscas.ac.cn>
7
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
---
9
target/riscv/cpu.c | 13 +++++++++++++
10
1 file changed, 13 insertions(+)
11
12
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/riscv/cpu.c
15
+++ b/target/riscv/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
17
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
18
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
19
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
20
+ DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
21
+ DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
22
+ DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
23
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
24
+ DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
25
+ DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
26
+ DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
27
+ DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
28
+ DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
29
+ DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
30
+ DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
31
+ DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
32
+ DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
33
+ DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
34
35
DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
36
DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
37
--
38
2.35.1
diff view generated by jsdifflib
New patch
[PULL 18/25] target/riscv: Fix incorrect PTE merge in walk_pte
1
From: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
1
2
3
Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
4
case, walk_pte will erroneously merge them.
5
6
Enforce the split up, by tracking the virtual base address.
7
8
Let's say we have the mapping:
9
0x81200000 -> 0x89623000 (4K)
10
0x8120f000 -> 0x89624000 (4K)
11
12
Before, walk_pte would have shown:
13
14
vaddr paddr size attr
15
---------------- ---------------- ---------------- -------
16
0000000081200000 0000000089623000 0000000000002000 rwxu-ad
17
18
as it only checks for subsequent paddrs. With this patch, it becomes:
19
20
vaddr paddr size attr
21
---------------- ---------------- ---------------- -------
22
0000000081200000 0000000089623000 0000000000001000 rwxu-ad
23
000000008120f000 0000000089624000 0000000000001000 rwxu-ad
24
25
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
26
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
27
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
28
Message-Id: <20220423215907.673663-1-ralf.ramsauer@oth-regensburg.de>
29
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
30
---
31
target/riscv/monitor.c | 11 +++++++----
32
1 file changed, 7 insertions(+), 4 deletions(-)
33
34
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/monitor.c
37
+++ b/target/riscv/monitor.c
38
@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
39
{
40
hwaddr pte_addr;
41
hwaddr paddr;
42
+ target_ulong last_start = -1;
43
target_ulong pgsize;
44
target_ulong pte;
45
int ptshift;
46
@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
47
* A leaf PTE has been found
48
*
49
* If current PTE's permission bits differ from the last one,
50
- * or current PTE's ppn does not make a contiguous physical
51
- * address block together with the last one, print out the last
52
- * contiguous mapped block details.
53
+ * or the current PTE breaks up a contiguous virtual or
54
+ * physical mapping, address block together with the last one,
55
+ * print out the last contiguous mapped block details.
56
*/
57
if ((*last_attr != attr) ||
58
- (*last_paddr + *last_size != paddr)) {
59
+ (*last_paddr + *last_size != paddr) ||
60
+ (last_start + *last_size != start)) {
61
print_pte(mon, va_bits, *vbase, *pbase,
62
*last_paddr + *last_size - *pbase, *last_attr);
63
64
@@ -XXX,XX +XXX,XX @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
65
*last_attr = attr;
66
}
67
68
+ last_start = start;
69
*last_paddr = paddr;
70
*last_size = pgsize;
71
} else {
72
--
73
2.35.1
diff view generated by jsdifflib
New patch
[PULL 19/25] target/riscv: add scalar crypto related extenstion strings to isa_string
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
1
2
3
- add zbk* and zk* strings to isa_edata_arr
4
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
7
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20220426095204.24142-1-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
target/riscv/cpu.c | 13 +++++++++++++
13
1 file changed, 13 insertions(+)
14
15
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/riscv/cpu.c
18
+++ b/target/riscv/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
20
ISA_EDATA_ENTRY(zba, ext_zba),
21
ISA_EDATA_ENTRY(zbb, ext_zbb),
22
ISA_EDATA_ENTRY(zbc, ext_zbc),
23
+ ISA_EDATA_ENTRY(zbkb, ext_zbkb),
24
+ ISA_EDATA_ENTRY(zbkc, ext_zbkc),
25
+ ISA_EDATA_ENTRY(zbkx, ext_zbkx),
26
ISA_EDATA_ENTRY(zbs, ext_zbs),
27
+ ISA_EDATA_ENTRY(zk, ext_zk),
28
+ ISA_EDATA_ENTRY(zkn, ext_zkn),
29
+ ISA_EDATA_ENTRY(zknd, ext_zknd),
30
+ ISA_EDATA_ENTRY(zkne, ext_zkne),
31
+ ISA_EDATA_ENTRY(zknh, ext_zknh),
32
+ ISA_EDATA_ENTRY(zkr, ext_zkr),
33
+ ISA_EDATA_ENTRY(zks, ext_zks),
34
+ ISA_EDATA_ENTRY(zksed, ext_zksed),
35
+ ISA_EDATA_ENTRY(zksh, ext_zksh),
36
+ ISA_EDATA_ENTRY(zkt, ext_zkt),
37
ISA_EDATA_ENTRY(zve32f, ext_zve32f),
38
ISA_EDATA_ENTRY(zve64f, ext_zve64f),
39
ISA_EDATA_ENTRY(svinval, ext_svinval),
40
--
41
2.35.1
diff view generated by jsdifflib
New patch
[PULL 20/25] hw/riscv: virt: Add a machine done notifier
1
1
From: Alistair Francis <alistair.francis@wdc.com>
2
3
Move the binary and device tree loading code to the machine done
4
notifier. This allows us to prepare for editing the device tree as part
5
of the notifier.
6
7
This is based on similar code in the ARM virt machine.
8
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
11
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
12
Message-Id: <20220427234146.1130752-2-alistair.francis@opensource.wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
include/hw/riscv/virt.h | 1 +
16
hw/riscv/virt.c | 191 +++++++++++++++++++++-------------------
17
2 files changed, 102 insertions(+), 90 deletions(-)
18
19
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/riscv/virt.h
22
+++ b/include/hw/riscv/virt.h
23
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
24
MachineState parent;
25
26
/*< public >*/
27
+ Notifier machine_done;
28
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
29
DeviceState *irqchip[VIRT_SOCKETS_MAX];
30
PFlashCFI01 *flash[2];
31
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/riscv/virt.c
34
+++ b/hw/riscv/virt.c
35
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
36
return aplic_m;
37
}
38
39
+static void virt_machine_done(Notifier *notifier, void *data)
40
+{
41
+ RISCVVirtState *s = container_of(notifier, RISCVVirtState,
42
+ machine_done);
43
+ const MemMapEntry *memmap = virt_memmap;
44
+ MachineState *machine = MACHINE(s);
45
+ target_ulong start_addr = memmap[VIRT_DRAM].base;
46
+ target_ulong firmware_end_addr, kernel_start_addr;
47
+ uint32_t fdt_load_addr;
48
+ uint64_t kernel_entry;
49
+
50
+ /*
51
+ * Only direct boot kernel is currently supported for KVM VM,
52
+ * so the "-bios" parameter is not supported when KVM is enabled.
53
+ */
54
+ if (kvm_enabled()) {
55
+ if (machine->firmware) {
56
+ if (strcmp(machine->firmware, "none")) {
57
+ error_report("Machine mode firmware is not supported in "
58
+ "combination with KVM.");
59
+ exit(1);
60
+ }
61
+ } else {
62
+ machine->firmware = g_strdup("none");
63
+ }
64
+ }
65
+
66
+ if (riscv_is_32bit(&s->soc[0])) {
67
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
68
+ RISCV32_BIOS_BIN, start_addr, NULL);
69
+ } else {
70
+ firmware_end_addr = riscv_find_and_load_firmware(machine,
71
+ RISCV64_BIOS_BIN, start_addr, NULL);
72
+ }
73
+
74
+ if (machine->kernel_filename) {
75
+ kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
76
+ firmware_end_addr);
77
+
78
+ kernel_entry = riscv_load_kernel(machine->kernel_filename,
79
+ kernel_start_addr, NULL);
80
+
81
+ if (machine->initrd_filename) {
82
+ hwaddr start;
83
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
84
+ machine->ram_size, kernel_entry,
85
+ &start);
86
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen",
87
+ "linux,initrd-start", start);
88
+ qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
89
+ end);
90
+ }
91
+ } else {
92
+ /*
93
+ * If dynamic firmware is used, it doesn't know where is the next mode
94
+ * if kernel argument is not set.
95
+ */
96
+ kernel_entry = 0;
97
+ }
98
+
99
+ if (drive_get(IF_PFLASH, 0, 0)) {
100
+ /*
101
+ * Pflash was supplied, let's overwrite the address we jump to after
102
+ * reset to the base of the flash.
103
+ */
104
+ start_addr = virt_memmap[VIRT_FLASH].base;
105
+ }
106
+
107
+ /*
108
+ * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
109
+ * tree cannot be altered and we get FDT_ERR_NOSPACE.
110
+ */
111
+ s->fw_cfg = create_fw_cfg(machine);
112
+ rom_set_fw(s->fw_cfg);
113
+
114
+ /* Compute the fdt load address in dram */
115
+ fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
116
+ machine->ram_size, machine->fdt);
117
+ /* load the reset vector */
118
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
119
+ virt_memmap[VIRT_MROM].base,
120
+ virt_memmap[VIRT_MROM].size, kernel_entry,
121
+ fdt_load_addr, machine->fdt);
122
+
123
+ /*
124
+ * Only direct boot kernel is currently supported for KVM VM,
125
+ * So here setup kernel start address and fdt address.
126
+ * TODO:Support firmware loading and integrate to TCG start
127
+ */
128
+ if (kvm_enabled()) {
129
+ riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
130
+ }
131
+}
132
+
133
static void virt_machine_init(MachineState *machine)
134
{
135
const MemMapEntry *memmap = virt_memmap;
136
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
137
MemoryRegion *system_memory = get_system_memory();
138
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
139
char *soc_name;
140
- target_ulong start_addr = memmap[VIRT_DRAM].base;
141
- target_ulong firmware_end_addr, kernel_start_addr;
142
- uint32_t fdt_load_addr;
143
- uint64_t kernel_entry;
144
DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
145
int i, base_hartid, hart_count;
146
147
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
148
memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
149
machine->ram);
150
151
- /* create device tree */
152
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
153
- riscv_is_32bit(&s->soc[0]));
154
-
155
/* boot rom */
156
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
157
memmap[VIRT_MROM].size, &error_fatal);
158
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
159
mask_rom);
160
161
- /*
162
- * Only direct boot kernel is currently supported for KVM VM,
163
- * so the "-bios" parameter is not supported when KVM is enabled.
164
- */
165
- if (kvm_enabled()) {
166
- if (machine->firmware) {
167
- if (strcmp(machine->firmware, "none")) {
168
- error_report("Machine mode firmware is not supported in "
169
- "combination with KVM.");
170
- exit(1);
171
- }
172
- } else {
173
- machine->firmware = g_strdup("none");
174
- }
175
- }
176
-
177
- if (riscv_is_32bit(&s->soc[0])) {
178
- firmware_end_addr = riscv_find_and_load_firmware(machine,
179
- RISCV32_BIOS_BIN, start_addr, NULL);
180
- } else {
181
- firmware_end_addr = riscv_find_and_load_firmware(machine,
182
- RISCV64_BIOS_BIN, start_addr, NULL);
183
- }
184
-
185
- if (machine->kernel_filename) {
186
- kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
187
- firmware_end_addr);
188
-
189
- kernel_entry = riscv_load_kernel(machine->kernel_filename,
190
- kernel_start_addr, NULL);
191
-
192
- if (machine->initrd_filename) {
193
- hwaddr start;
194
- hwaddr end = riscv_load_initrd(machine->initrd_filename,
195
- machine->ram_size, kernel_entry,
196
- &start);
197
- qemu_fdt_setprop_cell(machine->fdt, "/chosen",
198
- "linux,initrd-start", start);
199
- qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
200
- end);
201
- }
202
- } else {
203
- /*
204
- * If dynamic firmware is used, it doesn't know where is the next mode
205
- * if kernel argument is not set.
206
- */
207
- kernel_entry = 0;
208
- }
209
-
210
- if (drive_get(IF_PFLASH, 0, 0)) {
211
- /*
212
- * Pflash was supplied, let's overwrite the address we jump to after
213
- * reset to the base of the flash.
214
- */
215
- start_addr = virt_memmap[VIRT_FLASH].base;
216
- }
217
-
218
- /*
219
- * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
220
- * tree cannot be altered and we get FDT_ERR_NOSPACE.
221
- */
222
- s->fw_cfg = create_fw_cfg(machine);
223
- rom_set_fw(s->fw_cfg);
224
-
225
- /* Compute the fdt load address in dram */
226
- fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
227
- machine->ram_size, machine->fdt);
228
- /* load the reset vector */
229
- riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
230
- virt_memmap[VIRT_MROM].base,
231
- virt_memmap[VIRT_MROM].size, kernel_entry,
232
- fdt_load_addr, machine->fdt);
233
-
234
- /*
235
- * Only direct boot kernel is currently supported for KVM VM,
236
- * So here setup kernel start address and fdt address.
237
- * TODO:Support firmware loading and integrate to TCG start
238
- */
239
- if (kvm_enabled()) {
240
- riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
241
- }
242
-
243
/* SiFive Test MMIO device */
244
sifive_test_create(memmap[VIRT_TEST].base);
245
246
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
247
drive_get(IF_PFLASH, 0, i));
248
}
249
virt_flash_map(s, system_memory);
250
+
251
+ /* create device tree */
252
+ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
253
+ riscv_is_32bit(&s->soc[0]));
254
+
255
+ s->machine_done.notify = virt_machine_done;
256
+ qemu_add_machine_init_done_notifier(&s->machine_done);
257
}
258
259
static void virt_machine_instance_init(Object *obj)
260
--
261
2.35.1
diff view generated by jsdifflib
New patch
[PULL 21/25] hw/core: Move the ARM sysbus-fdt to core
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
The ARM virt machine currently uses sysbus-fdt to create device tree
4
entries for dynamically created MMIO devices.
5
6
The RISC-V virt machine can also benefit from this, so move the code to
7
the core directory.
8
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
11
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
12
Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
include/hw/{arm => core}/sysbus-fdt.h | 0
16
hw/arm/virt.c | 2 +-
17
hw/arm/xlnx-versal-virt.c | 1 -
18
hw/{arm => core}/sysbus-fdt.c | 2 +-
19
hw/arm/meson.build | 1 -
20
hw/core/meson.build | 1 +
21
6 files changed, 3 insertions(+), 4 deletions(-)
22
rename include/hw/{arm => core}/sysbus-fdt.h (100%)
23
rename hw/{arm => core}/sysbus-fdt.c (99%)
24
25
diff --git a/include/hw/arm/sysbus-fdt.h b/include/hw/core/sysbus-fdt.h
26
similarity index 100%
27
rename from include/hw/arm/sysbus-fdt.h
28
rename to include/hw/core/sysbus-fdt.h
29
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/virt.c
32
+++ b/hw/arm/virt.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qemu/module.h"
35
#include "hw/pci-host/gpex.h"
36
#include "hw/virtio/virtio-pci.h"
37
-#include "hw/arm/sysbus-fdt.h"
38
+#include "hw/core/sysbus-fdt.h"
39
#include "hw/platform-bus.h"
40
#include "hw/qdev-properties.h"
41
#include "hw/arm/fdt.h"
42
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/xlnx-versal-virt.c
45
+++ b/hw/arm/xlnx-versal-virt.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "sysemu/device_tree.h"
48
#include "hw/boards.h"
49
#include "hw/sysbus.h"
50
-#include "hw/arm/sysbus-fdt.h"
51
#include "hw/arm/fdt.h"
52
#include "cpu.h"
53
#include "hw/qdev-properties.h"
54
diff --git a/hw/arm/sysbus-fdt.c b/hw/core/sysbus-fdt.c
55
similarity index 99%
56
rename from hw/arm/sysbus-fdt.c
57
rename to hw/core/sysbus-fdt.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/sysbus-fdt.c
60
+++ b/hw/core/sysbus-fdt.c
61
@@ -XXX,XX +XXX,XX @@
62
#ifdef CONFIG_LINUX
63
#include <linux/vfio.h>
64
#endif
65
-#include "hw/arm/sysbus-fdt.h"
66
+#include "hw/core/sysbus-fdt.h"
67
#include "qemu/error-report.h"
68
#include "sysemu/device_tree.h"
69
#include "sysemu/tpm.h"
70
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/meson.build
73
+++ b/hw/arm/meson.build
74
@@ -XXX,XX +XXX,XX @@
75
arm_ss = ss.source_set()
76
arm_ss.add(files('boot.c'), fdt)
77
-arm_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
78
arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
79
arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
80
arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
81
diff --git a/hw/core/meson.build b/hw/core/meson.build
82
index XXXXXXX..XXXXXXX 100644
83
--- a/hw/core/meson.build
84
+++ b/hw/core/meson.build
85
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PTIMER', if_true: files('ptimer.c'))
86
softmmu_ss.add(when: 'CONFIG_REGISTER', if_true: files('register.c'))
87
softmmu_ss.add(when: 'CONFIG_SPLIT_IRQ', if_true: files('split-irq.c'))
88
softmmu_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c'))
89
+softmmu_ss.add(when: 'CONFIG_PLATFORM_BUS', if_true: files('sysbus-fdt.c'))
90
91
softmmu_ss.add(files(
92
'cpu-sysemu.c',
93
--
94
2.35.1
diff view generated by jsdifflib
New patch
[PULL 22/25] hw/riscv: virt: Create a platform bus
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
Create a platform bus to allow dynamic devices to be connected. This is
4
based on the ARM implementation.
5
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Message-Id: <20220427234146.1130752-4-alistair.francis@opensource.wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
include/hw/riscv/virt.h | 7 ++++-
13
hw/riscv/virt.c | 68 +++++++++++++++++++++++++++++------------
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 56 insertions(+), 20 deletions(-)
16
17
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/virt.h
20
+++ b/include/hw/riscv/virt.h
21
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
22
23
/*< public >*/
24
Notifier machine_done;
25
+ DeviceState *platform_bus_dev;
26
RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
27
DeviceState *irqchip[VIRT_SOCKETS_MAX];
28
PFlashCFI01 *flash[2];
29
@@ -XXX,XX +XXX,XX @@ enum {
30
VIRT_DRAM,
31
VIRT_PCIE_MMIO,
32
VIRT_PCIE_PIO,
33
+ VIRT_PLATFORM_BUS,
34
VIRT_PCIE_ECAM
35
};
36
37
@@ -XXX,XX +XXX,XX @@ enum {
38
VIRTIO_IRQ = 1, /* 1 to 8 */
39
VIRTIO_COUNT = 8,
40
PCIE_IRQ = 0x20, /* 32 to 35 */
41
- VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
42
+ VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
43
+ VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
44
};
45
46
+#define VIRT_PLATFORM_BUS_NUM_IRQS 32
47
+
48
#define VIRT_IRQCHIP_IPI_MSI 1
49
#define VIRT_IRQCHIP_NUM_MSIS 255
50
#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
51
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/riscv/virt.c
54
+++ b/hw/riscv/virt.c
55
@@ -XXX,XX +XXX,XX @@
56
#include "hw/intc/riscv_imsic.h"
57
#include "hw/intc/sifive_plic.h"
58
#include "hw/misc/sifive_test.h"
59
+#include "hw/platform-bus.h"
60
#include "chardev/char.h"
61
#include "sysemu/device_tree.h"
62
#include "sysemu/sysemu.h"
63
@@ -XXX,XX +XXX,XX @@
64
#endif
65
66
static const MemMapEntry virt_memmap[] = {
67
- [VIRT_DEBUG] = { 0x0, 0x100 },
68
- [VIRT_MROM] = { 0x1000, 0xf000 },
69
- [VIRT_TEST] = { 0x100000, 0x1000 },
70
- [VIRT_RTC] = { 0x101000, 0x1000 },
71
- [VIRT_CLINT] = { 0x2000000, 0x10000 },
72
- [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
73
- [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
74
- [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
75
- [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
76
- [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
77
- [VIRT_UART0] = { 0x10000000, 0x100 },
78
- [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
79
- [VIRT_FW_CFG] = { 0x10100000, 0x18 },
80
- [VIRT_FLASH] = { 0x20000000, 0x4000000 },
81
- [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
82
- [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
83
- [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
84
- [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
85
- [VIRT_DRAM] = { 0x80000000, 0x0 },
86
+ [VIRT_DEBUG] = { 0x0, 0x100 },
87
+ [VIRT_MROM] = { 0x1000, 0xf000 },
88
+ [VIRT_TEST] = { 0x100000, 0x1000 },
89
+ [VIRT_RTC] = { 0x101000, 0x1000 },
90
+ [VIRT_CLINT] = { 0x2000000, 0x10000 },
91
+ [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
92
+ [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
93
+ [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 },
94
+ [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
95
+ [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
96
+ [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
97
+ [VIRT_UART0] = { 0x10000000, 0x100 },
98
+ [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
99
+ [VIRT_FW_CFG] = { 0x10100000, 0x18 },
100
+ [VIRT_FLASH] = { 0x20000000, 0x4000000 },
101
+ [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
102
+ [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
103
+ [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
104
+ [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
105
+ [VIRT_DRAM] = { 0x80000000, 0x0 },
106
};
107
108
/* PCIe high mmio is fixed for RV32 */
109
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
110
return aplic_m;
111
}
112
113
+static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip)
114
+{
115
+ DeviceState *dev;
116
+ SysBusDevice *sysbus;
117
+ const MemMapEntry *memmap = virt_memmap;
118
+ int i;
119
+ MemoryRegion *sysmem = get_system_memory();
120
+
121
+ dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
122
+ dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
123
+ qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS);
124
+ qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size);
125
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
126
+ s->platform_bus_dev = dev;
127
+
128
+ sysbus = SYS_BUS_DEVICE(dev);
129
+ for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) {
130
+ int irq = VIRT_PLATFORM_BUS_IRQ + i;
131
+ sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq));
132
+ }
133
+
134
+ memory_region_add_subregion(sysmem,
135
+ memmap[VIRT_PLATFORM_BUS].base,
136
+ sysbus_mmio_get_region(sysbus, 0));
137
+}
138
+
139
static void virt_machine_done(Notifier *notifier, void *data)
140
{
141
RISCVVirtState *s = container_of(notifier, RISCVVirtState,
142
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
143
memmap[VIRT_PCIE_PIO].base,
144
DEVICE(pcie_irqchip));
145
146
+ create_platform_bus(s, DEVICE(mmio_irqchip));
147
+
148
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
149
0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
150
serial_hd(0), DEVICE_LITTLE_ENDIAN);
151
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/riscv/Kconfig
154
+++ b/hw/riscv/Kconfig
155
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
156
select SIFIVE_TEST
157
select VIRTIO_MMIO
158
select FW_CFG_DMA
159
+ select PLATFORM_BUS
160
161
config SIFIVE_E
162
bool
163
--
164
2.35.1
diff view generated by jsdifflib
New patch
[PULL 23/25] hw/riscv: virt: Add support for generating platform FDT entries
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
Similar to the ARM virt machine add support for adding device tree
4
entries for dynamically created devices.
5
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
8
Message-Id: <20220427234146.1130752-5-alistair.francis@opensource.wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
11
hw/riscv/virt.c | 19 +++++++++++++++++++
12
1 file changed, 19 insertions(+)
13
14
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/riscv/virt.c
17
+++ b/hw/riscv/virt.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/qdev-properties.h"
20
#include "hw/char/serial.h"
21
#include "target/riscv/cpu.h"
22
+#include "hw/core/sysbus-fdt.h"
23
#include "hw/riscv/riscv_hart.h"
24
#include "hw/riscv/virt.h"
25
#include "hw/riscv/boot.h"
26
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_plic(RISCVVirtState *s,
27
riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
28
qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
29
plic_phandles[socket]);
30
+
31
+ platform_bus_add_all_fdt_nodes(mc->fdt, plic_name,
32
+ memmap[VIRT_PLATFORM_BUS].base,
33
+ memmap[VIRT_PLATFORM_BUS].size,
34
+ VIRT_PLATFORM_BUS_IRQ);
35
+
36
g_free(plic_name);
37
38
g_free(plic_cells);
39
@@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
40
IMSIC_MMIO_GROUP_MIN_SHIFT);
41
}
42
qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
43
+
44
+ platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name,
45
+ memmap[VIRT_PLATFORM_BUS].base,
46
+ memmap[VIRT_PLATFORM_BUS].size,
47
+ VIRT_PLATFORM_BUS_IRQ);
48
+
49
g_free(imsic_name);
50
51
/* S-level IMSIC node */
52
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
53
VIRT_IRQCHIP_NUM_SOURCES);
54
riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
55
qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
56
+
57
+ platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name,
58
+ memmap[VIRT_PLATFORM_BUS].base,
59
+ memmap[VIRT_PLATFORM_BUS].size,
60
+ VIRT_PLATFORM_BUS_IRQ);
61
+
62
g_free(aplic_name);
63
64
g_free(aplic_cells);
65
--
66
2.35.1
diff view generated by jsdifflib
[PULL 2/2] intc/ibex_plic: Ensure we don't loose interrupts
[PULL 24/25] hw/riscv: virt: Add device plug support
1
If an interrupt occurs between when we claim and complete an interrupt
1
From: Alistair Francis <alistair.francis@wdc.com>
2
we currently drop the interrupt in ibex_plic_irqs_set_pending(). This
3
somewhat matches hardware that also ignore the interrupt between the
4
claim and complete process.
5
2
6
In the case of hardware though the physical interrupt line will still
3
Add support for plugging in devices, this was tested with the TPM
7
be asserted after we have completed the interrupt. This means we will
4
device.
8
still act on the interrupt after the complete process. In QEMU we don't
9
and instead we drop the interrupt as it is never recorded.
10
11
This patch changed the behaviour of the Ibex PLIC so that we save all
12
interrupts that occur while we are between claiming and completing an
13
interrupt so that we can act on them after the completition process.
14
15
This fixes interrupts being dropped when running Tock on OpenTitain in
16
QEMU.
17
5
18
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Message-id: e7bcf98c6925b1e6e7828e7c3f85293a09a65b12.1605136387.git.alistair.francis@wdc.com
7
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
8
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9
Message-Id: <20220427234146.1130752-6-alistair.francis@opensource.wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
---
11
---
21
include/hw/intc/ibex_plic.h | 1 +
12
hw/riscv/virt.c | 35 +++++++++++++++++++++++++++++++++++
22
hw/intc/ibex_plic.c | 17 ++++++++++++++++-
13
1 file changed, 35 insertions(+)
23
2 files changed, 17 insertions(+), 1 deletion(-)
24
14
25
diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h
15
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
26
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/intc/ibex_plic.h
17
--- a/hw/riscv/virt.c
28
+++ b/include/hw/intc/ibex_plic.h
18
+++ b/hw/riscv/virt.c
29
@@ -XXX,XX +XXX,XX @@ struct IbexPlicState {
19
@@ -XXX,XX +XXX,XX @@ static void virt_set_aclint(Object *obj, bool value, Error **errp)
30
MemoryRegion mmio;
20
s->have_aclint = value;
31
21
}
32
uint32_t *pending;
22
33
+ uint32_t *hidden_pending;
23
+static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
34
uint32_t *claimed;
24
+ DeviceState *dev)
35
uint32_t *source;
25
+{
36
uint32_t *priority;
26
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
37
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/intc/ibex_plic.c
40
+++ b/hw/intc/ibex_plic.c
41
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
42
* The interrupt has been claimed, but not completed.
43
* The pending bit can't be set.
44
*/
45
+ s->hidden_pending[pending_num] |= level << (irq % 32);
46
return;
47
}
48
49
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_write(void *opaque, hwaddr addr,
50
s->claim = 0;
51
}
52
if (s->claimed[value / 32] & 1 << (value % 32)) {
53
+ int pending_num = value / 32;
54
+
27
+
55
/* This value was already claimed, clear it. */
28
+ if (device_is_dynamic_sysbus(mc, dev)) {
56
- s->claimed[value / 32] &= ~(1 << (value % 32));
29
+ return HOTPLUG_HANDLER(machine);
57
+ s->claimed[pending_num] &= ~(1 << (value % 32));
30
+ }
31
+ return NULL;
32
+}
58
+
33
+
59
+ if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
34
+static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
60
+ /*
35
+ DeviceState *dev, Error **errp)
61
+ * If the bit in hidden_pending is set then that means we
36
+{
62
+ * received an interrupt between claiming and completing
37
+ RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev);
63
+ * the interrupt that hasn't since been de-asserted.
38
+
64
+ * On hardware this would trigger an interrupt, so let's
39
+ if (s->platform_bus_dev) {
65
+ * trigger one here as well.
40
+ MachineClass *mc = MACHINE_GET_CLASS(s);
66
+ */
41
+
67
+ s->pending[pending_num] |= 1 << (value % 32);
42
+ if (device_is_dynamic_sysbus(mc, dev)) {
68
+ }
43
+ platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev),
69
}
44
+ SYS_BUS_DEVICE(dev));
70
}
45
+ }
71
46
+ }
72
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_realize(DeviceState *dev, Error **errp)
47
+}
73
int i;
48
+
74
49
static void virt_machine_class_init(ObjectClass *oc, void *data)
75
s->pending = g_new0(uint32_t, s->pending_num);
50
{
76
+ s->hidden_pending = g_new0(uint32_t, s->pending_num);
51
char str[128];
77
s->claimed = g_new0(uint32_t, s->pending_num);
52
MachineClass *mc = MACHINE_CLASS(oc);
78
s->source = g_new0(uint32_t, s->source_num);
53
+ HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
79
s->priority = g_new0(uint32_t, s->priority_num);
54
55
mc->desc = "RISC-V VirtIO board";
56
mc->init = virt_machine_init;
57
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
58
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
59
mc->numa_mem_supported = true;
60
mc->default_ram_id = "riscv_virt_board.ram";
61
+ assert(!mc->get_hotplug_handler);
62
+ mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
63
+
64
+ hc->plug = virt_machine_device_plug_cb;
65
66
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
67
68
@@ -XXX,XX +XXX,XX @@ static const TypeInfo virt_machine_typeinfo = {
69
.class_init = virt_machine_class_init,
70
.instance_init = virt_machine_instance_init,
71
.instance_size = sizeof(RISCVVirtState),
72
+ .interfaces = (InterfaceInfo[]) {
73
+ { TYPE_HOTPLUG_HANDLER },
74
+ { }
75
+ },
76
};
77
78
static void virt_machine_init_register_types(void)
80
--
79
--
81
2.29.2
80
2.35.1
82
83
diff view generated by jsdifflib
[PULL 1/2] intc/ibex_plic: Fix some typos in the comments
[PULL 25/25] hw/riscv: Enable TPM backends
1
From: Alistair Francis <alistair.francis@wdc.com>
2
3
Imply the TPM sysbus devices. This allows users to add TPM devices to
4
the RISC-V virt board.
5
6
This was tested by first creating an emulated TPM device:
7
8
swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
9
--ctrl type=unixio,path=swtpm-sock
10
11
Then launching QEMU with:
12
13
-chardev socket,id=chrtpm,path=swtpm-sock \
14
-tpmdev emulator,id=tpm0,chardev=chrtpm \
15
-device tpm-tis-device,tpmdev=tpm0
16
17
The TPM device can be seen in the memory tree and the generated device
18
tree.
19
20
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942
1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2
Message-id: 22d2fb0d7af5ca316c67ac909926368d1bcb7cf5.1605136387.git.alistair.francis@wdc.com
22
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
23
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
24
Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com>
25
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3
---
26
---
4
hw/intc/ibex_plic.c | 4 ++--
27
docs/system/riscv/virt.rst | 20 ++++++++++++++++++++
5
1 file changed, 2 insertions(+), 2 deletions(-)
28
hw/riscv/virt.c | 4 ++++
29
hw/riscv/Kconfig | 1 +
30
3 files changed, 25 insertions(+)
6
31
7
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
32
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
8
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
9
--- a/hw/intc/ibex_plic.c
34
--- a/docs/system/riscv/virt.rst
10
+++ b/hw/intc/ibex_plic.c
35
+++ b/docs/system/riscv/virt.rst
11
@@ -XXX,XX +XXX,XX @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
36
@@ -XXX,XX +XXX,XX @@ The minimal QEMU commands to run U-Boot SPL are:
12
37
To test 32-bit U-Boot images, switch to use qemu-riscv32_smode_defconfig and
13
if (s->claimed[pending_num] & 1 << (irq % 32)) {
38
riscv32_spl_defconfig builds, and replace ``qemu-system-riscv64`` with
14
/*
39
``qemu-system-riscv32`` in the command lines above to boot the 32-bit U-Boot.
15
- * The interrupt has been claimed, but not compelted.
40
+
16
+ * The interrupt has been claimed, but not completed.
41
+Enabling TPM
17
* The pending bit can't be set.
42
+------------
18
*/
43
+
19
return;
44
+A TPM device can be connected to the virt board by following the steps below.
20
@@ -XXX,XX +XXX,XX @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
45
+
21
int pending_num = s->claim / 32;
46
+First launch the TPM emulator
22
s->pending[pending_num] &= ~(1 << (s->claim % 32));
47
+
23
48
+ swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
24
- /* Set the interrupt as claimed, but not compelted */
49
+ --ctrl type=unixio,path=swtpm-sock
25
+ /* Set the interrupt as claimed, but not completed */
50
+
26
s->claimed[pending_num] |= 1 << (s->claim % 32);
51
+Then launch QEMU with:
27
52
+
28
/* Return the current claimed interrupt */
53
+ ...
54
+ -chardev socket,id=chrtpm,path=swtpm-sock \
55
+ -tpmdev emulator,id=tpm0,chardev=chrtpm \
56
+ -device tpm-tis-device,tpmdev=tpm0
57
+
58
+The TPM device can be seen in the memory tree and the generated device
59
+tree and should be accessible from the guest software.
60
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/riscv/virt.c
63
+++ b/hw/riscv/virt.c
64
@@ -XXX,XX +XXX,XX @@
65
#include "sysemu/device_tree.h"
66
#include "sysemu/sysemu.h"
67
#include "sysemu/kvm.h"
68
+#include "sysemu/tpm.h"
69
#include "hw/pci/pci.h"
70
#include "hw/pci-host/gpex.h"
71
#include "hw/display/ramfb.h"
72
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
73
hc->plug = virt_machine_device_plug_cb;
74
75
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
76
+#ifdef CONFIG_TPM
77
+ machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
78
+#endif
79
80
object_class_property_add_bool(oc, "aclint", virt_get_aclint,
81
virt_set_aclint);
82
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/riscv/Kconfig
85
+++ b/hw/riscv/Kconfig
86
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
87
imply PCI_DEVICES
88
imply VIRTIO_VGA
89
imply TEST_DEVICES
90
+ imply TPM_TIS_SYSBUS
91
select RISCV_NUMA
92
select GOLDFISH_RTC
93
select MSI_NONBROKEN
29
--
94
--
30
2.29.2
95
2.35.1
31
32
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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