[PULL 00/16] target-arm queue
[PULL 00/21] target-arm queue
1
Patches for rc1: nothing major, just some minor bugfixes and
1
The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:
2
code cleanups.
3
2
4
-- PMM
3
Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)
5
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
7
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
9
4
10
are available in the Git repository at:
5
are available in the Git repository at:
11
6
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306
13
8
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
9
for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:
15
10
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
11
hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
15
* allwinner-h3: Fix I2C controller model for Sun6i SoCs
21
* Minor coding style fixes
16
* allwinner-h3: Add missing i2c controllers
22
* docs: add some notes on the sbsa-ref machine
17
* Expose M-profile system registers to gdbstub
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
18
* Expose pauth information to gdbstub
24
* target/arm: Fix neon VTBL/VTBX for len > 1
19
* Support direct boot for Linux/arm64 EFI zboot images
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
20
* Fix incorrect stage 2 MMU setup validation
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
30
* hw/arm/nseries: Check return value from load_image_targphys()
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
33
21
34
----------------------------------------------------------------
22
----------------------------------------------------------------
35
Alex Bennée (1):
23
Ard Biesheuvel (1):
36
docs: add some notes on the sbsa-ref machine
24
hw: arm: Support direct boot for Linux/arm64 EFI zboot images
37
25
38
AlexChen (1):
26
David Reiss (2):
39
ssi: Fix bad printf format specifiers
27
target/arm: Export arm_v7m_mrs_control
28
target/arm: Export arm_v7m_get_sp_ptr
40
29
41
Andrew Jones (1):
30
Richard Henderson (16):
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
31
target/arm: Normalize aarch64 gdbstub get/set function names
32
target/arm: Unexport arm_gen_dynamic_sysreg_xml
33
target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
34
target/arm: Split out output_vector_union_type
35
target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
36
target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
37
target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
38
target/arm: Add name argument to output_vector_union_type
39
target/arm: Simplify iteration over bit widths
40
target/arm: Create pauth_ptr_mask
41
target/arm: Implement gdbstub pauth extension
42
target/arm: Implement gdbstub m-profile systemreg and secext
43
target/arm: Handle m-profile in arm_is_secure
44
target/arm: Stub arm_hcr_el2_eff for m-profile
45
target/arm: Diagnose incorrect usage of arm_is_secure subroutines
46
target/arm: Rewrite check_s2_mmu_setup
43
47
44
Havard Skinnemoen (1):
48
qianfan Zhao (2):
45
tests/qtest/npcm7xx_rng-test: count runs properly
49
hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
50
hw: arm: allwinner-h3: Fix and complete H3 i2c devices
46
51
47
Peter Maydell (2):
52
configs/targets/aarch64-linux-user.mak | 2 +-
48
hw/arm/nseries: Check return value from load_image_targphys()
53
configs/targets/aarch64-softmmu.mak | 2 +-
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
54
configs/targets/aarch64_be-linux-user.mak | 2 +-
50
55
include/hw/arm/allwinner-h3.h | 6 +
51
Philippe Mathieu-Daudé (6):
56
include/hw/i2c/allwinner-i2c.h | 6 +
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
57
include/hw/loader.h | 19 ++
53
hw/arm/armsse: Correct expansion MPC interrupt lines
58
target/arm/cpu.h | 17 +-
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
59
target/arm/internals.h | 34 +++-
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
60
hw/arm/allwinner-h3.c | 29 +++-
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
61
hw/arm/boot.c | 6 +
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
62
hw/core/loader.c | 91 ++++++++++
58
63
hw/i2c/allwinner-i2c.c | 26 ++-
59
Richard Henderson (1):
64
target/arm/gdbstub.c | 278 ++++++++++++++++++------------
60
target/arm: Fix neon VTBL/VTBX for len > 1
65
target/arm/gdbstub64.c | 175 ++++++++++++++++++-
61
66
target/arm/helper.c | 3 +
62
Xinhao Zhang (3):
67
target/arm/ptw.c | 173 +++++++++++--------
63
target/arm: add spaces around operator
68
target/arm/tcg/m_helper.c | 90 +++++-----
64
target/arm: Don't use '#' flag of printf format
69
target/arm/tcg/pauth_helper.c | 26 ++-
65
target/arm: add space before the open parenthesis '('
70
gdb-xml/aarch64-pauth.xml | 15 ++
66
71
19 files changed, 742 insertions(+), 258 deletions(-)
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
72
create mode 100644 gdb-xml/aarch64-pauth.xml
68
docs/system/target-arm.rst | 1 +
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
70
target/arm/helper.h | 2 +-
71
hw/arm/armsse.c | 3 +-
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
73
hw/arm/nseries.c | 26 ++++++++----------
74
hw/arm/stm32f205_soc.c | 1 -
75
hw/misc/stm32f2xx_syscfg.c | 2 --
76
hw/ssi/imx_spi.c | 2 +-
77
hw/ssi/xilinx_spi.c | 2 +-
78
target/arm/arch_dump.c | 8 +++---
79
target/arm/arm-semi.c | 8 +++---
80
target/arm/helper.c | 2 +-
81
target/arm/op_helper.c | 23 +++++++++-------
82
target/arm/translate-a64.c | 4 +--
83
target/arm/translate.c | 2 +-
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
85
hw/arm/Kconfig | 3 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
87
20 files changed, 123 insertions(+), 98 deletions(-)
88
create mode 100644 docs/system/arm/sbsa.rst
89
diff view generated by jsdifflib
[PULL 15/16] tests/qtest/npcm7xx_rng-test: count runs properly
[PULL 01/21] target/arm: Normalize aarch64 gdbstub get/set function names
1
From: Havard Skinnemoen <hskinnemoen@google.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
3
Make the form of the function names between fp and sve the same:
4
plus one. Currently, it's counting the number of times these transitions
4
- arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
5
do _not_ happen, plus one.
5
- aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.
6
6
7
Source:
7
Reviewed-by: Fabiano Rosas <farosas@suse.de>
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
section 2.3.4 point (3).
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
10
Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
13
target/arm/internals.h | 8 ++++----
17
1 file changed, 1 insertion(+), 1 deletion(-)
14
target/arm/gdbstub.c | 9 +++++----
15
target/arm/gdbstub64.c | 8 ++++----
16
3 files changed, 13 insertions(+), 12 deletions(-)
18
17
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
21
--- a/tests/qtest/npcm7xx_rng-test.c
20
--- a/target/arm/internals.h
22
+++ b/tests/qtest/npcm7xx_rng-test.c
21
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
22
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
24
pi = (double)nr_ones / nr_bits;
23
}
25
24
26
for (k = 0; k < nr_bits - 1; k++) {
25
#ifdef TARGET_AARCH64
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
26
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
27
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
28
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
29
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
30
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
31
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
32
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
33
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
34
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
35
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
36
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
37
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/gdbstub.c
40
+++ b/target/arm/gdbstub.c
41
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
42
*/
43
#ifdef TARGET_AARCH64
44
if (isar_feature_aa64_sve(&cpu->isar)) {
45
- gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
46
- arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
47
+ int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
48
+ gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
49
+ aarch64_gdb_set_sve_reg, nreg,
50
"sve-registers.xml", 0);
51
} else {
52
- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
53
- aarch64_fpu_gdb_set_reg,
54
+ gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
55
+ aarch64_gdb_set_fpu_reg,
56
34, "aarch64-fpu.xml", 0);
57
}
58
#endif
59
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/gdbstub64.c
62
+++ b/target/arm/gdbstub64.c
63
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
64
return 0;
65
}
66
67
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
68
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
69
{
70
switch (reg) {
71
case 0 ... 31:
72
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
29
}
73
}
30
vn_obs += 1;
74
}
75
76
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
77
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
78
{
79
switch (reg) {
80
case 0 ... 31:
81
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
82
}
83
}
84
85
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
86
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
87
{
88
ARMCPU *cpu = env_archcpu(env);
89
90
@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
91
return 0;
92
}
93
94
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
95
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
96
{
97
ARMCPU *cpu = env_archcpu(env);
31
98
32
--
99
--
33
2.20.1
100
2.34.1
34
101
35
102
diff view generated by jsdifflib
[PULL 02/16] ssi: Fix bad printf format specifiers
[PULL 02/21] target/arm: Unexport arm_gen_dynamic_sysreg_xml
1
From: AlexChen <alex.chen@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We should use printf format specifier "%u" instead of "%d" for
3
This function is not used outside gdbstub.c.
4
argument of type "unsigned int".
5
4
6
Reported-by: Euler Robot <euler.robot@huawei.com>
5
Reviewed-by: Fabiano Rosas <farosas@suse.de>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 5FA280F5.8060902@huawei.com
8
Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/ssi/imx_spi.c | 2 +-
11
target/arm/cpu.h | 1 -
13
hw/ssi/xilinx_spi.c | 2 +-
12
target/arm/gdbstub.c | 2 +-
14
2 files changed, 2 insertions(+), 2 deletions(-)
13
2 files changed, 1 insertion(+), 2 deletions(-)
15
14
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/imx_spi.c
17
--- a/target/arm/cpu.h
19
+++ b/hw/ssi/imx_spi.c
18
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
19
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
21
case ECSPI_MSGDATA:
20
* Helpers to dynamically generates XML descriptions of the sysregs
22
return "ECSPI_MSGDATA";
21
* and SVE registers. Returns the number of registers in each set.
23
default:
22
*/
24
- sprintf(unknown, "%d ?", reg);
23
-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
25
+ sprintf(unknown, "%u ?", reg);
24
int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
26
return unknown;
25
26
/* Returns the dynamically generated XML for the gdb stub.
27
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/gdbstub.c
30
+++ b/target/arm/gdbstub.c
31
@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
27
}
32
}
28
}
33
}
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
34
30
index XXXXXXX..XXXXXXX 100644
35
-int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
31
--- a/hw/ssi/xilinx_spi.c
36
+static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
32
+++ b/hw/ssi/xilinx_spi.c
37
{
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
38
ARMCPU *cpu = ARM_CPU(cs);
34
irq chain unless things really changed. */
39
GString *s = g_string_new(NULL);
35
if (pending != s->irqline) {
36
s->irqline = pending;
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
40
qemu_set_irq(s->irq, pending);
41
}
42
--
40
--
43
2.20.1
41
2.34.1
44
42
45
43
diff view generated by jsdifflib
[PULL 08/16] target/arm: Fix neon VTBL/VTBX for len > 1
[PULL 03/21] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The helper function did not get updated when we reorganized
3
The function is only used for aarch64, so move it to the
4
the vector register file for SVE. Since then, the neon dregs
4
file that has the other aarch64 gdbstub stuff. Move the
5
are non-sequential and cannot be simply indexed.
5
declaration to internals.h.
6
6
7
At the same time, make the helper function operate on 64-bit
7
Reviewed-by: Fabiano Rosas <farosas@suse.de>
8
quantities so that we do not have to call it twice.
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
10
Fixes: c39c2b9043e
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
10
Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
12
---
18
target/arm/helper.h | 2 +-
13
target/arm/cpu.h | 6 ---
19
target/arm/op_helper.c | 23 +++++++++--------
14
target/arm/internals.h | 1 +
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
15
target/arm/gdbstub.c | 120 -----------------------------------------
21
3 files changed, 29 insertions(+), 40 deletions(-)
16
target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
22
17
4 files changed, 119 insertions(+), 126 deletions(-)
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper.h
21
--- a/target/arm/cpu.h
26
+++ b/target/arm/helper.h
22
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
23
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
24
int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
25
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
26
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
27
-/*
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
28
- * Helpers to dynamically generates XML descriptions of the sysregs
33
29
- * and SVE registers. Returns the number of registers in each set.
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
30
- */
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
31
-int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
32
-
33
/* Returns the dynamically generated XML for the gdb stub.
34
* Returns a pointer to the XML contents for the specified XML file or NULL
35
* if the XML name doesn't match the predefined one.
36
diff --git a/target/arm/internals.h b/target/arm/internals.h
37
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/op_helper.c
38
--- a/target/arm/internals.h
39
+++ b/target/arm/op_helper.c
39
+++ b/target/arm/internals.h
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
40
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
41
cpu_loop_exit_restore(cs, ra);
42
}
41
}
43
42
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
43
#ifdef TARGET_AARCH64
45
- uint32_t maxindex)
44
+int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
45
int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
47
+ uint64_t ireg, uint64_t def)
46
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
47
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
48
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/gdbstub.c
51
+++ b/target/arm/gdbstub.c
52
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
53
return cpu->dyn_sysreg_xml.num;
54
}
55
56
-struct TypeSize {
57
- const char *gdb_type;
58
- int size;
59
- const char sz, suffix;
60
-};
61
-
62
-static const struct TypeSize vec_lanes[] = {
63
- /* quads */
64
- { "uint128", 128, 'q', 'u' },
65
- { "int128", 128, 'q', 's' },
66
- /* 64 bit */
67
- { "ieee_double", 64, 'd', 'f' },
68
- { "uint64", 64, 'd', 'u' },
69
- { "int64", 64, 'd', 's' },
70
- /* 32 bit */
71
- { "ieee_single", 32, 's', 'f' },
72
- { "uint32", 32, 's', 'u' },
73
- { "int32", 32, 's', 's' },
74
- /* 16 bit */
75
- { "ieee_half", 16, 'h', 'f' },
76
- { "uint16", 16, 'h', 'u' },
77
- { "int16", 16, 'h', 's' },
78
- /* bytes */
79
- { "uint8", 8, 'b', 'u' },
80
- { "int8", 8, 'b', 's' },
81
-};
82
-
83
-
84
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
85
-{
86
- ARMCPU *cpu = ARM_CPU(cs);
87
- GString *s = g_string_new(NULL);
88
- DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
89
- g_autoptr(GString) ts = g_string_new("");
90
- int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
91
- info->num = 0;
92
- g_string_printf(s, "<?xml version=\"1.0\"?>");
93
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
94
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
95
-
96
- /* First define types and totals in a whole VL */
97
- for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
98
- int count = reg_width / vec_lanes[i].size;
99
- g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
100
- g_string_append_printf(s,
101
- "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
102
- ts->str, vec_lanes[i].gdb_type, count);
103
- }
104
- /*
105
- * Now define a union for each size group containing unsigned and
106
- * signed and potentially float versions of each size from 128 to
107
- * 8 bits.
108
- */
109
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
110
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
111
- g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
112
- for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
113
- if (vec_lanes[j].size == bits) {
114
- g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
115
- vec_lanes[j].suffix,
116
- vec_lanes[j].sz, vec_lanes[j].suffix);
117
- }
118
- }
119
- g_string_append(s, "</union>");
120
- }
121
- /* And now the final union of unions */
122
- g_string_append(s, "<union id=\"svev\">");
123
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
124
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
125
- g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
126
- suf[i], suf[i]);
127
- }
128
- g_string_append(s, "</union>");
129
-
130
- /* Finally the sve prefix type */
131
- g_string_append_printf(s,
132
- "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
133
- reg_width / 8);
134
-
135
- /* Then define each register in parts for each vq */
136
- for (i = 0; i < 32; i++) {
137
- g_string_append_printf(s,
138
- "<reg name=\"z%d\" bitsize=\"%d\""
139
- " regnum=\"%d\" type=\"svev\"/>",
140
- i, reg_width, base_reg++);
141
- info->num++;
142
- }
143
- /* fpscr & status registers */
144
- g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
145
- " regnum=\"%d\" group=\"float\""
146
- " type=\"int\"/>", base_reg++);
147
- g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
148
- " regnum=\"%d\" group=\"float\""
149
- " type=\"int\"/>", base_reg++);
150
- info->num += 2;
151
-
152
- for (i = 0; i < 16; i++) {
153
- g_string_append_printf(s,
154
- "<reg name=\"p%d\" bitsize=\"%d\""
155
- " regnum=\"%d\" type=\"svep\"/>",
156
- i, cpu->sve_max_vq * 16, base_reg++);
157
- info->num++;
158
- }
159
- g_string_append_printf(s,
160
- "<reg name=\"ffr\" bitsize=\"%d\""
161
- " regnum=\"%d\" group=\"vector\""
162
- " type=\"svep\"/>",
163
- cpu->sve_max_vq * 16, base_reg++);
164
- g_string_append_printf(s,
165
- "<reg name=\"vg\" bitsize=\"64\""
166
- " regnum=\"%d\" type=\"int\"/>",
167
- base_reg++);
168
- info->num += 2;
169
- g_string_append_printf(s, "</feature>");
170
- cpu->dyn_svereg_xml.desc = g_string_free(s, false);
171
-
172
- return cpu->dyn_svereg_xml.num;
173
-}
174
-
175
-
176
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
48
{
177
{
49
- uint32_t val, shift;
178
ARMCPU *cpu = ARM_CPU(cs);
50
- uint64_t *table = vn;
179
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
51
+ uint64_t tmp, val = 0;
180
index XXXXXXX..XXXXXXX 100644
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
181
--- a/target/arm/gdbstub64.c
53
+ uint32_t base_reg = desc >> 2;
182
+++ b/target/arm/gdbstub64.c
54
+ uint32_t shift, index, reg;
183
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
55
184
56
- val = 0;
185
return 0;
57
- for (shift = 0; shift < 32; shift += 8) {
58
- uint32_t index = (ireg >> shift) & 0xff;
59
+ for (shift = 0; shift < 64; shift += 8) {
60
+ index = (ireg >> shift) & 0xff;
61
if (index < maxindex) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
63
- val |= tmp << shift;
64
+ reg = base_reg + (index >> 3);
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
186
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
187
+
76
index XXXXXXX..XXXXXXX 100644
188
+struct TypeSize {
77
--- a/target/arm/translate-neon.c.inc
189
+ const char *gdb_type;
78
+++ b/target/arm/translate-neon.c.inc
190
+ short size;
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
191
+ char sz, suffix;
80
192
+};
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
193
+
82
{
194
+static const struct TypeSize vec_lanes[] = {
83
- int n;
195
+ /* quads */
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
196
+ { "uint128", 128, 'q', 'u' },
85
- TCGv_ptr ptr1;
197
+ { "int128", 128, 'q', 's' },
86
+ TCGv_i64 val, def;
198
+ /* 64 bit */
87
+ TCGv_i32 desc;
199
+ { "ieee_double", 64, 'd', 'f' },
88
200
+ { "uint64", 64, 'd', 'u' },
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
201
+ { "int64", 64, 'd', 's' },
90
return false;
202
+ /* 32 bit */
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
203
+ { "ieee_single", 32, 's', 'f' },
92
return true;
204
+ { "uint32", 32, 's', 'u' },
93
}
205
+ { "int32", 32, 's', 's' },
94
206
+ /* 16 bit */
95
- n = a->len + 1;
207
+ { "ieee_half", 16, 'h', 'f' },
96
- if ((a->vn + n) > 32) {
208
+ { "uint16", 16, 'h', 'u' },
97
+ if ((a->vn + a->len + 1) > 32) {
209
+ { "int16", 16, 'h', 's' },
98
/*
210
+ /* bytes */
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
211
+ { "uint8", 8, 'b', 'u' },
100
* helper function running off the end of the register file.
212
+ { "int8", 8, 'b', 's' },
101
*/
213
+};
102
return false;
214
+
103
}
215
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
104
- n <<= 3;
216
+{
105
- tmp = tcg_temp_new_i32();
217
+ ARMCPU *cpu = ARM_CPU(cs);
106
- if (a->op) {
218
+ GString *s = g_string_new(NULL);
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
219
+ DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
108
- } else {
220
+ g_autoptr(GString) ts = g_string_new("");
109
- tcg_gen_movi_i32(tmp, 0);
221
+ int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
110
- }
222
+ info->num = 0;
111
- tmp2 = tcg_temp_new_i32();
223
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
224
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
113
- ptr1 = vfp_reg_ptr(true, a->vn);
225
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
114
- tmp4 = tcg_const_i32(n);
226
+
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
227
+ /* First define types and totals in a whole VL */
116
228
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
229
+ int count = reg_width / vec_lanes[i].size;
118
+ def = tcg_temp_new_i64();
230
+ g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
119
if (a->op) {
231
+ g_string_append_printf(s,
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
232
+ "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
121
+ read_neon_element64(def, a->vd, 0, MO_64);
233
+ ts->str, vec_lanes[i].gdb_type, count);
122
} else {
234
+ }
123
- tcg_gen_movi_i32(tmp, 0);
235
+ /*
124
+ tcg_gen_movi_i64(def, 0);
236
+ * Now define a union for each size group containing unsigned and
125
}
237
+ * signed and potentially float versions of each size from 128 to
126
- tmp3 = tcg_temp_new_i32();
238
+ * 8 bits.
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
239
+ */
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
240
+ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
129
- tcg_temp_free_i32(tmp);
241
+ const char suf[] = { 'q', 'd', 's', 'h', 'b' };
130
- tcg_temp_free_i32(tmp4);
242
+ g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
131
- tcg_temp_free_ptr(ptr1);
243
+ for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
132
+ val = tcg_temp_new_i64();
244
+ if (vec_lanes[j].size == bits) {
133
+ read_neon_element64(val, a->vm, 0, MO_64);
245
+ g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
134
246
+ vec_lanes[j].suffix,
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
247
+ vec_lanes[j].sz, vec_lanes[j].suffix);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
248
+ }
137
- tcg_temp_free_i32(tmp2);
249
+ }
138
- tcg_temp_free_i32(tmp3);
250
+ g_string_append(s, "</union>");
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
251
+ }
140
+ write_neon_element64(val, a->vd, 0, MO_64);
252
+ /* And now the final union of unions */
141
+
253
+ g_string_append(s, "<union id=\"svev\">");
142
+ tcg_temp_free_i64(def);
254
+ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
143
+ tcg_temp_free_i64(val);
255
+ const char suf[] = { 'q', 'd', 's', 'h', 'b' };
144
+ tcg_temp_free_i32(desc);
256
+ g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
145
return true;
257
+ suf[i], suf[i]);
146
}
258
+ }
147
259
+ g_string_append(s, "</union>");
260
+
261
+ /* Finally the sve prefix type */
262
+ g_string_append_printf(s,
263
+ "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
264
+ reg_width / 8);
265
+
266
+ /* Then define each register in parts for each vq */
267
+ for (i = 0; i < 32; i++) {
268
+ g_string_append_printf(s,
269
+ "<reg name=\"z%d\" bitsize=\"%d\""
270
+ " regnum=\"%d\" type=\"svev\"/>",
271
+ i, reg_width, base_reg++);
272
+ info->num++;
273
+ }
274
+ /* fpscr & status registers */
275
+ g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
276
+ " regnum=\"%d\" group=\"float\""
277
+ " type=\"int\"/>", base_reg++);
278
+ g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
279
+ " regnum=\"%d\" group=\"float\""
280
+ " type=\"int\"/>", base_reg++);
281
+ info->num += 2;
282
+
283
+ for (i = 0; i < 16; i++) {
284
+ g_string_append_printf(s,
285
+ "<reg name=\"p%d\" bitsize=\"%d\""
286
+ " regnum=\"%d\" type=\"svep\"/>",
287
+ i, cpu->sve_max_vq * 16, base_reg++);
288
+ info->num++;
289
+ }
290
+ g_string_append_printf(s,
291
+ "<reg name=\"ffr\" bitsize=\"%d\""
292
+ " regnum=\"%d\" group=\"vector\""
293
+ " type=\"svep\"/>",
294
+ cpu->sve_max_vq * 16, base_reg++);
295
+ g_string_append_printf(s,
296
+ "<reg name=\"vg\" bitsize=\"64\""
297
+ " regnum=\"%d\" type=\"int\"/>",
298
+ base_reg++);
299
+ info->num += 2;
300
+ g_string_append_printf(s, "</feature>");
301
+ info->desc = g_string_free(s, false);
302
+
303
+ return info->num;
304
+}
148
--
305
--
149
2.20.1
306
2.34.1
150
307
151
308
diff view generated by jsdifflib
New patch
[PULL 04/21] target/arm: Split out output_vector_union_type
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Create a subroutine for creating the union of unions
4
of the various type sizes that a vector may contain.
5
6
Reviewed-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
13
1 file changed, 45 insertions(+), 38 deletions(-)
14
15
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/gdbstub64.c
18
+++ b/target/arm/gdbstub64.c
19
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
20
return 0;
21
}
22
23
-struct TypeSize {
24
- const char *gdb_type;
25
- short size;
26
- char sz, suffix;
27
-};
28
-
29
-static const struct TypeSize vec_lanes[] = {
30
- /* quads */
31
- { "uint128", 128, 'q', 'u' },
32
- { "int128", 128, 'q', 's' },
33
- /* 64 bit */
34
- { "ieee_double", 64, 'd', 'f' },
35
- { "uint64", 64, 'd', 'u' },
36
- { "int64", 64, 'd', 's' },
37
- /* 32 bit */
38
- { "ieee_single", 32, 's', 'f' },
39
- { "uint32", 32, 's', 'u' },
40
- { "int32", 32, 's', 's' },
41
- /* 16 bit */
42
- { "ieee_half", 16, 'h', 'f' },
43
- { "uint16", 16, 'h', 'u' },
44
- { "int16", 16, 'h', 's' },
45
- /* bytes */
46
- { "uint8", 8, 'b', 'u' },
47
- { "int8", 8, 'b', 's' },
48
-};
49
-
50
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
51
+static void output_vector_union_type(GString *s, int reg_width)
52
{
53
- ARMCPU *cpu = ARM_CPU(cs);
54
- GString *s = g_string_new(NULL);
55
- DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
56
+ struct TypeSize {
57
+ const char *gdb_type;
58
+ short size;
59
+ char sz, suffix;
60
+ };
61
+
62
+ static const struct TypeSize vec_lanes[] = {
63
+ /* quads */
64
+ { "uint128", 128, 'q', 'u' },
65
+ { "int128", 128, 'q', 's' },
66
+ /* 64 bit */
67
+ { "ieee_double", 64, 'd', 'f' },
68
+ { "uint64", 64, 'd', 'u' },
69
+ { "int64", 64, 'd', 's' },
70
+ /* 32 bit */
71
+ { "ieee_single", 32, 's', 'f' },
72
+ { "uint32", 32, 's', 'u' },
73
+ { "int32", 32, 's', 's' },
74
+ /* 16 bit */
75
+ { "ieee_half", 16, 'h', 'f' },
76
+ { "uint16", 16, 'h', 'u' },
77
+ { "int16", 16, 'h', 's' },
78
+ /* bytes */
79
+ { "uint8", 8, 'b', 'u' },
80
+ { "int8", 8, 'b', 's' },
81
+ };
82
+
83
+ static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
84
+
85
g_autoptr(GString) ts = g_string_new("");
86
- int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
87
- info->num = 0;
88
- g_string_printf(s, "<?xml version=\"1.0\"?>");
89
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
90
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
91
+ int i, j, bits;
92
93
/* First define types and totals in a whole VL */
94
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
95
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
96
* 8 bits.
97
*/
98
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
99
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
100
g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
101
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
102
if (vec_lanes[j].size == bits) {
103
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
104
/* And now the final union of unions */
105
g_string_append(s, "<union id=\"svev\">");
106
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
107
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
108
g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
109
suf[i], suf[i]);
110
}
111
g_string_append(s, "</union>");
112
+}
113
+
114
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
115
+{
116
+ ARMCPU *cpu = ARM_CPU(cs);
117
+ GString *s = g_string_new(NULL);
118
+ DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
119
+ int i, reg_width = (cpu->sve_max_vq * 128);
120
+ info->num = 0;
121
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
122
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
123
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
124
+
125
+ output_vector_union_type(s, reg_width);
126
127
/* Finally the sve prefix type */
128
g_string_append_printf(s,
129
--
130
2.34.1
diff view generated by jsdifflib
[PULL 14/16] hw/arm/nseries: Check return value from load_image_targphys()
[PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
1
The nseries machines have a codepath that allows them to load a
1
From: Richard Henderson <richard.henderson@linaro.org>
2
secondary bootloader. This code wasn't checking that the
3
load_image_targphys() succeeded. Check the return value and report
4
the error to the user.
5
2
6
While we're in the vicinity, fix the comment style of the
3
Rather than increment base_reg and num, compute num from the change
7
comment documenting what this image load is doing.
4
to base_reg at the end. Clean up some nearby comments.
8
5
9
Fixes: Coverity CID 1192904
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
13
---
10
---
14
hw/arm/nseries.c | 15 +++++++++++----
11
target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
15
1 file changed, 11 insertions(+), 4 deletions(-)
12
1 file changed, 16 insertions(+), 11 deletions(-)
16
13
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/nseries.c
16
--- a/target/arm/gdbstub64.c
20
+++ b/hw/arm/nseries.c
17
+++ b/target/arm/gdbstub64.c
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
18
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
22
/* No, wait, better start at the ROM. */
19
g_string_append(s, "</union>");
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
20
}
24
21
25
- /* This is intended for loading the `secondary.bin' program from
22
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
26
+ /*
23
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
27
+ * This is intended for loading the `secondary.bin' program from
24
{
28
* Nokia images (the NOLO bootloader). The entry point seems
25
ARMCPU *cpu = ARM_CPU(cs);
29
* to be at OMAP2_Q2_BASE + 0x400000.
26
GString *s = g_string_new(NULL);
30
*
27
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
28
- int i, reg_width = (cpu->sve_max_vq * 128);
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
29
- info->num = 0;
33
*
30
+ int reg_width = cpu->sve_max_vq * 128;
34
* The code above is for loading the `zImage' file from Nokia
31
+ int base_reg = orig_base_reg;
35
- * images. */
32
+ int i;
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
33
+
37
- machine->ram_size - 0x400000);
34
g_string_printf(s, "<?xml version=\"1.0\"?>");
38
+ * images.
35
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
39
+ */
36
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
40
+ if (load_image_targphys(option_rom[0].name,
37
41
+ OMAP2_Q2_BASE + 0x400000,
38
+ /* Create the vector union type. */
42
+ machine->ram_size - 0x400000) < 0) {
39
output_vector_union_type(s, reg_width);
43
+ error_report("Failed to load secondary bootloader %s",
40
44
+ option_rom[0].name);
41
- /* Finally the sve prefix type */
45
+ exit(EXIT_FAILURE);
42
+ /* Create the predicate vector type. */
46
+ }
43
g_string_append_printf(s,
47
44
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
48
n800_setup_nolo_tags(nolo_tags);
45
reg_width / 8);
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
46
47
- /* Then define each register in parts for each vq */
48
+ /* Define the vector registers. */
49
for (i = 0; i < 32; i++) {
50
g_string_append_printf(s,
51
"<reg name=\"z%d\" bitsize=\"%d\""
52
" regnum=\"%d\" type=\"svev\"/>",
53
i, reg_width, base_reg++);
54
- info->num++;
55
}
56
+
57
/* fpscr & status registers */
58
g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
59
" regnum=\"%d\" group=\"float\""
60
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
61
g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
62
" regnum=\"%d\" group=\"float\""
63
" type=\"int\"/>", base_reg++);
64
- info->num += 2;
65
66
+ /* Define the predicate registers. */
67
for (i = 0; i < 16; i++) {
68
g_string_append_printf(s,
69
"<reg name=\"p%d\" bitsize=\"%d\""
70
" regnum=\"%d\" type=\"svep\"/>",
71
i, cpu->sve_max_vq * 16, base_reg++);
72
- info->num++;
73
}
74
g_string_append_printf(s,
75
"<reg name=\"ffr\" bitsize=\"%d\""
76
" regnum=\"%d\" group=\"vector\""
77
" type=\"svep\"/>",
78
cpu->sve_max_vq * 16, base_reg++);
79
+
80
+ /* Define the vector length pseudo-register. */
81
g_string_append_printf(s,
82
"<reg name=\"vg\" bitsize=\"64\""
83
" regnum=\"%d\" type=\"int\"/>",
84
base_reg++);
85
- info->num += 2;
86
- g_string_append_printf(s, "</feature>");
87
- info->desc = g_string_free(s, false);
88
89
+ g_string_append_printf(s, "</feature>");
90
+
91
+ info->desc = g_string_free(s, false);
92
+ info->num = base_reg - orig_base_reg;
93
return info->num;
94
}
50
--
95
--
51
2.20.1
96
2.34.1
52
97
53
98
diff view generated by jsdifflib
[PULL 13/16] hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
[PULL 06/21] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We don't need to fill the full pic[] array if we only use
3
Reviewed-by: Fabiano Rosas <farosas@suse.de>
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
when necessary.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
6
Message-id: 20230227213329.793795-7-richard.henderson@linaro.org
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
8
---
12
hw/arm/musicpal.c | 25 +++++++++++++------------
9
target/arm/gdbstub64.c | 5 +++--
13
1 file changed, 13 insertions(+), 12 deletions(-)
10
1 file changed, 3 insertions(+), 2 deletions(-)
14
11
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
12
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/musicpal.c
14
--- a/target/arm/gdbstub64.c
18
+++ b/hw/arm/musicpal.c
15
+++ b/target/arm/gdbstub64.c
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
16
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
20
static void musicpal_init(MachineState *machine)
17
GString *s = g_string_new(NULL);
21
{
18
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
22
ARMCPU *cpu;
19
int reg_width = cpu->sve_max_vq * 128;
23
- qemu_irq pic[32];
20
+ int pred_width = cpu->sve_max_vq * 16;
24
DeviceState *dev;
21
int base_reg = orig_base_reg;
25
+ DeviceState *pic;
22
int i;
26
DeviceState *uart_orgate;
23
27
DeviceState *i2c_dev;
24
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
28
DeviceState *lcd_dev;
25
g_string_append_printf(s,
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
26
"<reg name=\"p%d\" bitsize=\"%d\""
30
&error_fatal);
27
" regnum=\"%d\" type=\"svep\"/>",
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
28
- i, cpu->sve_max_vq * 16, base_reg++);
32
29
+ i, pred_width, base_reg++);
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
30
}
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
31
g_string_append_printf(s,
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
32
"<reg name=\"ffr\" bitsize=\"%d\""
36
- for (i = 0; i < 32; i++) {
33
" regnum=\"%d\" group=\"vector\""
37
- pic[i] = qdev_get_gpio_in(dev, i);
34
" type=\"svep\"/>",
38
- }
35
- cpu->sve_max_vq * 16, base_reg++);
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
36
+ pred_width, base_reg++);
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
37
41
- pic[MP_TIMER4_IRQ], NULL);
38
/* Define the vector length pseudo-register. */
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
39
g_string_append_printf(s,
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
47
48
/* Logically OR both UART IRQs together */
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
55
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
57
qdev_get_gpio_in(uart_orgate, 0),
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
59
OBJECT(get_system_memory()), &error_fatal);
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
65
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
67
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
69
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
71
- pic[MP_GPIO_IRQ]);
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
75
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
77
NULL);
78
sysbus_realize_and_unref(s, &error_fatal);
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
82
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
85
--
40
--
86
2.20.1
41
2.34.1
87
42
88
43
diff view generated by jsdifflib
[PULL 05/16] target/arm: add space before the open parenthesis '('
[PULL 07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fix code style. Space required before the open parenthesis '('.
3
Define svep based on the size of the predicates,
4
not the primary vector registers.
4
5
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate.c | 2 +-
11
target/arm/gdbstub64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
16
--- a/target/arm/gdbstub64.c
17
+++ b/target/arm/translate.c
17
+++ b/target/arm/gdbstub64.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
18
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
19
- Hardware watchpoints.
19
/* Create the predicate vector type. */
20
Hardware breakpoints have already been handled and skip this code.
20
g_string_append_printf(s,
21
*/
21
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
22
- switch(dc->base.is_jmp) {
22
- reg_width / 8);
23
+ switch (dc->base.is_jmp) {
23
+ pred_width / 8);
24
case DISAS_NEXT:
24
25
case DISAS_TOO_MANY:
25
/* Define the vector registers. */
26
gen_goto_tb(dc, 1, dc->base.pc_next);
26
for (i = 0; i < 32; i++) {
27
--
27
--
28
2.20.1
28
2.34.1
29
30
diff view generated by jsdifflib
[PULL 12/16] hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
[PULL 08/21] target/arm: Add name argument to output_vector_union_type
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The MusicPal board code connects both of the IRQ outputs of the UART
3
This will make the function usable between SVE and SME.
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
9
4
10
This kind of wiring needs an explicitly created OR gate; add one.
11
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
10
---
18
hw/arm/musicpal.c | 17 +++++++++++++----
11
target/arm/gdbstub64.c | 28 ++++++++++++++--------------
19
hw/arm/Kconfig | 1 +
12
1 file changed, 14 insertions(+), 14 deletions(-)
20
2 files changed, 14 insertions(+), 4 deletions(-)
21
13
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
23
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/musicpal.c
16
--- a/target/arm/gdbstub64.c
25
+++ b/hw/arm/musicpal.c
17
+++ b/target/arm/gdbstub64.c
26
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
27
#include "ui/console.h"
19
return 0;
28
#include "hw/i2c/i2c.h"
20
}
29
#include "hw/irq.h"
21
30
+#include "hw/or-irq.h"
22
-static void output_vector_union_type(GString *s, int reg_width)
31
#include "hw/audio/wm8750.h"
23
+static void output_vector_union_type(GString *s, int reg_width,
32
#include "sysemu/block-backend.h"
24
+ const char *name)
33
#include "sysemu/runstate.h"
25
{
34
@@ -XXX,XX +XXX,XX @@
26
struct TypeSize {
35
#define MP_TIMER4_IRQ 7
27
const char *gdb_type;
36
#define MP_EHCI_IRQ 8
28
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
37
#define MP_ETH_IRQ 9
29
};
38
-#define MP_UART1_IRQ 11
30
39
-#define MP_UART2_IRQ 11
31
static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
40
+#define MP_UART_SHARED_IRQ 11
32
-
41
#define MP_GPIO_IRQ 12
33
- g_autoptr(GString) ts = g_string_new("");
42
#define MP_RTC_IRQ 28
34
int i, j, bits;
43
#define MP_AUDIO_IRQ 30
35
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
36
/* First define types and totals in a whole VL */
45
ARMCPU *cpu;
37
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
46
qemu_irq pic[32];
38
- int count = reg_width / vec_lanes[i].size;
47
DeviceState *dev;
39
- g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
48
+ DeviceState *uart_orgate;
40
g_string_append_printf(s,
49
DeviceState *i2c_dev;
41
- "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
50
DeviceState *lcd_dev;
42
- ts->str, vec_lanes[i].gdb_type, count);
51
DeviceState *key_dev;
43
+ "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
44
+ name, vec_lanes[i].sz, vec_lanes[i].suffix,
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
45
+ vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
54
pic[MP_TIMER4_IRQ], NULL);
46
}
55
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
57
+ /* Logically OR both UART IRQs together */
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
62
+
47
+
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
48
/*
64
+ qdev_get_gpio_in(uart_orgate, 0),
49
* Now define a union for each size group containing unsigned and
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
50
* signed and potentially float versions of each size from 128 to
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
51
* 8 bits.
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
52
*/
68
+ qdev_get_gpio_in(uart_orgate, 1),
53
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
54
- g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
70
55
+ g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
71
/* Register flash */
56
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
57
if (vec_lanes[j].size == bits) {
73
index XXXXXXX..XXXXXXX 100644
58
- g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
74
--- a/hw/arm/Kconfig
59
- vec_lanes[j].suffix,
75
+++ b/hw/arm/Kconfig
60
+ g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
61
+ vec_lanes[j].suffix, name,
77
62
vec_lanes[j].sz, vec_lanes[j].suffix);
78
config MUSICPAL
63
}
79
bool
64
}
80
+ select OR_IRQ
65
g_string_append(s, "</union>");
81
select BITBANG_I2C
66
}
82
select MARVELL_88W8618
67
+
83
select PTIMER
68
/* And now the final union of unions */
69
- g_string_append(s, "<union id=\"svev\">");
70
+ g_string_append_printf(s, "<union id=\"%s\">", name);
71
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
72
- g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
73
- suf[i], suf[i]);
74
+ g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
75
+ suf[i], name, suf[i]);
76
}
77
g_string_append(s, "</union>");
78
}
79
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
80
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
81
82
/* Create the vector union type. */
83
- output_vector_union_type(s, reg_width);
84
+ output_vector_union_type(s, reg_width, "svev");
85
86
/* Create the predicate vector type. */
87
g_string_append_printf(s,
84
--
88
--
85
2.20.1
89
2.34.1
86
90
87
91
diff view generated by jsdifflib
New patch
[PULL 09/21] target/arm: Simplify iteration over bit widths
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Order suf[] by the log8 of the width.
4
Use ARRAY_SIZE instead of hard-coding 128.
5
6
This changes the order of the union definitions,
7
but retains the order of the union-of-union members.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/gdbstub64.c | 10 ++++++----
15
1 file changed, 6 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/gdbstub64.c
20
+++ b/target/arm/gdbstub64.c
21
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
22
{ "int8", 8, 'b', 's' },
23
};
24
25
- static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
26
- int i, j, bits;
27
+ static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
28
+ int i, j;
29
30
/* First define types and totals in a whole VL */
31
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
32
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
33
* signed and potentially float versions of each size from 128 to
34
* 8 bits.
35
*/
36
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
37
+ for (i = 0; i < ARRAY_SIZE(suf); i++) {
38
+ int bits = 8 << i;
39
+
40
g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
41
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
42
if (vec_lanes[j].size == bits) {
43
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
44
45
/* And now the final union of unions */
46
g_string_append_printf(s, "<union id=\"%s\">", name);
47
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
48
+ for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
49
g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
50
suf[i], name, suf[i]);
51
}
52
--
53
2.34.1
diff view generated by jsdifflib
New patch
[PULL 10/21] target/arm: Create pauth_ptr_mask
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Keep the logic for pauth within pauth_helper.c, and expose
4
a helper function for use with the gdbstub pac extension.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 10 ++++++++++
12
target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
13
2 files changed, 32 insertions(+), 4 deletions(-)
14
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
18
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
20
bool arm_singlestep_active(CPUARMState *env);
21
bool arm_generate_debug_exceptions(CPUARMState *env);
22
23
+/**
24
+ * pauth_ptr_mask:
25
+ * @env: cpu context
26
+ * @ptr: selects between TTBR0 and TTBR1
27
+ * @data: selects between TBI and TBID
28
+ *
29
+ * Return a mask of the bits of @ptr that contain the authentication code.
30
+ */
31
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
32
+
33
/* Add the cpreg definitions for debug related system registers */
34
void define_debug_regs(ARMCPU *cpu);
35
36
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/tcg/pauth_helper.c
39
+++ b/target/arm/tcg/pauth_helper.c
40
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
41
return pac | ext | ptr;
42
}
43
44
-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
45
+static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
46
{
47
- /* Note that bit 55 is used whether or not the regime has 2 ranges. */
48
- uint64_t extfield = sextract64(ptr, 55, 1);
49
int bot_pac_bit = 64 - param.tsz;
50
int top_pac_bit = 64 - 8 * param.tbi;
51
52
- return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
53
+ return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
54
+}
55
+
56
+static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
57
+{
58
+ uint64_t mask = pauth_ptr_mask_internal(param);
59
+
60
+ /* Note that bit 55 is used whether or not the regime has 2 ranges. */
61
+ if (extract64(ptr, 55, 1)) {
62
+ return ptr | mask;
63
+ } else {
64
+ return ptr & ~mask;
65
+ }
66
+}
67
+
68
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
69
+{
70
+ ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
71
+ ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
72
+
73
+ return pauth_ptr_mask_internal(param);
74
}
75
76
static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
77
--
78
2.34.1
diff view generated by jsdifflib
[PULL 06/16] docs: add some notes on the sbsa-ref machine
[PULL 11/21] target/arm: Implement gdbstub pauth extension
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We should at least document what this machine is about.
3
The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
4
ptrace register set.
4
5
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
6
The original gdb feature consists of two masks, data and code, which are
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
used to mask out the authentication code within a pointer. Following
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
8
discussion with Luis Machado, add two more masks in order to support
8
Cc: Leif Lindholm <leif@nuviainc.com>
9
pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
10
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
11
[PMM: fixed filename mismatch]
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
16
---
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
17
configs/targets/aarch64-linux-user.mak | 2 +-
15
docs/system/target-arm.rst | 1 +
18
configs/targets/aarch64-softmmu.mak | 2 +-
16
2 files changed, 33 insertions(+)
19
configs/targets/aarch64_be-linux-user.mak | 2 +-
17
create mode 100644 docs/system/arm/sbsa.rst
20
target/arm/internals.h | 2 ++
21
target/arm/gdbstub.c | 5 ++++
22
target/arm/gdbstub64.c | 34 +++++++++++++++++++++++
23
gdb-xml/aarch64-pauth.xml | 15 ++++++++++
24
7 files changed, 59 insertions(+), 3 deletions(-)
25
create mode 100644 gdb-xml/aarch64-pauth.xml
18
26
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
27
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
28
index XXXXXXX..XXXXXXX 100644
29
--- a/configs/targets/aarch64-linux-user.mak
30
+++ b/configs/targets/aarch64-linux-user.mak
31
@@ -XXX,XX +XXX,XX @@
32
TARGET_ARCH=aarch64
33
TARGET_BASE_ARCH=arm
34
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
35
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
36
TARGET_HAS_BFLT=y
37
CONFIG_SEMIHOSTING=y
38
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
39
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
40
index XXXXXXX..XXXXXXX 100644
41
--- a/configs/targets/aarch64-softmmu.mak
42
+++ b/configs/targets/aarch64-softmmu.mak
43
@@ -XXX,XX +XXX,XX @@
44
TARGET_ARCH=aarch64
45
TARGET_BASE_ARCH=arm
46
TARGET_SUPPORTS_MTTCG=y
47
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
48
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
49
TARGET_NEED_FDT=y
50
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
51
index XXXXXXX..XXXXXXX 100644
52
--- a/configs/targets/aarch64_be-linux-user.mak
53
+++ b/configs/targets/aarch64_be-linux-user.mak
54
@@ -XXX,XX +XXX,XX @@
55
TARGET_ARCH=aarch64
56
TARGET_BASE_ARCH=arm
57
TARGET_BIG_ENDIAN=y
58
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
59
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
60
TARGET_HAS_BFLT=y
61
CONFIG_SEMIHOSTING=y
62
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
63
diff --git a/target/arm/internals.h b/target/arm/internals.h
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/internals.h
66
+++ b/target/arm/internals.h
67
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
68
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
69
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
70
int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
71
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
72
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
73
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
74
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
75
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
76
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/gdbstub.c
79
+++ b/target/arm/gdbstub.c
80
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
81
aarch64_gdb_set_fpu_reg,
82
34, "aarch64-fpu.xml", 0);
83
}
84
+ if (isar_feature_aa64_pauth(&cpu->isar)) {
85
+ gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
86
+ aarch64_gdb_set_pauth_reg,
87
+ 4, "aarch64-pauth.xml", 0);
88
+ }
89
#endif
90
} else {
91
if (arm_feature(env, ARM_FEATURE_NEON)) {
92
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/gdbstub64.c
95
+++ b/target/arm/gdbstub64.c
96
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
97
return 0;
98
}
99
100
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
101
+{
102
+ switch (reg) {
103
+ case 0: /* pauth_dmask */
104
+ case 1: /* pauth_cmask */
105
+ case 2: /* pauth_dmask_high */
106
+ case 3: /* pauth_cmask_high */
107
+ /*
108
+ * Note that older versions of this feature only contained
109
+ * pauth_{d,c}mask, for use with Linux user processes, and
110
+ * thus exclusively in the low half of the address space.
111
+ *
112
+ * To support system mode, and to debug kernels, two new regs
113
+ * were added to cover the high half of the address space.
114
+ * For the purpose of pauth_ptr_mask, we can use any well-formed
115
+ * address within the address space half -- here, 0 and -1.
116
+ */
117
+ {
118
+ bool is_data = !(reg & 1);
119
+ bool is_high = reg & 2;
120
+ uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
121
+ return gdb_get_reg64(buf, mask);
122
+ }
123
+ default:
124
+ return 0;
125
+ }
126
+}
127
+
128
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
129
+{
130
+ /* All pseudo registers are read-only. */
131
+ return 0;
132
+}
133
+
134
static void output_vector_union_type(GString *s, int reg_width,
135
const char *name)
136
{
137
diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
20
new file mode 100644
138
new file mode 100644
21
index XXXXXXX..XXXXXXX
139
index XXXXXXX..XXXXXXX
22
--- /dev/null
140
--- /dev/null
23
+++ b/docs/system/arm/sbsa.rst
141
+++ b/gdb-xml/aarch64-pauth.xml
24
@@ -XXX,XX +XXX,XX @@
142
@@ -XXX,XX +XXX,XX @@
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
143
+<?xml version="1.0"?>
26
+==================================================================
144
+<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.
27
+
145
+
28
+While the `virt` board is a generic board platform that doesn't match
146
+ Copying and distribution of this file, with or without modification,
29
+any real hardware the `sbsa-ref` board intends to look like real
147
+ are permitted in any medium without royalty provided the copyright
30
+hardware. The `Server Base System Architecture
148
+ notice and this notice are preserved. -->
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
32
+minimum base line of hardware support and importantly how the firmware
33
+reports that to any operating system. It is a static system that
34
+reports a very minimal DT to the firmware for non-discoverable
35
+information about components affected by the qemu command line (i.e.
36
+cpus and memory). As a result it must have a firmware specifically
37
+built to expect a certain hardware layout (as you would in a real
38
+machine).
39
+
149
+
40
+It is intended to be a machine for developing firmware and testing
150
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
41
+standards compliance with operating systems.
151
+<feature name="org.gnu.gdb.aarch64.pauth">
152
+ <reg name="pauth_dmask" bitsize="64"/>
153
+ <reg name="pauth_cmask" bitsize="64"/>
154
+ <reg name="pauth_dmask_high" bitsize="64"/>
155
+ <reg name="pauth_cmask_high" bitsize="64"/>
156
+</feature>
42
+
157
+
43
+Supported devices
44
+"""""""""""""""""
45
+
46
+The sbsa-ref board supports:
47
+
48
+ - A configurable number of AArch64 CPUs
49
+ - GIC version 3
50
+ - System bus AHCI controller
51
+ - System bus EHCI controller
52
+ - CDROM and hard disc on AHCI bus
53
+ - E1000E ethernet card on PCIe bus
54
+ - VGA display adaptor on PCIe bus
55
+ - A generic SBSA watchdog device
56
+
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
58
index XXXXXXX..XXXXXXX 100644
59
--- a/docs/system/target-arm.rst
60
+++ b/docs/system/target-arm.rst
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
62
arm/mps2
63
arm/musca
64
arm/realview
65
+ arm/sbsa
66
arm/versatile
67
arm/vexpress
68
arm/aspeed
69
--
158
--
70
2.20.1
159
2.34.1
71
72
diff view generated by jsdifflib
[PULL 09/16] hw/arm/armsse: Correct expansion MPC interrupt lines
[PULL 12/21] target/arm: Export arm_v7m_mrs_control
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: David Reiss <dreiss@meta.com>
2
2
3
We can use one MPC per SRAM bank, but we currently only wire the
3
Allow the function to be used outside of m_helper.c.
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
4
Rename with an "arm_" prefix.
5
5
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: David Reiss <dreiss@meta.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
11
[rth: Split out of a larger patch]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
hw/arm/armsse.c | 3 ++-
15
target/arm/internals.h | 3 +++
13
1 file changed, 2 insertions(+), 1 deletion(-)
16
target/arm/tcg/m_helper.c | 6 +++---
17
2 files changed, 6 insertions(+), 3 deletions(-)
14
18
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/armsse.c
21
--- a/target/arm/internals.h
18
+++ b/hw/arm/armsse.c
22
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
23
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
20
qdev_get_gpio_in(dev_splitter, 0));
24
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
21
qdev_connect_gpio_out(dev_splitter, 0,
25
#endif
22
qdev_get_gpio_in_named(dev_secctl,
26
23
- "mpc_status", 0));
27
+/* Read the CONTROL register as the MRS instruction would. */
24
+ "mpc_status",
28
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
25
+ i - IOTS_NUM_EXP_MPC));
29
+
26
}
30
#ifdef CONFIG_USER_ONLY
27
31
static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
28
qdev_connect_gpio_out(dev_splitter, 1,
32
#else
33
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/tcg/m_helper.c
36
+++ b/target/arm/tcg/m_helper.c
37
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
38
return xpsr_read(env) & mask;
39
}
40
41
-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
42
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
43
{
44
uint32_t value = env->v7m.control[secure];
45
46
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
47
case 0 ... 7: /* xPSR sub-fields */
48
return v7m_mrs_xpsr(env, reg, 0);
49
case 20: /* CONTROL */
50
- return v7m_mrs_control(env, 0);
51
+ return arm_v7m_mrs_control(env, 0);
52
default:
53
/* Unprivileged reads others as zero. */
54
return 0;
55
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
56
case 0 ... 7: /* xPSR sub-fields */
57
return v7m_mrs_xpsr(env, reg, el);
58
case 20: /* CONTROL */
59
- return v7m_mrs_control(env, env->v7m.secure);
60
+ return arm_v7m_mrs_control(env, env->v7m.secure);
61
case 0x94: /* CONTROL_NS */
62
/*
63
* We have to handle this here because unprivileged Secure code
29
--
64
--
30
2.20.1
65
2.34.1
31
66
32
67
diff view generated by jsdifflib
[PULL 11/16] hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
[PULL 13/21] target/arm: Export arm_v7m_get_sp_ptr
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: David Reiss <dreiss@meta.com>
2
2
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
3
Allow the function to be used outside of m_helper.c.
4
OMAP2 chip support") takes care of creating the 3 UARTs.
4
Move to be outside of ifndef CONFIG_USER_ONLY block.
5
Rename from get_v7m_sp_ptr.
5
6
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
8
which create the UART and connects it to an IRQ output,
9
overwritting the existing peripheral and its IRQ connection.
10
This is incorrect.
11
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
16
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: David Reiss <dreiss@meta.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
12
[rth: Split out of a larger patch]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
15
---
22
hw/arm/nseries.c | 11 -----------
16
target/arm/internals.h | 10 +++++
23
1 file changed, 11 deletions(-)
17
target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
18
2 files changed, 51 insertions(+), 43 deletions(-)
24
19
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
20
diff --git a/target/arm/internals.h b/target/arm/internals.h
26
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/nseries.c
22
--- a/target/arm/internals.h
28
+++ b/hw/arm/nseries.c
23
+++ b/target/arm/internals.h
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
24
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
25
/* Read the CONTROL register as the MRS instruction would. */
26
uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
27
28
+/*
29
+ * Return a pointer to the location where we currently store the
30
+ * stack pointer for the requested security state and thread mode.
31
+ * This pointer will become invalid if the CPU state is updated
32
+ * such that the stack pointers are switched around (eg changing
33
+ * the SPSEL control bit).
34
+ */
35
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
36
+ bool threadmode, bool spsel);
37
+
38
#ifdef CONFIG_USER_ONLY
39
static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
40
#else
41
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/tcg/m_helper.c
44
+++ b/target/arm/tcg/m_helper.c
45
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
46
arm_rebuild_hflags(env);
31
}
47
}
32
48
33
-static void n8x0_uart_setup(struct n800_s *s)
49
-static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
50
- bool spsel)
34
-{
51
-{
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
36
- /*
52
- /*
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
53
- * Return a pointer to the location where we currently store the
38
- * here, but this code has been removed with the bluetooth backend.
54
- * stack pointer for the requested security state and thread mode.
55
- * This pointer will become invalid if the CPU state is updated
56
- * such that the stack pointers are switched around (eg changing
57
- * the SPSEL control bit).
58
- * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
59
- * Unlike that pseudocode, we require the caller to pass us in the
60
- * SPSEL control bit value; this is because we also use this
61
- * function in handling of pushing of the callee-saves registers
62
- * part of the v8M stack frame (pseudocode PushCalleeStack()),
63
- * and in the tailchain codepath the SPSEL bit comes from the exception
64
- * return magic LR value from the previous exception. The pseudocode
65
- * opencodes the stack-selection in PushCalleeStack(), but we prefer
66
- * to make this utility function generic enough to do the job.
39
- */
67
- */
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
68
- bool want_psp = threadmode && spsel;
69
-
70
- if (secure == env->v7m.secure) {
71
- if (want_psp == v7m_using_psp(env)) {
72
- return &env->regs[13];
73
- } else {
74
- return &env->v7m.other_sp;
75
- }
76
- } else {
77
- if (want_psp) {
78
- return &env->v7m.other_ss_psp;
79
- } else {
80
- return &env->v7m.other_ss_msp;
81
- }
82
- }
41
-}
83
-}
42
-
84
-
43
static void n8x0_usb_setup(struct n800_s *s)
85
static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
86
uint32_t *pvec)
44
{
87
{
45
SysBusDevice *dev;
88
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
89
!mode;
47
n8x0_spi_setup(s);
90
48
n8x0_dss_setup(s);
91
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
49
n8x0_cbus_setup(s);
92
- frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
50
- n8x0_uart_setup(s);
93
- lr & R_V7M_EXCRET_SPSEL_MASK);
51
if (machine_usb(machine)) {
94
+ frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
52
n8x0_usb_setup(s);
95
+ lr & R_V7M_EXCRET_SPSEL_MASK);
53
}
96
want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
97
if (want_psp) {
98
limit = env->v7m.psplim[M_REG_S];
99
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
100
* use 'frame_sp_p' after we do something that makes it invalid.
101
*/
102
bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
103
- uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
104
- return_to_secure,
105
- !return_to_handler,
106
- spsel);
107
+ uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
108
+ !return_to_handler, spsel);
109
uint32_t frameptr = *frame_sp_p;
110
bool pop_ok = true;
111
ARMMMUIdx mmu_idx;
112
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
113
threadmode = !arm_v7m_is_handler_mode(env);
114
spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
115
116
- frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
117
+ frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
118
frameptr = *frame_sp_p;
119
120
/*
121
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
122
}
123
124
#endif /* !CONFIG_USER_ONLY */
125
+
126
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
127
+ bool spsel)
128
+{
129
+ /*
130
+ * Return a pointer to the location where we currently store the
131
+ * stack pointer for the requested security state and thread mode.
132
+ * This pointer will become invalid if the CPU state is updated
133
+ * such that the stack pointers are switched around (eg changing
134
+ * the SPSEL control bit).
135
+ * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
136
+ * Unlike that pseudocode, we require the caller to pass us in the
137
+ * SPSEL control bit value; this is because we also use this
138
+ * function in handling of pushing of the callee-saves registers
139
+ * part of the v8M stack frame (pseudocode PushCalleeStack()),
140
+ * and in the tailchain codepath the SPSEL bit comes from the exception
141
+ * return magic LR value from the previous exception. The pseudocode
142
+ * opencodes the stack-selection in PushCalleeStack(), but we prefer
143
+ * to make this utility function generic enough to do the job.
144
+ */
145
+ bool want_psp = threadmode && spsel;
146
+
147
+ if (secure == env->v7m.secure) {
148
+ if (want_psp == v7m_using_psp(env)) {
149
+ return &env->regs[13];
150
+ } else {
151
+ return &env->v7m.other_sp;
152
+ }
153
+ } else {
154
+ if (want_psp) {
155
+ return &env->v7m.other_ss_psp;
156
+ } else {
157
+ return &env->v7m.other_ss_msp;
158
+ }
159
+ }
160
+}
54
--
161
--
55
2.20.1
162
2.34.1
56
163
57
164
diff view generated by jsdifflib
[PULL 04/16] target/arm: Don't use '#' flag of printf format
[PULL 14/21] target/arm: Implement gdbstub m-profile systemreg and secext
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fix code style. Don't use '#' flag of printf format ('%#') in
3
The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
4
format strings, use '0x' prefix instead
4
go ahead and implement the other system registers as well.
5
5
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Since there is significant overlap between the two, implement
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
them with common code. The only exception is the systemreg
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
8
view of CONTROL, which merges the banked bits as per MRS.
9
10
Signed-off-by: David Reiss <dreiss@meta.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
13
[rth: Substatial rewrite using enumerator and shared code.]
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
target/arm/translate-a64.c | 4 ++--
18
target/arm/cpu.h | 2 +
13
1 file changed, 2 insertions(+), 2 deletions(-)
19
target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
14
20
2 files changed, 180 insertions(+)
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
24
--- a/target/arm/cpu.h
18
+++ b/target/arm/translate-a64.c
25
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
26
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
27
21
break;
28
DynamicGDBXMLInfo dyn_sysreg_xml;
22
default:
29
DynamicGDBXMLInfo dyn_svereg_xml;
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
30
+ DynamicGDBXMLInfo dyn_m_systemreg_xml;
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
31
+ DynamicGDBXMLInfo dyn_m_secextreg_xml;
25
__func__, insn, fpopcode, s->pc_curr);
32
26
g_assert_not_reached();
33
/* Timers used by the generic (architected) timer */
27
}
34
QEMUTimer *gt_timer[NUM_GTIMERS];
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
35
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
29
case 0x7f: /* FSQRT (vector) */
36
index XXXXXXX..XXXXXXX 100644
30
break;
37
--- a/target/arm/gdbstub.c
31
default:
38
+++ b/target/arm/gdbstub.c
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
39
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
40
return cpu->dyn_sysreg_xml.num;
34
g_assert_not_reached();
41
}
42
43
+typedef enum {
44
+ M_SYSREG_MSP,
45
+ M_SYSREG_PSP,
46
+ M_SYSREG_PRIMASK,
47
+ M_SYSREG_CONTROL,
48
+ M_SYSREG_BASEPRI,
49
+ M_SYSREG_FAULTMASK,
50
+ M_SYSREG_MSPLIM,
51
+ M_SYSREG_PSPLIM,
52
+} MProfileSysreg;
53
+
54
+static const struct {
55
+ const char *name;
56
+ int feature;
57
+} m_sysreg_def[] = {
58
+ [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
59
+ [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
60
+ [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
61
+ [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
62
+ [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
63
+ [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
64
+ [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
65
+ [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
66
+};
67
+
68
+static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
69
+{
70
+ uint32_t *ptr;
71
+
72
+ switch (reg) {
73
+ case M_SYSREG_MSP:
74
+ ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
75
+ break;
76
+ case M_SYSREG_PSP:
77
+ ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
78
+ break;
79
+ case M_SYSREG_MSPLIM:
80
+ ptr = &env->v7m.msplim[sec];
81
+ break;
82
+ case M_SYSREG_PSPLIM:
83
+ ptr = &env->v7m.psplim[sec];
84
+ break;
85
+ case M_SYSREG_PRIMASK:
86
+ ptr = &env->v7m.primask[sec];
87
+ break;
88
+ case M_SYSREG_BASEPRI:
89
+ ptr = &env->v7m.basepri[sec];
90
+ break;
91
+ case M_SYSREG_FAULTMASK:
92
+ ptr = &env->v7m.faultmask[sec];
93
+ break;
94
+ case M_SYSREG_CONTROL:
95
+ ptr = &env->v7m.control[sec];
96
+ break;
97
+ default:
98
+ return NULL;
99
+ }
100
+ return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
101
+}
102
+
103
+static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
104
+ MProfileSysreg reg, bool secure)
105
+{
106
+ uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
107
+
108
+ if (ptr == NULL) {
109
+ return 0;
110
+ }
111
+ return gdb_get_reg32(buf, *ptr);
112
+}
113
+
114
+static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
115
+{
116
+ /*
117
+ * Here, we emulate MRS instruction, where CONTROL has a mix of
118
+ * banked and non-banked bits.
119
+ */
120
+ if (reg == M_SYSREG_CONTROL) {
121
+ return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
122
+ }
123
+ return m_sysreg_get(env, buf, reg, env->v7m.secure);
124
+}
125
+
126
+static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
127
+{
128
+ return 0; /* TODO */
129
+}
130
+
131
+static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
132
+{
133
+ ARMCPU *cpu = ARM_CPU(cs);
134
+ CPUARMState *env = &cpu->env;
135
+ GString *s = g_string_new(NULL);
136
+ int base_reg = orig_base_reg;
137
+ int i;
138
+
139
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
140
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
141
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
142
+
143
+ for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
144
+ if (arm_feature(env, m_sysreg_def[i].feature)) {
145
+ g_string_append_printf(s,
146
+ "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
147
+ m_sysreg_def[i].name, base_reg++);
148
+ }
149
+ }
150
+
151
+ g_string_append_printf(s, "</feature>");
152
+ cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
153
+ cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
154
+
155
+ return cpu->dyn_m_systemreg_xml.num;
156
+}
157
+
158
+#ifndef CONFIG_USER_ONLY
159
+/*
160
+ * For user-only, we see the non-secure registers via m_systemreg above.
161
+ * For secext, encode the non-secure view as even and secure view as odd.
162
+ */
163
+static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
164
+{
165
+ return m_sysreg_get(env, buf, reg >> 1, reg & 1);
166
+}
167
+
168
+static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
169
+{
170
+ return 0; /* TODO */
171
+}
172
+
173
+static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
174
+{
175
+ ARMCPU *cpu = ARM_CPU(cs);
176
+ GString *s = g_string_new(NULL);
177
+ int base_reg = orig_base_reg;
178
+ int i;
179
+
180
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
181
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
182
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
183
+
184
+ for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
185
+ g_string_append_printf(s,
186
+ "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
187
+ m_sysreg_def[i].name, base_reg++);
188
+ g_string_append_printf(s,
189
+ "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
190
+ m_sysreg_def[i].name, base_reg++);
191
+ }
192
+
193
+ g_string_append_printf(s, "</feature>");
194
+ cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
195
+ cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
196
+
197
+ return cpu->dyn_m_secextreg_xml.num;
198
+}
199
+#endif
200
+
201
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
202
{
203
ARMCPU *cpu = ARM_CPU(cs);
204
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
205
return cpu->dyn_sysreg_xml.desc;
206
} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
207
return cpu->dyn_svereg_xml.desc;
208
+ } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
209
+ return cpu->dyn_m_systemreg_xml.desc;
210
+#ifndef CONFIG_USER_ONLY
211
+ } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
212
+ return cpu->dyn_m_secextreg_xml.desc;
213
+#endif
35
}
214
}
36
215
return NULL;
216
}
217
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
218
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
219
"system-registers.xml", 0);
220
221
+ if (arm_feature(env, ARM_FEATURE_M)) {
222
+ gdb_register_coprocessor(cs,
223
+ arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
224
+ arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
225
+ "arm-m-system.xml", 0);
226
+#ifndef CONFIG_USER_ONLY
227
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
228
+ gdb_register_coprocessor(cs,
229
+ arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
230
+ arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
231
+ "arm-m-secext.xml", 0);
232
+ }
233
+#endif
234
+ }
235
}
37
--
236
--
38
2.20.1
237
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 15/21] target/arm: Handle m-profile in arm_is_secure
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230227225832.816605-2-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/cpu.h | 3 +++
10
1 file changed, 3 insertions(+)
11
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.h
15
+++ b/target/arm/cpu.h
16
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
17
/* Return true if the processor is in secure state */
18
static inline bool arm_is_secure(CPUARMState *env)
19
{
20
+ if (arm_feature(env, ARM_FEATURE_M)) {
21
+ return env->v7m.secure;
22
+ }
23
if (arm_is_el3_or_mon(env)) {
24
return true;
25
}
26
--
27
2.34.1
diff view generated by jsdifflib
[PULL 03/16] target/arm: add spaces around operator
[PULL 16/21] target/arm: Stub arm_hcr_el2_eff for m-profile
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fix code style. Operator needs spaces both sides.
3
M-profile doesn't have HCR_EL2. While we could test features
4
before each call, zero is a generally safe return value to
5
disable the code in the caller. This test is required to
6
avoid an assert in arm_is_secure_below_el3.
4
7
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/arch_dump.c | 8 ++++----
13
target/arm/helper.c | 3 +++
12
target/arm/arm-semi.c | 8 ++++----
14
1 file changed, 3 insertions(+)
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
15
15
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/arch_dump.c
19
+++ b/target/arm/arch_dump.c
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
21
22
for (i = 0; i < 32; ++i) {
23
uint64_t *q = aa64_vfp_qreg(env, i);
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
28
}
29
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
32
*/
33
for (i = 0; i < 32; ++i) {
34
uint64_t tmp = note.vfp.vregs[2*i];
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
36
- note.vfp.vregs[2*i+1] = tmp;
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
38
+ note.vfp.vregs[2 * i + 1] = tmp;
39
}
40
}
41
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/arm-semi.c
45
+++ b/target/arm/arm-semi.c
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
47
if (use_gdb_syscalls()) {
48
arm_semi_open_guestfd = guestfd;
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
83
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/helper.c
18
--- a/target/arm/helper.c
85
+++ b/target/arm/helper.c
19
+++ b/target/arm/helper.c
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
20
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
87
uint32_t sum;
21
88
sum = do_usad(a, b);
22
uint64_t arm_hcr_el2_eff(CPUARMState *env)
89
sum += do_usad(a >> 8, b >> 8);
23
{
90
- sum += do_usad(a >> 16, b >>16);
24
+ if (arm_feature(env, ARM_FEATURE_M)) {
91
+ sum += do_usad(a >> 16, b >> 16);
25
+ return 0;
92
sum += do_usad(a >> 24, b >> 24);
26
+ }
93
return sum;
27
return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
94
}
28
}
29
95
--
30
--
96
2.20.1
31
2.34.1
97
98
diff view generated by jsdifflib
[PULL 01/16] hw/arm/Kconfig: ARM_V7M depends on PTIMER
[PULL 17/21] target/arm: Diagnose incorrect usage of arm_is_secure subroutines
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
3
In several places we use arm_is_secure_below_el3 and
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
4
arm_is_el3_or_mon separately from arm_is_secure.
5
in the build when building armv7m_systick.
5
These functions make no sense for m-profile, and
6
would indicate prior incorrect feature testing.
6
7
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
hw/arm/Kconfig | 1 +
14
target/arm/cpu.h | 5 ++++-
13
1 file changed, 1 insertion(+)
15
1 file changed, 4 insertions(+), 1 deletion(-)
14
16
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/Kconfig
19
--- a/target/arm/cpu.h
18
+++ b/hw/arm/Kconfig
20
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
21
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
20
22
void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
21
config ARM_V7M
23
22
bool
24
#if !defined(CONFIG_USER_ONLY)
23
+ select PTIMER
25
-/* Return true if exception levels below EL3 are in secure state,
24
26
+/*
25
config ALLWINNER_A10
27
+ * Return true if exception levels below EL3 are in secure state,
26
bool
28
* or would be following an exception return to that level.
29
* Unlike arm_is_secure() (which is always a question about the
30
* _current_ state of the CPU) this doesn't care about the current
31
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
32
*/
33
static inline bool arm_is_secure_below_el3(CPUARMState *env)
34
{
35
+ assert(!arm_feature(env, ARM_FEATURE_M));
36
if (arm_feature(env, ARM_FEATURE_EL3)) {
37
return !(env->cp15.scr_el3 & SCR_NS);
38
} else {
39
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
40
/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
41
static inline bool arm_is_el3_or_mon(CPUARMState *env)
42
{
43
+ assert(!arm_feature(env, ARM_FEATURE_M));
44
if (arm_feature(env, ARM_FEATURE_EL3)) {
45
if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
46
/* CPU currently in AArch64 state and EL3 */
27
--
47
--
28
2.20.1
48
2.34.1
29
49
30
50
diff view generated by jsdifflib
New patch
[PULL 18/21] target/arm: Rewrite check_s2_mmu_setup
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Integrate neighboring code from get_phys_addr_lpae which computed
4
starting level, as it is easier to validate when doing both at the
5
same time. Mirror the checks at the start of AArch{64,32}.S2Walk,
6
especially S2InvalidSL and S2InconsistentSL.
7
8
This reverts 49ba115bb74, which was incorrect -- there is nothing
9
in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
10
pseudocode is consistent in referencing PAMax.
11
12
Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
19
1 file changed, 97 insertions(+), 76 deletions(-)
20
21
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/ptw.c
24
+++ b/target/arm/ptw.c
25
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
26
* check_s2_mmu_setup
27
* @cpu: ARMCPU
28
* @is_aa64: True if the translation regime is in AArch64 state
29
- * @startlevel: Suggested starting level
30
- * @inputsize: Bitsize of IPAs
31
+ * @tcr: VTCR_EL2 or VSTCR_EL2
32
+ * @ds: Effective value of TCR.DS.
33
+ * @iasize: Bitsize of IPAs
34
* @stride: Page-table stride (See the ARM ARM)
35
*
36
- * Returns true if the suggested S2 translation parameters are OK and
37
- * false otherwise.
38
+ * Decode the starting level of the S2 lookup, returning INT_MIN if
39
+ * the configuration is invalid.
40
*/
41
-static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
42
- int inputsize, int stride, int outputsize)
43
+static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
44
+ bool ds, int iasize, int stride)
45
{
46
- const int grainsize = stride + 3;
47
- int startsizecheck;
48
-
49
- /*
50
- * Negative levels are usually not allowed...
51
- * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
52
- * begins with level -1. Note that previous feature tests will have
53
- * eliminated this combination if it is not enabled.
54
- */
55
- if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
56
- return false;
57
- }
58
-
59
- startsizecheck = inputsize - ((3 - level) * stride + grainsize);
60
- if (startsizecheck < 1 || startsizecheck > stride + 4) {
61
- return false;
62
- }
63
+ int sl0, sl2, startlevel, granulebits, levels;
64
+ int s1_min_iasize, s1_max_iasize;
65
66
+ sl0 = extract32(tcr, 6, 2);
67
if (is_aa64) {
68
+ /*
69
+ * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
70
+ * get_phys_addr_lpae, that used aa64_va_parameters which apply
71
+ * to aarch64. If Stage1 is aarch32, the min_txsz is larger.
72
+ * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
73
+ * inputsize is 64 - 24 = 40.
74
+ */
75
+ if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
76
+ goto fail;
77
+ }
78
+
79
+ /*
80
+ * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
81
+ * so interleave AArch64.S2StartLevel.
82
+ */
83
switch (stride) {
84
- case 13: /* 64KB Pages. */
85
- if (level == 0 || (level == 1 && outputsize <= 42)) {
86
- return false;
87
+ case 9: /* 4KB */
88
+ /* SL2 is RES0 unless DS=1 & 4KB granule. */
89
+ sl2 = extract64(tcr, 33, 1);
90
+ if (ds && sl2) {
91
+ if (sl0 != 0) {
92
+ goto fail;
93
+ }
94
+ startlevel = -1;
95
+ } else {
96
+ startlevel = 2 - sl0;
97
+ switch (sl0) {
98
+ case 2:
99
+ if (arm_pamax(cpu) < 44) {
100
+ goto fail;
101
+ }
102
+ break;
103
+ case 3:
104
+ if (!cpu_isar_feature(aa64_st, cpu)) {
105
+ goto fail;
106
+ }
107
+ startlevel = 3;
108
+ break;
109
+ }
110
}
111
break;
112
- case 11: /* 16KB Pages. */
113
- if (level == 0 || (level == 1 && outputsize <= 40)) {
114
- return false;
115
+ case 11: /* 16KB */
116
+ switch (sl0) {
117
+ case 2:
118
+ if (arm_pamax(cpu) < 42) {
119
+ goto fail;
120
+ }
121
+ break;
122
+ case 3:
123
+ if (!ds) {
124
+ goto fail;
125
+ }
126
+ break;
127
}
128
+ startlevel = 3 - sl0;
129
break;
130
- case 9: /* 4KB Pages. */
131
- if (level == 0 && outputsize <= 42) {
132
- return false;
133
+ case 13: /* 64KB */
134
+ switch (sl0) {
135
+ case 2:
136
+ if (arm_pamax(cpu) < 44) {
137
+ goto fail;
138
+ }
139
+ break;
140
+ case 3:
141
+ goto fail;
142
}
143
+ startlevel = 3 - sl0;
144
break;
145
default:
146
g_assert_not_reached();
147
}
148
-
149
- /* Inputsize checks. */
150
- if (inputsize > outputsize &&
151
- (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
152
- /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
153
- return false;
154
- }
155
} else {
156
- /* AArch32 only supports 4KB pages. Assert on that. */
157
+ /*
158
+ * Things are simpler for AArch32 EL2, with only 4k pages.
159
+ * There is no separate S2InvalidSL function, but AArch32.S2Walk
160
+ * begins with walkparms.sl0 in {'1x'}.
161
+ */
162
assert(stride == 9);
163
-
164
- if (level == 0) {
165
- return false;
166
+ if (sl0 >= 2) {
167
+ goto fail;
168
}
169
+ startlevel = 2 - sl0;
170
}
171
- return true;
172
+
173
+ /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */
174
+ levels = 3 - startlevel;
175
+ granulebits = stride + 3;
176
+
177
+ s1_min_iasize = levels * stride + granulebits + 1;
178
+ s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
179
+
180
+ if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
181
+ return startlevel;
182
+ }
183
+
184
+ fail:
185
+ return INT_MIN;
186
}
187
188
/**
189
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
190
*/
191
level = 4 - (inputsize - 4) / stride;
192
} else {
193
- /*
194
- * For stage 2 translations the starting level is specified by the
195
- * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
196
- */
197
- uint32_t sl0 = extract32(tcr, 6, 2);
198
- uint32_t sl2 = extract64(tcr, 33, 1);
199
- int32_t startlevel;
200
- bool ok;
201
-
202
- /* SL2 is RES0 unless DS=1 & 4kb granule. */
203
- if (param.ds && stride == 9 && sl2) {
204
- if (sl0 != 0) {
205
- level = 0;
206
- goto do_translation_fault;
207
- }
208
- startlevel = -1;
209
- } else if (!aarch64 || stride == 9) {
210
- /* AArch32 or 4KB pages */
211
- startlevel = 2 - sl0;
212
-
213
- if (cpu_isar_feature(aa64_st, cpu)) {
214
- startlevel &= 3;
215
- }
216
- } else {
217
- /* 16KB or 64KB pages */
218
- startlevel = 3 - sl0;
219
- }
220
-
221
- /* Check that the starting level is valid. */
222
- ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
223
- inputsize, stride, outputsize);
224
- if (!ok) {
225
+ int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
226
+ inputsize, stride);
227
+ if (startlevel == INT_MIN) {
228
+ level = 0;
229
goto do_translation_fault;
230
}
231
level = startlevel;
232
--
233
2.34.1
diff view generated by jsdifflib
[PULL 16/16] target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
[PULL 19/21] hw: arm: Support direct boot for Linux/arm64 EFI zboot images
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
1
From: Ard Biesheuvel <ardb@kernel.org>
2
check, except in special cases. Move a stray UNDEF check in the VTBL
3
trans function up above the access check.
4
2
3
Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
4
format, using gzip compression for the payload.
5
6
For doing EFI boot in QEMU, this is completely transparent, as the
7
firmware or bootloader will take care of this. However, for direct
8
kernel boot without firmware, we will lose the ability to boot such
9
distro kernels unless we deal with the new format directly.
10
11
EFI zboot images contain metadata in the header regarding the placement
12
of the compressed payload inside the image, and the type of compression
13
used. This means we can wire up the existing gzip support without too
14
much hassle, by parsing the header and grabbing the payload from inside
15
the loaded zboot image.
16
17
Cc: Peter Maydell <peter.maydell@linaro.org>
18
Cc: Alex Bennée <alex.bennee@linaro.org>
19
Cc: Richard Henderson <richard.henderson@linaro.org>
20
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
22
Message-id: 20230303160109.3626966-1-ardb@kernel.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
[PMM: tweaked comment formatting, fixed checkpatch nits]
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
8
---
26
---
9
target/arm/translate-neon.c.inc | 8 ++++----
27
include/hw/loader.h | 19 ++++++++++
10
1 file changed, 4 insertions(+), 4 deletions(-)
28
hw/arm/boot.c | 6 +++
29
hw/core/loader.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
30
3 files changed, 116 insertions(+)
11
31
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
32
diff --git a/include/hw/loader.h b/include/hw/loader.h
13
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate-neon.c.inc
34
--- a/include/hw/loader.h
15
+++ b/target/arm/translate-neon.c.inc
35
+++ b/include/hw/loader.h
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
36
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
17
return false;
37
uint8_t **buffer);
38
ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
39
40
+/**
41
+ * unpack_efi_zboot_image:
42
+ * @buffer: pointer to a variable holding the address of a buffer containing the
43
+ * image
44
+ * @size: pointer to a variable holding the size of the buffer
45
+ *
46
+ * Check whether the buffer contains a EFI zboot image, and if it does, extract
47
+ * the compressed payload and decompress it into a new buffer. If successful,
48
+ * the old buffer is freed, and the *buffer and size variables pointed to by the
49
+ * function arguments are updated to refer to the newly populated buffer.
50
+ *
51
+ * Returns 0 if the image could not be identified as a EFI zboot image.
52
+ * Returns -1 if the buffer contents were identified as a EFI zboot image, but
53
+ * unpacking failed for any reason.
54
+ * Returns the size of the decompressed payload if decompression was performed
55
+ * successfully.
56
+ */
57
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
58
+
59
#define ELF_LOAD_FAILED -1
60
#define ELF_LOAD_NOT_ELF -2
61
#define ELF_LOAD_WRONG_ARCH -3
62
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/hw/arm/boot.c
65
+++ b/hw/arm/boot.c
66
@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
67
return -1;
68
}
69
size = len;
70
+
71
+ /* Unpack the image if it is a EFI zboot image */
72
+ if (unpack_efi_zboot_image(&buffer, &size) < 0) {
73
+ g_free(buffer);
74
+ return -1;
75
+ }
18
}
76
}
19
77
20
- if (!vfp_access_check(s)) {
78
/* check the arm64 magic header value -- very old kernels may not have it */
21
- return true;
79
diff --git a/hw/core/loader.c b/hw/core/loader.c
22
- }
80
index XXXXXXX..XXXXXXX 100644
23
-
81
--- a/hw/core/loader.c
24
if ((a->vn + a->len + 1) > 32) {
82
+++ b/hw/core/loader.c
25
/*
83
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
84
return bytes;
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
85
}
28
return false;
86
29
}
87
+/* The PE/COFF MS-DOS stub magic number */
30
88
+#define EFI_PE_MSDOS_MAGIC "MZ"
31
+ if (!vfp_access_check(s)) {
89
+
32
+ return true;
90
+/*
91
+ * The Linux header magic number for a EFI PE/COFF
92
+ * image targetting an unspecified architecture.
93
+ */
94
+#define EFI_PE_LINUX_MAGIC "\xcd\x23\x82\x81"
95
+
96
+/*
97
+ * Bootable Linux kernel images may be packaged as EFI zboot images, which are
98
+ * self-decompressing executables when loaded via EFI. The compressed payload
99
+ * can also be extracted from the image and decompressed by a non-EFI loader.
100
+ *
101
+ * The de facto specification for this format is at the following URL:
102
+ *
103
+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
104
+ *
105
+ * This definition is based on Linux upstream commit 29636a5ce87beba.
106
+ */
107
+struct linux_efi_zboot_header {
108
+ uint8_t msdos_magic[2]; /* PE/COFF 'MZ' magic number */
109
+ uint8_t reserved0[2];
110
+ uint8_t zimg[4]; /* "zimg" for Linux EFI zboot images */
111
+ uint32_t payload_offset; /* LE offset to compressed payload */
112
+ uint32_t payload_size; /* LE size of the compressed payload */
113
+ uint8_t reserved1[8];
114
+ char compression_type[32]; /* Compression type, NUL terminated */
115
+ uint8_t linux_magic[4]; /* Linux header magic */
116
+ uint32_t pe_header_offset; /* LE offset to the PE header */
117
+};
118
+
119
+/*
120
+ * Check whether *buffer points to a Linux EFI zboot image in memory.
121
+ *
122
+ * If it does, attempt to decompress it to a new buffer, and free the old one.
123
+ * If any of this fails, return an error to the caller.
124
+ *
125
+ * If the image is not a Linux EFI zboot image, do nothing and return success.
126
+ */
127
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
128
+{
129
+ const struct linux_efi_zboot_header *header;
130
+ uint8_t *data = NULL;
131
+ int ploff, plsize;
132
+ ssize_t bytes;
133
+
134
+ /* ignore if this is too small to be a EFI zboot image */
135
+ if (*size < sizeof(*header)) {
136
+ return 0;
33
+ }
137
+ }
34
+
138
+
35
desc = tcg_const_i32((a->vn << 2) | a->len);
139
+ header = (struct linux_efi_zboot_header *)*buffer;
36
def = tcg_temp_new_i64();
140
+
37
if (a->op) {
141
+ /* ignore if this is not a Linux EFI zboot image */
142
+ if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
143
+ memcmp(&header->zimg, "zimg", 4) != 0 ||
144
+ memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
145
+ return 0;
146
+ }
147
+
148
+ if (strcmp(header->compression_type, "gzip") != 0) {
149
+ fprintf(stderr,
150
+ "unable to handle EFI zboot image with \"%.*s\" compression\n",
151
+ (int)sizeof(header->compression_type) - 1,
152
+ header->compression_type);
153
+ return -1;
154
+ }
155
+
156
+ ploff = ldl_le_p(&header->payload_offset);
157
+ plsize = ldl_le_p(&header->payload_size);
158
+
159
+ if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
160
+ fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
161
+ return -1;
162
+ }
163
+
164
+ data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
165
+ bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
166
+ if (bytes < 0) {
167
+ fprintf(stderr, "failed to decompress EFI zboot image\n");
168
+ g_free(data);
169
+ return -1;
170
+ }
171
+
172
+ g_free(*buffer);
173
+ *buffer = g_realloc(data, bytes);
174
+ *size = bytes;
175
+ return bytes;
176
+}
177
+
178
/*
179
* Functions for reboot-persistent memory regions.
180
* - used for vga bios and option roms.
38
--
181
--
39
2.20.1
182
2.34.1
40
183
41
184
diff view generated by jsdifflib
[PULL 10/16] hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
[PULL 20/21] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: qianfan Zhao <qianfanguijin@163.com>
2
2
3
The system configuration controller (SYSCFG) doesn't have
3
TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
4
any output IRQ (and the INTC input #71 belongs to the UART6).
4
register on SUN6i based SoCs, we should lower interrupt when the guest
5
Remove the invalid code.
5
set this bit.
6
6
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
7
The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
device connected on the i2c bus, next is the trace log:
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
9
10
allwinner_i2c_write write CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
11
allwinner_i2c_write write CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
12
allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
13
allwinner_i2c_read read STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
14
allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
15
allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
16
allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
17
allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE
18
allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
19
allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
20
allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
21
allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE
22
...
23
24
Fix it.
25
26
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
27
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
28
Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
31
---
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
32
include/hw/i2c/allwinner-i2c.h | 6 ++++++
14
hw/arm/stm32f205_soc.c | 1 -
33
hw/i2c/allwinner-i2c.c | 26 ++++++++++++++++++++++++--
15
hw/misc/stm32f2xx_syscfg.c | 2 --
34
2 files changed, 30 insertions(+), 2 deletions(-)
16
3 files changed, 5 deletions(-)
17
35
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
36
diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
19
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
38
--- a/include/hw/i2c/allwinner-i2c.h
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
39
+++ b/include/hw/i2c/allwinner-i2c.h
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
40
@@ -XXX,XX +XXX,XX @@
23
uint32_t syscfg_exticr3;
41
#include "qom/object.h"
24
uint32_t syscfg_exticr4;
42
25
uint32_t syscfg_cmpcr;
43
#define TYPE_AW_I2C "allwinner.i2c"
26
-
44
+
27
- qemu_irq irq;
45
+/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
46
+#define TYPE_AW_I2C_SUN6I TYPE_AW_I2C "-sun6i"
47
+
48
OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
49
50
#define AW_I2C_MEM_SIZE 0x24
51
@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
52
uint8_t srst;
53
uint8_t efr;
54
uint8_t lcr;
55
+
56
+ bool irq_clear_inverted;
28
};
57
};
29
58
30
#endif /* HW_STM32F2XX_SYSCFG_H */
59
#endif /* ALLWINNER_I2C_H */
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
60
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
32
index XXXXXXX..XXXXXXX 100644
61
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/stm32f205_soc.c
62
--- a/hw/i2c/allwinner-i2c.c
34
+++ b/hw/arm/stm32f205_soc.c
63
+++ b/hw/i2c/allwinner-i2c.c
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
64
@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
36
}
65
s->stat = STAT_FROM_STA(STAT_IDLE);
37
busdev = SYS_BUS_DEVICE(dev);
66
s->cntr &= ~TWI_CNTR_M_STP;
38
sysbus_mmio_map(busdev, 0, 0x40013800);
67
}
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
68
- if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
40
69
- /* Interrupt flag cleared */
41
/* Attach UART (uses USART registers) and USART controllers */
70
+
42
for (i = 0; i < STM_NUM_USARTS; i++) {
71
+ if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
72
+ /* Write 0 to clear this flag */
44
index XXXXXXX..XXXXXXX 100644
73
+ qemu_irq_lower(s->irq);
45
--- a/hw/misc/stm32f2xx_syscfg.c
74
+ } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
46
+++ b/hw/misc/stm32f2xx_syscfg.c
75
+ /* Write 1 to clear this flag */
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
76
+ s->cntr &= ~TWI_CNTR_INT_FLAG;
77
qemu_irq_lower(s->irq);
78
}
79
+
80
if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
81
if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
82
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
83
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
84
.class_init = allwinner_i2c_class_init,
85
};
86
87
+static void allwinner_i2c_sun6i_init(Object *obj)
88
+{
89
+ AWI2CState *s = AW_I2C(obj);
90
+
91
+ s->irq_clear_inverted = true;
92
+}
93
+
94
+static const TypeInfo allwinner_i2c_sun6i_type_info = {
95
+ .name = TYPE_AW_I2C_SUN6I,
96
+ .parent = TYPE_SYS_BUS_DEVICE,
97
+ .instance_size = sizeof(AWI2CState),
98
+ .instance_init = allwinner_i2c_sun6i_init,
99
+ .class_init = allwinner_i2c_class_init,
100
+};
101
+
102
static void allwinner_i2c_register_types(void)
48
{
103
{
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
104
type_register_static(&allwinner_i2c_type_info);
50
105
+ type_register_static(&allwinner_i2c_sun6i_type_info);
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
106
}
52
-
107
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
108
type_init(allwinner_i2c_register_types)
54
TYPE_STM32F2XX_SYSCFG, 0x400);
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
56
--
109
--
57
2.20.1
110
2.34.1
58
59
diff view generated by jsdifflib
[PULL 07/16] hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
[PULL 21/21] hw: arm: allwinner-h3: Fix and complete H3 i2c devices
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: qianfan Zhao <qianfanguijin@163.com>
2
2
3
When using a Cortex-A15, the Virt machine does not use any
3
Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
4
MPCore peripherals. Remove the dependency.
4
The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
5
control register's INT_FLAG bit.
5
6
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
7
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
8
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
hw/arm/Kconfig | 1 -
12
include/hw/arm/allwinner-h3.h | 6 ++++++
14
1 file changed, 1 deletion(-)
13
hw/arm/allwinner-h3.c | 29 +++++++++++++++++++++++++----
14
2 files changed, 31 insertions(+), 4 deletions(-)
15
15
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Kconfig
18
--- a/include/hw/arm/allwinner-h3.h
19
+++ b/hw/arm/Kconfig
19
+++ b/include/hw/arm/allwinner-h3.h
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
20
@@ -XXX,XX +XXX,XX @@ enum {
21
imply VFIO_PLATFORM
21
AW_H3_DEV_UART3,
22
imply VFIO_XGMAC
22
AW_H3_DEV_EMAC,
23
imply TPM_TIS_SYSBUS
23
AW_H3_DEV_TWI0,
24
- select A15MPCORE
24
+ AW_H3_DEV_TWI1,
25
select ACPI
25
+ AW_H3_DEV_TWI2,
26
select ARM_SMMUV3
26
AW_H3_DEV_DRAMCOM,
27
select GPIO_KEY
27
AW_H3_DEV_DRAMCTL,
28
AW_H3_DEV_DRAMPHY,
29
@@ -XXX,XX +XXX,XX @@ enum {
30
AW_H3_DEV_GIC_VCPU,
31
AW_H3_DEV_RTC,
32
AW_H3_DEV_CPUCFG,
33
+ AW_H3_DEV_R_TWI,
34
AW_H3_DEV_SDRAM
35
};
36
37
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
38
AwSidState sid;
39
AwSdHostState mmc0;
40
AWI2CState i2c0;
41
+ AWI2CState i2c1;
42
+ AWI2CState i2c2;
43
+ AWI2CState r_twi;
44
AwSun8iEmacState emac;
45
AwRtcState rtc;
46
GICState gic;
47
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/arm/allwinner-h3.c
50
+++ b/hw/arm/allwinner-h3.c
51
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
52
[AW_H3_DEV_UART2] = 0x01c28800,
53
[AW_H3_DEV_UART3] = 0x01c28c00,
54
[AW_H3_DEV_TWI0] = 0x01c2ac00,
55
+ [AW_H3_DEV_TWI1] = 0x01c2b000,
56
+ [AW_H3_DEV_TWI2] = 0x01c2b400,
57
[AW_H3_DEV_EMAC] = 0x01c30000,
58
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
59
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
60
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
61
[AW_H3_DEV_GIC_VCPU] = 0x01c86000,
62
[AW_H3_DEV_RTC] = 0x01f00000,
63
[AW_H3_DEV_CPUCFG] = 0x01f01c00,
64
+ [AW_H3_DEV_R_TWI] = 0x01f02400,
65
[AW_H3_DEV_SDRAM] = 0x40000000
66
};
67
68
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
69
{ "uart1", 0x01c28400, 1 * KiB },
70
{ "uart2", 0x01c28800, 1 * KiB },
71
{ "uart3", 0x01c28c00, 1 * KiB },
72
- { "twi1", 0x01c2b000, 1 * KiB },
73
- { "twi2", 0x01c2b400, 1 * KiB },
74
{ "scr", 0x01c2c400, 1 * KiB },
75
{ "gpu", 0x01c40000, 64 * KiB },
76
{ "hstmr", 0x01c60000, 4 * KiB },
77
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
78
{ "r_prcm", 0x01f01400, 1 * KiB },
79
{ "r_twd", 0x01f01800, 1 * KiB },
80
{ "r_cir-rx", 0x01f02000, 1 * KiB },
81
- { "r_twi", 0x01f02400, 1 * KiB },
82
{ "r_uart", 0x01f02800, 1 * KiB },
83
{ "r_pio", 0x01f02c00, 1 * KiB },
84
{ "r_pwm", 0x01f03800, 1 * KiB },
85
@@ -XXX,XX +XXX,XX @@ enum {
86
AW_H3_GIC_SPI_UART2 = 2,
87
AW_H3_GIC_SPI_UART3 = 3,
88
AW_H3_GIC_SPI_TWI0 = 6,
89
+ AW_H3_GIC_SPI_TWI1 = 7,
90
+ AW_H3_GIC_SPI_TWI2 = 8,
91
AW_H3_GIC_SPI_TIMER0 = 18,
92
AW_H3_GIC_SPI_TIMER1 = 19,
93
+ AW_H3_GIC_SPI_R_TWI = 44,
94
AW_H3_GIC_SPI_MMC0 = 60,
95
AW_H3_GIC_SPI_EHCI0 = 72,
96
AW_H3_GIC_SPI_OHCI0 = 73,
97
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
98
99
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
100
101
- object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
102
+ object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
103
+ object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I);
104
+ object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I);
105
+ object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
106
}
107
108
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
109
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
110
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
111
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
112
113
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
114
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
115
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
116
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
117
+
118
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
119
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
120
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
121
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
122
+
123
+ sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
124
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
125
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
126
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
127
+
128
/* Unimplemented devices */
129
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
130
create_unimplemented_device(unimplemented[i].device_name,
28
--
131
--
29
2.20.1
132
2.34.1
30
31
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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