1
Patches for rc1: nothing major, just some minor bugfixes and
1
The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:
2
code cleanups.
3
2
4
-- PMM
3
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)
5
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
7
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
9
4
10
are available in the Git repository at:
5
are available in the Git repository at:
11
6
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216
13
8
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
9
for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:
15
10
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
11
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
15
* Some mostly M-profile-related code cleanups
21
* Minor coding style fixes
16
* avocado: Retire the boot_linux.py AArch64 TCG tests
22
* docs: add some notes on the sbsa-ref machine
17
* hw/arm/smmuv3: Add GBPA register
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
18
* arm/virt: don't try to spell out the accelerator
24
* target/arm: Fix neon VTBL/VTBX for len > 1
19
* hw/arm: Attach PSPI module to NPCM7XX SoC
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
20
* Some cleanup/refactoring patches aiming towards
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
21
allowing building Arm targets without CONFIG_TCG
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
30
* hw/arm/nseries: Check return value from load_image_targphys()
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
33
22
34
----------------------------------------------------------------
23
----------------------------------------------------------------
35
Alex Bennée (1):
24
Alex Bennée (1):
36
docs: add some notes on the sbsa-ref machine
25
tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
37
26
38
AlexChen (1):
27
Claudio Fontana (3):
39
ssi: Fix bad printf format specifiers
28
target/arm: rename handle_semihosting to tcg_handle_semihosting
29
target/arm: wrap psci call with tcg_enabled
30
target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
40
31
41
Andrew Jones (1):
32
Cornelia Huck (1):
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
33
arm/virt: don't try to spell out the accelerator
43
34
44
Havard Skinnemoen (1):
35
Fabiano Rosas (7):
45
tests/qtest/npcm7xx_rng-test: count runs properly
36
target/arm: Move PC alignment check
37
target/arm: Move cpregs code out of cpu.h
38
tests/avocado: Skip tests that require a missing accelerator
39
tests/avocado: Tag TCG tests with accel:tcg
40
target/arm: Use "max" as default cpu for the virt machine with KVM
41
tests/qtest: arm-cpu-features: Match tests to required accelerators
42
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
46
43
47
Peter Maydell (2):
44
Hao Wu (3):
48
hw/arm/nseries: Check return value from load_image_targphys()
45
MAINTAINERS: Add myself to maintainers and remove Havard
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
46
hw/ssi: Add Nuvoton PSPI Module
47
hw/arm: Attach PSPI module to NPCM7XX SoC
50
48
51
Philippe Mathieu-Daudé (6):
49
Jean-Philippe Brucker (2):
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
50
hw/arm/smmu-common: Support 64-bit addresses
53
hw/arm/armsse: Correct expansion MPC interrupt lines
51
hw/arm/smmu-common: Fix TTB1 handling
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
58
52
59
Richard Henderson (1):
53
Mostafa Saleh (1):
60
target/arm: Fix neon VTBL/VTBX for len > 1
54
hw/arm/smmuv3: Add GBPA register
61
55
62
Xinhao Zhang (3):
56
Philippe Mathieu-Daudé (12):
63
target/arm: add spaces around operator
57
hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
64
target/arm: Don't use '#' flag of printf format
58
target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
65
target/arm: add space before the open parenthesis '('
59
target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
60
target/arm: Constify ID_PFR1 on user emulation
61
target/arm: Convert CPUARMState::eabi to boolean
62
target/arm: Avoid resetting CPUARMState::eabi field
63
target/arm: Restrict CPUARMState::gicv3state to sysemu
64
target/arm: Restrict CPUARMState::arm_boot_info to sysemu
65
target/arm: Restrict CPUARMState::nvic to sysemu
66
target/arm: Store CPUARMState::nvic as NVICState*
67
target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
68
hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
66
69
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
70
MAINTAINERS | 8 +-
68
docs/system/target-arm.rst | 1 +
71
docs/system/arm/nuvoton.rst | 2 +-
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
72
hw/arm/smmuv3-internal.h | 7 +
70
target/arm/helper.h | 2 +-
73
include/hw/arm/npcm7xx.h | 2 +
71
hw/arm/armsse.c | 3 +-
74
include/hw/arm/smmu-common.h | 2 -
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
75
include/hw/arm/smmuv3.h | 1 +
73
hw/arm/nseries.c | 26 ++++++++----------
76
include/hw/intc/armv7m_nvic.h | 128 +++++++++++++++++-
74
hw/arm/stm32f205_soc.c | 1 -
77
include/hw/ssi/npcm_pspi.h | 53 ++++++++
75
hw/misc/stm32f2xx_syscfg.c | 2 --
78
linux-user/user-internals.h | 2 +-
76
hw/ssi/imx_spi.c | 2 +-
79
target/arm/cpregs.h | 98 ++++++++++++++
77
hw/ssi/xilinx_spi.c | 2 +-
80
target/arm/cpu.h | 228 ++-------------------------------
78
target/arm/arch_dump.c | 8 +++---
81
target/arm/internals.h | 14 --
79
target/arm/arm-semi.c | 8 +++---
82
hw/arm/npcm7xx.c | 25 +++-
80
target/arm/helper.c | 2 +-
83
hw/arm/smmu-common.c | 4 +-
81
target/arm/op_helper.c | 23 +++++++++-------
84
hw/arm/smmuv3.c | 43 ++++++-
82
target/arm/translate-a64.c | 4 +--
85
hw/arm/virt.c | 10 +-
83
target/arm/translate.c | 2 +-
86
hw/intc/armv7m_nvic.c | 38 ++----
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
87
hw/ssi/npcm_pspi.c | 221 ++++++++++++++++++++++++++++++++
85
hw/arm/Kconfig | 3 +-
88
linux-user/arm/cpu_loop.c | 4 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
89
target/arm/cpu.c | 5 +-
87
20 files changed, 123 insertions(+), 98 deletions(-)
90
target/arm/cpu_tcg.c | 3 +
88
create mode 100644 docs/system/arm/sbsa.rst
91
target/arm/helper.c | 31 +++--
92
target/arm/m_helper.c | 86 +++++++------
93
target/arm/machine.c | 18 +--
94
tests/qtest/arm-cpu-features.c | 28 ++--
95
hw/arm/Kconfig | 1 +
96
hw/ssi/meson.build | 2 +-
97
hw/ssi/trace-events | 5 +
98
tests/avocado/avocado_qemu/__init__.py | 4 +
99
tests/avocado/boot_linux.py | 48 ++-----
100
tests/avocado/boot_linux_console.py | 1 +
101
tests/avocado/machine_aarch64_virt.py | 63 ++++++++-
102
tests/avocado/reverse_debugging.py | 8 ++
103
tests/qtest/meson.build | 4 +-
104
34 files changed, 798 insertions(+), 399 deletions(-)
105
create mode 100644 include/hw/ssi/npcm_pspi.h
106
create mode 100644 hw/ssi/npcm_pspi.c
89
107
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
4
similarly to automatic conversion from commit 8063396bf3
5
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230206223502.25122-2-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/intc/armv7m_nvic.h | 5 +----
13
1 file changed, 1 insertion(+), 4 deletions(-)
14
15
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/intc/armv7m_nvic.h
18
+++ b/include/hw/intc/armv7m_nvic.h
19
@@ -XXX,XX +XXX,XX @@
20
#include "qom/object.h"
21
22
#define TYPE_NVIC "armv7m_nvic"
23
-
24
-typedef struct NVICState NVICState;
25
-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
26
- TYPE_NVIC)
27
+OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
28
29
/* Highest permitted number of exceptions (architectural limit) */
30
#define NVIC_MAX_VECTORS 512
31
--
32
2.34.1
33
34
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230206223502.25122-3-philmd@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/m_helper.c | 11 ++++++++---
10
1 file changed, 8 insertions(+), 3 deletions(-)
11
12
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/m_helper.c
15
+++ b/target/arm/m_helper.c
16
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
17
return 0;
18
}
19
20
-#else
21
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
22
+{
23
+ return ARMMMUIdx_MUser;
24
+}
25
+
26
+#else /* !CONFIG_USER_ONLY */
27
28
/*
29
* What kind of stack write are we doing? This affects how exceptions
30
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
31
return tt_resp;
32
}
33
34
-#endif /* !CONFIG_USER_ONLY */
35
-
36
ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
37
bool secstate, bool priv, bool negpri)
38
{
39
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
40
41
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
42
}
43
+
44
+#endif /* !CONFIG_USER_ONLY */
45
--
46
2.34.1
47
48
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
3
arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
4
OMAP2 chip support") takes care of creating the 3 UARTs.
4
are only used for system emulation in m_helper.c.
5
Move the definitions to avoid prototype forward declarations.
5
6
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
which create the UART and connects it to an IRQ output,
9
Message-id: 20230206223502.25122-4-philmd@linaro.org
9
overwritting the existing peripheral and its IRQ connection.
10
This is incorrect.
11
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
16
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
11
---
22
hw/arm/nseries.c | 11 -----------
12
target/arm/internals.h | 14 --------
23
1 file changed, 11 deletions(-)
13
target/arm/m_helper.c | 74 +++++++++++++++++++++---------------------
14
2 files changed, 37 insertions(+), 51 deletions(-)
24
15
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
26
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/nseries.c
18
--- a/target/arm/internals.h
28
+++ b/hw/arm/nseries.c
19
+++ b/target/arm/internals.h
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
20
@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
21
22
int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
23
24
-/*
25
- * Return the MMU index for a v7M CPU with all relevant information
26
- * manually specified.
27
- */
28
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
29
- bool secstate, bool priv, bool negpri);
30
-
31
-/*
32
- * Return the MMU index for a v7M CPU in the specified security and
33
- * privilege state.
34
- */
35
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
36
- bool secstate, bool priv);
37
-
38
/* Return the MMU index for a v7M CPU in the specified security state */
39
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
40
41
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/m_helper.c
44
+++ b/target/arm/m_helper.c
45
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
46
47
#else /* !CONFIG_USER_ONLY */
48
49
+static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
50
+ bool secstate, bool priv, bool negpri)
51
+{
52
+ ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
53
+
54
+ if (priv) {
55
+ mmu_idx |= ARM_MMU_IDX_M_PRIV;
56
+ }
57
+
58
+ if (negpri) {
59
+ mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
60
+ }
61
+
62
+ if (secstate) {
63
+ mmu_idx |= ARM_MMU_IDX_M_S;
64
+ }
65
+
66
+ return mmu_idx;
67
+}
68
+
69
+static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
70
+ bool secstate, bool priv)
71
+{
72
+ bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
73
+
74
+ return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
75
+}
76
+
77
+/* Return the MMU index for a v7M CPU in the specified security state */
78
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
79
+{
80
+ bool priv = arm_v7m_is_handler_mode(env) ||
81
+ !(env->v7m.control[secstate] & 1);
82
+
83
+ return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
84
+}
85
+
86
/*
87
* What kind of stack write are we doing? This affects how exceptions
88
* generated during the stacking are treated.
89
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
90
return tt_resp;
31
}
91
}
32
92
33
-static void n8x0_uart_setup(struct n800_s *s)
93
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
94
- bool secstate, bool priv, bool negpri)
34
-{
95
-{
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
96
- ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
36
- /*
97
-
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
98
- if (priv) {
38
- * here, but this code has been removed with the bluetooth backend.
99
- mmu_idx |= ARM_MMU_IDX_M_PRIV;
39
- */
100
- }
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
101
-
102
- if (negpri) {
103
- mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
104
- }
105
-
106
- if (secstate) {
107
- mmu_idx |= ARM_MMU_IDX_M_S;
108
- }
109
-
110
- return mmu_idx;
41
-}
111
-}
42
-
112
-
43
static void n8x0_usb_setup(struct n800_s *s)
113
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
44
{
114
- bool secstate, bool priv)
45
SysBusDevice *dev;
115
-{
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
116
- bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
47
n8x0_spi_setup(s);
117
-
48
n8x0_dss_setup(s);
118
- return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
49
n8x0_cbus_setup(s);
119
-}
50
- n8x0_uart_setup(s);
120
-
51
if (machine_usb(machine)) {
121
-/* Return the MMU index for a v7M CPU in the specified security state */
52
n8x0_usb_setup(s);
122
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
53
}
123
-{
124
- bool priv = arm_v7m_is_handler_mode(env) ||
125
- !(env->v7m.control[secstate] & 1);
126
-
127
- return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
128
-}
129
-
130
#endif /* !CONFIG_USER_ONLY */
54
--
131
--
55
2.20.1
132
2.34.1
56
133
57
134
diff view generated by jsdifflib
1
From: AlexChen <alex.chen@huawei.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
We should use printf format specifier "%u" instead of "%d" for
3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
argument of type "unsigned int".
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
5
Message-id: 20230206223502.25122-5-philmd@linaro.org
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 5FA280F5.8060902@huawei.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
hw/ssi/imx_spi.c | 2 +-
8
target/arm/helper.c | 12 ++++++++++--
13
hw/ssi/xilinx_spi.c | 2 +-
9
1 file changed, 10 insertions(+), 2 deletions(-)
14
2 files changed, 2 insertions(+), 2 deletions(-)
15
10
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/imx_spi.c
13
--- a/target/arm/helper.c
19
+++ b/hw/ssi/imx_spi.c
14
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
15
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
21
case ECSPI_MSGDATA:
22
return "ECSPI_MSGDATA";
23
default:
24
- sprintf(unknown, "%d ?", reg);
25
+ sprintf(unknown, "%u ?", reg);
26
return unknown;
27
}
16
}
28
}
17
}
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
18
30
index XXXXXXX..XXXXXXX 100644
19
+#ifndef CONFIG_USER_ONLY
31
--- a/hw/ssi/xilinx_spi.c
20
/*
32
+++ b/hw/ssi/xilinx_spi.c
21
* We don't know until after realize whether there's a GICv3
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
22
* attached, and that is what registers the gicv3 sysregs.
34
irq chain unless things really changed. */
23
@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
35
if (pending != s->irqline) {
24
return pfr1;
36
s->irqline = pending;
25
}
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
26
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
27
-#ifndef CONFIG_USER_ONLY
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
28
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
40
qemu_set_irq(s->irq, pending);
29
{
41
}
30
ARMCPU *cpu = env_archcpu(env);
31
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
32
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
33
.access = PL1_R, .type = ARM_CP_NO_RAW,
34
.accessfn = access_aa32_tid3,
35
+#ifdef CONFIG_USER_ONLY
36
+ .type = ARM_CP_CONST,
37
+ .resetvalue = cpu->isar.id_pfr1,
38
+#else
39
+ .type = ARM_CP_NO_RAW,
40
+ .accessfn = access_aa32_tid3,
41
.readfn = id_pfr1_read,
42
- .writefn = arm_cp_write_ignore },
43
+ .writefn = arm_cp_write_ignore
44
+#endif
45
+ },
46
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
47
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
48
.access = PL1_R, .type = ARM_CP_CONST,
42
--
49
--
43
2.20.1
50
2.34.1
44
51
45
52
diff view generated by jsdifflib
1
From: Havard Skinnemoen <hskinnemoen@google.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
3
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
4
plus one. Currently, it's counting the number of times these transitions
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
do _not_ happen, plus one.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
6
Message-id: 20230206223502.25122-6-philmd@linaro.org
7
Source:
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
9
section 2.3.4 point (3).
10
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
8
---
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
9
linux-user/user-internals.h | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
10
target/arm/cpu.h | 2 +-
11
linux-user/arm/cpu_loop.c | 4 ++--
12
3 files changed, 4 insertions(+), 4 deletions(-)
18
13
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
14
diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/tests/qtest/npcm7xx_rng-test.c
16
--- a/linux-user/user-internals.h
22
+++ b/tests/qtest/npcm7xx_rng-test.c
17
+++ b/linux-user/user-internals.h
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
18
@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
24
pi = (double)nr_ones / nr_bits;
19
#ifdef TARGET_ARM
25
20
static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
26
for (k = 0; k < nr_bits - 1; k++) {
21
{
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
22
- return cpu_env->eabi == 1;
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
23
+ return cpu_env->eabi;
29
}
24
}
30
vn_obs += 1;
25
#elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
26
static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
27
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu.h
30
+++ b/target/arm/cpu.h
31
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
32
33
#if defined(CONFIG_USER_ONLY)
34
/* For usermode syscall translation. */
35
- int eabi;
36
+ bool eabi;
37
#endif
38
39
struct CPUBreakpoint *cpu_breakpoint[16];
40
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/linux-user/arm/cpu_loop.c
43
+++ b/linux-user/arm/cpu_loop.c
44
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
45
break;
46
case EXCP_SWI:
47
{
48
- env->eabi = 1;
49
+ env->eabi = true;
50
/* system call */
51
if (env->thumb) {
52
/* Thumb is always EABI style with syscall number in r7 */
53
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
54
* > 0xfffff and are handled below as out-of-range.
55
*/
56
n ^= ARM_SYSCALL_BASE;
57
- env->eabi = 0;
58
+ env->eabi = false;
59
}
60
}
31
61
32
--
62
--
33
2.20.1
63
2.34.1
34
64
35
65
diff view generated by jsdifflib
1
The nseries machines have a codepath that allows them to load a
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
secondary bootloader. This code wasn't checking that the
3
load_image_targphys() succeeded. Check the return value and report
4
the error to the user.
5
2
6
While we're in the vicinity, fix the comment style of the
3
Although the 'eabi' field is only used in user emulation where
7
comment documenting what this image load is doing.
4
CPU reset doesn't occur, it doesn't belong to the area to reset.
5
Move it after the 'end_reset_fields' for consistency.
8
6
9
Fixes: Coverity CID 1192904
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20230206223502.25122-7-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
13
---
11
---
14
hw/arm/nseries.c | 15 +++++++++++----
12
target/arm/cpu.h | 9 ++++-----
15
1 file changed, 11 insertions(+), 4 deletions(-)
13
1 file changed, 4 insertions(+), 5 deletions(-)
16
14
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/nseries.c
17
--- a/target/arm/cpu.h
20
+++ b/hw/arm/nseries.c
18
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
19
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
22
/* No, wait, better start at the ROM. */
20
ARMVectorReg zarray[ARM_MAX_VQ * 16];
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
21
#endif
24
22
25
- /* This is intended for loading the `secondary.bin' program from
23
-#if defined(CONFIG_USER_ONLY)
26
+ /*
24
- /* For usermode syscall translation. */
27
+ * This is intended for loading the `secondary.bin' program from
25
- bool eabi;
28
* Nokia images (the NOLO bootloader). The entry point seems
26
-#endif
29
* to be at OMAP2_Q2_BASE + 0x400000.
27
-
30
*
28
struct CPUBreakpoint *cpu_breakpoint[16];
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
29
struct CPUWatchpoint *cpu_watchpoint[16];
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
30
33
*
31
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
34
* The code above is for loading the `zImage' file from Nokia
32
const struct arm_boot_info *boot_info;
35
- * images. */
33
/* Store GICv3CPUState to access from this struct */
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
34
void *gicv3state;
37
- machine->ram_size - 0x400000);
35
+#if defined(CONFIG_USER_ONLY)
38
+ * images.
36
+ /* For usermode syscall translation. */
39
+ */
37
+ bool eabi;
40
+ if (load_image_targphys(option_rom[0].name,
38
+#endif /* CONFIG_USER_ONLY */
41
+ OMAP2_Q2_BASE + 0x400000,
39
42
+ machine->ram_size - 0x400000) < 0) {
40
#ifdef TARGET_TAGGED_ADDRESSES
43
+ error_report("Failed to load secondary bootloader %s",
41
/* Linux syscall tagged address support */
44
+ option_rom[0].name);
45
+ exit(EXIT_FAILURE);
46
+ }
47
48
n800_setup_nolo_tags(nolo_tags);
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
50
--
42
--
51
2.20.1
43
2.34.1
52
44
53
45
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
We don't need to fill the full pic[] array if we only use
3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
when necessary.
5
Message-id: 20230206223502.25122-8-philmd@linaro.org
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
hw/arm/musicpal.c | 25 +++++++++++++------------
8
target/arm/cpu.h | 3 ++-
13
1 file changed, 13 insertions(+), 12 deletions(-)
9
1 file changed, 2 insertions(+), 1 deletion(-)
14
10
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/musicpal.c
13
--- a/target/arm/cpu.h
18
+++ b/hw/arm/musicpal.c
14
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
15
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
20
static void musicpal_init(MachineState *machine)
16
21
{
17
void *nvic;
22
ARMCPU *cpu;
18
const struct arm_boot_info *boot_info;
23
- qemu_irq pic[32];
19
+#if !defined(CONFIG_USER_ONLY)
24
DeviceState *dev;
20
/* Store GICv3CPUState to access from this struct */
25
+ DeviceState *pic;
21
void *gicv3state;
26
DeviceState *uart_orgate;
22
-#if defined(CONFIG_USER_ONLY)
27
DeviceState *i2c_dev;
23
+#else /* CONFIG_USER_ONLY */
28
DeviceState *lcd_dev;
24
/* For usermode syscall translation. */
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
25
bool eabi;
30
&error_fatal);
26
#endif /* CONFIG_USER_ONLY */
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
32
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
36
- for (i = 0; i < 32; i++) {
37
- pic[i] = qdev_get_gpio_in(dev, i);
38
- }
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
41
- pic[MP_TIMER4_IRQ], NULL);
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
47
48
/* Logically OR both UART IRQs together */
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
55
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
57
qdev_get_gpio_in(uart_orgate, 0),
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
59
OBJECT(get_system_memory()), &error_fatal);
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
65
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
67
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
69
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
71
- pic[MP_GPIO_IRQ]);
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
75
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
77
NULL);
78
sysbus_realize_and_unref(s, &error_fatal);
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
82
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
85
--
27
--
86
2.20.1
28
2.34.1
87
29
88
30
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
The MusicPal board code connects both of the IRQ outputs of the UART
3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
to the same input is not valid as it produces subtly wrong behaviour
5
Message-id: 20230206223502.25122-9-philmd@linaro.org
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
9
10
This kind of wiring needs an explicitly created OR gate; add one.
11
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
7
---
18
hw/arm/musicpal.c | 17 +++++++++++++----
8
target/arm/cpu.h | 2 +-
19
hw/arm/Kconfig | 1 +
9
1 file changed, 1 insertion(+), 1 deletion(-)
20
2 files changed, 14 insertions(+), 4 deletions(-)
21
10
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/musicpal.c
13
--- a/target/arm/cpu.h
25
+++ b/hw/arm/musicpal.c
14
+++ b/target/arm/cpu.h
26
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
27
#include "ui/console.h"
16
} sau;
28
#include "hw/i2c/i2c.h"
17
29
#include "hw/irq.h"
18
void *nvic;
30
+#include "hw/or-irq.h"
19
- const struct arm_boot_info *boot_info;
31
#include "hw/audio/wm8750.h"
20
#if !defined(CONFIG_USER_ONLY)
32
#include "sysemu/block-backend.h"
21
+ const struct arm_boot_info *boot_info;
33
#include "sysemu/runstate.h"
22
/* Store GICv3CPUState to access from this struct */
34
@@ -XXX,XX +XXX,XX @@
23
void *gicv3state;
35
#define MP_TIMER4_IRQ 7
24
#else /* CONFIG_USER_ONLY */
36
#define MP_EHCI_IRQ 8
37
#define MP_ETH_IRQ 9
38
-#define MP_UART1_IRQ 11
39
-#define MP_UART2_IRQ 11
40
+#define MP_UART_SHARED_IRQ 11
41
#define MP_GPIO_IRQ 12
42
#define MP_RTC_IRQ 28
43
#define MP_AUDIO_IRQ 30
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
45
ARMCPU *cpu;
46
qemu_irq pic[32];
47
DeviceState *dev;
48
+ DeviceState *uart_orgate;
49
DeviceState *i2c_dev;
50
DeviceState *lcd_dev;
51
DeviceState *key_dev;
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
54
pic[MP_TIMER4_IRQ], NULL);
55
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
57
+ /* Logically OR both UART IRQs together */
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
62
+
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
64
+ qdev_get_gpio_in(uart_orgate, 0),
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
68
+ qdev_get_gpio_in(uart_orgate, 1),
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
70
71
/* Register flash */
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/arm/Kconfig
75
+++ b/hw/arm/Kconfig
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
77
78
config MUSICPAL
79
bool
80
+ select OR_IRQ
81
select BITBANG_I2C
82
select MARVELL_88W8618
83
select PTIMER
84
--
25
--
85
2.20.1
26
2.34.1
86
27
87
28
diff view generated by jsdifflib
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Fix code style. Space required before the open parenthesis '('.
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
5
Message-id: 20230206223502.25122-10-philmd@linaro.org
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
target/arm/translate.c | 2 +-
8
target/arm/cpu.h | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
9
1 file changed, 1 insertion(+), 1 deletion(-)
13
10
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
13
--- a/target/arm/cpu.h
17
+++ b/target/arm/translate.c
14
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
15
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
19
- Hardware watchpoints.
16
uint32_t ctrl;
20
Hardware breakpoints have already been handled and skip this code.
17
} sau;
21
*/
18
22
- switch(dc->base.is_jmp) {
19
- void *nvic;
23
+ switch (dc->base.is_jmp) {
20
#if !defined(CONFIG_USER_ONLY)
24
case DISAS_NEXT:
21
+ void *nvic;
25
case DISAS_TOO_MANY:
22
const struct arm_boot_info *boot_info;
26
gen_goto_tb(dc, 1, dc->base.pc_next);
23
/* Store GICv3CPUState to access from this struct */
24
void *gicv3state;
27
--
25
--
28
2.20.1
26
2.34.1
29
27
30
28
diff view generated by jsdifflib
New patch
1
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
3
There is no point in using a void pointer to access the NVIC.
4
Use the real type to avoid casting it while debugging.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230206223502.25122-11-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 46 ++++++++++++++++++++++---------------------
12
hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
13
target/arm/cpu.c | 1 +
14
target/arm/m_helper.c | 2 +-
15
4 files changed, 39 insertions(+), 48 deletions(-)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
22
23
typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
24
25
+typedef struct NVICState NVICState;
26
+
27
typedef struct CPUArchState {
28
/* Regs for current mode. */
29
uint32_t regs[16];
30
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
31
} sau;
32
33
#if !defined(CONFIG_USER_ONLY)
34
- void *nvic;
35
+ NVICState *nvic;
36
const struct arm_boot_info *boot_info;
37
/* Store GICv3CPUState to access from this struct */
38
void *gicv3state;
39
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
40
41
/* Interface between CPU and Interrupt controller. */
42
#ifndef CONFIG_USER_ONLY
43
-bool armv7m_nvic_can_take_pending_exception(void *opaque);
44
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
45
#else
46
-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
47
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
48
{
49
return true;
50
}
51
#endif
52
/**
53
* armv7m_nvic_set_pending: mark the specified exception as pending
54
- * @opaque: the NVIC
55
+ * @s: the NVIC
56
* @irq: the exception number to mark pending
57
* @secure: false for non-banked exceptions or for the nonsecure
58
* version of a banked exception, true for the secure version of a banked
59
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
60
* if @secure is true and @irq does not specify one of the fixed set
61
* of architecturally banked exceptions.
62
*/
63
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
64
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
65
/**
66
* armv7m_nvic_set_pending_derived: mark this derived exception as pending
67
- * @opaque: the NVIC
68
+ * @s: the NVIC
69
* @irq: the exception number to mark pending
70
* @secure: false for non-banked exceptions or for the nonsecure
71
* version of a banked exception, true for the secure version of a banked
72
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
73
* exceptions (exceptions generated in the course of trying to take
74
* a different exception).
75
*/
76
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
77
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
78
/**
79
* armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
80
- * @opaque: the NVIC
81
+ * @s: the NVIC
82
* @irq: the exception number to mark pending
83
* @secure: false for non-banked exceptions or for the nonsecure
84
* version of a banked exception, true for the secure version of a banked
85
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
86
* Similar to armv7m_nvic_set_pending(), but specifically for exceptions
87
* generated in the course of lazy stacking of FP registers.
88
*/
89
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
90
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
91
/**
92
* armv7m_nvic_get_pending_irq_info: return highest priority pending
93
* exception, and whether it targets Secure state
94
- * @opaque: the NVIC
95
+ * @s: the NVIC
96
* @pirq: set to pending exception number
97
* @ptargets_secure: set to whether pending exception targets Secure
98
*
99
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
100
* to true if the current highest priority pending exception should
101
* be taken to Secure state, false for NS.
102
*/
103
-void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
104
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
105
bool *ptargets_secure);
106
/**
107
* armv7m_nvic_acknowledge_irq: make highest priority pending exception active
108
- * @opaque: the NVIC
109
+ * @s: the NVIC
110
*
111
* Move the current highest priority pending exception from the pending
112
* state to the active state, and update v7m.exception to indicate that
113
* it is the exception currently being handled.
114
*/
115
-void armv7m_nvic_acknowledge_irq(void *opaque);
116
+void armv7m_nvic_acknowledge_irq(NVICState *s);
117
/**
118
* armv7m_nvic_complete_irq: complete specified interrupt or exception
119
- * @opaque: the NVIC
120
+ * @s: the NVIC
121
* @irq: the exception number to complete
122
* @secure: true if this exception was secure
123
*
124
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
125
* 0 if there is still an irq active after this one was completed
126
* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
127
*/
128
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
129
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
130
/**
131
* armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
132
- * @opaque: the NVIC
133
+ * @s: the NVIC
134
* @irq: the exception number to mark pending
135
* @secure: false for non-banked exceptions or for the nonsecure
136
* version of a banked exception, true for the secure version of a banked
137
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
138
* interrupt the current execution priority. This controls whether the
139
* RDY bit for it in the FPCCR is set.
140
*/
141
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
142
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
143
/**
144
* armv7m_nvic_raw_execution_priority: return the raw execution priority
145
- * @opaque: the NVIC
146
+ * @s: the NVIC
147
*
148
* Returns: the raw execution priority as defined by the v8M architecture.
149
* This is the execution priority minus the effects of AIRCR.PRIS,
150
* and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
151
* (v8M ARM ARM I_PKLD.)
152
*/
153
-int armv7m_nvic_raw_execution_priority(void *opaque);
154
+int armv7m_nvic_raw_execution_priority(NVICState *s);
155
/**
156
* armv7m_nvic_neg_prio_requested: return true if the requested execution
157
* priority is negative for the specified security state.
158
- * @opaque: the NVIC
159
+ * @s: the NVIC
160
* @secure: the security state to test
161
* This corresponds to the pseudocode IsReqExecPriNeg().
162
*/
163
#ifndef CONFIG_USER_ONLY
164
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
165
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
166
#else
167
-static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
168
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
169
{
170
return false;
171
}
172
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
173
index XXXXXXX..XXXXXXX 100644
174
--- a/hw/intc/armv7m_nvic.c
175
+++ b/hw/intc/armv7m_nvic.c
176
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
177
return MIN(running, s->exception_prio);
178
}
179
180
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
181
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
182
{
183
/* Return true if the requested execution priority is negative
184
* for the specified security state, ie that security state
185
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
186
* mean we don't allow FAULTMASK_NS to actually make the execution
187
* priority negative). Compare pseudocode IsReqExcPriNeg().
188
*/
189
- NVICState *s = opaque;
190
-
191
if (s->cpu->env.v7m.faultmask[secure]) {
192
return true;
193
}
194
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
195
return false;
196
}
197
198
-bool armv7m_nvic_can_take_pending_exception(void *opaque)
199
+bool armv7m_nvic_can_take_pending_exception(NVICState *s)
200
{
201
- NVICState *s = opaque;
202
-
203
return nvic_exec_prio(s) > nvic_pending_prio(s);
204
}
205
206
-int armv7m_nvic_raw_execution_priority(void *opaque)
207
+int armv7m_nvic_raw_execution_priority(NVICState *s)
208
{
209
- NVICState *s = opaque;
210
-
211
return s->exception_prio;
212
}
213
214
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
215
* if @secure is true and @irq does not specify one of the fixed set
216
* of architecturally banked exceptions.
217
*/
218
-static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
219
+static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
220
{
221
- NVICState *s = (NVICState *)opaque;
222
VecInfo *vec;
223
224
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
225
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
226
}
227
}
228
229
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
230
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
231
{
232
- do_armv7m_nvic_set_pending(opaque, irq, secure, false);
233
+ do_armv7m_nvic_set_pending(s, irq, secure, false);
234
}
235
236
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
237
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
238
{
239
- do_armv7m_nvic_set_pending(opaque, irq, secure, true);
240
+ do_armv7m_nvic_set_pending(s, irq, secure, true);
241
}
242
243
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
244
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
245
{
246
/*
247
* Pend an exception during lazy FP stacking. This differs
248
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
249
* whether we should escalate depends on the saved context
250
* in the FPCCR register, not on the current state of the CPU/NVIC.
251
*/
252
- NVICState *s = (NVICState *)opaque;
253
bool banked = exc_is_banked(irq);
254
VecInfo *vec;
255
bool targets_secure;
256
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
257
}
258
259
/* Make pending IRQ active. */
260
-void armv7m_nvic_acknowledge_irq(void *opaque)
261
+void armv7m_nvic_acknowledge_irq(NVICState *s)
262
{
263
- NVICState *s = (NVICState *)opaque;
264
CPUARMState *env = &s->cpu->env;
265
const int pending = s->vectpending;
266
const int running = nvic_exec_prio(s);
267
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
268
exc_targets_secure(s, s->vectpending);
269
}
270
271
-void armv7m_nvic_get_pending_irq_info(void *opaque,
272
+void armv7m_nvic_get_pending_irq_info(NVICState *s,
273
int *pirq, bool *ptargets_secure)
274
{
275
- NVICState *s = (NVICState *)opaque;
276
const int pending = s->vectpending;
277
bool targets_secure;
278
279
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
280
*pirq = pending;
281
}
282
283
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
284
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
285
{
286
- NVICState *s = (NVICState *)opaque;
287
VecInfo *vec = NULL;
288
int ret = 0;
289
290
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
291
return ret;
292
}
293
294
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
295
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
296
{
297
/*
298
* Return whether an exception is "ready", i.e. it is enabled and is
299
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
300
* for non-banked exceptions secure is always false; for banked exceptions
301
* it indicates which of the exceptions is required.
302
*/
303
- NVICState *s = (NVICState *)opaque;
304
bool banked = exc_is_banked(irq);
305
VecInfo *vec;
306
int running = nvic_exec_prio(s);
307
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
308
index XXXXXXX..XXXXXXX 100644
309
--- a/target/arm/cpu.c
310
+++ b/target/arm/cpu.c
311
@@ -XXX,XX +XXX,XX @@
312
#if !defined(CONFIG_USER_ONLY)
313
#include "hw/loader.h"
314
#include "hw/boards.h"
315
+#include "hw/intc/armv7m_nvic.h"
316
#endif
317
#include "sysemu/tcg.h"
318
#include "sysemu/qtest.h"
319
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/target/arm/m_helper.c
322
+++ b/target/arm/m_helper.c
323
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
324
* that we will need later in order to do lazy FP reg stacking.
325
*/
326
bool is_secure = env->v7m.secure;
327
- void *nvic = env->nvic;
328
+ NVICState *nvic = env->nvic;
329
/*
330
* Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
331
* are banked and we want to update the bit in the bank for the
332
--
333
2.34.1
334
335
diff view generated by jsdifflib
New patch
1
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
3
While dozens of files include "cpu.h", only 3 files require
4
these NVIC helper declarations.
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20230206223502.25122-12-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
12
target/arm/cpu.h | 123 ----------------------------------
13
target/arm/cpu.c | 4 +-
14
target/arm/cpu_tcg.c | 3 +
15
target/arm/m_helper.c | 3 +
16
5 files changed, 132 insertions(+), 124 deletions(-)
17
18
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/intc/armv7m_nvic.h
21
+++ b/include/hw/intc/armv7m_nvic.h
22
@@ -XXX,XX +XXX,XX @@ struct NVICState {
23
qemu_irq sysresetreq;
24
};
25
26
+/* Interface between CPU and Interrupt controller. */
27
+/**
28
+ * armv7m_nvic_set_pending: mark the specified exception as pending
29
+ * @s: the NVIC
30
+ * @irq: the exception number to mark pending
31
+ * @secure: false for non-banked exceptions or for the nonsecure
32
+ * version of a banked exception, true for the secure version of a banked
33
+ * exception.
34
+ *
35
+ * Marks the specified exception as pending. Note that we will assert()
36
+ * if @secure is true and @irq does not specify one of the fixed set
37
+ * of architecturally banked exceptions.
38
+ */
39
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
40
+/**
41
+ * armv7m_nvic_set_pending_derived: mark this derived exception as pending
42
+ * @s: the NVIC
43
+ * @irq: the exception number to mark pending
44
+ * @secure: false for non-banked exceptions or for the nonsecure
45
+ * version of a banked exception, true for the secure version of a banked
46
+ * exception.
47
+ *
48
+ * Similar to armv7m_nvic_set_pending(), but specifically for derived
49
+ * exceptions (exceptions generated in the course of trying to take
50
+ * a different exception).
51
+ */
52
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
53
+/**
54
+ * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
55
+ * @s: the NVIC
56
+ * @irq: the exception number to mark pending
57
+ * @secure: false for non-banked exceptions or for the nonsecure
58
+ * version of a banked exception, true for the secure version of a banked
59
+ * exception.
60
+ *
61
+ * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
62
+ * generated in the course of lazy stacking of FP registers.
63
+ */
64
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
65
+/**
66
+ * armv7m_nvic_get_pending_irq_info: return highest priority pending
67
+ * exception, and whether it targets Secure state
68
+ * @s: the NVIC
69
+ * @pirq: set to pending exception number
70
+ * @ptargets_secure: set to whether pending exception targets Secure
71
+ *
72
+ * This function writes the number of the highest priority pending
73
+ * exception (the one which would be made active by
74
+ * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
75
+ * to true if the current highest priority pending exception should
76
+ * be taken to Secure state, false for NS.
77
+ */
78
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
79
+ bool *ptargets_secure);
80
+/**
81
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
82
+ * @s: the NVIC
83
+ *
84
+ * Move the current highest priority pending exception from the pending
85
+ * state to the active state, and update v7m.exception to indicate that
86
+ * it is the exception currently being handled.
87
+ */
88
+void armv7m_nvic_acknowledge_irq(NVICState *s);
89
+/**
90
+ * armv7m_nvic_complete_irq: complete specified interrupt or exception
91
+ * @s: the NVIC
92
+ * @irq: the exception number to complete
93
+ * @secure: true if this exception was secure
94
+ *
95
+ * Returns: -1 if the irq was not active
96
+ * 1 if completing this irq brought us back to base (no active irqs)
97
+ * 0 if there is still an irq active after this one was completed
98
+ * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
99
+ */
100
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
101
+/**
102
+ * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
103
+ * @s: the NVIC
104
+ * @irq: the exception number to mark pending
105
+ * @secure: false for non-banked exceptions or for the nonsecure
106
+ * version of a banked exception, true for the secure version of a banked
107
+ * exception.
108
+ *
109
+ * Return whether an exception is "ready", i.e. whether the exception is
110
+ * enabled and is configured at a priority which would allow it to
111
+ * interrupt the current execution priority. This controls whether the
112
+ * RDY bit for it in the FPCCR is set.
113
+ */
114
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
115
+/**
116
+ * armv7m_nvic_raw_execution_priority: return the raw execution priority
117
+ * @s: the NVIC
118
+ *
119
+ * Returns: the raw execution priority as defined by the v8M architecture.
120
+ * This is the execution priority minus the effects of AIRCR.PRIS,
121
+ * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
122
+ * (v8M ARM ARM I_PKLD.)
123
+ */
124
+int armv7m_nvic_raw_execution_priority(NVICState *s);
125
+/**
126
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
127
+ * priority is negative for the specified security state.
128
+ * @s: the NVIC
129
+ * @secure: the security state to test
130
+ * This corresponds to the pseudocode IsReqExecPriNeg().
131
+ */
132
+#ifndef CONFIG_USER_ONLY
133
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
134
+#else
135
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
136
+{
137
+ return false;
138
+}
139
+#endif
140
+#ifndef CONFIG_USER_ONLY
141
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
142
+#else
143
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
144
+{
145
+ return true;
146
+}
147
+#endif
148
+
149
#endif
150
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/target/arm/cpu.h
153
+++ b/target/arm/cpu.h
154
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
155
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
156
uint32_t cur_el, bool secure);
157
158
-/* Interface between CPU and Interrupt controller. */
159
-#ifndef CONFIG_USER_ONLY
160
-bool armv7m_nvic_can_take_pending_exception(NVICState *s);
161
-#else
162
-static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
163
-{
164
- return true;
165
-}
166
-#endif
167
-/**
168
- * armv7m_nvic_set_pending: mark the specified exception as pending
169
- * @s: the NVIC
170
- * @irq: the exception number to mark pending
171
- * @secure: false for non-banked exceptions or for the nonsecure
172
- * version of a banked exception, true for the secure version of a banked
173
- * exception.
174
- *
175
- * Marks the specified exception as pending. Note that we will assert()
176
- * if @secure is true and @irq does not specify one of the fixed set
177
- * of architecturally banked exceptions.
178
- */
179
-void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
180
-/**
181
- * armv7m_nvic_set_pending_derived: mark this derived exception as pending
182
- * @s: the NVIC
183
- * @irq: the exception number to mark pending
184
- * @secure: false for non-banked exceptions or for the nonsecure
185
- * version of a banked exception, true for the secure version of a banked
186
- * exception.
187
- *
188
- * Similar to armv7m_nvic_set_pending(), but specifically for derived
189
- * exceptions (exceptions generated in the course of trying to take
190
- * a different exception).
191
- */
192
-void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
193
-/**
194
- * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
195
- * @s: the NVIC
196
- * @irq: the exception number to mark pending
197
- * @secure: false for non-banked exceptions or for the nonsecure
198
- * version of a banked exception, true for the secure version of a banked
199
- * exception.
200
- *
201
- * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
202
- * generated in the course of lazy stacking of FP registers.
203
- */
204
-void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
205
-/**
206
- * armv7m_nvic_get_pending_irq_info: return highest priority pending
207
- * exception, and whether it targets Secure state
208
- * @s: the NVIC
209
- * @pirq: set to pending exception number
210
- * @ptargets_secure: set to whether pending exception targets Secure
211
- *
212
- * This function writes the number of the highest priority pending
213
- * exception (the one which would be made active by
214
- * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
215
- * to true if the current highest priority pending exception should
216
- * be taken to Secure state, false for NS.
217
- */
218
-void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
219
- bool *ptargets_secure);
220
-/**
221
- * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
222
- * @s: the NVIC
223
- *
224
- * Move the current highest priority pending exception from the pending
225
- * state to the active state, and update v7m.exception to indicate that
226
- * it is the exception currently being handled.
227
- */
228
-void armv7m_nvic_acknowledge_irq(NVICState *s);
229
-/**
230
- * armv7m_nvic_complete_irq: complete specified interrupt or exception
231
- * @s: the NVIC
232
- * @irq: the exception number to complete
233
- * @secure: true if this exception was secure
234
- *
235
- * Returns: -1 if the irq was not active
236
- * 1 if completing this irq brought us back to base (no active irqs)
237
- * 0 if there is still an irq active after this one was completed
238
- * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
239
- */
240
-int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
241
-/**
242
- * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
243
- * @s: the NVIC
244
- * @irq: the exception number to mark pending
245
- * @secure: false for non-banked exceptions or for the nonsecure
246
- * version of a banked exception, true for the secure version of a banked
247
- * exception.
248
- *
249
- * Return whether an exception is "ready", i.e. whether the exception is
250
- * enabled and is configured at a priority which would allow it to
251
- * interrupt the current execution priority. This controls whether the
252
- * RDY bit for it in the FPCCR is set.
253
- */
254
-bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
255
-/**
256
- * armv7m_nvic_raw_execution_priority: return the raw execution priority
257
- * @s: the NVIC
258
- *
259
- * Returns: the raw execution priority as defined by the v8M architecture.
260
- * This is the execution priority minus the effects of AIRCR.PRIS,
261
- * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
262
- * (v8M ARM ARM I_PKLD.)
263
- */
264
-int armv7m_nvic_raw_execution_priority(NVICState *s);
265
-/**
266
- * armv7m_nvic_neg_prio_requested: return true if the requested execution
267
- * priority is negative for the specified security state.
268
- * @s: the NVIC
269
- * @secure: the security state to test
270
- * This corresponds to the pseudocode IsReqExecPriNeg().
271
- */
272
-#ifndef CONFIG_USER_ONLY
273
-bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
274
-#else
275
-static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
276
-{
277
- return false;
278
-}
279
-#endif
280
-
281
/* Interface for defining coprocessor registers.
282
* Registers are defined in tables of arm_cp_reginfo structs
283
* which are passed to define_arm_cp_regs().
284
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
285
index XXXXXXX..XXXXXXX 100644
286
--- a/target/arm/cpu.c
287
+++ b/target/arm/cpu.c
288
@@ -XXX,XX +XXX,XX @@
289
#if !defined(CONFIG_USER_ONLY)
290
#include "hw/loader.h"
291
#include "hw/boards.h"
292
+#ifdef CONFIG_TCG
293
#include "hw/intc/armv7m_nvic.h"
294
-#endif
295
+#endif /* CONFIG_TCG */
296
+#endif /* !CONFIG_USER_ONLY */
297
#include "sysemu/tcg.h"
298
#include "sysemu/qtest.h"
299
#include "sysemu/hw_accel.h"
300
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
301
index XXXXXXX..XXXXXXX 100644
302
--- a/target/arm/cpu_tcg.c
303
+++ b/target/arm/cpu_tcg.c
304
@@ -XXX,XX +XXX,XX @@
305
#include "hw/boards.h"
306
#endif
307
#include "cpregs.h"
308
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
309
+#include "hw/intc/armv7m_nvic.h"
310
+#endif
311
312
313
/* Share AArch32 -cpu max features with AArch64. */
314
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
315
index XXXXXXX..XXXXXXX 100644
316
--- a/target/arm/m_helper.c
317
+++ b/target/arm/m_helper.c
318
@@ -XXX,XX +XXX,XX @@
319
#include "exec/cpu_ldst.h"
320
#include "semihosting/common-semi.h"
321
#endif
322
+#if !defined(CONFIG_USER_ONLY)
323
+#include "hw/intc/armv7m_nvic.h"
324
+#endif
325
326
static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
327
uint32_t reg, uint32_t val)
328
--
329
2.34.1
330
331
diff view generated by jsdifflib
New patch
1
1
From: Alex Bennée <alex.bennee@linaro.org>
2
3
The two TCG tests for GICv2 and GICv3 are very heavy weight distros
4
that take a long time to boot up, especially for an --enable-debug
5
build. The total code coverage they give is:
6
7
Overall coverage rate:
8
lines......: 11.2% (59584 of 530123 lines)
9
functions..: 15.0% (7436 of 49443 functions)
10
branches...: 6.3% (19273 of 303933 branches)
11
12
We already get pretty close to that with the machine_aarch64_virt
13
tests which only does one full boot (~120s vs ~600s) of alpine. We
14
expand the kernel+initrd boot (~8s) to test both GICs and also add an
15
RNG device and a block device to generate a few IRQs and exercise the
16
storage layer. With that we get to a coverage of:
17
18
Overall coverage rate:
19
lines......: 11.0% (58121 of 530123 lines)
20
functions..: 14.9% (7343 of 49443 functions)
21
branches...: 6.0% (18269 of 303933 branches)
22
23
which I feel is close enough given the massive time saving. If we want
24
to target any more sub-systems we can use lighter weight more directed
25
tests.
26
27
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
28
Reviewed-by: Fabiano Rosas <farosas@suse.de>
29
Acked-by: Richard Henderson <richard.henderson@linaro.org>
30
Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
31
Cc: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
34
tests/avocado/boot_linux.py | 48 ++++----------------
35
tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
36
2 files changed, 65 insertions(+), 46 deletions(-)
37
38
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
39
index XXXXXXX..XXXXXXX 100644
40
--- a/tests/avocado/boot_linux.py
41
+++ b/tests/avocado/boot_linux.py
42
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
43
self.launch_and_wait(set_up_ssh_connection=False)
44
45
46
-# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
47
-# heavyweight. There are lighter weight distros which we use in the
48
-# machine_aarch64_virt.py tests.
49
+# For Aarch64 we only boot KVM tests in CI as booting the current
50
+# Fedora OS in TCG tests is very heavyweight. There are lighter weight
51
+# distros which we use in the machine_aarch64_virt.py tests.
52
class BootLinuxAarch64(LinuxTest):
53
"""
54
:avocado: tags=arch:aarch64
55
:avocado: tags=machine:virt
56
- :avocado: tags=machine:gic-version=2
57
"""
58
timeout = 720
59
60
- def add_common_args(self):
61
- self.vm.add_args('-bios',
62
- os.path.join(BUILD_DIR, 'pc-bios',
63
- 'edk2-aarch64-code.fd'))
64
- self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
65
- self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
66
-
67
- @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
68
- def test_fedora_cloud_tcg_gicv2(self):
69
- """
70
- :avocado: tags=accel:tcg
71
- :avocado: tags=cpu:max
72
- :avocado: tags=device:gicv2
73
- """
74
- self.require_accelerator("tcg")
75
- self.vm.add_args("-accel", "tcg")
76
- self.vm.add_args("-cpu", "max,lpa2=off")
77
- self.vm.add_args("-machine", "virt,gic-version=2")
78
- self.add_common_args()
79
- self.launch_and_wait(set_up_ssh_connection=False)
80
-
81
- @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
82
- def test_fedora_cloud_tcg_gicv3(self):
83
- """
84
- :avocado: tags=accel:tcg
85
- :avocado: tags=cpu:max
86
- :avocado: tags=device:gicv3
87
- """
88
- self.require_accelerator("tcg")
89
- self.vm.add_args("-accel", "tcg")
90
- self.vm.add_args("-cpu", "max,lpa2=off")
91
- self.vm.add_args("-machine", "virt,gic-version=3")
92
- self.add_common_args()
93
- self.launch_and_wait(set_up_ssh_connection=False)
94
-
95
def test_virt_kvm(self):
96
"""
97
:avocado: tags=accel:kvm
98
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
99
self.require_accelerator("kvm")
100
self.vm.add_args("-accel", "kvm")
101
self.vm.add_args("-machine", "virt,gic-version=host")
102
- self.add_common_args()
103
+ self.vm.add_args('-bios',
104
+ os.path.join(BUILD_DIR, 'pc-bios',
105
+ 'edk2-aarch64-code.fd'))
106
+ self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
107
+ self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
108
self.launch_and_wait(set_up_ssh_connection=False)
109
110
111
diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
112
index XXXXXXX..XXXXXXX 100644
113
--- a/tests/avocado/machine_aarch64_virt.py
114
+++ b/tests/avocado/machine_aarch64_virt.py
115
@@ -XXX,XX +XXX,XX @@
116
117
import time
118
import os
119
+import logging
120
121
from avocado_qemu import QemuSystemTest
122
from avocado_qemu import wait_for_console_pattern
123
from avocado_qemu import exec_command
124
from avocado_qemu import BUILD_DIR
125
+from avocado.utils import process
126
+from avocado.utils.path import find_command
127
128
class Aarch64VirtMachine(QemuSystemTest):
129
KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
130
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
131
self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
132
133
134
- def test_aarch64_virt(self):
135
+ def common_aarch64_virt(self, machine):
136
"""
137
- :avocado: tags=arch:aarch64
138
- :avocado: tags=machine:virt
139
- :avocado: tags=accel:tcg
140
- :avocado: tags=cpu:max
141
+ Common code to launch basic virt machine with kernel+initrd
142
+ and a scratch disk.
143
"""
144
+ logger = logging.getLogger('aarch64_virt')
145
+
146
kernel_url = ('https://fileserver.linaro.org/s/'
147
'z6B2ARM7DQT3HWN/download')
148
-
149
kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
150
kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
151
152
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
153
'console=ttyAMA0')
154
self.require_accelerator("tcg")
155
self.vm.add_args('-cpu', 'max,pauth-impdef=on',
156
+ '-machine', machine,
157
'-accel', 'tcg',
158
'-kernel', kernel_path,
159
'-append', kernel_command_line)
160
+
161
+ # A RNG offers an easy way to generate a few IRQs
162
+ self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
163
+ self.vm.add_args('-object',
164
+ 'rng-random,id=rng0,filename=/dev/urandom')
165
+
166
+ # Also add a scratch block device
167
+ logger.info('creating scratch qcow2 image')
168
+ image_path = os.path.join(self.workdir, 'scratch.qcow2')
169
+ qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
170
+ if not os.path.exists(qemu_img):
171
+ qemu_img = find_command('qemu-img', False)
172
+ if qemu_img is False:
173
+ self.cancel('Could not find "qemu-img", which is required to '
174
+ 'create the temporary qcow2 image')
175
+ cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
176
+ process.run(cmd)
177
+
178
+ # Add the device
179
+ self.vm.add_args('-blockdev',
180
+ f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
181
+ self.vm.add_args('-device',
182
+ 'virtio-blk-device,drive=scratch')
183
+
184
self.vm.launch()
185
self.wait_for_console_pattern('Welcome to Buildroot')
186
time.sleep(0.1)
187
exec_command(self, 'root')
188
time.sleep(0.1)
189
+ exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
190
+ time.sleep(0.1)
191
+ exec_command(self, 'md5sum /dev/vda')
192
+ time.sleep(0.1)
193
+ exec_command(self, 'cat /proc/interrupts')
194
+ time.sleep(0.1)
195
exec_command(self, 'cat /proc/self/maps')
196
time.sleep(0.1)
197
+
198
+ def test_aarch64_virt_gicv3(self):
199
+ """
200
+ :avocado: tags=arch:aarch64
201
+ :avocado: tags=machine:virt
202
+ :avocado: tags=accel:tcg
203
+ :avocado: tags=cpu:max
204
+ """
205
+ self.common_aarch64_virt("virt,gic_version=3")
206
+
207
+ def test_aarch64_virt_gicv2(self):
208
+ """
209
+ :avocado: tags=arch:aarch64
210
+ :avocado: tags=machine:virt
211
+ :avocado: tags=accel:tcg
212
+ :avocado: tags=cpu:max
213
+ """
214
+ self.common_aarch64_virt("virt,gic-version=2")
215
--
216
2.34.1
217
218
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Mostafa Saleh <smostafa@google.com>
2
2
3
The system configuration controller (SYSCFG) doesn't have
3
GBPA register can be used to globally abort all
4
any output IRQ (and the INTC input #71 belongs to the UART6).
4
transactions.
5
Remove the invalid code.
6
5
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
6
It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
8
be zero(Do not abort incoming transactions).
9
10
Other fields have default values of Use Incoming.
11
12
If UPDATE is not set, the write is ignored. This is the only permitted
13
behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)
14
15
As this patch adds a new state to the SMMU (GBPA), it is added
16
in a new subsection for forward migration compatibility.
17
GBPA is only migrated if its value is different from the reset value.
18
It does this to be backward migration compatible if SW didn't write
19
the register.
20
21
Signed-off-by: Mostafa Saleh <smostafa@google.com>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Eric Auger <eric.auger@redhat.com>
24
Message-id: 20230214094009.2445653-1-smostafa@google.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
27
---
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
28
hw/arm/smmuv3-internal.h | 7 +++++++
14
hw/arm/stm32f205_soc.c | 1 -
29
include/hw/arm/smmuv3.h | 1 +
15
hw/misc/stm32f2xx_syscfg.c | 2 --
30
hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++-
16
3 files changed, 5 deletions(-)
31
3 files changed, 50 insertions(+), 1 deletion(-)
17
32
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
33
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
19
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
35
--- a/hw/arm/smmuv3-internal.h
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
36
+++ b/hw/arm/smmuv3-internal.h
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
37
@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK, 0x24)
23
uint32_t syscfg_exticr3;
38
REG32(CR1, 0x28)
24
uint32_t syscfg_exticr4;
39
REG32(CR2, 0x2c)
25
uint32_t syscfg_cmpcr;
40
REG32(STATUSR, 0x40)
26
-
41
+REG32(GBPA, 0x44)
27
- qemu_irq irq;
42
+ FIELD(GBPA, ABORT, 20, 1)
43
+ FIELD(GBPA, UPDATE, 31, 1)
44
+
45
+/* Use incoming. */
46
+#define SMMU_GBPA_RESET_VAL 0x1000
47
+
48
REG32(IRQ_CTRL, 0x50)
49
FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1)
50
FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1)
51
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
52
index XXXXXXX..XXXXXXX 100644
53
--- a/include/hw/arm/smmuv3.h
54
+++ b/include/hw/arm/smmuv3.h
55
@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
56
uint32_t cr[3];
57
uint32_t cr0ack;
58
uint32_t statusr;
59
+ uint32_t gbpa;
60
uint32_t irq_ctrl;
61
uint32_t gerror;
62
uint32_t gerrorn;
63
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/smmuv3.c
66
+++ b/hw/arm/smmuv3.c
67
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
68
s->gerror = 0;
69
s->gerrorn = 0;
70
s->statusr = 0;
71
+ s->gbpa = SMMU_GBPA_RESET_VAL;
72
}
73
74
static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
75
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
76
qemu_mutex_lock(&s->mutex);
77
78
if (!smmu_enabled(s)) {
79
- status = SMMU_TRANS_DISABLE;
80
+ if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
81
+ status = SMMU_TRANS_ABORT;
82
+ } else {
83
+ status = SMMU_TRANS_DISABLE;
84
+ }
85
goto epilogue;
86
}
87
88
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
89
case A_GERROR_IRQ_CFG2:
90
s->gerror_irq_cfg2 = data;
91
return MEMTX_OK;
92
+ case A_GBPA:
93
+ /*
94
+ * If UPDATE is not set, the write is ignored. This is the only
95
+ * permitted behavior in SMMUv3.2 and later.
96
+ */
97
+ if (data & R_GBPA_UPDATE_MASK) {
98
+ /* Ignore update bit as write is synchronous. */
99
+ s->gbpa = data & ~R_GBPA_UPDATE_MASK;
100
+ }
101
+ return MEMTX_OK;
102
case A_STRTAB_BASE: /* 64b */
103
s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
104
return MEMTX_OK;
105
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
106
case A_STATUSR:
107
*data = s->statusr;
108
return MEMTX_OK;
109
+ case A_GBPA:
110
+ *data = s->gbpa;
111
+ return MEMTX_OK;
112
case A_IRQ_CTRL:
113
case A_IRQ_CTRL_ACK:
114
*data = s->irq_ctrl;
115
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
116
},
28
};
117
};
29
118
30
#endif /* HW_STM32F2XX_SYSCFG_H */
119
+static bool smmuv3_gbpa_needed(void *opaque)
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
120
+{
32
index XXXXXXX..XXXXXXX 100644
121
+ SMMUv3State *s = opaque;
33
--- a/hw/arm/stm32f205_soc.c
122
+
34
+++ b/hw/arm/stm32f205_soc.c
123
+ /* Only migrate GBPA if it has different reset value. */
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
124
+ return s->gbpa != SMMU_GBPA_RESET_VAL;
36
}
125
+}
37
busdev = SYS_BUS_DEVICE(dev);
126
+
38
sysbus_mmio_map(busdev, 0, 0x40013800);
127
+static const VMStateDescription vmstate_gbpa = {
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
128
+ .name = "smmuv3/gbpa",
40
129
+ .version_id = 1,
41
/* Attach UART (uses USART registers) and USART controllers */
130
+ .minimum_version_id = 1,
42
for (i = 0; i < STM_NUM_USARTS; i++) {
131
+ .needed = smmuv3_gbpa_needed,
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
132
+ .fields = (VMStateField[]) {
44
index XXXXXXX..XXXXXXX 100644
133
+ VMSTATE_UINT32(gbpa, SMMUv3State),
45
--- a/hw/misc/stm32f2xx_syscfg.c
134
+ VMSTATE_END_OF_LIST()
46
+++ b/hw/misc/stm32f2xx_syscfg.c
135
+ }
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
136
+};
48
{
137
+
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
138
static const VMStateDescription vmstate_smmuv3 = {
50
139
.name = "smmuv3",
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
140
.version_id = 1,
52
-
141
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
142
54
TYPE_STM32F2XX_SYSCFG, 0x400);
143
VMSTATE_END_OF_LIST(),
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
144
},
145
+ .subsections = (const VMStateDescription * []) {
146
+ &vmstate_gbpa,
147
+ NULL
148
+ }
149
};
150
151
static void smmuv3_instance_init(Object *obj)
56
--
152
--
57
2.20.1
153
2.34.1
58
59
diff view generated by jsdifflib
1
From: Andrew Jones <drjones@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
3
Since commit acc0b8b05a when running the ZynqMP ZCU102 board with
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
4
a QEMU configured using --without-default-devices, we get:
5
in the build when building armv7m_systick.
6
5
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
6
$ qemu-system-aarch64 -M xlnx-zcu102
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
qemu-system-aarch64: missing object type 'usb_dwc3'
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
8
Abort trap: 6
9
10
Fix by adding the missing Kconfig dependency.
11
12
Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers")
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20230216092327.2203-1-philmd@linaro.org
15
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
hw/arm/Kconfig | 1 +
18
hw/arm/Kconfig | 1 +
13
1 file changed, 1 insertion(+)
19
1 file changed, 1 insertion(+)
14
20
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
21
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/Kconfig
23
--- a/hw/arm/Kconfig
18
+++ b/hw/arm/Kconfig
24
+++ b/hw/arm/Kconfig
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
25
@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
20
26
select XLNX_CSU_DMA
21
config ARM_V7M
27
select XLNX_ZYNQMP
22
bool
28
select XLNX_ZDMA
23
+ select PTIMER
29
+ select USB_DWC3
24
30
25
config ALLWINNER_A10
31
config XLNX_VERSAL
26
bool
32
bool
27
--
33
--
28
2.20.1
34
2.34.1
29
35
30
36
diff view generated by jsdifflib
New patch
1
From: Cornelia Huck <cohuck@redhat.com>
1
2
3
Just use current_accel_name() directly.
4
5
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/virt.c | 6 +++---
11
1 file changed, 3 insertions(+), 3 deletions(-)
12
13
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/virt.c
16
+++ b/hw/arm/virt.c
17
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
18
if (vms->secure && (kvm_enabled() || hvf_enabled())) {
19
error_report("mach-virt: %s does not support providing "
20
"Security extensions (TrustZone) to the guest CPU",
21
- kvm_enabled() ? "KVM" : "HVF");
22
+ current_accel_name());
23
exit(1);
24
}
25
26
if (vms->virt && (kvm_enabled() || hvf_enabled())) {
27
error_report("mach-virt: %s does not support providing "
28
"Virtualization extensions to the guest CPU",
29
- kvm_enabled() ? "KVM" : "HVF");
30
+ current_accel_name());
31
exit(1);
32
}
33
34
if (vms->mte && (kvm_enabled() || hvf_enabled())) {
35
error_report("mach-virt: %s does not support providing "
36
"MTE to the guest CPU",
37
- kvm_enabled() ? "KVM" : "HVF");
38
+ current_accel_name());
39
exit(1);
40
}
41
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
1
From: Hao Wu <wuhaotsh@google.com>
1
2
3
Havard is no longer working on the Nuvoton systems for a while
4
and won't be able to do any work on it in the future. So I'll
5
take over maintaining the Nuvoton system from him.
6
7
Signed-off-by: Hao Wu <wuhaotsh@google.com>
8
Acked-by: Havard Skinnemoen <hskinnemoen@google.com>
9
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
10
Message-id: 20230208235433.3989937-2-wuhaotsh@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
MAINTAINERS | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/MAINTAINERS b/MAINTAINERS
17
index XXXXXXX..XXXXXXX 100644
18
--- a/MAINTAINERS
19
+++ b/MAINTAINERS
20
@@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h
21
F: docs/system/arm/musicpal.rst
22
23
Nuvoton NPCM7xx
24
-M: Havard Skinnemoen <hskinnemoen@google.com>
25
M: Tyrone Ting <kfting@nuvoton.com>
26
+M: Hao Wu <wuhaotsh@google.com>
27
L: qemu-arm@nongnu.org
28
S: Supported
29
F: hw/*/npcm7xx*
30
--
31
2.34.1
diff view generated by jsdifflib
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
We should at least document what this machine is about.
3
Nuvoton's PSPI is a general purpose SPI module which enables
4
connections to SPI-based peripheral devices.
4
5
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
6
Signed-off-by: Hao Wu <wuhaotsh@google.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Chris Rauer <crauer@google.com>
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
8
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
8
Cc: Leif Lindholm <leif@nuviainc.com>
9
Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
[PMM: fixed filename mismatch]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
12
MAINTAINERS | 6 +-
15
docs/system/target-arm.rst | 1 +
13
include/hw/ssi/npcm_pspi.h | 53 +++++++++
16
2 files changed, 33 insertions(+)
14
hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++
17
create mode 100644 docs/system/arm/sbsa.rst
15
hw/ssi/meson.build | 2 +-
16
hw/ssi/trace-events | 5 +
17
5 files changed, 283 insertions(+), 4 deletions(-)
18
create mode 100644 include/hw/ssi/npcm_pspi.h
19
create mode 100644 hw/ssi/npcm_pspi.c
18
20
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
21
diff --git a/MAINTAINERS b/MAINTAINERS
22
index XXXXXXX..XXXXXXX 100644
23
--- a/MAINTAINERS
24
+++ b/MAINTAINERS
25
@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
26
M: Hao Wu <wuhaotsh@google.com>
27
L: qemu-arm@nongnu.org
28
S: Supported
29
-F: hw/*/npcm7xx*
30
-F: include/hw/*/npcm7xx*
31
-F: tests/qtest/npcm7xx*
32
+F: hw/*/npcm*
33
+F: include/hw/*/npcm*
34
+F: tests/qtest/npcm*
35
F: pc-bios/npcm7xx_bootrom.bin
36
F: roms/vbootrom
37
F: docs/system/arm/nuvoton.rst
38
diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
20
new file mode 100644
39
new file mode 100644
21
index XXXXXXX..XXXXXXX
40
index XXXXXXX..XXXXXXX
22
--- /dev/null
41
--- /dev/null
23
+++ b/docs/system/arm/sbsa.rst
42
+++ b/include/hw/ssi/npcm_pspi.h
24
@@ -XXX,XX +XXX,XX @@
43
@@ -XXX,XX +XXX,XX @@
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
44
+/*
26
+==================================================================
45
+ * Nuvoton Peripheral SPI Module
27
+
46
+ *
28
+While the `virt` board is a generic board platform that doesn't match
47
+ * Copyright 2023 Google LLC
29
+any real hardware the `sbsa-ref` board intends to look like real
48
+ *
30
+hardware. The `Server Base System Architecture
49
+ * This program is free software; you can redistribute it and/or modify it
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
50
+ * under the terms of the GNU General Public License as published by the
32
+minimum base line of hardware support and importantly how the firmware
51
+ * Free Software Foundation; either version 2 of the License, or
33
+reports that to any operating system. It is a static system that
52
+ * (at your option) any later version.
34
+reports a very minimal DT to the firmware for non-discoverable
53
+ *
35
+information about components affected by the qemu command line (i.e.
54
+ * This program is distributed in the hope that it will be useful, but WITHOUT
36
+cpus and memory). As a result it must have a firmware specifically
55
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
37
+built to expect a certain hardware layout (as you would in a real
56
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
38
+machine).
57
+ * for more details.
39
+
58
+ */
40
+It is intended to be a machine for developing firmware and testing
59
+#ifndef NPCM_PSPI_H
41
+standards compliance with operating systems.
60
+#define NPCM_PSPI_H
42
+
61
+
43
+Supported devices
62
+#include "hw/ssi/ssi.h"
44
+"""""""""""""""""
63
+#include "hw/sysbus.h"
45
+
64
+
46
+The sbsa-ref board supports:
65
+/*
47
+
66
+ * Number of registers in our device state structure. Don't change this without
48
+ - A configurable number of AArch64 CPUs
67
+ * incrementing the version_id in the vmstate.
49
+ - GIC version 3
68
+ */
50
+ - System bus AHCI controller
69
+#define NPCM_PSPI_NR_REGS 3
51
+ - System bus EHCI controller
70
+
52
+ - CDROM and hard disc on AHCI bus
71
+/**
53
+ - E1000E ethernet card on PCIe bus
72
+ * NPCMPSPIState - Device state for one Flash Interface Unit.
54
+ - VGA display adaptor on PCIe bus
73
+ * @parent: System bus device.
55
+ - A generic SBSA watchdog device
74
+ * @mmio: Memory region for register access.
56
+
75
+ * @spi: The SPI bus mastered by this controller.
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
76
+ * @regs: Register contents.
77
+ * @irq: The interrupt request queue for this module.
78
+ *
79
+ * Each PSPI has a shared bank of registers, and controls up to four chip
80
+ * selects. Each chip select has a dedicated memory region which may be used to
81
+ * read and write the flash connected to that chip select as if it were memory.
82
+ */
83
+typedef struct NPCMPSPIState {
84
+ SysBusDevice parent;
85
+
86
+ MemoryRegion mmio;
87
+
88
+ SSIBus *spi;
89
+ uint16_t regs[NPCM_PSPI_NR_REGS];
90
+ qemu_irq irq;
91
+} NPCMPSPIState;
92
+
93
+#define TYPE_NPCM_PSPI "npcm-pspi"
94
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
95
+
96
+#endif /* NPCM_PSPI_H */
97
diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
98
new file mode 100644
99
index XXXXXXX..XXXXXXX
100
--- /dev/null
101
+++ b/hw/ssi/npcm_pspi.c
102
@@ -XXX,XX +XXX,XX @@
103
+/*
104
+ * Nuvoton NPCM Peripheral SPI Module (PSPI)
105
+ *
106
+ * Copyright 2023 Google LLC
107
+ *
108
+ * This program is free software; you can redistribute it and/or modify it
109
+ * under the terms of the GNU General Public License as published by the
110
+ * Free Software Foundation; either version 2 of the License, or
111
+ * (at your option) any later version.
112
+ *
113
+ * This program is distributed in the hope that it will be useful, but WITHOUT
114
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
115
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
116
+ * for more details.
117
+ */
118
+
119
+#include "qemu/osdep.h"
120
+
121
+#include "hw/irq.h"
122
+#include "hw/registerfields.h"
123
+#include "hw/ssi/npcm_pspi.h"
124
+#include "migration/vmstate.h"
125
+#include "qapi/error.h"
126
+#include "qemu/error-report.h"
127
+#include "qemu/log.h"
128
+#include "qemu/module.h"
129
+#include "qemu/units.h"
130
+
131
+#include "trace.h"
132
+
133
+REG16(PSPI_DATA, 0x0)
134
+REG16(PSPI_CTL1, 0x2)
135
+ FIELD(PSPI_CTL1, SPIEN, 0, 1)
136
+ FIELD(PSPI_CTL1, MOD, 2, 1)
137
+ FIELD(PSPI_CTL1, EIR, 5, 1)
138
+ FIELD(PSPI_CTL1, EIW, 6, 1)
139
+ FIELD(PSPI_CTL1, SCM, 7, 1)
140
+ FIELD(PSPI_CTL1, SCIDL, 8, 1)
141
+ FIELD(PSPI_CTL1, SCDV, 9, 7)
142
+REG16(PSPI_STAT, 0x4)
143
+ FIELD(PSPI_STAT, BSY, 0, 1)
144
+ FIELD(PSPI_STAT, RBF, 1, 1)
145
+
146
+static void npcm_pspi_update_irq(NPCMPSPIState *s)
147
+{
148
+ int level = 0;
149
+
150
+ /* Only fire IRQ when the module is enabled. */
151
+ if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
152
+ /* Update interrupt as BSY is cleared. */
153
+ if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
154
+ FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
155
+ level = 1;
156
+ }
157
+
158
+ /* Update interrupt as RBF is set. */
159
+ if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
160
+ FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
161
+ level = 1;
162
+ }
163
+ }
164
+ qemu_set_irq(s->irq, level);
165
+}
166
+
167
+static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
168
+{
169
+ uint16_t value = s->regs[R_PSPI_DATA];
170
+
171
+ /* Clear stat bits as the value are read out. */
172
+ s->regs[R_PSPI_STAT] = 0;
173
+
174
+ return value;
175
+}
176
+
177
+static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
178
+{
179
+ uint16_t value = 0;
180
+
181
+ if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
182
+ value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
183
+ }
184
+ value |= ssi_transfer(s->spi, extract16(data, 0, 8));
185
+ s->regs[R_PSPI_DATA] = value;
186
+
187
+ /* Mark data as available */
188
+ s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
189
+}
190
+
191
+/* Control register read handler. */
192
+static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
193
+ unsigned int size)
194
+{
195
+ NPCMPSPIState *s = opaque;
196
+ uint16_t value;
197
+
198
+ switch (addr) {
199
+ case A_PSPI_DATA:
200
+ value = npcm_pspi_read_data(s);
201
+ break;
202
+
203
+ case A_PSPI_CTL1:
204
+ value = s->regs[R_PSPI_CTL1];
205
+ break;
206
+
207
+ case A_PSPI_STAT:
208
+ value = s->regs[R_PSPI_STAT];
209
+ break;
210
+
211
+ default:
212
+ qemu_log_mask(LOG_GUEST_ERROR,
213
+ "%s: write to invalid offset 0x%" PRIx64 "\n",
214
+ DEVICE(s)->canonical_path, addr);
215
+ return 0;
216
+ }
217
+ trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
218
+ npcm_pspi_update_irq(s);
219
+
220
+ return value;
221
+}
222
+
223
+/* Control register write handler. */
224
+static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
225
+ unsigned int size)
226
+{
227
+ NPCMPSPIState *s = opaque;
228
+ uint16_t value = v;
229
+
230
+ trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
231
+
232
+ switch (addr) {
233
+ case A_PSPI_DATA:
234
+ npcm_pspi_write_data(s, value);
235
+ break;
236
+
237
+ case A_PSPI_CTL1:
238
+ s->regs[R_PSPI_CTL1] = value;
239
+ break;
240
+
241
+ case A_PSPI_STAT:
242
+ qemu_log_mask(LOG_GUEST_ERROR,
243
+ "%s: write to read-only register PSPI_STAT: 0x%08"
244
+ PRIx64 "\n", DEVICE(s)->canonical_path, v);
245
+ break;
246
+
247
+ default:
248
+ qemu_log_mask(LOG_GUEST_ERROR,
249
+ "%s: write to invalid offset 0x%" PRIx64 "\n",
250
+ DEVICE(s)->canonical_path, addr);
251
+ return;
252
+ }
253
+ npcm_pspi_update_irq(s);
254
+}
255
+
256
+static const MemoryRegionOps npcm_pspi_ctrl_ops = {
257
+ .read = npcm_pspi_ctrl_read,
258
+ .write = npcm_pspi_ctrl_write,
259
+ .endianness = DEVICE_LITTLE_ENDIAN,
260
+ .valid = {
261
+ .min_access_size = 1,
262
+ .max_access_size = 2,
263
+ .unaligned = false,
264
+ },
265
+ .impl = {
266
+ .min_access_size = 2,
267
+ .max_access_size = 2,
268
+ .unaligned = false,
269
+ },
270
+};
271
+
272
+static void npcm_pspi_enter_reset(Object *obj, ResetType type)
273
+{
274
+ NPCMPSPIState *s = NPCM_PSPI(obj);
275
+
276
+ trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
277
+ memset(s->regs, 0, sizeof(s->regs));
278
+}
279
+
280
+static void npcm_pspi_realize(DeviceState *dev, Error **errp)
281
+{
282
+ NPCMPSPIState *s = NPCM_PSPI(dev);
283
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
284
+ Object *obj = OBJECT(dev);
285
+
286
+ s->spi = ssi_create_bus(dev, "pspi");
287
+ memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
288
+ "mmio", 4 * KiB);
289
+ sysbus_init_mmio(sbd, &s->mmio);
290
+ sysbus_init_irq(sbd, &s->irq);
291
+}
292
+
293
+static const VMStateDescription vmstate_npcm_pspi = {
294
+ .name = "npcm-pspi",
295
+ .version_id = 0,
296
+ .minimum_version_id = 0,
297
+ .fields = (VMStateField[]) {
298
+ VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
299
+ VMSTATE_END_OF_LIST(),
300
+ },
301
+};
302
+
303
+
304
+static void npcm_pspi_class_init(ObjectClass *klass, void *data)
305
+{
306
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
307
+ DeviceClass *dc = DEVICE_CLASS(klass);
308
+
309
+ dc->desc = "NPCM Peripheral SPI Module";
310
+ dc->realize = npcm_pspi_realize;
311
+ dc->vmsd = &vmstate_npcm_pspi;
312
+ rc->phases.enter = npcm_pspi_enter_reset;
313
+}
314
+
315
+static const TypeInfo npcm_pspi_types[] = {
316
+ {
317
+ .name = TYPE_NPCM_PSPI,
318
+ .parent = TYPE_SYS_BUS_DEVICE,
319
+ .instance_size = sizeof(NPCMPSPIState),
320
+ .class_init = npcm_pspi_class_init,
321
+ },
322
+};
323
+DEFINE_TYPES(npcm_pspi_types);
324
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
58
index XXXXXXX..XXXXXXX 100644
325
index XXXXXXX..XXXXXXX 100644
59
--- a/docs/system/target-arm.rst
326
--- a/hw/ssi/meson.build
60
+++ b/docs/system/target-arm.rst
327
+++ b/hw/ssi/meson.build
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
328
@@ -XXX,XX +XXX,XX @@
62
arm/mps2
329
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
63
arm/musca
330
softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
64
arm/realview
331
-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
65
+ arm/sbsa
332
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
66
arm/versatile
333
softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
67
arm/vexpress
334
softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
68
arm/aspeed
335
softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
336
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
337
index XXXXXXX..XXXXXXX 100644
338
--- a/hw/ssi/trace-events
339
+++ b/hw/ssi/trace-events
340
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
341
npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
342
npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
343
344
+# npcm_pspi.c
345
+npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
346
+npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
347
+npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
348
+
349
# ibex_spi_host.c
350
351
ibex_spi_host_reset(const char *msg) "%s"
69
--
352
--
70
2.20.1
353
2.34.1
71
72
diff view generated by jsdifflib
New patch
1
From: Hao Wu <wuhaotsh@google.com>
1
2
3
Signed-off-by: Hao Wu <wuhaotsh@google.com>
4
Reviewed-by: Titus Rwantare <titusr@google.com>
5
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
6
Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
docs/system/arm/nuvoton.rst | 2 +-
10
include/hw/arm/npcm7xx.h | 2 ++
11
hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++--
12
3 files changed, 26 insertions(+), 3 deletions(-)
13
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/nuvoton.rst
17
+++ b/docs/system/arm/nuvoton.rst
18
@@ -XXX,XX +XXX,XX @@ Supported devices
19
* SMBus controller (SMBF)
20
* Ethernet controller (EMC)
21
* Tachometer
22
+ * Peripheral SPI controller (PSPI)
23
24
Missing devices
25
---------------
26
@@ -XXX,XX +XXX,XX @@ Missing devices
27
28
* Ethernet controller (GMAC)
29
* USB device (USBD)
30
- * Peripheral SPI controller (PSPI)
31
* SD/MMC host
32
* PECI interface
33
* PCI and PCIe root complex and bridges
34
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/arm/npcm7xx.h
37
+++ b/include/hw/arm/npcm7xx.h
38
@@ -XXX,XX +XXX,XX @@
39
#include "hw/nvram/npcm7xx_otp.h"
40
#include "hw/timer/npcm7xx_timer.h"
41
#include "hw/ssi/npcm7xx_fiu.h"
42
+#include "hw/ssi/npcm_pspi.h"
43
#include "hw/usb/hcd-ehci.h"
44
#include "hw/usb/hcd-ohci.h"
45
#include "target/arm/cpu.h"
46
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
47
NPCM7xxFIUState fiu[2];
48
NPCM7xxEMCState emc[2];
49
NPCM7xxSDHCIState mmc;
50
+ NPCMPSPIState pspi[2];
51
};
52
53
#define TYPE_NPCM7XX "npcm7xx"
54
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/npcm7xx.c
57
+++ b/hw/arm/npcm7xx.c
58
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
59
NPCM7XX_EMC1RX_IRQ = 15,
60
NPCM7XX_EMC1TX_IRQ,
61
NPCM7XX_MMC_IRQ = 26,
62
+ NPCM7XX_PSPI2_IRQ = 28,
63
+ NPCM7XX_PSPI1_IRQ = 31,
64
NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
65
NPCM7XX_TIMER1_IRQ,
66
NPCM7XX_TIMER2_IRQ,
67
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
68
0xf0826000,
69
};
70
71
+/* Register base address for each PSPI Module */
72
+static const hwaddr npcm7xx_pspi_addr[] = {
73
+ 0xf0200000,
74
+ 0xf0201000,
75
+};
76
+
77
static const struct {
78
hwaddr regs_addr;
79
uint32_t unconnected_pins;
80
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
81
object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
82
}
83
84
+ for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
85
+ object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
86
+ }
87
+
88
object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
89
}
90
91
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
92
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
93
npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
94
95
+ /* PSPI */
96
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
97
+ for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
98
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
99
+ int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
100
+
101
+ sysbus_realize(sbd, &error_abort);
102
+ sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
103
+ sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
104
+ }
105
+
106
create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
107
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
108
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
109
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
110
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
111
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
112
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
113
- create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
114
- create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
115
create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
116
create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
117
create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
118
--
119
2.34.1
diff view generated by jsdifflib
New patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
2
3
Addresses targeting the second translation table (TTB1) in the SMMU have
4
all upper bits set. Ensure the IOMMU region covers all 64 bits.
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/smmu-common.h | 2 --
13
hw/arm/smmu-common.c | 2 +-
14
2 files changed, 1 insertion(+), 3 deletions(-)
15
16
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/smmu-common.h
19
+++ b/include/hw/arm/smmu-common.h
20
@@ -XXX,XX +XXX,XX @@
21
#define SMMU_PCI_DEVFN_MAX 256
22
#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
23
24
-#define SMMU_MAX_VA_BITS 48
25
-
26
/*
27
* Page table walk error types
28
*/
29
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/smmu-common.c
32
+++ b/hw/arm/smmu-common.c
33
@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
34
35
memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
36
s->mrtypename,
37
- OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
38
+ OBJECT(s), name, UINT64_MAX);
39
address_space_init(&sdev->as,
40
MEMORY_REGION(&sdev->iommu), name);
41
trace_smmu_add_mr(name);
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
1
2
3
Addresses targeting the second translation table (TTB1) in the SMMU have
4
all upper bits set (except for the top byte when TBI is enabled). Fix
5
the TTB1 check.
6
7
Reported-by: Ola Hugosson <ola.hugosson@arm.com>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/smmu-common.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/smmu-common.c
20
+++ b/hw/arm/smmu-common.c
21
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
22
/* there is a ttbr0 region and we are in it (high bits all zero) */
23
return &cfg->tt[0];
24
} else if (cfg->tt[1].tsz &&
25
- !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
26
+ sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
27
/* there is a ttbr1 region and we are in it (high bits all one) */
28
return &cfg->tt[1];
29
} else if (!cfg->tt[0].tsz) {
30
--
31
2.34.1
diff view generated by jsdifflib
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Claudio Fontana <cfontana@suse.de>
2
2
3
Fix code style. Don't use '#' flag of printf format ('%#') in
3
make it clearer from the name that this is a tcg-only function.
4
format strings, use '0x' prefix instead
5
4
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
5
Signed-off-by: Claudio Fontana <cfontana@suse.de>
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/translate-a64.c | 4 ++--
12
target/arm/helper.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
17
--- a/target/arm/helper.c
18
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
20
* trapped to the hypervisor in KVM.
21
break;
21
*/
22
default:
22
#ifdef CONFIG_TCG
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
23
-static void handle_semihosting(CPUState *cs)
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
24
+static void tcg_handle_semihosting(CPUState *cs)
25
__func__, insn, fpopcode, s->pc_curr);
25
{
26
g_assert_not_reached();
26
ARMCPU *cpu = ARM_CPU(cs);
27
}
27
CPUARMState *env = &cpu->env;
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
28
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
29
case 0x7f: /* FSQRT (vector) */
29
*/
30
break;
30
#ifdef CONFIG_TCG
31
default:
31
if (cs->exception_index == EXCP_SEMIHOST) {
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
32
- handle_semihosting(cs);
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
33
+ tcg_handle_semihosting(cs);
34
g_assert_not_reached();
34
return;
35
}
35
}
36
36
#endif
37
--
37
--
38
2.20.1
38
2.34.1
39
39
40
40
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Claudio Fontana <cfontana@suse.de>
2
2
3
We can use one MPC per SRAM bank, but we currently only wire the
3
for "all" builds (tcg + kvm), we want to avoid doing
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
4
the psci check if tcg is built-in, but not enabled.
5
5
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
6
Signed-off-by: Claudio Fontana <cfontana@suse.de>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
8
Signed-off-by: Fabiano Rosas <farosas@suse.de>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
hw/arm/armsse.c | 3 ++-
12
target/arm/helper.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
14
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/armsse.c
17
--- a/target/arm/helper.c
18
+++ b/hw/arm/armsse.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
19
@@ -XXX,XX +XXX,XX @@
20
qdev_get_gpio_in(dev_splitter, 0));
20
#include "hw/irq.h"
21
qdev_connect_gpio_out(dev_splitter, 0,
21
#include "sysemu/cpu-timers.h"
22
qdev_get_gpio_in_named(dev_secctl,
22
#include "sysemu/kvm.h"
23
- "mpc_status", 0));
23
+#include "sysemu/tcg.h"
24
+ "mpc_status",
24
#include "qapi/qapi-commands-machine-target.h"
25
+ i - IOTS_NUM_EXP_MPC));
25
#include "qapi/error.h"
26
}
26
#include "qemu/guest-random.h"
27
27
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
28
qdev_connect_gpio_out(dev_splitter, 1,
28
env->exception.syndrome);
29
}
30
31
- if (arm_is_psci_call(cpu, cs->exception_index)) {
32
+ if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
33
arm_handle_psci_call(cpu);
34
qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
35
return;
29
--
36
--
30
2.20.1
37
2.34.1
31
38
32
39
diff view generated by jsdifflib
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Claudio Fontana <cfontana@suse.de>
2
2
3
Fix code style. Operator needs spaces both sides.
3
Signed-off-by: Claudio Fontana <cfontana@suse.de>
4
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
5
Signed-off-by: Fabiano Rosas <farosas@suse.de>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
6
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
target/arm/arch_dump.c | 8 ++++----
9
target/arm/helper.c | 12 +++++++-----
12
target/arm/arm-semi.c | 8 ++++----
10
1 file changed, 7 insertions(+), 5 deletions(-)
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
15
11
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/arch_dump.c
19
+++ b/target/arm/arch_dump.c
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
21
22
for (i = 0; i < 32; ++i) {
23
uint64_t *q = aa64_vfp_qreg(env, i);
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
28
}
29
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
32
*/
33
for (i = 0; i < 32; ++i) {
34
uint64_t tmp = note.vfp.vregs[2*i];
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
36
- note.vfp.vregs[2*i+1] = tmp;
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
38
+ note.vfp.vregs[2 * i + 1] = tmp;
39
}
40
}
41
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/arm-semi.c
45
+++ b/target/arm/arm-semi.c
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
47
if (use_gdb_syscalls()) {
48
arm_semi_open_guestfd = guestfd;
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
83
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/helper.c
14
--- a/target/arm/helper.c
85
+++ b/target/arm/helper.c
15
+++ b/target/arm/helper.c
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
16
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
87
uint32_t sum;
17
unsigned int cur_el = arm_current_el(env);
88
sum = do_usad(a, b);
18
int rt;
89
sum += do_usad(a >> 8, b >> 8);
19
90
- sum += do_usad(a >> 16, b >>16);
20
- /*
91
+ sum += do_usad(a >> 16, b >> 16);
21
- * Note that new_el can never be 0. If cur_el is 0, then
92
sum += do_usad(a >> 24, b >> 24);
22
- * el0_a64 is is_a64(), else el0_a64 is ignored.
93
return sum;
23
- */
94
}
24
- aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
25
+ if (tcg_enabled()) {
26
+ /*
27
+ * Note that new_el can never be 0. If cur_el is 0, then
28
+ * el0_a64 is is_a64(), else el0_a64 is ignored.
29
+ */
30
+ aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
31
+ }
32
33
if (cur_el < new_el) {
34
/*
95
--
35
--
96
2.20.1
36
2.34.1
97
37
98
38
diff view generated by jsdifflib
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
1
From: Fabiano Rosas <farosas@suse.de>
2
check, except in special cases. Move a stray UNDEF check in the VTBL
3
trans function up above the access check.
4
2
3
Move this earlier to make the next patch diff cleaner. While here
4
update the comment slightly to not give the impression that the
5
misalignment affects only TCG.
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
8
---
12
---
9
target/arm/translate-neon.c.inc | 8 ++++----
13
target/arm/machine.c | 18 +++++++++---------
10
1 file changed, 4 insertions(+), 4 deletions(-)
14
1 file changed, 9 insertions(+), 9 deletions(-)
11
15
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
16
diff --git a/target/arm/machine.c b/target/arm/machine.c
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate-neon.c.inc
18
--- a/target/arm/machine.c
15
+++ b/target/arm/translate-neon.c.inc
19
+++ b/target/arm/machine.c
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
20
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
17
return false;
21
}
18
}
22
}
19
23
20
- if (!vfp_access_check(s)) {
24
+ /*
21
- return true;
25
+ * Misaligned thumb pc is architecturally impossible. Fail the
26
+ * incoming migration. For TCG it would trigger the assert in
27
+ * thumb_tr_translate_insn().
28
+ */
29
+ if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
30
+ return -1;
31
+ }
32
+
33
hw_breakpoint_update_all(cpu);
34
hw_watchpoint_update_all(cpu);
35
36
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
37
}
38
}
39
40
- /*
41
- * Misaligned thumb pc is architecturally impossible.
42
- * We have an assert in thumb_tr_translate_insn to verify this.
43
- * Fail an incoming migrate to avoid this assert.
44
- */
45
- if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
46
- return -1;
22
- }
47
- }
23
-
48
-
24
if ((a->vn + a->len + 1) > 32) {
49
if (!kvm_enabled()) {
25
/*
50
pmu_op_finish(&cpu->env);
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
28
return false;
29
}
51
}
30
31
+ if (!vfp_access_check(s)) {
32
+ return true;
33
+ }
34
+
35
desc = tcg_const_i32((a->vn << 2) | a->len);
36
def = tcg_temp_new_i64();
37
if (a->op) {
38
--
52
--
39
2.20.1
53
2.34.1
40
54
41
55
diff view generated by jsdifflib
New patch
1
1
From: Fabiano Rosas <farosas@suse.de>
2
3
Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
4
a cpregs.h header which is more suitable for this code.
5
6
Code moved verbatim.
7
8
Signed-off-by: Fabiano Rosas <farosas@suse.de>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
15
target/arm/cpu.h | 91 -----------------------------------------
16
2 files changed, 98 insertions(+), 91 deletions(-)
17
18
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpregs.h
21
+++ b/target/arm/cpregs.h
22
@@ -XXX,XX +XXX,XX @@ enum {
23
ARM_CP_SME = 1 << 19,
24
};
25
26
+/*
27
+ * Interface for defining coprocessor registers.
28
+ * Registers are defined in tables of arm_cp_reginfo structs
29
+ * which are passed to define_arm_cp_regs().
30
+ */
31
+
32
+/*
33
+ * When looking up a coprocessor register we look for it
34
+ * via an integer which encodes all of:
35
+ * coprocessor number
36
+ * Crn, Crm, opc1, opc2 fields
37
+ * 32 or 64 bit register (ie is it accessed via MRC/MCR
38
+ * or via MRRC/MCRR?)
39
+ * non-secure/secure bank (AArch32 only)
40
+ * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
41
+ * (In this case crn and opc2 should be zero.)
42
+ * For AArch64, there is no 32/64 bit size distinction;
43
+ * instead all registers have a 2 bit op0, 3 bit op1 and op2,
44
+ * and 4 bit CRn and CRm. The encoding patterns are chosen
45
+ * to be easy to convert to and from the KVM encodings, and also
46
+ * so that the hashtable can contain both AArch32 and AArch64
47
+ * registers (to allow for interprocessing where we might run
48
+ * 32 bit code on a 64 bit core).
49
+ */
50
+/*
51
+ * This bit is private to our hashtable cpreg; in KVM register
52
+ * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
53
+ * in the upper bits of the 64 bit ID.
54
+ */
55
+#define CP_REG_AA64_SHIFT 28
56
+#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
57
+
58
+/*
59
+ * To enable banking of coprocessor registers depending on ns-bit we
60
+ * add a bit to distinguish between secure and non-secure cpregs in the
61
+ * hashtable.
62
+ */
63
+#define CP_REG_NS_SHIFT 29
64
+#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
65
+
66
+#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
67
+ ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
68
+ ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
69
+
70
+#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
71
+ (CP_REG_AA64_MASK | \
72
+ ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
73
+ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
74
+ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
75
+ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
76
+ ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
77
+ ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
78
+
79
+/*
80
+ * Convert a full 64 bit KVM register ID to the truncated 32 bit
81
+ * version used as a key for the coprocessor register hashtable
82
+ */
83
+static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
84
+{
85
+ uint32_t cpregid = kvmid;
86
+ if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
87
+ cpregid |= CP_REG_AA64_MASK;
88
+ } else {
89
+ if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
90
+ cpregid |= (1 << 15);
91
+ }
92
+
93
+ /*
94
+ * KVM is always non-secure so add the NS flag on AArch32 register
95
+ * entries.
96
+ */
97
+ cpregid |= 1 << CP_REG_NS_SHIFT;
98
+ }
99
+ return cpregid;
100
+}
101
+
102
+/*
103
+ * Convert a truncated 32 bit hashtable key into the full
104
+ * 64 bit KVM register ID.
105
+ */
106
+static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
107
+{
108
+ uint64_t kvmid;
109
+
110
+ if (cpregid & CP_REG_AA64_MASK) {
111
+ kvmid = cpregid & ~CP_REG_AA64_MASK;
112
+ kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
113
+ } else {
114
+ kvmid = cpregid & ~(1 << 15);
115
+ if (cpregid & (1 << 15)) {
116
+ kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
117
+ } else {
118
+ kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
119
+ }
120
+ }
121
+ return kvmid;
122
+}
123
+
124
/*
125
* Valid values for ARMCPRegInfo state field, indicating which of
126
* the AArch32 and AArch64 execution states this register is visible in.
127
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
128
index XXXXXXX..XXXXXXX 100644
129
--- a/target/arm/cpu.h
130
+++ b/target/arm/cpu.h
131
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
132
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
133
uint32_t cur_el, bool secure);
134
135
-/* Interface for defining coprocessor registers.
136
- * Registers are defined in tables of arm_cp_reginfo structs
137
- * which are passed to define_arm_cp_regs().
138
- */
139
-
140
-/* When looking up a coprocessor register we look for it
141
- * via an integer which encodes all of:
142
- * coprocessor number
143
- * Crn, Crm, opc1, opc2 fields
144
- * 32 or 64 bit register (ie is it accessed via MRC/MCR
145
- * or via MRRC/MCRR?)
146
- * non-secure/secure bank (AArch32 only)
147
- * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
148
- * (In this case crn and opc2 should be zero.)
149
- * For AArch64, there is no 32/64 bit size distinction;
150
- * instead all registers have a 2 bit op0, 3 bit op1 and op2,
151
- * and 4 bit CRn and CRm. The encoding patterns are chosen
152
- * to be easy to convert to and from the KVM encodings, and also
153
- * so that the hashtable can contain both AArch32 and AArch64
154
- * registers (to allow for interprocessing where we might run
155
- * 32 bit code on a 64 bit core).
156
- */
157
-/* This bit is private to our hashtable cpreg; in KVM register
158
- * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
159
- * in the upper bits of the 64 bit ID.
160
- */
161
-#define CP_REG_AA64_SHIFT 28
162
-#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
163
-
164
-/* To enable banking of coprocessor registers depending on ns-bit we
165
- * add a bit to distinguish between secure and non-secure cpregs in the
166
- * hashtable.
167
- */
168
-#define CP_REG_NS_SHIFT 29
169
-#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
170
-
171
-#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
172
- ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
173
- ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
174
-
175
-#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
176
- (CP_REG_AA64_MASK | \
177
- ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
178
- ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
179
- ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
180
- ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
181
- ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
182
- ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
183
-
184
-/* Convert a full 64 bit KVM register ID to the truncated 32 bit
185
- * version used as a key for the coprocessor register hashtable
186
- */
187
-static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
188
-{
189
- uint32_t cpregid = kvmid;
190
- if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
191
- cpregid |= CP_REG_AA64_MASK;
192
- } else {
193
- if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
194
- cpregid |= (1 << 15);
195
- }
196
-
197
- /* KVM is always non-secure so add the NS flag on AArch32 register
198
- * entries.
199
- */
200
- cpregid |= 1 << CP_REG_NS_SHIFT;
201
- }
202
- return cpregid;
203
-}
204
-
205
-/* Convert a truncated 32 bit hashtable key into the full
206
- * 64 bit KVM register ID.
207
- */
208
-static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
209
-{
210
- uint64_t kvmid;
211
-
212
- if (cpregid & CP_REG_AA64_MASK) {
213
- kvmid = cpregid & ~CP_REG_AA64_MASK;
214
- kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
215
- } else {
216
- kvmid = cpregid & ~(1 << 15);
217
- if (cpregid & (1 << 15)) {
218
- kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
219
- } else {
220
- kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
221
- }
222
- }
223
- return kvmid;
224
-}
225
-
226
/* Return the highest implemented Exception Level */
227
static inline int arm_highest_el(CPUARMState *env)
228
{
229
--
230
2.34.1
231
232
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
The helper function did not get updated when we reorganized
3
If a test was tagged with the "accel" tag and the specified
4
the vector register file for SVE. Since then, the neon dregs
4
accelerator it not present in the qemu binary, cancel the test.
5
are non-sequential and cannot be simply indexed.
6
5
7
At the same time, make the helper function operate on 64-bit
6
We can now write tests without explicit calls to require_accelerator,
8
quantities so that we do not have to call it twice.
7
just the tag is enough.
9
8
10
Fixes: c39c2b9043e
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
13
---
18
target/arm/helper.h | 2 +-
14
tests/avocado/avocado_qemu/__init__.py | 4 ++++
19
target/arm/op_helper.c | 23 +++++++++--------
15
1 file changed, 4 insertions(+)
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
21
3 files changed, 29 insertions(+), 40 deletions(-)
22
16
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
17
diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
24
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper.h
19
--- a/tests/avocado/avocado_qemu/__init__.py
26
+++ b/target/arm/helper.h
20
+++ b/tests/avocado/avocado_qemu/__init__.py
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
21
@@ -XXX,XX +XXX,XX @@ def setUp(self):
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
22
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
23
super().setUp('qemu-system-')
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
24
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
25
+ accel_required = self._get_unique_tag_val('accel')
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
26
+ if accel_required:
33
27
+ self.require_accelerator(accel_required)
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
41
cpu_loop_exit_restore(cs, ra);
42
}
43
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
45
- uint32_t maxindex)
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
47
+ uint64_t ireg, uint64_t def)
48
{
49
- uint32_t val, shift;
50
- uint64_t *table = vn;
51
+ uint64_t tmp, val = 0;
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
53
+ uint32_t base_reg = desc >> 2;
54
+ uint32_t shift, index, reg;
55
56
- val = 0;
57
- for (shift = 0; shift < 32; shift += 8) {
58
- uint32_t index = (ireg >> shift) & 0xff;
59
+ for (shift = 0; shift < 64; shift += 8) {
60
+ index = (ireg >> shift) & 0xff;
61
if (index < maxindex) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
63
- val |= tmp << shift;
64
+ reg = base_reg + (index >> 3);
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
110
- }
111
- tmp2 = tcg_temp_new_i32();
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
113
- ptr1 = vfp_reg_ptr(true, a->vn);
114
- tmp4 = tcg_const_i32(n);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
122
} else {
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
125
}
126
- tmp3 = tcg_temp_new_i32();
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
129
- tcg_temp_free_i32(tmp);
130
- tcg_temp_free_i32(tmp4);
131
- tcg_temp_free_ptr(ptr1);
132
+ val = tcg_temp_new_i64();
133
+ read_neon_element64(val, a->vm, 0, MO_64);
134
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
137
- tcg_temp_free_i32(tmp2);
138
- tcg_temp_free_i32(tmp3);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
140
+ write_neon_element64(val, a->vd, 0, MO_64);
141
+
28
+
142
+ tcg_temp_free_i64(def);
29
self.machine = self.params.get('machine',
143
+ tcg_temp_free_i64(val);
30
default=self._get_unique_tag_val('machine'))
144
+ tcg_temp_free_i32(desc);
145
return true;
146
}
147
31
148
--
32
--
149
2.20.1
33
2.34.1
150
34
151
35
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
When using a Cortex-A15, the Virt machine does not use any
3
This allows the test to be skipped when TCG is not present in the QEMU
4
MPCore peripherals. Remove the dependency.
4
binary.
5
5
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
hw/arm/Kconfig | 1 -
11
tests/avocado/boot_linux_console.py | 1 +
14
1 file changed, 1 deletion(-)
12
tests/avocado/reverse_debugging.py | 8 ++++++++
13
2 files changed, 9 insertions(+)
15
14
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
15
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Kconfig
17
--- a/tests/avocado/boot_linux_console.py
19
+++ b/hw/arm/Kconfig
18
+++ b/tests/avocado/boot_linux_console.py
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
19
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
21
imply VFIO_PLATFORM
20
22
imply VFIO_XGMAC
21
def test_aarch64_raspi3_atf(self):
23
imply TPM_TIS_SYSBUS
22
"""
24
- select A15MPCORE
23
+ :avocado: tags=accel:tcg
25
select ACPI
24
:avocado: tags=arch:aarch64
26
select ARM_SMMUV3
25
:avocado: tags=machine:raspi3b
27
select GPIO_KEY
26
:avocado: tags=cpu:cortex-a53
27
diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
28
index XXXXXXX..XXXXXXX 100644
29
--- a/tests/avocado/reverse_debugging.py
30
+++ b/tests/avocado/reverse_debugging.py
31
@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
32
vm.shutdown()
33
34
class ReverseDebugging_X86_64(ReverseDebugging):
35
+ """
36
+ :avocado: tags=accel:tcg
37
+ """
38
+
39
REG_PC = 0x10
40
REG_CS = 0x12
41
def get_pc(self, g):
42
@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
43
self.reverse_debugging()
44
45
class ReverseDebugging_AArch64(ReverseDebugging):
46
+ """
47
+ :avocado: tags=accel:tcg
48
+ """
49
+
50
REG_PC = 32
51
52
# unidentified gitlab timeout problem
28
--
53
--
29
2.20.1
54
2.34.1
30
55
31
56
diff view generated by jsdifflib
New patch
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
4
KVM-only build the 'max' cpu.
5
6
Note that we cannot use 'host' here because the qtests can run without
7
any other accelerator (than qtest) and 'host' depends on KVM being
8
enabled.
9
10
Signed-off-by: Fabiano Rosas <farosas@suse.de>
11
Acked-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/arm/virt.c | 4 ++++
16
1 file changed, 4 insertions(+)
17
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/virt.c
21
+++ b/hw/arm/virt.c
22
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
23
mc->minimum_page_bits = 12;
24
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
25
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
26
+#ifdef CONFIG_TCG
27
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
28
+#else
29
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
30
+#endif
31
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
32
mc->kvm_type = virt_kvm_type;
33
assert(!mc->get_hotplug_handler);
34
--
35
2.34.1
diff view generated by jsdifflib
New patch
1
From: Fabiano Rosas <farosas@suse.de>
1
2
3
Signed-off-by: Fabiano Rosas <farosas@suse.de>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Acked-by: Thomas Huth <thuth@redhat.com>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
9
1 file changed, 18 insertions(+), 10 deletions(-)
10
11
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tests/qtest/arm-cpu-features.c
14
+++ b/tests/qtest/arm-cpu-features.c
15
@@ -XXX,XX +XXX,XX @@
16
#define SVE_MAX_VQ 16
17
18
#define MACHINE "-machine virt,gic-version=max -accel tcg "
19
-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
20
+#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
21
#define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \
22
" 'arguments': { 'type': 'full', "
23
#define QUERY_TAIL "}}"
24
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
25
{
26
g_test_init(&argc, &argv, NULL);
27
28
- qtest_add_data_func("/arm/query-cpu-model-expansion",
29
- NULL, test_query_cpu_model_expansion);
30
+ if (qtest_has_accel("tcg")) {
31
+ qtest_add_data_func("/arm/query-cpu-model-expansion",
32
+ NULL, test_query_cpu_model_expansion);
33
+ }
34
+
35
+ if (!g_str_equal(qtest_get_arch(), "aarch64")) {
36
+ goto out;
37
+ }
38
39
/*
40
* For now we only run KVM specific tests with AArch64 QEMU in
41
* order avoid attempting to run an AArch32 QEMU with KVM on
42
* AArch64 hosts. That won't work and isn't easy to detect.
43
*/
44
- if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
45
+ if (qtest_has_accel("kvm")) {
46
/*
47
* This tests target the 'host' CPU type, so register it only if
48
* KVM is available.
49
*/
50
qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
51
NULL, test_query_cpu_model_expansion_kvm);
52
- }
53
54
- if (g_str_equal(qtest_get_arch(), "aarch64")) {
55
- qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
56
- NULL, sve_tests_sve_max_vq_8);
57
- qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
58
- NULL, sve_tests_sve_off);
59
qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
60
NULL, sve_tests_sve_off_kvm);
61
}
62
63
+ if (qtest_has_accel("tcg")) {
64
+ qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
65
+ NULL, sve_tests_sve_max_vq_8);
66
+ qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
67
+ NULL, sve_tests_sve_off);
68
+ }
69
+
70
+out:
71
return g_test_run();
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}
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--
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2.34.1
diff view generated by jsdifflib
New patch
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From: Fabiano Rosas <farosas@suse.de>
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These tests set -accel tcg, so restrict them to when TCG is present.
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Signed-off-by: Fabiano Rosas <farosas@suse.de>
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Acked-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Thomas Huth <thuth@redhat.com>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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tests/qtest/meson.build | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
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index XXXXXXX..XXXXXXX 100644
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--- a/tests/qtest/meson.build
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+++ b/tests/qtest/meson.build
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@@ -XXX,XX +XXX,XX @@ qtests_arm = \
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# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
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qtests_aarch64 = \
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(cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \
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- (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \
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- (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \
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+ (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \
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+ ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \
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(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
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(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
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['arm-cpu-features',
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--
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2.34.1
diff view generated by jsdifflib