[PULL 00/16] target-arm queue
[PULL 00/26] target-arm queue
1
Patches for rc1: nothing major, just some minor bugfixes and
1
The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:
2
code cleanups.
3
2
4
-- PMM
3
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging (2022-03-02 12:38:46 +0000)
5
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
7
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
9
4
10
are available in the Git repository at:
5
are available in the Git repository at:
11
6
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220302
13
8
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
9
for you to fetch changes up to 268c11984e67867c22f53beb3c7f8b98900d66b2:
15
10
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
11
ui/cocoa.m: Remove unnecessary NSAutoreleasePools (2022-03-02 19:27:37 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
15
* mps3-an547: Add missing user ahb interfaces
21
* Minor coding style fixes
16
* hw/arm/mps2-tz.c: Update AN547 documentation URL
22
* docs: add some notes on the sbsa-ref machine
17
* hw/input/tsc210x: Don't abort on bad SPI word widths
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
18
* hw/i2c: flatten pca954x mux device
24
* target/arm: Fix neon VTBL/VTBX for len > 1
19
* target/arm: Support PSCI 1.1 and SMCCC 1.0
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
20
* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
21
* tests/qtest: add qtests for npcm7xx sdhci
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
22
* Implement FEAT_LVA
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
23
* Implement FEAT_LPA
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
24
* Implement FEAT_LPA2 (but do not enable it yet)
30
* hw/arm/nseries: Check return value from load_image_targphys()
25
* Report KVM's actual PSCI version to guest in dtb
31
* tests/qtest/npcm7xx_rng-test: count runs properly
26
* ui/cocoa.m: Fix updateUIInfo threading issues
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
27
* ui/cocoa.m: Remove unnecessary NSAutoreleasePools
33
28
34
----------------------------------------------------------------
29
----------------------------------------------------------------
35
Alex Bennée (1):
30
Akihiko Odaki (1):
36
docs: add some notes on the sbsa-ref machine
31
target/arm: Support PSCI 1.1 and SMCCC 1.0
37
32
38
AlexChen (1):
33
Jimmy Brisson (1):
39
ssi: Fix bad printf format specifiers
34
mps3-an547: Add missing user ahb interfaces
40
35
41
Andrew Jones (1):
36
Patrick Venture (1):
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
37
hw/i2c: flatten pca954x mux device
43
38
44
Havard Skinnemoen (1):
39
Peter Maydell (5):
45
tests/qtest/npcm7xx_rng-test: count runs properly
40
hw/arm/mps2-tz.c: Update AN547 documentation URL
41
hw/input/tsc210x: Don't abort on bad SPI word widths
42
target/arm: Report KVM's actual PSCI version to guest in dtb
43
ui/cocoa.m: Fix updateUIInfo threading issues
44
ui/cocoa.m: Remove unnecessary NSAutoreleasePools
46
45
47
Peter Maydell (2):
46
Richard Henderson (16):
48
hw/arm/nseries: Check return value from load_image_targphys()
47
hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
48
target/arm: Set TCR_EL1.TSZ for user-only
49
target/arm: Fault on invalid TCR_ELx.TxSZ
50
target/arm: Move arm_pamax out of line
51
target/arm: Pass outputsize down to check_s2_mmu_setup
52
target/arm: Use MAKE_64BIT_MASK to compute indexmask
53
target/arm: Honor TCR_ELx.{I}PS
54
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
55
target/arm: Implement FEAT_LVA
56
target/arm: Implement FEAT_LPA
57
target/arm: Extend arm_fi_to_lfsc to level -1
58
target/arm: Introduce tlbi_aa64_get_range
59
target/arm: Fix TLBIRange.base for 16k and 64k pages
60
target/arm: Validate tlbi TG matches translation granule in use
61
target/arm: Advertise all page sizes for -cpu max
62
target/arm: Implement FEAT_LPA2
50
63
51
Philippe Mathieu-Daudé (6):
64
Shengtan Mao (1):
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
65
tests/qtest: add qtests for npcm7xx sdhci
53
hw/arm/armsse: Correct expansion MPC interrupt lines
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
58
66
59
Richard Henderson (1):
67
Wentao_Liang (1):
60
target/arm: Fix neon VTBL/VTBX for len > 1
68
target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
61
69
62
Xinhao Zhang (3):
70
docs/system/arm/emulation.rst | 3 +
63
target/arm: add spaces around operator
71
include/hw/registerfields.h | 48 +++++-
64
target/arm: Don't use '#' flag of printf format
72
target/arm/cpu-param.h | 4 +-
65
target/arm: add space before the open parenthesis '('
73
target/arm/cpu.h | 27 ++++
66
74
target/arm/internals.h | 58 ++++---
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
75
target/arm/kvm-consts.h | 14 +-
68
docs/system/target-arm.rst | 1 +
76
hw/arm/boot.c | 11 +-
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
77
hw/arm/mps2-tz.c | 6 +-
70
target/arm/helper.h | 2 +-
78
hw/i2c/i2c_mux_pca954x.c | 77 ++-------
71
hw/arm/armsse.c | 3 +-
79
hw/input/tsc210x.c | 8 +-
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
80
target/arm/cpu.c | 8 +-
73
hw/arm/nseries.c | 26 ++++++++----------
81
target/arm/cpu64.c | 7 +-
74
hw/arm/stm32f205_soc.c | 1 -
82
target/arm/helper.c | 332 ++++++++++++++++++++++++++++++---------
75
hw/misc/stm32f2xx_syscfg.c | 2 --
83
target/arm/hvf/hvf.c | 27 +++-
76
hw/ssi/imx_spi.c | 2 +-
84
target/arm/kvm64.c | 14 +-
77
hw/ssi/xilinx_spi.c | 2 +-
85
target/arm/psci.c | 35 ++++-
78
target/arm/arch_dump.c | 8 +++---
86
target/arm/translate-a64.c | 2 +-
79
target/arm/arm-semi.c | 8 +++---
87
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++
80
target/arm/helper.c | 2 +-
88
tests/qtest/meson.build | 1 +
81
target/arm/op_helper.c | 23 +++++++++-------
89
ui/cocoa.m | 31 ++--
82
target/arm/translate-a64.c | 4 +--
90
20 files changed, 736 insertions(+), 192 deletions(-)
83
target/arm/translate.c | 2 +-
91
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
85
hw/arm/Kconfig | 3 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
87
20 files changed, 123 insertions(+), 98 deletions(-)
88
create mode 100644 docs/system/arm/sbsa.rst
89
diff view generated by jsdifflib
[PULL 15/16] tests/qtest/npcm7xx_rng-test: count runs properly
[PULL 01/26] mps3-an547: Add missing user ahb interfaces
1
From: Havard Skinnemoen <hskinnemoen@google.com>
1
From: Jimmy Brisson <jimmy.brisson@linaro.org>
2
2
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
3
With these interfaces missing, TFM would delegate peripherals 0, 1,
4
plus one. Currently, it's counting the number of times these transitions
4
2, 3 and 8, and qemu would ignore the delegation of interface 8, as
5
do _not_ happen, plus one.
5
it thought interface 4 was eth & USB.
6
6
7
Source:
7
This patch corrects this behavior and allows TFM to delegate the
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
8
eth & USB peripheral to NS mode.
9
section 2.3.4 point (3).
10
9
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
10
(The old QEMU behaviour was based on revision B of the AN547
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
11
appnote; revision C corrects this error in the documentation,
12
and this commit brings QEMU in to line with how the FPGA
13
image really behaves.)
14
15
Signed-off-by: Jimmy Brisson <jimmy.brisson@linaro.org>
16
Message-id: 20220210210227.3203883-1-jimmy.brisson@linaro.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
[PMM: added commit message note clarifying that the old behaviour
19
was a docs issue, not because there were two different versions
20
of the FPGA image]
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
22
---
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
23
hw/arm/mps2-tz.c | 4 ++++
17
1 file changed, 1 insertion(+), 1 deletion(-)
24
1 file changed, 4 insertions(+)
18
25
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
26
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
20
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
21
--- a/tests/qtest/npcm7xx_rng-test.c
28
--- a/hw/arm/mps2-tz.c
22
+++ b/tests/qtest/npcm7xx_rng-test.c
29
+++ b/hw/arm/mps2-tz.c
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
30
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
24
pi = (double)nr_ones / nr_bits;
31
{ "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
25
32
{ "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
26
for (k = 0; k < nr_bits - 1; k++) {
33
{ "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
34
+ { /* port 4 USER AHB interface 0 */ },
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
35
+ { /* port 5 USER AHB interface 1 */ },
29
}
36
+ { /* port 6 USER AHB interface 2 */ },
30
vn_obs += 1;
37
+ { /* port 7 USER AHB interface 3 */ },
31
38
{ "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } },
39
},
40
},
32
--
41
--
33
2.20.1
42
2.25.1
34
35
diff view generated by jsdifflib
[PULL 14/16] hw/arm/nseries: Check return value from load_image_targphys()
[PULL 02/26] hw/arm/mps2-tz.c: Update AN547 documentation URL
1
The nseries machines have a codepath that allows them to load a
1
The AN547 application note URL has changed: update our comment
2
secondary bootloader. This code wasn't checking that the
2
accordingly. (Rev B is still downloadable from the old URL,
3
load_image_targphys() succeeded. Check the return value and report
3
but there is a new Rev C of the document now.)
4
the error to the user.
5
4
6
While we're in the vicinity, fix the comment style of the
7
comment documenting what this image load is doing.
8
9
Fixes: Coverity CID 1192904
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220221094144.426191-1-peter.maydell@linaro.org
13
---
9
---
14
hw/arm/nseries.c | 15 +++++++++++----
10
hw/arm/mps2-tz.c | 2 +-
15
1 file changed, 11 insertions(+), 4 deletions(-)
11
1 file changed, 1 insertion(+), 1 deletion(-)
16
12
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/nseries.c
15
--- a/hw/arm/mps2-tz.c
20
+++ b/hw/arm/nseries.c
16
+++ b/hw/arm/mps2-tz.c
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
17
@@ -XXX,XX +XXX,XX @@
22
/* No, wait, better start at the ROM. */
18
* Application Note AN524:
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
19
* https://developer.arm.com/documentation/dai0524/latest/
24
20
* Application Note AN547:
25
- /* This is intended for loading the `secondary.bin' program from
21
- * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf
26
+ /*
22
+ * https://developer.arm.com/documentation/dai0547/latest/
27
+ * This is intended for loading the `secondary.bin' program from
23
*
28
* Nokia images (the NOLO bootloader). The entry point seems
24
* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
29
* to be at OMAP2_Q2_BASE + 0x400000.
25
* (ARM ECM0601256) for the details of some of the device layout:
30
*
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
33
*
34
* The code above is for loading the `zImage' file from Nokia
35
- * images. */
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
37
- machine->ram_size - 0x400000);
38
+ * images.
39
+ */
40
+ if (load_image_targphys(option_rom[0].name,
41
+ OMAP2_Q2_BASE + 0x400000,
42
+ machine->ram_size - 0x400000) < 0) {
43
+ error_report("Failed to load secondary bootloader %s",
44
+ option_rom[0].name);
45
+ exit(EXIT_FAILURE);
46
+ }
47
48
n800_setup_nolo_tags(nolo_tags);
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
50
--
26
--
51
2.20.1
27
2.25.1
52
28
53
29
diff view generated by jsdifflib
[PULL 05/16] target/arm: add space before the open parenthesis '('
[PULL 03/26] hw/input/tsc210x: Don't abort on bad SPI word widths
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
The tsc210x doesn't support anything other than 16-bit reads on the
2
SPI bus, but the guest can program the SPI controller to attempt
3
them anyway. If this happens, don't abort QEMU, just log this as
4
a guest error.
2
5
3
Fix code style. Space required before the open parenthesis '('.
6
This fixes our machine_arm_n8x0.py:N8x0Machine.test_n800
7
acceptance test, which hits this assertion.
4
8
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
9
The reason we hit the assertion is because the guest kernel thinks
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
10
there is a TSC2005 on this SPI bus address, not a TSC210x. (The n810
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
11
*does* have a TSC2005 at this address.) The TSC2005 supports the
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
24-bit accesses which the guest driver makes, and the TSC210x does
13
not (that is, our TSC210x emulation is not missing support for a word
14
width the hardware can handle). It's not clear whether the problem
15
here is that the guest kernel incorrectly thinks the n800 has the
16
same device at this SPI bus address as the n810, or that QEMU's n810
17
board model doesn't get the SPI devices right. At this late date
18
there no longer appears to be any reliable information on the web
19
about the hardware behaviour, but I am inclined to think this is a
20
guest kernel bug. In any case, we prefer not to abort QEMU for
21
guest-triggerable conditions, so logging the error is the right thing
22
to do.
23
24
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/736
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
27
Message-id: 20220221140750.514557-1-peter.maydell@linaro.org
10
---
28
---
11
target/arm/translate.c | 2 +-
29
hw/input/tsc210x.c | 8 ++++++--
12
1 file changed, 1 insertion(+), 1 deletion(-)
30
1 file changed, 6 insertions(+), 2 deletions(-)
13
31
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
32
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
15
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
34
--- a/hw/input/tsc210x.c
17
+++ b/target/arm/translate.c
35
+++ b/hw/input/tsc210x.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
36
@@ -XXX,XX +XXX,XX @@
19
- Hardware watchpoints.
37
#include "hw/hw.h"
20
Hardware breakpoints have already been handled and skip this code.
38
#include "audio/audio.h"
21
*/
39
#include "qemu/timer.h"
22
- switch(dc->base.is_jmp) {
40
+#include "qemu/log.h"
23
+ switch (dc->base.is_jmp) {
41
#include "sysemu/reset.h"
24
case DISAS_NEXT:
42
#include "ui/console.h"
25
case DISAS_TOO_MANY:
43
#include "hw/arm/omap.h" /* For I2SCodec */
26
gen_goto_tb(dc, 1, dc->base.pc_next);
44
@@ -XXX,XX +XXX,XX @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
45
TSC210xState *s = opaque;
46
uint32_t ret = 0;
47
48
- if (len != 16)
49
- hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len);
50
+ if (len != 16) {
51
+ qemu_log_mask(LOG_GUEST_ERROR,
52
+ "%s: bad SPI word width %i\n", __func__, len);
53
+ return 0;
54
+ }
55
56
/* TODO: sequential reads etc - how do we make sure the host doesn't
57
* unintentionally read out a conversion result from a register while
27
--
58
--
28
2.20.1
59
2.25.1
29
60
30
61
diff view generated by jsdifflib
[PULL 02/16] ssi: Fix bad printf format specifiers
[PULL 04/26] hw/i2c: flatten pca954x mux device
1
From: AlexChen <alex.chen@huawei.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
We should use printf format specifier "%u" instead of "%d" for
3
Previously this device created N subdevices which each owned an i2c bus.
4
argument of type "unsigned int".
4
Now this device simply owns the N i2c busses directly.
5
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
6
Tested: Verified devices behind mux are still accessible via qmp and i2c
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
7
from within an arm32 SoC.
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
9
Message-id: 5FA280F5.8060902@huawei.com
9
Reviewed-by: Hao Wu <wuhaotsh@google.com>
10
Signed-off-by: Patrick Venture <venture@google.com>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20220202164533.1283668-1-venture@google.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
15
---
12
hw/ssi/imx_spi.c | 2 +-
16
hw/i2c/i2c_mux_pca954x.c | 77 +++++++---------------------------------
13
hw/ssi/xilinx_spi.c | 2 +-
17
1 file changed, 13 insertions(+), 64 deletions(-)
14
2 files changed, 2 insertions(+), 2 deletions(-)
15
18
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
19
diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/imx_spi.c
21
--- a/hw/i2c/i2c_mux_pca954x.c
19
+++ b/hw/ssi/imx_spi.c
22
+++ b/hw/i2c/i2c_mux_pca954x.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
23
@@ -XXX,XX +XXX,XX @@
21
case ECSPI_MSGDATA:
24
#define PCA9548_CHANNEL_COUNT 8
22
return "ECSPI_MSGDATA";
25
#define PCA9546_CHANNEL_COUNT 4
23
default:
26
24
- sprintf(unknown, "%d ?", reg);
27
-/*
25
+ sprintf(unknown, "%u ?", reg);
28
- * struct Pca954xChannel - The i2c mux device will have N of these states
26
return unknown;
29
- * that own the i2c channel bus.
30
- * @bus: The owned channel bus.
31
- * @enabled: Is this channel active?
32
- */
33
-typedef struct Pca954xChannel {
34
- SysBusDevice parent;
35
-
36
- I2CBus *bus;
37
-
38
- bool enabled;
39
-} Pca954xChannel;
40
-
41
-#define TYPE_PCA954X_CHANNEL "pca954x-channel"
42
-#define PCA954X_CHANNEL(obj) \
43
- OBJECT_CHECK(Pca954xChannel, (obj), TYPE_PCA954X_CHANNEL)
44
-
45
/*
46
* struct Pca954xState - The pca954x state object.
47
* @control: The value written to the mux control.
48
@@ -XXX,XX +XXX,XX @@ typedef struct Pca954xState {
49
50
uint8_t control;
51
52
- /* The channel i2c buses. */
53
- Pca954xChannel channel[PCA9548_CHANNEL_COUNT];
54
+ bool enabled[PCA9548_CHANNEL_COUNT];
55
+ I2CBus *bus[PCA9548_CHANNEL_COUNT];
56
} Pca954xState;
57
58
/*
59
@@ -XXX,XX +XXX,XX @@ static bool pca954x_match(I2CSlave *candidate, uint8_t address,
60
}
61
62
for (i = 0; i < mc->nchans; i++) {
63
- if (!mux->channel[i].enabled) {
64
+ if (!mux->enabled[i]) {
65
continue;
66
}
67
68
- if (i2c_scan_bus(mux->channel[i].bus, address, broadcast,
69
+ if (i2c_scan_bus(mux->bus[i], address, broadcast,
70
current_devs)) {
71
if (!broadcast) {
72
return true;
73
@@ -XXX,XX +XXX,XX @@ static void pca954x_enable_channel(Pca954xState *s, uint8_t enable_mask)
74
*/
75
for (i = 0; i < mc->nchans; i++) {
76
if (enable_mask & (1 << i)) {
77
- s->channel[i].enabled = true;
78
+ s->enabled[i] = true;
79
} else {
80
- s->channel[i].enabled = false;
81
+ s->enabled[i] = false;
82
}
27
}
83
}
28
}
84
}
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
85
@@ -XXX,XX +XXX,XX @@ I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel)
30
index XXXXXXX..XXXXXXX 100644
86
Pca954xState *pca954x = PCA954X(mux);
31
--- a/hw/ssi/xilinx_spi.c
87
32
+++ b/hw/ssi/xilinx_spi.c
88
g_assert(channel < pc->nchans);
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
89
- return I2C_BUS(qdev_get_child_bus(DEVICE(&pca954x->channel[channel]),
34
irq chain unless things really changed. */
90
- "i2c-bus"));
35
if (pending != s->irqline) {
91
-}
36
s->irqline = pending;
92
-
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
93
-static void pca954x_channel_init(Object *obj)
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
94
-{
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
95
- Pca954xChannel *s = PCA954X_CHANNEL(obj);
40
qemu_set_irq(s->irq, pending);
96
- s->bus = i2c_init_bus(DEVICE(s), "i2c-bus");
97
-
98
- /* Start all channels as disabled. */
99
- s->enabled = false;
100
-}
101
-
102
-static void pca954x_channel_class_init(ObjectClass *klass, void *data)
103
-{
104
- DeviceClass *dc = DEVICE_CLASS(klass);
105
- dc->desc = "Pca954x Channel";
106
+ return pca954x->bus[channel];
107
}
108
109
static void pca9546_class_init(ObjectClass *klass, void *data)
110
@@ -XXX,XX +XXX,XX @@ static void pca9548_class_init(ObjectClass *klass, void *data)
111
s->nchans = PCA9548_CHANNEL_COUNT;
112
}
113
114
-static void pca954x_realize(DeviceState *dev, Error **errp)
115
-{
116
- Pca954xState *s = PCA954X(dev);
117
- Pca954xClass *c = PCA954X_GET_CLASS(s);
118
- int i;
119
-
120
- /* SMBus modules. Cannot fail. */
121
- for (i = 0; i < c->nchans; i++) {
122
- sysbus_realize(SYS_BUS_DEVICE(&s->channel[i]), &error_abort);
123
- }
124
-}
125
-
126
static void pca954x_init(Object *obj)
127
{
128
Pca954xState *s = PCA954X(obj);
129
Pca954xClass *c = PCA954X_GET_CLASS(obj);
130
int i;
131
132
- /* Only initialize the children we expect. */
133
+ /* SMBus modules. Cannot fail. */
134
for (i = 0; i < c->nchans; i++) {
135
- object_initialize_child(obj, "channel[*]", &s->channel[i],
136
- TYPE_PCA954X_CHANNEL);
137
+ g_autofree gchar *bus_name = g_strdup_printf("i2c.%d", i);
138
+
139
+ /* start all channels as disabled. */
140
+ s->enabled[i] = false;
141
+ s->bus[i] = i2c_init_bus(DEVICE(s), bus_name);
41
}
142
}
143
}
144
145
@@ -XXX,XX +XXX,XX @@ static void pca954x_class_init(ObjectClass *klass, void *data)
146
rc->phases.enter = pca954x_enter_reset;
147
148
dc->desc = "Pca954x i2c-mux";
149
- dc->realize = pca954x_realize;
150
151
k->write_data = pca954x_write_data;
152
k->receive_byte = pca954x_read_byte;
153
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pca954x_info[] = {
154
.parent = TYPE_PCA954X,
155
.class_init = pca9548_class_init,
156
},
157
- {
158
- .name = TYPE_PCA954X_CHANNEL,
159
- .parent = TYPE_SYS_BUS_DEVICE,
160
- .class_init = pca954x_channel_class_init,
161
- .instance_size = sizeof(Pca954xChannel),
162
- .instance_init = pca954x_channel_init,
163
- }
164
};
165
166
DEFINE_TYPES(pca954x_info)
42
--
167
--
43
2.20.1
168
2.25.1
44
169
45
170
diff view generated by jsdifflib
New patch
[PULL 05/26] target/arm: Support PSCI 1.1 and SMCCC 1.0
1
From: Akihiko Odaki <akihiko.odaki@gmail.com>
1
2
3
Support the latest PSCI on TCG and HVF. A 64-bit function called from
4
AArch32 now returns NOT_SUPPORTED, which is necessary to adhere to SMC
5
Calling Convention 1.0. It is still not compliant with SMCCC 1.3 since
6
they do not implement mandatory functions.
7
8
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
9
Message-id: 20220213035753.34577-1-akihiko.odaki@gmail.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: update MISMATCH_CHECK checks on PSCI_VERSION macros to match]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/kvm-consts.h | 13 +++++++++----
15
hw/arm/boot.c | 12 +++++++++---
16
target/arm/cpu.c | 5 +++--
17
target/arm/hvf/hvf.c | 27 ++++++++++++++++++++++++++-
18
target/arm/kvm64.c | 2 +-
19
target/arm/psci.c | 35 ++++++++++++++++++++++++++++++++---
20
6 files changed, 80 insertions(+), 14 deletions(-)
21
22
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/kvm-consts.h
25
+++ b/target/arm/kvm-consts.h
26
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE);
27
#define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4)
28
#define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5)
29
30
+#define QEMU_PSCI_1_0_FN_PSCI_FEATURES QEMU_PSCI_0_2_FN(10)
31
+
32
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND);
33
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF);
34
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON);
35
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE);
36
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND);
37
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON);
38
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE);
39
+MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES);
40
41
/* PSCI v0.2 return values used by TCG emulation of PSCI */
42
43
/* No Trusted OS migration to worry about when offlining CPUs */
44
#define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2
45
46
-/* We implement version 0.2 only */
47
-#define QEMU_PSCI_0_2_RET_VERSION_0_2 2
48
+#define QEMU_PSCI_VERSION_0_1 0x00001
49
+#define QEMU_PSCI_VERSION_0_2 0x00002
50
+#define QEMU_PSCI_VERSION_1_1 0x10001
51
52
MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
53
-MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2,
54
- (PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2)));
55
+/* We don't bother to check every possible version value */
56
+MISMATCH_CHECK(QEMU_PSCI_VERSION_0_2, PSCI_VERSION(0, 2));
57
+MISMATCH_CHECK(QEMU_PSCI_VERSION_1_1, PSCI_VERSION(1, 1));
58
59
/* PSCI return values (inclusive of all PSCI versions) */
60
#define QEMU_PSCI_RET_SUCCESS 0
61
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/boot.c
64
+++ b/hw/arm/boot.c
65
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
66
}
67
68
qemu_fdt_add_subnode(fdt, "/psci");
69
- if (armcpu->psci_version == 2) {
70
- const char comp[] = "arm,psci-0.2\0arm,psci";
71
- qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
72
+ if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 ||
73
+ armcpu->psci_version == QEMU_PSCI_VERSION_1_1) {
74
+ if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) {
75
+ const char comp[] = "arm,psci-0.2\0arm,psci";
76
+ qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
77
+ } else {
78
+ const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci";
79
+ qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
80
+ }
81
82
cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
83
if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
84
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/target/arm/cpu.c
87
+++ b/target/arm/cpu.c
88
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
89
* picky DTB consumer will also provide a helpful error message.
90
*/
91
cpu->dtb_compatible = "qemu,unknown";
92
- cpu->psci_version = 1; /* By default assume PSCI v0.1 */
93
+ cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */
94
cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
95
96
if (tcg_enabled() || hvf_enabled()) {
97
- cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */
98
+ /* TCG and HVF implement PSCI 1.1 */
99
+ cpu->psci_version = QEMU_PSCI_VERSION_1_1;
100
}
101
}
102
103
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/hvf/hvf.c
106
+++ b/target/arm/hvf/hvf.c
107
@@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu)
108
109
switch (param[0]) {
110
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
111
- ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
112
+ ret = QEMU_PSCI_VERSION_1_1;
113
break;
114
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
115
ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
116
@@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu)
117
case QEMU_PSCI_0_2_FN_MIGRATE:
118
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
119
break;
120
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
121
+ switch (param[1]) {
122
+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
123
+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
124
+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
125
+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
126
+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
127
+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
128
+ case QEMU_PSCI_0_1_FN_CPU_ON:
129
+ case QEMU_PSCI_0_2_FN_CPU_ON:
130
+ case QEMU_PSCI_0_2_FN64_CPU_ON:
131
+ case QEMU_PSCI_0_1_FN_CPU_OFF:
132
+ case QEMU_PSCI_0_2_FN_CPU_OFF:
133
+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
134
+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
135
+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
136
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
137
+ ret = 0;
138
+ break;
139
+ case QEMU_PSCI_0_1_FN_MIGRATE:
140
+ case QEMU_PSCI_0_2_FN_MIGRATE:
141
+ default:
142
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
143
+ }
144
+ break;
145
default:
146
return false;
147
}
148
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
149
index XXXXXXX..XXXXXXX 100644
150
--- a/target/arm/kvm64.c
151
+++ b/target/arm/kvm64.c
152
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
153
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
154
}
155
if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
156
- cpu->psci_version = 2;
157
+ cpu->psci_version = QEMU_PSCI_VERSION_0_2;
158
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
159
}
160
if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
161
diff --git a/target/arm/psci.c b/target/arm/psci.c
162
index XXXXXXX..XXXXXXX 100644
163
--- a/target/arm/psci.c
164
+++ b/target/arm/psci.c
165
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
166
{
167
/*
168
* This function partially implements the logic for dispatching Power State
169
- * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b),
170
+ * Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b),
171
* to the extent required for bringing up and taking down secondary cores,
172
* and for handling reset and poweroff requests.
173
* Additional information about the calling convention used is available in
174
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
175
}
176
177
if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
178
- ret = QEMU_PSCI_RET_INVALID_PARAMS;
179
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
180
goto err;
181
}
182
183
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
184
ARMCPU *target_cpu;
185
186
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
187
- ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
188
+ ret = QEMU_PSCI_VERSION_1_1;
189
break;
190
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
191
ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
192
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
193
}
194
helper_wfi(env, 4);
195
break;
196
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
197
+ switch (param[1]) {
198
+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
199
+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
200
+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
201
+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
202
+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
203
+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
204
+ case QEMU_PSCI_0_1_FN_CPU_ON:
205
+ case QEMU_PSCI_0_2_FN_CPU_ON:
206
+ case QEMU_PSCI_0_2_FN64_CPU_ON:
207
+ case QEMU_PSCI_0_1_FN_CPU_OFF:
208
+ case QEMU_PSCI_0_2_FN_CPU_OFF:
209
+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
210
+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
211
+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
212
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
213
+ if (!(param[1] & QEMU_PSCI_0_2_64BIT) || is_a64(env)) {
214
+ ret = 0;
215
+ break;
216
+ }
217
+ /* fallthrough */
218
+ case QEMU_PSCI_0_1_FN_MIGRATE:
219
+ case QEMU_PSCI_0_2_FN_MIGRATE:
220
+ default:
221
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
222
+ break;
223
+ }
224
+ break;
225
case QEMU_PSCI_0_1_FN_MIGRATE:
226
case QEMU_PSCI_0_2_FN_MIGRATE:
227
default:
228
--
229
2.25.1
diff view generated by jsdifflib
[PULL 04/16] target/arm: Don't use '#' flag of printf format
[PULL 06/26] target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Wentao_Liang <Wentao_Liang_g@163.com>
2
2
3
Fix code style. Don't use '#' flag of printf format ('%#') in
3
handle_simd_shift_fpint_conv() was accidentally freeing the TCG
4
format strings, use '0x' prefix instead
4
temporary tcg_fpstatus too early, before the last use of it. Move
5
the free down to where it belongs.
5
6
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
7
Signed-off-by: Wentao_Liang <Wentao_Liang_g@163.com>
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
9
[PMM: cleaned up commit message]
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/translate-a64.c | 4 ++--
12
target/arm/translate-a64.c | 2 +-
13
1 file changed, 2 insertions(+), 2 deletions(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
20
}
21
break;
22
default:
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
25
__func__, insn, fpopcode, s->pc_curr);
26
g_assert_not_reached();
27
}
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
29
case 0x7f: /* FSQRT (vector) */
30
break;
31
default:
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
34
g_assert_not_reached();
35
}
21
}
36
22
23
- tcg_temp_free_ptr(tcg_fpstatus);
24
tcg_temp_free_i32(tcg_shift);
25
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
26
+ tcg_temp_free_ptr(tcg_fpstatus);
27
tcg_temp_free_i32(tcg_rmode);
28
}
29
37
--
30
--
38
2.20.1
31
2.25.1
39
40
diff view generated by jsdifflib
[PULL 06/16] docs: add some notes on the sbsa-ref machine
[PULL 07/26] tests/qtest: add qtests for npcm7xx sdhci
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Shengtan Mao <stmao@google.com>
2
2
3
We should at least document what this machine is about.
3
Reviewed-by: Hao Wu <wuhaotsh@google.com>
4
4
Reviewed-by: Chris Rauer <crauer@google.com>
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
5
Signed-off-by: Shengtan Mao <stmao@google.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
7
Message-id: 20220225174451.192304-1-wuhaotsh@google.com
8
Cc: Leif Lindholm <leif@nuviainc.com>
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
[PMM: fixed filename mismatch]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
10
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++++++++
15
docs/system/target-arm.rst | 1 +
11
tests/qtest/meson.build | 1 +
16
2 files changed, 33 insertions(+)
12
2 files changed, 216 insertions(+)
17
create mode 100644 docs/system/arm/sbsa.rst
13
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
18
14
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
15
diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c
20
new file mode 100644
16
new file mode 100644
21
index XXXXXXX..XXXXXXX
17
index XXXXXXX..XXXXXXX
22
--- /dev/null
18
--- /dev/null
23
+++ b/docs/system/arm/sbsa.rst
19
+++ b/tests/qtest/npcm7xx_sdhci-test.c
24
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
21
+/*
26
+==================================================================
22
+ * QTests for NPCM7xx SD-3.0 / MMC-4.51 Host Controller
27
+
23
+ *
28
+While the `virt` board is a generic board platform that doesn't match
24
+ * Copyright (c) 2022 Google LLC
29
+any real hardware the `sbsa-ref` board intends to look like real
25
+ *
30
+hardware. The `Server Base System Architecture
26
+ * This program is free software; you can redistribute it and/or modify it
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
27
+ * under the terms of the GNU General Public License as published by the
32
+minimum base line of hardware support and importantly how the firmware
28
+ * Free Software Foundation; either version 2 of the License, or
33
+reports that to any operating system. It is a static system that
29
+ * (at your option) any later version.
34
+reports a very minimal DT to the firmware for non-discoverable
30
+ *
35
+information about components affected by the qemu command line (i.e.
31
+ * This program is distributed in the hope that it will be useful, but WITHOUT
36
+cpus and memory). As a result it must have a firmware specifically
32
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
37
+built to expect a certain hardware layout (as you would in a real
33
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
38
+machine).
34
+ * for more details.
39
+
35
+ */
40
+It is intended to be a machine for developing firmware and testing
36
+
41
+standards compliance with operating systems.
37
+#include "qemu/osdep.h"
42
+
38
+#include "hw/sd/npcm7xx_sdhci.h"
43
+Supported devices
39
+
44
+"""""""""""""""""
40
+#include "libqos/libqtest.h"
45
+
41
+#include "libqtest-single.h"
46
+The sbsa-ref board supports:
42
+#include "libqos/sdhci-cmd.h"
47
+
43
+
48
+ - A configurable number of AArch64 CPUs
44
+#define NPCM7XX_REG_SIZE 0x100
49
+ - GIC version 3
45
+#define NPCM7XX_MMC_BA 0xF0842000
50
+ - System bus AHCI controller
46
+#define NPCM7XX_BLK_SIZE 512
51
+ - System bus EHCI controller
47
+#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30)
52
+ - CDROM and hard disc on AHCI bus
48
+
53
+ - E1000E ethernet card on PCIe bus
49
+char *sd_path;
54
+ - VGA display adaptor on PCIe bus
50
+
55
+ - A generic SBSA watchdog device
51
+static QTestState *setup_sd_card(void)
56
+
52
+{
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
53
+ QTestState *qts = qtest_initf(
54
+ "-machine kudo-bmc "
55
+ "-device sd-card,drive=drive0 "
56
+ "-drive id=drive0,if=none,file=%s,format=raw,auto-read-only=off",
57
+ sd_path);
58
+
59
+ qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_SWRST, SDHC_RESET_ALL);
60
+ qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_CLKCON,
61
+ SDHC_CLOCK_SDCLK_EN | SDHC_CLOCK_INT_STABLE |
62
+ SDHC_CLOCK_INT_EN);
63
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD);
64
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8));
65
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID);
66
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_SEND_RELATIVE_ADDR);
67
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x45670000, 0,
68
+ SDHC_SELECT_DESELECT_CARD);
69
+
70
+ return qts;
71
+}
72
+
73
+static void write_sdread(QTestState *qts, const char *msg)
74
+{
75
+ int fd, ret;
76
+ size_t len = strlen(msg);
77
+ char *rmsg = g_malloc(len);
78
+
79
+ /* write message to sd */
80
+ fd = open(sd_path, O_WRONLY);
81
+ g_assert(fd >= 0);
82
+ ret = write(fd, msg, len);
83
+ close(fd);
84
+ g_assert(ret == len);
85
+
86
+ /* read message using sdhci */
87
+ ret = sdhci_read_cmd(qts, NPCM7XX_MMC_BA, rmsg, len);
88
+ g_assert(ret == len);
89
+ g_assert(!memcmp(rmsg, msg, len));
90
+
91
+ g_free(rmsg);
92
+}
93
+
94
+/* Check MMC can read values from sd */
95
+static void test_read_sd(void)
96
+{
97
+ QTestState *qts = setup_sd_card();
98
+
99
+ write_sdread(qts, "hello world");
100
+ write_sdread(qts, "goodbye");
101
+
102
+ qtest_quit(qts);
103
+}
104
+
105
+static void sdwrite_read(QTestState *qts, const char *msg)
106
+{
107
+ int fd, ret;
108
+ size_t len = strlen(msg);
109
+ char *rmsg = g_malloc(len);
110
+
111
+ /* write message using sdhci */
112
+ sdhci_write_cmd(qts, NPCM7XX_MMC_BA, msg, len, NPCM7XX_BLK_SIZE);
113
+
114
+ /* read message from sd */
115
+ fd = open(sd_path, O_RDONLY);
116
+ g_assert(fd >= 0);
117
+ ret = read(fd, rmsg, len);
118
+ close(fd);
119
+ g_assert(ret == len);
120
+
121
+ g_assert(!memcmp(rmsg, msg, len));
122
+
123
+ g_free(rmsg);
124
+}
125
+
126
+/* Check MMC can write values to sd */
127
+static void test_write_sd(void)
128
+{
129
+ QTestState *qts = setup_sd_card();
130
+
131
+ sdwrite_read(qts, "hello world");
132
+ sdwrite_read(qts, "goodbye");
133
+
134
+ qtest_quit(qts);
135
+}
136
+
137
+/* Check SDHCI has correct default values. */
138
+static void test_reset(void)
139
+{
140
+ QTestState *qts = qtest_init("-machine kudo-bmc");
141
+ uint64_t addr = NPCM7XX_MMC_BA;
142
+ uint64_t end_addr = addr + NPCM7XX_REG_SIZE;
143
+ uint16_t prstvals_resets[] = {NPCM7XX_PRSTVALS_0_RESET,
144
+ NPCM7XX_PRSTVALS_1_RESET,
145
+ 0,
146
+ NPCM7XX_PRSTVALS_3_RESET,
147
+ 0,
148
+ 0};
149
+ int i;
150
+ uint32_t mask;
151
+
152
+ while (addr < end_addr) {
153
+ switch (addr - NPCM7XX_MMC_BA) {
154
+ case SDHC_PRNSTS:
155
+ /*
156
+ * ignores bits 20 to 24: they are changed when reading registers
157
+ */
158
+ mask = 0x1f00000;
159
+ g_assert_cmphex(qtest_readl(qts, addr) | mask, ==,
160
+ NPCM7XX_PRSNTS_RESET | mask);
161
+ addr += 4;
162
+ break;
163
+ case SDHC_BLKGAP:
164
+ g_assert_cmphex(qtest_readb(qts, addr), ==, NPCM7XX_BLKGAP_RESET);
165
+ addr += 1;
166
+ break;
167
+ case SDHC_CAPAB:
168
+ g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_CAPAB_RESET);
169
+ addr += 8;
170
+ break;
171
+ case SDHC_MAXCURR:
172
+ g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_MAXCURR_RESET);
173
+ addr += 8;
174
+ break;
175
+ case SDHC_HCVER:
176
+ g_assert_cmphex(qtest_readw(qts, addr), ==, NPCM7XX_HCVER_RESET);
177
+ addr += 2;
178
+ break;
179
+ case NPCM7XX_PRSTVALS:
180
+ for (i = 0; i < NPCM7XX_PRSTVALS_SIZE; ++i) {
181
+ g_assert_cmphex(qtest_readw(qts, addr + 2 * i), ==,
182
+ prstvals_resets[i]);
183
+ }
184
+ addr += NPCM7XX_PRSTVALS_SIZE * 2;
185
+ break;
186
+ default:
187
+ g_assert_cmphex(qtest_readb(qts, addr), ==, 0);
188
+ addr += 1;
189
+ }
190
+ }
191
+
192
+ qtest_quit(qts);
193
+}
194
+
195
+static void drive_destroy(void)
196
+{
197
+ unlink(sd_path);
198
+ g_free(sd_path);
199
+}
200
+
201
+static void drive_create(void)
202
+{
203
+ int fd, ret;
204
+ GError *error = NULL;
205
+
206
+ /* Create a temporary raw image */
207
+ fd = g_file_open_tmp("sdhci_XXXXXX", &sd_path, &error);
208
+ if (fd == -1) {
209
+ fprintf(stderr, "unable to create sdhci file: %s\n", error->message);
210
+ g_error_free(error);
211
+ }
212
+ g_assert(sd_path != NULL);
213
+
214
+ ret = ftruncate(fd, NPCM7XX_TEST_IMAGE_SIZE);
215
+ g_assert_cmpint(ret, ==, 0);
216
+ g_message("%s", sd_path);
217
+ close(fd);
218
+}
219
+
220
+int main(int argc, char **argv)
221
+{
222
+ int ret;
223
+
224
+ drive_create();
225
+
226
+ g_test_init(&argc, &argv, NULL);
227
+
228
+ qtest_add_func("npcm7xx_sdhci/reset", test_reset);
229
+ qtest_add_func("npcm7xx_sdhci/write_sd", test_write_sd);
230
+ qtest_add_func("npcm7xx_sdhci/read_sd", test_read_sd);
231
+
232
+ ret = g_test_run();
233
+ drive_destroy();
234
+ return ret;
235
+}
236
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
58
index XXXXXXX..XXXXXXX 100644
237
index XXXXXXX..XXXXXXX 100644
59
--- a/docs/system/target-arm.rst
238
--- a/tests/qtest/meson.build
60
+++ b/docs/system/target-arm.rst
239
+++ b/tests/qtest/meson.build
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
240
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
62
arm/mps2
241
'npcm7xx_gpio-test',
63
arm/musca
242
'npcm7xx_pwm-test',
64
arm/realview
243
'npcm7xx_rng-test',
65
+ arm/sbsa
244
+ 'npcm7xx_sdhci-test',
66
arm/versatile
245
'npcm7xx_smbus-test',
67
arm/vexpress
246
'npcm7xx_timer-test',
68
arm/aspeed
247
'npcm7xx_watchdog_timer-test'] + \
69
--
248
--
70
2.20.1
249
2.25.1
71
72
diff view generated by jsdifflib
[PULL 13/16] hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
[PULL 08/26] hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We don't need to fill the full pic[] array if we only use
3
Add new macros to manipulate signed fields within the register.
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
5
when necessary.
6
4
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20220301215958.157011-2-richard.henderson@linaro.org
8
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
hw/arm/musicpal.c | 25 +++++++++++++------------
12
include/hw/registerfields.h | 48 ++++++++++++++++++++++++++++++++++++-
13
1 file changed, 13 insertions(+), 12 deletions(-)
13
1 file changed, 47 insertions(+), 1 deletion(-)
14
14
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
15
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/musicpal.c
17
--- a/include/hw/registerfields.h
18
+++ b/hw/arm/musicpal.c
18
+++ b/include/hw/registerfields.h
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
19
@@ -XXX,XX +XXX,XX @@
20
static void musicpal_init(MachineState *machine)
20
extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
21
{
21
R_ ## reg ## _ ## field ## _LENGTH)
22
ARMCPU *cpu;
22
23
- qemu_irq pic[32];
23
+#define FIELD_SEX8(storage, reg, field) \
24
DeviceState *dev;
24
+ sextract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
25
+ DeviceState *pic;
25
+ R_ ## reg ## _ ## field ## _LENGTH)
26
DeviceState *uart_orgate;
26
+#define FIELD_SEX16(storage, reg, field) \
27
DeviceState *i2c_dev;
27
+ sextract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
28
DeviceState *lcd_dev;
28
+ R_ ## reg ## _ ## field ## _LENGTH)
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
29
+#define FIELD_SEX32(storage, reg, field) \
30
&error_fatal);
30
+ sextract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
31
+ R_ ## reg ## _ ## field ## _LENGTH)
32
32
+#define FIELD_SEX64(storage, reg, field) \
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
33
+ sextract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
34
+ R_ ## reg ## _ ## field ## _LENGTH)
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
35
+
36
- for (i = 0; i < 32; i++) {
36
/* Extract a field from an array of registers */
37
- pic[i] = qdev_get_gpio_in(dev, i);
37
#define ARRAY_FIELD_EX32(regs, reg, field) \
38
- }
38
FIELD_EX32((regs)[R_ ## reg], reg, field)
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
39
@@ -XXX,XX +XXX,XX @@
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
40
_d; })
41
- pic[MP_TIMER4_IRQ], NULL);
41
#define FIELD_DP64(storage, reg, field, val) ({ \
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
42
struct { \
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
43
- uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
44
+ uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
45
+ } _v = { .v = val }; \
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
46
+ uint64_t _d; \
47
47
+ _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
48
/* Logically OR both UART IRQs together */
48
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
49
+ _d; })
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
50
+
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
51
+#define FIELD_SDP8(storage, reg, field, val) ({ \
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
52
+ struct { \
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
53
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
54
+ } _v = { .v = val }; \
55
55
+ uint8_t _d; \
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
56
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
57
qdev_get_gpio_in(uart_orgate, 0),
57
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
58
+ _d; })
59
OBJECT(get_system_memory()), &error_fatal);
59
+#define FIELD_SDP16(storage, reg, field, val) ({ \
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
60
+ struct { \
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
61
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
62
+ } _v = { .v = val }; \
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
63
+ uint16_t _d; \
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
64
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
65
65
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
66
+ _d; })
67
67
+#define FIELD_SDP32(storage, reg, field, val) ({ \
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
68
+ struct { \
69
69
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
70
+ } _v = { .v = val }; \
71
- pic[MP_GPIO_IRQ]);
71
+ uint32_t _d; \
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
72
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
73
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
74
+ _d; })
75
75
+#define FIELD_SDP64(storage, reg, field, val) ({ \
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
76
+ struct { \
77
NULL);
77
+ int64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
78
sysbus_realize_and_unref(s, &error_fatal);
78
} _v = { .v = val }; \
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
79
uint64_t _d; \
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
80
_d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
82
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
85
--
81
--
86
2.20.1
82
2.25.1
87
83
88
84
diff view generated by jsdifflib
New patch
[PULL 09/26] target/arm: Set TCR_EL1.TSZ for user-only
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Set this as the kernel would, to 48 bits, to keep the computation
4
of the address space correct for PAuth.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220301215958.157011-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.c | 3 ++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
19
aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
20
}
21
/*
22
+ * Enable 48-bit address space (TODO: take reserved_va into account).
23
* Enable TBI0 but not TBI1.
24
* Note that this must match useronly_clean_ptr.
25
*/
26
- env->cp15.tcr_el[1].raw_tcr = (1ULL << 37);
27
+ env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37);
28
29
/* Enable MTE */
30
if (cpu_isar_feature(aa64_mte, cpu)) {
31
--
32
2.25.1
diff view generated by jsdifflib
New patch
[PULL 10/26] target/arm: Fault on invalid TCR_ELx.TxSZ
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Without FEAT_LVA, the behaviour of programming an invalid value
4
is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid
5
minimum value requires a Translation fault.
6
7
It is most self-consistent to choose to generate the fault always.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220301215958.157011-4-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/internals.h | 1 +
15
target/arm/helper.c | 32 ++++++++++++++++++++++++++++----
16
2 files changed, 29 insertions(+), 4 deletions(-)
17
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
21
+++ b/target/arm/internals.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
23
bool hpd : 1;
24
bool using16k : 1;
25
bool using64k : 1;
26
+ bool tsz_oob : 1; /* tsz has been clamped to legal range */
27
} ARMVAParameters;
28
29
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
35
ARMMMUIdx mmu_idx, bool data)
36
{
37
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
38
- bool epd, hpd, using16k, using64k;
39
- int select, tsz, tbi, max_tsz;
40
+ bool epd, hpd, using16k, using64k, tsz_oob;
41
+ int select, tsz, tbi, max_tsz, min_tsz;
42
43
if (!regime_has_2_ranges(mmu_idx)) {
44
select = 0;
45
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
46
} else {
47
max_tsz = 39;
48
}
49
+ min_tsz = 16; /* TODO: ARMv8.2-LVA */
50
51
- tsz = MIN(tsz, max_tsz);
52
- tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
53
+ if (tsz > max_tsz) {
54
+ tsz = max_tsz;
55
+ tsz_oob = true;
56
+ } else if (tsz < min_tsz) {
57
+ tsz = min_tsz;
58
+ tsz_oob = true;
59
+ } else {
60
+ tsz_oob = false;
61
+ }
62
63
/* Present TBI as a composite with TBID. */
64
tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
65
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
66
.hpd = hpd,
67
.using16k = using16k,
68
.using64k = using64k,
69
+ .tsz_oob = tsz_oob,
70
};
71
}
72
73
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
74
param = aa64_va_parameters(env, address, mmu_idx,
75
access_type != MMU_INST_FETCH);
76
level = 0;
77
+
78
+ /*
79
+ * If TxSZ is programmed to a value larger than the maximum,
80
+ * or smaller than the effective minimum, it is IMPLEMENTATION
81
+ * DEFINED whether we behave as if the field were programmed
82
+ * within bounds, or if a level 0 Translation fault is generated.
83
+ *
84
+ * With FEAT_LVA, fault on less than minimum becomes required,
85
+ * so our choice is to always raise the fault.
86
+ */
87
+ if (param.tsz_oob) {
88
+ fault_type = ARMFault_Translation;
89
+ goto do_fault;
90
+ }
91
+
92
addrsize = 64 - 8 * param.tbi;
93
inputsize = 64 - param.tsz;
94
} else {
95
--
96
2.25.1
diff view generated by jsdifflib
[PULL 12/16] hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
[PULL 11/26] target/arm: Move arm_pamax out of line
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The MusicPal board code connects both of the IRQ outputs of the UART
3
We will shortly share parts of this function with other portions
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
4
of address translation.
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
9
5
10
This kind of wiring needs an explicitly created OR gate; add one.
11
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220301215958.157011-5-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
12
---
18
hw/arm/musicpal.c | 17 +++++++++++++----
13
target/arm/internals.h | 19 +------------------
19
hw/arm/Kconfig | 1 +
14
target/arm/helper.c | 22 ++++++++++++++++++++++
20
2 files changed, 14 insertions(+), 4 deletions(-)
15
2 files changed, 23 insertions(+), 18 deletions(-)
21
16
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
23
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/musicpal.c
19
--- a/target/arm/internals.h
25
+++ b/hw/arm/musicpal.c
20
+++ b/target/arm/internals.h
26
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static inline void update_spsel(CPUARMState *env, uint32_t imm)
27
#include "ui/console.h"
22
* Returns the implementation defined bit-width of physical addresses.
28
#include "hw/i2c/i2c.h"
23
* The ARMv8 reference manuals refer to this as PAMax().
29
#include "hw/irq.h"
24
*/
30
+#include "hw/or-irq.h"
25
-static inline unsigned int arm_pamax(ARMCPU *cpu)
31
#include "hw/audio/wm8750.h"
26
-{
32
#include "sysemu/block-backend.h"
27
- static const unsigned int pamax_map[] = {
33
#include "sysemu/runstate.h"
28
- [0] = 32,
34
@@ -XXX,XX +XXX,XX @@
29
- [1] = 36,
35
#define MP_TIMER4_IRQ 7
30
- [2] = 40,
36
#define MP_EHCI_IRQ 8
31
- [3] = 42,
37
#define MP_ETH_IRQ 9
32
- [4] = 44,
38
-#define MP_UART1_IRQ 11
33
- [5] = 48,
39
-#define MP_UART2_IRQ 11
34
- };
40
+#define MP_UART_SHARED_IRQ 11
35
- unsigned int parange =
41
#define MP_GPIO_IRQ 12
36
- FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
42
#define MP_RTC_IRQ 28
37
-
43
#define MP_AUDIO_IRQ 30
38
- /* id_aa64mmfr0 is a read-only register so values outside of the
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
39
- * supported mappings can be considered an implementation error. */
45
ARMCPU *cpu;
40
- assert(parange < ARRAY_SIZE(pamax_map));
46
qemu_irq pic[32];
41
- return pamax_map[parange];
47
DeviceState *dev;
42
-}
48
+ DeviceState *uart_orgate;
43
+unsigned int arm_pamax(ARMCPU *cpu);
49
DeviceState *i2c_dev;
44
50
DeviceState *lcd_dev;
45
/* Return true if extended addresses are enabled.
51
DeviceState *key_dev;
46
* This is always the case if our translation regime is 64 bit,
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
48
index XXXXXXX..XXXXXXX 100644
54
pic[MP_TIMER4_IRQ], NULL);
49
--- a/target/arm/helper.c
55
50
+++ b/target/arm/helper.c
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
51
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
57
+ /* Logically OR both UART IRQs together */
52
}
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
53
#endif /* !CONFIG_USER_ONLY */
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
54
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
55
+/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
56
+unsigned int arm_pamax(ARMCPU *cpu)
57
+{
58
+ static const unsigned int pamax_map[] = {
59
+ [0] = 32,
60
+ [1] = 36,
61
+ [2] = 40,
62
+ [3] = 42,
63
+ [4] = 44,
64
+ [5] = 48,
65
+ };
66
+ unsigned int parange =
67
+ FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
62
+
68
+
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
69
+ /*
64
+ qdev_get_gpio_in(uart_orgate, 0),
70
+ * id_aa64mmfr0 is a read-only register so values outside of the
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
71
+ * supported mappings can be considered an implementation error.
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
72
+ */
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
73
+ assert(parange < ARRAY_SIZE(pamax_map));
68
+ qdev_get_gpio_in(uart_orgate, 1),
74
+ return pamax_map[parange];
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
75
+}
70
76
+
71
/* Register flash */
77
static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
78
{
73
index XXXXXXX..XXXXXXX 100644
79
if (regime_has_2_ranges(mmu_idx)) {
74
--- a/hw/arm/Kconfig
75
+++ b/hw/arm/Kconfig
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
77
78
config MUSICPAL
79
bool
80
+ select OR_IRQ
81
select BITBANG_I2C
82
select MARVELL_88W8618
83
select PTIMER
84
--
80
--
85
2.20.1
81
2.25.1
86
82
87
83
diff view generated by jsdifflib
[PULL 09/16] hw/arm/armsse: Correct expansion MPC interrupt lines
[PULL 12/26] target/arm: Pass outputsize down to check_s2_mmu_setup
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We can use one MPC per SRAM bank, but we currently only wire the
3
Pass down the width of the output address from translation.
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
4
For now this is still just PAMax, but a subsequent patch will
5
compute the correct value from TCR_ELx.{I}PS.
5
6
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220301215958.157011-6-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
hw/arm/armsse.c | 3 ++-
12
target/arm/helper.c | 21 ++++++++++-----------
13
1 file changed, 2 insertions(+), 1 deletion(-)
13
1 file changed, 10 insertions(+), 11 deletions(-)
14
14
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/armsse.c
17
--- a/target/arm/helper.c
18
+++ b/hw/arm/armsse.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
19
@@ -XXX,XX +XXX,XX @@ do_fault:
20
qdev_get_gpio_in(dev_splitter, 0));
20
* false otherwise.
21
qdev_connect_gpio_out(dev_splitter, 0,
21
*/
22
qdev_get_gpio_in_named(dev_secctl,
22
static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
23
- "mpc_status", 0));
23
- int inputsize, int stride)
24
+ "mpc_status",
24
+ int inputsize, int stride, int outputsize)
25
+ i - IOTS_NUM_EXP_MPC));
25
{
26
const int grainsize = stride + 3;
27
int startsizecheck;
28
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
29
}
30
31
if (is_aa64) {
32
- CPUARMState *env = &cpu->env;
33
- unsigned int pamax = arm_pamax(cpu);
34
-
35
switch (stride) {
36
case 13: /* 64KB Pages. */
37
- if (level == 0 || (level == 1 && pamax <= 42)) {
38
+ if (level == 0 || (level == 1 && outputsize <= 42)) {
39
return false;
40
}
41
break;
42
case 11: /* 16KB Pages. */
43
- if (level == 0 || (level == 1 && pamax <= 40)) {
44
+ if (level == 0 || (level == 1 && outputsize <= 40)) {
45
return false;
46
}
47
break;
48
case 9: /* 4KB Pages. */
49
- if (level == 0 && pamax <= 42) {
50
+ if (level == 0 && outputsize <= 42) {
51
return false;
52
}
53
break;
54
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
26
}
55
}
27
56
28
qdev_connect_gpio_out(dev_splitter, 1,
57
/* Inputsize checks. */
58
- if (inputsize > pamax &&
59
- (arm_el_is_aa64(env, 1) || inputsize > 40)) {
60
+ if (inputsize > outputsize &&
61
+ (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
62
/* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
63
return false;
64
}
65
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
66
target_ulong page_size;
67
uint32_t attrs;
68
int32_t stride;
69
- int addrsize, inputsize;
70
+ int addrsize, inputsize, outputsize;
71
TCR *tcr = regime_tcr(env, mmu_idx);
72
int ap, ns, xn, pxn;
73
uint32_t el = regime_el(env, mmu_idx);
74
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
75
76
addrsize = 64 - 8 * param.tbi;
77
inputsize = 64 - param.tsz;
78
+ outputsize = arm_pamax(cpu);
79
} else {
80
param = aa32_va_parameters(env, address, mmu_idx);
81
level = 1;
82
addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
83
inputsize = addrsize - param.tsz;
84
+ outputsize = 40;
85
}
86
87
/*
88
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
89
90
/* Check that the starting level is valid. */
91
ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
92
- inputsize, stride);
93
+ inputsize, stride, outputsize);
94
if (!ok) {
95
fault_type = ARMFault_Translation;
96
goto do_fault;
29
--
97
--
30
2.20.1
98
2.25.1
31
32
diff view generated by jsdifflib
[PULL 07/16] hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
[PULL 13/26] target/arm: Use MAKE_64BIT_MASK to compute indexmask
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When using a Cortex-A15, the Virt machine does not use any
3
The macro is a bit more readable than the inlined computation.
4
MPCore peripherals. Remove the dependency.
5
4
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20220301215958.157011-7-richard.henderson@linaro.org
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
hw/arm/Kconfig | 1 -
10
target/arm/helper.c | 4 ++--
14
1 file changed, 1 deletion(-)
11
1 file changed, 2 insertions(+), 2 deletions(-)
15
12
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Kconfig
15
--- a/target/arm/helper.c
19
+++ b/hw/arm/Kconfig
16
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
17
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
21
imply VFIO_PLATFORM
18
level = startlevel;
22
imply VFIO_XGMAC
19
}
23
imply TPM_TIS_SYSBUS
20
24
- select A15MPCORE
21
- indexmask_grainsize = (1ULL << (stride + 3)) - 1;
25
select ACPI
22
- indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
26
select ARM_SMMUV3
23
+ indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3);
27
select GPIO_KEY
24
+ indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level)));
25
26
/* Now we can extract the actual base address from the TTBR */
27
descaddr = extract64(ttbr, 0, 48);
28
--
28
--
29
2.20.1
29
2.25.1
30
30
31
31
diff view generated by jsdifflib
[PULL 01/16] hw/arm/Kconfig: ARM_V7M depends on PTIMER
[PULL 14/26] target/arm: Honor TCR_ELx.{I}PS
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
3
This field controls the output (intermediate) physical address size
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
4
of the translation process. V8 requires to raise an AddressSize
5
in the build when building armv7m_systick.
5
fault if the page tables are programmed incorrectly, such that any
6
intermediate descriptor address, or the final translated address,
7
is out of range.
6
8
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Add a PS field to ARMVAParameters, and properly compute outputsize
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
in get_phys_addr_lpae. Test the descaddr as extracted from TTBR
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
11
and from page table entries.
12
13
Restrict descaddrmask so that we won't raise the fault for v7.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20220301215958.157011-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
20
---
12
hw/arm/Kconfig | 1 +
21
target/arm/internals.h | 1 +
13
1 file changed, 1 insertion(+)
22
target/arm/helper.c | 72 ++++++++++++++++++++++++++++++++----------
23
2 files changed, 57 insertions(+), 16 deletions(-)
14
24
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
25
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/Kconfig
27
--- a/target/arm/internals.h
18
+++ b/hw/arm/Kconfig
28
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
29
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
20
30
*/
21
config ARM_V7M
31
typedef struct ARMVAParameters {
22
bool
32
unsigned tsz : 8;
23
+ select PTIMER
33
+ unsigned ps : 3;
24
34
unsigned select : 1;
25
config ALLWINNER_A10
35
bool tbi : 1;
26
bool
36
bool epd : 1;
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/helper.c
40
+++ b/target/arm/helper.c
41
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
42
}
43
#endif /* !CONFIG_USER_ONLY */
44
45
+/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
46
+static const uint8_t pamax_map[] = {
47
+ [0] = 32,
48
+ [1] = 36,
49
+ [2] = 40,
50
+ [3] = 42,
51
+ [4] = 44,
52
+ [5] = 48,
53
+};
54
+
55
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
56
unsigned int arm_pamax(ARMCPU *cpu)
57
{
58
- static const unsigned int pamax_map[] = {
59
- [0] = 32,
60
- [1] = 36,
61
- [2] = 40,
62
- [3] = 42,
63
- [4] = 44,
64
- [5] = 48,
65
- };
66
unsigned int parange =
67
FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
68
69
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
70
{
71
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
72
bool epd, hpd, using16k, using64k, tsz_oob;
73
- int select, tsz, tbi, max_tsz, min_tsz;
74
+ int select, tsz, tbi, max_tsz, min_tsz, ps;
75
76
if (!regime_has_2_ranges(mmu_idx)) {
77
select = 0;
78
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
79
hpd = extract32(tcr, 24, 1);
80
}
81
epd = false;
82
+ ps = extract32(tcr, 16, 3);
83
} else {
84
/*
85
* Bit 55 is always between the two regions, and is canonical for
86
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
87
epd = extract32(tcr, 23, 1);
88
hpd = extract64(tcr, 42, 1);
89
}
90
+ ps = extract64(tcr, 32, 3);
91
}
92
93
if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
94
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
95
96
return (ARMVAParameters) {
97
.tsz = tsz,
98
+ .ps = ps,
99
.select = select,
100
.tbi = tbi,
101
.epd = epd,
102
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
103
104
/* TODO: This code does not support shareability levels. */
105
if (aarch64) {
106
+ int ps;
107
+
108
param = aa64_va_parameters(env, address, mmu_idx,
109
access_type != MMU_INST_FETCH);
110
level = 0;
111
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
112
113
addrsize = 64 - 8 * param.tbi;
114
inputsize = 64 - param.tsz;
115
- outputsize = arm_pamax(cpu);
116
+
117
+ /*
118
+ * Bound PS by PARANGE to find the effective output address size.
119
+ * ID_AA64MMFR0 is a read-only register so values outside of the
120
+ * supported mappings can be considered an implementation error.
121
+ */
122
+ ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
123
+ ps = MIN(ps, param.ps);
124
+ assert(ps < ARRAY_SIZE(pamax_map));
125
+ outputsize = pamax_map[ps];
126
} else {
127
param = aa32_va_parameters(env, address, mmu_idx);
128
level = 1;
129
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
130
131
/* Now we can extract the actual base address from the TTBR */
132
descaddr = extract64(ttbr, 0, 48);
133
+
134
+ /*
135
+ * If the base address is out of range, raise AddressSizeFault.
136
+ * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
137
+ * but we've just cleared the bits above 47, so simplify the test.
138
+ */
139
+ if (descaddr >> outputsize) {
140
+ level = 0;
141
+ fault_type = ARMFault_AddressSize;
142
+ goto do_fault;
143
+ }
144
+
145
/*
146
* We rely on this masking to clear the RES0 bits at the bottom of the TTBR
147
* and also to mask out CnP (bit 0) which could validly be non-zero.
148
*/
149
descaddr &= ~indexmask;
150
151
- /* The address field in the descriptor goes up to bit 39 for ARMv7
152
- * but up to bit 47 for ARMv8, but we use the descaddrmask
153
- * up to bit 39 for AArch32, because we don't need other bits in that case
154
- * to construct next descriptor address (anyway they should be all zeroes).
155
+ /*
156
+ * For AArch32, the address field in the descriptor goes up to bit 39
157
+ * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
158
+ * or an AddressSize fault is raised. So for v8 we extract those SBZ
159
+ * bits as part of the address, which will be checked via outputsize.
160
+ * For AArch64, the address field always goes up to bit 47 (with extra
161
+ * bits for FEAT_LPA placed elsewhere). AArch64 implies v8.
162
*/
163
- descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
164
- ~indexmask_grainsize;
165
+ if (arm_feature(env, ARM_FEATURE_V8)) {
166
+ descaddrmask = MAKE_64BIT_MASK(0, 48);
167
+ } else {
168
+ descaddrmask = MAKE_64BIT_MASK(0, 40);
169
+ }
170
+ descaddrmask &= ~indexmask_grainsize;
171
172
/* Secure accesses start with the page table in secure memory and
173
* can be downgraded to non-secure at any step. Non-secure accesses
174
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
175
/* Invalid, or the Reserved level 3 encoding */
176
goto do_fault;
177
}
178
+
179
descaddr = descriptor & descaddrmask;
180
+ if (descaddr >> outputsize) {
181
+ fault_type = ARMFault_AddressSize;
182
+ goto do_fault;
183
+ }
184
185
if ((descriptor & 2) && (level < 3)) {
186
/* Table entry. The top five bits are attributes which may
27
--
187
--
28
2.20.1
188
2.25.1
29
189
30
190
diff view generated by jsdifflib
New patch
[PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The original A.a revision of the AArch64 ARM required that we
4
force-extend the addresses in these registers from 49 bits.
5
This language has been loosened via a combination of IMPLEMENTATION
6
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
7
the entire aligned address.
8
9
This means that we do not have to consider whether or not FEAT_LVA
10
is enabled, and decide from which bit an address might need to be
11
extended.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.c | 32 ++++++++++++++++++++++++--------
19
1 file changed, 24 insertions(+), 8 deletions(-)
20
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
24
+++ b/target/arm/helper.c
25
@@ -XXX,XX +XXX,XX @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
26
ARMCPU *cpu = env_archcpu(env);
27
int i = ri->crm;
28
29
- /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
30
- * register reads and behaves as if values written are sign extended.
31
+ /*
32
* Bits [1:0] are RES0.
33
+ *
34
+ * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
35
+ * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
36
+ * they contain the value written. It is CONSTRAINED UNPREDICTABLE
37
+ * whether the RESS bits are ignored when comparing an address.
38
+ *
39
+ * Therefore we are allowed to compare the entire register, which lets
40
+ * us avoid considering whether or not FEAT_LVA is actually enabled.
41
*/
42
- value = sextract64(value, 0, 49) & ~3ULL;
43
+ value &= ~3ULL;
44
45
raw_write(env, ri, value);
46
hw_watchpoint_update(cpu, i);
47
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
48
case 0: /* unlinked address match */
49
case 1: /* linked address match */
50
{
51
- /* Bits [63:49] are hardwired to the value of bit [48]; that is,
52
- * we behave as if the register was sign extended. Bits [1:0] are
53
- * RES0. The BAS field is used to allow setting breakpoints on 16
54
- * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
55
+ /*
56
+ * Bits [1:0] are RES0.
57
+ *
58
+ * It is IMPLEMENTATION DEFINED whether bits [63:49]
59
+ * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
60
+ * of the VA field ([48] or [52] for FEAT_LVA), or whether the
61
+ * value is read as written. It is CONSTRAINED UNPREDICTABLE
62
+ * whether the RESS bits are ignored when comparing an address.
63
+ * Therefore we are allowed to compare the entire register, which
64
+ * lets us avoid considering whether FEAT_LVA is actually enabled.
65
+ *
66
+ * The BAS field is used to allow setting breakpoints on 16-bit
67
+ * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
68
* a bp will fire if the addresses covered by the bp and the addresses
69
* covered by the insn overlap but the insn doesn't start at the
70
* start of the bp address range. We choose to require the insn and
71
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
72
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
73
*/
74
int bas = extract64(bcr, 5, 4);
75
- addr = sextract64(bvr, 0, 49) & ~3ULL;
76
+ addr = bvr & ~3ULL;
77
if (bas == 0) {
78
return;
79
}
80
--
81
2.25.1
diff view generated by jsdifflib
New patch
[PULL 16/26] target/arm: Implement FEAT_LVA
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This feature is relatively small, as it applies only to
4
64k pages and thus requires no additional changes to the
5
table descriptor walking algorithm, only a change to the
6
minimum TSZ (which is the inverse of the maximum virtual
7
address space size).
8
9
Note that this feature widens VBAR_ELx, but we already
10
treat the register as being 64 bits wide.
11
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220301215958.157011-10-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
docs/system/arm/emulation.rst | 1 +
18
target/arm/cpu-param.h | 2 +-
19
target/arm/cpu.h | 5 +++++
20
target/arm/cpu64.c | 1 +
21
target/arm/helper.c | 9 ++++++++-
22
5 files changed, 16 insertions(+), 2 deletions(-)
23
24
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
25
index XXXXXXX..XXXXXXX 100644
26
--- a/docs/system/arm/emulation.rst
27
+++ b/docs/system/arm/emulation.rst
28
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
29
- FEAT_LRCPC (Load-acquire RCpc instructions)
30
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
31
- FEAT_LSE (Large System Extensions)
32
+- FEAT_LVA (Large Virtual Address space)
33
- FEAT_MTE (Memory Tagging Extension)
34
- FEAT_MTE2 (Memory Tagging Extension)
35
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
36
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/cpu-param.h
39
+++ b/target/arm/cpu-param.h
40
@@ -XXX,XX +XXX,XX @@
41
#ifdef TARGET_AARCH64
42
# define TARGET_LONG_BITS 64
43
# define TARGET_PHYS_ADDR_SPACE_BITS 48
44
-# define TARGET_VIRT_ADDR_SPACE_BITS 48
45
+# define TARGET_VIRT_ADDR_SPACE_BITS 52
46
#else
47
# define TARGET_LONG_BITS 32
48
# define TARGET_PHYS_ADDR_SPACE_BITS 40
49
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/cpu.h
52
+++ b/target/arm/cpu.h
53
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
54
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
55
}
56
57
+static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
58
+{
59
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
60
+}
61
+
62
static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
63
{
64
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
65
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/target/arm/cpu64.c
68
+++ b/target/arm/cpu64.c
69
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
70
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
71
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
72
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
73
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
74
cpu->isar.id_aa64mmfr2 = t;
75
76
t = cpu->isar.id_aa64zfr0;
77
diff --git a/target/arm/helper.c b/target/arm/helper.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/helper.c
80
+++ b/target/arm/helper.c
81
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
82
} else {
83
max_tsz = 39;
84
}
85
- min_tsz = 16; /* TODO: ARMv8.2-LVA */
86
+
87
+ min_tsz = 16;
88
+ if (using64k) {
89
+ if (cpu_isar_feature(aa64_lva, env_archcpu(env))) {
90
+ min_tsz = 12;
91
+ }
92
+ }
93
+ /* TODO: FEAT_LPA2 */
94
95
if (tsz > max_tsz) {
96
tsz = max_tsz;
97
--
98
2.25.1
diff view generated by jsdifflib
[PULL 10/16] hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
[PULL 17/26] target/arm: Implement FEAT_LPA
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The system configuration controller (SYSCFG) doesn't have
3
This feature widens physical addresses (and intermediate physical
4
any output IRQ (and the INTC input #71 belongs to the UART6).
4
addresses for 2-stage translation) from 48 to 52 bits, when using
5
Remove the invalid code.
5
64k pages. The only thing left at this point is to handle the
6
extra bits in the TTBR and in the table descriptors.
6
7
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
8
Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
mask out the high bits when writing to those registers, so no changes
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
10
are required there.
11
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220301215958.157011-11-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
16
---
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
17
docs/system/arm/emulation.rst | 1 +
14
hw/arm/stm32f205_soc.c | 1 -
18
target/arm/cpu-param.h | 2 +-
15
hw/misc/stm32f2xx_syscfg.c | 2 --
19
target/arm/cpu64.c | 2 +-
16
3 files changed, 5 deletions(-)
20
target/arm/helper.c | 19 ++++++++++++++++---
21
4 files changed, 19 insertions(+), 5 deletions(-)
17
22
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
23
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
19
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
25
--- a/docs/system/arm/emulation.rst
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
26
+++ b/docs/system/arm/emulation.rst
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
27
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
23
uint32_t syscfg_exticr3;
28
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
24
uint32_t syscfg_exticr4;
29
- FEAT_JSCVT (JavaScript conversion instructions)
25
uint32_t syscfg_cmpcr;
30
- FEAT_LOR (Limited ordering regions)
26
-
31
+- FEAT_LPA (Large Physical Address space)
27
- qemu_irq irq;
32
- FEAT_LRCPC (Load-acquire RCpc instructions)
33
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
34
- FEAT_LSE (Large System Extensions)
35
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu-param.h
38
+++ b/target/arm/cpu-param.h
39
@@ -XXX,XX +XXX,XX @@
40
41
#ifdef TARGET_AARCH64
42
# define TARGET_LONG_BITS 64
43
-# define TARGET_PHYS_ADDR_SPACE_BITS 48
44
+# define TARGET_PHYS_ADDR_SPACE_BITS 52
45
# define TARGET_VIRT_ADDR_SPACE_BITS 52
46
#else
47
# define TARGET_LONG_BITS 32
48
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/cpu64.c
51
+++ b/target/arm/cpu64.c
52
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
53
cpu->isar.id_aa64pfr1 = t;
54
55
t = cpu->isar.id_aa64mmfr0;
56
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
57
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
58
cpu->isar.id_aa64mmfr0 = t;
59
60
t = cpu->isar.id_aa64mmfr1;
61
diff --git a/target/arm/helper.c b/target/arm/helper.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/helper.c
64
+++ b/target/arm/helper.c
65
@@ -XXX,XX +XXX,XX @@ static const uint8_t pamax_map[] = {
66
[3] = 42,
67
[4] = 44,
68
[5] = 48,
69
+ [6] = 52,
28
};
70
};
29
71
30
#endif /* HW_STM32F2XX_SYSCFG_H */
72
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
73
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
32
index XXXXXXX..XXXXXXX 100644
74
descaddr = extract64(ttbr, 0, 48);
33
--- a/hw/arm/stm32f205_soc.c
75
34
+++ b/hw/arm/stm32f205_soc.c
76
/*
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
77
- * If the base address is out of range, raise AddressSizeFault.
36
}
78
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
37
busdev = SYS_BUS_DEVICE(dev);
79
+ *
38
sysbus_mmio_map(busdev, 0, 0x40013800);
80
+ * Otherwise, if the base address is out of range, raise AddressSizeFault.
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
81
* In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
40
82
* but we've just cleared the bits above 47, so simplify the test.
41
/* Attach UART (uses USART registers) and USART controllers */
83
*/
42
for (i = 0; i < STM_NUM_USARTS; i++) {
84
- if (descaddr >> outputsize) {
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
85
+ if (outputsize > 48) {
44
index XXXXXXX..XXXXXXX 100644
86
+ descaddr |= extract64(ttbr, 2, 4) << 48;
45
--- a/hw/misc/stm32f2xx_syscfg.c
87
+ } else if (descaddr >> outputsize) {
46
+++ b/hw/misc/stm32f2xx_syscfg.c
88
level = 0;
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
89
fault_type = ARMFault_AddressSize;
48
{
90
goto do_fault;
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
91
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
50
92
}
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
93
52
-
94
descaddr = descriptor & descaddrmask;
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
95
- if (descaddr >> outputsize) {
54
TYPE_STM32F2XX_SYSCFG, 0x400);
96
+
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
97
+ /*
98
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
99
+ * of descriptor. Otherwise, if descaddr is out of range, raise
100
+ * AddressSizeFault.
101
+ */
102
+ if (outputsize > 48) {
103
+ descaddr |= extract64(descriptor, 12, 4) << 48;
104
+ } else if (descaddr >> outputsize) {
105
fault_type = ARMFault_AddressSize;
106
goto do_fault;
107
}
56
--
108
--
57
2.20.1
109
2.25.1
58
59
diff view generated by jsdifflib
New patch
[PULL 18/26] target/arm: Extend arm_fi_to_lfsc to level -1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
With FEAT_LPA2, rather than introducing translation level 4,
4
we introduce level -1, below the current level 0. Extend
5
arm_fi_to_lfsc to handle these faults.
6
7
Assert that this new translation level does not leak into
8
fault types for which it is not defined, which allows some
9
masking of fi->level to be removed.
10
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220301215958.157011-12-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/internals.h | 35 +++++++++++++++++++++++++++++------
17
1 file changed, 29 insertions(+), 6 deletions(-)
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
24
case ARMFault_None:
25
return 0;
26
case ARMFault_AddressSize:
27
- fsc = fi->level & 3;
28
+ assert(fi->level >= -1 && fi->level <= 3);
29
+ if (fi->level < 0) {
30
+ fsc = 0b101001;
31
+ } else {
32
+ fsc = fi->level;
33
+ }
34
break;
35
case ARMFault_AccessFlag:
36
- fsc = (fi->level & 3) | (0x2 << 2);
37
+ assert(fi->level >= 0 && fi->level <= 3);
38
+ fsc = 0b001000 | fi->level;
39
break;
40
case ARMFault_Permission:
41
- fsc = (fi->level & 3) | (0x3 << 2);
42
+ assert(fi->level >= 0 && fi->level <= 3);
43
+ fsc = 0b001100 | fi->level;
44
break;
45
case ARMFault_Translation:
46
- fsc = (fi->level & 3) | (0x1 << 2);
47
+ assert(fi->level >= -1 && fi->level <= 3);
48
+ if (fi->level < 0) {
49
+ fsc = 0b101011;
50
+ } else {
51
+ fsc = 0b000100 | fi->level;
52
+ }
53
break;
54
case ARMFault_SyncExternal:
55
fsc = 0x10 | (fi->ea << 12);
56
break;
57
case ARMFault_SyncExternalOnWalk:
58
- fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12);
59
+ assert(fi->level >= -1 && fi->level <= 3);
60
+ if (fi->level < 0) {
61
+ fsc = 0b010011;
62
+ } else {
63
+ fsc = 0b010100 | fi->level;
64
+ }
65
+ fsc |= fi->ea << 12;
66
break;
67
case ARMFault_SyncParity:
68
fsc = 0x18;
69
break;
70
case ARMFault_SyncParityOnWalk:
71
- fsc = (fi->level & 3) | (0x7 << 2);
72
+ assert(fi->level >= -1 && fi->level <= 3);
73
+ if (fi->level < 0) {
74
+ fsc = 0b011011;
75
+ } else {
76
+ fsc = 0b011100 | fi->level;
77
+ }
78
break;
79
case ARMFault_AsyncParity:
80
fsc = 0x19;
81
--
82
2.25.1
diff view generated by jsdifflib
[PULL 08/16] target/arm: Fix neon VTBL/VTBX for len > 1
[PULL 19/26] target/arm: Introduce tlbi_aa64_get_range
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The helper function did not get updated when we reorganized
3
Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base,
4
the vector register file for SVE. Since then, the neon dregs
4
returning a structure containing both results. Pass in the
5
are non-sequential and cannot be simply indexed.
5
ARMMMUIdx, rather than the digested two_ranges boolean.
6
6
7
At the same time, make the helper function operate on 64-bit
7
This is in preparation for FEAT_LPA2, where the interpretation
8
quantities so that we do not have to call it twice.
8
of 'value' depends on the effective value of DS for the regime.
9
9
10
Fixes: c39c2b9043e
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
12
Message-id: 20220301215958.157011-13-richard.henderson@linaro.org
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
14
---
18
target/arm/helper.h | 2 +-
15
target/arm/helper.c | 58 +++++++++++++++++++--------------------------
19
target/arm/op_helper.c | 23 +++++++++--------
16
1 file changed, 24 insertions(+), 34 deletions(-)
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
21
3 files changed, 29 insertions(+), 40 deletions(-)
22
17
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
24
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper.h
20
--- a/target/arm/helper.c
26
+++ b/target/arm/helper.h
21
+++ b/target/arm/helper.c
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
22
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
33
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
41
cpu_loop_exit_restore(cs, ra);
42
}
23
}
43
24
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
25
#ifdef TARGET_AARCH64
45
- uint32_t maxindex)
26
-static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
27
- uint64_t value)
47
+ uint64_t ireg, uint64_t def)
28
-{
29
- unsigned int page_shift;
30
- unsigned int page_size_granule;
31
- uint64_t num;
32
- uint64_t scale;
33
- uint64_t exponent;
34
+typedef struct {
35
+ uint64_t base;
36
uint64_t length;
37
+} TLBIRange;
38
+
39
+static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
40
+ uint64_t value)
41
+{
42
+ unsigned int page_size_granule, page_shift, num, scale, exponent;
43
+ TLBIRange ret = { };
44
45
- num = extract64(value, 39, 5);
46
- scale = extract64(value, 44, 2);
47
page_size_granule = extract64(value, 46, 2);
48
49
if (page_size_granule == 0) {
50
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
51
page_size_granule);
52
- return 0;
53
+ return ret;
54
}
55
56
page_shift = (page_size_granule - 1) * 2 + 12;
57
-
58
+ num = extract64(value, 39, 5);
59
+ scale = extract64(value, 44, 2);
60
exponent = (5 * scale) + 1;
61
- length = (num + 1) << (exponent + page_shift);
62
63
- return length;
64
-}
65
+ ret.length = (num + 1) << (exponent + page_shift);
66
67
-static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value,
68
- bool two_ranges)
69
-{
70
- /* TODO: ARMv8.7 FEAT_LPA2 */
71
- uint64_t pageaddr;
72
-
73
- if (two_ranges) {
74
- pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
75
+ if (regime_has_2_ranges(mmuidx)) {
76
+ ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
77
} else {
78
- pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS;
79
+ ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS;
80
}
81
82
- return pageaddr;
83
+ return ret;
84
}
85
86
static void do_rvae_write(CPUARMState *env, uint64_t value,
87
int idxmap, bool synced)
48
{
88
{
49
- uint32_t val, shift;
89
ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap);
50
- uint64_t *table = vn;
90
- bool two_ranges = regime_has_2_ranges(one_idx);
51
+ uint64_t tmp, val = 0;
91
- uint64_t baseaddr, length;
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
92
+ TLBIRange range;
53
+ uint32_t base_reg = desc >> 2;
93
int bits;
54
+ uint32_t shift, index, reg;
94
55
95
- baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges);
56
- val = 0;
96
- length = tlbi_aa64_range_get_length(env, value);
57
- for (shift = 0; shift < 32; shift += 8) {
97
- bits = tlbbits_for_regime(env, one_idx, baseaddr);
58
- uint32_t index = (ireg >> shift) & 0xff;
98
+ range = tlbi_aa64_get_range(env, one_idx, value);
59
+ for (shift = 0; shift < 64; shift += 8) {
99
+ bits = tlbbits_for_regime(env, one_idx, range.base);
60
+ index = (ireg >> shift) & 0xff;
100
61
if (index < maxindex) {
101
if (synced) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
102
tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
63
- val |= tmp << shift;
103
- baseaddr,
64
+ reg = base_reg + (index >> 3);
104
- length,
65
+ tmp = *aa32_vfp_dreg(env, reg);
105
+ range.base,
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
106
+ range.length,
67
} else {
107
idxmap,
68
- val |= def & (0xff << shift);
108
bits);
69
+ tmp = def & (0xffull << shift);
109
} else {
70
}
110
- tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr,
71
+ val |= tmp;
111
- length, idxmap, bits);
112
+ tlb_flush_range_by_mmuidx(env_cpu(env), range.base,
113
+ range.length, idxmap, bits);
72
}
114
}
73
return val;
74
}
115
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
110
- }
111
- tmp2 = tcg_temp_new_i32();
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
113
- ptr1 = vfp_reg_ptr(true, a->vn);
114
- tmp4 = tcg_const_i32(n);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
122
} else {
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
125
}
126
- tmp3 = tcg_temp_new_i32();
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
129
- tcg_temp_free_i32(tmp);
130
- tcg_temp_free_i32(tmp4);
131
- tcg_temp_free_ptr(ptr1);
132
+ val = tcg_temp_new_i64();
133
+ read_neon_element64(val, a->vm, 0, MO_64);
134
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
137
- tcg_temp_free_i32(tmp2);
138
- tcg_temp_free_i32(tmp3);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
140
+ write_neon_element64(val, a->vd, 0, MO_64);
141
+
142
+ tcg_temp_free_i64(def);
143
+ tcg_temp_free_i64(val);
144
+ tcg_temp_free_i32(desc);
145
return true;
146
}
147
116
148
--
117
--
149
2.20.1
118
2.25.1
150
151
diff view generated by jsdifflib
[PULL 03/16] target/arm: add spaces around operator
[PULL 20/26] target/arm: Fix TLBIRange.base for 16k and 64k pages
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fix code style. Operator needs spaces both sides.
3
The shift of the BaseADDR field depends on the translation
4
granule in use.
4
5
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE")
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Reported-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220301215958.157011-14-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/arch_dump.c | 8 ++++----
13
target/arm/helper.c | 5 +++--
12
target/arm/arm-semi.c | 8 ++++----
14
1 file changed, 3 insertions(+), 2 deletions(-)
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
15
15
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/arch_dump.c
19
+++ b/target/arm/arch_dump.c
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
21
22
for (i = 0; i < 32; ++i) {
23
uint64_t *q = aa64_vfp_qreg(env, i);
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
28
}
29
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
32
*/
33
for (i = 0; i < 32; ++i) {
34
uint64_t tmp = note.vfp.vregs[2*i];
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
36
- note.vfp.vregs[2*i+1] = tmp;
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
38
+ note.vfp.vregs[2 * i + 1] = tmp;
39
}
40
}
41
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/arm-semi.c
45
+++ b/target/arm/arm-semi.c
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
47
if (use_gdb_syscalls()) {
48
arm_semi_open_guestfd = guestfd;
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
83
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/helper.c
18
--- a/target/arm/helper.c
85
+++ b/target/arm/helper.c
19
+++ b/target/arm/helper.c
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
20
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
87
uint32_t sum;
21
ret.length = (num + 1) << (exponent + page_shift);
88
sum = do_usad(a, b);
22
89
sum += do_usad(a >> 8, b >> 8);
23
if (regime_has_2_ranges(mmuidx)) {
90
- sum += do_usad(a >> 16, b >>16);
24
- ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
91
+ sum += do_usad(a >> 16, b >> 16);
25
+ ret.base = sextract64(value, 0, 37);
92
sum += do_usad(a >> 24, b >> 24);
26
} else {
93
return sum;
27
- ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS;
28
+ ret.base = extract64(value, 0, 37);
29
}
30
+ ret.base <<= page_shift;
31
32
return ret;
94
}
33
}
95
--
34
--
96
2.20.1
35
2.25.1
97
98
diff view generated by jsdifflib
New patch
[PULL 21/26] target/arm: Validate tlbi TG matches translation granule in use
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
For FEAT_LPA2, we will need other ARMVAParameters, which themselves
4
depend on the translation granule in use. We might as well validate
5
that the given TG matches; the architecture "does not require that
6
the instruction invalidates any entries" if this is not true.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220301215958.157011-15-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper.c | 10 +++++++---
14
1 file changed, 7 insertions(+), 3 deletions(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
21
uint64_t value)
22
{
23
unsigned int page_size_granule, page_shift, num, scale, exponent;
24
+ /* Extract one bit to represent the va selector in use. */
25
+ uint64_t select = sextract64(value, 36, 1);
26
+ ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true);
27
TLBIRange ret = { };
28
29
page_size_granule = extract64(value, 46, 2);
30
31
- if (page_size_granule == 0) {
32
- qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
33
+ /* The granule encoded in value must match the granule in use. */
34
+ if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) {
35
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n",
36
page_size_granule);
37
return ret;
38
}
39
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
40
41
ret.length = (num + 1) << (exponent + page_shift);
42
43
- if (regime_has_2_ranges(mmuidx)) {
44
+ if (param.select) {
45
ret.base = sextract64(value, 0, 37);
46
} else {
47
ret.base = extract64(value, 0, 37);
48
--
49
2.25.1
diff view generated by jsdifflib
New patch
[PULL 22/26] target/arm: Advertise all page sizes for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We support 16k pages, but do not advertize that in ID_AA64MMFR0.
4
5
The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer
6
to the same support as stage1 lookups. This setting is deprecated, so
7
indicate support for all stage2 page sizes directly.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20220301215958.157011-16-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu64.c | 4 ++++
15
1 file changed, 4 insertions(+)
16
17
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu64.c
20
+++ b/target/arm/cpu64.c
21
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
22
23
t = cpu->isar.id_aa64mmfr0;
24
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
25
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
26
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
27
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
28
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
29
cpu->isar.id_aa64mmfr0 = t;
30
31
t = cpu->isar.id_aa64mmfr1;
32
--
33
2.25.1
diff view generated by jsdifflib
[PULL 11/16] hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
[PULL 23/26] target/arm: Implement FEAT_LPA2
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
3
This feature widens physical addresses (and intermediate physical
4
OMAP2 chip support") takes care of creating the 3 UARTs.
4
addresses for 2-stage translation) from 48 to 52 bits, when using
5
5
4k or 16k pages.
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
6
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
7
This introduces the DS bit to TCR_ELx, which is RES0 unless the
8
which create the UART and connects it to an IRQ output,
8
page size is enabled and supports LPA2, resulting in the effective
9
overwritting the existing peripheral and its IRQ connection.
9
value of DS for a given table walk. The DS bit changes the format
10
This is incorrect.
10
of the page table descriptor slightly, moving the PS field out to
11
11
TCR so that all pages have the same sharability and repurposing
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
12
those bits of the page table descriptor for the highest bits of
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
13
the output address.
14
chardev") removed the use of this peripheral. We can simply
14
15
remove the code.
15
Do not yet enable FEAT_LPA2; we need extra plumbing to avoid
16
16
tickling an old kernel bug.
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20220301215958.157011-17-richard.henderson@linaro.org
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
---
22
hw/arm/nseries.c | 11 -----------
23
docs/system/arm/emulation.rst | 1 +
23
1 file changed, 11 deletions(-)
24
target/arm/cpu.h | 22 ++++++++
24
25
target/arm/internals.h | 2 +
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
26
target/arm/helper.c | 102 +++++++++++++++++++++++++++++-----
27
4 files changed, 112 insertions(+), 15 deletions(-)
28
29
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
26
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/nseries.c
31
--- a/docs/system/arm/emulation.rst
28
+++ b/hw/arm/nseries.c
32
+++ b/docs/system/arm/emulation.rst
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
33
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
34
- FEAT_JSCVT (JavaScript conversion instructions)
35
- FEAT_LOR (Limited ordering regions)
36
- FEAT_LPA (Large Physical Address space)
37
+- FEAT_LPA2 (Large Physical and virtual Address space v2)
38
- FEAT_LRCPC (Load-acquire RCpc instructions)
39
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
40
- FEAT_LSE (Large System Extensions)
41
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/cpu.h
44
+++ b/target/arm/cpu.h
45
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
46
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
31
}
47
}
32
48
33
-static void n8x0_uart_setup(struct n800_s *s)
49
+static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
34
-{
50
+{
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
51
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
36
- /*
52
+}
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
53
+
38
- * here, but this code has been removed with the bluetooth backend.
54
+static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
39
- */
55
+{
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
56
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
41
-}
57
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
42
-
58
+}
43
static void n8x0_usb_setup(struct n800_s *s)
59
+
60
+static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
61
+{
62
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
63
+}
64
+
65
+static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
66
+{
67
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
68
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
69
+}
70
+
71
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
44
{
72
{
45
SysBusDevice *dev;
73
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
74
diff --git a/target/arm/internals.h b/target/arm/internals.h
47
n8x0_spi_setup(s);
75
index XXXXXXX..XXXXXXX 100644
48
n8x0_dss_setup(s);
76
--- a/target/arm/internals.h
49
n8x0_cbus_setup(s);
77
+++ b/target/arm/internals.h
50
- n8x0_uart_setup(s);
78
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
51
if (machine_usb(machine)) {
79
typedef struct ARMVAParameters {
52
n8x0_usb_setup(s);
80
unsigned tsz : 8;
53
}
81
unsigned ps : 3;
82
+ unsigned sh : 2;
83
unsigned select : 1;
84
bool tbi : 1;
85
bool epd : 1;
86
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
87
bool using16k : 1;
88
bool using64k : 1;
89
bool tsz_oob : 1; /* tsz has been clamped to legal range */
90
+ bool ds : 1;
91
} ARMVAParameters;
92
93
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
94
diff --git a/target/arm/helper.c b/target/arm/helper.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/target/arm/helper.c
97
+++ b/target/arm/helper.c
98
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
99
} else {
100
ret.base = extract64(value, 0, 37);
101
}
102
+ if (param.ds) {
103
+ /*
104
+ * With DS=1, BaseADDR is always shifted 16 so that it is able
105
+ * to address all 52 va bits. The input address is perforce
106
+ * aligned on a 64k boundary regardless of translation granule.
107
+ */
108
+ page_shift = 16;
109
+ }
110
ret.base <<= page_shift;
111
112
return ret;
113
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
114
const int grainsize = stride + 3;
115
int startsizecheck;
116
117
- /* Negative levels are never allowed. */
118
- if (level < 0) {
119
+ /*
120
+ * Negative levels are usually not allowed...
121
+ * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
122
+ * begins with level -1. Note that previous feature tests will have
123
+ * eliminated this combination if it is not enabled.
124
+ */
125
+ if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
126
return false;
127
}
128
129
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
130
ARMMMUIdx mmu_idx, bool data)
131
{
132
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
133
- bool epd, hpd, using16k, using64k, tsz_oob;
134
- int select, tsz, tbi, max_tsz, min_tsz, ps;
135
+ bool epd, hpd, using16k, using64k, tsz_oob, ds;
136
+ int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
137
+ ARMCPU *cpu = env_archcpu(env);
138
139
if (!regime_has_2_ranges(mmu_idx)) {
140
select = 0;
141
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
142
hpd = extract32(tcr, 24, 1);
143
}
144
epd = false;
145
+ sh = extract32(tcr, 12, 2);
146
ps = extract32(tcr, 16, 3);
147
+ ds = extract64(tcr, 32, 1);
148
} else {
149
/*
150
* Bit 55 is always between the two regions, and is canonical for
151
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
152
if (!select) {
153
tsz = extract32(tcr, 0, 6);
154
epd = extract32(tcr, 7, 1);
155
+ sh = extract32(tcr, 12, 2);
156
using64k = extract32(tcr, 14, 1);
157
using16k = extract32(tcr, 15, 1);
158
hpd = extract64(tcr, 41, 1);
159
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
160
using64k = tg == 3;
161
tsz = extract32(tcr, 16, 6);
162
epd = extract32(tcr, 23, 1);
163
+ sh = extract32(tcr, 28, 2);
164
hpd = extract64(tcr, 42, 1);
165
}
166
ps = extract64(tcr, 32, 3);
167
+ ds = extract64(tcr, 59, 1);
168
}
169
170
- if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
171
+ if (cpu_isar_feature(aa64_st, cpu)) {
172
max_tsz = 48 - using64k;
173
} else {
174
max_tsz = 39;
175
}
176
177
+ /*
178
+ * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
179
+ * adjust the effective value of DS, as documented.
180
+ */
181
min_tsz = 16;
182
if (using64k) {
183
- if (cpu_isar_feature(aa64_lva, env_archcpu(env))) {
184
+ if (cpu_isar_feature(aa64_lva, cpu)) {
185
+ min_tsz = 12;
186
+ }
187
+ ds = false;
188
+ } else if (ds) {
189
+ switch (mmu_idx) {
190
+ case ARMMMUIdx_Stage2:
191
+ case ARMMMUIdx_Stage2_S:
192
+ if (using16k) {
193
+ ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu);
194
+ } else {
195
+ ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu);
196
+ }
197
+ break;
198
+ default:
199
+ if (using16k) {
200
+ ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu);
201
+ } else {
202
+ ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu);
203
+ }
204
+ break;
205
+ }
206
+ if (ds) {
207
min_tsz = 12;
208
}
209
}
210
- /* TODO: FEAT_LPA2 */
211
212
if (tsz > max_tsz) {
213
tsz = max_tsz;
214
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
215
return (ARMVAParameters) {
216
.tsz = tsz,
217
.ps = ps,
218
+ .sh = sh,
219
.select = select,
220
.tbi = tbi,
221
.epd = epd,
222
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
223
.using16k = using16k,
224
.using64k = using64k,
225
.tsz_oob = tsz_oob,
226
+ .ds = ds,
227
};
228
}
229
230
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
231
* VTCR_EL2.SL0 field (whose interpretation depends on the page size)
232
*/
233
uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
234
+ uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1);
235
uint32_t startlevel;
236
bool ok;
237
238
- if (!aarch64 || stride == 9) {
239
+ /* SL2 is RES0 unless DS=1 & 4kb granule. */
240
+ if (param.ds && stride == 9 && sl2) {
241
+ if (sl0 != 0) {
242
+ level = 0;
243
+ fault_type = ARMFault_Translation;
244
+ goto do_fault;
245
+ }
246
+ startlevel = -1;
247
+ } else if (!aarch64 || stride == 9) {
248
/* AArch32 or 4KB pages */
249
startlevel = 2 - sl0;
250
251
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
252
* for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
253
* or an AddressSize fault is raised. So for v8 we extract those SBZ
254
* bits as part of the address, which will be checked via outputsize.
255
- * For AArch64, the address field always goes up to bit 47 (with extra
256
- * bits for FEAT_LPA placed elsewhere). AArch64 implies v8.
257
+ * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
258
+ * the highest bits of a 52-bit output are placed elsewhere.
259
*/
260
- if (arm_feature(env, ARM_FEATURE_V8)) {
261
+ if (param.ds) {
262
+ descaddrmask = MAKE_64BIT_MASK(0, 50);
263
+ } else if (arm_feature(env, ARM_FEATURE_V8)) {
264
descaddrmask = MAKE_64BIT_MASK(0, 48);
265
} else {
266
descaddrmask = MAKE_64BIT_MASK(0, 40);
267
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
268
269
/*
270
* For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
271
- * of descriptor. Otherwise, if descaddr is out of range, raise
272
- * AddressSizeFault.
273
+ * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
274
+ * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
275
+ * raise AddressSizeFault.
276
*/
277
if (outputsize > 48) {
278
- descaddr |= extract64(descriptor, 12, 4) << 48;
279
+ if (param.ds) {
280
+ descaddr |= extract64(descriptor, 8, 2) << 50;
281
+ } else {
282
+ descaddr |= extract64(descriptor, 12, 4) << 48;
283
+ }
284
} else if (descaddr >> outputsize) {
285
fault_type = ARMFault_AddressSize;
286
goto do_fault;
287
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
288
assert(attrindx <= 7);
289
cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
290
}
291
- cacheattrs->shareability = extract32(attrs, 6, 2);
292
+
293
+ /*
294
+ * For FEAT_LPA2 and effective DS, the SH field in the attributes
295
+ * was re-purposed for output address bits. The SH attribute in
296
+ * that case comes from TCR_ELx, which we extracted earlier.
297
+ */
298
+ if (param.ds) {
299
+ cacheattrs->shareability = param.sh;
300
+ } else {
301
+ cacheattrs->shareability = extract32(attrs, 6, 2);
302
+ }
303
304
*phys_ptr = descaddr;
305
*page_size_ptr = page_size;
54
--
306
--
55
2.20.1
307
2.25.1
56
57
diff view generated by jsdifflib
[PULL 16/16] target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
[PULL 24/26] target/arm: Report KVM's actual PSCI version to guest in dtb
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
1
When we're using KVM, the PSCI implementation is provided by the
2
check, except in special cases. Move a stray UNDEF check in the VTBL
2
kernel, but QEMU has to tell the guest about it via the device tree.
3
trans function up above the access check.
3
Currently we look at the KVM_CAP_ARM_PSCI_0_2 capability to determine
4
if the kernel is providing at least PSCI 0.2, but if the kernel
5
provides a newer version than that we will still only tell the guest
6
it has PSCI 0.2. (This is fairly harmless; it just means the guest
7
won't use newer parts of the PSCI API.)
8
9
The kernel exposes the specific PSCI version it is implementing via
10
the ONE_REG API; use this to report in the dtb that the PSCI
11
implementation is 1.0-compatible if appropriate. (The device tree
12
binding currently only distinguishes "pre-0.2", "0.2-compatible" and
13
"1.0-compatible".)
4
14
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Marc Zyngier <maz@kernel.org>
17
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
19
Reviewed-by: Andrew Jones <drjones@redhat.com>
20
Message-id: 20220224134655.1207865-1-peter.maydell@linaro.org
8
---
21
---
9
target/arm/translate-neon.c.inc | 8 ++++----
22
target/arm/kvm-consts.h | 1 +
10
1 file changed, 4 insertions(+), 4 deletions(-)
23
hw/arm/boot.c | 5 ++---
24
target/arm/kvm64.c | 12 ++++++++++++
25
3 files changed, 15 insertions(+), 3 deletions(-)
11
26
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
27
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
13
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate-neon.c.inc
29
--- a/target/arm/kvm-consts.h
15
+++ b/target/arm/translate-neon.c.inc
30
+++ b/target/arm/kvm-consts.h
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
31
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES);
17
return false;
32
33
#define QEMU_PSCI_VERSION_0_1 0x00001
34
#define QEMU_PSCI_VERSION_0_2 0x00002
35
+#define QEMU_PSCI_VERSION_1_0 0x10000
36
#define QEMU_PSCI_VERSION_1_1 0x10001
37
38
MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
39
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/boot.c
42
+++ b/hw/arm/boot.c
43
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
18
}
44
}
19
45
20
- if (!vfp_access_check(s)) {
46
qemu_fdt_add_subnode(fdt, "/psci");
21
- return true;
47
- if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 ||
22
- }
48
- armcpu->psci_version == QEMU_PSCI_VERSION_1_1) {
23
-
49
- if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) {
24
if ((a->vn + a->len + 1) > 32) {
50
+ if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) {
25
/*
51
+ if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) {
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
52
const char comp[] = "arm,psci-0.2\0arm,psci";
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
53
qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
28
return false;
54
} else {
55
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/kvm64.c
58
+++ b/target/arm/kvm64.c
59
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
60
uint64_t mpidr;
61
ARMCPU *cpu = ARM_CPU(cs);
62
CPUARMState *env = &cpu->env;
63
+ uint64_t psciver;
64
65
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
66
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
67
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
68
}
29
}
69
}
30
70
31
+ if (!vfp_access_check(s)) {
71
+ /*
32
+ return true;
72
+ * KVM reports the exact PSCI version it is implementing via a
73
+ * special sysreg. If it is present, use its contents to determine
74
+ * what to report to the guest in the dtb (it is the PSCI version,
75
+ * in the same 15-bits major 16-bits minor format that PSCI_VERSION
76
+ * returns).
77
+ */
78
+ if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) {
79
+ cpu->psci_version = psciver;
33
+ }
80
+ }
34
+
81
+
35
desc = tcg_const_i32((a->vn << 2) | a->len);
82
/*
36
def = tcg_temp_new_i64();
83
* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
37
if (a->op) {
84
* Currently KVM has its own idea about MPIDR assignment, so we
38
--
85
--
39
2.20.1
86
2.25.1
40
41
diff view generated by jsdifflib
New patch
[PULL 25/26] ui/cocoa.m: Fix updateUIInfo threading issues
1
The updateUIInfo method makes Cocoa API calls. It also calls back
2
into QEMU functions like dpy_set_ui_info(). To do this safely, we
3
need to follow two rules:
4
* Cocoa API calls are made on the Cocoa UI thread
5
* When calling back into QEMU we must hold the iothread lock
1
6
7
Fix the places where we got this wrong, by taking the iothread lock
8
while executing updateUIInfo, and moving the call in cocoa_switch()
9
inside the dispatch_async block.
10
11
Some of the Cocoa UI methods which call updateUIInfo are invoked as
12
part of the initial application startup, while we're still doing the
13
little cross-thread dance described in the comment just above
14
call_qemu_main(). This meant they were calling back into the QEMU UI
15
layer before we'd actually finished initializing our display and
16
registered the DisplayChangeListener, which isn't really valid. Once
17
updateUIInfo takes the iothread lock, we no longer get away with
18
this, because during this startup phase the iothread lock is held by
19
the QEMU main-loop thread which is waiting for us to finish our
20
display initialization. So we must suppress updateUIInfo until
21
applicationDidFinishLaunching allows the QEMU main-loop thread to
22
continue.
23
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
26
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
27
Message-id: 20220224101330.967429-2-peter.maydell@linaro.org
28
---
29
ui/cocoa.m | 25 ++++++++++++++++++++++---
30
1 file changed, 22 insertions(+), 3 deletions(-)
31
32
diff --git a/ui/cocoa.m b/ui/cocoa.m
33
index XXXXXXX..XXXXXXX 100644
34
--- a/ui/cocoa.m
35
+++ b/ui/cocoa.m
36
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
37
}
38
}
39
40
-- (void) updateUIInfo
41
+- (void) updateUIInfoLocked
42
{
43
+ /* Must be called with the iothread lock, i.e. via updateUIInfo */
44
NSSize frameSize;
45
QemuUIInfo info;
46
47
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
48
dpy_set_ui_info(dcl.con, &info, TRUE);
49
}
50
51
+- (void) updateUIInfo
52
+{
53
+ if (!allow_events) {
54
+ /*
55
+ * Don't try to tell QEMU about UI information in the application
56
+ * startup phase -- we haven't yet registered dcl with the QEMU UI
57
+ * layer, and also trying to take the iothread lock would deadlock.
58
+ * When cocoa_display_init() does register the dcl, the UI layer
59
+ * will call cocoa_switch(), which will call updateUIInfo, so
60
+ * we don't lose any information here.
61
+ */
62
+ return;
63
+ }
64
+
65
+ with_iothread_lock(^{
66
+ [self updateUIInfoLocked];
67
+ });
68
+}
69
+
70
- (void)viewDidMoveToWindow
71
{
72
[self updateUIInfo];
73
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
74
75
COCOA_DEBUG("qemu_cocoa: cocoa_switch\n");
76
77
- [cocoaView updateUIInfo];
78
-
79
// The DisplaySurface will be freed as soon as this callback returns.
80
// We take a reference to the underlying pixman image here so it does
81
// not disappear from under our feet; the switchSurface method will
82
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
83
pixman_image_ref(image);
84
85
dispatch_async(dispatch_get_main_queue(), ^{
86
+ [cocoaView updateUIInfo];
87
[cocoaView switchSurface:image];
88
});
89
[pool release];
90
--
91
2.25.1
diff view generated by jsdifflib
New patch
[PULL 26/26] ui/cocoa.m: Remove unnecessary NSAutoreleasePools
1
In commit 6e657e64cdc478 in 2013 we added some autorelease pools to
2
deal with complaints from macOS when we made calls into Cocoa from
3
threads that didn't have automatically created autorelease pools.
4
Later on, macOS got stricter about forbidding cross-thread Cocoa
5
calls, and in commit 5588840ff77800e839d8 we restructured the code to
6
avoid them. This left the autorelease pool creation in several
7
functions without any purpose; delete it.
1
8
9
We still need the pool in cocoa_refresh() for the clipboard related
10
code which is called directly there.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
14
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
15
Message-id: 20220224101330.967429-3-peter.maydell@linaro.org
16
---
17
ui/cocoa.m | 6 ------
18
1 file changed, 6 deletions(-)
19
20
diff --git a/ui/cocoa.m b/ui/cocoa.m
21
index XXXXXXX..XXXXXXX 100644
22
--- a/ui/cocoa.m
23
+++ b/ui/cocoa.m
24
@@ -XXX,XX +XXX,XX @@ int main (int argc, char **argv) {
25
static void cocoa_update(DisplayChangeListener *dcl,
26
int x, int y, int w, int h)
27
{
28
- NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init];
29
-
30
COCOA_DEBUG("qemu_cocoa: cocoa_update\n");
31
32
dispatch_async(dispatch_get_main_queue(), ^{
33
@@ -XXX,XX +XXX,XX @@ static void cocoa_update(DisplayChangeListener *dcl,
34
}
35
[cocoaView setNeedsDisplayInRect:rect];
36
});
37
-
38
- [pool release];
39
}
40
41
static void cocoa_switch(DisplayChangeListener *dcl,
42
DisplaySurface *surface)
43
{
44
- NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init];
45
pixman_image_t *image = surface->image;
46
47
COCOA_DEBUG("qemu_cocoa: cocoa_switch\n");
48
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
49
[cocoaView updateUIInfo];
50
[cocoaView switchSurface:image];
51
});
52
- [pool release];
53
}
54
55
static void cocoa_refresh(DisplayChangeListener *dcl)
56
--
57
2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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