1
Patches for rc1: nothing major, just some minor bugfixes and
1
A few patches for the rc today...
2
code cleanups.
3
2
4
-- PMM
3
The following changes since commit 109918d24a3bb9ed3d05beb34ea4ac6be443c138:
5
4
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
5
Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-for-6.0-pull-request' into staging (2021-04-05 22:15:38 +0100)
7
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
9
6
10
are available in the Git repository at:
7
are available in the Git repository at:
11
8
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210406
13
10
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
11
for you to fetch changes up to 49bc76550c37f4a2b92a05cb3e6989a739d56ac9:
15
12
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
13
Remove myself as i.mx31 maintainer (2021-04-06 11:49:15 +0100)
17
14
18
----------------------------------------------------------------
15
----------------------------------------------------------------
19
target-arm queue:
16
target-arm queue:
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
17
* ppc/e500 and arm/virt: only add valid dynamic sysbus devices to the
21
* Minor coding style fixes
18
platform bus
22
* docs: add some notes on the sbsa-ref machine
19
* update i.mx31 maintainer list
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
20
* Revert "target/arm: Make number of counters in PMCR follow the CPU"
24
* target/arm: Fix neon VTBL/VTBX for len > 1
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
30
* hw/arm/nseries: Check return value from load_image_targphys()
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
33
21
34
----------------------------------------------------------------
22
----------------------------------------------------------------
35
Alex Bennée (1):
23
Chubb, Peter (Data61, Eveleigh) (1):
36
docs: add some notes on the sbsa-ref machine
24
Remove myself as i.mx31 maintainer
37
25
38
AlexChen (1):
26
Peter Maydell (5):
39
ssi: Fix bad printf format specifiers
27
include/hw/boards.h: Document machine_class_allow_dynamic_sysbus_dev()
28
machine: Provide a function to check the dynamic sysbus allowlist
29
hw/arm/virt: Only try to add valid dynamic sysbus devices to platform bus
30
hw/ppc/e500plat: Only try to add valid dynamic sysbus devices to platform bus
31
Revert "target/arm: Make number of counters in PMCR follow the CPU"
40
32
41
Andrew Jones (1):
33
include/hw/boards.h | 39 +++++++++++++++++++++++++++++++++++++++
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
34
target/arm/cpu.h | 1 -
35
hw/arm/virt.c | 8 ++++++--
36
hw/core/machine.c | 21 ++++++++++++++++-----
37
hw/ppc/e500plat.c | 8 ++++++--
38
target/arm/cpu64.c | 3 ---
39
target/arm/cpu_tcg.c | 5 -----
40
target/arm/helper.c | 29 ++++++++++++-----------------
41
target/arm/kvm64.c | 2 --
42
MAINTAINERS | 1 -
43
10 files changed, 79 insertions(+), 38 deletions(-)
43
44
44
Havard Skinnemoen (1):
45
tests/qtest/npcm7xx_rng-test: count runs properly
46
47
Peter Maydell (2):
48
hw/arm/nseries: Check return value from load_image_targphys()
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
50
51
Philippe Mathieu-Daudé (6):
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
53
hw/arm/armsse: Correct expansion MPC interrupt lines
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
58
59
Richard Henderson (1):
60
target/arm: Fix neon VTBL/VTBX for len > 1
61
62
Xinhao Zhang (3):
63
target/arm: add spaces around operator
64
target/arm: Don't use '#' flag of printf format
65
target/arm: add space before the open parenthesis '('
66
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
68
docs/system/target-arm.rst | 1 +
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
70
target/arm/helper.h | 2 +-
71
hw/arm/armsse.c | 3 +-
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
73
hw/arm/nseries.c | 26 ++++++++----------
74
hw/arm/stm32f205_soc.c | 1 -
75
hw/misc/stm32f2xx_syscfg.c | 2 --
76
hw/ssi/imx_spi.c | 2 +-
77
hw/ssi/xilinx_spi.c | 2 +-
78
target/arm/arch_dump.c | 8 +++---
79
target/arm/arm-semi.c | 8 +++---
80
target/arm/helper.c | 2 +-
81
target/arm/op_helper.c | 23 +++++++++-------
82
target/arm/translate-a64.c | 4 +--
83
target/arm/translate.c | 2 +-
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
85
hw/arm/Kconfig | 3 +-
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
87
20 files changed, 123 insertions(+), 98 deletions(-)
88
create mode 100644 docs/system/arm/sbsa.rst
89
diff view generated by jsdifflib
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
5
in the build when building armv7m_systick.
6
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/Kconfig | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/Kconfig
18
+++ b/hw/arm/Kconfig
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
20
21
config ARM_V7M
22
bool
23
+ select PTIMER
24
25
config ALLWINNER_A10
26
bool
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
Deleted patch
1
From: AlexChen <alex.chen@huawei.com>
2
1
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 5FA280F5.8060902@huawei.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/ssi/imx_spi.c | 2 +-
13
hw/ssi/xilinx_spi.c | 2 +-
14
2 files changed, 2 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/ssi/imx_spi.c
19
+++ b/hw/ssi/imx_spi.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
21
case ECSPI_MSGDATA:
22
return "ECSPI_MSGDATA";
23
default:
24
- sprintf(unknown, "%d ?", reg);
25
+ sprintf(unknown, "%u ?", reg);
26
return unknown;
27
}
28
}
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/ssi/xilinx_spi.c
32
+++ b/hw/ssi/xilinx_spi.c
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
34
irq chain unless things really changed. */
35
if (pending != s->irqline) {
36
s->irqline = pending;
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
40
qemu_set_irq(s->irq, pending);
41
}
42
--
43
2.20.1
44
45
diff view generated by jsdifflib
1
From: Havard Skinnemoen <hskinnemoen@google.com>
1
The function machine_class_allow_dynamic_sysbus_dev() is currently
2
undocumented; add a doc comment.
2
3
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
plus one. Currently, it's counting the number of times these transitions
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
do _not_ happen, plus one.
6
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20210325153310.9131-2-peter.maydell@linaro.org
9
---
10
include/hw/boards.h | 15 +++++++++++++++
11
1 file changed, 15 insertions(+)
6
12
7
Source:
13
diff --git a/include/hw/boards.h b/include/hw/boards.h
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
9
section 2.3.4 point (3).
10
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
17
1 file changed, 1 insertion(+), 1 deletion(-)
18
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
20
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
21
--- a/tests/qtest/npcm7xx_rng-test.c
15
--- a/include/hw/boards.h
22
+++ b/tests/qtest/npcm7xx_rng-test.c
16
+++ b/include/hw/boards.h
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
17
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
24
pi = (double)nr_ones / nr_bits;
18
const CpuInstanceProperties *props,
25
19
Error **errp);
26
for (k = 0; k < nr_bits - 1; k++) {
20
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
21
+/**
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
22
+ * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices
29
}
23
+ * @mc: Machine class
30
vn_obs += 1;
24
+ * @type: type to allow (should be a subtype of TYPE_SYS_BUS_DEVICE)
31
25
+ *
26
+ * Add the QOM type @type to the list of devices of which are subtypes
27
+ * of TYPE_SYS_BUS_DEVICE but which are still permitted to be dynamically
28
+ * created (eg by the user on the command line with -device).
29
+ * By default if the user tries to create any devices on the command line
30
+ * that are subtypes of TYPE_SYS_BUS_DEVICE they will get an error message;
31
+ * for the special cases which are permitted for this machine model, the
32
+ * machine model class init code must call this function to add them
33
+ * to the list of specifically permitted devices.
34
+ */
35
void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type);
36
+
37
/*
38
* Checks that backend isn't used, preps it for exclusive usage and
39
* returns migratable MemoryRegion provided by backend.
32
--
40
--
33
2.20.1
41
2.20.1
34
42
35
43
diff view generated by jsdifflib
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
Provide a new function dynamic_sysbus_dev_allowed() which checks the
2
per-machine list of permitted dynamic sysbus devices and returns a
3
boolean result indicating whether the device is allowed. We can use
4
this in the implementation of validate_sysbus_device(), but we will
5
also need it so that machine hotplug callbacks can validate devices
6
rather than assuming that any sysbus device might be hotpluggable
7
into the platform bus.
2
8
3
Fix code style. Don't use '#' flag of printf format ('%#') in
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
format strings, use '0x' prefix instead
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 20210325153310.9131-3-peter.maydell@linaro.org
14
---
15
include/hw/boards.h | 24 ++++++++++++++++++++++++
16
hw/core/machine.c | 21 ++++++++++++++++-----
17
2 files changed, 40 insertions(+), 5 deletions(-)
5
18
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
19
diff --git a/include/hw/boards.h b/include/hw/boards.h
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
21
--- a/include/hw/boards.h
18
+++ b/target/arm/translate-a64.c
22
+++ b/include/hw/boards.h
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
23
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
24
*/
21
break;
25
void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type);
22
default:
26
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
27
+/**
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
28
+ * device_is_dynamic_sysbus: test whether device is a dynamic sysbus device
25
__func__, insn, fpopcode, s->pc_curr);
29
+ * @mc: Machine class
26
g_assert_not_reached();
30
+ * @dev: device to check
27
}
31
+ *
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
32
+ * Returns: true if @dev is a sysbus device on the machine's list
29
case 0x7f: /* FSQRT (vector) */
33
+ * of dynamically pluggable sysbus devices; otherwise false.
30
break;
34
+ *
31
default:
35
+ * This function checks whether @dev is a valid dynamic sysbus device,
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
36
+ * by first confirming that it is a sysbus device and then checking it
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
37
+ * against the list of permitted dynamic sysbus devices which has been
34
g_assert_not_reached();
38
+ * set up by the machine using machine_class_allow_dynamic_sysbus_dev().
39
+ *
40
+ * It is valid to call this with something that is not a subclass of
41
+ * TYPE_SYS_BUS_DEVICE; the function will return false in this case.
42
+ * This allows hotplug callback functions to be written as:
43
+ * if (device_is_dynamic_sysbus(mc, dev)) {
44
+ * handle dynamic sysbus case;
45
+ * } else if (some other kind of hotplug) {
46
+ * handle that;
47
+ * }
48
+ */
49
+bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev);
50
+
51
/*
52
* Checks that backend isn't used, preps it for exclusive usage and
53
* returns migratable MemoryRegion provided by backend.
54
diff --git a/hw/core/machine.c b/hw/core/machine.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/core/machine.c
57
+++ b/hw/core/machine.c
58
@@ -XXX,XX +XXX,XX @@ void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type)
59
QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type));
60
}
61
62
-static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque)
63
+bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev)
64
{
65
- MachineState *machine = opaque;
66
- MachineClass *mc = MACHINE_GET_CLASS(machine);
67
bool allowed = false;
68
strList *wl;
69
+ Object *obj = OBJECT(dev);
70
+
71
+ if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) {
72
+ return false;
73
+ }
74
75
for (wl = mc->allowed_dynamic_sysbus_devices;
76
!allowed && wl;
77
wl = wl->next) {
78
- allowed |= !!object_dynamic_cast(OBJECT(sbdev), wl->value);
79
+ allowed |= !!object_dynamic_cast(obj, wl->value);
35
}
80
}
36
81
82
- if (!allowed) {
83
+ return allowed;
84
+}
85
+
86
+static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque)
87
+{
88
+ MachineState *machine = opaque;
89
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
90
+
91
+ if (!device_is_dynamic_sysbus(mc, DEVICE(sbdev))) {
92
error_report("Option '-device %s' cannot be handled by this machine",
93
object_class_get_name(object_get_class(OBJECT(sbdev))));
94
exit(1);
37
--
95
--
38
2.20.1
96
2.20.1
39
97
40
98
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The virt machine device plug callback currently calls
2
platform_bus_link_device() for any sysbus device. This is overly
3
broad, because platform_bus_link_device() will unconditionally grab
4
the IRQs and MMIOs of the device it is passed, whether it was
5
intended for the platform bus or not. Restrict hotpluggability of
6
sysbus devices to only those devices on the dynamic sysbus
7
allowlist.
2
8
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
9
We were mostly getting away with this because the board creates the
4
OMAP2 chip support") takes care of creating the 3 UARTs.
10
platform bus as the last device it creates, and so the hotplug
11
callback did not do anything for all the sysbus devices created by
12
the board itself. However if the user plugged in a device which
13
itself uses a sysbus device internally we would have mishandled this
14
and probably asserted.
5
15
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
which create the UART and connects it to an IRQ output,
18
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
9
overwritting the existing peripheral and its IRQ connection.
19
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
This is incorrect.
20
Message-id: 20210325153310.9131-4-peter.maydell@linaro.org
21
---
22
hw/arm/virt.c | 8 ++++++--
23
1 file changed, 6 insertions(+), 2 deletions(-)
11
24
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
16
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
hw/arm/nseries.c | 11 -----------
23
1 file changed, 11 deletions(-)
24
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
26
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/nseries.c
27
--- a/hw/arm/virt.c
28
+++ b/hw/arm/nseries.c
28
+++ b/hw/arm/virt.c
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
29
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
30
VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
31
}
31
32
32
if (vms->platform_bus_dev) {
33
-static void n8x0_uart_setup(struct n800_s *s)
33
- if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
34
-{
34
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
35
+
36
- /*
36
+ if (device_is_dynamic_sysbus(mc, dev)) {
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
37
platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
38
- * here, but this code has been removed with the bluetooth backend.
38
SYS_BUS_DEVICE(dev));
39
- */
39
}
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
40
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
41
-}
41
static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
42
-
42
DeviceState *dev)
43
static void n8x0_usb_setup(struct n800_s *s)
44
{
43
{
45
SysBusDevice *dev;
44
- if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE) ||
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
45
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
47
n8x0_spi_setup(s);
46
+
48
n8x0_dss_setup(s);
47
+ if (device_is_dynamic_sysbus(mc, dev) ||
49
n8x0_cbus_setup(s);
48
(object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
50
- n8x0_uart_setup(s);
49
return HOTPLUG_HANDLER(machine);
51
if (machine_usb(machine)) {
52
n8x0_usb_setup(s);
53
}
50
}
54
--
51
--
55
2.20.1
52
2.20.1
56
53
57
54
diff view generated by jsdifflib
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
1
The e500plat machine device plug callback currently calls
2
check, except in special cases. Move a stray UNDEF check in the VTBL
2
platform_bus_link_device() for any sysbus device. This is overly
3
trans function up above the access check.
3
broad, because platform_bus_link_device() will unconditionally grab
4
the IRQs and MMIOs of the device it is passed, whether it was
5
intended for the platform bus or not. Restrict hotpluggability of
6
sysbus devices to only those devices on the dynamic sysbus allowlist.
7
8
We were mostly getting away with this because the board creates the
9
platform bus as the last device it creates, and so the hotplug
10
callback did not do anything for all the sysbus devices created by
11
the board itself. However if the user plugged in a device which
12
itself uses a sysbus device internally we would have mishandled this
13
and probably asserted. An example of this is:
14
qemu-system-ppc64 -M ppce500 -device macio-oldworld
15
16
This isn't a sensible command because the macio-oldworld device
17
is really specific to the 'g3beige' machine, but we now fail
18
with a reasonable error message rather than asserting:
19
qemu-system-ppc64: Device heathrow is not supported by this machine yet.
4
20
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
23
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
24
Reviewed-by: Eric Auger <eric.auger@redhat.com>
25
Acked-by: David Gibson <david@gibson.dropbear.id.au>
26
Message-id: 20210325153310.9131-5-peter.maydell@linaro.org
8
---
27
---
9
target/arm/translate-neon.c.inc | 8 ++++----
28
hw/ppc/e500plat.c | 8 ++++++--
10
1 file changed, 4 insertions(+), 4 deletions(-)
29
1 file changed, 6 insertions(+), 2 deletions(-)
11
30
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
31
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
13
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/translate-neon.c.inc
33
--- a/hw/ppc/e500plat.c
15
+++ b/target/arm/translate-neon.c.inc
34
+++ b/hw/ppc/e500plat.c
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
35
@@ -XXX,XX +XXX,XX @@ static void e500plat_machine_device_plug_cb(HotplugHandler *hotplug_dev,
17
return false;
36
PPCE500MachineState *pms = PPCE500_MACHINE(hotplug_dev);
37
38
if (pms->pbus_dev) {
39
- if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
40
+ MachineClass *mc = MACHINE_GET_CLASS(pms);
41
+
42
+ if (device_is_dynamic_sysbus(mc, dev)) {
43
platform_bus_link_device(pms->pbus_dev, SYS_BUS_DEVICE(dev));
44
}
18
}
45
}
19
46
@@ -XXX,XX +XXX,XX @@ static
20
- if (!vfp_access_check(s)) {
47
HotplugHandler *e500plat_machine_get_hotpug_handler(MachineState *machine,
21
- return true;
48
DeviceState *dev)
22
- }
49
{
23
-
50
- if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
24
if ((a->vn + a->len + 1) > 32) {
51
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
25
/*
52
+
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
53
+ if (device_is_dynamic_sysbus(mc, dev)) {
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
54
return HOTPLUG_HANDLER(machine);
28
return false;
29
}
55
}
30
56
31
+ if (!vfp_access_check(s)) {
32
+ return true;
33
+ }
34
+
35
desc = tcg_const_i32((a->vn << 2) | a->len);
36
def = tcg_temp_new_i64();
37
if (a->op) {
38
--
57
--
39
2.20.1
58
2.20.1
40
59
41
60
diff view generated by jsdifflib
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
1
This reverts commit f7fb73b8cdd3f77e26f9fcff8cf24ff1b58d200f.
2
2
3
Fix code style. Operator needs spaces both sides.
3
This change turned out to be a bit half-baked, and doesn't
4
4
work with KVM, which fails with the error:
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
5
"qemu-system-aarch64: Failed to retrieve host CPU features"
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
6
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
7
because KVM does not allow accessing of the PMCR_EL0 value in
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
the scratch "query CPU ID registers" VM unless we have first
9
set the KVM_ARM_VCPU_PMU_V3 feature on the VM.
10
11
Revert the change for 6.0.
12
13
Reported-by: Zenghui Yu <yuzenghui@huawei.com>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Tested-by: Zenghui Yu <yuzenghui@huawei.com>
16
Message-id: 20210331154822.23332-1-peter.maydell@linaro.org
10
---
17
---
11
target/arm/arch_dump.c | 8 ++++----
18
target/arm/cpu.h | 1 -
12
target/arm/arm-semi.c | 8 ++++----
19
target/arm/cpu64.c | 3 ---
13
target/arm/helper.c | 2 +-
20
target/arm/cpu_tcg.c | 5 -----
14
3 files changed, 9 insertions(+), 9 deletions(-)
21
target/arm/helper.c | 29 ++++++++++++-----------------
15
22
target/arm/kvm64.c | 2 --
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
23
5 files changed, 12 insertions(+), 28 deletions(-)
17
index XXXXXXX..XXXXXXX 100644
24
18
--- a/target/arm/arch_dump.c
25
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
+++ b/target/arm/arch_dump.c
26
index XXXXXXX..XXXXXXX 100644
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
27
--- a/target/arm/cpu.h
21
28
+++ b/target/arm/cpu.h
22
for (i = 0; i < 32; ++i) {
29
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
23
uint64_t *q = aa64_vfp_qreg(env, i);
30
uint64_t id_aa64mmfr2;
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
31
uint64_t id_aa64dfr0;
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
32
uint64_t id_aa64dfr1;
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
33
- uint64_t reset_pmcr_el0;
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
34
} isar;
28
}
35
uint64_t midr;
29
36
uint32_t revidr;
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
37
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
38
index XXXXXXX..XXXXXXX 100644
32
*/
39
--- a/target/arm/cpu64.c
33
for (i = 0; i < 32; ++i) {
40
+++ b/target/arm/cpu64.c
34
uint64_t tmp = note.vfp.vregs[2*i];
41
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
42
cpu->gic_num_lrs = 4;
36
- note.vfp.vregs[2*i+1] = tmp;
43
cpu->gic_vpribits = 5;
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
44
cpu->gic_vprebits = 5;
38
+ note.vfp.vregs[2 * i + 1] = tmp;
45
- cpu->isar.reset_pmcr_el0 = 0x41013000;
39
}
46
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
40
}
47
}
41
48
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
49
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
43
index XXXXXXX..XXXXXXX 100644
50
cpu->gic_num_lrs = 4;
44
--- a/target/arm/arm-semi.c
51
cpu->gic_vpribits = 5;
45
+++ b/target/arm/arm-semi.c
52
cpu->gic_vprebits = 5;
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
53
- cpu->isar.reset_pmcr_el0 = 0x41033000;
47
if (use_gdb_syscalls()) {
54
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
48
arm_semi_open_guestfd = guestfd;
55
}
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
56
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
57
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
58
cpu->gic_num_lrs = 4;
52
} else {
59
cpu->gic_vpribits = 5;
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
60
cpu->gic_vprebits = 5;
54
if (ret == (uint32_t)-1) {
61
- cpu->isar.reset_pmcr_el0 = 0x41023000;
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
62
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
56
GET_ARG(1);
63
}
57
if (use_gdb_syscalls()) {
64
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
65
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
59
- arg0, (int)arg1+1);
66
index XXXXXXX..XXXXXXX 100644
60
+ arg0, (int)arg1 + 1);
67
--- a/target/arm/cpu_tcg.c
61
} else {
68
+++ b/target/arm/cpu_tcg.c
62
s = lock_user_string(arg0);
69
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
63
if (!s) {
70
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
71
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
65
GET_ARG(3);
72
cpu->reset_auxcr = 2;
66
if (use_gdb_syscalls()) {
73
- cpu->isar.reset_pmcr_el0 = 0x41002000;
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
74
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
75
}
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
76
70
} else {
77
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
71
char *s2;
78
cpu->clidr = (1 << 27) | (1 << 24) | 3;
72
s = lock_user_string(arg0);
79
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
80
cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
74
GET_ARG(1);
81
- cpu->isar.reset_pmcr_el0 = 0x41093000;
75
if (use_gdb_syscalls()) {
82
define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
83
}
77
- arg0, (int)arg1+1);
84
78
+ arg0, (int)arg1 + 1);
85
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
79
} else {
86
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
80
s = lock_user_string(arg0);
87
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
81
if (!s) {
88
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
89
- cpu->isar.reset_pmcr_el0 = 0x41072000;
90
define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
91
}
92
93
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
94
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
95
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
96
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
97
- cpu->isar.reset_pmcr_el0 = 0x410F3000;
98
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
99
}
100
101
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
102
cpu->isar.id_isar6 = 0x0;
103
cpu->mp_is_up = true;
104
cpu->pmsav7_dregion = 16;
105
- cpu->isar.reset_pmcr_el0 = 0x41151800;
106
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
107
}
108
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
109
diff --git a/target/arm/helper.c b/target/arm/helper.c
83
index XXXXXXX..XXXXXXX 100644
110
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/helper.c
111
--- a/target/arm/helper.c
85
+++ b/target/arm/helper.c
112
+++ b/target/arm/helper.c
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
113
@@ -XXX,XX +XXX,XX @@
87
uint32_t sum;
114
#endif
88
sum = do_usad(a, b);
115
89
sum += do_usad(a >> 8, b >> 8);
116
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
90
- sum += do_usad(a >> 16, b >>16);
117
+#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
91
+ sum += do_usad(a >> 16, b >> 16);
118
92
sum += do_usad(a >> 24, b >> 24);
119
#ifndef CONFIG_USER_ONLY
93
return sum;
120
94
}
121
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
122
123
static inline uint32_t pmu_num_counters(CPUARMState *env)
124
{
125
- ARMCPU *cpu = env_archcpu(env);
126
-
127
- return (cpu->isar.reset_pmcr_el0 & PMCRN_MASK) >> PMCRN_SHIFT;
128
+ return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
129
}
130
131
/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
132
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
133
.resetvalue = 0,
134
.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
135
#endif
136
+ /* The only field of MDCR_EL2 that has a defined architectural reset value
137
+ * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
138
+ */
139
+ { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
140
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
141
+ .access = PL2_RW, .resetvalue = PMCR_NUM_COUNTERS,
142
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
143
{ .name = "HPFAR", .state = ARM_CP_STATE_AA32,
144
.cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
145
.access = PL2_RW, .accessfn = access_el3_aa32ns,
146
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
147
* field as main ID register, and we implement four counters in
148
* addition to the cycle count register.
149
*/
150
- unsigned int i, pmcrn = pmu_num_counters(&cpu->env);
151
+ unsigned int i, pmcrn = PMCR_NUM_COUNTERS;
152
ARMCPRegInfo pmcr = {
153
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
154
.access = PL0_RW,
155
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
156
.access = PL0_RW, .accessfn = pmreg_access,
157
.type = ARM_CP_IO,
158
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
159
- .resetvalue = cpu->isar.reset_pmcr_el0,
160
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
161
+ PMCRLC,
162
.writefn = pmcr_write, .raw_writefn = raw_write,
163
};
164
-
165
define_one_arm_cp_reg(cpu, &pmcr);
166
define_one_arm_cp_reg(cpu, &pmcr64);
167
for (i = 0; i < pmcrn; i++) {
168
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
169
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
170
REGINFO_SENTINEL
171
};
172
- /*
173
- * The only field of MDCR_EL2 that has a defined architectural reset
174
- * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
175
- */
176
- ARMCPRegInfo mdcr_el2 = {
177
- .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
178
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
179
- .access = PL2_RW, .resetvalue = pmu_num_counters(env),
180
- .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2),
181
- };
182
- define_one_arm_cp_reg(cpu, &mdcr_el2);
183
define_arm_cp_regs(cpu, vpidr_regs);
184
define_arm_cp_regs(cpu, el2_cp_reginfo);
185
if (arm_feature(env, ARM_FEATURE_V8)) {
186
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
187
index XXXXXXX..XXXXXXX 100644
188
--- a/target/arm/kvm64.c
189
+++ b/target/arm/kvm64.c
190
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
191
ARM64_SYS_REG(3, 0, 0, 7, 1));
192
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
193
ARM64_SYS_REG(3, 0, 0, 7, 2));
194
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
195
- ARM64_SYS_REG(3, 3, 9, 12, 0));
196
197
/*
198
* Note that if AArch32 support is not present in the host,
95
--
199
--
96
2.20.1
200
2.20.1
97
201
98
202
diff view generated by jsdifflib
Deleted patch
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
1
3
Fix code style. Space required before the open parenthesis '('.
4
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
17
+++ b/target/arm/translate.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
19
- Hardware watchpoints.
20
Hardware breakpoints have already been handled and skip this code.
21
*/
22
- switch(dc->base.is_jmp) {
23
+ switch (dc->base.is_jmp) {
24
case DISAS_NEXT:
25
case DISAS_TOO_MANY:
26
gen_goto_tb(dc, 1, dc->base.pc_next);
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
Deleted patch
1
From: Alex Bennée <alex.bennee@linaro.org>
2
1
3
We should at least document what this machine is about.
4
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
8
Cc: Leif Lindholm <leif@nuviainc.com>
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
[PMM: fixed filename mismatch]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
15
docs/system/target-arm.rst | 1 +
16
2 files changed, 33 insertions(+)
17
create mode 100644 docs/system/arm/sbsa.rst
18
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
20
new file mode 100644
21
index XXXXXXX..XXXXXXX
22
--- /dev/null
23
+++ b/docs/system/arm/sbsa.rst
24
@@ -XXX,XX +XXX,XX @@
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
26
+==================================================================
27
+
28
+While the `virt` board is a generic board platform that doesn't match
29
+any real hardware the `sbsa-ref` board intends to look like real
30
+hardware. The `Server Base System Architecture
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
32
+minimum base line of hardware support and importantly how the firmware
33
+reports that to any operating system. It is a static system that
34
+reports a very minimal DT to the firmware for non-discoverable
35
+information about components affected by the qemu command line (i.e.
36
+cpus and memory). As a result it must have a firmware specifically
37
+built to expect a certain hardware layout (as you would in a real
38
+machine).
39
+
40
+It is intended to be a machine for developing firmware and testing
41
+standards compliance with operating systems.
42
+
43
+Supported devices
44
+"""""""""""""""""
45
+
46
+The sbsa-ref board supports:
47
+
48
+ - A configurable number of AArch64 CPUs
49
+ - GIC version 3
50
+ - System bus AHCI controller
51
+ - System bus EHCI controller
52
+ - CDROM and hard disc on AHCI bus
53
+ - E1000E ethernet card on PCIe bus
54
+ - VGA display adaptor on PCIe bus
55
+ - A generic SBSA watchdog device
56
+
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
58
index XXXXXXX..XXXXXXX 100644
59
--- a/docs/system/target-arm.rst
60
+++ b/docs/system/target-arm.rst
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
62
arm/mps2
63
arm/musca
64
arm/realview
65
+ arm/sbsa
66
arm/versatile
67
arm/vexpress
68
arm/aspeed
69
--
70
2.20.1
71
72
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: "Chubb, Peter (Data61, Eveleigh)" <Peter.Chubb@data61.csiro.au>
2
2
3
When using a Cortex-A15, the Virt machine does not use any
3
Remove Peter Chubb as i/MX31 maintainer.
4
MPCore peripherals. Remove the dependency.
5
4
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
5
I'm leaving my current job and will no longer have access to the
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
6
hardware to test or maintain this port.
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
8
Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
hw/arm/Kconfig | 1 -
12
MAINTAINERS | 1 -
14
1 file changed, 1 deletion(-)
13
1 file changed, 1 deletion(-)
15
14
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
15
diff --git a/MAINTAINERS b/MAINTAINERS
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Kconfig
17
--- a/MAINTAINERS
19
+++ b/hw/arm/Kconfig
18
+++ b/MAINTAINERS
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
19
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx25_ccm.h
21
imply VFIO_PLATFORM
20
F: include/hw/watchdog/wdt_imx2.h
22
imply VFIO_XGMAC
21
23
imply TPM_TIS_SYSBUS
22
i.MX31 (kzm)
24
- select A15MPCORE
23
-M: Peter Chubb <peter.chubb@nicta.com.au>
25
select ACPI
24
M: Peter Maydell <peter.maydell@linaro.org>
26
select ARM_SMMUV3
25
L: qemu-arm@nongnu.org
27
select GPIO_KEY
26
S: Odd Fixes
28
--
27
--
29
2.20.1
28
2.20.1
30
29
31
30
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The helper function did not get updated when we reorganized
4
the vector register file for SVE. Since then, the neon dregs
5
are non-sequential and cannot be simply indexed.
6
7
At the same time, make the helper function operate on 64-bit
8
quantities so that we do not have to call it twice.
9
10
Fixes: c39c2b9043e
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.h | 2 +-
19
target/arm/op_helper.c | 23 +++++++++--------
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
21
3 files changed, 29 insertions(+), 40 deletions(-)
22
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper.h
26
+++ b/target/arm/helper.h
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
33
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
41
cpu_loop_exit_restore(cs, ra);
42
}
43
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
45
- uint32_t maxindex)
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
47
+ uint64_t ireg, uint64_t def)
48
{
49
- uint32_t val, shift;
50
- uint64_t *table = vn;
51
+ uint64_t tmp, val = 0;
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
53
+ uint32_t base_reg = desc >> 2;
54
+ uint32_t shift, index, reg;
55
56
- val = 0;
57
- for (shift = 0; shift < 32; shift += 8) {
58
- uint32_t index = (ireg >> shift) & 0xff;
59
+ for (shift = 0; shift < 64; shift += 8) {
60
+ index = (ireg >> shift) & 0xff;
61
if (index < maxindex) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
63
- val |= tmp << shift;
64
+ reg = base_reg + (index >> 3);
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
110
- }
111
- tmp2 = tcg_temp_new_i32();
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
113
- ptr1 = vfp_reg_ptr(true, a->vn);
114
- tmp4 = tcg_const_i32(n);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
122
} else {
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
125
}
126
- tmp3 = tcg_temp_new_i32();
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
129
- tcg_temp_free_i32(tmp);
130
- tcg_temp_free_i32(tmp4);
131
- tcg_temp_free_ptr(ptr1);
132
+ val = tcg_temp_new_i64();
133
+ read_neon_element64(val, a->vm, 0, MO_64);
134
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
137
- tcg_temp_free_i32(tmp2);
138
- tcg_temp_free_i32(tmp3);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
140
+ write_neon_element64(val, a->vd, 0, MO_64);
141
+
142
+ tcg_temp_free_i64(def);
143
+ tcg_temp_free_i64(val);
144
+ tcg_temp_free_i32(desc);
145
return true;
146
}
147
148
--
149
2.20.1
150
151
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
We can use one MPC per SRAM bank, but we currently only wire the
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
5
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/armsse.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/armsse.c
18
+++ b/hw/arm/armsse.c
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
20
qdev_get_gpio_in(dev_splitter, 0));
21
qdev_connect_gpio_out(dev_splitter, 0,
22
qdev_get_gpio_in_named(dev_secctl,
23
- "mpc_status", 0));
24
+ "mpc_status",
25
+ i - IOTS_NUM_EXP_MPC));
26
}
27
28
qdev_connect_gpio_out(dev_splitter, 1,
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The system configuration controller (SYSCFG) doesn't have
4
any output IRQ (and the INTC input #71 belongs to the UART6).
5
Remove the invalid code.
6
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
14
hw/arm/stm32f205_soc.c | 1 -
15
hw/misc/stm32f2xx_syscfg.c | 2 --
16
3 files changed, 5 deletions(-)
17
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
23
uint32_t syscfg_exticr3;
24
uint32_t syscfg_exticr4;
25
uint32_t syscfg_cmpcr;
26
-
27
- qemu_irq irq;
28
};
29
30
#endif /* HW_STM32F2XX_SYSCFG_H */
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/stm32f205_soc.c
34
+++ b/hw/arm/stm32f205_soc.c
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
36
}
37
busdev = SYS_BUS_DEVICE(dev);
38
sysbus_mmio_map(busdev, 0, 0x40013800);
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
40
41
/* Attach UART (uses USART registers) and USART controllers */
42
for (i = 0; i < STM_NUM_USARTS; i++) {
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/misc/stm32f2xx_syscfg.c
46
+++ b/hw/misc/stm32f2xx_syscfg.c
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
48
{
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
50
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
52
-
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
54
TYPE_STM32F2XX_SYSCFG, 0x400);
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
56
--
57
2.20.1
58
59
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The MusicPal board code connects both of the IRQ outputs of the UART
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
9
10
This kind of wiring needs an explicitly created OR gate; add one.
11
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/arm/musicpal.c | 17 +++++++++++++----
19
hw/arm/Kconfig | 1 +
20
2 files changed, 14 insertions(+), 4 deletions(-)
21
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/musicpal.c
25
+++ b/hw/arm/musicpal.c
26
@@ -XXX,XX +XXX,XX @@
27
#include "ui/console.h"
28
#include "hw/i2c/i2c.h"
29
#include "hw/irq.h"
30
+#include "hw/or-irq.h"
31
#include "hw/audio/wm8750.h"
32
#include "sysemu/block-backend.h"
33
#include "sysemu/runstate.h"
34
@@ -XXX,XX +XXX,XX @@
35
#define MP_TIMER4_IRQ 7
36
#define MP_EHCI_IRQ 8
37
#define MP_ETH_IRQ 9
38
-#define MP_UART1_IRQ 11
39
-#define MP_UART2_IRQ 11
40
+#define MP_UART_SHARED_IRQ 11
41
#define MP_GPIO_IRQ 12
42
#define MP_RTC_IRQ 28
43
#define MP_AUDIO_IRQ 30
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
45
ARMCPU *cpu;
46
qemu_irq pic[32];
47
DeviceState *dev;
48
+ DeviceState *uart_orgate;
49
DeviceState *i2c_dev;
50
DeviceState *lcd_dev;
51
DeviceState *key_dev;
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
54
pic[MP_TIMER4_IRQ], NULL);
55
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
57
+ /* Logically OR both UART IRQs together */
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
62
+
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
64
+ qdev_get_gpio_in(uart_orgate, 0),
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
68
+ qdev_get_gpio_in(uart_orgate, 1),
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
70
71
/* Register flash */
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/arm/Kconfig
75
+++ b/hw/arm/Kconfig
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
77
78
config MUSICPAL
79
bool
80
+ select OR_IRQ
81
select BITBANG_I2C
82
select MARVELL_88W8618
83
select PTIMER
84
--
85
2.20.1
86
87
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
We don't need to fill the full pic[] array if we only use
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
5
when necessary.
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/musicpal.c | 25 +++++++++++++------------
13
1 file changed, 13 insertions(+), 12 deletions(-)
14
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/musicpal.c
18
+++ b/hw/arm/musicpal.c
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
20
static void musicpal_init(MachineState *machine)
21
{
22
ARMCPU *cpu;
23
- qemu_irq pic[32];
24
DeviceState *dev;
25
+ DeviceState *pic;
26
DeviceState *uart_orgate;
27
DeviceState *i2c_dev;
28
DeviceState *lcd_dev;
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
30
&error_fatal);
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
32
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
36
- for (i = 0; i < 32; i++) {
37
- pic[i] = qdev_get_gpio_in(dev, i);
38
- }
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
41
- pic[MP_TIMER4_IRQ], NULL);
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
47
48
/* Logically OR both UART IRQs together */
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
55
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
57
qdev_get_gpio_in(uart_orgate, 0),
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
59
OBJECT(get_system_memory()), &error_fatal);
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
65
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
67
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
69
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
71
- pic[MP_GPIO_IRQ]);
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
75
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
77
NULL);
78
sysbus_realize_and_unref(s, &error_fatal);
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
82
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
85
--
86
2.20.1
87
88
diff view generated by jsdifflib
Deleted patch
1
The nseries machines have a codepath that allows them to load a
2
secondary bootloader. This code wasn't checking that the
3
load_image_targphys() succeeded. Check the return value and report
4
the error to the user.
5
1
6
While we're in the vicinity, fix the comment style of the
7
comment documenting what this image load is doing.
8
9
Fixes: Coverity CID 1192904
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
13
---
14
hw/arm/nseries.c | 15 +++++++++++----
15
1 file changed, 11 insertions(+), 4 deletions(-)
16
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/nseries.c
20
+++ b/hw/arm/nseries.c
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
22
/* No, wait, better start at the ROM. */
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
24
25
- /* This is intended for loading the `secondary.bin' program from
26
+ /*
27
+ * This is intended for loading the `secondary.bin' program from
28
* Nokia images (the NOLO bootloader). The entry point seems
29
* to be at OMAP2_Q2_BASE + 0x400000.
30
*
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
33
*
34
* The code above is for loading the `zImage' file from Nokia
35
- * images. */
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
37
- machine->ram_size - 0x400000);
38
+ * images.
39
+ */
40
+ if (load_image_targphys(option_rom[0].name,
41
+ OMAP2_Q2_BASE + 0x400000,
42
+ machine->ram_size - 0x400000) < 0) {
43
+ error_report("Failed to load secondary bootloader %s",
44
+ option_rom[0].name);
45
+ exit(EXIT_FAILURE);
46
+ }
47
48
n800_setup_nolo_tags(nolo_tags);
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
50
--
51
2.20.1
52
53
diff view generated by jsdifflib