1 | Patches for rc1: nothing major, just some minor bugfixes and | 1 | Another arm pullreq; nothing particularly exciting here. |
---|---|---|---|
2 | code cleanups. | ||
3 | 2 | ||
4 | -- PMM | 3 | -- PMM |
5 | 4 | ||
6 | The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f: | ||
7 | 5 | ||
8 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000) | 6 | The following changes since commit e27d5b488ef08408691bfed61f34ee2858136287: |
7 | |||
8 | Merge remote-tracking branch 'remotes/juanquintela/tags/pull-migration-pull-request' into staging (2020-02-28 14:02:31 +0000) | ||
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200228 |
13 | 13 | ||
14 | for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa: | 14 | for you to fetch changes up to 1904f9b5f1d94fe12fe021db6b504c87d684f6db: |
15 | 15 | ||
16 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000) | 16 | hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 (2020-02-28 16:14:57 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * hw/arm/Kconfig: ARM_V7M depends on PTIMER | 20 | * hw/arm: Use TYPE_PL011 to create serial port |
21 | * Minor coding style fixes | 21 | * target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn |
22 | * docs: add some notes on the sbsa-ref machine | 22 | * hw/arm/integratorcp: Map the audio codec controller |
23 | * hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals | 23 | * GICv2: Correctly implement the limited number of priority bits |
24 | * target/arm: Fix neon VTBL/VTBX for len > 1 | 24 | * target/arm: refactoring of VFP related feature checks and decode |
25 | * hw/arm/armsse: Correct expansion MPC interrupt lines | 25 | * xilinx_zynq: Fix USB port instantiation |
26 | * hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | 26 | * acceptance tests for n800, n810, integratorcp |
27 | * hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | 27 | * Implement v8.3-RCPC, v8.4-RCPC, v8.3-CCIDX |
28 | * hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | 28 | * arm_gic_kvm: Don't assume kernel can provide a GICv2 |
29 | * hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | 29 | (provide better error message for user error) |
30 | * hw/arm/nseries: Check return value from load_image_targphys() | ||
31 | * tests/qtest/npcm7xx_rng-test: count runs properly | ||
32 | * target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | ||
33 | 30 | ||
34 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
35 | Alex Bennée (1): | 32 | Gavin Shan (1): |
36 | docs: add some notes on the sbsa-ref machine | 33 | hw/arm: Use TYPE_PL011 to create serial port |
37 | 34 | ||
38 | AlexChen (1): | 35 | Guenter Roeck (2): |
39 | ssi: Fix bad printf format specifiers | 36 | hw/arm/xilinx_zynq: Fix USB port instantiation |
37 | hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class | ||
40 | 38 | ||
41 | Andrew Jones (1): | 39 | Peter Maydell (5): |
42 | hw/arm/Kconfig: ARM_V7M depends on PTIMER | 40 | target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 |
41 | target/arm: Implement v8.3-RCPC | ||
42 | target/arm: Implement v8.4-RCPC | ||
43 | target/arm: Implement ARMv8.3-CCIDX | ||
44 | hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 | ||
43 | 45 | ||
44 | Havard Skinnemoen (1): | 46 | Philippe Mathieu-Daudé (3): |
45 | tests/qtest/npcm7xx_rng-test: count runs properly | 47 | hw/arm/integratorcp: Map the audio codec controller |
48 | tests/acceptance: Extract boot_integratorcp() from test_integratorcp() | ||
49 | tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer | ||
46 | 50 | ||
47 | Peter Maydell (2): | 51 | Richard Henderson (17): |
48 | hw/arm/nseries: Check return value from load_image_targphys() | 52 | target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn |
49 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | 53 | target/arm: Add isar_feature_aa32_vfp_simd |
54 | target/arm: Rename isar_feature_aa32_fpdp_v2 | ||
55 | target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} | ||
56 | target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp | ||
57 | target/arm: Perform fpdp_v2 check first | ||
58 | target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 | ||
59 | target/arm: Add missing checks for fpsp_v2 | ||
60 | target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac | ||
61 | target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn | ||
62 | target/arm: Move VLLDM and VLSTM to vfp.decode | ||
63 | target/arm: Move the vfp decodetree calls next to the base isa | ||
64 | linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP | ||
65 | target/arm: Remove ARM_FEATURE_VFP* | ||
66 | target/arm: Add formats for some vfp 2 and 3-register insns | ||
67 | target/arm: Split VFM decode | ||
68 | target/arm: Split VMINMAXNM decode | ||
50 | 69 | ||
51 | Philippe Mathieu-Daudé (6): | 70 | Sai Pavan Boddu (3): |
52 | hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals | 71 | arm_gic: Mask the un-supported priority bits |
53 | hw/arm/armsse: Correct expansion MPC interrupt lines | 72 | cpu/a9mpcore: Set number of GIC priority bits to 5 |
54 | hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | 73 | cpu/arm11mpcore: Set number of GIC priority bits to 4 |
55 | hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | ||
56 | hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | ||
57 | hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
58 | 74 | ||
59 | Richard Henderson (1): | 75 | Thomas Huth (2): |
60 | target/arm: Fix neon VTBL/VTBX for len > 1 | 76 | tests/acceptance: Add a test for the N800 and N810 arm machines |
77 | tests/acceptance: Add a test for the integratorcp arm machine | ||
61 | 78 | ||
62 | Xinhao Zhang (3): | 79 | include/hw/intc/arm_gic.h | 2 + |
63 | target/arm: add spaces around operator | 80 | include/hw/intc/arm_gic_common.h | 1 + |
64 | target/arm: Don't use '#' flag of printf format | 81 | target/arm/cpu.h | 88 +++++- |
65 | target/arm: add space before the open parenthesis '(' | 82 | hw/arm/integratorcp.c | 1 + |
83 | hw/arm/sbsa-ref.c | 3 +- | ||
84 | hw/arm/virt.c | 3 +- | ||
85 | hw/arm/xilinx_zynq.c | 5 +- | ||
86 | hw/arm/xlnx-versal.c | 3 +- | ||
87 | hw/cpu/a9mpcore.c | 4 + | ||
88 | hw/cpu/arm11mpcore.c | 5 + | ||
89 | hw/intc/arm_gic.c | 33 +- | ||
90 | hw/intc/arm_gic_common.c | 1 + | ||
91 | hw/intc/arm_gic_kvm.c | 9 + | ||
92 | hw/intc/armv7m_nvic.c | 20 +- | ||
93 | hw/usb/hcd-ehci-sysbus.c | 17 - | ||
94 | linux-user/arm/signal.c | 4 +- | ||
95 | linux-user/elfload.c | 25 +- | ||
96 | target/arm/arch_dump.c | 11 +- | ||
97 | target/arm/cpu.c | 44 +-- | ||
98 | target/arm/cpu64.c | 5 +- | ||
99 | target/arm/helper.c | 23 +- | ||
100 | target/arm/kvm32.c | 5 - | ||
101 | target/arm/kvm64.c | 1 - | ||
102 | target/arm/m_helper.c | 11 +- | ||
103 | target/arm/machine.c | 5 +- | ||
104 | target/arm/translate-a64.c | 114 +++++++ | ||
105 | target/arm/translate-vfp.inc.c | 448 +++++++++++++++++---------- | ||
106 | target/arm/translate.c | 122 ++------ | ||
107 | MAINTAINERS | 2 + | ||
108 | hw/arm/Kconfig | 1 + | ||
109 | target/arm/vfp-uncond.decode | 12 +- | ||
110 | target/arm/vfp.decode | 153 ++++----- | ||
111 | tests/acceptance/machine_arm_integratorcp.py | 99 ++++++ | ||
112 | tests/acceptance/machine_arm_n8x0.py | 49 +++ | ||
113 | 34 files changed, 865 insertions(+), 464 deletions(-) | ||
114 | create mode 100644 tests/acceptance/machine_arm_integratorcp.py | ||
115 | create mode 100644 tests/acceptance/machine_arm_n8x0.py | ||
66 | 116 | ||
67 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++ | ||
68 | docs/system/target-arm.rst | 1 + | ||
69 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | ||
70 | target/arm/helper.h | 2 +- | ||
71 | hw/arm/armsse.c | 3 +- | ||
72 | hw/arm/musicpal.c | 40 +++++++++++++++++---------- | ||
73 | hw/arm/nseries.c | 26 ++++++++---------- | ||
74 | hw/arm/stm32f205_soc.c | 1 - | ||
75 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
76 | hw/ssi/imx_spi.c | 2 +- | ||
77 | hw/ssi/xilinx_spi.c | 2 +- | ||
78 | target/arm/arch_dump.c | 8 +++--- | ||
79 | target/arm/arm-semi.c | 8 +++--- | ||
80 | target/arm/helper.c | 2 +- | ||
81 | target/arm/op_helper.c | 23 +++++++++------- | ||
82 | target/arm/translate-a64.c | 4 +-- | ||
83 | target/arm/translate.c | 2 +- | ||
84 | tests/qtest/npcm7xx_rng-test.c | 2 +- | ||
85 | hw/arm/Kconfig | 3 +- | ||
86 | target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------ | ||
87 | 20 files changed, 123 insertions(+), 98 deletions(-) | ||
88 | create mode 100644 docs/system/arm/sbsa.rst | ||
89 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Gavin Shan <gshan@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers") | 3 | This uses TYPE_PL011 when creating the serial port so that the code |
4 | changed armv7m_systick to build on ptimers. Make sure we have ptimers | 4 | looks cleaner. |
5 | in the build when building armv7m_systick. | ||
6 | 5 | ||
7 | Signed-off-by: Andrew Jones <drjones@redhat.com> | 6 | Signed-off-by: Gavin Shan <gshan@redhat.com> |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
9 | Message-id: 20201104103343.30392-1-drjones@redhat.com | 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
9 | Message-id: 20200224222223.4128-1-gshan@redhat.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | hw/arm/Kconfig | 1 + | 12 | hw/arm/sbsa-ref.c | 3 ++- |
13 | 1 file changed, 1 insertion(+) | 13 | hw/arm/virt.c | 3 ++- |
14 | hw/arm/xlnx-versal.c | 3 ++- | ||
15 | 3 files changed, 6 insertions(+), 3 deletions(-) | ||
14 | 16 | ||
15 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 17 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c |
16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/Kconfig | 19 | --- a/hw/arm/sbsa-ref.c |
18 | +++ b/hw/arm/Kconfig | 20 | +++ b/hw/arm/sbsa-ref.c |
19 | @@ -XXX,XX +XXX,XX @@ config ZYNQ | 21 | @@ -XXX,XX +XXX,XX @@ |
20 | 22 | #include "hw/pci-host/gpex.h" | |
21 | config ARM_V7M | 23 | #include "hw/qdev-properties.h" |
22 | bool | 24 | #include "hw/usb.h" |
23 | + select PTIMER | 25 | +#include "hw/char/pl011.h" |
24 | 26 | #include "net/net.h" | |
25 | config ALLWINNER_A10 | 27 | |
26 | bool | 28 | #define RAMLIMIT_GB 8192 |
29 | @@ -XXX,XX +XXX,XX @@ static void create_uart(const SBSAMachineState *sms, int uart, | ||
30 | { | ||
31 | hwaddr base = sbsa_ref_memmap[uart].base; | ||
32 | int irq = sbsa_ref_irqmap[uart]; | ||
33 | - DeviceState *dev = qdev_create(NULL, "pl011"); | ||
34 | + DeviceState *dev = qdev_create(NULL, TYPE_PL011); | ||
35 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | ||
36 | |||
37 | qdev_prop_set_chr(dev, "chardev", chr); | ||
38 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/hw/arm/virt.c | ||
41 | +++ b/hw/arm/virt.c | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | #include "hw/mem/nvdimm.h" | ||
44 | #include "hw/acpi/generic_event_device.h" | ||
45 | #include "hw/virtio/virtio-iommu.h" | ||
46 | +#include "hw/char/pl011.h" | ||
47 | |||
48 | #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ | ||
49 | static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ | ||
50 | @@ -XXX,XX +XXX,XX @@ static void create_uart(const VirtMachineState *vms, int uart, | ||
51 | int irq = vms->irqmap[uart]; | ||
52 | const char compat[] = "arm,pl011\0arm,primecell"; | ||
53 | const char clocknames[] = "uartclk\0apb_pclk"; | ||
54 | - DeviceState *dev = qdev_create(NULL, "pl011"); | ||
55 | + DeviceState *dev = qdev_create(NULL, TYPE_PL011); | ||
56 | SysBusDevice *s = SYS_BUS_DEVICE(dev); | ||
57 | |||
58 | qdev_prop_set_chr(dev, "chardev", chr); | ||
59 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
60 | index XXXXXXX..XXXXXXX 100644 | ||
61 | --- a/hw/arm/xlnx-versal.c | ||
62 | +++ b/hw/arm/xlnx-versal.c | ||
63 | @@ -XXX,XX +XXX,XX @@ | ||
64 | #include "hw/misc/unimp.h" | ||
65 | #include "hw/intc/arm_gicv3_common.h" | ||
66 | #include "hw/arm/xlnx-versal.h" | ||
67 | +#include "hw/char/pl011.h" | ||
68 | |||
69 | #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") | ||
70 | #define GEM_REVISION 0x40070106 | ||
71 | @@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic) | ||
72 | DeviceState *dev; | ||
73 | MemoryRegion *mr; | ||
74 | |||
75 | - dev = qdev_create(NULL, "pl011"); | ||
76 | + dev = qdev_create(NULL, TYPE_PL011); | ||
77 | s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev); | ||
78 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); | ||
79 | object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); | ||
27 | -- | 80 | -- |
28 | 2.20.1 | 81 | 2.20.1 |
29 | 82 | ||
30 | 83 | diff view generated by jsdifflib |
1 | From: Havard Skinnemoen <hskinnemoen@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The number of runs is equal to the number of 0-1 and 1-0 transitions, | 3 | We had set this for aarch32-only in arm_max_initfn, but |
4 | plus one. Currently, it's counting the number of times these transitions | 4 | failed to set the same bit for aarch64. |
5 | do _not_ happen, plus one. | ||
6 | 5 | ||
7 | Source: | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf | 7 | Message-id: 20200218190958.745-2-richard.henderson@linaro.org |
9 | section 2.3.4 point (3). | ||
10 | |||
11 | Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
12 | Message-id: 20201103011457.2959989-2-hskinnemoen@google.com | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 10 | --- |
16 | tests/qtest/npcm7xx_rng-test.c | 2 +- | 11 | target/arm/cpu64.c | 1 + |
17 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 1 insertion(+) |
18 | 13 | ||
19 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c | 14 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
20 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/tests/qtest/npcm7xx_rng-test.c | 16 | --- a/target/arm/cpu64.c |
22 | +++ b/tests/qtest/npcm7xx_rng-test.c | 17 | +++ b/target/arm/cpu64.c |
23 | @@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits) | 18 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
24 | pi = (double)nr_ones / nr_bits; | 19 | cpu->isar.id_mmfr3 = u; |
25 | 20 | ||
26 | for (k = 0; k < nr_bits - 1; k++) { | 21 | u = cpu->isar.id_mmfr4; |
27 | - vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf)); | 22 | + u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ |
28 | + vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf)); | 23 | u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ |
29 | } | 24 | cpu->isar.id_mmfr4 = u; |
30 | vn_obs += 1; | ||
31 | 25 | ||
32 | -- | 26 | -- |
33 | 2.20.1 | 27 | 2.20.1 |
34 | 28 | ||
35 | 29 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | The MusicPal board code connects both of the IRQ outputs of the UART | 3 | The Linux kernel displays errors why trying to detect the PL041 |
4 | to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly | 4 | audio interface: |
5 | to the same input is not valid as it produces subtly wrong behaviour | ||
6 | (for instance if both the IRQ lines are high, and then one goes | ||
7 | low, the INTC input will see this as a high-to-low transition | ||
8 | even though the second IRQ line should still be holding it high). | ||
9 | 5 | ||
10 | This kind of wiring needs an explicitly created OR gate; add one. | 6 | Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018 |
7 | CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177 | ||
8 | CPU: VIVT data cache, VIVT instruction cache | ||
9 | OF: fdt: Machine model: ARM Integrator/CP | ||
10 | ... | ||
11 | OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000 | ||
11 | 12 | ||
12 | Inspired-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Since we have it already modelled, simply plug it. |
14 | |||
13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 15 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
14 | Message-id: 20201107193403.436146-5-f4bug@amsat.org | 16 | Message-id: 20200223233033.15371-2-f4bug@amsat.org |
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 19 | --- |
18 | hw/arm/musicpal.c | 17 +++++++++++++---- | 20 | hw/arm/integratorcp.c | 1 + |
19 | hw/arm/Kconfig | 1 + | 21 | hw/arm/Kconfig | 1 + |
20 | 2 files changed, 14 insertions(+), 4 deletions(-) | 22 | 2 files changed, 2 insertions(+) |
21 | 23 | ||
22 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | 24 | diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c |
23 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/hw/arm/musicpal.c | 26 | --- a/hw/arm/integratorcp.c |
25 | +++ b/hw/arm/musicpal.c | 27 | +++ b/hw/arm/integratorcp.c |
26 | @@ -XXX,XX +XXX,XX @@ | 28 | @@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine) |
27 | #include "ui/console.h" | 29 | qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0)); |
28 | #include "hw/i2c/i2c.h" | 30 | qdev_connect_gpio_out(dev, 1, |
29 | #include "hw/irq.h" | 31 | qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0)); |
30 | +#include "hw/or-irq.h" | 32 | + sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL); |
31 | #include "hw/audio/wm8750.h" | 33 | |
32 | #include "sysemu/block-backend.h" | 34 | if (nd_table[0].used) |
33 | #include "sysemu/runstate.h" | 35 | smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); |
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | #define MP_TIMER4_IRQ 7 | ||
36 | #define MP_EHCI_IRQ 8 | ||
37 | #define MP_ETH_IRQ 9 | ||
38 | -#define MP_UART1_IRQ 11 | ||
39 | -#define MP_UART2_IRQ 11 | ||
40 | +#define MP_UART_SHARED_IRQ 11 | ||
41 | #define MP_GPIO_IRQ 12 | ||
42 | #define MP_RTC_IRQ 28 | ||
43 | #define MP_AUDIO_IRQ 30 | ||
44 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
45 | ARMCPU *cpu; | ||
46 | qemu_irq pic[32]; | ||
47 | DeviceState *dev; | ||
48 | + DeviceState *uart_orgate; | ||
49 | DeviceState *i2c_dev; | ||
50 | DeviceState *lcd_dev; | ||
51 | DeviceState *key_dev; | ||
52 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
53 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | ||
54 | pic[MP_TIMER4_IRQ], NULL); | ||
55 | |||
56 | - serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], | ||
57 | + /* Logically OR both UART IRQs together */ | ||
58 | + uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | ||
59 | + object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | ||
60 | + qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | ||
61 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | ||
62 | + | ||
63 | + serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | ||
64 | + qdev_get_gpio_in(uart_orgate, 0), | ||
65 | 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); | ||
66 | - serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], | ||
67 | + serial_mm_init(address_space_mem, MP_UART2_BASE, 2, | ||
68 | + qdev_get_gpio_in(uart_orgate, 1), | ||
69 | 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); | ||
70 | |||
71 | /* Register flash */ | ||
72 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 36 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
73 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
74 | --- a/hw/arm/Kconfig | 38 | --- a/hw/arm/Kconfig |
75 | +++ b/hw/arm/Kconfig | 39 | +++ b/hw/arm/Kconfig |
76 | @@ -XXX,XX +XXX,XX @@ config MUSCA | 40 | @@ -XXX,XX +XXX,XX @@ config INTEGRATOR |
77 | 41 | select INTEGRATOR_DEBUG | |
78 | config MUSICPAL | 42 | select PL011 # UART |
79 | bool | 43 | select PL031 # RTC |
80 | + select OR_IRQ | 44 | + select PL041 # audio |
81 | select BITBANG_I2C | 45 | select PL050 # keyboard/mouse |
82 | select MARVELL_88W8618 | 46 | select PL110 # pl111 LCD controller |
83 | select PTIMER | 47 | select PL181 # display |
84 | -- | 48 | -- |
85 | 2.20.1 | 49 | 2.20.1 |
86 | 50 | ||
87 | 51 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | The system configuration controller (SYSCFG) doesn't have | 3 | The GICv2 allows the implementation to implement a variable number |
4 | any output IRQ (and the INTC input #71 belongs to the UART6). | 4 | of priority bits; unimplemented bits in the priority registers |
5 | Remove the invalid code. | 5 | are read as zeros, writes ignored. We were previously always |
6 | implementing a full 8 bits of priority, which is allowed but not | ||
7 | what the real hardware typically does (which is usually to have | ||
8 | 4 or 5 bits of priority). | ||
6 | 9 | ||
7 | Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC") | 10 | Add a new device property to allow the number of implemented |
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | property bits to be specified. |
9 | Message-id: 20201107193403.436146-3-f4bug@amsat.org | 12 | |
13 | Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | ||
14 | Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com | ||
15 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
17 | [PMM: improved commit message] | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 19 | --- |
13 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | 20 | include/hw/intc/arm_gic.h | 2 ++ |
14 | hw/arm/stm32f205_soc.c | 1 - | 21 | include/hw/intc/arm_gic_common.h | 1 + |
15 | hw/misc/stm32f2xx_syscfg.c | 2 -- | 22 | hw/intc/arm_gic.c | 33 ++++++++++++++++++++++++++++++-- |
16 | 3 files changed, 5 deletions(-) | 23 | hw/intc/arm_gic_common.c | 1 + |
24 | 4 files changed, 35 insertions(+), 2 deletions(-) | ||
17 | 25 | ||
18 | diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h | 26 | diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h |
19 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/misc/stm32f2xx_syscfg.h | 28 | --- a/include/hw/intc/arm_gic.h |
21 | +++ b/include/hw/misc/stm32f2xx_syscfg.h | 29 | +++ b/include/hw/intc/arm_gic.h |
22 | @@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState { | 30 | @@ -XXX,XX +XXX,XX @@ |
23 | uint32_t syscfg_exticr3; | 31 | |
24 | uint32_t syscfg_exticr4; | 32 | /* Number of SGI target-list bits */ |
25 | uint32_t syscfg_cmpcr; | 33 | #define GIC_TARGETLIST_BITS 8 |
26 | - | 34 | +#define GIC_MAX_PRIORITY_BITS 8 |
27 | - qemu_irq irq; | 35 | +#define GIC_MIN_PRIORITY_BITS 4 |
36 | |||
37 | #define TYPE_ARM_GIC "arm_gic" | ||
38 | #define ARM_GIC(obj) \ | ||
39 | diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/include/hw/intc/arm_gic_common.h | ||
42 | +++ b/include/hw/intc/arm_gic_common.h | ||
43 | @@ -XXX,XX +XXX,XX @@ typedef struct GICState { | ||
44 | uint16_t priority_mask[GIC_NCPU_VCPU]; | ||
45 | uint16_t running_priority[GIC_NCPU_VCPU]; | ||
46 | uint16_t current_pending[GIC_NCPU_VCPU]; | ||
47 | + uint32_t n_prio_bits; | ||
48 | |||
49 | /* If we present the GICv2 without security extensions to a guest, | ||
50 | * the guest can configure the GICC_CTLR to configure group 1 binary point | ||
51 | diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/hw/intc/arm_gic.c | ||
54 | +++ b/hw/intc/arm_gic.c | ||
55 | @@ -XXX,XX +XXX,XX @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) | ||
56 | return ret; | ||
57 | } | ||
58 | |||
59 | +static uint32_t gic_fullprio_mask(GICState *s, int cpu) | ||
60 | +{ | ||
61 | + /* | ||
62 | + * Return a mask word which clears the unimplemented priority | ||
63 | + * bits from a priority value for an interrupt. (Not to be | ||
64 | + * confused with the group priority, whose mask depends on BPR.) | ||
65 | + */ | ||
66 | + int priBits; | ||
67 | + | ||
68 | + if (gic_is_vcpu(cpu)) { | ||
69 | + priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS; | ||
70 | + } else { | ||
71 | + priBits = s->n_prio_bits; | ||
72 | + } | ||
73 | + return ~0U << (8 - priBits); | ||
74 | +} | ||
75 | + | ||
76 | void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, | ||
77 | MemTxAttrs attrs) | ||
78 | { | ||
79 | @@ -XXX,XX +XXX,XX @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, | ||
80 | val = 0x80 | (val >> 1); /* Non-secure view */ | ||
81 | } | ||
82 | |||
83 | + val &= gic_fullprio_mask(s, cpu); | ||
84 | + | ||
85 | if (irq < GIC_INTERNAL) { | ||
86 | s->priority1[irq][cpu] = val; | ||
87 | } else { | ||
88 | @@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, | ||
89 | } | ||
90 | prio = (prio << 1) & 0xff; /* Non-secure view */ | ||
91 | } | ||
92 | - return prio; | ||
93 | + return prio & gic_fullprio_mask(s, cpu); | ||
94 | } | ||
95 | |||
96 | static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, | ||
97 | @@ -XXX,XX +XXX,XX @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, | ||
98 | return; | ||
99 | } | ||
100 | } | ||
101 | - s->priority_mask[cpu] = pmask; | ||
102 | + s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu); | ||
103 | } | ||
104 | |||
105 | static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) | ||
106 | @@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp) | ||
107 | return; | ||
108 | } | ||
109 | |||
110 | + if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS || | ||
111 | + (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS : | ||
112 | + s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) { | ||
113 | + error_setg(errp, "num-priority-bits cannot be greater than %d" | ||
114 | + " or less than %d", GIC_MAX_PRIORITY_BITS, | ||
115 | + s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS : | ||
116 | + GIC_MIN_PRIORITY_BITS); | ||
117 | + return; | ||
118 | + } | ||
119 | + | ||
120 | /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if | ||
121 | * enabled, virtualization extensions related interfaces (main virtual | ||
122 | * interface (s->vifaceiomem[0]) and virtual CPU interface). | ||
123 | diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c | ||
124 | index XXXXXXX..XXXXXXX 100644 | ||
125 | --- a/hw/intc/arm_gic_common.c | ||
126 | +++ b/hw/intc/arm_gic_common.c | ||
127 | @@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = { | ||
128 | DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), | ||
129 | /* True if the GIC should implement the virtualization extensions */ | ||
130 | DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0), | ||
131 | + DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8), | ||
132 | DEFINE_PROP_END_OF_LIST(), | ||
28 | }; | 133 | }; |
29 | 134 | ||
30 | #endif /* HW_STM32F2XX_SYSCFG_H */ | ||
31 | diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/arm/stm32f205_soc.c | ||
34 | +++ b/hw/arm/stm32f205_soc.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | ||
36 | } | ||
37 | busdev = SYS_BUS_DEVICE(dev); | ||
38 | sysbus_mmio_map(busdev, 0, 0x40013800); | ||
39 | - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71)); | ||
40 | |||
41 | /* Attach UART (uses USART registers) and USART controllers */ | ||
42 | for (i = 0; i < STM_NUM_USARTS; i++) { | ||
43 | diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/misc/stm32f2xx_syscfg.c | ||
46 | +++ b/hw/misc/stm32f2xx_syscfg.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj) | ||
48 | { | ||
49 | STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj); | ||
50 | |||
51 | - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | ||
52 | - | ||
53 | memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s, | ||
54 | TYPE_STM32F2XX_SYSCFG, 0x400); | ||
55 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | ||
56 | -- | 135 | -- |
57 | 2.20.1 | 136 | 2.20.1 |
58 | 137 | ||
59 | 138 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | When using a Cortex-A15, the Virt machine does not use any | 3 | All A9 CPUs have a GIC with 5 bits of priority. |
4 | MPCore peripherals. Remove the dependency. | ||
5 | 4 | ||
6 | Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig") | 5 | Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> |
7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 7 | Message-id: 1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com |
9 | Message-id: 20201107114852.271922-1-philmd@redhat.com | 8 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | hw/arm/Kconfig | 1 - | 12 | hw/cpu/a9mpcore.c | 4 ++++ |
14 | 1 file changed, 1 deletion(-) | 13 | 1 file changed, 4 insertions(+) |
15 | 14 | ||
16 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 15 | diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/Kconfig | 17 | --- a/hw/cpu/a9mpcore.c |
19 | +++ b/hw/arm/Kconfig | 18 | +++ b/hw/cpu/a9mpcore.c |
20 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT | 19 | @@ -XXX,XX +XXX,XX @@ |
21 | imply VFIO_PLATFORM | 20 | #include "hw/qdev-properties.h" |
22 | imply VFIO_XGMAC | 21 | #include "hw/core/cpu.h" |
23 | imply TPM_TIS_SYSBUS | 22 | |
24 | - select A15MPCORE | 23 | +#define A9_GIC_NUM_PRIORITY_BITS 5 |
25 | select ACPI | 24 | + |
26 | select ARM_SMMUV3 | 25 | static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
27 | select GPIO_KEY | 26 | { |
27 | A9MPPrivState *s = (A9MPPrivState *)opaque; | ||
28 | @@ -XXX,XX +XXX,XX @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) | ||
29 | gicdev = DEVICE(&s->gic); | ||
30 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); | ||
31 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); | ||
32 | + qdev_prop_set_uint32(gicdev, "num-priority-bits", | ||
33 | + A9_GIC_NUM_PRIORITY_BITS); | ||
34 | |||
35 | /* Make the GIC's TZ support match the CPUs. We assume that | ||
36 | * either all the CPUs have TZ, or none do. | ||
28 | -- | 37 | -- |
29 | 2.20.1 | 38 | 2.20.1 |
30 | 39 | ||
31 | 40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | ||
1 | 2 | ||
3 | The GIC built into the ARM11MPCore is always implemented with 4 | ||
4 | priority bits; set the GIC property accordingly. | ||
5 | |||
6 | Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com | ||
9 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | [PMM: tweaked commit message] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/cpu/arm11mpcore.c | 5 +++++ | ||
15 | 1 file changed, 5 insertions(+) | ||
16 | |||
17 | diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/cpu/arm11mpcore.c | ||
20 | +++ b/hw/cpu/arm11mpcore.c | ||
21 | @@ -XXX,XX +XXX,XX @@ | ||
22 | #include "hw/irq.h" | ||
23 | #include "hw/qdev-properties.h" | ||
24 | |||
25 | +#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 | ||
26 | |||
27 | static void mpcore_priv_set_irq(void *opaque, int irq, int level) | ||
28 | { | ||
29 | @@ -XXX,XX +XXX,XX @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp) | ||
30 | |||
31 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); | ||
32 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); | ||
33 | + qdev_prop_set_uint32(gicdev, "num-priority-bits", | ||
34 | + ARM11MPCORE_NUM_GIC_PRIORITY_BITS); | ||
35 | + | ||
36 | + | ||
37 | object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); | ||
38 | if (err != NULL) { | ||
39 | error_propagate(errp, err); | ||
40 | -- | ||
41 | 2.20.1 | ||
42 | |||
43 | diff view generated by jsdifflib |
1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Fix code style. Operator needs spaces both sides. | 3 | Use this in the places that were checking ARM_FEATURE_VFP, and |
4 | 4 | are obviously testing for the existance of the register set | |
5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | 5 | as opposed to testing for some particular instruction extension. |
6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | 6 | |
7 | Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Message-id: 20200224222232.13807-2-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | target/arm/arch_dump.c | 8 ++++---- | 12 | target/arm/cpu.h | 9 +++++++++ |
12 | target/arm/arm-semi.c | 8 ++++---- | 13 | hw/intc/armv7m_nvic.c | 20 ++++++++++---------- |
13 | target/arm/helper.c | 2 +- | 14 | linux-user/arm/signal.c | 4 ++-- |
14 | 3 files changed, 9 insertions(+), 9 deletions(-) | 15 | target/arm/arch_dump.c | 11 ++++++----- |
15 | 16 | target/arm/cpu.c | 4 ++-- | |
17 | target/arm/helper.c | 4 ++-- | ||
18 | target/arm/m_helper.c | 11 ++++++----- | ||
19 | 7 files changed, 37 insertions(+), 26 deletions(-) | ||
20 | |||
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/arm/cpu.h | ||
24 | +++ b/target/arm/cpu.h | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) | ||
26 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; | ||
27 | } | ||
28 | |||
29 | +static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) | ||
30 | +{ | ||
31 | + /* | ||
32 | + * Return true if either VFP or SIMD is implemented. | ||
33 | + * In this case, a minimum of VFP w/ D0-D15. | ||
34 | + */ | ||
35 | + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; | ||
36 | +} | ||
37 | + | ||
38 | static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) | ||
39 | { | ||
40 | /* Return true if D16-D31 are implemented */ | ||
41 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/hw/intc/armv7m_nvic.c | ||
44 | +++ b/hw/intc/armv7m_nvic.c | ||
45 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
46 | case 0xd84: /* CSSELR */ | ||
47 | return cpu->env.v7m.csselr[attrs.secure]; | ||
48 | case 0xd88: /* CPACR */ | ||
49 | - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
50 | + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
51 | return 0; | ||
52 | } | ||
53 | return cpu->env.v7m.cpacr[attrs.secure]; | ||
54 | case 0xd8c: /* NSACR */ | ||
55 | - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
56 | + if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
57 | return 0; | ||
58 | } | ||
59 | return cpu->env.v7m.nsacr; | ||
60 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
61 | } | ||
62 | return cpu->env.v7m.sfar; | ||
63 | case 0xf34: /* FPCCR */ | ||
64 | - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
65 | + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
66 | return 0; | ||
67 | } | ||
68 | if (attrs.secure) { | ||
69 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
70 | return value; | ||
71 | } | ||
72 | case 0xf38: /* FPCAR */ | ||
73 | - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
74 | + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
75 | return 0; | ||
76 | } | ||
77 | return cpu->env.v7m.fpcar[attrs.secure]; | ||
78 | case 0xf3c: /* FPDSCR */ | ||
79 | - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
80 | + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
81 | return 0; | ||
82 | } | ||
83 | return cpu->env.v7m.fpdscr[attrs.secure]; | ||
84 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
85 | } | ||
86 | break; | ||
87 | case 0xd88: /* CPACR */ | ||
88 | - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
89 | + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
90 | /* We implement only the Floating Point extension's CP10/CP11 */ | ||
91 | cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); | ||
92 | } | ||
93 | break; | ||
94 | case 0xd8c: /* NSACR */ | ||
95 | - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
96 | + if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
97 | /* We implement only the Floating Point extension's CP10/CP11 */ | ||
98 | cpu->env.v7m.nsacr = value & (3 << 10); | ||
99 | } | ||
100 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
101 | break; | ||
102 | } | ||
103 | case 0xf34: /* FPCCR */ | ||
104 | - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
105 | + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
106 | /* Not all bits here are banked. */ | ||
107 | uint32_t fpccr_s; | ||
108 | |||
109 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
110 | } | ||
111 | break; | ||
112 | case 0xf38: /* FPCAR */ | ||
113 | - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
114 | + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
115 | value &= ~7; | ||
116 | cpu->env.v7m.fpcar[attrs.secure] = value; | ||
117 | } | ||
118 | break; | ||
119 | case 0xf3c: /* FPDSCR */ | ||
120 | - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
121 | + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
122 | value &= 0x07c00000; | ||
123 | cpu->env.v7m.fpdscr[attrs.secure] = value; | ||
124 | } | ||
125 | diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c | ||
126 | index XXXXXXX..XXXXXXX 100644 | ||
127 | --- a/linux-user/arm/signal.c | ||
128 | +++ b/linux-user/arm/signal.c | ||
129 | @@ -XXX,XX +XXX,XX @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc, | ||
130 | setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); | ||
131 | /* Save coprocessor signal frame. */ | ||
132 | regspace = uc->tuc_regspace; | ||
133 | - if (arm_feature(env, ARM_FEATURE_VFP)) { | ||
134 | + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { | ||
135 | regspace = setup_sigframe_v2_vfp(regspace, env); | ||
136 | } | ||
137 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | ||
138 | @@ -XXX,XX +XXX,XX @@ static int do_sigframe_return_v2(CPUARMState *env, | ||
139 | |||
140 | /* Restore coprocessor signal frame */ | ||
141 | regspace = uc->tuc_regspace; | ||
142 | - if (arm_feature(env, ARM_FEATURE_VFP)) { | ||
143 | + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { | ||
144 | regspace = restore_sigframe_v2_vfp(env, regspace); | ||
145 | if (!regspace) { | ||
146 | return 1; | ||
16 | diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c | 147 | diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c |
17 | index XXXXXXX..XXXXXXX 100644 | 148 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/arch_dump.c | 149 | --- a/target/arm/arch_dump.c |
19 | +++ b/target/arm/arch_dump.c | 150 | +++ b/target/arm/arch_dump.c |
20 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, | 151 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, |
21 | 152 | int cpuid, void *opaque) | |
22 | for (i = 0; i < 32; ++i) { | 153 | { |
23 | uint64_t *q = aa64_vfp_qreg(env, i); | 154 | struct arm_note note; |
24 | - note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]); | 155 | - CPUARMState *env = &ARM_CPU(cs)->env; |
25 | - note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]); | 156 | + ARMCPU *cpu = ARM_CPU(cs); |
26 | + note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]); | 157 | + CPUARMState *env = &cpu->env; |
27 | + note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]); | 158 | DumpState *s = opaque; |
28 | } | 159 | - int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP); |
29 | 160 | + int ret, i; | |
30 | if (s->dump_info.d_endian == ELFDATA2MSB) { | 161 | + bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu); |
31 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, | 162 | |
32 | */ | 163 | arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); |
33 | for (i = 0; i < 32; ++i) { | 164 | |
34 | uint64_t tmp = note.vfp.vregs[2*i]; | 165 | @@ -XXX,XX +XXX,XX @@ int cpu_get_dump_info(ArchDumpInfo *info, |
35 | - note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1]; | 166 | ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) |
36 | - note.vfp.vregs[2*i+1] = tmp; | 167 | { |
37 | + note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1]; | 168 | ARMCPU *cpu = ARM_CPU(first_cpu); |
38 | + note.vfp.vregs[2 * i + 1] = tmp; | 169 | - CPUARMState *env = &cpu->env; |
39 | } | 170 | size_t note_size; |
40 | } | 171 | |
41 | 172 | if (class == ELFCLASS64) { | |
42 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | 173 | @@ -XXX,XX +XXX,XX @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) |
43 | index XXXXXXX..XXXXXXX 100644 | 174 | note_size += AARCH64_PRFPREG_NOTE_SIZE; |
44 | --- a/target/arm/arm-semi.c | 175 | #ifdef TARGET_AARCH64 |
45 | +++ b/target/arm/arm-semi.c | 176 | if (cpu_isar_feature(aa64_sve, cpu)) { |
46 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 177 | - note_size += AARCH64_SVE_NOTE_SIZE(env); |
47 | if (use_gdb_syscalls()) { | 178 | + note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env); |
48 | arm_semi_open_guestfd = guestfd; | 179 | } |
49 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | 180 | #endif |
50 | - (int)arg2+1, gdb_open_modeflags[arg1]); | 181 | } else { |
51 | + (int)arg2 + 1, gdb_open_modeflags[arg1]); | 182 | note_size = ARM_PRSTATUS_NOTE_SIZE; |
52 | } else { | 183 | - if (arm_feature(env, ARM_FEATURE_VFP)) { |
53 | ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); | 184 | + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
54 | if (ret == (uint32_t)-1) { | 185 | note_size += ARM_VFP_NOTE_SIZE; |
55 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 186 | } |
56 | GET_ARG(1); | 187 | } |
57 | if (use_gdb_syscalls()) { | 188 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
58 | ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", | 189 | index XXXXXXX..XXXXXXX 100644 |
59 | - arg0, (int)arg1+1); | 190 | --- a/target/arm/cpu.c |
60 | + arg0, (int)arg1 + 1); | 191 | +++ b/target/arm/cpu.c |
61 | } else { | 192 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) |
62 | s = lock_user_string(arg0); | 193 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; |
63 | if (!s) { | 194 | } |
64 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 195 | |
65 | GET_ARG(3); | 196 | - if (arm_feature(env, ARM_FEATURE_VFP)) { |
66 | if (use_gdb_syscalls()) { | 197 | + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
67 | return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", | 198 | env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; |
68 | - arg0, (int)arg1+1, arg2, (int)arg3+1); | 199 | env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | |
69 | + arg0, (int)arg1 + 1, arg2, (int)arg3 + 1); | 200 | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; |
70 | } else { | 201 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
71 | char *s2; | 202 | int numvfpregs = 0; |
72 | s = lock_user_string(arg0); | 203 | if (cpu_isar_feature(aa32_simd_r32, cpu)) { |
73 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | 204 | numvfpregs = 32; |
74 | GET_ARG(1); | 205 | - } else if (arm_feature(env, ARM_FEATURE_VFP)) { |
75 | if (use_gdb_syscalls()) { | 206 | + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { |
76 | return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", | 207 | numvfpregs = 16; |
77 | - arg0, (int)arg1+1); | 208 | } |
78 | + arg0, (int)arg1 + 1); | 209 | for (i = 0; i < numvfpregs; i++) { |
79 | } else { | ||
80 | s = lock_user_string(arg0); | ||
81 | if (!s) { | ||
82 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 210 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
83 | index XXXXXXX..XXXXXXX 100644 | 211 | index XXXXXXX..XXXXXXX 100644 |
84 | --- a/target/arm/helper.c | 212 | --- a/target/arm/helper.c |
85 | +++ b/target/arm/helper.c | 213 | +++ b/target/arm/helper.c |
86 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | 214 | @@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
87 | uint32_t sum; | 215 | * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. |
88 | sum = do_usad(a, b); | 216 | * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell. |
89 | sum += do_usad(a >> 8, b >> 8); | 217 | */ |
90 | - sum += do_usad(a >> 16, b >>16); | 218 | - if (arm_feature(env, ARM_FEATURE_VFP)) { |
91 | + sum += do_usad(a >> 16, b >> 16); | 219 | + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { |
92 | sum += do_usad(a >> 24, b >> 24); | 220 | /* VFP coprocessor: cp10 & cp11 [23:20] */ |
93 | return sum; | 221 | mask |= (1 << 31) | (1 << 30) | (0xf << 20); |
94 | } | 222 | |
223 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
224 | } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { | ||
225 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | ||
226 | 35, "arm-vfp3.xml", 0); | ||
227 | - } else if (arm_feature(env, ARM_FEATURE_VFP)) { | ||
228 | + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
229 | gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, | ||
230 | 19, "arm-vfp.xml", 0); | ||
231 | } | ||
232 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
233 | index XXXXXXX..XXXXXXX 100644 | ||
234 | --- a/target/arm/m_helper.c | ||
235 | +++ b/target/arm/m_helper.c | ||
236 | @@ -XXX,XX +XXX,XX @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr) | ||
237 | */ | ||
238 | uint32_t sig = 0xfefa125a; | ||
239 | |||
240 | - if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) { | ||
241 | + if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) | ||
242 | + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { | ||
243 | sig |= 1; | ||
244 | } | ||
245 | return sig; | ||
246 | @@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, | ||
247 | |||
248 | if (dotailchain) { | ||
249 | /* Sanitize LR FType and PREFIX bits */ | ||
250 | - if (!arm_feature(env, ARM_FEATURE_VFP)) { | ||
251 | + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
252 | lr |= R_V7M_EXCRET_FTYPE_MASK; | ||
253 | } | ||
254 | lr = deposit32(lr, 24, 8, 0xff); | ||
255 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
256 | |||
257 | ftype = excret & R_V7M_EXCRET_FTYPE_MASK; | ||
258 | |||
259 | - if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { | ||
260 | + if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) { | ||
261 | qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception " | ||
262 | "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " | ||
263 | "if FPU not present\n", | ||
264 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
265 | * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0, | ||
266 | * RES0 if the FPU is not present, and is stored in the S bank | ||
267 | */ | ||
268 | - if (arm_feature(env, ARM_FEATURE_VFP) && | ||
269 | + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) && | ||
270 | extract32(env->v7m.nsacr, 10, 1)) { | ||
271 | env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; | ||
272 | env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; | ||
273 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | ||
274 | env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; | ||
275 | env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; | ||
276 | } | ||
277 | - if (arm_feature(env, ARM_FEATURE_VFP)) { | ||
278 | + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { | ||
279 | /* | ||
280 | * SFPA is RAZ/WI from NS or if no FPU. | ||
281 | * FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present. | ||
95 | -- | 282 | -- |
96 | 2.20.1 | 283 | 2.20.1 |
97 | 284 | ||
98 | 285 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | The old name, isar_feature_aa32_fpdp, does not reflect | ||
4 | that the test includes VFPv2. We will introduce another | ||
5 | feature tests for VFPv3. | ||
6 | |||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200224222232.13807-3-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/cpu.h | 4 ++-- | ||
13 | target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- | ||
14 | 2 files changed, 22 insertions(+), 22 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/cpu.h | ||
19 | +++ b/target/arm/cpu.h | ||
20 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) | ||
21 | return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; | ||
22 | } | ||
23 | |||
24 | -static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) | ||
25 | +static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) | ||
26 | { | ||
27 | - /* Return true if CPU supports double precision floating point */ | ||
28 | + /* Return true if CPU supports double precision floating point, VFPv2 */ | ||
29 | return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; | ||
30 | } | ||
31 | |||
32 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/translate-vfp.inc.c | ||
35 | +++ b/target/arm/translate-vfp.inc.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
37 | return false; | ||
38 | } | ||
39 | |||
40 | - if (dp && !dc_isar_feature(aa32_fpdp, s)) { | ||
41 | + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
42 | return false; | ||
43 | } | ||
44 | |||
45 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) | ||
46 | return false; | ||
47 | } | ||
48 | |||
49 | - if (dp && !dc_isar_feature(aa32_fpdp, s)) { | ||
50 | + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
51 | return false; | ||
52 | } | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
55 | return false; | ||
56 | } | ||
57 | |||
58 | - if (dp && !dc_isar_feature(aa32_fpdp, s)) { | ||
59 | + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
60 | return false; | ||
61 | } | ||
62 | |||
63 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
64 | return false; | ||
65 | } | ||
66 | |||
67 | - if (dp && !dc_isar_feature(aa32_fpdp, s)) { | ||
68 | + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
69 | return false; | ||
70 | } | ||
71 | |||
72 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
73 | return false; | ||
74 | } | ||
75 | |||
76 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
77 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
78 | return false; | ||
79 | } | ||
80 | |||
81 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
82 | return false; | ||
83 | } | ||
84 | |||
85 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
86 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
87 | return false; | ||
88 | } | ||
89 | |||
90 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) | ||
91 | return false; | ||
92 | } | ||
93 | |||
94 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
95 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
96 | return false; | ||
97 | } | ||
98 | |||
99 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
100 | return false; | ||
101 | } | ||
102 | |||
103 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
104 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
105 | return false; | ||
106 | } | ||
107 | |||
108 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) | ||
109 | return false; | ||
110 | } | ||
111 | |||
112 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
113 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
114 | return false; | ||
115 | } | ||
116 | |||
117 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) | ||
118 | return false; | ||
119 | } | ||
120 | |||
121 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
122 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
123 | return false; | ||
124 | } | ||
125 | |||
126 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) | ||
127 | return false; | ||
128 | } | ||
129 | |||
130 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
131 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
132 | return false; | ||
133 | } | ||
134 | |||
135 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) | ||
136 | return false; | ||
137 | } | ||
138 | |||
139 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
140 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
141 | return false; | ||
142 | } | ||
143 | |||
144 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) | ||
145 | return false; | ||
146 | } | ||
147 | |||
148 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
149 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
150 | return false; | ||
151 | } | ||
152 | |||
153 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) | ||
154 | return false; | ||
155 | } | ||
156 | |||
157 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
158 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
159 | return false; | ||
160 | } | ||
161 | |||
162 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
163 | return false; | ||
164 | } | ||
165 | |||
166 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
167 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
168 | return false; | ||
169 | } | ||
170 | |||
171 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
172 | return false; | ||
173 | } | ||
174 | |||
175 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
176 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
177 | return false; | ||
178 | } | ||
179 | |||
180 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
181 | return false; | ||
182 | } | ||
183 | |||
184 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
185 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
186 | return false; | ||
187 | } | ||
188 | |||
189 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
190 | return false; | ||
191 | } | ||
192 | |||
193 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
194 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
195 | return false; | ||
196 | } | ||
197 | |||
198 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
199 | return false; | ||
200 | } | ||
201 | |||
202 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
203 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
204 | return false; | ||
205 | } | ||
206 | |||
207 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
208 | return false; | ||
209 | } | ||
210 | |||
211 | - if (!dc_isar_feature(aa32_fpdp, s)) { | ||
212 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
213 | return false; | ||
214 | } | ||
215 | |||
216 | -- | ||
217 | 2.20.1 | ||
218 | |||
219 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | We will shortly use these to test for VFPv2 and VFPv3 | ||
4 | in different situations. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200224222232.13807-4-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 18 ++++++++++++++++++ | ||
12 | 1 file changed, 18 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) | ||
19 | return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; | ||
20 | } | ||
21 | |||
22 | +static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) | ||
23 | +{ | ||
24 | + /* Return true if CPU supports single precision floating point, VFPv2 */ | ||
25 | + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; | ||
26 | +} | ||
27 | + | ||
28 | +static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) | ||
29 | +{ | ||
30 | + /* Return true if CPU supports single precision floating point, VFPv3 */ | ||
31 | + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2; | ||
32 | +} | ||
33 | + | ||
34 | static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) | ||
35 | { | ||
36 | /* Return true if CPU supports double precision floating point, VFPv2 */ | ||
37 | return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; | ||
38 | } | ||
39 | |||
40 | +static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) | ||
41 | +{ | ||
42 | + /* Return true if CPU supports double precision floating point, VFPv3 */ | ||
43 | + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; | ||
44 | +} | ||
45 | + | ||
46 | /* | ||
47 | * We always set the FP and SIMD FP16 fields to indicate identical | ||
48 | * levels of support (assuming SIMD is implemented at all), so | ||
49 | -- | ||
50 | 2.20.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | We cannot easily create "any" functions for these, because the | ||
4 | ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero. | ||
5 | Which means that an aarch32-only cpu will return incorrect results | ||
6 | when testing the aarch64 registers. | ||
7 | |||
8 | To use these, we must either have context or additionally test | ||
9 | vs ARM_FEATURE_AARCH64. | ||
10 | |||
11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Message-id: 20200224222232.13807-5-richard.henderson@linaro.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | target/arm/cpu.h | 11 +++++++++++ | ||
17 | target/arm/cpu.c | 9 ++++++--- | ||
18 | target/arm/machine.c | 5 +++-- | ||
19 | 3 files changed, 20 insertions(+), 5 deletions(-) | ||
20 | |||
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/arm/cpu.h | ||
24 | +++ b/target/arm/cpu.h | ||
25 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) | ||
26 | return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2; | ||
27 | } | ||
28 | |||
29 | +static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) | ||
30 | +{ | ||
31 | + return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); | ||
32 | +} | ||
33 | + | ||
34 | /* | ||
35 | * We always set the FP and SIMD FP16 fields to indicate identical | ||
36 | * levels of support (assuming SIMD is implemented at all), so | ||
37 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id) | ||
38 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2; | ||
39 | } | ||
40 | |||
41 | +static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) | ||
42 | +{ | ||
43 | + /* We always set the AdvSIMD and FP fields identically. */ | ||
44 | + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf; | ||
45 | +} | ||
46 | + | ||
47 | static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) | ||
48 | { | ||
49 | /* We always set the AdvSIMD and FP fields identically wrt FP16. */ | ||
50 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/target/arm/cpu.c | ||
53 | +++ b/target/arm/cpu.c | ||
54 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj) | ||
55 | * KVM does not currently allow us to lie to the guest about its | ||
56 | * ID/feature registers, so the guest always sees what the host has. | ||
57 | */ | ||
58 | - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
59 | + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) | ||
60 | + ? cpu_isar_feature(aa64_fp_simd, cpu) | ||
61 | + : cpu_isar_feature(aa32_vfp, cpu)) { | ||
62 | cpu->has_vfp = true; | ||
63 | if (!kvm_enabled()) { | ||
64 | qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); | ||
65 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
66 | * We rely on no XScale CPU having VFP so we can use the same bits in the | ||
67 | * TB flags field for VECSTRIDE and XSCALE_CPAR. | ||
68 | */ | ||
69 | - assert(!(arm_feature(env, ARM_FEATURE_VFP) && | ||
70 | - arm_feature(env, ARM_FEATURE_XSCALE))); | ||
71 | + assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || | ||
72 | + !cpu_isar_feature(aa32_vfp_simd, cpu) || | ||
73 | + !arm_feature(env, ARM_FEATURE_XSCALE)); | ||
74 | |||
75 | if (arm_feature(env, ARM_FEATURE_V7) && | ||
76 | !arm_feature(env, ARM_FEATURE_M) && | ||
77 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/target/arm/machine.c | ||
80 | +++ b/target/arm/machine.c | ||
81 | @@ -XXX,XX +XXX,XX @@ | ||
82 | static bool vfp_needed(void *opaque) | ||
83 | { | ||
84 | ARMCPU *cpu = opaque; | ||
85 | - CPUARMState *env = &cpu->env; | ||
86 | |||
87 | - return arm_feature(env, ARM_FEATURE_VFP); | ||
88 | + return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) | ||
89 | + ? cpu_isar_feature(aa64_fp_simd, cpu) | ||
90 | + : cpu_isar_feature(aa32_vfp_simd, cpu)); | ||
91 | } | ||
92 | |||
93 | static int get_fpscr(QEMUFile *f, void *opaque, size_t size, | ||
94 | -- | ||
95 | 2.20.1 | ||
96 | |||
97 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | Shuffle the order of the checks so that we test the ISA | ||
4 | before we test anything else, such as the register arguments. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200224222232.13807-7-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate-vfp.inc.c | 140 +++++++++++++++++---------------- | ||
12 | 1 file changed, 71 insertions(+), 69 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate-vfp.inc.c | ||
17 | +++ b/target/arm/translate-vfp.inc.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
19 | return false; | ||
20 | } | ||
21 | |||
22 | - /* UNDEF accesses to D16-D31 if they don't exist */ | ||
23 | - if (dp && !dc_isar_feature(aa32_simd_r32, s) && | ||
24 | - ((a->vm | a->vn | a->vd) & 0x10)) { | ||
25 | + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
26 | return false; | ||
27 | } | ||
28 | |||
29 | - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
30 | + /* UNDEF accesses to D16-D31 if they don't exist */ | ||
31 | + if (dp && !dc_isar_feature(aa32_simd_r32, s) && | ||
32 | + ((a->vm | a->vn | a->vd) & 0x10)) { | ||
33 | return false; | ||
34 | } | ||
35 | |||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) | ||
37 | return false; | ||
38 | } | ||
39 | |||
40 | - /* UNDEF accesses to D16-D31 if they don't exist */ | ||
41 | - if (dp && !dc_isar_feature(aa32_simd_r32, s) && | ||
42 | - ((a->vm | a->vn | a->vd) & 0x10)) { | ||
43 | + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
44 | return false; | ||
45 | } | ||
46 | |||
47 | - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
48 | + /* UNDEF accesses to D16-D31 if they don't exist */ | ||
49 | + if (dp && !dc_isar_feature(aa32_simd_r32, s) && | ||
50 | + ((a->vm | a->vn | a->vd) & 0x10)) { | ||
51 | return false; | ||
52 | } | ||
53 | |||
54 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
55 | return false; | ||
56 | } | ||
57 | |||
58 | - /* UNDEF accesses to D16-D31 if they don't exist */ | ||
59 | - if (dp && !dc_isar_feature(aa32_simd_r32, s) && | ||
60 | - ((a->vm | a->vd) & 0x10)) { | ||
61 | + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
62 | return false; | ||
63 | } | ||
64 | |||
65 | - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
66 | + /* UNDEF accesses to D16-D31 if they don't exist */ | ||
67 | + if (dp && !dc_isar_feature(aa32_simd_r32, s) && | ||
68 | + ((a->vm | a->vd) & 0x10)) { | ||
69 | return false; | ||
70 | } | ||
71 | |||
72 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
73 | return false; | ||
74 | } | ||
75 | |||
76 | - /* UNDEF accesses to D16-D31 if they don't exist */ | ||
77 | - if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | ||
78 | + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
79 | return false; | ||
80 | } | ||
81 | |||
82 | - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
83 | + /* UNDEF accesses to D16-D31 if they don't exist */ | ||
84 | + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | ||
85 | return false; | ||
86 | } | ||
87 | |||
88 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
89 | TCGv_i64 f0, f1, fd; | ||
90 | TCGv_ptr fpst; | ||
91 | |||
92 | - /* UNDEF accesses to D16-D31 if they don't exist */ | ||
93 | - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { | ||
94 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
95 | return false; | ||
96 | } | ||
97 | |||
98 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
99 | + /* UNDEF accesses to D16-D31 if they don't exist */ | ||
100 | + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { | ||
101 | return false; | ||
102 | } | ||
103 | |||
104 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
105 | int veclen = s->vec_len; | ||
106 | TCGv_i64 f0, fd; | ||
107 | |||
108 | - /* UNDEF accesses to D16-D31 if they don't exist */ | ||
109 | - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { | ||
110 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
111 | return false; | ||
112 | } | ||
113 | |||
114 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
115 | + /* UNDEF accesses to D16-D31 if they don't exist */ | ||
116 | + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { | ||
117 | return false; | ||
118 | } | ||
119 | |||
120 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) | ||
121 | return false; | ||
122 | } | ||
123 | |||
124 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
125 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
126 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
127 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
128 | return false; | ||
129 | } | ||
130 | |||
131 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
132 | |||
133 | vd = a->vd; | ||
134 | |||
135 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
136 | - if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { | ||
137 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
138 | return false; | ||
139 | } | ||
140 | |||
141 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
142 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
143 | + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { | ||
144 | return false; | ||
145 | } | ||
146 | |||
147 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) | ||
148 | { | ||
149 | TCGv_i64 vd, vm; | ||
150 | |||
151 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
152 | + return false; | ||
153 | + } | ||
154 | + | ||
155 | /* Vm/M bits must be zero for the Z variant */ | ||
156 | if (a->z && a->vm != 0) { | ||
157 | return false; | ||
158 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) | ||
159 | return false; | ||
160 | } | ||
161 | |||
162 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
163 | - return false; | ||
164 | - } | ||
165 | - | ||
166 | if (!vfp_access_check(s)) { | ||
167 | return true; | ||
168 | } | ||
169 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) | ||
170 | TCGv_i32 tmp; | ||
171 | TCGv_i64 vd; | ||
172 | |||
173 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
174 | + return false; | ||
175 | + } | ||
176 | + | ||
177 | if (!dc_isar_feature(aa32_fp16_dpconv, s)) { | ||
178 | return false; | ||
179 | } | ||
180 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) | ||
181 | return false; | ||
182 | } | ||
183 | |||
184 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
185 | - return false; | ||
186 | - } | ||
187 | - | ||
188 | if (!vfp_access_check(s)) { | ||
189 | return true; | ||
190 | } | ||
191 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) | ||
192 | TCGv_i32 tmp; | ||
193 | TCGv_i64 vm; | ||
194 | |||
195 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
196 | + return false; | ||
197 | + } | ||
198 | + | ||
199 | if (!dc_isar_feature(aa32_fp16_dpconv, s)) { | ||
200 | return false; | ||
201 | } | ||
202 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) | ||
203 | return false; | ||
204 | } | ||
205 | |||
206 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
207 | - return false; | ||
208 | - } | ||
209 | - | ||
210 | if (!vfp_access_check(s)) { | ||
211 | return true; | ||
212 | } | ||
213 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) | ||
214 | TCGv_ptr fpst; | ||
215 | TCGv_i64 tmp; | ||
216 | |||
217 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
218 | + return false; | ||
219 | + } | ||
220 | + | ||
221 | if (!dc_isar_feature(aa32_vrint, s)) { | ||
222 | return false; | ||
223 | } | ||
224 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) | ||
225 | return false; | ||
226 | } | ||
227 | |||
228 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
229 | - return false; | ||
230 | - } | ||
231 | - | ||
232 | if (!vfp_access_check(s)) { | ||
233 | return true; | ||
234 | } | ||
235 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) | ||
236 | TCGv_i64 tmp; | ||
237 | TCGv_i32 tcg_rmode; | ||
238 | |||
239 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
240 | + return false; | ||
241 | + } | ||
242 | + | ||
243 | if (!dc_isar_feature(aa32_vrint, s)) { | ||
244 | return false; | ||
245 | } | ||
246 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) | ||
247 | return false; | ||
248 | } | ||
249 | |||
250 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
251 | - return false; | ||
252 | - } | ||
253 | - | ||
254 | if (!vfp_access_check(s)) { | ||
255 | return true; | ||
256 | } | ||
257 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) | ||
258 | TCGv_ptr fpst; | ||
259 | TCGv_i64 tmp; | ||
260 | |||
261 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
262 | + return false; | ||
263 | + } | ||
264 | + | ||
265 | if (!dc_isar_feature(aa32_vrint, s)) { | ||
266 | return false; | ||
267 | } | ||
268 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) | ||
269 | return false; | ||
270 | } | ||
271 | |||
272 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
273 | - return false; | ||
274 | - } | ||
275 | - | ||
276 | if (!vfp_access_check(s)) { | ||
277 | return true; | ||
278 | } | ||
279 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
280 | TCGv_i64 vd; | ||
281 | TCGv_i32 vm; | ||
282 | |||
283 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
284 | - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | ||
285 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
286 | return false; | ||
287 | } | ||
288 | |||
289 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
290 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
291 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | ||
292 | return false; | ||
293 | } | ||
294 | |||
295 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
296 | TCGv_i64 vm; | ||
297 | TCGv_i32 vd; | ||
298 | |||
299 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
300 | - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | ||
301 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
302 | return false; | ||
303 | } | ||
304 | |||
305 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
306 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
307 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | ||
308 | return false; | ||
309 | } | ||
310 | |||
311 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
312 | TCGv_i64 vd; | ||
313 | TCGv_ptr fpst; | ||
314 | |||
315 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
316 | - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | ||
317 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
318 | return false; | ||
319 | } | ||
320 | |||
321 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
322 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
323 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | ||
324 | return false; | ||
325 | } | ||
326 | |||
327 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
328 | TCGv_i32 vd; | ||
329 | TCGv_i64 vm; | ||
330 | |||
331 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
332 | + return false; | ||
333 | + } | ||
334 | + | ||
335 | if (!dc_isar_feature(aa32_jscvt, s)) { | ||
336 | return false; | ||
337 | } | ||
338 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
339 | return false; | ||
340 | } | ||
341 | |||
342 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
343 | - return false; | ||
344 | - } | ||
345 | - | ||
346 | if (!vfp_access_check(s)) { | ||
347 | return true; | ||
348 | } | ||
349 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
350 | TCGv_ptr fpst; | ||
351 | int frac_bits; | ||
352 | |||
353 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
354 | + return false; | ||
355 | + } | ||
356 | + | ||
357 | if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { | ||
358 | return false; | ||
359 | } | ||
360 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
361 | return false; | ||
362 | } | ||
363 | |||
364 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
365 | - return false; | ||
366 | - } | ||
367 | - | ||
368 | if (!vfp_access_check(s)) { | ||
369 | return true; | ||
370 | } | ||
371 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
372 | TCGv_i64 vm; | ||
373 | TCGv_ptr fpst; | ||
374 | |||
375 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
376 | - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | ||
377 | + if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
378 | return false; | ||
379 | } | ||
380 | |||
381 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
382 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
383 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | ||
384 | return false; | ||
385 | } | ||
386 | |||
387 | -- | ||
388 | 2.20.1 | ||
389 | |||
390 | diff view generated by jsdifflib |
1 | Checks for UNDEF cases should go before the "is VFP enabled?" access | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | check, except in special cases. Move a stray UNDEF check in the VTBL | ||
3 | trans function up above the access check. | ||
4 | 2 | ||
3 | Sort this check to the start of a trans_* function. | ||
4 | Merge this with any existing test for fpdp_v2. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200224222232.13807-8-richard.henderson@linaro.org | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201109145324.2859-1-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | target/arm/translate-neon.c.inc | 8 ++++---- | 11 | target/arm/translate-vfp.inc.c | 24 ++++++++---------------- |
10 | 1 file changed, 4 insertions(+), 4 deletions(-) | 12 | 1 file changed, 8 insertions(+), 16 deletions(-) |
11 | 13 | ||
12 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | 14 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/translate-neon.c.inc | 16 | --- a/target/arm/translate-vfp.inc.c |
15 | +++ b/target/arm/translate-neon.c.inc | 17 | +++ b/target/arm/translate-vfp.inc.c |
16 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | 18 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) |
19 | * VFPv2 allows access to FPSID from userspace; VFPv3 restricts | ||
20 | * all ID registers to privileged access only. | ||
21 | */ | ||
22 | - if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) { | ||
23 | + if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) { | ||
24 | return false; | ||
25 | } | ||
26 | ignore_vfp_enabled = true; | ||
27 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
28 | case ARM_VFP_FPINST: | ||
29 | case ARM_VFP_FPINST2: | ||
30 | /* Not present in VFPv3 */ | ||
31 | - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) { | ||
32 | + if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) { | ||
33 | return false; | ||
34 | } | ||
35 | break; | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
37 | |||
38 | vd = a->vd; | ||
39 | |||
40 | - if (!dc_isar_feature(aa32_fpshvec, s) && | ||
41 | - (veclen != 0 || s->vec_stride != 0)) { | ||
42 | + if (!dc_isar_feature(aa32_fpsp_v3, s)) { | ||
17 | return false; | 43 | return false; |
18 | } | 44 | } |
19 | 45 | ||
20 | - if (!vfp_access_check(s)) { | 46 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { |
21 | - return true; | 47 | + if (!dc_isar_feature(aa32_fpshvec, s) && |
48 | + (veclen != 0 || s->vec_stride != 0)) { | ||
49 | return false; | ||
50 | } | ||
51 | |||
52 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
53 | |||
54 | vd = a->vd; | ||
55 | |||
56 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { | ||
57 | + if (!dc_isar_feature(aa32_fpdp_v3, s)) { | ||
58 | return false; | ||
59 | } | ||
60 | |||
61 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
62 | return false; | ||
63 | } | ||
64 | |||
65 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { | ||
66 | - return false; | ||
22 | - } | 67 | - } |
23 | - | 68 | - |
24 | if ((a->vn + a->len + 1) > 32) { | 69 | if (!vfp_access_check(s)) { |
25 | /* | 70 | return true; |
26 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | 71 | } |
27 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | 72 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) |
73 | TCGv_ptr fpst; | ||
74 | int frac_bits; | ||
75 | |||
76 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { | ||
77 | + if (!dc_isar_feature(aa32_fpsp_v3, s)) { | ||
28 | return false; | 78 | return false; |
29 | } | 79 | } |
30 | 80 | ||
31 | + if (!vfp_access_check(s)) { | 81 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) |
32 | + return true; | 82 | TCGv_ptr fpst; |
33 | + } | 83 | int frac_bits; |
34 | + | 84 | |
35 | desc = tcg_const_i32((a->vn << 2) | a->len); | 85 | - if (!dc_isar_feature(aa32_fpdp_v2, s)) { |
36 | def = tcg_temp_new_i64(); | 86 | - return false; |
37 | if (a->op) { | 87 | - } |
88 | - | ||
89 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { | ||
90 | + if (!dc_isar_feature(aa32_fpdp_v3, s)) { | ||
91 | return false; | ||
92 | } | ||
93 | |||
38 | -- | 94 | -- |
39 | 2.20.1 | 95 | 2.20.1 |
40 | 96 | ||
41 | 97 | diff view generated by jsdifflib |
1 | From: AlexChen <alex.chen@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We should use printf format specifier "%u" instead of "%d" for | 3 | We will eventually remove the early ARM_FEATURE_VFP test, |
4 | argument of type "unsigned int". | 4 | so add a proper test for each trans_* that does not already |
5 | 5 | have another ISA test. | |
6 | Reported-by: Euler Robot <euler.robot@huawei.com> | 6 | |
7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 5FA280F5.8060902@huawei.com | 9 | Message-id: 20200224222232.13807-9-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | hw/ssi/imx_spi.c | 2 +- | 12 | target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++---- |
13 | hw/ssi/xilinx_spi.c | 2 +- | 13 | 1 file changed, 69 insertions(+), 9 deletions(-) |
14 | 2 files changed, 2 insertions(+), 2 deletions(-) | 14 | |
15 | 15 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c | |
16 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/ssi/imx_spi.c | 17 | --- a/target/arm/translate-vfp.inc.c |
19 | +++ b/hw/ssi/imx_spi.c | 18 | +++ b/target/arm/translate-vfp.inc.c |
20 | @@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg) | 19 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) |
21 | case ECSPI_MSGDATA: | 20 | int pass; |
22 | return "ECSPI_MSGDATA"; | 21 | uint32_t offset; |
23 | default: | 22 | |
24 | - sprintf(unknown, "%d ?", reg); | 23 | + /* SIZE == 2 is a VFP instruction; otherwise NEON. */ |
25 | + sprintf(unknown, "%u ?", reg); | 24 | + if (a->size == 2 |
26 | return unknown; | 25 | + ? !dc_isar_feature(aa32_fpsp_v2, s) |
27 | } | 26 | + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { |
28 | } | 27 | + return false; |
29 | diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c | 28 | + } |
30 | index XXXXXXX..XXXXXXX 100644 | 29 | + |
31 | --- a/hw/ssi/xilinx_spi.c | 30 | /* UNDEF accesses to D16-D31 if they don't exist */ |
32 | +++ b/hw/ssi/xilinx_spi.c | 31 | if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { |
33 | @@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s) | 32 | return false; |
34 | irq chain unless things really changed. */ | 33 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) |
35 | if (pending != s->irqline) { | 34 | pass = extract32(offset, 2, 1); |
36 | s->irqline = pending; | 35 | offset = extract32(offset, 0, 2) * 8; |
37 | - DB_PRINT("irq_change of state %d ISR:%x IER:%X\n", | 36 | |
38 | + DB_PRINT("irq_change of state %u ISR:%x IER:%X\n", | 37 | - if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { |
39 | pending, s->regs[R_IPISR], s->regs[R_IPIER]); | 38 | - return false; |
40 | qemu_set_irq(s->irq, pending); | 39 | - } |
40 | - | ||
41 | if (!vfp_access_check(s)) { | ||
42 | return true; | ||
43 | } | ||
44 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
45 | int pass; | ||
46 | uint32_t offset; | ||
47 | |||
48 | + /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | ||
49 | + if (a->size == 2 | ||
50 | + ? !dc_isar_feature(aa32_fpsp_v2, s) | ||
51 | + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
52 | + return false; | ||
53 | + } | ||
54 | + | ||
55 | /* UNDEF accesses to D16-D31 if they don't exist */ | ||
56 | if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { | ||
57 | return false; | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
59 | pass = extract32(offset, 2, 1); | ||
60 | offset = extract32(offset, 0, 2) * 8; | ||
61 | |||
62 | - if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
63 | - return false; | ||
64 | - } | ||
65 | - | ||
66 | if (!vfp_access_check(s)) { | ||
67 | return true; | ||
68 | } | ||
69 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
70 | TCGv_i32 tmp; | ||
71 | bool ignore_vfp_enabled = false; | ||
72 | |||
73 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
74 | + return false; | ||
75 | + } | ||
76 | + | ||
77 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
78 | /* | ||
79 | * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. | ||
80 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) | ||
81 | { | ||
82 | TCGv_i32 tmp; | ||
83 | |||
84 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
85 | + return false; | ||
86 | + } | ||
87 | + | ||
88 | if (!vfp_access_check(s)) { | ||
89 | return true; | ||
90 | } | ||
91 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) | ||
92 | { | ||
93 | TCGv_i32 tmp; | ||
94 | |||
95 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
96 | + return false; | ||
97 | + } | ||
98 | + | ||
99 | /* | ||
100 | * VMOV between two general-purpose registers and two single precision | ||
101 | * floating point registers | ||
102 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) | ||
103 | |||
104 | /* | ||
105 | * VMOV between two general-purpose registers and one double precision | ||
106 | - * floating point register | ||
107 | + * floating point register. Note that this does not require support | ||
108 | + * for double precision arithmetic. | ||
109 | */ | ||
110 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
111 | + return false; | ||
112 | + } | ||
113 | |||
114 | /* UNDEF accesses to D16-D31 if they don't exist */ | ||
115 | if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | ||
116 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
117 | uint32_t offset; | ||
118 | TCGv_i32 addr, tmp; | ||
119 | |||
120 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
121 | + return false; | ||
122 | + } | ||
123 | + | ||
124 | if (!vfp_access_check(s)) { | ||
125 | return true; | ||
126 | } | ||
127 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) | ||
128 | TCGv_i32 addr; | ||
129 | TCGv_i64 tmp; | ||
130 | |||
131 | + /* Note that this does not require support for double arithmetic. */ | ||
132 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
133 | + return false; | ||
134 | + } | ||
135 | + | ||
136 | /* UNDEF accesses to D16-D31 if they don't exist */ | ||
137 | if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | ||
138 | return false; | ||
139 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) | ||
140 | TCGv_i32 addr, tmp; | ||
141 | int i, n; | ||
142 | |||
143 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
144 | + return false; | ||
145 | + } | ||
146 | + | ||
147 | n = a->imm; | ||
148 | |||
149 | if (n == 0 || (a->vd + n) > 32) { | ||
150 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) | ||
151 | TCGv_i64 tmp; | ||
152 | int i, n; | ||
153 | |||
154 | + /* Note that this does not require support for double arithmetic. */ | ||
155 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
156 | + return false; | ||
157 | + } | ||
158 | + | ||
159 | n = a->imm >> 1; | ||
160 | |||
161 | if (n == 0 || (a->vd + n) > 32 || n > 16) { | ||
162 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
163 | TCGv_i32 f0, f1, fd; | ||
164 | TCGv_ptr fpst; | ||
165 | |||
166 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
167 | + return false; | ||
168 | + } | ||
169 | + | ||
170 | if (!dc_isar_feature(aa32_fpshvec, s) && | ||
171 | (veclen != 0 || s->vec_stride != 0)) { | ||
172 | return false; | ||
173 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
174 | int veclen = s->vec_len; | ||
175 | TCGv_i32 f0, fd; | ||
176 | |||
177 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
178 | + return false; | ||
179 | + } | ||
180 | + | ||
181 | if (!dc_isar_feature(aa32_fpshvec, s) && | ||
182 | (veclen != 0 || s->vec_stride != 0)) { | ||
183 | return false; | ||
184 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a) | ||
185 | { | ||
186 | TCGv_i32 vd, vm; | ||
187 | |||
188 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
189 | + return false; | ||
190 | + } | ||
191 | + | ||
192 | /* Vm/M bits must be zero for the Z variant */ | ||
193 | if (a->z && a->vm != 0) { | ||
194 | return false; | ||
195 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
196 | TCGv_i32 vm; | ||
197 | TCGv_ptr fpst; | ||
198 | |||
199 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
200 | + return false; | ||
201 | + } | ||
202 | + | ||
203 | if (!vfp_access_check(s)) { | ||
204 | return true; | ||
205 | } | ||
206 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
207 | TCGv_i32 vm; | ||
208 | TCGv_ptr fpst; | ||
209 | |||
210 | + if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
211 | + return false; | ||
212 | + } | ||
213 | + | ||
214 | if (!vfp_access_check(s)) { | ||
215 | return true; | ||
41 | } | 216 | } |
42 | -- | 217 | -- |
43 | 2.20.1 | 218 | 2.20.1 |
44 | 219 | ||
45 | 220 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | All remaining tests for VFP4 are for fused multiply-add insns. | ||
4 | |||
5 | Since the MVFR1 field is used for both VFP and NEON, move its adjustment | ||
6 | from the !has_neon block to the (!has_vfp && !has_neon) block. | ||
7 | |||
8 | Test for vfp of the appropraite width alongside the test for simdfmac | ||
9 | within translate-vfp.inc.c. Within disas_neon_data_insn, we have | ||
10 | already tested for ARM_FEATURE_NEON. | ||
11 | |||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Message-id: 20200224222232.13807-10-richard.henderson@linaro.org | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | target/arm/cpu.h | 12 ++++++++++++ | ||
18 | target/arm/cpu.c | 6 +++++- | ||
19 | target/arm/translate-vfp.inc.c | 22 ++++++++++++++++++---- | ||
20 | target/arm/translate.c | 2 +- | ||
21 | 4 files changed, 36 insertions(+), 6 deletions(-) | ||
22 | |||
23 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/arm/cpu.h | ||
26 | +++ b/target/arm/cpu.h | ||
27 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) | ||
28 | return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; | ||
29 | } | ||
30 | |||
31 | +/* | ||
32 | + * Note that this ID register field covers both VFP and Neon FMAC, | ||
33 | + * so should usually be tested in combination with some other | ||
34 | + * check that confirms the presence of whichever of VFP or Neon is | ||
35 | + * relevant, to avoid accidentally enabling a Neon feature on | ||
36 | + * a VFP-no-Neon core or vice-versa. | ||
37 | + */ | ||
38 | +static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) | ||
39 | +{ | ||
40 | + return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0; | ||
41 | +} | ||
42 | + | ||
43 | static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) | ||
44 | { | ||
45 | return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1; | ||
46 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/cpu.c | ||
49 | +++ b/target/arm/cpu.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
51 | u = FIELD_DP32(u, MVFR1, SIMDINT, 0); | ||
52 | u = FIELD_DP32(u, MVFR1, SIMDSP, 0); | ||
53 | u = FIELD_DP32(u, MVFR1, SIMDHP, 0); | ||
54 | - u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); | ||
55 | cpu->isar.mvfr1 = u; | ||
56 | |||
57 | u = cpu->isar.mvfr2; | ||
58 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
59 | u = cpu->isar.mvfr0; | ||
60 | u = FIELD_DP32(u, MVFR0, SIMDREG, 0); | ||
61 | cpu->isar.mvfr0 = u; | ||
62 | + | ||
63 | + /* Despite the name, this field covers both VFP and Neon */ | ||
64 | + u = cpu->isar.mvfr1; | ||
65 | + u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0); | ||
66 | + cpu->isar.mvfr1 = u; | ||
67 | } | ||
68 | |||
69 | if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { | ||
70 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/target/arm/translate-vfp.inc.c | ||
73 | +++ b/target/arm/translate-vfp.inc.c | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) | ||
75 | |||
76 | /* | ||
77 | * Present in VFPv4 only. | ||
78 | + * Note that we can't rely on the SIMDFMAC check alone, because | ||
79 | + * in a Neon-no-VFP core that ID register field will be non-zero. | ||
80 | + */ | ||
81 | + if (!dc_isar_feature(aa32_simdfmac, s) || | ||
82 | + !dc_isar_feature(aa32_fpsp_v2, s)) { | ||
83 | + return false; | ||
84 | + } | ||
85 | + /* | ||
86 | * In v7A, UNPREDICTABLE with non-zero vector length/stride; from | ||
87 | * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. | ||
88 | */ | ||
89 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || | ||
90 | - (s->vec_len != 0 || s->vec_stride != 0)) { | ||
91 | + if (s->vec_len != 0 || s->vec_stride != 0) { | ||
92 | return false; | ||
93 | } | ||
94 | |||
95 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) | ||
96 | |||
97 | /* | ||
98 | * Present in VFPv4 only. | ||
99 | + * Note that we can't rely on the SIMDFMAC check alone, because | ||
100 | + * in a Neon-no-VFP core that ID register field will be non-zero. | ||
101 | + */ | ||
102 | + if (!dc_isar_feature(aa32_simdfmac, s) || | ||
103 | + !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
104 | + return false; | ||
105 | + } | ||
106 | + /* | ||
107 | * In v7A, UNPREDICTABLE with non-zero vector length/stride; from | ||
108 | * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. | ||
109 | */ | ||
110 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || | ||
111 | - (s->vec_len != 0 || s->vec_stride != 0)) { | ||
112 | + if (s->vec_len != 0 || s->vec_stride != 0) { | ||
113 | return false; | ||
114 | } | ||
115 | |||
116 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/target/arm/translate.c | ||
119 | +++ b/target/arm/translate.c | ||
120 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
121 | } | ||
122 | break; | ||
123 | case NEON_3R_VFM_VQRDMLSH: | ||
124 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { | ||
125 | + if (!dc_isar_feature(aa32_simdfmac, s)) { | ||
126 | return 1; | ||
127 | } | ||
128 | break; | ||
129 | -- | ||
130 | 2.20.1 | ||
131 | |||
132 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | We now have proper ISA checks within each trans_* function. | ||
4 | |||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200224222232.13807-11-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/translate.c | 4 ---- | ||
11 | 1 file changed, 4 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate.c | ||
16 | +++ b/target/arm/translate.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var) | ||
18 | */ | ||
19 | static int disas_vfp_insn(DisasContext *s, uint32_t insn) | ||
20 | { | ||
21 | - if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { | ||
22 | - return 1; | ||
23 | - } | ||
24 | - | ||
25 | /* | ||
26 | * If the decodetree decoder handles this insn it will always | ||
27 | * emit code to either execute the insn or generate an appropriate | ||
28 | -- | ||
29 | 2.20.1 | ||
30 | |||
31 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Now that we no longer have an early check for ARM_FEATURE_VFP, | ||
4 | we can use the proper ISA check in trans_VLLDM_VLSTM. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Message-id: 20200224222232.13807-12-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate-vfp.inc.c | 39 +++++++++++++++++++++++++ | ||
12 | target/arm/translate.c | 53 ++++++---------------------------- | ||
13 | target/arm/vfp.decode | 2 ++ | ||
14 | 3 files changed, 50 insertions(+), 44 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/translate-vfp.inc.c | ||
19 | +++ b/target/arm/translate-vfp.inc.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
21 | tcg_temp_free_ptr(fpst); | ||
22 | return true; | ||
23 | } | ||
24 | + | ||
25 | +/* | ||
26 | + * Decode VLLDM and VLSTM are nonstandard because: | ||
27 | + * * if there is no FPU then these insns must NOP in | ||
28 | + * Secure state and UNDEF in Nonsecure state | ||
29 | + * * if there is an FPU then these insns do not have | ||
30 | + * the usual behaviour that vfp_access_check() provides of | ||
31 | + * being controlled by CPACR/NSACR enable bits or the | ||
32 | + * lazy-stacking logic. | ||
33 | + */ | ||
34 | +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) | ||
35 | +{ | ||
36 | + TCGv_i32 fptr; | ||
37 | + | ||
38 | + if (!arm_dc_feature(s, ARM_FEATURE_M) || | ||
39 | + !arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
40 | + return false; | ||
41 | + } | ||
42 | + /* If not secure, UNDEF. */ | ||
43 | + if (!s->v8m_secure) { | ||
44 | + return false; | ||
45 | + } | ||
46 | + /* If no fpu, NOP. */ | ||
47 | + if (!dc_isar_feature(aa32_vfp, s)) { | ||
48 | + return true; | ||
49 | + } | ||
50 | + | ||
51 | + fptr = load_reg(s, a->rn); | ||
52 | + if (a->l) { | ||
53 | + gen_helper_v7m_vlldm(cpu_env, fptr); | ||
54 | + } else { | ||
55 | + gen_helper_v7m_vlstm(cpu_env, fptr); | ||
56 | + } | ||
57 | + tcg_temp_free_i32(fptr); | ||
58 | + | ||
59 | + /* End the TB, because we have updated FP control bits */ | ||
60 | + s->base.is_jmp = DISAS_UPDATE; | ||
61 | + return true; | ||
62 | +} | ||
63 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/target/arm/translate.c | ||
66 | +++ b/target/arm/translate.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
68 | goto illegal_op; /* op0 = 0b11 : unallocated */ | ||
69 | } | ||
70 | |||
71 | - /* | ||
72 | - * Decode VLLDM and VLSTM first: these are nonstandard because: | ||
73 | - * * if there is no FPU then these insns must NOP in | ||
74 | - * Secure state and UNDEF in Nonsecure state | ||
75 | - * * if there is an FPU then these insns do not have | ||
76 | - * the usual behaviour that disas_vfp_insn() provides of | ||
77 | - * being controlled by CPACR/NSACR enable bits or the | ||
78 | - * lazy-stacking logic. | ||
79 | - */ | ||
80 | - if (arm_dc_feature(s, ARM_FEATURE_V8) && | ||
81 | - (insn & 0xffa00f00) == 0xec200a00) { | ||
82 | - /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx | ||
83 | - * - VLLDM, VLSTM | ||
84 | - * We choose to UNDEF if the RAZ bits are non-zero. | ||
85 | - */ | ||
86 | - if (!s->v8m_secure || (insn & 0x0040f0ff)) { | ||
87 | + if (disas_vfp_insn(s, insn)) { | ||
88 | + if (((insn >> 8) & 0xe) == 10 && | ||
89 | + dc_isar_feature(aa32_fpsp_v2, s)) { | ||
90 | + /* FP, and the CPU supports it */ | ||
91 | goto illegal_op; | ||
92 | + } else { | ||
93 | + /* All other insns: NOCP */ | ||
94 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
95 | + syn_uncategorized(), | ||
96 | + default_exception_el(s)); | ||
97 | } | ||
98 | - | ||
99 | - if (arm_dc_feature(s, ARM_FEATURE_VFP)) { | ||
100 | - uint32_t rn = (insn >> 16) & 0xf; | ||
101 | - TCGv_i32 fptr = load_reg(s, rn); | ||
102 | - | ||
103 | - if (extract32(insn, 20, 1)) { | ||
104 | - gen_helper_v7m_vlldm(cpu_env, fptr); | ||
105 | - } else { | ||
106 | - gen_helper_v7m_vlstm(cpu_env, fptr); | ||
107 | - } | ||
108 | - tcg_temp_free_i32(fptr); | ||
109 | - | ||
110 | - /* End the TB, because we have updated FP control bits */ | ||
111 | - s->base.is_jmp = DISAS_UPDATE; | ||
112 | - } | ||
113 | - break; | ||
114 | } | ||
115 | - if (arm_dc_feature(s, ARM_FEATURE_VFP) && | ||
116 | - ((insn >> 8) & 0xe) == 10) { | ||
117 | - /* FP, and the CPU supports it */ | ||
118 | - if (disas_vfp_insn(s, insn)) { | ||
119 | - goto illegal_op; | ||
120 | - } | ||
121 | - break; | ||
122 | - } | ||
123 | - | ||
124 | - /* All other insns: NOCP */ | ||
125 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(), | ||
126 | - default_exception_el(s)); | ||
127 | break; | ||
128 | } | ||
129 | if ((insn & 0xfe000a00) == 0xfc000800 | ||
130 | diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode | ||
131 | index XXXXXXX..XXXXXXX 100644 | ||
132 | --- a/target/arm/vfp.decode | ||
133 | +++ b/target/arm/vfp.decode | ||
134 | @@ -XXX,XX +XXX,XX @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \ | ||
135 | vd=%vd_sp vm=%vm_sp | ||
136 | VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ | ||
137 | vd=%vd_sp vm=%vm_dp | ||
138 | + | ||
139 | +VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 | ||
140 | -- | ||
141 | 2.20.1 | ||
142 | |||
143 | diff view generated by jsdifflib |
1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Fix code style. Space required before the open parenthesis '('. | 3 | Have the calls adjacent as an intermediate step toward |
4 | actually merging the decodes. | ||
4 | 5 | ||
5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | ||
7 | Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20200224222232.13807-13-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/translate.c | 2 +- | 11 | target/arm/translate.c | 83 +++++++++++++++--------------------------- |
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 29 insertions(+), 54 deletions(-) |
13 | 13 | ||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.c | 16 | --- a/target/arm/translate.c |
17 | +++ b/target/arm/translate.c | 17 | +++ b/target/arm/translate.c |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | 18 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var) |
19 | - Hardware watchpoints. | 19 | tcg_temp_free_i32(tmp); |
20 | Hardware breakpoints have already been handled and skip this code. | 20 | } |
21 | */ | 21 | |
22 | - switch(dc->base.is_jmp) { | 22 | -/* |
23 | + switch (dc->base.is_jmp) { | 23 | - * Disassemble a VFP instruction. Returns nonzero if an error occurred |
24 | case DISAS_NEXT: | 24 | - * (ie. an undefined instruction). |
25 | case DISAS_TOO_MANY: | 25 | - */ |
26 | gen_goto_tb(dc, 1, dc->base.pc_next); | 26 | -static int disas_vfp_insn(DisasContext *s, uint32_t insn) |
27 | -{ | ||
28 | - /* | ||
29 | - * If the decodetree decoder handles this insn it will always | ||
30 | - * emit code to either execute the insn or generate an appropriate | ||
31 | - * exception; so we don't need to ever return non-zero to tell | ||
32 | - * the calling code to emit an UNDEF exception. | ||
33 | - */ | ||
34 | - if (extract32(insn, 28, 4) == 0xf) { | ||
35 | - if (disas_vfp_uncond(s, insn)) { | ||
36 | - return 0; | ||
37 | - } | ||
38 | - } else { | ||
39 | - if (disas_vfp(s, insn)) { | ||
40 | - return 0; | ||
41 | - } | ||
42 | - } | ||
43 | - /* If the decodetree decoder didn't handle this insn, it must be UNDEF */ | ||
44 | - return 1; | ||
45 | -} | ||
46 | - | ||
47 | static inline bool use_goto_tb(DisasContext *s, target_ulong dest) | ||
48 | { | ||
49 | #ifndef CONFIG_USER_ONLY | ||
50 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
51 | ARCH(5); | ||
52 | |||
53 | /* Unconditional instructions. */ | ||
54 | - if (disas_a32_uncond(s, insn)) { | ||
55 | + /* TODO: Perhaps merge these into one decodetree output file. */ | ||
56 | + if (disas_a32_uncond(s, insn) || | ||
57 | + disas_vfp_uncond(s, insn)) { | ||
58 | return; | ||
59 | } | ||
60 | /* fall back to legacy decoder */ | ||
61 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
62 | } | ||
63 | return; | ||
64 | } | ||
65 | - if ((insn & 0x0f000e10) == 0x0e000a00) { | ||
66 | - /* VFP. */ | ||
67 | - if (disas_vfp_insn(s, insn)) { | ||
68 | - goto illegal_op; | ||
69 | - } | ||
70 | - return; | ||
71 | - } | ||
72 | if ((insn & 0x0e000f00) == 0x0c000100) { | ||
73 | if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { | ||
74 | /* iWMMXt register transfer. */ | ||
75 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
76 | arm_skip_unless(s, cond); | ||
77 | } | ||
78 | |||
79 | - if (disas_a32(s, insn)) { | ||
80 | + /* TODO: Perhaps merge these into one decodetree output file. */ | ||
81 | + if (disas_a32(s, insn) || | ||
82 | + disas_vfp(s, insn)) { | ||
83 | return; | ||
84 | } | ||
85 | /* fall back to legacy decoder */ | ||
86 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
87 | case 0xd: | ||
88 | case 0xe: | ||
89 | if (((insn >> 8) & 0xe) == 10) { | ||
90 | - /* VFP. */ | ||
91 | - if (disas_vfp_insn(s, insn)) { | ||
92 | - goto illegal_op; | ||
93 | - } | ||
94 | - } else if (disas_coproc_insn(s, insn)) { | ||
95 | + /* VFP, but failed disas_vfp. */ | ||
96 | + goto illegal_op; | ||
97 | + } | ||
98 | + if (disas_coproc_insn(s, insn)) { | ||
99 | /* Coprocessor. */ | ||
100 | goto illegal_op; | ||
101 | } | ||
102 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
103 | ARCH(6T2); | ||
104 | } | ||
105 | |||
106 | - if (disas_t32(s, insn)) { | ||
107 | + /* | ||
108 | + * TODO: Perhaps merge these into one decodetree output file. | ||
109 | + * Note disas_vfp is written for a32 with cond field in the | ||
110 | + * top nibble. The t32 encoding requires 0xe in the top nibble. | ||
111 | + */ | ||
112 | + if (disas_t32(s, insn) || | ||
113 | + disas_vfp_uncond(s, insn) || | ||
114 | + ((insn >> 28) == 0xe && disas_vfp(s, insn))) { | ||
115 | return; | ||
116 | } | ||
117 | /* fall back to legacy decoder */ | ||
118 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
119 | goto illegal_op; /* op0 = 0b11 : unallocated */ | ||
120 | } | ||
121 | |||
122 | - if (disas_vfp_insn(s, insn)) { | ||
123 | - if (((insn >> 8) & 0xe) == 10 && | ||
124 | - dc_isar_feature(aa32_fpsp_v2, s)) { | ||
125 | - /* FP, and the CPU supports it */ | ||
126 | - goto illegal_op; | ||
127 | - } else { | ||
128 | - /* All other insns: NOCP */ | ||
129 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
130 | - syn_uncategorized(), | ||
131 | - default_exception_el(s)); | ||
132 | - } | ||
133 | + if (((insn >> 8) & 0xe) == 10 && | ||
134 | + dc_isar_feature(aa32_fpsp_v2, s)) { | ||
135 | + /* FP, and the CPU supports it */ | ||
136 | + goto illegal_op; | ||
137 | + } else { | ||
138 | + /* All other insns: NOCP */ | ||
139 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
140 | + syn_uncategorized(), | ||
141 | + default_exception_el(s)); | ||
142 | } | ||
143 | break; | ||
144 | } | ||
145 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
146 | goto illegal_op; | ||
147 | } | ||
148 | } else if (((insn >> 8) & 0xe) == 10) { | ||
149 | - if (disas_vfp_insn(s, insn)) { | ||
150 | - goto illegal_op; | ||
151 | - } | ||
152 | + /* VFP, but failed disas_vfp. */ | ||
153 | + goto illegal_op; | ||
154 | } else { | ||
155 | if (insn & (1 << 28)) | ||
156 | goto illegal_op; | ||
27 | -- | 157 | -- |
28 | 2.20.1 | 158 | 2.20.1 |
29 | 159 | ||
30 | 160 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Use isar feature tests instead of feature bit tests. | ||
4 | |||
5 | Although none of QEMUs current cpus have VFPv3 without D32, | ||
6 | replace the large comment explaining why with one line that | ||
7 | sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. | ||
8 | Mirror the test sequence used in the linux kernel. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Message-id: 20200224222232.13807-14-richard.henderson@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | linux-user/elfload.c | 23 +++++++++++++---------- | ||
16 | 1 file changed, 13 insertions(+), 10 deletions(-) | ||
17 | |||
18 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/linux-user/elfload.c | ||
21 | +++ b/linux-user/elfload.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
23 | |||
24 | /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ | ||
25 | GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); | ||
26 | - GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); | ||
27 | GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); | ||
28 | GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); | ||
29 | GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); | ||
30 | - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); | ||
31 | GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); | ||
32 | - GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); | ||
33 | + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); | ||
34 | GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); | ||
35 | GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); | ||
36 | - /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c. | ||
37 | - * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of | ||
38 | - * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated | ||
39 | - * to our VFP_FP16 feature bit. | ||
40 | - */ | ||
41 | - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32); | ||
42 | - GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); | ||
43 | + GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP); | ||
44 | + | ||
45 | + if (cpu_isar_feature(aa32_fpsp_v3, cpu) || | ||
46 | + cpu_isar_feature(aa32_fpdp_v3, cpu)) { | ||
47 | + hwcaps |= ARM_HWCAP_ARM_VFPv3; | ||
48 | + if (cpu_isar_feature(aa32_simd_r32, cpu)) { | ||
49 | + hwcaps |= ARM_HWCAP_ARM_VFPD32; | ||
50 | + } else { | ||
51 | + hwcaps |= ARM_HWCAP_ARM_VFPv3D16; | ||
52 | + } | ||
53 | + } | ||
54 | + GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); | ||
55 | |||
56 | return hwcaps; | ||
57 | } | ||
58 | -- | ||
59 | 2.20.1 | ||
60 | |||
61 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | We have converted all tests against these features | ||
4 | to ISAR tests. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200224222232.13807-15-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 3 --- | ||
12 | target/arm/cpu.c | 25 ------------------------- | ||
13 | target/arm/cpu64.c | 3 --- | ||
14 | target/arm/kvm32.c | 5 ----- | ||
15 | target/arm/kvm64.c | 1 - | ||
16 | 5 files changed, 37 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/cpu.h | ||
21 | +++ b/target/arm/cpu.h | ||
22 | @@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); | ||
23 | * mapping in linux-user/elfload.c:get_elf_hwcap(). | ||
24 | */ | ||
25 | enum arm_features { | ||
26 | - ARM_FEATURE_VFP, | ||
27 | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ | ||
28 | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ | ||
29 | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ | ||
30 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | ||
31 | ARM_FEATURE_V7, | ||
32 | ARM_FEATURE_THUMB2, | ||
33 | ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ | ||
34 | - ARM_FEATURE_VFP3, | ||
35 | ARM_FEATURE_NEON, | ||
36 | ARM_FEATURE_M, /* Microcontroller profile. */ | ||
37 | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ | ||
38 | @@ -XXX,XX +XXX,XX @@ enum arm_features { | ||
39 | ARM_FEATURE_V5, | ||
40 | ARM_FEATURE_STRONGARM, | ||
41 | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ | ||
42 | - ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ | ||
43 | ARM_FEATURE_GENERIC_TIMER, | ||
44 | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ | ||
45 | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */ | ||
46 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/cpu.c | ||
49 | +++ b/target/arm/cpu.c | ||
50 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj) | ||
51 | if (arm_feature(&cpu->env, ARM_FEATURE_M)) { | ||
52 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | ||
53 | } | ||
54 | - /* Similarly for the VFP feature bits */ | ||
55 | - if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { | ||
56 | - set_feature(&cpu->env, ARM_FEATURE_VFP3); | ||
57 | - } | ||
58 | - if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { | ||
59 | - set_feature(&cpu->env, ARM_FEATURE_VFP); | ||
60 | - } | ||
61 | |||
62 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || | ||
63 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | ||
64 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
65 | uint64_t t; | ||
66 | uint32_t u; | ||
67 | |||
68 | - unset_feature(env, ARM_FEATURE_VFP); | ||
69 | - unset_feature(env, ARM_FEATURE_VFP3); | ||
70 | - unset_feature(env, ARM_FEATURE_VFP4); | ||
71 | - | ||
72 | t = cpu->isar.id_aa64isar1; | ||
73 | t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); | ||
74 | cpu->isar.id_aa64isar1 = t; | ||
75 | @@ -XXX,XX +XXX,XX @@ static void arm926_initfn(Object *obj) | ||
76 | |||
77 | cpu->dtb_compatible = "arm,arm926"; | ||
78 | set_feature(&cpu->env, ARM_FEATURE_V5); | ||
79 | - set_feature(&cpu->env, ARM_FEATURE_VFP); | ||
80 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
81 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | ||
82 | cpu->midr = 0x41069265; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void arm1026_initfn(Object *obj) | ||
84 | |||
85 | cpu->dtb_compatible = "arm,arm1026"; | ||
86 | set_feature(&cpu->env, ARM_FEATURE_V5); | ||
87 | - set_feature(&cpu->env, ARM_FEATURE_VFP); | ||
88 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | ||
89 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
90 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | ||
91 | @@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj) | ||
92 | |||
93 | cpu->dtb_compatible = "arm,arm1136"; | ||
94 | set_feature(&cpu->env, ARM_FEATURE_V6); | ||
95 | - set_feature(&cpu->env, ARM_FEATURE_VFP); | ||
96 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
97 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | ||
98 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | ||
99 | @@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj) | ||
100 | cpu->dtb_compatible = "arm,arm1136"; | ||
101 | set_feature(&cpu->env, ARM_FEATURE_V6K); | ||
102 | set_feature(&cpu->env, ARM_FEATURE_V6); | ||
103 | - set_feature(&cpu->env, ARM_FEATURE_VFP); | ||
104 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
105 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | ||
106 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | ||
107 | @@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj) | ||
108 | |||
109 | cpu->dtb_compatible = "arm,arm1176"; | ||
110 | set_feature(&cpu->env, ARM_FEATURE_V6K); | ||
111 | - set_feature(&cpu->env, ARM_FEATURE_VFP); | ||
112 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | ||
113 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
114 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | ||
115 | @@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj) | ||
116 | |||
117 | cpu->dtb_compatible = "arm,arm11mpcore"; | ||
118 | set_feature(&cpu->env, ARM_FEATURE_V6K); | ||
119 | - set_feature(&cpu->env, ARM_FEATURE_VFP); | ||
120 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | ||
121 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); | ||
122 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
123 | @@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj) | ||
124 | set_feature(&cpu->env, ARM_FEATURE_M); | ||
125 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
126 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
127 | - set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
128 | cpu->midr = 0x410fc240; /* r0p0 */ | ||
129 | cpu->pmsav7_dregion = 8; | ||
130 | cpu->isar.mvfr0 = 0x10110021; | ||
131 | @@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj) | ||
132 | set_feature(&cpu->env, ARM_FEATURE_M); | ||
133 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
134 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
135 | - set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
136 | cpu->midr = 0x411fc272; /* r1p2 */ | ||
137 | cpu->pmsav7_dregion = 8; | ||
138 | cpu->isar.mvfr0 = 0x10110221; | ||
139 | @@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj) | ||
140 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | ||
141 | set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | ||
142 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | ||
143 | - set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
144 | cpu->midr = 0x410fd213; /* r0p3 */ | ||
145 | cpu->pmsav7_dregion = 16; | ||
146 | cpu->sau_sregion = 8; | ||
147 | @@ -XXX,XX +XXX,XX @@ static void cortex_r5f_initfn(Object *obj) | ||
148 | ARMCPU *cpu = ARM_CPU(obj); | ||
149 | |||
150 | cortex_r5_initfn(obj); | ||
151 | - set_feature(&cpu->env, ARM_FEATURE_VFP3); | ||
152 | cpu->isar.mvfr0 = 0x10110221; | ||
153 | cpu->isar.mvfr1 = 0x00000011; | ||
154 | } | ||
155 | @@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj) | ||
156 | |||
157 | cpu->dtb_compatible = "arm,cortex-a8"; | ||
158 | set_feature(&cpu->env, ARM_FEATURE_V7); | ||
159 | - set_feature(&cpu->env, ARM_FEATURE_VFP3); | ||
160 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
161 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | ||
162 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | ||
163 | @@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj) | ||
164 | |||
165 | cpu->dtb_compatible = "arm,cortex-a9"; | ||
166 | set_feature(&cpu->env, ARM_FEATURE_V7); | ||
167 | - set_feature(&cpu->env, ARM_FEATURE_VFP3); | ||
168 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
169 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | ||
170 | set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
171 | @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) | ||
172 | |||
173 | cpu->dtb_compatible = "arm,cortex-a7"; | ||
174 | set_feature(&cpu->env, ARM_FEATURE_V7VE); | ||
175 | - set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
176 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
177 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | ||
178 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
179 | @@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj) | ||
180 | |||
181 | cpu->dtb_compatible = "arm,cortex-a15"; | ||
182 | set_feature(&cpu->env, ARM_FEATURE_V7VE); | ||
183 | - set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
184 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
185 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | ||
186 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
187 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
188 | index XXXXXXX..XXXXXXX 100644 | ||
189 | --- a/target/arm/cpu64.c | ||
190 | +++ b/target/arm/cpu64.c | ||
191 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | ||
192 | |||
193 | cpu->dtb_compatible = "arm,cortex-a57"; | ||
194 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
195 | - set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
196 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
197 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
198 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
199 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
200 | |||
201 | cpu->dtb_compatible = "arm,cortex-a53"; | ||
202 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
203 | - set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
204 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
205 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
206 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
207 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj) | ||
208 | |||
209 | cpu->dtb_compatible = "arm,cortex-a72"; | ||
210 | set_feature(&cpu->env, ARM_FEATURE_V8); | ||
211 | - set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
212 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
213 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
214 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
215 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | ||
216 | index XXXXXXX..XXXXXXX 100644 | ||
217 | --- a/target/arm/kvm32.c | ||
218 | +++ b/target/arm/kvm32.c | ||
219 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
220 | * bits, but a few must be tested. | ||
221 | */ | ||
222 | set_feature(&features, ARM_FEATURE_V7VE); | ||
223 | - set_feature(&features, ARM_FEATURE_VFP3); | ||
224 | set_feature(&features, ARM_FEATURE_GENERIC_TIMER); | ||
225 | |||
226 | if (extract32(id_pfr0, 12, 4) == 1) { | ||
227 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
228 | if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) { | ||
229 | set_feature(&features, ARM_FEATURE_NEON); | ||
230 | } | ||
231 | - if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) { | ||
232 | - /* FMAC support implies VFPv4 */ | ||
233 | - set_feature(&features, ARM_FEATURE_VFP4); | ||
234 | - } | ||
235 | |||
236 | ahcf->features = features; | ||
237 | |||
238 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
239 | index XXXXXXX..XXXXXXX 100644 | ||
240 | --- a/target/arm/kvm64.c | ||
241 | +++ b/target/arm/kvm64.c | ||
242 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
243 | * feature bits. | ||
244 | */ | ||
245 | set_feature(&features, ARM_FEATURE_V8); | ||
246 | - set_feature(&features, ARM_FEATURE_VFP4); | ||
247 | set_feature(&features, ARM_FEATURE_NEON); | ||
248 | set_feature(&features, ARM_FEATURE_AARCH64); | ||
249 | set_feature(&features, ARM_FEATURE_PMU); | ||
250 | -- | ||
251 | 2.20.1 | ||
252 | |||
253 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Richard Henderson <richard.henderson@linaro.org> | |
2 | |||
3 | Those vfp instructions without extra opcode fields can | ||
4 | share a common @format for brevity. | ||
5 | |||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200224222232.13807-16-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/vfp.decode | 134 ++++++++++++++++-------------------------- | ||
12 | 1 file changed, 52 insertions(+), 82 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/vfp.decode | ||
17 | +++ b/target/arm/vfp.decode | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | %vmov_imm 16:4 0:4 | ||
21 | |||
22 | +@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
23 | +@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
24 | + | ||
25 | +@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp | ||
26 | +@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp | ||
27 | +@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp | ||
28 | +@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp | ||
29 | + | ||
30 | # VMOV scalar to general-purpose register; note that this does | ||
31 | # include some Neon cases. | ||
32 | VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ | ||
33 | @@ -XXX,XX +XXX,XX @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \ | ||
34 | vn=%vn_dp | ||
35 | |||
36 | VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 | ||
37 | -VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \ | ||
38 | - vn=%vn_sp | ||
39 | +VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp | ||
40 | |||
41 | -VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \ | ||
42 | - vm=%vm_sp | ||
43 | -VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \ | ||
44 | - vm=%vm_dp | ||
45 | +VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp | ||
46 | +VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp | ||
47 | |||
48 | # Note that the half-precision variants of VLDR and VSTR are | ||
49 | # not part of this decodetree at all because they have bits [9:8] == 0b01 | ||
50 | -VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \ | ||
51 | - vd=%vd_sp | ||
52 | -VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \ | ||
53 | - vd=%vd_dp | ||
54 | +VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp | ||
55 | +VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp | ||
56 | |||
57 | # We split the load/store multiple up into two patterns to avoid | ||
58 | # overlap with other insns in the "Advanced SIMD load/store and 64-bit move" | ||
59 | @@ -XXX,XX +XXX,XX @@ VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ | ||
60 | vd=%vd_dp p=1 u=0 w=1 | ||
61 | |||
62 | # 3-register VFP data-processing; bits [23,21:20,6] identify the operation. | ||
63 | -VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \ | ||
64 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
65 | -VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \ | ||
66 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
67 | +VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s | ||
68 | +VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
69 | |||
70 | -VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \ | ||
71 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
72 | -VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \ | ||
73 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
74 | +VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s | ||
75 | +VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d | ||
76 | |||
77 | -VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \ | ||
78 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
79 | -VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \ | ||
80 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
81 | +VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s | ||
82 | +VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
83 | |||
84 | -VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \ | ||
85 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
86 | -VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \ | ||
87 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
88 | +VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s | ||
89 | +VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d | ||
90 | |||
91 | -VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \ | ||
92 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
93 | -VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \ | ||
94 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
95 | +VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s | ||
96 | +VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
97 | |||
98 | -VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \ | ||
99 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
100 | -VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \ | ||
101 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
102 | +VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s | ||
103 | +VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d | ||
104 | |||
105 | -VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \ | ||
106 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
107 | -VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \ | ||
108 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
109 | +VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s | ||
110 | +VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
111 | |||
112 | -VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \ | ||
113 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
114 | -VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \ | ||
115 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
116 | +VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s | ||
117 | +VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d | ||
118 | |||
119 | -VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \ | ||
120 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
121 | -VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \ | ||
122 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
123 | +VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s | ||
124 | +VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
125 | |||
126 | VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ | ||
127 | vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1 | ||
128 | @@ -XXX,XX +XXX,XX @@ VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ | ||
129 | VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \ | ||
130 | vd=%vd_dp imm=%vmov_imm | ||
131 | |||
132 | -VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \ | ||
133 | - vd=%vd_sp vm=%vm_sp | ||
134 | -VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \ | ||
135 | - vd=%vd_dp vm=%vm_dp | ||
136 | +VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss | ||
137 | +VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd | ||
138 | |||
139 | -VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ | ||
140 | - vd=%vd_sp vm=%vm_sp | ||
141 | -VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ | ||
142 | - vd=%vd_dp vm=%vm_dp | ||
143 | +VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss | ||
144 | +VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd | ||
145 | |||
146 | -VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ | ||
147 | - vd=%vd_sp vm=%vm_sp | ||
148 | -VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ | ||
149 | - vd=%vd_dp vm=%vm_dp | ||
150 | +VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss | ||
151 | +VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd | ||
152 | |||
153 | -VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \ | ||
154 | - vd=%vd_sp vm=%vm_sp | ||
155 | -VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \ | ||
156 | - vd=%vd_dp vm=%vm_dp | ||
157 | +VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss | ||
158 | +VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd | ||
159 | |||
160 | VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ | ||
161 | vd=%vd_sp vm=%vm_sp | ||
162 | @@ -XXX,XX +XXX,XX @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \ | ||
163 | VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ | ||
164 | vd=%vd_dp vm=%vm_sp | ||
165 | |||
166 | -# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on size bit | ||
167 | +# VCVTB and VCVTT to f16: Vd format is always vd_sp; | ||
168 | +# Vm format depends on size bit | ||
169 | VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ | ||
170 | vd=%vd_sp vm=%vm_sp | ||
171 | VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ | ||
172 | vd=%vd_sp vm=%vm_dp | ||
173 | |||
174 | -VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \ | ||
175 | - vd=%vd_sp vm=%vm_sp | ||
176 | -VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \ | ||
177 | - vd=%vd_dp vm=%vm_dp | ||
178 | +VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss | ||
179 | +VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd | ||
180 | |||
181 | -VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \ | ||
182 | - vd=%vd_sp vm=%vm_sp | ||
183 | -VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \ | ||
184 | - vd=%vd_dp vm=%vm_dp | ||
185 | +VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss | ||
186 | +VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd | ||
187 | |||
188 | -VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \ | ||
189 | - vd=%vd_sp vm=%vm_sp | ||
190 | -VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \ | ||
191 | - vd=%vd_dp vm=%vm_dp | ||
192 | +VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss | ||
193 | +VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd | ||
194 | |||
195 | -# VCVT between single and double: Vm precision depends on size; Vd is its reverse | ||
196 | -VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \ | ||
197 | - vd=%vd_dp vm=%vm_sp | ||
198 | -VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \ | ||
199 | - vd=%vd_sp vm=%vm_dp | ||
200 | +# VCVT between single and double: | ||
201 | +# Vm precision depends on size; Vd is its reverse | ||
202 | +VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds | ||
203 | +VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd | ||
204 | |||
205 | # VCVT from integer to floating point: Vm always single; Vd depends on size | ||
206 | VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ | ||
207 | @@ -XXX,XX +XXX,XX @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \ | ||
208 | vd=%vd_dp vm=%vm_sp | ||
209 | |||
210 | # VJCVT is always dp to sp | ||
211 | -VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \ | ||
212 | - vd=%vd_sp vm=%vm_dp | ||
213 | +VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd | ||
214 | |||
215 | # VCVT between floating-point and fixed-point. The immediate value | ||
216 | # is in the same format as a Vm single-precision register number. | ||
217 | -- | ||
218 | 2.20.1 | ||
219 | |||
220 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The helper function did not get updated when we reorganized | 3 | Passing the raw o1 and o2 fields from the manual is less |
4 | the vector register file for SVE. Since then, the neon dregs | 4 | instructive than it might be. Do the full decode and let |
5 | are non-sequential and cannot be simply indexed. | 5 | the trans_* functions pass in booleans to a helper. |
6 | 6 | ||
7 | At the same time, make the helper function operate on 64-bit | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | quantities so that we do not have to call it twice. | ||
9 | |||
10 | Fixes: c39c2b9043e | ||
11 | Reported-by: Ard Biesheuvel <ardb@kernel.org> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
13 | [PMM: use aa32_vfp_dreg() rather than opencoding] | 9 | Message-id: 20200224222232.13807-17-richard.henderson@linaro.org |
14 | Message-id: 20201105171126.88014-1-richard.henderson@linaro.org | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 11 | --- |
18 | target/arm/helper.h | 2 +- | 12 | target/arm/translate-vfp.inc.c | 52 ++++++++++++++++++++++++++++++---- |
19 | target/arm/op_helper.c | 23 +++++++++-------- | 13 | target/arm/vfp.decode | 17 +++++------ |
20 | target/arm/translate-neon.c.inc | 44 +++++++++++---------------------- | 14 | 2 files changed, 55 insertions(+), 14 deletions(-) |
21 | 3 files changed, 29 insertions(+), 40 deletions(-) | ||
22 | 15 | ||
23 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 16 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c |
24 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/helper.h | 18 | --- a/target/arm/translate-vfp.inc.c |
26 | +++ b/target/arm/helper.h | 19 | +++ b/target/arm/translate-vfp.inc.c |
27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) | 20 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a) |
28 | DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) | 21 | return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false); |
29 | DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) | ||
30 | DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) | ||
31 | -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) | ||
33 | |||
34 | DEF_HELPER_3(shl_cc, i32, env, i32, i32) | ||
35 | DEF_HELPER_3(shr_cc, i32, env, i32, i32) | ||
36 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/op_helper.c | ||
39 | +++ b/target/arm/op_helper.c | ||
40 | @@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, | ||
41 | cpu_loop_exit_restore(cs, ra); | ||
42 | } | 22 | } |
43 | 23 | ||
44 | -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, | 24 | -static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) |
45 | - uint32_t maxindex) | 25 | +static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) |
46 | +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, | ||
47 | + uint64_t ireg, uint64_t def) | ||
48 | { | 26 | { |
49 | - uint32_t val, shift; | 27 | /* |
50 | - uint64_t *table = vn; | 28 | * VFNMA : fd = muladd(-fd, fn, fm) |
51 | + uint64_t tmp, val = 0; | 29 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) |
52 | + uint32_t maxindex = ((desc & 3) + 1) * 8; | 30 | |
53 | + uint32_t base_reg = desc >> 2; | 31 | neon_load_reg32(vn, a->vn); |
54 | + uint32_t shift, index, reg; | 32 | neon_load_reg32(vm, a->vm); |
55 | 33 | - if (a->o2) { | |
56 | - val = 0; | 34 | + if (neg_n) { |
57 | - for (shift = 0; shift < 32; shift += 8) { | 35 | /* VFNMS, VFMS */ |
58 | - uint32_t index = (ireg >> shift) & 0xff; | 36 | gen_helper_vfp_negs(vn, vn); |
59 | + for (shift = 0; shift < 64; shift += 8) { | ||
60 | + index = (ireg >> shift) & 0xff; | ||
61 | if (index < maxindex) { | ||
62 | - uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; | ||
63 | - val |= tmp << shift; | ||
64 | + reg = base_reg + (index >> 3); | ||
65 | + tmp = *aa32_vfp_dreg(env, reg); | ||
66 | + tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; | ||
67 | } else { | ||
68 | - val |= def & (0xff << shift); | ||
69 | + tmp = def & (0xffull << shift); | ||
70 | } | ||
71 | + val |= tmp; | ||
72 | } | 37 | } |
73 | return val; | 38 | neon_load_reg32(vd, a->vd); |
74 | } | 39 | - if (a->o1 & 1) { |
75 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | 40 | + if (neg_d) { |
76 | index XXXXXXX..XXXXXXX 100644 | 41 | /* VFNMA, VFNMS */ |
77 | --- a/target/arm/translate-neon.c.inc | 42 | gen_helper_vfp_negs(vd, vd); |
78 | +++ b/target/arm/translate-neon.c.inc | ||
79 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
80 | |||
81 | static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
82 | { | ||
83 | - int n; | ||
84 | - TCGv_i32 tmp, tmp2, tmp3, tmp4; | ||
85 | - TCGv_ptr ptr1; | ||
86 | + TCGv_i64 val, def; | ||
87 | + TCGv_i32 desc; | ||
88 | |||
89 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
90 | return false; | ||
91 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
92 | return true; | ||
93 | } | 43 | } |
94 | 44 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) | |
95 | - n = a->len + 1; | ||
96 | - if ((a->vn + n) > 32) { | ||
97 | + if ((a->vn + a->len + 1) > 32) { | ||
98 | /* | ||
99 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | ||
100 | * helper function running off the end of the register file. | ||
101 | */ | ||
102 | return false; | ||
103 | } | ||
104 | - n <<= 3; | ||
105 | - tmp = tcg_temp_new_i32(); | ||
106 | - if (a->op) { | ||
107 | - read_neon_element32(tmp, a->vd, 0, MO_32); | ||
108 | - } else { | ||
109 | - tcg_gen_movi_i32(tmp, 0); | ||
110 | - } | ||
111 | - tmp2 = tcg_temp_new_i32(); | ||
112 | - read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
113 | - ptr1 = vfp_reg_ptr(true, a->vn); | ||
114 | - tmp4 = tcg_const_i32(n); | ||
115 | - gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
116 | |||
117 | + desc = tcg_const_i32((a->vn << 2) | a->len); | ||
118 | + def = tcg_temp_new_i64(); | ||
119 | if (a->op) { | ||
120 | - read_neon_element32(tmp, a->vd, 1, MO_32); | ||
121 | + read_neon_element64(def, a->vd, 0, MO_64); | ||
122 | } else { | ||
123 | - tcg_gen_movi_i32(tmp, 0); | ||
124 | + tcg_gen_movi_i64(def, 0); | ||
125 | } | ||
126 | - tmp3 = tcg_temp_new_i32(); | ||
127 | - read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
128 | - gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
129 | - tcg_temp_free_i32(tmp); | ||
130 | - tcg_temp_free_i32(tmp4); | ||
131 | - tcg_temp_free_ptr(ptr1); | ||
132 | + val = tcg_temp_new_i64(); | ||
133 | + read_neon_element64(val, a->vm, 0, MO_64); | ||
134 | |||
135 | - write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
136 | - write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
137 | - tcg_temp_free_i32(tmp2); | ||
138 | - tcg_temp_free_i32(tmp3); | ||
139 | + gen_helper_neon_tbl(val, cpu_env, desc, val, def); | ||
140 | + write_neon_element64(val, a->vd, 0, MO_64); | ||
141 | + | ||
142 | + tcg_temp_free_i64(def); | ||
143 | + tcg_temp_free_i64(val); | ||
144 | + tcg_temp_free_i32(desc); | ||
145 | return true; | 45 | return true; |
146 | } | 46 | } |
147 | 47 | ||
48 | -static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) | ||
49 | +static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a) | ||
50 | +{ | ||
51 | + return do_vfm_sp(s, a, false, false); | ||
52 | +} | ||
53 | + | ||
54 | +static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a) | ||
55 | +{ | ||
56 | + return do_vfm_sp(s, a, true, false); | ||
57 | +} | ||
58 | + | ||
59 | +static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a) | ||
60 | +{ | ||
61 | + return do_vfm_sp(s, a, false, true); | ||
62 | +} | ||
63 | + | ||
64 | +static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a) | ||
65 | +{ | ||
66 | + return do_vfm_sp(s, a, true, true); | ||
67 | +} | ||
68 | + | ||
69 | +static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) | ||
70 | { | ||
71 | /* | ||
72 | * VFNMA : fd = muladd(-fd, fn, fm) | ||
73 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) | ||
74 | |||
75 | neon_load_reg64(vn, a->vn); | ||
76 | neon_load_reg64(vm, a->vm); | ||
77 | - if (a->o2) { | ||
78 | + if (neg_n) { | ||
79 | /* VFNMS, VFMS */ | ||
80 | gen_helper_vfp_negd(vn, vn); | ||
81 | } | ||
82 | neon_load_reg64(vd, a->vd); | ||
83 | - if (a->o1 & 1) { | ||
84 | + if (neg_d) { | ||
85 | /* VFNMA, VFNMS */ | ||
86 | gen_helper_vfp_negd(vd, vd); | ||
87 | } | ||
88 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) | ||
89 | return true; | ||
90 | } | ||
91 | |||
92 | +static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a) | ||
93 | +{ | ||
94 | + return do_vfm_dp(s, a, false, false); | ||
95 | +} | ||
96 | + | ||
97 | +static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a) | ||
98 | +{ | ||
99 | + return do_vfm_dp(s, a, true, false); | ||
100 | +} | ||
101 | + | ||
102 | +static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a) | ||
103 | +{ | ||
104 | + return do_vfm_dp(s, a, false, true); | ||
105 | +} | ||
106 | + | ||
107 | +static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a) | ||
108 | +{ | ||
109 | + return do_vfm_dp(s, a, true, true); | ||
110 | +} | ||
111 | + | ||
112 | static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
113 | { | ||
114 | uint32_t delta_d = 0; | ||
115 | diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode | ||
116 | index XXXXXXX..XXXXXXX 100644 | ||
117 | --- a/target/arm/vfp.decode | ||
118 | +++ b/target/arm/vfp.decode | ||
119 | @@ -XXX,XX +XXX,XX @@ VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d | ||
120 | VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s | ||
121 | VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
122 | |||
123 | -VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ | ||
124 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1 | ||
125 | -VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \ | ||
126 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=1 | ||
127 | -VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \ | ||
128 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=2 | ||
129 | -VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \ | ||
130 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2 | ||
131 | +VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s | ||
132 | +VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s | ||
133 | +VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s | ||
134 | +VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s | ||
135 | + | ||
136 | +VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
137 | +VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d | ||
138 | +VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
139 | +VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d | ||
140 | |||
141 | VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ | ||
142 | vd=%vd_sp imm=%vmov_imm | ||
148 | -- | 143 | -- |
149 | 2.20.1 | 144 | 2.20.1 |
150 | 145 | ||
151 | 146 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic | 3 | Passing the raw op field from the manual is less instructive |
4 | OMAP2 chip support") takes care of creating the 3 UARTs. | 4 | than it might be. Do the full decode and use the existing |
5 | helpers to perform the expansion. | ||
5 | 6 | ||
6 | Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+ | 7 | Since these are v8 insns, VECLEN+VECSTRIDE are already RES0. |
7 | extensions and attach to n8x0's UART") added n8x0_uart_setup() | ||
8 | which create the UART and connects it to an IRQ output, | ||
9 | overwritting the existing peripheral and its IRQ connection. | ||
10 | This is incorrect. | ||
11 | 8 | ||
12 | Fortunately we don't need to fix this, because commit 6da68df7f9b | ||
13 | ("hw/arm/nseries: Replace the bluetooth chardev with a "null" | ||
14 | chardev") removed the use of this peripheral. We can simply | ||
15 | remove the code. | ||
16 | |||
17 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
18 | Message-id: 20201107193403.436146-4-f4bug@amsat.org | ||
19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20200224222232.13807-18-richard.henderson@linaro.org | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | --- | 13 | --- |
22 | hw/arm/nseries.c | 11 ----------- | 14 | target/arm/translate-vfp.inc.c | 109 +++++++++++---------------------- |
23 | 1 file changed, 11 deletions(-) | 15 | target/arm/vfp-uncond.decode | 12 ++-- |
16 | 2 files changed, 44 insertions(+), 77 deletions(-) | ||
24 | 17 | ||
25 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | 18 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c |
26 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/hw/arm/nseries.c | 20 | --- a/target/arm/translate-vfp.inc.c |
28 | +++ b/hw/arm/nseries.c | 21 | +++ b/target/arm/translate-vfp.inc.c |
29 | @@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s) | 22 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) |
30 | cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); | 23 | return true; |
31 | } | 24 | } |
32 | 25 | ||
33 | -static void n8x0_uart_setup(struct n800_s *s) | 26 | -static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) |
34 | -{ | 27 | -{ |
35 | - Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL); | 28 | - uint32_t rd, rn, rm; |
36 | - /* | 29 | - bool dp = a->dp; |
37 | - * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO | 30 | - bool vmin = a->op; |
38 | - * here, but this code has been removed with the bluetooth backend. | 31 | - TCGv_ptr fpst; |
39 | - */ | 32 | - |
40 | - omap_uart_attach(s->mpu->uart[BT_UART], radio); | 33 | - if (!dc_isar_feature(aa32_vminmaxnm, s)) { |
34 | - return false; | ||
35 | - } | ||
36 | - | ||
37 | - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { | ||
38 | - return false; | ||
39 | - } | ||
40 | - | ||
41 | - /* UNDEF accesses to D16-D31 if they don't exist */ | ||
42 | - if (dp && !dc_isar_feature(aa32_simd_r32, s) && | ||
43 | - ((a->vm | a->vn | a->vd) & 0x10)) { | ||
44 | - return false; | ||
45 | - } | ||
46 | - | ||
47 | - rd = a->vd; | ||
48 | - rn = a->vn; | ||
49 | - rm = a->vm; | ||
50 | - | ||
51 | - if (!vfp_access_check(s)) { | ||
52 | - return true; | ||
53 | - } | ||
54 | - | ||
55 | - fpst = get_fpstatus_ptr(0); | ||
56 | - | ||
57 | - if (dp) { | ||
58 | - TCGv_i64 frn, frm, dest; | ||
59 | - | ||
60 | - frn = tcg_temp_new_i64(); | ||
61 | - frm = tcg_temp_new_i64(); | ||
62 | - dest = tcg_temp_new_i64(); | ||
63 | - | ||
64 | - neon_load_reg64(frn, rn); | ||
65 | - neon_load_reg64(frm, rm); | ||
66 | - if (vmin) { | ||
67 | - gen_helper_vfp_minnumd(dest, frn, frm, fpst); | ||
68 | - } else { | ||
69 | - gen_helper_vfp_maxnumd(dest, frn, frm, fpst); | ||
70 | - } | ||
71 | - neon_store_reg64(dest, rd); | ||
72 | - tcg_temp_free_i64(frn); | ||
73 | - tcg_temp_free_i64(frm); | ||
74 | - tcg_temp_free_i64(dest); | ||
75 | - } else { | ||
76 | - TCGv_i32 frn, frm, dest; | ||
77 | - | ||
78 | - frn = tcg_temp_new_i32(); | ||
79 | - frm = tcg_temp_new_i32(); | ||
80 | - dest = tcg_temp_new_i32(); | ||
81 | - | ||
82 | - neon_load_reg32(frn, rn); | ||
83 | - neon_load_reg32(frm, rm); | ||
84 | - if (vmin) { | ||
85 | - gen_helper_vfp_minnums(dest, frn, frm, fpst); | ||
86 | - } else { | ||
87 | - gen_helper_vfp_maxnums(dest, frn, frm, fpst); | ||
88 | - } | ||
89 | - neon_store_reg32(dest, rd); | ||
90 | - tcg_temp_free_i32(frn); | ||
91 | - tcg_temp_free_i32(frm); | ||
92 | - tcg_temp_free_i32(dest); | ||
93 | - } | ||
94 | - | ||
95 | - tcg_temp_free_ptr(fpst); | ||
96 | - return true; | ||
41 | -} | 97 | -} |
42 | - | 98 | - |
43 | static void n8x0_usb_setup(struct n800_s *s) | 99 | /* |
100 | * Table for converting the most common AArch32 encoding of | ||
101 | * rounding mode to arm_fprounding order (which matches the | ||
102 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a) | ||
103 | return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false); | ||
104 | } | ||
105 | |||
106 | +static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a) | ||
107 | +{ | ||
108 | + if (!dc_isar_feature(aa32_vminmaxnm, s)) { | ||
109 | + return false; | ||
110 | + } | ||
111 | + return do_vfp_3op_sp(s, gen_helper_vfp_minnums, | ||
112 | + a->vd, a->vn, a->vm, false); | ||
113 | +} | ||
114 | + | ||
115 | +static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a) | ||
116 | +{ | ||
117 | + if (!dc_isar_feature(aa32_vminmaxnm, s)) { | ||
118 | + return false; | ||
119 | + } | ||
120 | + return do_vfp_3op_sp(s, gen_helper_vfp_maxnums, | ||
121 | + a->vd, a->vn, a->vm, false); | ||
122 | +} | ||
123 | + | ||
124 | +static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a) | ||
125 | +{ | ||
126 | + if (!dc_isar_feature(aa32_vminmaxnm, s)) { | ||
127 | + return false; | ||
128 | + } | ||
129 | + return do_vfp_3op_dp(s, gen_helper_vfp_minnumd, | ||
130 | + a->vd, a->vn, a->vm, false); | ||
131 | +} | ||
132 | + | ||
133 | +static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a) | ||
134 | +{ | ||
135 | + if (!dc_isar_feature(aa32_vminmaxnm, s)) { | ||
136 | + return false; | ||
137 | + } | ||
138 | + return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd, | ||
139 | + a->vd, a->vn, a->vm, false); | ||
140 | +} | ||
141 | + | ||
142 | static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | ||
44 | { | 143 | { |
45 | SysBusDevice *dev; | 144 | /* |
46 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | 145 | diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode |
47 | n8x0_spi_setup(s); | 146 | index XXXXXXX..XXXXXXX 100644 |
48 | n8x0_dss_setup(s); | 147 | --- a/target/arm/vfp-uncond.decode |
49 | n8x0_cbus_setup(s); | 148 | +++ b/target/arm/vfp-uncond.decode |
50 | - n8x0_uart_setup(s); | 149 | @@ -XXX,XX +XXX,XX @@ |
51 | if (machine_usb(machine)) { | 150 | %vd_dp 22:1 12:4 |
52 | n8x0_usb_setup(s); | 151 | %vd_sp 12:4 22:1 |
53 | } | 152 | |
153 | +@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp | ||
154 | +@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
155 | + | ||
156 | VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ | ||
157 | vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0 | ||
158 | VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ | ||
159 | vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1 | ||
160 | |||
161 | -VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ | ||
162 | - vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0 | ||
163 | -VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \ | ||
164 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1 | ||
165 | +VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s | ||
166 | +VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s | ||
167 | + | ||
168 | +VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d | ||
169 | +VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d | ||
170 | |||
171 | VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ | ||
172 | vm=%vm_sp vd=%vd_sp dp=0 | ||
54 | -- | 173 | -- |
55 | 2.20.1 | 174 | 2.20.1 |
56 | 175 | ||
57 | 176 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Guenter Roeck <linux@roeck-us.net> | ||
1 | 2 | ||
3 | USB ports on Xilinx Zync must be instantiated as TYPE_CHIPIDEA to work. | ||
4 | Linux expects and checks various chipidea registers, which do not exist | ||
5 | with the basic ehci emulation. This patch series fixes the problem. | ||
6 | |||
7 | Without this patch, USB ports fail to instantiate under Linux. | ||
8 | |||
9 | ci_hdrc ci_hdrc.0: doesn't support host | ||
10 | ci_hdrc ci_hdrc.0: no supported roles | ||
11 | |||
12 | With this patch, USB ports are instantiated, and it is possible | ||
13 | to boot from USB drive. | ||
14 | |||
15 | ci_hdrc ci_hdrc.0: EHCI Host Controller | ||
16 | ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1 | ||
17 | ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00 | ||
18 | usb 1-1: new full-speed USB device number 2 using ci_hdrc | ||
19 | usb 1-1: not running at top speed; connect to a high speed hub | ||
20 | usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x81 has invalid maxpacket 512, setting to 64 | ||
21 | usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x2 has invalid maxpacket 512, setting to 64 | ||
22 | usb-storage 1-1:1.0: USB Mass Storage device detected | ||
23 | scsi host0: usb-storage 1-1:1.0 | ||
24 | |||
25 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
26 | Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> | ||
27 | Message-id: 20200215122354.13706-2-linux@roeck-us.net | ||
28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
29 | --- | ||
30 | hw/arm/xilinx_zynq.c | 5 +++-- | ||
31 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
32 | |||
33 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/hw/arm/xilinx_zynq.c | ||
36 | +++ b/hw/arm/xilinx_zynq.c | ||
37 | @@ -XXX,XX +XXX,XX @@ | ||
38 | #include "hw/loader.h" | ||
39 | #include "hw/misc/zynq-xadc.h" | ||
40 | #include "hw/ssi/ssi.h" | ||
41 | +#include "hw/usb/chipidea.h" | ||
42 | #include "qemu/error-report.h" | ||
43 | #include "hw/sd/sdhci.h" | ||
44 | #include "hw/char/cadence_uart.h" | ||
45 | @@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine) | ||
46 | zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); | ||
47 | zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); | ||
48 | |||
49 | - sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); | ||
50 | - sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); | ||
51 | + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); | ||
52 | + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); | ||
53 | |||
54 | cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); | ||
55 | cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); | ||
56 | -- | ||
57 | 2.20.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Guenter Roeck <linux@roeck-us.net> | ||
1 | 2 | ||
3 | Xilinx USB devices are now instantiated through TYPE_CHIPIDEA, | ||
4 | and xlnx support in the EHCI code is no longer needed. | ||
5 | |||
6 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
7 | Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> | ||
8 | Message-id: 20200215122354.13706-3-linux@roeck-us.net | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | hw/usb/hcd-ehci-sysbus.c | 17 ----------------- | ||
12 | 1 file changed, 17 deletions(-) | ||
13 | |||
14 | diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/usb/hcd-ehci-sysbus.c | ||
17 | +++ b/hw/usb/hcd-ehci-sysbus.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo ehci_platform_type_info = { | ||
19 | .class_init = ehci_platform_class_init, | ||
20 | }; | ||
21 | |||
22 | -static void ehci_xlnx_class_init(ObjectClass *oc, void *data) | ||
23 | -{ | ||
24 | - SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); | ||
25 | - DeviceClass *dc = DEVICE_CLASS(oc); | ||
26 | - | ||
27 | - set_bit(DEVICE_CATEGORY_USB, dc->categories); | ||
28 | - sec->capsbase = 0x100; | ||
29 | - sec->opregbase = 0x140; | ||
30 | -} | ||
31 | - | ||
32 | -static const TypeInfo ehci_xlnx_type_info = { | ||
33 | - .name = "xlnx,ps7-usb", | ||
34 | - .parent = TYPE_SYS_BUS_EHCI, | ||
35 | - .class_init = ehci_xlnx_class_init, | ||
36 | -}; | ||
37 | - | ||
38 | static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) | ||
39 | { | ||
40 | SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc); | ||
41 | @@ -XXX,XX +XXX,XX @@ static void ehci_sysbus_register_types(void) | ||
42 | { | ||
43 | type_register_static(&ehci_type_info); | ||
44 | type_register_static(&ehci_platform_type_info); | ||
45 | - type_register_static(&ehci_xlnx_type_info); | ||
46 | type_register_static(&ehci_exynos4210_type_info); | ||
47 | type_register_static(&ehci_tegra2_type_info); | ||
48 | type_register_static(&ehci_ppc4xx_type_info); | ||
49 | -- | ||
50 | 2.20.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Thomas Huth <thuth@redhat.com> | ||
1 | 2 | ||
3 | Old kernels from the Meego project can be used to check that Linux | ||
4 | is at least starting on these machines. | ||
5 | |||
6 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
7 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
10 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Message-id: 20200225172501.29609-2-philmd@redhat.com | ||
12 | Message-Id: <20200129131920.22302-1-thuth@redhat.com> | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | MAINTAINERS | 1 + | ||
17 | tests/acceptance/machine_arm_n8x0.py | 49 ++++++++++++++++++++++++++++ | ||
18 | 2 files changed, 50 insertions(+) | ||
19 | create mode 100644 tests/acceptance/machine_arm_n8x0.py | ||
20 | |||
21 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/MAINTAINERS | ||
24 | +++ b/MAINTAINERS | ||
25 | @@ -XXX,XX +XXX,XX @@ F: hw/rtc/twl92230.c | ||
26 | F: include/hw/display/blizzard.h | ||
27 | F: include/hw/input/tsc2xxx.h | ||
28 | F: include/hw/misc/cbus.h | ||
29 | +F: tests/acceptance/machine_arm_n8x0.py | ||
30 | |||
31 | Palm | ||
32 | M: Andrzej Zaborowski <balrogg@gmail.com> | ||
33 | diff --git a/tests/acceptance/machine_arm_n8x0.py b/tests/acceptance/machine_arm_n8x0.py | ||
34 | new file mode 100644 | ||
35 | index XXXXXXX..XXXXXXX | ||
36 | --- /dev/null | ||
37 | +++ b/tests/acceptance/machine_arm_n8x0.py | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | +# Functional test that boots a Linux kernel and checks the console | ||
40 | +# | ||
41 | +# Copyright (c) 2020 Red Hat, Inc. | ||
42 | +# | ||
43 | +# Author: | ||
44 | +# Thomas Huth <thuth@redhat.com> | ||
45 | +# | ||
46 | +# This work is licensed under the terms of the GNU GPL, version 2 or | ||
47 | +# later. See the COPYING file in the top-level directory. | ||
48 | + | ||
49 | +import os | ||
50 | + | ||
51 | +from avocado import skipUnless | ||
52 | +from avocado_qemu import Test | ||
53 | +from avocado_qemu import wait_for_console_pattern | ||
54 | + | ||
55 | +class N8x0Machine(Test): | ||
56 | + """Boots the Linux kernel and checks that the console is operational""" | ||
57 | + | ||
58 | + timeout = 90 | ||
59 | + | ||
60 | + def __do_test_n8x0(self): | ||
61 | + kernel_url = ('http://stskeeps.subnetmask.net/meego-n8x0/' | ||
62 | + 'meego-arm-n8x0-1.0.80.20100712.1431-' | ||
63 | + 'vmlinuz-2.6.35~rc4-129.1-n8x0') | ||
64 | + kernel_hash = 'e9d5ab8d7548923a0061b6fbf601465e479ed269' | ||
65 | + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) | ||
66 | + | ||
67 | + self.vm.set_console(console_index=1) | ||
68 | + self.vm.add_args('-kernel', kernel_path, | ||
69 | + '-append', 'printk.time=0 console=ttyS1') | ||
70 | + self.vm.launch() | ||
71 | + wait_for_console_pattern(self, 'TSC2005 driver initializing') | ||
72 | + | ||
73 | + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') | ||
74 | + def test_n800(self): | ||
75 | + """ | ||
76 | + :avocado: tags=arch:arm | ||
77 | + :avocado: tags=machine:n800 | ||
78 | + """ | ||
79 | + self.__do_test_n8x0() | ||
80 | + | ||
81 | + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') | ||
82 | + def test_n810(self): | ||
83 | + """ | ||
84 | + :avocado: tags=arch:arm | ||
85 | + :avocado: tags=machine:n810 | ||
86 | + """ | ||
87 | + self.__do_test_n8x0() | ||
88 | -- | ||
89 | 2.20.1 | ||
90 | |||
91 | diff view generated by jsdifflib |
1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | From: Thomas Huth <thuth@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | We should at least document what this machine is about. | 3 | There is a kernel and initrd available on github which we can use |
4 | for testing this machine. | ||
4 | 5 | ||
5 | Reviewed-by: Graeme Gregory <graeme@nuviainc.com> | 6 | Signed-off-by: Thomas Huth <thuth@redhat.com> |
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
7 | Message-id: 20201104165254.24822-1-alex.bennee@linaro.org | 8 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
8 | Cc: Leif Lindholm <leif@nuviainc.com> | 9 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> |
9 | Cc: Shashi Mallela <shashi.mallela@linaro.org> | 10 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 11 | Message-id: 20200225172501.29609-3-philmd@redhat.com |
11 | [PMM: fixed filename mismatch] | 12 | Message-Id: <20200131170233.14584-1-thuth@redhat.com> |
13 | [PMD: Renamed test method, moved description from class to method] | ||
14 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 16 | --- |
14 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++ | 17 | MAINTAINERS | 1 + |
15 | docs/system/target-arm.rst | 1 + | 18 | tests/acceptance/machine_arm_integratorcp.py | 43 ++++++++++++++++++++ |
16 | 2 files changed, 33 insertions(+) | 19 | 2 files changed, 44 insertions(+) |
17 | create mode 100644 docs/system/arm/sbsa.rst | 20 | create mode 100644 tests/acceptance/machine_arm_integratorcp.py |
18 | 21 | ||
19 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst | 22 | diff --git a/MAINTAINERS b/MAINTAINERS |
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/MAINTAINERS | ||
25 | +++ b/MAINTAINERS | ||
26 | @@ -XXX,XX +XXX,XX @@ S: Maintained | ||
27 | F: hw/arm/integratorcp.c | ||
28 | F: hw/misc/arm_integrator_debug.c | ||
29 | F: include/hw/misc/arm_integrator_debug.h | ||
30 | +F: tests/acceptance/machine_arm_integratorcp.py | ||
31 | |||
32 | MCIMX6UL EVK / i.MX6ul | ||
33 | M: Peter Maydell <peter.maydell@linaro.org> | ||
34 | diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py | ||
20 | new file mode 100644 | 35 | new file mode 100644 |
21 | index XXXXXXX..XXXXXXX | 36 | index XXXXXXX..XXXXXXX |
22 | --- /dev/null | 37 | --- /dev/null |
23 | +++ b/docs/system/arm/sbsa.rst | 38 | +++ b/tests/acceptance/machine_arm_integratorcp.py |
24 | @@ -XXX,XX +XXX,XX @@ | 39 | @@ -XXX,XX +XXX,XX @@ |
25 | +Arm Server Base System Architecture Reference board (``sbsa-ref``) | 40 | +# Functional test that boots a Linux kernel and checks the console |
26 | +================================================================== | 41 | +# |
42 | +# Copyright (c) 2020 Red Hat, Inc. | ||
43 | +# | ||
44 | +# Author: | ||
45 | +# Thomas Huth <thuth@redhat.com> | ||
46 | +# | ||
47 | +# This work is licensed under the terms of the GNU GPL, version 2 or | ||
48 | +# later. See the COPYING file in the top-level directory. | ||
27 | + | 49 | + |
28 | +While the `virt` board is a generic board platform that doesn't match | 50 | +import os |
29 | +any real hardware the `sbsa-ref` board intends to look like real | ||
30 | +hardware. The `Server Base System Architecture | ||
31 | +<https://developer.arm.com/documentation/den0029/latest>` defines a | ||
32 | +minimum base line of hardware support and importantly how the firmware | ||
33 | +reports that to any operating system. It is a static system that | ||
34 | +reports a very minimal DT to the firmware for non-discoverable | ||
35 | +information about components affected by the qemu command line (i.e. | ||
36 | +cpus and memory). As a result it must have a firmware specifically | ||
37 | +built to expect a certain hardware layout (as you would in a real | ||
38 | +machine). | ||
39 | + | 51 | + |
40 | +It is intended to be a machine for developing firmware and testing | 52 | +from avocado import skipUnless |
41 | +standards compliance with operating systems. | 53 | +from avocado_qemu import Test |
54 | +from avocado_qemu import wait_for_console_pattern | ||
42 | + | 55 | + |
43 | +Supported devices | 56 | +class IntegratorMachine(Test): |
44 | +""""""""""""""""" | ||
45 | + | 57 | + |
46 | +The sbsa-ref board supports: | 58 | + timeout = 90 |
47 | + | 59 | + |
48 | + - A configurable number of AArch64 CPUs | 60 | + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') |
49 | + - GIC version 3 | 61 | + def test_integratorcp_console(self): |
50 | + - System bus AHCI controller | 62 | + """ |
51 | + - System bus EHCI controller | 63 | + Boots the Linux kernel and checks that the console is operational |
52 | + - CDROM and hard disc on AHCI bus | 64 | + :avocado: tags=arch:arm |
53 | + - E1000E ethernet card on PCIe bus | 65 | + :avocado: tags=machine:integratorcp |
54 | + - VGA display adaptor on PCIe bus | 66 | + """ |
55 | + - A generic SBSA watchdog device | 67 | + kernel_url = ('https://github.com/zayac/qemu-arm/raw/master/' |
68 | + 'arm-test/kernel/zImage.integrator') | ||
69 | + kernel_hash = '0d7adba893c503267c946a3cbdc63b4b54f25468' | ||
70 | + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) | ||
56 | + | 71 | + |
57 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | 72 | + initrd_url = ('https://github.com/zayac/qemu-arm/raw/master/' |
58 | index XXXXXXX..XXXXXXX 100644 | 73 | + 'arm-test/kernel/arm_root.img') |
59 | --- a/docs/system/target-arm.rst | 74 | + initrd_hash = 'b51e4154285bf784e017a37586428332d8c7bd8b' |
60 | +++ b/docs/system/target-arm.rst | 75 | + initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash) |
61 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 76 | + |
62 | arm/mps2 | 77 | + self.vm.set_console() |
63 | arm/musca | 78 | + self.vm.add_args('-kernel', kernel_path, |
64 | arm/realview | 79 | + '-initrd', initrd_path, |
65 | + arm/sbsa | 80 | + '-append', 'printk.time=0 console=ttyAMA0') |
66 | arm/versatile | 81 | + self.vm.launch() |
67 | arm/vexpress | 82 | + wait_for_console_pattern(self, 'Log in as root') |
68 | arm/aspeed | ||
69 | -- | 83 | -- |
70 | 2.20.1 | 84 | 2.20.1 |
71 | 85 | ||
72 | 86 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | We can use one MPC per SRAM bank, but we currently only wire the | 3 | As we want to re-use this code, extract it as a new function. |
4 | IRQ from the first expansion MPC to the IRQ splitter. Fix that. | 4 | Since we are using the PL011 serial console, add a Avocado tag |
5 | to ease filtering of tests. | ||
5 | 6 | ||
6 | Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines") | 7 | Reviewed-by: Thomas Huth <thuth@redhat.com> |
8 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Message-id: 20201107193403.436146-2-f4bug@amsat.org | 10 | Message-id: 20200225172501.29609-4-philmd@redhat.com |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | hw/arm/armsse.c | 3 ++- | 13 | tests/acceptance/machine_arm_integratorcp.py | 18 +++++++++++------- |
13 | 1 file changed, 2 insertions(+), 1 deletion(-) | 14 | 1 file changed, 11 insertions(+), 7 deletions(-) |
14 | 15 | ||
15 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | 16 | diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/armsse.c | 18 | --- a/tests/acceptance/machine_arm_integratorcp.py |
18 | +++ b/hw/arm/armsse.c | 19 | +++ b/tests/acceptance/machine_arm_integratorcp.py |
19 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | 20 | @@ -XXX,XX +XXX,XX @@ class IntegratorMachine(Test): |
20 | qdev_get_gpio_in(dev_splitter, 0)); | 21 | |
21 | qdev_connect_gpio_out(dev_splitter, 0, | 22 | timeout = 90 |
22 | qdev_get_gpio_in_named(dev_secctl, | 23 | |
23 | - "mpc_status", 0)); | 24 | - @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') |
24 | + "mpc_status", | 25 | - def test_integratorcp_console(self): |
25 | + i - IOTS_NUM_EXP_MPC)); | 26 | - """ |
26 | } | 27 | - Boots the Linux kernel and checks that the console is operational |
27 | 28 | - :avocado: tags=arch:arm | |
28 | qdev_connect_gpio_out(dev_splitter, 1, | 29 | - :avocado: tags=machine:integratorcp |
30 | - """ | ||
31 | + def boot_integratorcp(self): | ||
32 | kernel_url = ('https://github.com/zayac/qemu-arm/raw/master/' | ||
33 | 'arm-test/kernel/zImage.integrator') | ||
34 | kernel_hash = '0d7adba893c503267c946a3cbdc63b4b54f25468' | ||
35 | @@ -XXX,XX +XXX,XX @@ class IntegratorMachine(Test): | ||
36 | '-initrd', initrd_path, | ||
37 | '-append', 'printk.time=0 console=ttyAMA0') | ||
38 | self.vm.launch() | ||
39 | + | ||
40 | + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') | ||
41 | + def test_integratorcp_console(self): | ||
42 | + """ | ||
43 | + Boots the Linux kernel and checks that the console is operational | ||
44 | + :avocado: tags=arch:arm | ||
45 | + :avocado: tags=machine:integratorcp | ||
46 | + :avocado: tags=device:pl011 | ||
47 | + """ | ||
48 | + self.boot_integratorcp() | ||
49 | wait_for_console_pattern(self, 'Log in as root') | ||
29 | -- | 50 | -- |
30 | 2.20.1 | 51 | 2.20.1 |
31 | 52 | ||
32 | 53 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | We don't need to fill the full pic[] array if we only use | 3 | Add a test that verifies the Tux logo is displayed on the framebuffer. |
4 | few of the interrupt lines. Directly call qdev_get_gpio_in() | 4 | |
5 | when necessary. | 5 | We simply follow the OpenCV "Template Matching with Multiple Objects" |
6 | tutorial, replacing Lionel Messi by Tux: | ||
7 | https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html | ||
8 | |||
9 | When OpenCV and NumPy are installed, this test can be run using: | ||
10 | |||
11 | $ AVOCADO_ALLOW_UNTRUSTED_CODE=hmmm \ | ||
12 | avocado --show=app,framebuffer run -t device:framebuffer \ | ||
13 | tests/acceptance/machine_arm_integratorcp.py | ||
14 | JOB ID : 8c46b0f8269242e87d738247883ea2a470df949e | ||
15 | JOB LOG : avocado/job-results/job-2020-01-31T21.38-8c46b0f/job.log | ||
16 | (1/1) tests/acceptance/machine_arm_integratorcp.py:IntegratorMachine.test_framebuffer_tux_logo: | ||
17 | framebuffer: found Tux at position [x, y] = (0, 0) | ||
18 | PASS (3.96 s) | ||
19 | RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 | ||
20 | JOB TIME : 4.23 s | ||
6 | 21 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 22 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Message-id: 20201107193403.436146-6-f4bug@amsat.org | 23 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Message-id: 20200225172501.29609-5-philmd@redhat.com |
25 | Message-Id: <20200131211102.29612-3-f4bug@amsat.org> | ||
26 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 28 | --- |
12 | hw/arm/musicpal.c | 25 +++++++++++++------------ | 29 | tests/acceptance/machine_arm_integratorcp.py | 52 ++++++++++++++++++++ |
13 | 1 file changed, 13 insertions(+), 12 deletions(-) | 30 | 1 file changed, 52 insertions(+) |
14 | 31 | ||
15 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | 32 | diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py |
16 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/musicpal.c | 34 | --- a/tests/acceptance/machine_arm_integratorcp.py |
18 | +++ b/hw/arm/musicpal.c | 35 | +++ b/tests/acceptance/machine_arm_integratorcp.py |
19 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = { | 36 | @@ -XXX,XX +XXX,XX @@ |
20 | static void musicpal_init(MachineState *machine) | 37 | # later. See the COPYING file in the top-level directory. |
21 | { | 38 | |
22 | ARMCPU *cpu; | 39 | import os |
23 | - qemu_irq pic[32]; | 40 | +import logging |
24 | DeviceState *dev; | 41 | |
25 | + DeviceState *pic; | 42 | from avocado import skipUnless |
26 | DeviceState *uart_orgate; | 43 | from avocado_qemu import Test |
27 | DeviceState *i2c_dev; | 44 | from avocado_qemu import wait_for_console_pattern |
28 | DeviceState *lcd_dev; | 45 | |
29 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | 46 | + |
30 | &error_fatal); | 47 | +NUMPY_AVAILABLE = True |
31 | memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); | 48 | +try: |
32 | 49 | + import numpy as np | |
33 | - dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, | 50 | +except ImportError: |
34 | + pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, | 51 | + NUMPY_AVAILABLE = False |
35 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); | 52 | + |
36 | - for (i = 0; i < 32; i++) { | 53 | +CV2_AVAILABLE = True |
37 | - pic[i] = qdev_get_gpio_in(dev, i); | 54 | +try: |
38 | - } | 55 | + import cv2 |
39 | - sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], | 56 | +except ImportError: |
40 | - pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | 57 | + CV2_AVAILABLE = False |
41 | - pic[MP_TIMER4_IRQ], NULL); | 58 | + |
42 | + sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, | 59 | + |
43 | + qdev_get_gpio_in(pic, MP_TIMER1_IRQ), | 60 | class IntegratorMachine(Test): |
44 | + qdev_get_gpio_in(pic, MP_TIMER2_IRQ), | 61 | |
45 | + qdev_get_gpio_in(pic, MP_TIMER3_IRQ), | 62 | timeout = 90 |
46 | + qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL); | 63 | @@ -XXX,XX +XXX,XX @@ class IntegratorMachine(Test): |
47 | 64 | """ | |
48 | /* Logically OR both UART IRQs together */ | 65 | self.boot_integratorcp() |
49 | uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | 66 | wait_for_console_pattern(self, 'Log in as root') |
50 | object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | 67 | + |
51 | qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | 68 | + @skipUnless(NUMPY_AVAILABLE, 'Python NumPy not installed') |
52 | - qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | 69 | + @skipUnless(CV2_AVAILABLE, 'Python OpenCV not installed') |
53 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, | 70 | + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') |
54 | + qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ)); | 71 | + def test_framebuffer_tux_logo(self): |
55 | 72 | + """ | |
56 | serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | 73 | + Boot Linux and verify the Tux logo is displayed on the framebuffer. |
57 | qdev_get_gpio_in(uart_orgate, 0), | 74 | + :avocado: tags=arch:arm |
58 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | 75 | + :avocado: tags=machine:integratorcp |
59 | OBJECT(get_system_memory()), &error_fatal); | 76 | + :avocado: tags=device:pl110 |
60 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | 77 | + :avocado: tags=device:framebuffer |
61 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); | 78 | + """ |
62 | - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); | 79 | + screendump_path = os.path.join(self.workdir, "screendump.pbm") |
63 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | 80 | + tuxlogo_url = ('https://github.com/torvalds/linux/raw/v2.6.12/' |
64 | + qdev_get_gpio_in(pic, MP_ETH_IRQ)); | 81 | + 'drivers/video/logo/logo_linux_vga16.ppm') |
65 | 82 | + tuxlogo_hash = '3991c2ddbd1ddaecda7601f8aafbcf5b02dc86af' | |
66 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); | 83 | + tuxlogo_path = self.fetch_asset(tuxlogo_url, asset_hash=tuxlogo_hash) |
67 | 84 | + | |
68 | sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); | 85 | + self.boot_integratorcp() |
69 | 86 | + framebuffer_ready = 'Console: switching to colour frame buffer device' | |
70 | dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, | 87 | + wait_for_console_pattern(self, framebuffer_ready) |
71 | - pic[MP_GPIO_IRQ]); | 88 | + self.vm.command('human-monitor-command', command_line='stop') |
72 | + qdev_get_gpio_in(pic, MP_GPIO_IRQ)); | 89 | + self.vm.command('human-monitor-command', |
73 | i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); | 90 | + command_line='screendump %s' % screendump_path) |
74 | i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); | 91 | + logger = logging.getLogger('framebuffer') |
75 | 92 | + | |
76 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | 93 | + cpu_count = 1 |
77 | NULL); | 94 | + match_threshold = 0.92 |
78 | sysbus_realize_and_unref(s, &error_fatal); | 95 | + screendump_bgr = cv2.imread(screendump_path) |
79 | sysbus_mmio_map(s, 0, MP_AUDIO_BASE); | 96 | + screendump_gray = cv2.cvtColor(screendump_bgr, cv2.COLOR_BGR2GRAY) |
80 | - sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); | 97 | + result = cv2.matchTemplate(screendump_gray, cv2.imread(tuxlogo_path, 0), |
81 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ)); | 98 | + cv2.TM_CCOEFF_NORMED) |
82 | 99 | + loc = np.where(result >= match_threshold) | |
83 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; | 100 | + tux_count = 0 |
84 | arm_load_kernel(cpu, machine, &musicpal_binfo); | 101 | + for tux_count, pt in enumerate(zip(*loc[::-1]), start=1): |
102 | + logger.debug('found Tux at position [x, y] = %s', pt) | ||
103 | + self.assertGreaterEqual(tux_count, cpu_count) | ||
85 | -- | 104 | -- |
86 | 2.20.1 | 105 | 2.20.1 |
87 | 106 | ||
88 | 107 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | We missed an instance of using FIELD_EX32 on a 64-bit ID | ||
2 | register, in isar_feature_aa64_pmu_8_4(). Fix it. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200224172846.13053-2-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/cpu.h | 4 ++-- | ||
10 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/cpu.h | ||
15 | +++ b/target/arm/cpu.h | ||
16 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) | ||
17 | |||
18 | static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) | ||
19 | { | ||
20 | - return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && | ||
21 | - FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; | ||
22 | + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && | ||
23 | + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; | ||
24 | } | ||
25 | |||
26 | /* | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The v8.3-RCPC extension implements three new load instructions | ||
2 | which provide slightly weaker consistency guarantees than the | ||
3 | existing load-acquire operations. For QEMU we choose to simply | ||
4 | implement them with a full LDAQ barrier. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200224172846.13053-3-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/cpu.h | 5 +++++ | ||
11 | linux-user/elfload.c | 1 + | ||
12 | target/arm/cpu64.c | 1 + | ||
13 | target/arm/translate-a64.c | 24 ++++++++++++++++++++++++ | ||
14 | 4 files changed, 31 insertions(+) | ||
15 | |||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/cpu.h | ||
19 | +++ b/target/arm/cpu.h | ||
20 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) | ||
21 | FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; | ||
22 | } | ||
23 | |||
24 | +static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) | ||
25 | +{ | ||
26 | + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; | ||
27 | +} | ||
28 | + | ||
29 | /* | ||
30 | * Feature tests for "does this exist in either 32-bit or 64-bit?" | ||
31 | */ | ||
32 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/linux-user/elfload.c | ||
35 | +++ b/linux-user/elfload.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
37 | GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); | ||
38 | GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); | ||
39 | GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); | ||
40 | + GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); | ||
41 | |||
42 | return hwcaps; | ||
43 | } | ||
44 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/cpu64.c | ||
47 | +++ b/target/arm/cpu64.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
49 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | ||
50 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | ||
51 | t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); | ||
52 | + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */ | ||
53 | cpu->isar.id_aa64isar1 = t; | ||
54 | |||
55 | t = cpu->isar.id_aa64pfr0; | ||
56 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/arm/translate-a64.c | ||
59 | +++ b/target/arm/translate-a64.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
61 | int rs = extract32(insn, 16, 5); | ||
62 | int rn = extract32(insn, 5, 5); | ||
63 | int o3_opc = extract32(insn, 12, 4); | ||
64 | + bool r = extract32(insn, 22, 1); | ||
65 | + bool a = extract32(insn, 23, 1); | ||
66 | TCGv_i64 tcg_rs, clean_addr; | ||
67 | AtomicThreeOpFn *fn; | ||
68 | |||
69 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
70 | case 010: /* SWP */ | ||
71 | fn = tcg_gen_atomic_xchg_i64; | ||
72 | break; | ||
73 | + case 014: /* LDAPR, LDAPRH, LDAPRB */ | ||
74 | + if (!dc_isar_feature(aa64_rcpc_8_3, s) || | ||
75 | + rs != 31 || a != 1 || r != 0) { | ||
76 | + unallocated_encoding(s); | ||
77 | + return; | ||
78 | + } | ||
79 | + break; | ||
80 | default: | ||
81 | unallocated_encoding(s); | ||
82 | return; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
84 | gen_check_sp_alignment(s); | ||
85 | } | ||
86 | clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
87 | + | ||
88 | + if (o3_opc == 014) { | ||
89 | + /* | ||
90 | + * LDAPR* are a special case because they are a simple load, not a | ||
91 | + * fetch-and-do-something op. | ||
92 | + * The architectural consistency requirements here are weaker than | ||
93 | + * full load-acquire (we only need "load-acquire processor consistent"), | ||
94 | + * but we choose to implement them as full LDAQ. | ||
95 | + */ | ||
96 | + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, | ||
97 | + true, rt, disas_ldst_compute_iss_sf(size, false, 0), true); | ||
98 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
99 | + return; | ||
100 | + } | ||
101 | + | ||
102 | tcg_rs = read_cpu_reg(s, rs, true); | ||
103 | |||
104 | if (o3_opc == 1) { /* LDCLR */ | ||
105 | -- | ||
106 | 2.20.1 | ||
107 | |||
108 | diff view generated by jsdifflib |
1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | 1 | The v8.4-RCPC extension implements some new instructions: |
---|---|---|---|
2 | * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW | ||
3 | * STLUR, STLURB, STLURH | ||
2 | 4 | ||
3 | Fix code style. Don't use '#' flag of printf format ('%#') in | 5 | These are all in a new subgroup of encodings that sits below the |
4 | format strings, use '0x' prefix instead | 6 | top-level "Loads and Stores" group in the Arm ARM. |
5 | 7 | ||
6 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | 8 | The STLUR* instructions have standard store-release semantics; the |
7 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | 9 | LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose |
8 | Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com | 10 | to implement them as the slightly stronger Load-Acquire. |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20200224172846.13053-4-peter.maydell@linaro.org | ||
11 | --- | 15 | --- |
12 | target/arm/translate-a64.c | 4 ++-- | 16 | target/arm/cpu.h | 5 +++ |
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 17 | linux-user/elfload.c | 1 + |
18 | target/arm/cpu64.c | 2 +- | ||
19 | target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++++ | ||
20 | 4 files changed, 97 insertions(+), 1 deletion(-) | ||
14 | 21 | ||
22 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/arm/cpu.h | ||
25 | +++ b/target/arm/cpu.h | ||
26 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) | ||
27 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; | ||
28 | } | ||
29 | |||
30 | +static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) | ||
31 | +{ | ||
32 | + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; | ||
33 | +} | ||
34 | + | ||
35 | /* | ||
36 | * Feature tests for "does this exist in either 32-bit or 64-bit?" | ||
37 | */ | ||
38 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/linux-user/elfload.c | ||
41 | +++ b/linux-user/elfload.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
43 | GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); | ||
44 | GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); | ||
45 | GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); | ||
46 | + GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); | ||
47 | |||
48 | return hwcaps; | ||
49 | } | ||
50 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/target/arm/cpu64.c | ||
53 | +++ b/target/arm/cpu64.c | ||
54 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
55 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | ||
56 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | ||
57 | t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); | ||
58 | - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */ | ||
59 | + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ | ||
60 | cpu->isar.id_aa64isar1 = t; | ||
61 | |||
62 | t = cpu->isar.id_aa64pfr0; | ||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 63 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 64 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 65 | --- a/target/arm/translate-a64.c |
18 | +++ b/target/arm/translate-a64.c | 66 | +++ b/target/arm/translate-a64.c |
19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | 67 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, |
20 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | 68 | } |
21 | break; | 69 | } |
22 | default: | 70 | |
23 | - fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", | 71 | +/* |
24 | + fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n", | 72 | + * LDAPR/STLR (unscaled immediate) |
25 | __func__, insn, fpopcode, s->pc_curr); | 73 | + * |
26 | g_assert_not_reached(); | 74 | + * 31 30 24 22 21 12 10 5 0 |
27 | } | 75 | + * +------+-------------+-----+---+--------+-----+----+-----+ |
28 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | 76 | + * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | |
29 | case 0x7f: /* FSQRT (vector) */ | 77 | + * +------+-------------+-----+---+--------+-----+----+-----+ |
78 | + * | ||
79 | + * Rt: source or destination register | ||
80 | + * Rn: base register | ||
81 | + * imm9: unscaled immediate offset | ||
82 | + * opc: 00: STLUR*, 01/10/11: various LDAPUR* | ||
83 | + * size: size of load/store | ||
84 | + */ | ||
85 | +static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) | ||
86 | +{ | ||
87 | + int rt = extract32(insn, 0, 5); | ||
88 | + int rn = extract32(insn, 5, 5); | ||
89 | + int offset = sextract32(insn, 12, 9); | ||
90 | + int opc = extract32(insn, 22, 2); | ||
91 | + int size = extract32(insn, 30, 2); | ||
92 | + TCGv_i64 clean_addr, dirty_addr; | ||
93 | + bool is_store = false; | ||
94 | + bool is_signed = false; | ||
95 | + bool extend = false; | ||
96 | + bool iss_sf; | ||
97 | + | ||
98 | + if (!dc_isar_feature(aa64_rcpc_8_4, s)) { | ||
99 | + unallocated_encoding(s); | ||
100 | + return; | ||
101 | + } | ||
102 | + | ||
103 | + switch (opc) { | ||
104 | + case 0: /* STLURB */ | ||
105 | + is_store = true; | ||
106 | + break; | ||
107 | + case 1: /* LDAPUR* */ | ||
108 | + break; | ||
109 | + case 2: /* LDAPURS* 64-bit variant */ | ||
110 | + if (size == 3) { | ||
111 | + unallocated_encoding(s); | ||
112 | + return; | ||
113 | + } | ||
114 | + is_signed = true; | ||
115 | + break; | ||
116 | + case 3: /* LDAPURS* 32-bit variant */ | ||
117 | + if (size > 1) { | ||
118 | + unallocated_encoding(s); | ||
119 | + return; | ||
120 | + } | ||
121 | + is_signed = true; | ||
122 | + extend = true; /* zero-extend 32->64 after signed load */ | ||
123 | + break; | ||
124 | + default: | ||
125 | + g_assert_not_reached(); | ||
126 | + } | ||
127 | + | ||
128 | + iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
129 | + | ||
130 | + if (rn == 31) { | ||
131 | + gen_check_sp_alignment(s); | ||
132 | + } | ||
133 | + | ||
134 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
135 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
136 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
137 | + | ||
138 | + if (is_store) { | ||
139 | + /* Store-Release semantics */ | ||
140 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
141 | + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true); | ||
142 | + } else { | ||
143 | + /* | ||
144 | + * Load-AcquirePC semantics; we implement as the slightly more | ||
145 | + * restrictive Load-Acquire. | ||
146 | + */ | ||
147 | + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, | ||
148 | + true, rt, iss_sf, true); | ||
149 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
150 | + } | ||
151 | +} | ||
152 | + | ||
153 | /* Load/store register (all forms) */ | ||
154 | static void disas_ldst_reg(DisasContext *s, uint32_t insn) | ||
155 | { | ||
156 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst(DisasContext *s, uint32_t insn) | ||
157 | case 0x0d: /* AdvSIMD load/store single structure */ | ||
158 | disas_ldst_single_struct(s, insn); | ||
30 | break; | 159 | break; |
160 | + case 0x19: /* LDAPR/STLR (unscaled immediate) */ | ||
161 | + if (extract32(insn, 10, 2) != 0 || | ||
162 | + extract32(insn, 21, 1) != 0) { | ||
163 | + unallocated_encoding(s); | ||
164 | + break; | ||
165 | + } | ||
166 | + disas_ldst_ldapr_stlr(s, insn); | ||
167 | + break; | ||
31 | default: | 168 | default: |
32 | - fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); | 169 | unallocated_encoding(s); |
33 | + fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop); | 170 | break; |
34 | g_assert_not_reached(); | ||
35 | } | ||
36 | |||
37 | -- | 171 | -- |
38 | 2.20.1 | 172 | 2.20.1 |
39 | 173 | ||
40 | 174 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers | ||
2 | have a format that uses the full 64 bit width of the register, and | ||
3 | adds a new CCSIDR2 register so AArch32 can get at the high 32 bits. | ||
1 | 4 | ||
5 | QEMU doesn't implement caches, so we just treat these ID registers as | ||
6 | opaque values that are set to the correct constant values for each | ||
7 | CPU. The only thing we need to do is allow 64-bit values in our | ||
8 | cssidr[] array and provide the CCSIDR2 accessors. | ||
9 | |||
10 | We don't set the CCIDX field in our 'max' CPU because the CCSIDR | ||
11 | constant values we use are the same as the ones used by the | ||
12 | Cortex-A57 and they are in the old 32-bit format. This means | ||
13 | that the extra regdef added here is unused currently, but it | ||
14 | means that whenever in the future we add a CPU that does need | ||
15 | the new 64-bit format it will just work when we set the cssidr | ||
16 | values and the ID registers for it. | ||
17 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20200224182626.29252-1-peter.maydell@linaro.org | ||
21 | --- | ||
22 | target/arm/cpu.h | 17 ++++++++++++++++- | ||
23 | target/arm/helper.c | 19 +++++++++++++++++++ | ||
24 | 2 files changed, 35 insertions(+), 1 deletion(-) | ||
25 | |||
26 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/cpu.h | ||
29 | +++ b/target/arm/cpu.h | ||
30 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
31 | /* The elements of this array are the CCSIDR values for each cache, | ||
32 | * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. | ||
33 | */ | ||
34 | - uint32_t ccsidr[16]; | ||
35 | + uint64_t ccsidr[16]; | ||
36 | uint64_t reset_cbar; | ||
37 | uint32_t reset_auxcr; | ||
38 | bool reset_hivecs; | ||
39 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) | ||
40 | return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0; | ||
41 | } | ||
42 | |||
43 | +static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) | ||
44 | +{ | ||
45 | + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; | ||
46 | +} | ||
47 | + | ||
48 | /* | ||
49 | * 64-bit feature tests via id registers. | ||
50 | */ | ||
51 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) | ||
52 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2; | ||
53 | } | ||
54 | |||
55 | +static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) | ||
56 | +{ | ||
57 | + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; | ||
58 | +} | ||
59 | + | ||
60 | /* | ||
61 | * Feature tests for "does this exist in either 32-bit or 64-bit?" | ||
62 | */ | ||
63 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) | ||
64 | return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); | ||
65 | } | ||
66 | |||
67 | +static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) | ||
68 | +{ | ||
69 | + return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); | ||
70 | +} | ||
71 | + | ||
72 | /* | ||
73 | * Forward to the above feature tests given an ARMCPU pointer. | ||
74 | */ | ||
75 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/helper.c | ||
78 | +++ b/target/arm/helper.c | ||
79 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = { | ||
80 | REGINFO_SENTINEL | ||
81 | }; | ||
82 | |||
83 | +static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
84 | +{ | ||
85 | + /* Read the high 32 bits of the current CCSIDR */ | ||
86 | + return extract64(ccsidr_read(env, ri), 32, 32); | ||
87 | +} | ||
88 | + | ||
89 | +static const ARMCPRegInfo ccsidr2_reginfo[] = { | ||
90 | + { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH, | ||
91 | + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2, | ||
92 | + .access = PL1_R, | ||
93 | + .accessfn = access_aa64_tid2, | ||
94 | + .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW }, | ||
95 | + REGINFO_SENTINEL | ||
96 | +}; | ||
97 | + | ||
98 | static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, | ||
99 | bool isread) | ||
100 | { | ||
101 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
102 | define_arm_cp_regs(cpu, predinv_reginfo); | ||
103 | } | ||
104 | |||
105 | + if (cpu_isar_feature(any_ccidx, cpu)) { | ||
106 | + define_arm_cp_regs(cpu, ccsidr2_reginfo); | ||
107 | + } | ||
108 | + | ||
109 | #ifndef CONFIG_USER_ONLY | ||
110 | /* | ||
111 | * Register redirections and aliases must be done last, | ||
112 | -- | ||
113 | 2.20.1 | ||
114 | |||
115 | diff view generated by jsdifflib |
1 | The nseries machines have a codepath that allows them to load a | 1 | In our KVM GICv2 realize function, we try to cope with old kernels |
---|---|---|---|
2 | secondary bootloader. This code wasn't checking that the | 2 | that don't provide the device control API (KVM_CAP_DEVICE_CTRL): we |
3 | load_image_targphys() succeeded. Check the return value and report | 3 | try to use the device control, and if that fails we fall back to |
4 | the error to the user. | 4 | assuming that the kernel has the old style KVM_CREATE_IRQCHIP and |
5 | that it will provide a GICv2. | ||
5 | 6 | ||
6 | While we're in the vicinity, fix the comment style of the | 7 | This doesn't cater for the possibility of a kernel and hardware which |
7 | comment documenting what this image load is doing. | 8 | only provide a GICv3, which is very common now. On that setup we |
9 | will abort() later on in kvm_arm_pmu_set_irq() when we try to wire up | ||
10 | an interrupt to the GIC we failed to create: | ||
8 | 11 | ||
9 | Fixes: Coverity CID 1192904 | 12 | qemu-system-aarch64: PMU: KVM_SET_DEVICE_ATTR: Invalid argument |
13 | qemu-system-aarch64: failed to set irq for PMU | ||
14 | Aborted | ||
15 | |||
16 | If the kernel advertises KVM_CAP_DEVICE_CTRL we should trust it if it | ||
17 | says it can't create a GICv2, rather than assuming it has one. We | ||
18 | can then produce a more helpful error message including a hint about | ||
19 | the most probable reason for the failure. | ||
20 | |||
21 | If the kernel doesn't advertise KVM_CAP_DEVICE_CTRL then it is truly | ||
22 | ancient by this point but we might as well still fall back to a | ||
23 | KVM_CREATE_IRQCHIP GICv2. | ||
24 | |||
25 | With this patch then the user misconfiguration which previously | ||
26 | caused an abort now prints: | ||
27 | qemu-system-aarch64: Initialization of device kvm-arm-gic failed: error creating in-kernel VGIC: No such device | ||
28 | Perhaps the host CPU does not support GICv2? | ||
29 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 31 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
12 | Message-id: 20201103114918.11807-1-peter.maydell@linaro.org | 32 | Reviewed-by: Andrew Jones <drjones@redhat.com> |
33 | Tested-by: Andrew Jones <drjones@redhat.com> | ||
34 | Message-id: 20200225182435.1131-1-peter.maydell@linaro.org | ||
13 | --- | 35 | --- |
14 | hw/arm/nseries.c | 15 +++++++++++---- | 36 | hw/intc/arm_gic_kvm.c | 9 +++++++++ |
15 | 1 file changed, 11 insertions(+), 4 deletions(-) | 37 | 1 file changed, 9 insertions(+) |
16 | 38 | ||
17 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | 39 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c |
18 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/nseries.c | 41 | --- a/hw/intc/arm_gic_kvm.c |
20 | +++ b/hw/arm/nseries.c | 42 | +++ b/hw/intc/arm_gic_kvm.c |
21 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | 43 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) |
22 | /* No, wait, better start at the ROM. */ | 44 | KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, |
23 | s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; | 45 | &error_abort); |
24 | 46 | } | |
25 | - /* This is intended for loading the `secondary.bin' program from | 47 | + } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) { |
48 | + error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); | ||
49 | + error_append_hint(errp, | ||
50 | + "Perhaps the host CPU does not support GICv2?\n"); | ||
51 | } else if (ret != -ENODEV && ret != -ENOTSUP) { | ||
26 | + /* | 52 | + /* |
27 | + * This is intended for loading the `secondary.bin' program from | 53 | + * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that |
28 | * Nokia images (the NOLO bootloader). The entry point seems | 54 | + * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE", |
29 | * to be at OMAP2_Q2_BASE + 0x400000. | 55 | + * and that we will get a GICv2 via KVM_CREATE_IRQCHIP. |
30 | * | ||
31 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
32 | * for them the entry point needs to be set to OMAP2_SRAM_BASE. | ||
33 | * | ||
34 | * The code above is for loading the `zImage' file from Nokia | ||
35 | - * images. */ | ||
36 | - load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000, | ||
37 | - machine->ram_size - 0x400000); | ||
38 | + * images. | ||
39 | + */ | 56 | + */ |
40 | + if (load_image_targphys(option_rom[0].name, | 57 | error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); |
41 | + OMAP2_Q2_BASE + 0x400000, | 58 | return; |
42 | + machine->ram_size - 0x400000) < 0) { | 59 | } |
43 | + error_report("Failed to load secondary bootloader %s", | ||
44 | + option_rom[0].name); | ||
45 | + exit(EXIT_FAILURE); | ||
46 | + } | ||
47 | |||
48 | n800_setup_nolo_tags(nolo_tags); | ||
49 | cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); | ||
50 | -- | 60 | -- |
51 | 2.20.1 | 61 | 2.20.1 |
52 | 62 | ||
53 | 63 | diff view generated by jsdifflib |