The following changes since commit 3c8c36c9087da957f580a9bb5ebf7814a753d1c6:

Merge remote-tracking branch 'remotes/kraxel/tags/ui-20201104-pull-request' into staging (2020-11-04 16:52:17 +0000)

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201109

for you to fetch changes up to 96338fefc19a143abdc91f6c44f37683274b08d4:

hw/intc/ibex_plic: Clear the claim register when read (2020-11-09 15:09:53 -0800)

This fixes two bugs in the RISC-V port. One is a bug in the

Ibex PLIC, the other fixes the Hypvervisor access functions.

Alistair Francis (6):

target/riscv: Add a virtualised MMU Mode

target/riscv: Set the virtualised MMU mode when doing hyp accesses

target/riscv: Remove the HS_TWO_STAGE flag

target/riscv: Remove the hyp load and store functions

target/riscv: Split the Hypervisor execute load helpers

hw/intc/ibex_plic: Clear the claim register when read

target/riscv/cpu-param.h | 11 ++-

target/riscv/cpu.h | 19 ++++-

target/riscv/cpu_bits.h | 1 -

target/riscv/helper.h | 5 +-

hw/intc/ibex_plic.c | 3 +

target/riscv/cpu_helper.c | 62 ++++++--------

target/riscv/op_helper.c | 124 ++-------------------------

target/riscv/translate.c | 2 +

target/riscv/insn_trans/trans_rvh.c.inc | 143 ++++++++++++--------------------

9 files changed, 115 insertions(+), 255 deletions(-)

Remove the special Virtulisation load and store functions and just use

the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions

instead.

As part of this change we ensure we still run an access check to make

sure we can perform the operations.

target/riscv/cpu.h | 12 +++

target/riscv/helper.h | 2 -

target/riscv/op_helper.c | 86 -----------------

target/riscv/translate.c | 2 +

target/riscv/insn_trans/trans_rvh.c.inc | 123 +++++++++---------------

5 files changed, 59 insertions(+), 166 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

--- a/target/riscv/cpu.h

+++ b/target/riscv/cpu.h

@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)

FIELD(TB_FLAGS, LMUL, 3, 2)

FIELD(TB_FLAGS, SEW, 5, 3)

FIELD(TB_FLAGS, VILL, 8, 1)

+/* Is a Hypervisor instruction load/store allowed? */

+FIELD(TB_FLAGS, HLSX, 9, 1)

/*

* A simplification for VLMAX

@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,

if (riscv_cpu_fp_enabled(env)) {

flags |= env->mstatus & MSTATUS_FS;

}

+ if (riscv_has_ext(env, RVH)) {

+ if (env->priv == PRV_M ||

+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||

+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&

+ get_field(env->hstatus, HSTATUS_HU))) {

+ flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);

#endif

+

*pflags = flags;

}

diff --git a/target/riscv/helper.h b/target/riscv/helper.h

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/helper.h

+++ b/target/riscv/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(tlb_flush, void, env)

#ifndef CONFIG_USER_ONLY

DEF_HELPER_1(hyp_tlb_flush, void, env)

DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)

-DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)

-DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)

DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)

#endif

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/op_helper.c

+++ b/target/riscv/op_helper.c

@@ -XXX,XX +XXX,XX @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)

helper_hyp_tlb_flush(env);

}

-target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,

- target_ulong attrs, target_ulong memop)

-{

- if (env->priv == PRV_M ||

- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||

- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&

- get_field(env->hstatus, HSTATUS_HU))) {

- target_ulong pte;

- int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;

-

- switch (memop) {

- case MO_SB:

- pte = cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC());

- break;

- case MO_UB:

- pte = cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC());

- break;

- case MO_TESW:

- pte = cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC());

- break;

- case MO_TEUW:

- pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());

- break;

- case MO_TESL:

- pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());

- break;

- case MO_TEUL:

- pte = cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());

- break;

- case MO_TEQ:

- pte = cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC());

- break;

- default:

- g_assert_not_reached();

- }

-

- return pte;

- }

-

- if (riscv_cpu_virt_enabled(env)) {

- riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());

- } else {

- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());

- }

- return 0;

-}

-

-void helper_hyp_store(CPURISCVState *env, target_ulong address,

- target_ulong val, target_ulong attrs, target_ulong memop)

-{

- if (env->priv == PRV_M ||

- (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||

- (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&

- get_field(env->hstatus, HSTATUS_HU))) {

- int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;

-

- switch (memop) {

- case MO_SB:

- case MO_UB:

- cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC());

- break;

- case MO_TESW:

- case MO_TEUW:

- cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC());

- break;

- case MO_TESL:

- case MO_TEUL:

- cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC());

- break;

- case MO_TEQ:

- cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC());

- break;

- default:

- g_assert_not_reached();

- }

-

- return;

- }

-

- if (riscv_cpu_virt_enabled(env)) {

- riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());

- } else {

- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());

- }

-}

-

target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,

target_ulong attrs, target_ulong memop)

{

diff --git a/target/riscv/translate.c b/target/riscv/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/translate.c

+++ b/target/riscv/translate.c

@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {

to reset this known value. */

int frm;

bool ext_ifencei;

+ bool hlsx;

/* vector extension */

bool vill;

uint8_t lmul;

@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)

ctx->frm = -1; /* unknown rounding mode */

ctx->ext_ifencei = cpu->cfg.ext_ifencei;

ctx->vlen = cpu->cfg.vlen;

+ ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);

ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);

ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);

ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);

diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/insn_trans/trans_rvh.c.inc

+++ b/target/riscv/insn_trans/trans_rvh.c.inc

@@ -XXX,XX +XXX,XX @@

* this program. If not, see <http://www.gnu.org/licenses/>.

*/

+#ifndef CONFIG_USER_ONLY

+static void check_access(DisasContext *ctx) {

+ if (!ctx->hlsx) {

+ if (ctx->virt_enabled) {

+ generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);

+ } else {

+ generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);

+ }

+ }

+}

+#endif

+

static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)

{

REQUIRE_EXT(ctx, RVH);

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv t1 = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_SB);

- gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);

+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);

gen_set_gpr(a->rd, t1);

tcg_temp_free(t0);

tcg_temp_free(t1);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv t1 = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_TESW);

- gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);

+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);

gen_set_gpr(a->rd, t1);

tcg_temp_free(t0);

tcg_temp_free(t1);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv t1 = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_TESL);

- gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);

+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);

gen_set_gpr(a->rd, t1);

tcg_temp_free(t0);

tcg_temp_free(t1);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv t1 = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_UB);

- gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);

+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_UB);

gen_set_gpr(a->rd, t1);

tcg_temp_free(t0);

tcg_temp_free(t1);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv t1 = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

- gen_get_gpr(t0, a->rs1);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_TEUW);

+ check_access(ctx);

- gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);

+ gen_get_gpr(t0, a->rs1);

+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUW);

gen_set_gpr(a->rd, t1);

tcg_temp_free(t0);

tcg_temp_free(t1);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv dat = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

gen_get_gpr(dat, a->rs2);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_SB);

- gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);

+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_SB);

tcg_temp_free(t0);

tcg_temp_free(dat);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv dat = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

gen_get_gpr(dat, a->rs2);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_TESW);

- gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);

+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESW);

tcg_temp_free(t0);

tcg_temp_free(dat);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv dat = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

gen_get_gpr(dat, a->rs2);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_TESL);

- gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);

+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TESL);

tcg_temp_free(t0);

tcg_temp_free(dat);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv t1 = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_TEUL);

- gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);

+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEUL);

gen_set_gpr(a->rd, t1);

tcg_temp_free(t0);

tcg_temp_free(t1);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv t1 = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_TEQ);

- gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);

+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);

gen_set_gpr(a->rd, t1);

tcg_temp_free(t0);

tcg_temp_free(t1);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)

#ifndef CONFIG_USER_ONLY

TCGv t0 = tcg_temp_new();

TCGv dat = tcg_temp_new();

- TCGv mem_idx = tcg_temp_new();

- TCGv memop = tcg_temp_new();

+

+ check_access(ctx);

gen_get_gpr(t0, a->rs1);

gen_get_gpr(dat, a->rs2);

- tcg_gen_movi_tl(mem_idx, ctx->mem_idx);

- tcg_gen_movi_tl(memop, MO_TEQ);

- gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);

+ tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MASK, MO_TEQ);

tcg_temp_free(t0);

tcg_temp_free(dat);

- tcg_temp_free(mem_idx);

- tcg_temp_free(memop);

return true;

#else

return false;

2.29.2

The HS_TWO_STAGE flag is no longer required as the MMU index contains

the information if we are performing a two stage access.

target/riscv/cpu.h | 3 +-

target/riscv/cpu_bits.h | 1 -

target/riscv/cpu_helper.c | 60 ++++++++++++++++-----------------------

target/riscv/op_helper.c | 12 --------

4 files changed, 25 insertions(+), 51 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h

--- a/target/riscv/cpu.h

+++ b/target/riscv/cpu.h

@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);

void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);

bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);

void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);

-bool riscv_cpu_two_stage_lookup(CPURISCVState *env);

-void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);

+bool riscv_cpu_two_stage_lookup(int mmu_idx);

int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);

hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/cpu_bits.h

+++ b/target/riscv/cpu_bits.h

@@ -XXX,XX +XXX,XX @@

* page table fault.

*/

#define FORCE_HS_EXCEP 2

-#define HS_TWO_STAGE 4

/* RV32 satp CSR field masks */

#define SATP32_MODE 0x80000000

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/cpu_helper.c

+++ b/target/riscv/cpu_helper.c

@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)

env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);

}

-bool riscv_cpu_two_stage_lookup(CPURISCVState *env)

+bool riscv_cpu_two_stage_lookup(int mmu_idx)

{

- if (!riscv_has_ext(env, RVH)) {

- return false;

- }

-

- return get_field(env->virt, HS_TWO_STAGE);

-void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)

- if (!riscv_has_ext(env, RVH)) {

- return;

- }

-

- env->virt = set_field(env->virt, HS_TWO_STAGE, enable);

+ return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;

int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)

@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,

* was called. Background registers will be used if the guest has

* forced a two stage translation to be on (in HS or M mode).

*/

- if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {

+ if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {

use_background = true;

}

@@ -XXX,XX +XXX,XX @@ restart:

static void raise_mmu_exception(CPURISCVState *env, target_ulong address,

MMUAccessType access_type, bool pmp_violation,

- bool first_stage)

+ bool first_stage, bool two_stage)

{

CPUState *cs = env_cpu(env);

int page_fault_exceptions;

@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,

}

break;

case MMU_DATA_LOAD:

- if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&

- !first_stage) {

+ if (two_stage && !first_stage) {

cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;

} else {

cs->exception_index = page_fault_exceptions ?

@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,

}

break;

case MMU_DATA_STORE:

- if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&

- !first_stage) {

+ if (two_stage && !first_stage) {

cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;

} else {

cs->exception_index = page_fault_exceptions ?

@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

int prot, prot2;

bool pmp_violation = false;

bool first_stage_error = true;

+ bool two_stage_lookup = false;

int ret = TRANSLATE_FAIL;

int mode = mmu_idx;

target_ulong tlb_size = 0;

@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

access_type != MMU_INST_FETCH &&

get_field(env->mstatus, MSTATUS_MPRV) &&

get_field(env->mstatus, MSTATUS_MPV)) {

- riscv_cpu_set_two_stage_lookup(env, true);

+ two_stage_lookup = true;

}

if (riscv_cpu_virt_enabled(env) ||

- (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {

+ ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) &&

+ access_type != MMU_INST_FETCH)) {

/* Two stage lookup */

ret = get_physical_address(env, &pa, &prot, address,

&env->guest_phys_fault_addr, access_type,

@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

__func__, address, ret, pa, prot);

}

- /* We did the two stage lookup based on MPRV, unset the lookup */

- if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&

- access_type != MMU_INST_FETCH &&

- get_field(env->mstatus, MSTATUS_MPRV) &&

- get_field(env->mstatus, MSTATUS_MPV)) {

- riscv_cpu_set_two_stage_lookup(env, false);

- }

-

if (riscv_feature(env, RISCV_FEATURE_PMP) &&

(ret == TRANSLATE_SUCCESS) &&

!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {

@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

} else if (probe) {

return false;

} else {

- raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error);

+ raise_mmu_exception(env, address, access_type, pmp_violation,

+ first_stage_error,

+ riscv_cpu_virt_enabled(env) ||

+ riscv_cpu_two_stage_lookup(mmu_idx));

riscv_raise_exception(env, cs->exception_index, retaddr);

}

@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)

/* handle the trap in S-mode */

if (riscv_has_ext(env, RVH)) {

target_ulong hdeleg = async ? env->hideleg : env->hedeleg;

+ bool two_stage_lookup = false;

+

+ if (env->priv == PRV_M ||

+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||

+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&

+ get_field(env->hstatus, HSTATUS_HU))) {

+ two_stage_lookup = true;

+ }

- if ((riscv_cpu_virt_enabled(env) ||

- riscv_cpu_two_stage_lookup(env)) && write_tval) {

+ if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write_tval) {

/*

* If we are writing a guest virtual address to stval, set

* this to 1. If we are trapping to VS we will set this to 0

@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)

riscv_cpu_set_force_hs_excep(env, 0);

} else {

/* Trap into HS mode */

- if (!riscv_cpu_two_stage_lookup(env)) {

+ if (!two_stage_lookup) {

env->hstatus = set_field(env->hstatus, HSTATUS_SPV,

riscv_cpu_virt_enabled(env));

}

- riscv_cpu_set_two_stage_lookup(env, false);

htval = env->guest_phys_fault_addr;

}

}

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/riscv/op_helper.c

+++ b/target/riscv/op_helper.c

@@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,

target_ulong pte;

int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;

- riscv_cpu_set_two_stage_lookup(env, true);

-

switch (memop) {

case MO_SB:

pte = cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC());

@@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,

g_assert_not_reached();

}

- riscv_cpu_set_two_stage_lookup(env, false);

-

return pte;

}

@@ -XXX,XX +XXX,XX @@ void helper_hyp_store(CPURISCVState *env, target_ulong address,

get_field(env->hstatus, HSTATUS_HU))) {

int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;

- riscv_cpu_set_two_stage_lookup(env, true);

-

switch (memop) {

case MO_SB:

case MO_UB:

@@ -XXX,XX +XXX,XX @@ void helper_hyp_store(CPURISCVState *env, target_ulong address,

g_assert_not_reached();

}

- riscv_cpu_set_two_stage_lookup(env, false);

-

return;

}

@@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,

target_ulong pte;

int mmu_idx = cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCESS_MASK;

- riscv_cpu_set_two_stage_lookup(env, true);

-

switch (memop) {

case MO_TEUW:

pte = cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());

@@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,

g_assert_not_reached();

}

- riscv_cpu_set_two_stage_lookup(env, false);

-

return pte;

}

2.29.2