1 | The following changes since commit 83851c7c60c90e9fb6a23ff48076387a77bc33cd: | 1 | The following changes since commit c5ea91da443b458352c1b629b490ee6631775cb4: |
---|---|---|---|
2 | 2 | ||
3 | Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-10-27-v3-tag' into staging (2020-11-03 12:47:58 +0000) | 3 | Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2023-09-08 10:06:25 -0400) |
4 | 4 | ||
5 | are available in the Git repository at: | 5 | are available in the Git repository at: |
6 | 6 | ||
7 | git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201103 | 7 | https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230911 |
8 | 8 | ||
9 | for you to fetch changes up to 422819776101520cb56658ee5facf926526cf870: | 9 | for you to fetch changes up to e7a03409f29e2da59297d55afbaec98c96e43e3a: |
10 | 10 | ||
11 | target/riscv/csr.c : add space before the open parenthesis '(' (2020-11-03 07:17:23 -0800) | 11 | target/riscv: don't read CSR in riscv_csrrw_do64 (2023-09-11 11:45:55 +1000) |
12 | 12 | ||
13 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
14 | This series adds support for migration to RISC-V QEMU and expands the | 14 | First RISC-V PR for 8.2 |
15 | Microchip PFSoC to allow unmodified HSS and Linux boots. | 15 | |
16 | * Remove 'host' CPU from TCG | ||
17 | * riscv_htif Fixup printing on big endian hosts | ||
18 | * Add zmmul isa string | ||
19 | * Add smepmp isa string | ||
20 | * Fix page_check_range use in fault-only-first | ||
21 | * Use existing lookup tables for MixColumns | ||
22 | * Add RISC-V vector cryptographic instruction set support | ||
23 | * Implement WARL behaviour for mcountinhibit/mcounteren | ||
24 | * Add Zihintntl extension ISA string to DTS | ||
25 | * Fix zfa fleq.d and fltq.d | ||
26 | * Fix upper/lower mtime write calculation | ||
27 | * Make rtc variable names consistent | ||
28 | * Use abi type for linux-user target_ucontext | ||
29 | * Add RISC-V KVM AIA Support | ||
30 | * Fix riscv,pmu DT node path in the virt machine | ||
31 | * Update CSR bits name for svadu extension | ||
32 | * Mark zicond non-experimental | ||
33 | * Fix satp_mode_finalize() when satp_mode.supported = 0 | ||
34 | * Fix non-KVM --enable-debug build | ||
35 | * Add new extensions to hwprobe | ||
36 | * Use accelerated helper for AES64KS1I | ||
37 | * Allocate itrigger timers only once | ||
38 | * Respect mseccfg.RLB for pmpaddrX changes | ||
39 | * Align the AIA model to v1.0 ratified spec | ||
40 | * Don't read the CSR in riscv_csrrw_do64 | ||
16 | 41 | ||
17 | ---------------------------------------------------------------- | 42 | ---------------------------------------------------------------- |
18 | Anup Patel (2): | 43 | Akihiko Odaki (1): |
19 | hw/riscv: sifive_u: Allow passing custom DTB | 44 | target/riscv: Allocate itrigger timers only once |
20 | hw/riscv: virt: Allow passing custom DTB | ||
21 | 45 | ||
22 | Bin Meng (10): | 46 | Ard Biesheuvel (2): |
23 | hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps | 47 | target/riscv: Use existing lookup tables for MixColumns |
24 | hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support | 48 | target/riscv: Use accelerated helper for AES64KS1I |
25 | hw/riscv: microchip_pfsoc: Connect DDR memory controller modules | ||
26 | hw/misc: Add Microchip PolarFire SoC IOSCB module support | ||
27 | hw/riscv: microchip_pfsoc: Connect the IOSCB module | ||
28 | hw/misc: Add Microchip PolarFire SoC SYSREG module support | ||
29 | hw/riscv: microchip_pfsoc: Connect the SYSREG module | ||
30 | hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 | ||
31 | hw/riscv: microchip_pfsoc: Correct DDR memory map | ||
32 | hw/riscv: microchip_pfsoc: Hook the I2C1 controller | ||
33 | 49 | ||
34 | Xinhao Zhang (1): | 50 | Conor Dooley (1): |
35 | target/riscv/csr.c : add space before the open parenthesis '(' | 51 | hw/riscv: virt: Fix riscv,pmu DT node path |
36 | 52 | ||
37 | Yifei Jiang (6): | 53 | Daniel Henrique Barboza (6): |
38 | target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit | 54 | target/riscv/cpu.c: do not run 'host' CPU with TCG |
39 | target/riscv: Add basic vmstate description of CPU | 55 | target/riscv/cpu.c: add zmmul isa string |
40 | target/riscv: Add PMP state description | 56 | target/riscv/cpu.c: add smepmp isa string |
41 | target/riscv: Add H extension state description | 57 | target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 |
42 | target/riscv: Add V extension state description | 58 | hw/riscv/virt.c: fix non-KVM --enable-debug build |
43 | target/riscv: Add sifive_plic vmstate | 59 | hw/intc/riscv_aplic.c fix non-KVM --enable-debug build |
44 | 60 | ||
45 | include/hw/intc/sifive_plic.h | 1 + | 61 | Dickon Hood (2): |
46 | include/hw/misc/mchp_pfsoc_dmc.h | 56 +++++++++ | 62 | target/riscv: Refactor translation of vector-widening instruction |
47 | include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++++ | 63 | target/riscv: Add Zvbb ISA extension support |
48 | include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++ | ||
49 | include/hw/riscv/microchip_pfsoc.h | 18 ++- | ||
50 | target/riscv/cpu.h | 24 ++-- | ||
51 | target/riscv/cpu_bits.h | 19 +-- | ||
52 | target/riscv/internals.h | 4 + | ||
53 | target/riscv/pmp.h | 2 + | ||
54 | hw/intc/sifive_plic.c | 26 +++- | ||
55 | hw/misc/mchp_pfsoc_dmc.c | 216 ++++++++++++++++++++++++++++++++ | ||
56 | hw/misc/mchp_pfsoc_ioscb.c | 242 ++++++++++++++++++++++++++++++++++++ | ||
57 | hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++ | ||
58 | hw/riscv/microchip_pfsoc.c | 125 ++++++++++++++++--- | ||
59 | hw/riscv/sifive_u.c | 28 +++-- | ||
60 | hw/riscv/virt.c | 27 ++-- | ||
61 | target/riscv/cpu.c | 16 +-- | ||
62 | target/riscv/cpu_helper.c | 35 ++---- | ||
63 | target/riscv/csr.c | 20 +-- | ||
64 | target/riscv/machine.c | 196 +++++++++++++++++++++++++++++ | ||
65 | target/riscv/op_helper.c | 11 +- | ||
66 | target/riscv/pmp.c | 29 +++-- | ||
67 | MAINTAINERS | 6 + | ||
68 | hw/misc/Kconfig | 9 ++ | ||
69 | hw/misc/meson.build | 3 + | ||
70 | hw/riscv/Kconfig | 3 + | ||
71 | target/riscv/meson.build | 3 +- | ||
72 | 27 files changed, 1180 insertions(+), 127 deletions(-) | ||
73 | create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h | ||
74 | create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h | ||
75 | create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h | ||
76 | create mode 100644 hw/misc/mchp_pfsoc_dmc.c | ||
77 | create mode 100644 hw/misc/mchp_pfsoc_ioscb.c | ||
78 | create mode 100644 hw/misc/mchp_pfsoc_sysreg.c | ||
79 | create mode 100644 target/riscv/machine.c | ||
80 | 64 | ||
65 | Jason Chien (3): | ||
66 | target/riscv: Add Zihintntl extension ISA string to DTS | ||
67 | hw/intc: Fix upper/lower mtime write calculation | ||
68 | hw/intc: Make rtc variable names consistent | ||
69 | |||
70 | Kiran Ostrolenk (4): | ||
71 | target/riscv: Refactor some of the generic vector functionality | ||
72 | target/riscv: Refactor vector-vector translation macro | ||
73 | target/riscv: Refactor some of the generic vector functionality | ||
74 | target/riscv: Add Zvknh ISA extension support | ||
75 | |||
76 | LIU Zhiwei (3): | ||
77 | target/riscv: Fix page_check_range use in fault-only-first | ||
78 | target/riscv: Fix zfa fleq.d and fltq.d | ||
79 | linux-user/riscv: Use abi type for target_ucontext | ||
80 | |||
81 | Lawrence Hunter (2): | ||
82 | target/riscv: Add Zvbc ISA extension support | ||
83 | target/riscv: Add Zvksh ISA extension support | ||
84 | |||
85 | Leon Schuermann (1): | ||
86 | target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes | ||
87 | |||
88 | Max Chou (3): | ||
89 | crypto: Create sm4_subword | ||
90 | crypto: Add SM4 constant parameter CK | ||
91 | target/riscv: Add Zvksed ISA extension support | ||
92 | |||
93 | Nazar Kazakov (4): | ||
94 | target/riscv: Remove redundant "cpu_vl == 0" checks | ||
95 | target/riscv: Move vector translation checks | ||
96 | target/riscv: Add Zvkned ISA extension support | ||
97 | target/riscv: Add Zvkg ISA extension support | ||
98 | |||
99 | Nikita Shubin (1): | ||
100 | target/riscv: don't read CSR in riscv_csrrw_do64 | ||
101 | |||
102 | Rob Bradford (1): | ||
103 | target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren | ||
104 | |||
105 | Robbin Ehn (1): | ||
106 | linux-user/riscv: Add new extensions to hwprobe | ||
107 | |||
108 | Thomas Huth (2): | ||
109 | hw/char/riscv_htif: Fix printing of console characters on big endian hosts | ||
110 | hw/char/riscv_htif: Fix the console syscall on big endian hosts | ||
111 | |||
112 | Tommy Wu (1): | ||
113 | target/riscv: Align the AIA model to v1.0 ratified spec | ||
114 | |||
115 | Vineet Gupta (1): | ||
116 | riscv: zicond: make non-experimental | ||
117 | |||
118 | Weiwei Li (1): | ||
119 | target/riscv: Update CSR bits name for svadu extension | ||
120 | |||
121 | Yong-Xuan Wang (5): | ||
122 | target/riscv: support the AIA device emulation with KVM enabled | ||
123 | target/riscv: check the in-kernel irqchip support | ||
124 | target/riscv: Create an KVM AIA irqchip | ||
125 | target/riscv: update APLIC and IMSIC to support KVM AIA | ||
126 | target/riscv: select KVM AIA in riscv virt machine | ||
127 | |||
128 | include/crypto/aes.h | 7 + | ||
129 | include/crypto/sm4.h | 9 + | ||
130 | target/riscv/cpu_bits.h | 8 +- | ||
131 | target/riscv/cpu_cfg.h | 9 + | ||
132 | target/riscv/debug.h | 3 +- | ||
133 | target/riscv/helper.h | 98 +++ | ||
134 | target/riscv/kvm_riscv.h | 5 + | ||
135 | target/riscv/vector_internals.h | 228 +++++++ | ||
136 | target/riscv/insn32.decode | 58 ++ | ||
137 | crypto/aes.c | 4 +- | ||
138 | crypto/sm4.c | 10 + | ||
139 | hw/char/riscv_htif.c | 12 +- | ||
140 | hw/intc/riscv_aclint.c | 11 +- | ||
141 | hw/intc/riscv_aplic.c | 52 +- | ||
142 | hw/intc/riscv_imsic.c | 25 +- | ||
143 | hw/riscv/virt.c | 374 ++++++------ | ||
144 | linux-user/riscv/signal.c | 4 +- | ||
145 | linux-user/syscall.c | 14 +- | ||
146 | target/arm/tcg/crypto_helper.c | 10 +- | ||
147 | target/riscv/cpu.c | 83 ++- | ||
148 | target/riscv/cpu_helper.c | 6 +- | ||
149 | target/riscv/crypto_helper.c | 51 +- | ||
150 | target/riscv/csr.c | 54 +- | ||
151 | target/riscv/debug.c | 15 +- | ||
152 | target/riscv/kvm.c | 201 ++++++- | ||
153 | target/riscv/pmp.c | 4 + | ||
154 | target/riscv/translate.c | 1 + | ||
155 | target/riscv/vcrypto_helper.c | 970 ++++++++++++++++++++++++++++++ | ||
156 | target/riscv/vector_helper.c | 245 +------- | ||
157 | target/riscv/vector_internals.c | 81 +++ | ||
158 | target/riscv/insn_trans/trans_rvv.c.inc | 171 +++--- | ||
159 | target/riscv/insn_trans/trans_rvvk.c.inc | 606 +++++++++++++++++++ | ||
160 | target/riscv/insn_trans/trans_rvzfa.c.inc | 4 +- | ||
161 | target/riscv/meson.build | 4 +- | ||
162 | 34 files changed, 2785 insertions(+), 652 deletions(-) | ||
163 | create mode 100644 target/riscv/vector_internals.h | ||
164 | create mode 100644 target/riscv/vcrypto_helper.c | ||
165 | create mode 100644 target/riscv/vector_internals.c | ||
166 | create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
---|---|---|---|
2 | 2 | ||
3 | Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. | 3 | The 'host' CPU is available in a CONFIG_KVM build and it's currently |
4 | available for all accels, but is a KVM only CPU. This means that in a | ||
5 | RISC-V KVM capable host we can do things like this: | ||
4 | 6 | ||
5 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 7 | $ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic |
8 | qemu-system-riscv64: H extension requires priv spec 1.12.0 | ||
9 | |||
10 | This CPU does not have a priv spec because we don't filter its extensions | ||
11 | via priv spec. We shouldn't be reaching riscv_cpu_realize_tcg() at all | ||
12 | with the 'host' CPU. | ||
13 | |||
14 | We don't have a way to filter the 'host' CPU out of the available CPU | ||
15 | options (-cpu help) if the build includes both KVM and TCG. What we can | ||
16 | do is to error out during riscv_cpu_realize_tcg() if the user chooses | ||
17 | the 'host' CPU with accel=tcg: | ||
18 | |||
19 | $ ./build/qemu-system-riscv64 -M virt,accel=tcg -cpu host --nographic | ||
20 | qemu-system-riscv64: 'host' CPU is not compatible with TCG acceleration | ||
21 | |||
22 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 23 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
7 | Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com | 24 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
25 | Message-Id: <20230721133411.474105-1-dbarboza@ventanamicro.com> | ||
8 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 26 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
9 | --- | 27 | --- |
10 | include/hw/riscv/microchip_pfsoc.h | 5 +++++ | 28 | target/riscv/cpu.c | 5 +++++ |
11 | hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ | 29 | 1 file changed, 5 insertions(+) |
12 | hw/riscv/Kconfig | 1 + | ||
13 | 3 files changed, 24 insertions(+) | ||
14 | 30 | ||
15 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | 31 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
16 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/include/hw/riscv/microchip_pfsoc.h | 33 | --- a/target/riscv/cpu.c |
18 | +++ b/include/hw/riscv/microchip_pfsoc.h | 34 | +++ b/target/riscv/cpu.c |
19 | @@ -XXX,XX +XXX,XX @@ | 35 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) |
20 | 36 | CPURISCVState *env = &cpu->env; | |
21 | #include "hw/char/mchp_pfsoc_mmuart.h" | 37 | Error *local_err = NULL; |
22 | #include "hw/dma/sifive_pdma.h" | 38 | |
23 | +#include "hw/misc/mchp_pfsoc_dmc.h" | 39 | + if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { |
24 | #include "hw/net/cadence_gem.h" | 40 | + error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); |
25 | #include "hw/sd/cadence_sdhci.h" | 41 | + return; |
26 | 42 | + } | |
27 | @@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState { | ||
28 | RISCVHartArrayState e_cpus; | ||
29 | RISCVHartArrayState u_cpus; | ||
30 | DeviceState *plic; | ||
31 | + MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; | ||
32 | + MchpPfSoCDdrCfgState ddr_cfg; | ||
33 | MchpPfSoCMMUartState *serial0; | ||
34 | MchpPfSoCMMUartState *serial1; | ||
35 | MchpPfSoCMMUartState *serial2; | ||
36 | @@ -XXX,XX +XXX,XX @@ enum { | ||
37 | MICROCHIP_PFSOC_MMUART0, | ||
38 | MICROCHIP_PFSOC_SYSREG, | ||
39 | MICROCHIP_PFSOC_MPUCFG, | ||
40 | + MICROCHIP_PFSOC_DDR_SGMII_PHY, | ||
41 | MICROCHIP_PFSOC_EMMC_SD, | ||
42 | + MICROCHIP_PFSOC_DDR_CFG, | ||
43 | MICROCHIP_PFSOC_MMUART1, | ||
44 | MICROCHIP_PFSOC_MMUART2, | ||
45 | MICROCHIP_PFSOC_MMUART3, | ||
46 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/riscv/microchip_pfsoc.c | ||
49 | +++ b/hw/riscv/microchip_pfsoc.c | ||
50 | @@ -XXX,XX +XXX,XX @@ | ||
51 | * 4) Cadence eMMC/SDHC controller and an SD card connected to it | ||
52 | * 5) SiFive Platform DMA (Direct Memory Access Controller) | ||
53 | * 6) GEM (Gigabit Ethernet MAC Controller) | ||
54 | + * 7) DMC (DDR Memory Controller) | ||
55 | * | ||
56 | * This board currently generates devicetree dynamically that indicates at least | ||
57 | * two harts and up to five harts. | ||
58 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
59 | [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, | ||
60 | [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, | ||
61 | [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, | ||
62 | + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, | ||
63 | [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, | ||
64 | + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, | ||
65 | [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, | ||
66 | [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, | ||
67 | [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, | ||
68 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj) | ||
69 | object_initialize_child(obj, "dma-controller", &s->dma, | ||
70 | TYPE_SIFIVE_PDMA); | ||
71 | |||
72 | + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, | ||
73 | + TYPE_MCHP_PFSOC_DDR_SGMII_PHY); | ||
74 | + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, | ||
75 | + TYPE_MCHP_PFSOC_DDR_CFG); | ||
76 | + | 43 | + |
77 | object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); | 44 | riscv_cpu_validate_misa_mxl(cpu, &local_err); |
78 | object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); | 45 | if (local_err != NULL) { |
79 | 46 | error_propagate(errp, local_err); | |
80 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
81 | memmap[MICROCHIP_PFSOC_MPUCFG].base, | ||
82 | memmap[MICROCHIP_PFSOC_MPUCFG].size); | ||
83 | |||
84 | + /* DDR SGMII PHY */ | ||
85 | + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); | ||
86 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, | ||
87 | + memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); | ||
88 | + | ||
89 | + /* DDR CFG */ | ||
90 | + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); | ||
91 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, | ||
92 | + memmap[MICROCHIP_PFSOC_DDR_CFG].base); | ||
93 | + | ||
94 | /* SDHCI */ | ||
95 | sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); | ||
96 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, | ||
97 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig | ||
98 | index XXXXXXX..XXXXXXX 100644 | ||
99 | --- a/hw/riscv/Kconfig | ||
100 | +++ b/hw/riscv/Kconfig | ||
101 | @@ -XXX,XX +XXX,XX @@ config IBEX | ||
102 | config MICROCHIP_PFSOC | ||
103 | bool | ||
104 | select CADENCE_SDHCI | ||
105 | + select MCHP_PFSOC_DMC | ||
106 | select MCHP_PFSOC_MMUART | ||
107 | select MSI_NONBROKEN | ||
108 | select SIFIVE_CLINT | ||
109 | -- | 47 | -- |
110 | 2.28.0 | 48 | 2.41.0 |
111 | 49 | ||
112 | 50 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Thomas Huth <thuth@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | The latest SD card image [1] released by Microchip ships a Linux | 3 | The character that should be printed is stored in the 64 bit "payload" |
4 | kernel with built-in PolarFire SoC I2C driver support. The device | 4 | variable. The code currently tries to print it by taking the address |
5 | tree file includes the description for the I2C1 node hence kernel | 5 | of the variable and passing this pointer to qemu_chr_fe_write(). However, |
6 | tries to probe the I2C1 device during boot. | 6 | this only works on little endian hosts where the least significant bits |
7 | are stored on the lowest address. To do this in a portable way, we have | ||
8 | to store the value in an uint8_t variable instead. | ||
7 | 9 | ||
8 | It is enough to create an unimplemented device for I2C1 to allow | 10 | Fixes: 5033606780 ("RISC-V HTIF Console") |
9 | the kernel to continue booting to the shell. | 11 | Signed-off-by: Thomas Huth <thuth@redhat.com> |
10 | |||
11 | [1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz | ||
12 | |||
13 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
15 | Message-id: 1603863010-15807-11-git-send-email-bmeng.cn@gmail.com | 13 | Reviewed-by: Bin Meng <bmeng@tinylab.org> |
14 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
16 | Message-Id: <20230721094720.902454-2-thuth@redhat.com> | ||
16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
17 | --- | 18 | --- |
18 | include/hw/riscv/microchip_pfsoc.h | 1 + | 19 | hw/char/riscv_htif.c | 3 ++- |
19 | hw/riscv/microchip_pfsoc.c | 6 ++++++ | 20 | 1 file changed, 2 insertions(+), 1 deletion(-) |
20 | 2 files changed, 7 insertions(+) | ||
21 | 21 | ||
22 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | 22 | diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c |
23 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/include/hw/riscv/microchip_pfsoc.h | 24 | --- a/hw/char/riscv_htif.c |
25 | +++ b/include/hw/riscv/microchip_pfsoc.h | 25 | +++ b/hw/char/riscv_htif.c |
26 | @@ -XXX,XX +XXX,XX @@ enum { | 26 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) |
27 | MICROCHIP_PFSOC_MMUART2, | 27 | s->tohost = 0; /* clear to indicate we read */ |
28 | MICROCHIP_PFSOC_MMUART3, | 28 | return; |
29 | MICROCHIP_PFSOC_MMUART4, | 29 | } else if (cmd == HTIF_CONSOLE_CMD_PUTC) { |
30 | + MICROCHIP_PFSOC_I2C1, | 30 | - qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1); |
31 | MICROCHIP_PFSOC_GEM0, | 31 | + uint8_t ch = (uint8_t)payload; |
32 | MICROCHIP_PFSOC_GEM1, | 32 | + qemu_chr_fe_write(&s->chr, &ch, 1); |
33 | MICROCHIP_PFSOC_GPIO0, | 33 | resp = 0x100 | (uint8_t)payload; |
34 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | 34 | } else { |
35 | index XXXXXXX..XXXXXXX 100644 | 35 | qemu_log("HTIF device %d: unknown command\n", device); |
36 | --- a/hw/riscv/microchip_pfsoc.c | ||
37 | +++ b/hw/riscv/microchip_pfsoc.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
39 | [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, | ||
40 | [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, | ||
41 | [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, | ||
42 | + [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, | ||
43 | [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, | ||
44 | [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, | ||
45 | [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, | ||
46 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
47 | qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), | ||
48 | serial_hd(4)); | ||
49 | |||
50 | + /* I2C1 */ | ||
51 | + create_unimplemented_device("microchip.pfsoc.i2c1", | ||
52 | + memmap[MICROCHIP_PFSOC_I2C1].base, | ||
53 | + memmap[MICROCHIP_PFSOC_I2C1].size); | ||
54 | + | ||
55 | /* GEMs */ | ||
56 | |||
57 | nd = &nd_table[0]; | ||
58 | -- | 36 | -- |
59 | 2.28.0 | 37 | 2.41.0 |
60 | 38 | ||
61 | 39 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Thomas Huth <thuth@redhat.com> | ||
1 | 2 | ||
3 | Values that have been read via cpu_physical_memory_read() from the | ||
4 | guest's memory have to be swapped in case the host endianess differs | ||
5 | from the guest. | ||
6 | |||
7 | Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall") | ||
8 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Reviewed-by: Bin Meng <bmeng@tinylab.org> | ||
11 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
12 | Message-Id: <20230721094720.902454-3-thuth@redhat.com> | ||
13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | --- | ||
15 | hw/char/riscv_htif.c | 9 +++++---- | ||
16 | 1 file changed, 5 insertions(+), 4 deletions(-) | ||
17 | |||
18 | diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/hw/char/riscv_htif.c | ||
21 | +++ b/hw/char/riscv_htif.c | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | #include "qemu/timer.h" | ||
24 | #include "qemu/error-report.h" | ||
25 | #include "exec/address-spaces.h" | ||
26 | +#include "exec/tswap.h" | ||
27 | #include "sysemu/dma.h" | ||
28 | |||
29 | #define RISCV_DEBUG_HTIF 0 | ||
30 | @@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) | ||
31 | } else { | ||
32 | uint64_t syscall[8]; | ||
33 | cpu_physical_memory_read(payload, syscall, sizeof(syscall)); | ||
34 | - if (syscall[0] == PK_SYS_WRITE && | ||
35 | - syscall[1] == HTIF_DEV_CONSOLE && | ||
36 | - syscall[3] == HTIF_CONSOLE_CMD_PUTC) { | ||
37 | + if (tswap64(syscall[0]) == PK_SYS_WRITE && | ||
38 | + tswap64(syscall[1]) == HTIF_DEV_CONSOLE && | ||
39 | + tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { | ||
40 | uint8_t ch; | ||
41 | - cpu_physical_memory_read(syscall[2], &ch, 1); | ||
42 | + cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1); | ||
43 | qemu_chr_fe_write(&s->chr, &ch, 1); | ||
44 | resp = 0x100 | (uint8_t)payload; | ||
45 | } else { | ||
46 | -- | ||
47 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | zmmul was promoted from experimental to ratified in commit 6d00ffad4e95. | ||
4 | Add a riscv,isa string for it. | ||
5 | |||
6 | Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental properties") | ||
7 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
8 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Message-Id: <20230720132424.371132-2-dbarboza@ventanamicro.com> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | --- | ||
13 | target/riscv/cpu.c | 1 + | ||
14 | 1 file changed, 1 insertion(+) | ||
15 | |||
16 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/riscv/cpu.c | ||
19 | +++ b/target/riscv/cpu.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
21 | ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), | ||
22 | ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), | ||
23 | ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), | ||
24 | + ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), | ||
25 | ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), | ||
26 | ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), | ||
27 | ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), | ||
28 | -- | ||
29 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | The cpu->cfg.epmp extension is still experimental, but it already has a | ||
4 | 'smepmp' riscv,isa string. Add it. | ||
5 | |||
6 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
7 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-Id: <20230720132424.371132-3-dbarboza@ventanamicro.com> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | target/riscv/cpu.c | 1 + | ||
13 | 1 file changed, 1 insertion(+) | ||
14 | |||
15 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/riscv/cpu.c | ||
18 | +++ b/target/riscv/cpu.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
20 | ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), | ||
21 | ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), | ||
22 | ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), | ||
23 | + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp), | ||
24 | ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), | ||
25 | ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), | ||
26 | ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), | ||
27 | -- | ||
28 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
1 | 2 | ||
3 | Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts | ||
4 | integer return value to bool type. However, it wrongly converted the use | ||
5 | of the API in riscv fault-only-first, where page_check_range < = 0, should | ||
6 | be converted to !page_check_range. | ||
7 | |||
8 | Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-ID: <20230729031618.821-1-zhiwei_liu@linux.alibaba.com> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | --- | ||
13 | target/riscv/vector_helper.c | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/riscv/vector_helper.c | ||
19 | +++ b/target/riscv/vector_helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ vext_ldff(void *vd, void *v0, target_ulong base, | ||
21 | cpu_mmu_index(env, false)); | ||
22 | if (host) { | ||
23 | #ifdef CONFIG_USER_ONLY | ||
24 | - if (page_check_range(addr, offset, PAGE_READ)) { | ||
25 | + if (!page_check_range(addr, offset, PAGE_READ)) { | ||
26 | vl = i; | ||
27 | goto ProbeSuccess; | ||
28 | } | ||
29 | -- | ||
30 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Ard Biesheuvel <ardb@kernel.org> |
---|---|---|---|
2 | 2 | ||
3 | It is not easy to find out the memory map for a specific component | 3 | The AES MixColumns and InvMixColumns operations are relatively |
4 | in the PolarFire SoC as the information is scattered in different | 4 | expensive 4x4 matrix multiplications in GF(2^8), which is why C |
5 | documents. Add some comments so that people can know where to get | 5 | implementations usually rely on precomputed lookup tables rather than |
6 | such information from the Microchip website. | 6 | performing the calculations on demand. |
7 | 7 | ||
8 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 8 | Given that we already carry those tables in QEMU, we can just grab the |
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | right value in the implementation of the RISC-V AES32 instructions. Note |
10 | Message-id: 1603863010-15807-2-git-send-email-bmeng.cn@gmail.com | 10 | that the tables in question are permuted according to the respective |
11 | Sbox, so we can omit the Sbox lookup as well in this case. | ||
12 | |||
13 | Cc: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Cc: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
15 | Cc: Zewen Ye <lustrew@foxmail.com> | ||
16 | Cc: Weiwei Li <liweiwei@iscas.ac.cn> | ||
17 | Cc: Junqiang Wang <wangjunqiang@iscas.ac.cn> | ||
18 | Signed-off-by: Ard Biesheuvel <ardb@kernel.org> | ||
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-ID: <20230731084043.1791984-1-ardb@kernel.org> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 21 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
12 | --- | 22 | --- |
13 | hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ | 23 | include/crypto/aes.h | 7 +++++++ |
14 | 1 file changed, 18 insertions(+) | 24 | crypto/aes.c | 4 ++-- |
25 | target/riscv/crypto_helper.c | 34 ++++------------------------------ | ||
26 | 3 files changed, 13 insertions(+), 32 deletions(-) | ||
15 | 27 | ||
16 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | 28 | diff --git a/include/crypto/aes.h b/include/crypto/aes.h |
17 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/riscv/microchip_pfsoc.c | 30 | --- a/include/crypto/aes.h |
19 | +++ b/hw/riscv/microchip_pfsoc.c | 31 | +++ b/include/crypto/aes.h |
32 | @@ -XXX,XX +XXX,XX @@ void AES_decrypt(const unsigned char *in, unsigned char *out, | ||
33 | extern const uint8_t AES_sbox[256]; | ||
34 | extern const uint8_t AES_isbox[256]; | ||
35 | |||
36 | +/* | ||
37 | +AES_Te0[x] = S [x].[02, 01, 01, 03]; | ||
38 | +AES_Td0[x] = Si[x].[0e, 09, 0d, 0b]; | ||
39 | +*/ | ||
40 | + | ||
41 | +extern const uint32_t AES_Te0[256], AES_Td0[256]; | ||
42 | + | ||
43 | #endif | ||
44 | diff --git a/crypto/aes.c b/crypto/aes.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/crypto/aes.c | ||
47 | +++ b/crypto/aes.c | ||
48 | @@ -XXX,XX +XXX,XX @@ AES_Td3[x] = Si[x].[09, 0d, 0b, 0e]; | ||
49 | AES_Td4[x] = Si[x].[01, 01, 01, 01]; | ||
50 | */ | ||
51 | |||
52 | -static const uint32_t AES_Te0[256] = { | ||
53 | +const uint32_t AES_Te0[256] = { | ||
54 | 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, | ||
55 | 0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, | ||
56 | 0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU, | ||
57 | @@ -XXX,XX +XXX,XX @@ static const uint32_t AES_Te4[256] = { | ||
58 | 0xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U, | ||
59 | }; | ||
60 | |||
61 | -static const uint32_t AES_Td0[256] = { | ||
62 | +const uint32_t AES_Td0[256] = { | ||
63 | 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, | ||
64 | 0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, | ||
65 | 0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U, | ||
66 | diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/riscv/crypto_helper.c | ||
69 | +++ b/target/riscv/crypto_helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ | 70 | @@ -XXX,XX +XXX,XX @@ |
21 | /* GEM version */ | 71 | #include "crypto/aes-round.h" |
22 | #define GEM_REVISION 0x0107010c | 72 | #include "crypto/sm4.h" |
23 | 73 | ||
24 | +/* | 74 | -#define AES_XTIME(a) \ |
25 | + * The complete description of the whole PolarFire SoC memory map is scattered | 75 | - ((a << 1) ^ ((a & 0x80) ? 0x1b : 0)) |
26 | + * in different documents. There are several places to look at for memory maps: | 76 | - |
27 | + * | 77 | -#define AES_GFMUL(a, b) (( \ |
28 | + * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA | 78 | - (((b) & 0x1) ? (a) : 0) ^ \ |
29 | + * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from | 79 | - (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \ |
30 | + * https://www.microsemi.com/document-portal/doc_download/ | 80 | - (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \ |
31 | + * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, | 81 | - (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF) |
32 | + * describes the whole picture of the PolarFire SoC memory map. | 82 | - |
33 | + * | 83 | -static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd) |
34 | + * 2 A zip file for PolarFire soC memory map, which can be downloaded from | 84 | -{ |
35 | + * https://www.microsemi.com/document-portal/doc_download/ | 85 | - uint32_t u; |
36 | + * 1244581-polarfire-soc-register-map, contains the following 2 major parts: | 86 | - |
37 | + * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm | 87 | - if (fwd) { |
38 | + * describes the complete integrated peripherals memory map | 88 | - u = (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) | |
39 | + * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm | 89 | - (AES_GFMUL(x, 2) << 0); |
40 | + * describes the complete IOSCB modules memory maps | 90 | - } else { |
41 | + */ | 91 | - u = (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) | |
42 | static const struct MemmapEntry { | 92 | - (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0); |
43 | hwaddr base; | 93 | - } |
44 | hwaddr size; | 94 | - return u; |
95 | -} | ||
96 | - | ||
97 | #define sext32_xlen(x) (target_ulong)(int32_t)(x) | ||
98 | |||
99 | static inline target_ulong aes32_operation(target_ulong shamt, | ||
100 | @@ -XXX,XX +XXX,XX @@ static inline target_ulong aes32_operation(target_ulong shamt, | ||
101 | bool enc, bool mix) | ||
102 | { | ||
103 | uint8_t si = rs2 >> shamt; | ||
104 | - uint8_t so; | ||
105 | uint32_t mixed; | ||
106 | target_ulong res; | ||
107 | |||
108 | if (enc) { | ||
109 | - so = AES_sbox[si]; | ||
110 | if (mix) { | ||
111 | - mixed = aes_mixcolumn_byte(so, true); | ||
112 | + mixed = be32_to_cpu(AES_Te0[si]); | ||
113 | } else { | ||
114 | - mixed = so; | ||
115 | + mixed = AES_sbox[si]; | ||
116 | } | ||
117 | } else { | ||
118 | - so = AES_isbox[si]; | ||
119 | if (mix) { | ||
120 | - mixed = aes_mixcolumn_byte(so, false); | ||
121 | + mixed = be32_to_cpu(AES_Td0[si]); | ||
122 | } else { | ||
123 | - mixed = so; | ||
124 | + mixed = AES_isbox[si]; | ||
125 | } | ||
126 | } | ||
127 | mixed = rol32(mixed, shamt); | ||
45 | -- | 128 | -- |
46 | 2.28.0 | 129 | 2.41.0 |
47 | 130 | ||
48 | 131 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> |
---|---|---|---|
2 | 2 | ||
3 | This creates a minimum model for Microchip PolarFire SoC SYSREG | 3 | Take some functions/macros out of `vector_helper` and put them in a new |
4 | module. It only implements the ENVM_CR register to tell guest | 4 | module called `vector_internals`. This ensures they can be used by both |
5 | software that eNVM is running at the configured divider rate. | 5 | vector and vector-crypto helpers (latter implemented in proceeding |
6 | commits). | ||
6 | 7 | ||
7 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 8 | Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> |
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> |
9 | Message-id: 1603863010-15807-7-git-send-email-bmeng.cn@gmail.com | 10 | Signed-off-by: Max Chou <max.chou@sifive.com> |
11 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | Message-ID: <20230711165917.2629866-2-max.chou@sifive.com> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
11 | --- | 14 | --- |
12 | include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++++++++ | 15 | target/riscv/vector_internals.h | 182 +++++++++++++++++++++++++++++ |
13 | hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++++++++++++++++ | 16 | target/riscv/vector_helper.c | 201 +------------------------------- |
14 | MAINTAINERS | 2 + | 17 | target/riscv/vector_internals.c | 81 +++++++++++++ |
15 | hw/misc/Kconfig | 3 + | 18 | target/riscv/meson.build | 1 + |
16 | hw/misc/meson.build | 1 + | 19 | 4 files changed, 265 insertions(+), 200 deletions(-) |
17 | 5 files changed, 144 insertions(+) | 20 | create mode 100644 target/riscv/vector_internals.h |
18 | create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h | 21 | create mode 100644 target/riscv/vector_internals.c |
19 | create mode 100644 hw/misc/mchp_pfsoc_sysreg.c | ||
20 | 22 | ||
21 | diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h | 23 | diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h |
22 | new file mode 100644 | 24 | new file mode 100644 |
23 | index XXXXXXX..XXXXXXX | 25 | index XXXXXXX..XXXXXXX |
24 | --- /dev/null | 26 | --- /dev/null |
25 | +++ b/include/hw/misc/mchp_pfsoc_sysreg.h | 27 | +++ b/target/riscv/vector_internals.h |
26 | @@ -XXX,XX +XXX,XX @@ | 28 | @@ -XXX,XX +XXX,XX @@ |
27 | +/* | 29 | +/* |
28 | + * Microchip PolarFire SoC SYSREG module emulation | 30 | + * RISC-V Vector Extension Internals |
29 | + * | 31 | + * |
30 | + * Copyright (c) 2020 Wind River Systems, Inc. | 32 | + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. |
31 | + * | 33 | + * |
32 | + * Author: | 34 | + * This program is free software; you can redistribute it and/or modify it |
33 | + * Bin Meng <bin.meng@windriver.com> | 35 | + * under the terms and conditions of the GNU General Public License, |
34 | + * | 36 | + * version 2 or later, as published by the Free Software Foundation. |
35 | + * This program is free software; you can redistribute it and/or | 37 | + * |
36 | + * modify it under the terms of the GNU General Public License as | 38 | + * This program is distributed in the hope it will be useful, but WITHOUT |
37 | + * published by the Free Software Foundation; either version 2 or | 39 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
38 | + * (at your option) version 3 of the License. | 40 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
39 | + * | 41 | + * more details. |
40 | + * This program is distributed in the hope that it will be useful, | 42 | + * |
41 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 43 | + * You should have received a copy of the GNU General Public License along with |
42 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 44 | + * this program. If not, see <http://www.gnu.org/licenses/>. |
43 | + * GNU General Public License for more details. | 45 | + */ |
44 | + * | 46 | + |
45 | + * You should have received a copy of the GNU General Public License along | 47 | +#ifndef TARGET_RISCV_VECTOR_INTERNALS_H |
46 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | 48 | +#define TARGET_RISCV_VECTOR_INTERNALS_H |
47 | + */ | 49 | + |
48 | + | 50 | +#include "qemu/osdep.h" |
49 | +#ifndef MCHP_PFSOC_SYSREG_H | 51 | +#include "qemu/bitops.h" |
50 | +#define MCHP_PFSOC_SYSREG_H | 52 | +#include "cpu.h" |
51 | + | 53 | +#include "tcg/tcg-gvec-desc.h" |
52 | +#define MCHP_PFSOC_SYSREG_REG_SIZE 0x2000 | 54 | +#include "internals.h" |
53 | + | 55 | + |
54 | +typedef struct MchpPfSoCSysregState { | 56 | +static inline uint32_t vext_nf(uint32_t desc) |
55 | + SysBusDevice parent; | 57 | +{ |
56 | + MemoryRegion sysreg; | 58 | + return FIELD_EX32(simd_data(desc), VDATA, NF); |
57 | +} MchpPfSoCSysregState; | 59 | +} |
58 | + | 60 | + |
59 | +#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg" | 61 | +/* |
60 | + | 62 | + * Note that vector data is stored in host-endian 64-bit chunks, |
61 | +#define MCHP_PFSOC_SYSREG(obj) \ | 63 | + * so addressing units smaller than that needs a host-endian fixup. |
62 | + OBJECT_CHECK(MchpPfSoCSysregState, (obj), \ | 64 | + */ |
63 | + TYPE_MCHP_PFSOC_SYSREG) | 65 | +#if HOST_BIG_ENDIAN |
64 | + | 66 | +#define H1(x) ((x) ^ 7) |
65 | +#endif /* MCHP_PFSOC_SYSREG_H */ | 67 | +#define H1_2(x) ((x) ^ 6) |
66 | diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c | 68 | +#define H1_4(x) ((x) ^ 4) |
69 | +#define H2(x) ((x) ^ 3) | ||
70 | +#define H4(x) ((x) ^ 1) | ||
71 | +#define H8(x) ((x)) | ||
72 | +#else | ||
73 | +#define H1(x) (x) | ||
74 | +#define H1_2(x) (x) | ||
75 | +#define H1_4(x) (x) | ||
76 | +#define H2(x) (x) | ||
77 | +#define H4(x) (x) | ||
78 | +#define H8(x) (x) | ||
79 | +#endif | ||
80 | + | ||
81 | +/* | ||
82 | + * Encode LMUL to lmul as following: | ||
83 | + * LMUL vlmul lmul | ||
84 | + * 1 000 0 | ||
85 | + * 2 001 1 | ||
86 | + * 4 010 2 | ||
87 | + * 8 011 3 | ||
88 | + * - 100 - | ||
89 | + * 1/8 101 -3 | ||
90 | + * 1/4 110 -2 | ||
91 | + * 1/2 111 -1 | ||
92 | + */ | ||
93 | +static inline int32_t vext_lmul(uint32_t desc) | ||
94 | +{ | ||
95 | + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); | ||
96 | +} | ||
97 | + | ||
98 | +static inline uint32_t vext_vm(uint32_t desc) | ||
99 | +{ | ||
100 | + return FIELD_EX32(simd_data(desc), VDATA, VM); | ||
101 | +} | ||
102 | + | ||
103 | +static inline uint32_t vext_vma(uint32_t desc) | ||
104 | +{ | ||
105 | + return FIELD_EX32(simd_data(desc), VDATA, VMA); | ||
106 | +} | ||
107 | + | ||
108 | +static inline uint32_t vext_vta(uint32_t desc) | ||
109 | +{ | ||
110 | + return FIELD_EX32(simd_data(desc), VDATA, VTA); | ||
111 | +} | ||
112 | + | ||
113 | +static inline uint32_t vext_vta_all_1s(uint32_t desc) | ||
114 | +{ | ||
115 | + return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); | ||
116 | +} | ||
117 | + | ||
118 | +/* | ||
119 | + * Earlier designs (pre-0.9) had a varying number of bits | ||
120 | + * per mask value (MLEN). In the 0.9 design, MLEN=1. | ||
121 | + * (Section 4.5) | ||
122 | + */ | ||
123 | +static inline int vext_elem_mask(void *v0, int index) | ||
124 | +{ | ||
125 | + int idx = index / 64; | ||
126 | + int pos = index % 64; | ||
127 | + return (((uint64_t *)v0)[idx] >> pos) & 1; | ||
128 | +} | ||
129 | + | ||
130 | +/* | ||
131 | + * Get number of total elements, including prestart, body and tail elements. | ||
132 | + * Note that when LMUL < 1, the tail includes the elements past VLMAX that | ||
133 | + * are held in the same vector register. | ||
134 | + */ | ||
135 | +static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, | ||
136 | + uint32_t esz) | ||
137 | +{ | ||
138 | + uint32_t vlenb = simd_maxsz(desc); | ||
139 | + uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); | ||
140 | + int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : | ||
141 | + ctzl(esz) - ctzl(sew) + vext_lmul(desc); | ||
142 | + return (vlenb << emul) / esz; | ||
143 | +} | ||
144 | + | ||
145 | +/* set agnostic elements to 1s */ | ||
146 | +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, | ||
147 | + uint32_t tot); | ||
148 | + | ||
149 | +/* expand macro args before macro */ | ||
150 | +#define RVVCALL(macro, ...) macro(__VA_ARGS__) | ||
151 | + | ||
152 | +/* (TD, T1, T2, TX1, TX2) */ | ||
153 | +#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t | ||
154 | +#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t | ||
155 | +#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t | ||
156 | +#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t | ||
157 | + | ||
158 | +/* operation of two vector elements */ | ||
159 | +typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); | ||
160 | + | ||
161 | +#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ | ||
162 | +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ | ||
163 | +{ \ | ||
164 | + TX1 s1 = *((T1 *)vs1 + HS1(i)); \ | ||
165 | + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ | ||
166 | + *((TD *)vd + HD(i)) = OP(s2, s1); \ | ||
167 | +} | ||
168 | + | ||
169 | +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, | ||
170 | + CPURISCVState *env, uint32_t desc, | ||
171 | + opivv2_fn *fn, uint32_t esz); | ||
172 | + | ||
173 | +/* generate the helpers for OPIVV */ | ||
174 | +#define GEN_VEXT_VV(NAME, ESZ) \ | ||
175 | +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ | ||
176 | + void *vs2, CPURISCVState *env, \ | ||
177 | + uint32_t desc) \ | ||
178 | +{ \ | ||
179 | + do_vext_vv(vd, v0, vs1, vs2, env, desc, \ | ||
180 | + do_##NAME, ESZ); \ | ||
181 | +} | ||
182 | + | ||
183 | +typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); | ||
184 | + | ||
185 | +/* | ||
186 | + * (T1)s1 gives the real operator type. | ||
187 | + * (TX1)(T1)s1 expands the operator type of widen or narrow operations. | ||
188 | + */ | ||
189 | +#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ | ||
190 | +static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ | ||
191 | +{ \ | ||
192 | + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ | ||
193 | + *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \ | ||
194 | +} | ||
195 | + | ||
196 | +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, | ||
197 | + CPURISCVState *env, uint32_t desc, | ||
198 | + opivx2_fn fn, uint32_t esz); | ||
199 | + | ||
200 | +/* generate the helpers for OPIVX */ | ||
201 | +#define GEN_VEXT_VX(NAME, ESZ) \ | ||
202 | +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ | ||
203 | + void *vs2, CPURISCVState *env, \ | ||
204 | + uint32_t desc) \ | ||
205 | +{ \ | ||
206 | + do_vext_vx(vd, v0, s1, vs2, env, desc, \ | ||
207 | + do_##NAME, ESZ); \ | ||
208 | +} | ||
209 | + | ||
210 | +#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ | ||
211 | diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c | ||
212 | index XXXXXXX..XXXXXXX 100644 | ||
213 | --- a/target/riscv/vector_helper.c | ||
214 | +++ b/target/riscv/vector_helper.c | ||
215 | @@ -XXX,XX +XXX,XX @@ | ||
216 | #include "fpu/softfloat.h" | ||
217 | #include "tcg/tcg-gvec-desc.h" | ||
218 | #include "internals.h" | ||
219 | +#include "vector_internals.h" | ||
220 | #include <math.h> | ||
221 | |||
222 | target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, | ||
223 | @@ -XXX,XX +XXX,XX @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, | ||
224 | return vl; | ||
225 | } | ||
226 | |||
227 | -/* | ||
228 | - * Note that vector data is stored in host-endian 64-bit chunks, | ||
229 | - * so addressing units smaller than that needs a host-endian fixup. | ||
230 | - */ | ||
231 | -#if HOST_BIG_ENDIAN | ||
232 | -#define H1(x) ((x) ^ 7) | ||
233 | -#define H1_2(x) ((x) ^ 6) | ||
234 | -#define H1_4(x) ((x) ^ 4) | ||
235 | -#define H2(x) ((x) ^ 3) | ||
236 | -#define H4(x) ((x) ^ 1) | ||
237 | -#define H8(x) ((x)) | ||
238 | -#else | ||
239 | -#define H1(x) (x) | ||
240 | -#define H1_2(x) (x) | ||
241 | -#define H1_4(x) (x) | ||
242 | -#define H2(x) (x) | ||
243 | -#define H4(x) (x) | ||
244 | -#define H8(x) (x) | ||
245 | -#endif | ||
246 | - | ||
247 | -static inline uint32_t vext_nf(uint32_t desc) | ||
248 | -{ | ||
249 | - return FIELD_EX32(simd_data(desc), VDATA, NF); | ||
250 | -} | ||
251 | - | ||
252 | -static inline uint32_t vext_vm(uint32_t desc) | ||
253 | -{ | ||
254 | - return FIELD_EX32(simd_data(desc), VDATA, VM); | ||
255 | -} | ||
256 | - | ||
257 | -/* | ||
258 | - * Encode LMUL to lmul as following: | ||
259 | - * LMUL vlmul lmul | ||
260 | - * 1 000 0 | ||
261 | - * 2 001 1 | ||
262 | - * 4 010 2 | ||
263 | - * 8 011 3 | ||
264 | - * - 100 - | ||
265 | - * 1/8 101 -3 | ||
266 | - * 1/4 110 -2 | ||
267 | - * 1/2 111 -1 | ||
268 | - */ | ||
269 | -static inline int32_t vext_lmul(uint32_t desc) | ||
270 | -{ | ||
271 | - return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); | ||
272 | -} | ||
273 | - | ||
274 | -static inline uint32_t vext_vta(uint32_t desc) | ||
275 | -{ | ||
276 | - return FIELD_EX32(simd_data(desc), VDATA, VTA); | ||
277 | -} | ||
278 | - | ||
279 | -static inline uint32_t vext_vma(uint32_t desc) | ||
280 | -{ | ||
281 | - return FIELD_EX32(simd_data(desc), VDATA, VMA); | ||
282 | -} | ||
283 | - | ||
284 | -static inline uint32_t vext_vta_all_1s(uint32_t desc) | ||
285 | -{ | ||
286 | - return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); | ||
287 | -} | ||
288 | - | ||
289 | /* | ||
290 | * Get the maximum number of elements can be operated. | ||
291 | * | ||
292 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) | ||
293 | return scale < 0 ? vlenb >> -scale : vlenb << scale; | ||
294 | } | ||
295 | |||
296 | -/* | ||
297 | - * Get number of total elements, including prestart, body and tail elements. | ||
298 | - * Note that when LMUL < 1, the tail includes the elements past VLMAX that | ||
299 | - * are held in the same vector register. | ||
300 | - */ | ||
301 | -static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, | ||
302 | - uint32_t esz) | ||
303 | -{ | ||
304 | - uint32_t vlenb = simd_maxsz(desc); | ||
305 | - uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); | ||
306 | - int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : | ||
307 | - ctzl(esz) - ctzl(sew) + vext_lmul(desc); | ||
308 | - return (vlenb << emul) / esz; | ||
309 | -} | ||
310 | - | ||
311 | static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) | ||
312 | { | ||
313 | return (addr & ~env->cur_pmmask) | env->cur_pmbase; | ||
314 | @@ -XXX,XX +XXX,XX @@ static void probe_pages(CPURISCVState *env, target_ulong addr, | ||
315 | } | ||
316 | } | ||
317 | |||
318 | -/* set agnostic elements to 1s */ | ||
319 | -static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, | ||
320 | - uint32_t tot) | ||
321 | -{ | ||
322 | - if (is_agnostic == 0) { | ||
323 | - /* policy undisturbed */ | ||
324 | - return; | ||
325 | - } | ||
326 | - if (tot - cnt == 0) { | ||
327 | - return; | ||
328 | - } | ||
329 | - memset(base + cnt, -1, tot - cnt); | ||
330 | -} | ||
331 | - | ||
332 | static inline void vext_set_elem_mask(void *v0, int index, | ||
333 | uint8_t value) | ||
334 | { | ||
335 | @@ -XXX,XX +XXX,XX @@ static inline void vext_set_elem_mask(void *v0, int index, | ||
336 | ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value); | ||
337 | } | ||
338 | |||
339 | -/* | ||
340 | - * Earlier designs (pre-0.9) had a varying number of bits | ||
341 | - * per mask value (MLEN). In the 0.9 design, MLEN=1. | ||
342 | - * (Section 4.5) | ||
343 | - */ | ||
344 | -static inline int vext_elem_mask(void *v0, int index) | ||
345 | -{ | ||
346 | - int idx = index / 64; | ||
347 | - int pos = index % 64; | ||
348 | - return (((uint64_t *)v0)[idx] >> pos) & 1; | ||
349 | -} | ||
350 | - | ||
351 | /* elements operations for load and store */ | ||
352 | typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr, | ||
353 | uint32_t idx, void *vd, uintptr_t retaddr); | ||
354 | @@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) | ||
355 | * Vector Integer Arithmetic Instructions | ||
356 | */ | ||
357 | |||
358 | -/* expand macro args before macro */ | ||
359 | -#define RVVCALL(macro, ...) macro(__VA_ARGS__) | ||
360 | - | ||
361 | /* (TD, T1, T2, TX1, TX2) */ | ||
362 | #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t | ||
363 | #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t | ||
364 | #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t | ||
365 | #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t | ||
366 | -#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t | ||
367 | -#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t | ||
368 | -#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t | ||
369 | -#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t | ||
370 | #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t | ||
371 | #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t | ||
372 | #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t | ||
373 | @@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) | ||
374 | #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t | ||
375 | #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t | ||
376 | |||
377 | -/* operation of two vector elements */ | ||
378 | -typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); | ||
379 | - | ||
380 | -#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ | ||
381 | -static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ | ||
382 | -{ \ | ||
383 | - TX1 s1 = *((T1 *)vs1 + HS1(i)); \ | ||
384 | - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ | ||
385 | - *((TD *)vd + HD(i)) = OP(s2, s1); \ | ||
386 | -} | ||
387 | #define DO_SUB(N, M) (N - M) | ||
388 | #define DO_RSUB(N, M) (M - N) | ||
389 | |||
390 | @@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB) | ||
391 | RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB) | ||
392 | RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) | ||
393 | |||
394 | -static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, | ||
395 | - CPURISCVState *env, uint32_t desc, | ||
396 | - opivv2_fn *fn, uint32_t esz) | ||
397 | -{ | ||
398 | - uint32_t vm = vext_vm(desc); | ||
399 | - uint32_t vl = env->vl; | ||
400 | - uint32_t total_elems = vext_get_total_elems(env, desc, esz); | ||
401 | - uint32_t vta = vext_vta(desc); | ||
402 | - uint32_t vma = vext_vma(desc); | ||
403 | - uint32_t i; | ||
404 | - | ||
405 | - for (i = env->vstart; i < vl; i++) { | ||
406 | - if (!vm && !vext_elem_mask(v0, i)) { | ||
407 | - /* set masked-off elements to 1s */ | ||
408 | - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); | ||
409 | - continue; | ||
410 | - } | ||
411 | - fn(vd, vs1, vs2, i); | ||
412 | - } | ||
413 | - env->vstart = 0; | ||
414 | - /* set tail elements to 1s */ | ||
415 | - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); | ||
416 | -} | ||
417 | - | ||
418 | -/* generate the helpers for OPIVV */ | ||
419 | -#define GEN_VEXT_VV(NAME, ESZ) \ | ||
420 | -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ | ||
421 | - void *vs2, CPURISCVState *env, \ | ||
422 | - uint32_t desc) \ | ||
423 | -{ \ | ||
424 | - do_vext_vv(vd, v0, vs1, vs2, env, desc, \ | ||
425 | - do_##NAME, ESZ); \ | ||
426 | -} | ||
427 | - | ||
428 | GEN_VEXT_VV(vadd_vv_b, 1) | ||
429 | GEN_VEXT_VV(vadd_vv_h, 2) | ||
430 | GEN_VEXT_VV(vadd_vv_w, 4) | ||
431 | @@ -XXX,XX +XXX,XX @@ GEN_VEXT_VV(vsub_vv_h, 2) | ||
432 | GEN_VEXT_VV(vsub_vv_w, 4) | ||
433 | GEN_VEXT_VV(vsub_vv_d, 8) | ||
434 | |||
435 | -typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); | ||
436 | - | ||
437 | -/* | ||
438 | - * (T1)s1 gives the real operator type. | ||
439 | - * (TX1)(T1)s1 expands the operator type of widen or narrow operations. | ||
440 | - */ | ||
441 | -#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ | ||
442 | -static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ | ||
443 | -{ \ | ||
444 | - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ | ||
445 | - *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \ | ||
446 | -} | ||
447 | |||
448 | RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD) | ||
449 | RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD) | ||
450 | @@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB) | ||
451 | RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB) | ||
452 | RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) | ||
453 | |||
454 | -static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, | ||
455 | - CPURISCVState *env, uint32_t desc, | ||
456 | - opivx2_fn fn, uint32_t esz) | ||
457 | -{ | ||
458 | - uint32_t vm = vext_vm(desc); | ||
459 | - uint32_t vl = env->vl; | ||
460 | - uint32_t total_elems = vext_get_total_elems(env, desc, esz); | ||
461 | - uint32_t vta = vext_vta(desc); | ||
462 | - uint32_t vma = vext_vma(desc); | ||
463 | - uint32_t i; | ||
464 | - | ||
465 | - for (i = env->vstart; i < vl; i++) { | ||
466 | - if (!vm && !vext_elem_mask(v0, i)) { | ||
467 | - /* set masked-off elements to 1s */ | ||
468 | - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); | ||
469 | - continue; | ||
470 | - } | ||
471 | - fn(vd, s1, vs2, i); | ||
472 | - } | ||
473 | - env->vstart = 0; | ||
474 | - /* set tail elements to 1s */ | ||
475 | - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); | ||
476 | -} | ||
477 | - | ||
478 | -/* generate the helpers for OPIVX */ | ||
479 | -#define GEN_VEXT_VX(NAME, ESZ) \ | ||
480 | -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ | ||
481 | - void *vs2, CPURISCVState *env, \ | ||
482 | - uint32_t desc) \ | ||
483 | -{ \ | ||
484 | - do_vext_vx(vd, v0, s1, vs2, env, desc, \ | ||
485 | - do_##NAME, ESZ); \ | ||
486 | -} | ||
487 | - | ||
488 | GEN_VEXT_VX(vadd_vx_b, 1) | ||
489 | GEN_VEXT_VX(vadd_vx_h, 2) | ||
490 | GEN_VEXT_VX(vadd_vx_w, 4) | ||
491 | diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c | ||
67 | new file mode 100644 | 492 | new file mode 100644 |
68 | index XXXXXXX..XXXXXXX | 493 | index XXXXXXX..XXXXXXX |
69 | --- /dev/null | 494 | --- /dev/null |
70 | +++ b/hw/misc/mchp_pfsoc_sysreg.c | 495 | +++ b/target/riscv/vector_internals.c |
71 | @@ -XXX,XX +XXX,XX @@ | 496 | @@ -XXX,XX +XXX,XX @@ |
72 | +/* | 497 | +/* |
73 | + * Microchip PolarFire SoC SYSREG module emulation | 498 | + * RISC-V Vector Extension Internals |
74 | + * | 499 | + * |
75 | + * Copyright (c) 2020 Wind River Systems, Inc. | 500 | + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. |
76 | + * | 501 | + * |
77 | + * Author: | 502 | + * This program is free software; you can redistribute it and/or modify it |
78 | + * Bin Meng <bin.meng@windriver.com> | 503 | + * under the terms and conditions of the GNU General Public License, |
79 | + * | 504 | + * version 2 or later, as published by the Free Software Foundation. |
80 | + * This program is free software; you can redistribute it and/or | 505 | + * |
81 | + * modify it under the terms of the GNU General Public License as | 506 | + * This program is distributed in the hope it will be useful, but WITHOUT |
82 | + * published by the Free Software Foundation; either version 2 or | 507 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
83 | + * (at your option) version 3 of the License. | 508 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
84 | + * | 509 | + * more details. |
85 | + * This program is distributed in the hope that it will be useful, | 510 | + * |
86 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 511 | + * You should have received a copy of the GNU General Public License along with |
87 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 512 | + * this program. If not, see <http://www.gnu.org/licenses/>. |
88 | + * GNU General Public License for more details. | 513 | + */ |
89 | + * | 514 | + |
90 | + * You should have received a copy of the GNU General Public License along | 515 | +#include "vector_internals.h" |
91 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | 516 | + |
92 | + */ | 517 | +/* set agnostic elements to 1s */ |
93 | + | 518 | +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, |
94 | +#include "qemu/osdep.h" | 519 | + uint32_t tot) |
95 | +#include "qemu/bitops.h" | 520 | +{ |
96 | +#include "qemu/log.h" | 521 | + if (is_agnostic == 0) { |
97 | +#include "qapi/error.h" | 522 | + /* policy undisturbed */ |
98 | +#include "hw/hw.h" | 523 | + return; |
99 | +#include "hw/sysbus.h" | ||
100 | +#include "hw/misc/mchp_pfsoc_sysreg.h" | ||
101 | + | ||
102 | +#define ENVM_CR 0xb8 | ||
103 | + | ||
104 | +static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset, | ||
105 | + unsigned size) | ||
106 | +{ | ||
107 | + uint32_t val = 0; | ||
108 | + | ||
109 | + switch (offset) { | ||
110 | + case ENVM_CR: | ||
111 | + /* Indicate the eNVM is running at the configured divider rate */ | ||
112 | + val = BIT(6); | ||
113 | + break; | ||
114 | + default: | ||
115 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
116 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
117 | + __func__, size, offset); | ||
118 | + break; | ||
119 | + } | 524 | + } |
120 | + | 525 | + if (tot - cnt == 0) { |
121 | + return val; | 526 | + return ; |
122 | +} | 527 | + } |
123 | + | 528 | + memset(base + cnt, -1, tot - cnt); |
124 | +static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset, | 529 | +} |
125 | + uint64_t value, unsigned size) | 530 | + |
126 | +{ | 531 | +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, |
127 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | 532 | + CPURISCVState *env, uint32_t desc, |
128 | + "(size %d, value 0x%" PRIx64 | 533 | + opivv2_fn *fn, uint32_t esz) |
129 | + ", offset 0x%" HWADDR_PRIx ")\n", | 534 | +{ |
130 | + __func__, size, value, offset); | 535 | + uint32_t vm = vext_vm(desc); |
131 | +} | 536 | + uint32_t vl = env->vl; |
132 | + | 537 | + uint32_t total_elems = vext_get_total_elems(env, desc, esz); |
133 | +static const MemoryRegionOps mchp_pfsoc_sysreg_ops = { | 538 | + uint32_t vta = vext_vta(desc); |
134 | + .read = mchp_pfsoc_sysreg_read, | 539 | + uint32_t vma = vext_vma(desc); |
135 | + .write = mchp_pfsoc_sysreg_write, | 540 | + uint32_t i; |
136 | + .endianness = DEVICE_LITTLE_ENDIAN, | 541 | + |
137 | +}; | 542 | + for (i = env->vstart; i < vl; i++) { |
138 | + | 543 | + if (!vm && !vext_elem_mask(v0, i)) { |
139 | +static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp) | 544 | + /* set masked-off elements to 1s */ |
140 | +{ | 545 | + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); |
141 | + MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev); | 546 | + continue; |
142 | + | 547 | + } |
143 | + memory_region_init_io(&s->sysreg, OBJECT(dev), | 548 | + fn(vd, vs1, vs2, i); |
144 | + &mchp_pfsoc_sysreg_ops, s, | 549 | + } |
145 | + "mchp.pfsoc.sysreg", | 550 | + env->vstart = 0; |
146 | + MCHP_PFSOC_SYSREG_REG_SIZE); | 551 | + /* set tail elements to 1s */ |
147 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg); | 552 | + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); |
148 | +} | 553 | +} |
149 | + | 554 | + |
150 | +static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data) | 555 | +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, |
151 | +{ | 556 | + CPURISCVState *env, uint32_t desc, |
152 | + DeviceClass *dc = DEVICE_CLASS(klass); | 557 | + opivx2_fn fn, uint32_t esz) |
153 | + | 558 | +{ |
154 | + dc->desc = "Microchip PolarFire SoC SYSREG module"; | 559 | + uint32_t vm = vext_vm(desc); |
155 | + dc->realize = mchp_pfsoc_sysreg_realize; | 560 | + uint32_t vl = env->vl; |
156 | +} | 561 | + uint32_t total_elems = vext_get_total_elems(env, desc, esz); |
157 | + | 562 | + uint32_t vta = vext_vta(desc); |
158 | +static const TypeInfo mchp_pfsoc_sysreg_info = { | 563 | + uint32_t vma = vext_vma(desc); |
159 | + .name = TYPE_MCHP_PFSOC_SYSREG, | 564 | + uint32_t i; |
160 | + .parent = TYPE_SYS_BUS_DEVICE, | 565 | + |
161 | + .instance_size = sizeof(MchpPfSoCSysregState), | 566 | + for (i = env->vstart; i < vl; i++) { |
162 | + .class_init = mchp_pfsoc_sysreg_class_init, | 567 | + if (!vm && !vext_elem_mask(v0, i)) { |
163 | +}; | 568 | + /* set masked-off elements to 1s */ |
164 | + | 569 | + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); |
165 | +static void mchp_pfsoc_sysreg_register_types(void) | 570 | + continue; |
166 | +{ | 571 | + } |
167 | + type_register_static(&mchp_pfsoc_sysreg_info); | 572 | + fn(vd, s1, vs2, i); |
168 | +} | 573 | + } |
169 | + | 574 | + env->vstart = 0; |
170 | +type_init(mchp_pfsoc_sysreg_register_types) | 575 | + /* set tail elements to 1s */ |
171 | diff --git a/MAINTAINERS b/MAINTAINERS | 576 | + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); |
577 | +} | ||
578 | diff --git a/target/riscv/meson.build b/target/riscv/meson.build | ||
172 | index XXXXXXX..XXXXXXX 100644 | 579 | index XXXXXXX..XXXXXXX 100644 |
173 | --- a/MAINTAINERS | 580 | --- a/target/riscv/meson.build |
174 | +++ b/MAINTAINERS | 581 | +++ b/target/riscv/meson.build |
175 | @@ -XXX,XX +XXX,XX @@ F: hw/riscv/microchip_pfsoc.c | 582 | @@ -XXX,XX +XXX,XX @@ riscv_ss.add(files( |
176 | F: hw/char/mchp_pfsoc_mmuart.c | 583 | 'gdbstub.c', |
177 | F: hw/misc/mchp_pfsoc_dmc.c | 584 | 'op_helper.c', |
178 | F: hw/misc/mchp_pfsoc_ioscb.c | 585 | 'vector_helper.c', |
179 | +F: hw/misc/mchp_pfsoc_sysreg.c | 586 | + 'vector_internals.c', |
180 | F: include/hw/riscv/microchip_pfsoc.h | 587 | 'bitmanip_helper.c', |
181 | F: include/hw/char/mchp_pfsoc_mmuart.h | 588 | 'translate.c', |
182 | F: include/hw/misc/mchp_pfsoc_dmc.h | 589 | 'm128_helper.c', |
183 | F: include/hw/misc/mchp_pfsoc_ioscb.h | ||
184 | +F: include/hw/misc/mchp_pfsoc_sysreg.h | ||
185 | |||
186 | RX Machines | ||
187 | ----------- | ||
188 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
189 | index XXXXXXX..XXXXXXX 100644 | ||
190 | --- a/hw/misc/Kconfig | ||
191 | +++ b/hw/misc/Kconfig | ||
192 | @@ -XXX,XX +XXX,XX @@ config MCHP_PFSOC_DMC | ||
193 | config MCHP_PFSOC_IOSCB | ||
194 | bool | ||
195 | |||
196 | +config MCHP_PFSOC_SYSREG | ||
197 | + bool | ||
198 | + | ||
199 | config SIFIVE_TEST | ||
200 | bool | ||
201 | |||
202 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
203 | index XXXXXXX..XXXXXXX 100644 | ||
204 | --- a/hw/misc/meson.build | ||
205 | +++ b/hw/misc/meson.build | ||
206 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) | ||
207 | # RISC-V devices | ||
208 | softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) | ||
209 | softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c')) | ||
210 | +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c')) | ||
211 | softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) | ||
212 | softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) | ||
213 | softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) | ||
214 | -- | 590 | -- |
215 | 2.28.0 | 591 | 2.41.0 |
216 | |||
217 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
1 | 2 | ||
3 | Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into | ||
4 | function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be | ||
5 | used in proceeding vector-crypto commits. | ||
6 | |||
7 | Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
11 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
12 | Message-ID: <20230711165917.2629866-3-max.chou@sifive.com> | ||
13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | --- | ||
15 | target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------ | ||
16 | 1 file changed, 32 insertions(+), 30 deletions(-) | ||
17 | |||
18 | diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/riscv/insn_trans/trans_rvv.c.inc | ||
21 | +++ b/target/riscv/insn_trans/trans_rvv.c.inc | ||
22 | @@ -XXX,XX +XXX,XX @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx) | ||
23 | GEN_OPIWX_WIDEN_TRANS(vwsubu_wx) | ||
24 | GEN_OPIWX_WIDEN_TRANS(vwsub_wx) | ||
25 | |||
26 | +static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm, | ||
27 | + gen_helper_gvec_4_ptr *fn, DisasContext *s) | ||
28 | +{ | ||
29 | + uint32_t data = 0; | ||
30 | + TCGLabel *over = gen_new_label(); | ||
31 | + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
32 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
33 | + | ||
34 | + data = FIELD_DP32(data, VDATA, VM, vm); | ||
35 | + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); | ||
36 | + data = FIELD_DP32(data, VDATA, VTA, s->vta); | ||
37 | + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); | ||
38 | + data = FIELD_DP32(data, VDATA, VMA, s->vma); | ||
39 | + tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1), | ||
40 | + vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8, | ||
41 | + s->cfg_ptr->vlen / 8, data, fn); | ||
42 | + mark_vs_dirty(s); | ||
43 | + gen_set_label(over); | ||
44 | + return true; | ||
45 | +} | ||
46 | + | ||
47 | /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ | ||
48 | /* OPIVV without GVEC IR */ | ||
49 | -#define GEN_OPIVV_TRANS(NAME, CHECK) \ | ||
50 | -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
51 | -{ \ | ||
52 | - if (CHECK(s, a)) { \ | ||
53 | - uint32_t data = 0; \ | ||
54 | - static gen_helper_gvec_4_ptr * const fns[4] = { \ | ||
55 | - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ | ||
56 | - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ | ||
57 | - }; \ | ||
58 | - TCGLabel *over = gen_new_label(); \ | ||
59 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
60 | - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
61 | - \ | ||
62 | - data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
63 | - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ | ||
64 | - data = FIELD_DP32(data, VDATA, VTA, s->vta); \ | ||
65 | - data = \ | ||
66 | - FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ | ||
67 | - data = FIELD_DP32(data, VDATA, VMA, s->vma); \ | ||
68 | - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ | ||
69 | - vreg_ofs(s, a->rs1), \ | ||
70 | - vreg_ofs(s, a->rs2), cpu_env, \ | ||
71 | - s->cfg_ptr->vlen / 8, \ | ||
72 | - s->cfg_ptr->vlen / 8, data, \ | ||
73 | - fns[s->sew]); \ | ||
74 | - mark_vs_dirty(s); \ | ||
75 | - gen_set_label(over); \ | ||
76 | - return true; \ | ||
77 | - } \ | ||
78 | - return false; \ | ||
79 | +#define GEN_OPIVV_TRANS(NAME, CHECK) \ | ||
80 | +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
81 | +{ \ | ||
82 | + if (CHECK(s, a)) { \ | ||
83 | + static gen_helper_gvec_4_ptr * const fns[4] = { \ | ||
84 | + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ | ||
85 | + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ | ||
86 | + }; \ | ||
87 | + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ | ||
88 | + } \ | ||
89 | + return false; \ | ||
90 | } | ||
91 | |||
92 | /* | ||
93 | -- | ||
94 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
1 | 2 | ||
3 | Remove the redundant "vl == 0" check which is already included within the vstart >= vl check, when vl == 0. | ||
4 | |||
5 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
6 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
7 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
8 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-ID: <20230711165917.2629866-4-max.chou@sifive.com> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | target/riscv/insn_trans/trans_rvv.c.inc | 31 +------------------------ | ||
13 | 1 file changed, 1 insertion(+), 30 deletions(-) | ||
14 | |||
15 | diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/riscv/insn_trans/trans_rvv.c.inc | ||
18 | +++ b/target/riscv/insn_trans/trans_rvv.c.inc | ||
19 | @@ -XXX,XX +XXX,XX @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, | ||
20 | TCGv_i32 desc; | ||
21 | |||
22 | TCGLabel *over = gen_new_label(); | ||
23 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
24 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
25 | |||
26 | dest = tcg_temp_new_ptr(); | ||
27 | @@ -XXX,XX +XXX,XX @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, | ||
28 | TCGv_i32 desc; | ||
29 | |||
30 | TCGLabel *over = gen_new_label(); | ||
31 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
32 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
33 | |||
34 | dest = tcg_temp_new_ptr(); | ||
35 | @@ -XXX,XX +XXX,XX @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, | ||
36 | TCGv_i32 desc; | ||
37 | |||
38 | TCGLabel *over = gen_new_label(); | ||
39 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
40 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
41 | |||
42 | dest = tcg_temp_new_ptr(); | ||
43 | @@ -XXX,XX +XXX,XX @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, | ||
44 | TCGv_i32 desc; | ||
45 | |||
46 | TCGLabel *over = gen_new_label(); | ||
47 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
48 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
49 | |||
50 | dest = tcg_temp_new_ptr(); | ||
51 | @@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, | ||
52 | return false; | ||
53 | } | ||
54 | |||
55 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
56 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
57 | |||
58 | if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { | ||
59 | @@ -XXX,XX +XXX,XX @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, | ||
60 | uint32_t data = 0; | ||
61 | |||
62 | TCGLabel *over = gen_new_label(); | ||
63 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
64 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
65 | |||
66 | dest = tcg_temp_new_ptr(); | ||
67 | @@ -XXX,XX +XXX,XX @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, | ||
68 | uint32_t data = 0; | ||
69 | |||
70 | TCGLabel *over = gen_new_label(); | ||
71 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
72 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
73 | |||
74 | dest = tcg_temp_new_ptr(); | ||
75 | @@ -XXX,XX +XXX,XX @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, | ||
76 | if (checkfn(s, a)) { | ||
77 | uint32_t data = 0; | ||
78 | TCGLabel *over = gen_new_label(); | ||
79 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
80 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
81 | |||
82 | data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, | ||
84 | if (opiwv_widen_check(s, a)) { | ||
85 | uint32_t data = 0; | ||
86 | TCGLabel *over = gen_new_label(); | ||
87 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
88 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
89 | |||
90 | data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
91 | @@ -XXX,XX +XXX,XX @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm, | ||
92 | { | ||
93 | uint32_t data = 0; | ||
94 | TCGLabel *over = gen_new_label(); | ||
95 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
96 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
97 | |||
98 | data = FIELD_DP32(data, VDATA, VM, vm); | ||
99 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
100 | gen_helper_##NAME##_w, \ | ||
101 | }; \ | ||
102 | TCGLabel *over = gen_new_label(); \ | ||
103 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
104 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
105 | \ | ||
106 | data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
107 | @@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) | ||
108 | gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, | ||
109 | }; | ||
110 | TCGLabel *over = gen_new_label(); | ||
111 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
112 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
113 | |||
114 | tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), | ||
115 | @@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) | ||
116 | vext_check_ss(s, a->rd, 0, 1)) { | ||
117 | TCGv s1; | ||
118 | TCGLabel *over = gen_new_label(); | ||
119 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
120 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
121 | |||
122 | s1 = get_gpr(s, a->rs1, EXT_SIGN); | ||
123 | @@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) | ||
124 | gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, | ||
125 | }; | ||
126 | TCGLabel *over = gen_new_label(); | ||
127 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
128 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
129 | |||
130 | s1 = tcg_constant_i64(simm); | ||
131 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
132 | }; \ | ||
133 | TCGLabel *over = gen_new_label(); \ | ||
134 | gen_set_rm(s, RISCV_FRM_DYN); \ | ||
135 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
136 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
137 | \ | ||
138 | data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
139 | @@ -XXX,XX +XXX,XX @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, | ||
140 | TCGv_i64 t1; | ||
141 | |||
142 | TCGLabel *over = gen_new_label(); | ||
143 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
144 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
145 | |||
146 | dest = tcg_temp_new_ptr(); | ||
147 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
148 | }; \ | ||
149 | TCGLabel *over = gen_new_label(); \ | ||
150 | gen_set_rm(s, RISCV_FRM_DYN); \ | ||
151 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
152 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\ | ||
153 | \ | ||
154 | data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
155 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
156 | }; \ | ||
157 | TCGLabel *over = gen_new_label(); \ | ||
158 | gen_set_rm(s, RISCV_FRM_DYN); \ | ||
159 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
160 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
161 | \ | ||
162 | data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
163 | @@ -XXX,XX +XXX,XX @@ static bool do_opfv(DisasContext *s, arg_rmr *a, | ||
164 | uint32_t data = 0; | ||
165 | TCGLabel *over = gen_new_label(); | ||
166 | gen_set_rm_chkfrm(s, rm); | ||
167 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
168 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
169 | |||
170 | data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
171 | @@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) | ||
172 | gen_helper_vmv_v_x_d, | ||
173 | }; | ||
174 | TCGLabel *over = gen_new_label(); | ||
175 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
176 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
177 | |||
178 | t1 = tcg_temp_new_i64(); | ||
179 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
180 | }; \ | ||
181 | TCGLabel *over = gen_new_label(); \ | ||
182 | gen_set_rm_chkfrm(s, FRM); \ | ||
183 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
184 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
185 | \ | ||
186 | data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
187 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
188 | }; \ | ||
189 | TCGLabel *over = gen_new_label(); \ | ||
190 | gen_set_rm(s, RISCV_FRM_DYN); \ | ||
191 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
192 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
193 | \ | ||
194 | data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
195 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
196 | }; \ | ||
197 | TCGLabel *over = gen_new_label(); \ | ||
198 | gen_set_rm_chkfrm(s, FRM); \ | ||
199 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
200 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
201 | \ | ||
202 | data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
203 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
204 | }; \ | ||
205 | TCGLabel *over = gen_new_label(); \ | ||
206 | gen_set_rm_chkfrm(s, FRM); \ | ||
207 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
208 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
209 | \ | ||
210 | data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
211 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ | ||
212 | uint32_t data = 0; \ | ||
213 | gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \ | ||
214 | TCGLabel *over = gen_new_label(); \ | ||
215 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ | ||
216 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
217 | \ | ||
218 | data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ | ||
219 | @@ -XXX,XX +XXX,XX @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) | ||
220 | require_vm(a->vm, a->rd)) { | ||
221 | uint32_t data = 0; | ||
222 | TCGLabel *over = gen_new_label(); | ||
223 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
224 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
225 | |||
226 | data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
227 | @@ -XXX,XX +XXX,XX @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) | ||
228 | TCGv s1; | ||
229 | TCGLabel *over = gen_new_label(); | ||
230 | |||
231 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
232 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
233 | |||
234 | t1 = tcg_temp_new_i64(); | ||
235 | @@ -XXX,XX +XXX,XX @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) | ||
236 | TCGv_i64 t1; | ||
237 | TCGLabel *over = gen_new_label(); | ||
238 | |||
239 | - /* if vl == 0 or vstart >= vl, skip vector register write back */ | ||
240 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
241 | + /* if vstart >= vl, skip vector register write back */ | ||
242 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
243 | |||
244 | /* NaN-box f[rs1] */ | ||
245 | @@ -XXX,XX +XXX,XX @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq) | ||
246 | uint32_t data = 0; | ||
247 | gen_helper_gvec_3_ptr *fn; | ||
248 | TCGLabel *over = gen_new_label(); | ||
249 | - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); | ||
250 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
251 | |||
252 | static gen_helper_gvec_3_ptr * const fns[6][4] = { | ||
253 | -- | ||
254 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Yifei Jiang <jiangyifei@huawei.com> | 1 | From: Lawrence Hunter <lawrence.hunter@codethink.co.uk> |
---|---|---|---|
2 | 2 | ||
3 | Add basic CPU state description to the newly created machine.c | 3 | This commit adds support for the Zvbc vector-crypto extension, which |
4 | 4 | consists of the following instructions: | |
5 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | 5 | |
6 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | 6 | * vclmulh.[vx,vv] |
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | * vclmul.[vx,vv] |
8 | Message-id: 20201026115530.304-3-jiangyifei@huawei.com | 8 | |
9 | Translation functions are defined in | ||
10 | `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in | ||
11 | `target/riscv/vcrypto_helper.c`. | ||
12 | |||
13 | Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
14 | Co-authored-by: Max Chou <max.chou@sifive.com> | ||
15 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
16 | Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | ||
17 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
18 | [max.chou@sifive.com: Exposed x-zvbc property] | ||
19 | Message-ID: <20230711165917.2629866-5-max.chou@sifive.com> | ||
9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 20 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
10 | --- | 21 | --- |
11 | target/riscv/internals.h | 4 +++ | 22 | target/riscv/cpu_cfg.h | 1 + |
12 | target/riscv/cpu.c | 8 +---- | 23 | target/riscv/helper.h | 6 +++ |
13 | target/riscv/machine.c | 74 ++++++++++++++++++++++++++++++++++++++++ | 24 | target/riscv/insn32.decode | 6 +++ |
14 | target/riscv/meson.build | 3 +- | 25 | target/riscv/cpu.c | 9 ++++ |
15 | 4 files changed, 81 insertions(+), 8 deletions(-) | 26 | target/riscv/translate.c | 1 + |
16 | create mode 100644 target/riscv/machine.c | 27 | target/riscv/vcrypto_helper.c | 59 ++++++++++++++++++++++ |
17 | 28 | target/riscv/insn_trans/trans_rvvk.c.inc | 62 ++++++++++++++++++++++++ | |
18 | diff --git a/target/riscv/internals.h b/target/riscv/internals.h | 29 | target/riscv/meson.build | 3 +- |
19 | index XXXXXXX..XXXXXXX 100644 | 30 | 8 files changed, 146 insertions(+), 1 deletion(-) |
20 | --- a/target/riscv/internals.h | 31 | create mode 100644 target/riscv/vcrypto_helper.c |
21 | +++ b/target/riscv/internals.h | 32 | create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc |
22 | @@ -XXX,XX +XXX,XX @@ target_ulong fclass_d(uint64_t frs1); | 33 | |
23 | #define SEW32 2 | 34 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h |
24 | #define SEW64 3 | 35 | index XXXXXXX..XXXXXXX 100644 |
25 | 36 | --- a/target/riscv/cpu_cfg.h | |
26 | +#ifndef CONFIG_USER_ONLY | 37 | +++ b/target/riscv/cpu_cfg.h |
27 | +extern const VMStateDescription vmstate_riscv_cpu; | 38 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { |
28 | +#endif | 39 | bool ext_zve32f; |
29 | + | 40 | bool ext_zve64f; |
30 | static inline uint64_t nanbox_s(float32 f) | 41 | bool ext_zve64d; |
31 | { | 42 | + bool ext_zvbc; |
32 | return f | MAKE_64BIT_MASK(32, 32); | 43 | bool ext_zmmul; |
44 | bool ext_zvfbfmin; | ||
45 | bool ext_zvfbfwma; | ||
46 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/riscv/helper.h | ||
49 | +++ b/target/riscv/helper.h | ||
50 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, env, i32) | ||
51 | |||
52 | DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32) | ||
53 | DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32) | ||
54 | + | ||
55 | +/* Vector crypto functions */ | ||
56 | +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) | ||
57 | +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) | ||
58 | +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) | ||
59 | +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) | ||
60 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/riscv/insn32.decode | ||
63 | +++ b/target/riscv/insn32.decode | ||
64 | @@ -XXX,XX +XXX,XX @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 1010111 @r2_vm | ||
65 | # *** Zvfbfwma Standard Extension *** | ||
66 | vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm | ||
67 | vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm | ||
68 | + | ||
69 | +# *** Zvbc vector crypto extension *** | ||
70 | +vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm | ||
71 | +vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm | ||
72 | +vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm | ||
73 | +vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm | ||
33 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | 74 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
34 | index XXXXXXX..XXXXXXX 100644 | 75 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/riscv/cpu.c | 76 | --- a/target/riscv/cpu.c |
36 | +++ b/target/riscv/cpu.c | 77 | +++ b/target/riscv/cpu.c |
37 | @@ -XXX,XX +XXX,XX @@ | 78 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { |
38 | #include "qemu/ctype.h" | 79 | ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), |
39 | #include "qemu/log.h" | 80 | ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), |
40 | #include "cpu.h" | 81 | ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), |
41 | +#include "internals.h" | 82 | + ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), |
42 | #include "exec/exec-all.h" | 83 | ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), |
43 | #include "qapi/error.h" | 84 | ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), |
44 | #include "qemu/error-report.h" | 85 | ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), |
45 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj) | 86 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) |
46 | cpu_set_cpustate_pointers(cpu); | 87 | return; |
47 | } | 88 | } |
48 | 89 | ||
49 | -#ifndef CONFIG_USER_ONLY | 90 | + if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { |
50 | -static const VMStateDescription vmstate_riscv_cpu = { | 91 | + error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions"); |
51 | - .name = "cpu", | 92 | + return; |
52 | - .unmigratable = 1, | 93 | + } |
53 | -}; | 94 | + |
54 | -#endif | 95 | if (cpu->cfg.ext_zk) { |
55 | - | 96 | cpu->cfg.ext_zkn = true; |
56 | static Property riscv_cpu_properties[] = { | 97 | cpu->cfg.ext_zkr = true; |
57 | DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), | 98 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { |
58 | DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), | 99 | DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), |
59 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | 100 | DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), |
101 | |||
102 | + /* Vector cryptography extensions */ | ||
103 | + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), | ||
104 | + | ||
105 | DEFINE_PROP_END_OF_LIST(), | ||
106 | }; | ||
107 | |||
108 | diff --git a/target/riscv/translate.c b/target/riscv/translate.c | ||
109 | index XXXXXXX..XXXXXXX 100644 | ||
110 | --- a/target/riscv/translate.c | ||
111 | +++ b/target/riscv/translate.c | ||
112 | @@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) | ||
113 | #include "insn_trans/trans_rvzfa.c.inc" | ||
114 | #include "insn_trans/trans_rvzfh.c.inc" | ||
115 | #include "insn_trans/trans_rvk.c.inc" | ||
116 | +#include "insn_trans/trans_rvvk.c.inc" | ||
117 | #include "insn_trans/trans_privileged.c.inc" | ||
118 | #include "insn_trans/trans_svinval.c.inc" | ||
119 | #include "insn_trans/trans_rvbf16.c.inc" | ||
120 | diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c | ||
60 | new file mode 100644 | 121 | new file mode 100644 |
61 | index XXXXXXX..XXXXXXX | 122 | index XXXXXXX..XXXXXXX |
62 | --- /dev/null | 123 | --- /dev/null |
63 | +++ b/target/riscv/machine.c | 124 | +++ b/target/riscv/vcrypto_helper.c |
64 | @@ -XXX,XX +XXX,XX @@ | 125 | @@ -XXX,XX +XXX,XX @@ |
65 | +/* | 126 | +/* |
66 | + * RISC-V VMState Description | 127 | + * RISC-V Vector Crypto Extension Helpers for QEMU. |
67 | + * | 128 | + * |
68 | + * Copyright (c) 2020 Huawei Technologies Co., Ltd | 129 | + * Copyright (C) 2023 SiFive, Inc. |
130 | + * Written by Codethink Ltd and SiFive. | ||
69 | + * | 131 | + * |
70 | + * This program is free software; you can redistribute it and/or modify it | 132 | + * This program is free software; you can redistribute it and/or modify it |
71 | + * under the terms and conditions of the GNU General Public License, | 133 | + * under the terms and conditions of the GNU General Public License, |
72 | + * version 2 or later, as published by the Free Software Foundation. | 134 | + * version 2 or later, as published by the Free Software Foundation. |
73 | + * | 135 | + * |
... | ... | ||
79 | + * You should have received a copy of the GNU General Public License along with | 141 | + * You should have received a copy of the GNU General Public License along with |
80 | + * this program. If not, see <http://www.gnu.org/licenses/>. | 142 | + * this program. If not, see <http://www.gnu.org/licenses/>. |
81 | + */ | 143 | + */ |
82 | + | 144 | + |
83 | +#include "qemu/osdep.h" | 145 | +#include "qemu/osdep.h" |
146 | +#include "qemu/host-utils.h" | ||
147 | +#include "qemu/bitops.h" | ||
84 | +#include "cpu.h" | 148 | +#include "cpu.h" |
85 | +#include "qemu/error-report.h" | 149 | +#include "exec/memop.h" |
86 | +#include "sysemu/kvm.h" | 150 | +#include "exec/exec-all.h" |
87 | +#include "migration/cpu.h" | 151 | +#include "exec/helper-proto.h" |
88 | + | 152 | +#include "internals.h" |
89 | +const VMStateDescription vmstate_riscv_cpu = { | 153 | +#include "vector_internals.h" |
90 | + .name = "cpu", | 154 | + |
91 | + .version_id = 1, | 155 | +static uint64_t clmul64(uint64_t y, uint64_t x) |
92 | + .minimum_version_id = 1, | 156 | +{ |
93 | + .fields = (VMStateField[]) { | 157 | + uint64_t result = 0; |
94 | + VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), | 158 | + for (int j = 63; j >= 0; j--) { |
95 | + VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), | 159 | + if ((y >> j) & 1) { |
96 | + VMSTATE_UINTTL(env.pc, RISCVCPU), | 160 | + result ^= (x << j); |
97 | + VMSTATE_UINTTL(env.load_res, RISCVCPU), | 161 | + } |
98 | + VMSTATE_UINTTL(env.load_val, RISCVCPU), | 162 | + } |
99 | + VMSTATE_UINTTL(env.frm, RISCVCPU), | 163 | + return result; |
100 | + VMSTATE_UINTTL(env.badaddr, RISCVCPU), | 164 | +} |
101 | + VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), | 165 | + |
102 | + VMSTATE_UINTTL(env.priv_ver, RISCVCPU), | 166 | +static uint64_t clmulh64(uint64_t y, uint64_t x) |
103 | + VMSTATE_UINTTL(env.vext_ver, RISCVCPU), | 167 | +{ |
104 | + VMSTATE_UINTTL(env.misa, RISCVCPU), | 168 | + uint64_t result = 0; |
105 | + VMSTATE_UINTTL(env.misa_mask, RISCVCPU), | 169 | + for (int j = 63; j >= 1; j--) { |
106 | + VMSTATE_UINT32(env.features, RISCVCPU), | 170 | + if ((y >> j) & 1) { |
107 | + VMSTATE_UINTTL(env.priv, RISCVCPU), | 171 | + result ^= (x >> (64 - j)); |
108 | + VMSTATE_UINTTL(env.virt, RISCVCPU), | 172 | + } |
109 | + VMSTATE_UINTTL(env.resetvec, RISCVCPU), | 173 | + } |
110 | + VMSTATE_UINTTL(env.mhartid, RISCVCPU), | 174 | + return result; |
111 | + VMSTATE_UINT64(env.mstatus, RISCVCPU), | 175 | +} |
112 | + VMSTATE_UINTTL(env.mip, RISCVCPU), | 176 | + |
113 | + VMSTATE_UINT32(env.miclaim, RISCVCPU), | 177 | +RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64) |
114 | + VMSTATE_UINTTL(env.mie, RISCVCPU), | 178 | +GEN_VEXT_VV(vclmul_vv, 8) |
115 | + VMSTATE_UINTTL(env.mideleg, RISCVCPU), | 179 | +RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64) |
116 | + VMSTATE_UINTTL(env.sptbr, RISCVCPU), | 180 | +GEN_VEXT_VX(vclmul_vx, 8) |
117 | + VMSTATE_UINTTL(env.satp, RISCVCPU), | 181 | +RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64) |
118 | + VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), | 182 | +GEN_VEXT_VV(vclmulh_vv, 8) |
119 | + VMSTATE_UINTTL(env.mbadaddr, RISCVCPU), | 183 | +RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) |
120 | + VMSTATE_UINTTL(env.medeleg, RISCVCPU), | 184 | +GEN_VEXT_VX(vclmulh_vx, 8) |
121 | + VMSTATE_UINTTL(env.stvec, RISCVCPU), | 185 | diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc |
122 | + VMSTATE_UINTTL(env.sepc, RISCVCPU), | 186 | new file mode 100644 |
123 | + VMSTATE_UINTTL(env.scause, RISCVCPU), | 187 | index XXXXXXX..XXXXXXX |
124 | + VMSTATE_UINTTL(env.mtvec, RISCVCPU), | 188 | --- /dev/null |
125 | + VMSTATE_UINTTL(env.mepc, RISCVCPU), | 189 | +++ b/target/riscv/insn_trans/trans_rvvk.c.inc |
126 | + VMSTATE_UINTTL(env.mcause, RISCVCPU), | 190 | @@ -XXX,XX +XXX,XX @@ |
127 | + VMSTATE_UINTTL(env.mtval, RISCVCPU), | 191 | +/* |
128 | + VMSTATE_UINTTL(env.scounteren, RISCVCPU), | 192 | + * RISC-V translation routines for the vector crypto extension. |
129 | + VMSTATE_UINTTL(env.mcounteren, RISCVCPU), | 193 | + * |
130 | + VMSTATE_UINTTL(env.sscratch, RISCVCPU), | 194 | + * Copyright (C) 2023 SiFive, Inc. |
131 | + VMSTATE_UINTTL(env.mscratch, RISCVCPU), | 195 | + * Written by Codethink Ltd and SiFive. |
132 | + VMSTATE_UINT64(env.mfromhost, RISCVCPU), | 196 | + * |
133 | + VMSTATE_UINT64(env.mtohost, RISCVCPU), | 197 | + * This program is free software; you can redistribute it and/or modify it |
134 | + VMSTATE_UINT64(env.timecmp, RISCVCPU), | 198 | + * under the terms and conditions of the GNU General Public License, |
135 | + | 199 | + * version 2 or later, as published by the Free Software Foundation. |
136 | + VMSTATE_END_OF_LIST() | 200 | + * |
137 | + } | 201 | + * This program is distributed in the hope it will be useful, but WITHOUT |
138 | +}; | 202 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
203 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
204 | + * more details. | ||
205 | + * | ||
206 | + * You should have received a copy of the GNU General Public License along with | ||
207 | + * this program. If not, see <http://www.gnu.org/licenses/>. | ||
208 | + */ | ||
209 | + | ||
210 | +/* | ||
211 | + * Zvbc | ||
212 | + */ | ||
213 | + | ||
214 | +#define GEN_VV_MASKED_TRANS(NAME, CHECK) \ | ||
215 | + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
216 | + { \ | ||
217 | + if (CHECK(s, a)) { \ | ||
218 | + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \ | ||
219 | + gen_helper_##NAME, s); \ | ||
220 | + } \ | ||
221 | + return false; \ | ||
222 | + } | ||
223 | + | ||
224 | +static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) | ||
225 | +{ | ||
226 | + return opivv_check(s, a) && | ||
227 | + s->cfg_ptr->ext_zvbc == true && | ||
228 | + s->sew == MO_64; | ||
229 | +} | ||
230 | + | ||
231 | +GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) | ||
232 | +GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check) | ||
233 | + | ||
234 | +#define GEN_VX_MASKED_TRANS(NAME, CHECK) \ | ||
235 | + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
236 | + { \ | ||
237 | + if (CHECK(s, a)) { \ | ||
238 | + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ | ||
239 | + gen_helper_##NAME, s); \ | ||
240 | + } \ | ||
241 | + return false; \ | ||
242 | + } | ||
243 | + | ||
244 | +static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) | ||
245 | +{ | ||
246 | + return opivx_check(s, a) && | ||
247 | + s->cfg_ptr->ext_zvbc == true && | ||
248 | + s->sew == MO_64; | ||
249 | +} | ||
250 | + | ||
251 | +GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) | ||
252 | +GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) | ||
139 | diff --git a/target/riscv/meson.build b/target/riscv/meson.build | 253 | diff --git a/target/riscv/meson.build b/target/riscv/meson.build |
140 | index XXXXXXX..XXXXXXX 100644 | 254 | index XXXXXXX..XXXXXXX 100644 |
141 | --- a/target/riscv/meson.build | 255 | --- a/target/riscv/meson.build |
142 | +++ b/target/riscv/meson.build | 256 | +++ b/target/riscv/meson.build |
143 | @@ -XXX,XX +XXX,XX @@ riscv_ss.add(files( | 257 | @@ -XXX,XX +XXX,XX @@ riscv_ss.add(files( |
144 | riscv_softmmu_ss = ss.source_set() | 258 | 'translate.c', |
145 | riscv_softmmu_ss.add(files( | 259 | 'm128_helper.c', |
146 | 'pmp.c', | 260 | 'crypto_helper.c', |
147 | - 'monitor.c' | 261 | - 'zce_helper.c' |
148 | + 'monitor.c', | 262 | + 'zce_helper.c', |
149 | + 'machine.c' | 263 | + 'vcrypto_helper.c' |
150 | )) | 264 | )) |
151 | 265 | riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) | |
152 | target_arch += {'riscv': riscv_ss} | 266 | |
153 | -- | 267 | -- |
154 | 2.28.0 | 268 | 2.41.0 |
155 | |||
156 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
1 | 2 | ||
3 | Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions | ||
4 | and into the corresponding macros. This enables the functions to be | ||
5 | reused in proceeding commits without check duplication. | ||
6 | |||
7 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
10 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
11 | Message-ID: <20230711165917.2629866-6-max.chou@sifive.com> | ||
12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | --- | ||
14 | target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++-------------- | ||
15 | 1 file changed, 12 insertions(+), 16 deletions(-) | ||
16 | |||
17 | diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/riscv/insn_trans/trans_rvv.c.inc | ||
20 | +++ b/target/riscv/insn_trans/trans_rvv.c.inc | ||
21 | @@ -XXX,XX +XXX,XX @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, | ||
22 | gen_helper_gvec_4_ptr *fn) | ||
23 | { | ||
24 | TCGLabel *over = gen_new_label(); | ||
25 | - if (!opivv_check(s, a)) { | ||
26 | - return false; | ||
27 | - } | ||
28 | |||
29 | tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
32 | gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ | ||
33 | gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ | ||
34 | }; \ | ||
35 | + if (!opivv_check(s, a)) { \ | ||
36 | + return false; \ | ||
37 | + } \ | ||
38 | return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ | ||
39 | } | ||
40 | |||
41 | @@ -XXX,XX +XXX,XX @@ static inline bool | ||
42 | do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, | ||
43 | gen_helper_opivx *fn) | ||
44 | { | ||
45 | - if (!opivx_check(s, a)) { | ||
46 | - return false; | ||
47 | - } | ||
48 | - | ||
49 | if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { | ||
50 | TCGv_i64 src1 = tcg_temp_new_i64(); | ||
51 | |||
52 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
53 | gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ | ||
54 | gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ | ||
55 | }; \ | ||
56 | + if (!opivx_check(s, a)) { \ | ||
57 | + return false; \ | ||
58 | + } \ | ||
59 | return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ | ||
60 | } | ||
61 | |||
62 | @@ -XXX,XX +XXX,XX @@ static inline bool | ||
63 | do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, | ||
64 | gen_helper_opivx *fn, imm_mode_t imm_mode) | ||
65 | { | ||
66 | - if (!opivx_check(s, a)) { | ||
67 | - return false; | ||
68 | - } | ||
69 | - | ||
70 | if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { | ||
71 | gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), | ||
72 | extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); | ||
73 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
74 | gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ | ||
75 | gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ | ||
76 | }; \ | ||
77 | + if (!opivx_check(s, a)) { \ | ||
78 | + return false; \ | ||
79 | + } \ | ||
80 | return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ | ||
81 | fns[s->sew], IMM_MODE); \ | ||
82 | } | ||
83 | @@ -XXX,XX +XXX,XX @@ static inline bool | ||
84 | do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, | ||
85 | gen_helper_opivx *fn) | ||
86 | { | ||
87 | - if (!opivx_check(s, a)) { | ||
88 | - return false; | ||
89 | - } | ||
90 | - | ||
91 | if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { | ||
92 | TCGv_i32 src1 = tcg_temp_new_i32(); | ||
93 | |||
94 | @@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
95 | gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ | ||
96 | gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ | ||
97 | }; \ | ||
98 | - \ | ||
99 | + if (!opivx_check(s, a)) { \ | ||
100 | + return false; \ | ||
101 | + } \ | ||
102 | return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ | ||
103 | } | ||
104 | |||
105 | -- | ||
106 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Dickon Hood <dickon.hood@codethink.co.uk> | ||
1 | 2 | ||
3 | Zvbb (implemented in later commit) has a widening instruction, which | ||
4 | requires an extra check on the enabled extensions. Refactor | ||
5 | GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing | ||
6 | it. | ||
7 | |||
8 | Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
11 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
12 | Message-ID: <20230711165917.2629866-7-max.chou@sifive.com> | ||
13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | --- | ||
15 | target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++-------------- | ||
16 | 1 file changed, 23 insertions(+), 29 deletions(-) | ||
17 | |||
18 | diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/riscv/insn_trans/trans_rvv.c.inc | ||
21 | +++ b/target/riscv/insn_trans/trans_rvv.c.inc | ||
22 | @@ -XXX,XX +XXX,XX @@ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a) | ||
23 | vext_check_ds(s, a->rd, a->rs2, a->vm); | ||
24 | } | ||
25 | |||
26 | -static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, | ||
27 | - gen_helper_opivx *fn) | ||
28 | -{ | ||
29 | - if (opivx_widen_check(s, a)) { | ||
30 | - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); | ||
31 | - } | ||
32 | - return false; | ||
33 | -} | ||
34 | - | ||
35 | -#define GEN_OPIVX_WIDEN_TRANS(NAME) \ | ||
36 | -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
37 | -{ \ | ||
38 | - static gen_helper_opivx * const fns[3] = { \ | ||
39 | - gen_helper_##NAME##_b, \ | ||
40 | - gen_helper_##NAME##_h, \ | ||
41 | - gen_helper_##NAME##_w \ | ||
42 | - }; \ | ||
43 | - return do_opivx_widen(s, a, fns[s->sew]); \ | ||
44 | +#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \ | ||
45 | +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
46 | +{ \ | ||
47 | + if (CHECK(s, a)) { \ | ||
48 | + static gen_helper_opivx * const fns[3] = { \ | ||
49 | + gen_helper_##NAME##_b, \ | ||
50 | + gen_helper_##NAME##_h, \ | ||
51 | + gen_helper_##NAME##_w \ | ||
52 | + }; \ | ||
53 | + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); \ | ||
54 | + } \ | ||
55 | + return false; \ | ||
56 | } | ||
57 | |||
58 | -GEN_OPIVX_WIDEN_TRANS(vwaddu_vx) | ||
59 | -GEN_OPIVX_WIDEN_TRANS(vwadd_vx) | ||
60 | -GEN_OPIVX_WIDEN_TRANS(vwsubu_vx) | ||
61 | -GEN_OPIVX_WIDEN_TRANS(vwsub_vx) | ||
62 | +GEN_OPIVX_WIDEN_TRANS(vwaddu_vx, opivx_widen_check) | ||
63 | +GEN_OPIVX_WIDEN_TRANS(vwadd_vx, opivx_widen_check) | ||
64 | +GEN_OPIVX_WIDEN_TRANS(vwsubu_vx, opivx_widen_check) | ||
65 | +GEN_OPIVX_WIDEN_TRANS(vwsub_vx, opivx_widen_check) | ||
66 | |||
67 | /* WIDEN OPIVV with WIDEN */ | ||
68 | static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) | ||
69 | @@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vrem_vx, opivx_check) | ||
70 | GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check) | ||
71 | GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check) | ||
72 | GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) | ||
73 | -GEN_OPIVX_WIDEN_TRANS(vwmul_vx) | ||
74 | -GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) | ||
75 | -GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) | ||
76 | +GEN_OPIVX_WIDEN_TRANS(vwmul_vx, opivx_widen_check) | ||
77 | +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx, opivx_widen_check) | ||
78 | +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx, opivx_widen_check) | ||
79 | |||
80 | /* Vector Single-Width Integer Multiply-Add Instructions */ | ||
81 | GEN_OPIVV_TRANS(vmacc_vv, opivv_check) | ||
82 | @@ -XXX,XX +XXX,XX @@ GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) | ||
83 | GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) | ||
84 | GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) | ||
85 | GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) | ||
86 | -GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) | ||
87 | -GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) | ||
88 | -GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) | ||
89 | -GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) | ||
90 | +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check) | ||
91 | +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check) | ||
92 | +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check) | ||
93 | +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check) | ||
94 | |||
95 | /* Vector Integer Merge and Move Instructions */ | ||
96 | static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) | ||
97 | -- | ||
98 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
1 | 2 | ||
3 | Move some macros out of `vector_helper` and into `vector_internals`. | ||
4 | This ensures they can be used by both vector and vector-crypto helpers | ||
5 | (latter implemented in proceeding commits). | ||
6 | |||
7 | Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
8 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
9 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
10 | Message-ID: <20230711165917.2629866-8-max.chou@sifive.com> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | --- | ||
13 | target/riscv/vector_internals.h | 46 +++++++++++++++++++++++++++++++++ | ||
14 | target/riscv/vector_helper.c | 42 ------------------------------ | ||
15 | 2 files changed, 46 insertions(+), 42 deletions(-) | ||
16 | |||
17 | diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/riscv/vector_internals.h | ||
20 | +++ b/target/riscv/vector_internals.h | ||
21 | @@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, | ||
22 | /* expand macro args before macro */ | ||
23 | #define RVVCALL(macro, ...) macro(__VA_ARGS__) | ||
24 | |||
25 | +/* (TD, T2, TX2) */ | ||
26 | +#define OP_UU_B uint8_t, uint8_t, uint8_t | ||
27 | +#define OP_UU_H uint16_t, uint16_t, uint16_t | ||
28 | +#define OP_UU_W uint32_t, uint32_t, uint32_t | ||
29 | +#define OP_UU_D uint64_t, uint64_t, uint64_t | ||
30 | + | ||
31 | /* (TD, T1, T2, TX1, TX2) */ | ||
32 | #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t | ||
33 | #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t | ||
34 | #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t | ||
35 | #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t | ||
36 | |||
37 | +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ | ||
38 | +static void do_##NAME(void *vd, void *vs2, int i) \ | ||
39 | +{ \ | ||
40 | + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ | ||
41 | + *((TD *)vd + HD(i)) = OP(s2); \ | ||
42 | +} | ||
43 | + | ||
44 | +#define GEN_VEXT_V(NAME, ESZ) \ | ||
45 | +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ | ||
46 | + CPURISCVState *env, uint32_t desc) \ | ||
47 | +{ \ | ||
48 | + uint32_t vm = vext_vm(desc); \ | ||
49 | + uint32_t vl = env->vl; \ | ||
50 | + uint32_t total_elems = \ | ||
51 | + vext_get_total_elems(env, desc, ESZ); \ | ||
52 | + uint32_t vta = vext_vta(desc); \ | ||
53 | + uint32_t vma = vext_vma(desc); \ | ||
54 | + uint32_t i; \ | ||
55 | + \ | ||
56 | + for (i = env->vstart; i < vl; i++) { \ | ||
57 | + if (!vm && !vext_elem_mask(v0, i)) { \ | ||
58 | + /* set masked-off elements to 1s */ \ | ||
59 | + vext_set_elems_1s(vd, vma, i * ESZ, \ | ||
60 | + (i + 1) * ESZ); \ | ||
61 | + continue; \ | ||
62 | + } \ | ||
63 | + do_##NAME(vd, vs2, i); \ | ||
64 | + } \ | ||
65 | + env->vstart = 0; \ | ||
66 | + /* set tail elements to 1s */ \ | ||
67 | + vext_set_elems_1s(vd, vta, vl * ESZ, \ | ||
68 | + total_elems * ESZ); \ | ||
69 | +} | ||
70 | + | ||
71 | /* operation of two vector elements */ | ||
72 | typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); | ||
73 | |||
74 | @@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ | ||
75 | do_##NAME, ESZ); \ | ||
76 | } | ||
77 | |||
78 | +/* Three of the widening shortening macros: */ | ||
79 | +/* (TD, T1, T2, TX1, TX2) */ | ||
80 | +#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t | ||
81 | +#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t | ||
82 | +#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t | ||
83 | + | ||
84 | #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ | ||
85 | diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/target/riscv/vector_helper.c | ||
88 | +++ b/target/riscv/vector_helper.c | ||
89 | @@ -XXX,XX +XXX,XX @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) | ||
90 | #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t | ||
91 | #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t | ||
92 | #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t | ||
93 | -#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t | ||
94 | -#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t | ||
95 | -#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t | ||
96 | #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t | ||
97 | #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t | ||
98 | #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t | ||
99 | @@ -XXX,XX +XXX,XX @@ GEN_VEXT_VF(vfwnmsac_vf_h, 4) | ||
100 | GEN_VEXT_VF(vfwnmsac_vf_w, 8) | ||
101 | |||
102 | /* Vector Floating-Point Square-Root Instruction */ | ||
103 | -/* (TD, T2, TX2) */ | ||
104 | -#define OP_UU_H uint16_t, uint16_t, uint16_t | ||
105 | -#define OP_UU_W uint32_t, uint32_t, uint32_t | ||
106 | -#define OP_UU_D uint64_t, uint64_t, uint64_t | ||
107 | - | ||
108 | #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ | ||
109 | static void do_##NAME(void *vd, void *vs2, int i, \ | ||
110 | CPURISCVState *env) \ | ||
111 | @@ -XXX,XX +XXX,XX @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) | ||
112 | GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) | ||
113 | |||
114 | /* Vector Floating-Point Classify Instruction */ | ||
115 | -#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ | ||
116 | -static void do_##NAME(void *vd, void *vs2, int i) \ | ||
117 | -{ \ | ||
118 | - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ | ||
119 | - *((TD *)vd + HD(i)) = OP(s2); \ | ||
120 | -} | ||
121 | - | ||
122 | -#define GEN_VEXT_V(NAME, ESZ) \ | ||
123 | -void HELPER(NAME)(void *vd, void *v0, void *vs2, \ | ||
124 | - CPURISCVState *env, uint32_t desc) \ | ||
125 | -{ \ | ||
126 | - uint32_t vm = vext_vm(desc); \ | ||
127 | - uint32_t vl = env->vl; \ | ||
128 | - uint32_t total_elems = \ | ||
129 | - vext_get_total_elems(env, desc, ESZ); \ | ||
130 | - uint32_t vta = vext_vta(desc); \ | ||
131 | - uint32_t vma = vext_vma(desc); \ | ||
132 | - uint32_t i; \ | ||
133 | - \ | ||
134 | - for (i = env->vstart; i < vl; i++) { \ | ||
135 | - if (!vm && !vext_elem_mask(v0, i)) { \ | ||
136 | - /* set masked-off elements to 1s */ \ | ||
137 | - vext_set_elems_1s(vd, vma, i * ESZ, \ | ||
138 | - (i + 1) * ESZ); \ | ||
139 | - continue; \ | ||
140 | - } \ | ||
141 | - do_##NAME(vd, vs2, i); \ | ||
142 | - } \ | ||
143 | - env->vstart = 0; \ | ||
144 | - /* set tail elements to 1s */ \ | ||
145 | - vext_set_elems_1s(vd, vta, vl * ESZ, \ | ||
146 | - total_elems * ESZ); \ | ||
147 | -} | ||
148 | - | ||
149 | target_ulong fclass_h(uint64_t frs1) | ||
150 | { | ||
151 | float16 f = frs1; | ||
152 | -- | ||
153 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Dickon Hood <dickon.hood@codethink.co.uk> |
---|---|---|---|
2 | 2 | ||
3 | The PolarFire SoC DDR Memory Controller mainly includes 2 modules, | 3 | This commit adds support for the Zvbb vector-crypto extension, which |
4 | called SGMII PHY module and the CFG module, as documented in the | 4 | consists of the following instructions: |
5 | chipset datasheet. | ||
6 | 5 | ||
7 | This creates a single file that groups these 2 modules, providing | 6 | * vrol.[vv,vx] |
8 | the minimum functionalities that make the HSS DDR initialization | 7 | * vror.[vv,vx,vi] |
9 | codes happy. | 8 | * vbrev8.v |
9 | * vrev8.v | ||
10 | * vandn.[vv,vx] | ||
11 | * vbrev.v | ||
12 | * vclz.v | ||
13 | * vctz.v | ||
14 | * vcpop.v | ||
15 | * vwsll.[vv,vx,vi] | ||
10 | 16 | ||
11 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 17 | Translation functions are defined in |
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 18 | `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in |
13 | Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com | 19 | `target/riscv/vcrypto_helper.c`. |
20 | |||
21 | Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
22 | Co-authored-by: William Salmon <will.salmon@codethink.co.uk> | ||
23 | Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
24 | [max.chou@sifive.com: Fix imm mode of vror.vi] | ||
25 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
26 | Signed-off-by: William Salmon <will.salmon@codethink.co.uk> | ||
27 | Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
28 | Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk> | ||
29 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
30 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
31 | [max.chou@sifive.com: Exposed x-zvbb property] | ||
32 | Message-ID: <20230711165917.2629866-9-max.chou@sifive.com> | ||
14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 33 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
15 | --- | 34 | --- |
16 | include/hw/misc/mchp_pfsoc_dmc.h | 56 ++++++++ | 35 | target/riscv/cpu_cfg.h | 1 + |
17 | hw/misc/mchp_pfsoc_dmc.c | 216 +++++++++++++++++++++++++++++++ | 36 | target/riscv/helper.h | 62 +++++++++ |
18 | MAINTAINERS | 2 + | 37 | target/riscv/insn32.decode | 20 +++ |
19 | hw/misc/Kconfig | 3 + | 38 | target/riscv/cpu.c | 12 ++ |
20 | hw/misc/meson.build | 1 + | 39 | target/riscv/vcrypto_helper.c | 138 +++++++++++++++++++ |
21 | 5 files changed, 278 insertions(+) | 40 | target/riscv/insn_trans/trans_rvvk.c.inc | 164 +++++++++++++++++++++++ |
22 | create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h | 41 | 6 files changed, 397 insertions(+) |
23 | create mode 100644 hw/misc/mchp_pfsoc_dmc.c | ||
24 | 42 | ||
25 | diff --git a/include/hw/misc/mchp_pfsoc_dmc.h b/include/hw/misc/mchp_pfsoc_dmc.h | 43 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h |
26 | new file mode 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
27 | index XXXXXXX..XXXXXXX | 45 | --- a/target/riscv/cpu_cfg.h |
28 | --- /dev/null | 46 | +++ b/target/riscv/cpu_cfg.h |
29 | +++ b/include/hw/misc/mchp_pfsoc_dmc.h | 47 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { |
48 | bool ext_zve32f; | ||
49 | bool ext_zve64f; | ||
50 | bool ext_zve64d; | ||
51 | + bool ext_zvbb; | ||
52 | bool ext_zvbc; | ||
53 | bool ext_zmmul; | ||
54 | bool ext_zvfbfmin; | ||
55 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/riscv/helper.h | ||
58 | +++ b/target/riscv/helper.h | ||
59 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) | ||
60 | DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) | ||
61 | DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) | ||
62 | DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) | ||
63 | + | ||
64 | +DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32) | ||
65 | +DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32) | ||
66 | +DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32) | ||
67 | +DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32) | ||
68 | + | ||
69 | +DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32) | ||
70 | +DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32) | ||
71 | +DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32) | ||
72 | +DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32) | ||
73 | + | ||
74 | +DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32) | ||
75 | +DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32) | ||
76 | +DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32) | ||
77 | +DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32) | ||
78 | + | ||
79 | +DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32) | ||
80 | +DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) | ||
81 | +DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) | ||
82 | +DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) | ||
83 | + | ||
84 | +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) | ||
85 | +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) | ||
86 | +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) | ||
87 | +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) | ||
88 | +DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) | ||
89 | +DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) | ||
90 | +DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) | ||
91 | +DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) | ||
92 | +DEF_HELPER_5(vbrev_v_b, void, ptr, ptr, ptr, env, i32) | ||
93 | +DEF_HELPER_5(vbrev_v_h, void, ptr, ptr, ptr, env, i32) | ||
94 | +DEF_HELPER_5(vbrev_v_w, void, ptr, ptr, ptr, env, i32) | ||
95 | +DEF_HELPER_5(vbrev_v_d, void, ptr, ptr, ptr, env, i32) | ||
96 | + | ||
97 | +DEF_HELPER_5(vclz_v_b, void, ptr, ptr, ptr, env, i32) | ||
98 | +DEF_HELPER_5(vclz_v_h, void, ptr, ptr, ptr, env, i32) | ||
99 | +DEF_HELPER_5(vclz_v_w, void, ptr, ptr, ptr, env, i32) | ||
100 | +DEF_HELPER_5(vclz_v_d, void, ptr, ptr, ptr, env, i32) | ||
101 | +DEF_HELPER_5(vctz_v_b, void, ptr, ptr, ptr, env, i32) | ||
102 | +DEF_HELPER_5(vctz_v_h, void, ptr, ptr, ptr, env, i32) | ||
103 | +DEF_HELPER_5(vctz_v_w, void, ptr, ptr, ptr, env, i32) | ||
104 | +DEF_HELPER_5(vctz_v_d, void, ptr, ptr, ptr, env, i32) | ||
105 | +DEF_HELPER_5(vcpop_v_b, void, ptr, ptr, ptr, env, i32) | ||
106 | +DEF_HELPER_5(vcpop_v_h, void, ptr, ptr, ptr, env, i32) | ||
107 | +DEF_HELPER_5(vcpop_v_w, void, ptr, ptr, ptr, env, i32) | ||
108 | +DEF_HELPER_5(vcpop_v_d, void, ptr, ptr, ptr, env, i32) | ||
109 | + | ||
110 | +DEF_HELPER_6(vwsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32) | ||
111 | +DEF_HELPER_6(vwsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32) | ||
112 | +DEF_HELPER_6(vwsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32) | ||
113 | +DEF_HELPER_6(vwsll_vx_b, void, ptr, ptr, tl, ptr, env, i32) | ||
114 | +DEF_HELPER_6(vwsll_vx_h, void, ptr, ptr, tl, ptr, env, i32) | ||
115 | +DEF_HELPER_6(vwsll_vx_w, void, ptr, ptr, tl, ptr, env, i32) | ||
116 | + | ||
117 | +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32) | ||
118 | +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32) | ||
119 | +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32) | ||
120 | +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32) | ||
121 | +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) | ||
122 | +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) | ||
123 | +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) | ||
124 | +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) | ||
125 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
126 | index XXXXXXX..XXXXXXX 100644 | ||
127 | --- a/target/riscv/insn32.decode | ||
128 | +++ b/target/riscv/insn32.decode | ||
30 | @@ -XXX,XX +XXX,XX @@ | 129 | @@ -XXX,XX +XXX,XX @@ |
31 | +/* | 130 | %imm_u 12:s20 !function=ex_shift_12 |
32 | + * Microchip PolarFire SoC DDR Memory Controller module emulation | 131 | %imm_bs 30:2 !function=ex_shift_3 |
33 | + * | 132 | %imm_rnum 20:4 |
34 | + * Copyright (c) 2020 Wind River Systems, Inc. | 133 | +%imm_z6 26:1 15:5 |
35 | + * | 134 | |
36 | + * Author: | 135 | # Argument sets: |
37 | + * Bin Meng <bin.meng@windriver.com> | 136 | &empty |
38 | + * | ||
39 | + * This program is free software; you can redistribute it and/or | ||
40 | + * modify it under the terms of the GNU General Public License as | ||
41 | + * published by the Free Software Foundation; either version 2 or | ||
42 | + * (at your option) version 3 of the License. | ||
43 | + * | ||
44 | + * This program is distributed in the hope that it will be useful, | ||
45 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
46 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
47 | + * GNU General Public License for more details. | ||
48 | + * | ||
49 | + * You should have received a copy of the GNU General Public License along | ||
50 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
51 | + */ | ||
52 | + | ||
53 | +#ifndef MCHP_PFSOC_DMC_H | ||
54 | +#define MCHP_PFSOC_DMC_H | ||
55 | + | ||
56 | +/* DDR SGMII PHY module */ | ||
57 | + | ||
58 | +#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000 | ||
59 | + | ||
60 | +typedef struct MchpPfSoCDdrSgmiiPhyState { | ||
61 | + SysBusDevice parent; | ||
62 | + MemoryRegion sgmii_phy; | ||
63 | +} MchpPfSoCDdrSgmiiPhyState; | ||
64 | + | ||
65 | +#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy" | ||
66 | + | ||
67 | +#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \ | ||
68 | + OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \ | ||
69 | + TYPE_MCHP_PFSOC_DDR_SGMII_PHY) | ||
70 | + | ||
71 | +/* DDR CFG module */ | ||
72 | + | ||
73 | +#define MCHP_PFSOC_DDR_CFG_REG_SIZE 0x40000 | ||
74 | + | ||
75 | +typedef struct MchpPfSoCDdrCfgState { | ||
76 | + SysBusDevice parent; | ||
77 | + MemoryRegion cfg; | ||
78 | +} MchpPfSoCDdrCfgState; | ||
79 | + | ||
80 | +#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg" | ||
81 | + | ||
82 | +#define MCHP_PFSOC_DDR_CFG(obj) \ | ||
83 | + OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \ | ||
84 | + TYPE_MCHP_PFSOC_DDR_CFG) | ||
85 | + | ||
86 | +#endif /* MCHP_PFSOC_DMC_H */ | ||
87 | diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c | ||
88 | new file mode 100644 | ||
89 | index XXXXXXX..XXXXXXX | ||
90 | --- /dev/null | ||
91 | +++ b/hw/misc/mchp_pfsoc_dmc.c | ||
92 | @@ -XXX,XX +XXX,XX @@ | 137 | @@ -XXX,XX +XXX,XX @@ |
93 | +/* | 138 | @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd |
94 | + * Microchip PolarFire SoC DDR Memory Controller module emulation | 139 | @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd |
95 | + * | 140 | @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd |
96 | + * Copyright (c) 2020 Wind River Systems, Inc. | 141 | +@r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=%imm_z6 %rd |
97 | + * | 142 | @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd |
98 | + * Author: | 143 | @r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd |
99 | + * Bin Meng <bin.meng@windriver.com> | 144 | @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 |
100 | + * | 145 | @@ -XXX,XX +XXX,XX @@ vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm |
101 | + * This program is free software; you can redistribute it and/or | 146 | vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm |
102 | + * modify it under the terms of the GNU General Public License as | 147 | vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm |
103 | + * published by the Free Software Foundation; either version 2 or | 148 | vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm |
104 | + * (at your option) version 3 of the License. | 149 | + |
105 | + * | 150 | +# *** Zvbb vector crypto extension *** |
106 | + * This program is distributed in the hope that it will be useful, | 151 | +vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm |
107 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 152 | +vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm |
108 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 153 | +vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm |
109 | + * GNU General Public License for more details. | 154 | +vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm |
110 | + * | 155 | +vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6 |
111 | + * You should have received a copy of the GNU General Public License along | 156 | +vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm |
112 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | 157 | +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm |
113 | + */ | 158 | +vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm |
114 | + | 159 | +vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm |
115 | +#include "qemu/osdep.h" | 160 | +vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm |
116 | +#include "qemu/bitops.h" | 161 | +vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm |
117 | +#include "qemu/log.h" | 162 | +vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm |
118 | +#include "qapi/error.h" | 163 | +vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm |
119 | +#include "hw/hw.h" | 164 | +vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm |
120 | +#include "hw/sysbus.h" | 165 | +vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm |
121 | +#include "hw/misc/mchp_pfsoc_dmc.h" | 166 | +vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm |
122 | + | 167 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
123 | +/* DDR SGMII PHY module */ | 168 | index XXXXXXX..XXXXXXX 100644 |
124 | + | 169 | --- a/target/riscv/cpu.c |
125 | +#define SGMII_PHY_IOC_REG1 0x208 | 170 | +++ b/target/riscv/cpu.c |
126 | +#define SGMII_PHY_TRAINING_STATUS 0x814 | 171 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { |
127 | +#define SGMII_PHY_DQ_DQS_ERR_DONE 0x834 | 172 | ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), |
128 | +#define SGMII_PHY_DQDQS_STATUS1 0x84c | 173 | ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), |
129 | +#define SGMII_PHY_PVT_STAT 0xc20 | 174 | ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), |
130 | + | 175 | + ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), |
131 | +static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset, | 176 | ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), |
132 | + unsigned size) | 177 | ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), |
178 | ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), | ||
179 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
180 | return; | ||
181 | } | ||
182 | |||
183 | + /* | ||
184 | + * In principle Zve*x would also suffice here, were they supported | ||
185 | + * in qemu | ||
186 | + */ | ||
187 | + if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) { | ||
188 | + error_setg(errp, | ||
189 | + "Vector crypto extensions require V or Zve* extensions"); | ||
190 | + return; | ||
191 | + } | ||
192 | + | ||
193 | if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { | ||
194 | error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions"); | ||
195 | return; | ||
196 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
197 | DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), | ||
198 | |||
199 | /* Vector cryptography extensions */ | ||
200 | + DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), | ||
201 | DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), | ||
202 | |||
203 | DEFINE_PROP_END_OF_LIST(), | ||
204 | diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c | ||
205 | index XXXXXXX..XXXXXXX 100644 | ||
206 | --- a/target/riscv/vcrypto_helper.c | ||
207 | +++ b/target/riscv/vcrypto_helper.c | ||
208 | @@ -XXX,XX +XXX,XX @@ | ||
209 | #include "qemu/osdep.h" | ||
210 | #include "qemu/host-utils.h" | ||
211 | #include "qemu/bitops.h" | ||
212 | +#include "qemu/bswap.h" | ||
213 | #include "cpu.h" | ||
214 | #include "exec/memop.h" | ||
215 | #include "exec/exec-all.h" | ||
216 | @@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64) | ||
217 | GEN_VEXT_VV(vclmulh_vv, 8) | ||
218 | RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) | ||
219 | GEN_VEXT_VX(vclmulh_vx, 8) | ||
220 | + | ||
221 | +RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, ror8) | ||
222 | +RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, ror16) | ||
223 | +RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, ror32) | ||
224 | +RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, ror64) | ||
225 | +GEN_VEXT_VV(vror_vv_b, 1) | ||
226 | +GEN_VEXT_VV(vror_vv_h, 2) | ||
227 | +GEN_VEXT_VV(vror_vv_w, 4) | ||
228 | +GEN_VEXT_VV(vror_vv_d, 8) | ||
229 | + | ||
230 | +RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, ror8) | ||
231 | +RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, ror16) | ||
232 | +RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, ror32) | ||
233 | +RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, ror64) | ||
234 | +GEN_VEXT_VX(vror_vx_b, 1) | ||
235 | +GEN_VEXT_VX(vror_vx_h, 2) | ||
236 | +GEN_VEXT_VX(vror_vx_w, 4) | ||
237 | +GEN_VEXT_VX(vror_vx_d, 8) | ||
238 | + | ||
239 | +RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, rol8) | ||
240 | +RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, rol16) | ||
241 | +RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, rol32) | ||
242 | +RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, rol64) | ||
243 | +GEN_VEXT_VV(vrol_vv_b, 1) | ||
244 | +GEN_VEXT_VV(vrol_vv_h, 2) | ||
245 | +GEN_VEXT_VV(vrol_vv_w, 4) | ||
246 | +GEN_VEXT_VV(vrol_vv_d, 8) | ||
247 | + | ||
248 | +RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, rol8) | ||
249 | +RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, rol16) | ||
250 | +RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, rol32) | ||
251 | +RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, rol64) | ||
252 | +GEN_VEXT_VX(vrol_vx_b, 1) | ||
253 | +GEN_VEXT_VX(vrol_vx_h, 2) | ||
254 | +GEN_VEXT_VX(vrol_vx_w, 4) | ||
255 | +GEN_VEXT_VX(vrol_vx_d, 8) | ||
256 | + | ||
257 | +static uint64_t brev8(uint64_t val) | ||
133 | +{ | 258 | +{ |
134 | + uint32_t val = 0; | 259 | + val = ((val & 0x5555555555555555ull) << 1) | |
135 | + static int training_status_bit; | 260 | + ((val & 0xAAAAAAAAAAAAAAAAull) >> 1); |
136 | + | 261 | + val = ((val & 0x3333333333333333ull) << 2) | |
137 | + switch (offset) { | 262 | + ((val & 0xCCCCCCCCCCCCCCCCull) >> 2); |
138 | + case SGMII_PHY_IOC_REG1: | 263 | + val = ((val & 0x0F0F0F0F0F0F0F0Full) << 4) | |
139 | + /* See ddr_pvt_calibration() in HSS */ | 264 | + ((val & 0xF0F0F0F0F0F0F0F0ull) >> 4); |
140 | + val = BIT(4) | BIT(2); | ||
141 | + break; | ||
142 | + case SGMII_PHY_TRAINING_STATUS: | ||
143 | + /* | ||
144 | + * The codes logic emulates the training status change from | ||
145 | + * DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS. | ||
146 | + * | ||
147 | + * See ddr_setup() in mss_ddr.c in the HSS source codes. | ||
148 | + */ | ||
149 | + val = 1 << training_status_bit; | ||
150 | + training_status_bit = (training_status_bit + 1) % 5; | ||
151 | + break; | ||
152 | + case SGMII_PHY_DQ_DQS_ERR_DONE: | ||
153 | + /* | ||
154 | + * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(), | ||
155 | + * check that DQ/DQS training passed without error. | ||
156 | + */ | ||
157 | + val = 8; | ||
158 | + break; | ||
159 | + case SGMII_PHY_DQDQS_STATUS1: | ||
160 | + /* | ||
161 | + * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(), | ||
162 | + * check that DQ/DQS calculated window is above 5 taps. | ||
163 | + */ | ||
164 | + val = 0xff; | ||
165 | + break; | ||
166 | + case SGMII_PHY_PVT_STAT: | ||
167 | + /* See sgmii_channel_setup() in HSS */ | ||
168 | + val = BIT(14) | BIT(6); | ||
169 | + break; | ||
170 | + default: | ||
171 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
172 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
173 | + __func__, size, offset); | ||
174 | + break; | ||
175 | + } | ||
176 | + | 265 | + |
177 | + return val; | 266 | + return val; |
178 | +} | 267 | +} |
179 | + | 268 | + |
180 | +static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset, | 269 | +RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8) |
181 | + uint64_t value, unsigned size) | 270 | +RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8) |
271 | +RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8) | ||
272 | +RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8) | ||
273 | +GEN_VEXT_V(vbrev8_v_b, 1) | ||
274 | +GEN_VEXT_V(vbrev8_v_h, 2) | ||
275 | +GEN_VEXT_V(vbrev8_v_w, 4) | ||
276 | +GEN_VEXT_V(vbrev8_v_d, 8) | ||
277 | + | ||
278 | +#define DO_IDENTITY(a) (a) | ||
279 | +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY) | ||
280 | +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) | ||
281 | +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) | ||
282 | +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) | ||
283 | +GEN_VEXT_V(vrev8_v_b, 1) | ||
284 | +GEN_VEXT_V(vrev8_v_h, 2) | ||
285 | +GEN_VEXT_V(vrev8_v_w, 4) | ||
286 | +GEN_VEXT_V(vrev8_v_d, 8) | ||
287 | + | ||
288 | +#define DO_ANDN(a, b) ((a) & ~(b)) | ||
289 | +RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN) | ||
290 | +RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN) | ||
291 | +RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN) | ||
292 | +RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN) | ||
293 | +GEN_VEXT_VV(vandn_vv_b, 1) | ||
294 | +GEN_VEXT_VV(vandn_vv_h, 2) | ||
295 | +GEN_VEXT_VV(vandn_vv_w, 4) | ||
296 | +GEN_VEXT_VV(vandn_vv_d, 8) | ||
297 | + | ||
298 | +RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN) | ||
299 | +RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN) | ||
300 | +RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN) | ||
301 | +RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN) | ||
302 | +GEN_VEXT_VX(vandn_vx_b, 1) | ||
303 | +GEN_VEXT_VX(vandn_vx_h, 2) | ||
304 | +GEN_VEXT_VX(vandn_vx_w, 4) | ||
305 | +GEN_VEXT_VX(vandn_vx_d, 8) | ||
306 | + | ||
307 | +RVVCALL(OPIVV1, vbrev_v_b, OP_UU_B, H1, H1, revbit8) | ||
308 | +RVVCALL(OPIVV1, vbrev_v_h, OP_UU_H, H2, H2, revbit16) | ||
309 | +RVVCALL(OPIVV1, vbrev_v_w, OP_UU_W, H4, H4, revbit32) | ||
310 | +RVVCALL(OPIVV1, vbrev_v_d, OP_UU_D, H8, H8, revbit64) | ||
311 | +GEN_VEXT_V(vbrev_v_b, 1) | ||
312 | +GEN_VEXT_V(vbrev_v_h, 2) | ||
313 | +GEN_VEXT_V(vbrev_v_w, 4) | ||
314 | +GEN_VEXT_V(vbrev_v_d, 8) | ||
315 | + | ||
316 | +RVVCALL(OPIVV1, vclz_v_b, OP_UU_B, H1, H1, clz8) | ||
317 | +RVVCALL(OPIVV1, vclz_v_h, OP_UU_H, H2, H2, clz16) | ||
318 | +RVVCALL(OPIVV1, vclz_v_w, OP_UU_W, H4, H4, clz32) | ||
319 | +RVVCALL(OPIVV1, vclz_v_d, OP_UU_D, H8, H8, clz64) | ||
320 | +GEN_VEXT_V(vclz_v_b, 1) | ||
321 | +GEN_VEXT_V(vclz_v_h, 2) | ||
322 | +GEN_VEXT_V(vclz_v_w, 4) | ||
323 | +GEN_VEXT_V(vclz_v_d, 8) | ||
324 | + | ||
325 | +RVVCALL(OPIVV1, vctz_v_b, OP_UU_B, H1, H1, ctz8) | ||
326 | +RVVCALL(OPIVV1, vctz_v_h, OP_UU_H, H2, H2, ctz16) | ||
327 | +RVVCALL(OPIVV1, vctz_v_w, OP_UU_W, H4, H4, ctz32) | ||
328 | +RVVCALL(OPIVV1, vctz_v_d, OP_UU_D, H8, H8, ctz64) | ||
329 | +GEN_VEXT_V(vctz_v_b, 1) | ||
330 | +GEN_VEXT_V(vctz_v_h, 2) | ||
331 | +GEN_VEXT_V(vctz_v_w, 4) | ||
332 | +GEN_VEXT_V(vctz_v_d, 8) | ||
333 | + | ||
334 | +RVVCALL(OPIVV1, vcpop_v_b, OP_UU_B, H1, H1, ctpop8) | ||
335 | +RVVCALL(OPIVV1, vcpop_v_h, OP_UU_H, H2, H2, ctpop16) | ||
336 | +RVVCALL(OPIVV1, vcpop_v_w, OP_UU_W, H4, H4, ctpop32) | ||
337 | +RVVCALL(OPIVV1, vcpop_v_d, OP_UU_D, H8, H8, ctpop64) | ||
338 | +GEN_VEXT_V(vcpop_v_b, 1) | ||
339 | +GEN_VEXT_V(vcpop_v_h, 2) | ||
340 | +GEN_VEXT_V(vcpop_v_w, 4) | ||
341 | +GEN_VEXT_V(vcpop_v_d, 8) | ||
342 | + | ||
343 | +#define DO_SLL(N, M) (N << (M & (sizeof(N) * 8 - 1))) | ||
344 | +RVVCALL(OPIVV2, vwsll_vv_b, WOP_UUU_B, H2, H1, H1, DO_SLL) | ||
345 | +RVVCALL(OPIVV2, vwsll_vv_h, WOP_UUU_H, H4, H2, H2, DO_SLL) | ||
346 | +RVVCALL(OPIVV2, vwsll_vv_w, WOP_UUU_W, H8, H4, H4, DO_SLL) | ||
347 | +GEN_VEXT_VV(vwsll_vv_b, 2) | ||
348 | +GEN_VEXT_VV(vwsll_vv_h, 4) | ||
349 | +GEN_VEXT_VV(vwsll_vv_w, 8) | ||
350 | + | ||
351 | +RVVCALL(OPIVX2, vwsll_vx_b, WOP_UUU_B, H2, H1, DO_SLL) | ||
352 | +RVVCALL(OPIVX2, vwsll_vx_h, WOP_UUU_H, H4, H2, DO_SLL) | ||
353 | +RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL) | ||
354 | +GEN_VEXT_VX(vwsll_vx_b, 2) | ||
355 | +GEN_VEXT_VX(vwsll_vx_h, 4) | ||
356 | +GEN_VEXT_VX(vwsll_vx_w, 8) | ||
357 | diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
358 | index XXXXXXX..XXXXXXX 100644 | ||
359 | --- a/target/riscv/insn_trans/trans_rvvk.c.inc | ||
360 | +++ b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
361 | @@ -XXX,XX +XXX,XX @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) | ||
362 | |||
363 | GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) | ||
364 | GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) | ||
365 | + | ||
366 | +/* | ||
367 | + * Zvbb | ||
368 | + */ | ||
369 | + | ||
370 | +#define GEN_OPIVI_GVEC_TRANS_CHECK(NAME, IMM_MODE, OPIVX, SUF, CHECK) \ | ||
371 | + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
372 | + { \ | ||
373 | + if (CHECK(s, a)) { \ | ||
374 | + static gen_helper_opivx *const fns[4] = { \ | ||
375 | + gen_helper_##OPIVX##_b, \ | ||
376 | + gen_helper_##OPIVX##_h, \ | ||
377 | + gen_helper_##OPIVX##_w, \ | ||
378 | + gen_helper_##OPIVX##_d, \ | ||
379 | + }; \ | ||
380 | + return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \ | ||
381 | + IMM_MODE); \ | ||
382 | + } \ | ||
383 | + return false; \ | ||
384 | + } | ||
385 | + | ||
386 | +#define GEN_OPIVV_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ | ||
387 | + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
388 | + { \ | ||
389 | + if (CHECK(s, a)) { \ | ||
390 | + static gen_helper_gvec_4_ptr *const fns[4] = { \ | ||
391 | + gen_helper_##NAME##_b, \ | ||
392 | + gen_helper_##NAME##_h, \ | ||
393 | + gen_helper_##NAME##_w, \ | ||
394 | + gen_helper_##NAME##_d, \ | ||
395 | + }; \ | ||
396 | + return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ | ||
397 | + } \ | ||
398 | + return false; \ | ||
399 | + } | ||
400 | + | ||
401 | +#define GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(NAME, SUF, CHECK) \ | ||
402 | + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
403 | + { \ | ||
404 | + if (CHECK(s, a)) { \ | ||
405 | + static gen_helper_opivx *const fns[4] = { \ | ||
406 | + gen_helper_##NAME##_b, \ | ||
407 | + gen_helper_##NAME##_h, \ | ||
408 | + gen_helper_##NAME##_w, \ | ||
409 | + gen_helper_##NAME##_d, \ | ||
410 | + }; \ | ||
411 | + return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \ | ||
412 | + fns[s->sew]); \ | ||
413 | + } \ | ||
414 | + return false; \ | ||
415 | + } | ||
416 | + | ||
417 | +static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a) | ||
182 | +{ | 418 | +{ |
183 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | 419 | + return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true; |
184 | + "(size %d, value 0x%" PRIx64 | ||
185 | + ", offset 0x%" HWADDR_PRIx ")\n", | ||
186 | + __func__, size, value, offset); | ||
187 | +} | 420 | +} |
188 | + | 421 | + |
189 | +static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = { | 422 | +static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a) |
190 | + .read = mchp_pfsoc_ddr_sgmii_phy_read, | ||
191 | + .write = mchp_pfsoc_ddr_sgmii_phy_write, | ||
192 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
193 | +}; | ||
194 | + | ||
195 | +static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp) | ||
196 | +{ | 423 | +{ |
197 | + MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev); | 424 | + return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true; |
198 | + | ||
199 | + memory_region_init_io(&s->sgmii_phy, OBJECT(dev), | ||
200 | + &mchp_pfsoc_ddr_sgmii_phy_ops, s, | ||
201 | + "mchp.pfsoc.ddr_sgmii_phy", | ||
202 | + MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE); | ||
203 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy); | ||
204 | +} | 425 | +} |
205 | + | 426 | + |
206 | +static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass, void *data) | 427 | +/* vrol.v[vx] */ |
428 | +GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check) | ||
429 | +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check) | ||
430 | + | ||
431 | +/* vror.v[vxi] */ | ||
432 | +GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check) | ||
433 | +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check) | ||
434 | +GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check) | ||
435 | + | ||
436 | +#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ | ||
437 | + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
438 | + { \ | ||
439 | + if (CHECK(s, a)) { \ | ||
440 | + static gen_helper_opivx *const fns[4] = { \ | ||
441 | + gen_helper_##NAME##_b, \ | ||
442 | + gen_helper_##NAME##_h, \ | ||
443 | + gen_helper_##NAME##_w, \ | ||
444 | + gen_helper_##NAME##_d, \ | ||
445 | + }; \ | ||
446 | + return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ | ||
447 | + } \ | ||
448 | + return false; \ | ||
449 | + } | ||
450 | + | ||
451 | +/* vandn.v[vx] */ | ||
452 | +GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check) | ||
453 | +GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check) | ||
454 | + | ||
455 | +#define GEN_OPIV_TRANS(NAME, CHECK) \ | ||
456 | + static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ | ||
457 | + { \ | ||
458 | + if (CHECK(s, a)) { \ | ||
459 | + uint32_t data = 0; \ | ||
460 | + static gen_helper_gvec_3_ptr *const fns[4] = { \ | ||
461 | + gen_helper_##NAME##_b, \ | ||
462 | + gen_helper_##NAME##_h, \ | ||
463 | + gen_helper_##NAME##_w, \ | ||
464 | + gen_helper_##NAME##_d, \ | ||
465 | + }; \ | ||
466 | + TCGLabel *over = gen_new_label(); \ | ||
467 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
468 | + \ | ||
469 | + data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
470 | + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ | ||
471 | + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ | ||
472 | + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ | ||
473 | + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ | ||
474 | + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ | ||
475 | + vreg_ofs(s, a->rs2), cpu_env, \ | ||
476 | + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \ | ||
477 | + data, fns[s->sew]); \ | ||
478 | + mark_vs_dirty(s); \ | ||
479 | + gen_set_label(over); \ | ||
480 | + return true; \ | ||
481 | + } \ | ||
482 | + return false; \ | ||
483 | + } | ||
484 | + | ||
485 | +static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a) | ||
207 | +{ | 486 | +{ |
208 | + DeviceClass *dc = DEVICE_CLASS(klass); | 487 | + return s->cfg_ptr->ext_zvbb == true && |
209 | + | 488 | + require_rvv(s) && |
210 | + dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module"; | 489 | + vext_check_isa_ill(s) && |
211 | + dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize; | 490 | + vext_check_ss(s, a->rd, a->rs2, a->vm); |
212 | +} | 491 | +} |
213 | + | 492 | + |
214 | +static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = { | 493 | +GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check) |
215 | + .name = TYPE_MCHP_PFSOC_DDR_SGMII_PHY, | 494 | +GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check) |
216 | + .parent = TYPE_SYS_BUS_DEVICE, | 495 | +GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check) |
217 | + .instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState), | 496 | +GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check) |
218 | + .class_init = mchp_pfsoc_ddr_sgmii_phy_class_init, | 497 | +GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check) |
219 | +}; | 498 | +GEN_OPIV_TRANS(vcpop_v, zvbb_opiv_check) |
220 | + | 499 | + |
221 | +static void mchp_pfsoc_ddr_sgmii_phy_register_types(void) | 500 | +static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a) |
222 | +{ | 501 | +{ |
223 | + type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info); | 502 | + return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a); |
224 | +} | 503 | +} |
225 | + | 504 | + |
226 | +type_init(mchp_pfsoc_ddr_sgmii_phy_register_types) | 505 | +static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a) |
227 | + | ||
228 | +/* DDR CFG module */ | ||
229 | + | ||
230 | +#define CFG_MT_DONE_ACK 0x4428 | ||
231 | +#define CFG_STAT_DFI_INIT_COMPLETE 0x10034 | ||
232 | +#define CFG_STAT_DFI_TRAINING_COMPLETE 0x10038 | ||
233 | + | ||
234 | +static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset, | ||
235 | + unsigned size) | ||
236 | +{ | 506 | +{ |
237 | + uint32_t val = 0; | 507 | + return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a); |
238 | + | ||
239 | + switch (offset) { | ||
240 | + case CFG_MT_DONE_ACK: | ||
241 | + /* memory test in MTC_test() */ | ||
242 | + val = BIT(0); | ||
243 | + break; | ||
244 | + case CFG_STAT_DFI_INIT_COMPLETE: | ||
245 | + /* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */ | ||
246 | + val = BIT(0); | ||
247 | + break; | ||
248 | + case CFG_STAT_DFI_TRAINING_COMPLETE: | ||
249 | + /* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */ | ||
250 | + val = BIT(0); | ||
251 | + break; | ||
252 | + default: | ||
253 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
254 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
255 | + __func__, size, offset); | ||
256 | + break; | ||
257 | + } | ||
258 | + | ||
259 | + return val; | ||
260 | +} | 508 | +} |
261 | + | 509 | + |
262 | +static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset, | 510 | +/* OPIVI without GVEC IR */ |
263 | + uint64_t value, unsigned size) | 511 | +#define GEN_OPIVI_WIDEN_TRANS(NAME, IMM_MODE, OPIVX, CHECK) \ |
264 | +{ | 512 | + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ |
265 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | 513 | + { \ |
266 | + "(size %d, value 0x%" PRIx64 | 514 | + if (CHECK(s, a)) { \ |
267 | + ", offset 0x%" HWADDR_PRIx ")\n", | 515 | + static gen_helper_opivx *const fns[3] = { \ |
268 | + __func__, size, value, offset); | 516 | + gen_helper_##OPIVX##_b, \ |
269 | +} | 517 | + gen_helper_##OPIVX##_h, \ |
270 | + | 518 | + gen_helper_##OPIVX##_w, \ |
271 | +static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = { | 519 | + }; \ |
272 | + .read = mchp_pfsoc_ddr_cfg_read, | 520 | + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, \ |
273 | + .write = mchp_pfsoc_ddr_cfg_write, | 521 | + IMM_MODE); \ |
274 | + .endianness = DEVICE_LITTLE_ENDIAN, | 522 | + } \ |
275 | +}; | 523 | + return false; \ |
276 | + | 524 | + } |
277 | +static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp) | 525 | + |
278 | +{ | 526 | +GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check) |
279 | + MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev); | 527 | +GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check) |
280 | + | 528 | +GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check) |
281 | + memory_region_init_io(&s->cfg, OBJECT(dev), | ||
282 | + &mchp_pfsoc_ddr_cfg_ops, s, | ||
283 | + "mchp.pfsoc.ddr_cfg", | ||
284 | + MCHP_PFSOC_DDR_CFG_REG_SIZE); | ||
285 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg); | ||
286 | +} | ||
287 | + | ||
288 | +static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, void *data) | ||
289 | +{ | ||
290 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
291 | + | ||
292 | + dc->desc = "Microchip PolarFire SoC DDR CFG module"; | ||
293 | + dc->realize = mchp_pfsoc_ddr_cfg_realize; | ||
294 | +} | ||
295 | + | ||
296 | +static const TypeInfo mchp_pfsoc_ddr_cfg_info = { | ||
297 | + .name = TYPE_MCHP_PFSOC_DDR_CFG, | ||
298 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
299 | + .instance_size = sizeof(MchpPfSoCDdrCfgState), | ||
300 | + .class_init = mchp_pfsoc_ddr_cfg_class_init, | ||
301 | +}; | ||
302 | + | ||
303 | +static void mchp_pfsoc_ddr_cfg_register_types(void) | ||
304 | +{ | ||
305 | + type_register_static(&mchp_pfsoc_ddr_cfg_info); | ||
306 | +} | ||
307 | + | ||
308 | +type_init(mchp_pfsoc_ddr_cfg_register_types) | ||
309 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
310 | index XXXXXXX..XXXXXXX 100644 | ||
311 | --- a/MAINTAINERS | ||
312 | +++ b/MAINTAINERS | ||
313 | @@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org | ||
314 | S: Supported | ||
315 | F: hw/riscv/microchip_pfsoc.c | ||
316 | F: hw/char/mchp_pfsoc_mmuart.c | ||
317 | +F: hw/misc/mchp_pfsoc_dmc.c | ||
318 | F: include/hw/riscv/microchip_pfsoc.h | ||
319 | F: include/hw/char/mchp_pfsoc_mmuart.h | ||
320 | +F: include/hw/misc/mchp_pfsoc_dmc.h | ||
321 | |||
322 | RX Machines | ||
323 | ----------- | ||
324 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
325 | index XXXXXXX..XXXXXXX 100644 | ||
326 | --- a/hw/misc/Kconfig | ||
327 | +++ b/hw/misc/Kconfig | ||
328 | @@ -XXX,XX +XXX,XX @@ config MAC_VIA | ||
329 | config AVR_POWER | ||
330 | bool | ||
331 | |||
332 | +config MCHP_PFSOC_DMC | ||
333 | + bool | ||
334 | + | ||
335 | config SIFIVE_TEST | ||
336 | bool | ||
337 | |||
338 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
339 | index XXXXXXX..XXXXXXX 100644 | ||
340 | --- a/hw/misc/meson.build | ||
341 | +++ b/hw/misc/meson.build | ||
342 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) | ||
343 | softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) | ||
344 | |||
345 | # RISC-V devices | ||
346 | +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) | ||
347 | softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) | ||
348 | softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) | ||
349 | softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) | ||
350 | -- | 529 | -- |
351 | 2.28.0 | 530 | 2.41.0 |
352 | |||
353 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
1 | 2 | ||
3 | This commit adds support for the Zvkned vector-crypto extension, which | ||
4 | consists of the following instructions: | ||
5 | |||
6 | * vaesef.[vv,vs] | ||
7 | * vaesdf.[vv,vs] | ||
8 | * vaesdm.[vv,vs] | ||
9 | * vaesz.vs | ||
10 | * vaesem.[vv,vs] | ||
11 | * vaeskf1.vi | ||
12 | * vaeskf2.vi | ||
13 | |||
14 | Translation functions are defined in | ||
15 | `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in | ||
16 | `target/riscv/vcrypto_helper.c`. | ||
17 | |||
18 | Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | ||
19 | Co-authored-by: William Salmon <will.salmon@codethink.co.uk> | ||
20 | [max.chou@sifive.com: Replaced vstart checking by TCG op] | ||
21 | Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | ||
22 | Signed-off-by: William Salmon <will.salmon@codethink.co.uk> | ||
23 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
24 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
25 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
26 | [max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned | ||
27 | property] | ||
28 | [max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl | ||
29 | egs checking by helper function] | ||
30 | [max.chou@sifive.com: Replaced bswap32 calls in aes key expanding] | ||
31 | Message-ID: <20230711165917.2629866-10-max.chou@sifive.com> | ||
32 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
33 | --- | ||
34 | target/riscv/cpu_cfg.h | 1 + | ||
35 | target/riscv/helper.h | 14 ++ | ||
36 | target/riscv/insn32.decode | 14 ++ | ||
37 | target/riscv/cpu.c | 4 +- | ||
38 | target/riscv/vcrypto_helper.c | 202 +++++++++++++++++++++++ | ||
39 | target/riscv/insn_trans/trans_rvvk.c.inc | 147 +++++++++++++++++ | ||
40 | 6 files changed, 381 insertions(+), 1 deletion(-) | ||
41 | |||
42 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/riscv/cpu_cfg.h | ||
45 | +++ b/target/riscv/cpu_cfg.h | ||
46 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
47 | bool ext_zve64d; | ||
48 | bool ext_zvbb; | ||
49 | bool ext_zvbc; | ||
50 | + bool ext_zvkned; | ||
51 | bool ext_zmmul; | ||
52 | bool ext_zvfbfmin; | ||
53 | bool ext_zvfbfwma; | ||
54 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/riscv/helper.h | ||
57 | +++ b/target/riscv/helper.h | ||
58 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) | ||
59 | DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) | ||
60 | DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) | ||
61 | DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) | ||
62 | + | ||
63 | +DEF_HELPER_2(egs_check, void, i32, env) | ||
64 | + | ||
65 | +DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) | ||
66 | +DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) | ||
67 | +DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) | ||
68 | +DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) | ||
69 | +DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32) | ||
70 | +DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) | ||
71 | +DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) | ||
72 | +DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) | ||
73 | +DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) | ||
74 | +DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) | ||
75 | +DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) | ||
76 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/riscv/insn32.decode | ||
79 | +++ b/target/riscv/insn32.decode | ||
80 | @@ -XXX,XX +XXX,XX @@ | ||
81 | @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd | ||
82 | @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd | ||
83 | @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd | ||
84 | +@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd | ||
85 | @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd | ||
86 | @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd | ||
87 | @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd | ||
88 | @@ -XXX,XX +XXX,XX @@ vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm | ||
89 | vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm | ||
90 | vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm | ||
91 | vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm | ||
92 | + | ||
93 | +# *** Zvkned vector crypto extension *** | ||
94 | +vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 | ||
95 | +vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 | ||
96 | +vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 | ||
97 | +vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 | ||
98 | +vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 | ||
99 | +vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 | ||
100 | +vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 | ||
101 | +vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 | ||
102 | +vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 | ||
103 | +vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
104 | +vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
105 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/target/riscv/cpu.c | ||
108 | +++ b/target/riscv/cpu.c | ||
109 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
110 | ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), | ||
111 | ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), | ||
112 | ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), | ||
113 | + ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), | ||
114 | ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), | ||
115 | ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), | ||
116 | ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), | ||
117 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
118 | * In principle Zve*x would also suffice here, were they supported | ||
119 | * in qemu | ||
120 | */ | ||
121 | - if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) { | ||
122 | + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) { | ||
123 | error_setg(errp, | ||
124 | "Vector crypto extensions require V or Zve* extensions"); | ||
125 | return; | ||
126 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
127 | /* Vector cryptography extensions */ | ||
128 | DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), | ||
129 | DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), | ||
130 | + DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), | ||
131 | |||
132 | DEFINE_PROP_END_OF_LIST(), | ||
133 | }; | ||
134 | diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c | ||
135 | index XXXXXXX..XXXXXXX 100644 | ||
136 | --- a/target/riscv/vcrypto_helper.c | ||
137 | +++ b/target/riscv/vcrypto_helper.c | ||
138 | @@ -XXX,XX +XXX,XX @@ | ||
139 | #include "qemu/bitops.h" | ||
140 | #include "qemu/bswap.h" | ||
141 | #include "cpu.h" | ||
142 | +#include "crypto/aes.h" | ||
143 | +#include "crypto/aes-round.h" | ||
144 | #include "exec/memop.h" | ||
145 | #include "exec/exec-all.h" | ||
146 | #include "exec/helper-proto.h" | ||
147 | @@ -XXX,XX +XXX,XX @@ RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL) | ||
148 | GEN_VEXT_VX(vwsll_vx_b, 2) | ||
149 | GEN_VEXT_VX(vwsll_vx_h, 4) | ||
150 | GEN_VEXT_VX(vwsll_vx_w, 8) | ||
151 | + | ||
152 | +void HELPER(egs_check)(uint32_t egs, CPURISCVState *env) | ||
153 | +{ | ||
154 | + uint32_t vl = env->vl; | ||
155 | + uint32_t vstart = env->vstart; | ||
156 | + | ||
157 | + if (vl % egs != 0 || vstart % egs != 0) { | ||
158 | + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
159 | + } | ||
160 | +} | ||
161 | + | ||
162 | +static inline void xor_round_key(AESState *round_state, AESState *round_key) | ||
163 | +{ | ||
164 | + round_state->v = round_state->v ^ round_key->v; | ||
165 | +} | ||
166 | + | ||
167 | +#define GEN_ZVKNED_HELPER_VV(NAME, ...) \ | ||
168 | + void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ | ||
169 | + uint32_t desc) \ | ||
170 | + { \ | ||
171 | + uint32_t vl = env->vl; \ | ||
172 | + uint32_t total_elems = vext_get_total_elems(env, desc, 4); \ | ||
173 | + uint32_t vta = vext_vta(desc); \ | ||
174 | + \ | ||
175 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \ | ||
176 | + AESState round_key; \ | ||
177 | + round_key.d[0] = *((uint64_t *)vs2 + H8(i * 2 + 0)); \ | ||
178 | + round_key.d[1] = *((uint64_t *)vs2 + H8(i * 2 + 1)); \ | ||
179 | + AESState round_state; \ | ||
180 | + round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0)); \ | ||
181 | + round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1)); \ | ||
182 | + __VA_ARGS__; \ | ||
183 | + *((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0]; \ | ||
184 | + *((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1]; \ | ||
185 | + } \ | ||
186 | + env->vstart = 0; \ | ||
187 | + /* set tail elements to 1s */ \ | ||
188 | + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ | ||
189 | + } | ||
190 | + | ||
191 | +#define GEN_ZVKNED_HELPER_VS(NAME, ...) \ | ||
192 | + void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ | ||
193 | + uint32_t desc) \ | ||
194 | + { \ | ||
195 | + uint32_t vl = env->vl; \ | ||
196 | + uint32_t total_elems = vext_get_total_elems(env, desc, 4); \ | ||
197 | + uint32_t vta = vext_vta(desc); \ | ||
198 | + \ | ||
199 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \ | ||
200 | + AESState round_key; \ | ||
201 | + round_key.d[0] = *((uint64_t *)vs2 + H8(0)); \ | ||
202 | + round_key.d[1] = *((uint64_t *)vs2 + H8(1)); \ | ||
203 | + AESState round_state; \ | ||
204 | + round_state.d[0] = *((uint64_t *)vd + H8(i * 2 + 0)); \ | ||
205 | + round_state.d[1] = *((uint64_t *)vd + H8(i * 2 + 1)); \ | ||
206 | + __VA_ARGS__; \ | ||
207 | + *((uint64_t *)vd + H8(i * 2 + 0)) = round_state.d[0]; \ | ||
208 | + *((uint64_t *)vd + H8(i * 2 + 1)) = round_state.d[1]; \ | ||
209 | + } \ | ||
210 | + env->vstart = 0; \ | ||
211 | + /* set tail elements to 1s */ \ | ||
212 | + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ | ||
213 | + } | ||
214 | + | ||
215 | +GEN_ZVKNED_HELPER_VV(vaesef_vv, aesenc_SB_SR_AK(&round_state, | ||
216 | + &round_state, | ||
217 | + &round_key, | ||
218 | + false);) | ||
219 | +GEN_ZVKNED_HELPER_VS(vaesef_vs, aesenc_SB_SR_AK(&round_state, | ||
220 | + &round_state, | ||
221 | + &round_key, | ||
222 | + false);) | ||
223 | +GEN_ZVKNED_HELPER_VV(vaesdf_vv, aesdec_ISB_ISR_AK(&round_state, | ||
224 | + &round_state, | ||
225 | + &round_key, | ||
226 | + false);) | ||
227 | +GEN_ZVKNED_HELPER_VS(vaesdf_vs, aesdec_ISB_ISR_AK(&round_state, | ||
228 | + &round_state, | ||
229 | + &round_key, | ||
230 | + false);) | ||
231 | +GEN_ZVKNED_HELPER_VV(vaesem_vv, aesenc_SB_SR_MC_AK(&round_state, | ||
232 | + &round_state, | ||
233 | + &round_key, | ||
234 | + false);) | ||
235 | +GEN_ZVKNED_HELPER_VS(vaesem_vs, aesenc_SB_SR_MC_AK(&round_state, | ||
236 | + &round_state, | ||
237 | + &round_key, | ||
238 | + false);) | ||
239 | +GEN_ZVKNED_HELPER_VV(vaesdm_vv, aesdec_ISB_ISR_AK_IMC(&round_state, | ||
240 | + &round_state, | ||
241 | + &round_key, | ||
242 | + false);) | ||
243 | +GEN_ZVKNED_HELPER_VS(vaesdm_vs, aesdec_ISB_ISR_AK_IMC(&round_state, | ||
244 | + &round_state, | ||
245 | + &round_key, | ||
246 | + false);) | ||
247 | +GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(&round_state, &round_key);) | ||
248 | + | ||
249 | +void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, | ||
250 | + CPURISCVState *env, uint32_t desc) | ||
251 | +{ | ||
252 | + uint32_t *vd = vd_vptr; | ||
253 | + uint32_t *vs2 = vs2_vptr; | ||
254 | + uint32_t vl = env->vl; | ||
255 | + uint32_t total_elems = vext_get_total_elems(env, desc, 4); | ||
256 | + uint32_t vta = vext_vta(desc); | ||
257 | + | ||
258 | + uimm &= 0b1111; | ||
259 | + if (uimm > 10 || uimm == 0) { | ||
260 | + uimm ^= 0b1000; | ||
261 | + } | ||
262 | + | ||
263 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
264 | + uint32_t rk[8], tmp; | ||
265 | + static const uint32_t rcon[] = { | ||
266 | + 0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010, | ||
267 | + 0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036, | ||
268 | + }; | ||
269 | + | ||
270 | + rk[0] = vs2[i * 4 + H4(0)]; | ||
271 | + rk[1] = vs2[i * 4 + H4(1)]; | ||
272 | + rk[2] = vs2[i * 4 + H4(2)]; | ||
273 | + rk[3] = vs2[i * 4 + H4(3)]; | ||
274 | + tmp = ror32(rk[3], 8); | ||
275 | + | ||
276 | + rk[4] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) | | ||
277 | + ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) | | ||
278 | + ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) | | ||
279 | + ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0)) | ||
280 | + ^ rcon[uimm - 1]; | ||
281 | + rk[5] = rk[1] ^ rk[4]; | ||
282 | + rk[6] = rk[2] ^ rk[5]; | ||
283 | + rk[7] = rk[3] ^ rk[6]; | ||
284 | + | ||
285 | + vd[i * 4 + H4(0)] = rk[4]; | ||
286 | + vd[i * 4 + H4(1)] = rk[5]; | ||
287 | + vd[i * 4 + H4(2)] = rk[6]; | ||
288 | + vd[i * 4 + H4(3)] = rk[7]; | ||
289 | + } | ||
290 | + env->vstart = 0; | ||
291 | + /* set tail elements to 1s */ | ||
292 | + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); | ||
293 | +} | ||
294 | + | ||
295 | +void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, | ||
296 | + CPURISCVState *env, uint32_t desc) | ||
297 | +{ | ||
298 | + uint32_t *vd = vd_vptr; | ||
299 | + uint32_t *vs2 = vs2_vptr; | ||
300 | + uint32_t vl = env->vl; | ||
301 | + uint32_t total_elems = vext_get_total_elems(env, desc, 4); | ||
302 | + uint32_t vta = vext_vta(desc); | ||
303 | + | ||
304 | + uimm &= 0b1111; | ||
305 | + if (uimm > 14 || uimm < 2) { | ||
306 | + uimm ^= 0b1000; | ||
307 | + } | ||
308 | + | ||
309 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
310 | + uint32_t rk[12], tmp; | ||
311 | + static const uint32_t rcon[] = { | ||
312 | + 0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010, | ||
313 | + 0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036, | ||
314 | + }; | ||
315 | + | ||
316 | + rk[0] = vd[i * 4 + H4(0)]; | ||
317 | + rk[1] = vd[i * 4 + H4(1)]; | ||
318 | + rk[2] = vd[i * 4 + H4(2)]; | ||
319 | + rk[3] = vd[i * 4 + H4(3)]; | ||
320 | + rk[4] = vs2[i * 4 + H4(0)]; | ||
321 | + rk[5] = vs2[i * 4 + H4(1)]; | ||
322 | + rk[6] = vs2[i * 4 + H4(2)]; | ||
323 | + rk[7] = vs2[i * 4 + H4(3)]; | ||
324 | + | ||
325 | + if (uimm % 2 == 0) { | ||
326 | + tmp = ror32(rk[7], 8); | ||
327 | + rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) | | ||
328 | + ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) | | ||
329 | + ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) | | ||
330 | + ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0)) | ||
331 | + ^ rcon[(uimm - 1) / 2]; | ||
332 | + } else { | ||
333 | + rk[8] = rk[0] ^ (((uint32_t)AES_sbox[(rk[7] >> 24) & 0xff] << 24) | | ||
334 | + ((uint32_t)AES_sbox[(rk[7] >> 16) & 0xff] << 16) | | ||
335 | + ((uint32_t)AES_sbox[(rk[7] >> 8) & 0xff] << 8) | | ||
336 | + ((uint32_t)AES_sbox[(rk[7] >> 0) & 0xff] << 0)); | ||
337 | + } | ||
338 | + rk[9] = rk[1] ^ rk[8]; | ||
339 | + rk[10] = rk[2] ^ rk[9]; | ||
340 | + rk[11] = rk[3] ^ rk[10]; | ||
341 | + | ||
342 | + vd[i * 4 + H4(0)] = rk[8]; | ||
343 | + vd[i * 4 + H4(1)] = rk[9]; | ||
344 | + vd[i * 4 + H4(2)] = rk[10]; | ||
345 | + vd[i * 4 + H4(3)] = rk[11]; | ||
346 | + } | ||
347 | + env->vstart = 0; | ||
348 | + /* set tail elements to 1s */ | ||
349 | + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); | ||
350 | +} | ||
351 | diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
352 | index XXXXXXX..XXXXXXX 100644 | ||
353 | --- a/target/riscv/insn_trans/trans_rvvk.c.inc | ||
354 | +++ b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
355 | @@ -XXX,XX +XXX,XX @@ static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a) | ||
356 | GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check) | ||
357 | GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check) | ||
358 | GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check) | ||
359 | + | ||
360 | +/* | ||
361 | + * Zvkned | ||
362 | + */ | ||
363 | + | ||
364 | +#define ZVKNED_EGS 4 | ||
365 | + | ||
366 | +#define GEN_V_UNMASKED_TRANS(NAME, CHECK, EGS) \ | ||
367 | + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ | ||
368 | + { \ | ||
369 | + if (CHECK(s, a)) { \ | ||
370 | + TCGv_ptr rd_v, rs2_v; \ | ||
371 | + TCGv_i32 desc, egs; \ | ||
372 | + uint32_t data = 0; \ | ||
373 | + TCGLabel *over = gen_new_label(); \ | ||
374 | + \ | ||
375 | + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \ | ||
376 | + /* save opcode for unwinding in case we throw an exception */ \ | ||
377 | + decode_save_opc(s); \ | ||
378 | + egs = tcg_constant_i32(EGS); \ | ||
379 | + gen_helper_egs_check(egs, cpu_env); \ | ||
380 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
381 | + } \ | ||
382 | + \ | ||
383 | + data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
384 | + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ | ||
385 | + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ | ||
386 | + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ | ||
387 | + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ | ||
388 | + rd_v = tcg_temp_new_ptr(); \ | ||
389 | + rs2_v = tcg_temp_new_ptr(); \ | ||
390 | + desc = tcg_constant_i32( \ | ||
391 | + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \ | ||
392 | + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ | ||
393 | + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ | ||
394 | + gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); \ | ||
395 | + mark_vs_dirty(s); \ | ||
396 | + gen_set_label(over); \ | ||
397 | + return true; \ | ||
398 | + } \ | ||
399 | + return false; \ | ||
400 | + } | ||
401 | + | ||
402 | +static bool vaes_check_vv(DisasContext *s, arg_rmr *a) | ||
403 | +{ | ||
404 | + int egw_bytes = ZVKNED_EGS << s->sew; | ||
405 | + return s->cfg_ptr->ext_zvkned == true && | ||
406 | + require_rvv(s) && | ||
407 | + vext_check_isa_ill(s) && | ||
408 | + MAXSZ(s) >= egw_bytes && | ||
409 | + require_align(a->rd, s->lmul) && | ||
410 | + require_align(a->rs2, s->lmul) && | ||
411 | + s->sew == MO_32; | ||
412 | +} | ||
413 | + | ||
414 | +static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) | ||
415 | +{ | ||
416 | + int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul; | ||
417 | + return !is_overlapped(vd, op_size, vs2, 1); | ||
418 | +} | ||
419 | + | ||
420 | +static bool vaes_check_vs(DisasContext *s, arg_rmr *a) | ||
421 | +{ | ||
422 | + int egw_bytes = ZVKNED_EGS << s->sew; | ||
423 | + return vaes_check_overlap(s, a->rd, a->rs2) && | ||
424 | + MAXSZ(s) >= egw_bytes && | ||
425 | + s->cfg_ptr->ext_zvkned == true && | ||
426 | + require_rvv(s) && | ||
427 | + vext_check_isa_ill(s) && | ||
428 | + require_align(a->rd, s->lmul) && | ||
429 | + s->sew == MO_32; | ||
430 | +} | ||
431 | + | ||
432 | +GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv, ZVKNED_EGS) | ||
433 | +GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs, ZVKNED_EGS) | ||
434 | +GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv, ZVKNED_EGS) | ||
435 | +GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs, ZVKNED_EGS) | ||
436 | +GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv, ZVKNED_EGS) | ||
437 | +GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs, ZVKNED_EGS) | ||
438 | +GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs, ZVKNED_EGS) | ||
439 | +GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv, ZVKNED_EGS) | ||
440 | +GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS) | ||
441 | + | ||
442 | +#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, EGS) \ | ||
443 | + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ | ||
444 | + { \ | ||
445 | + if (CHECK(s, a)) { \ | ||
446 | + TCGv_ptr rd_v, rs2_v; \ | ||
447 | + TCGv_i32 uimm_v, desc, egs; \ | ||
448 | + uint32_t data = 0; \ | ||
449 | + TCGLabel *over = gen_new_label(); \ | ||
450 | + \ | ||
451 | + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \ | ||
452 | + /* save opcode for unwinding in case we throw an exception */ \ | ||
453 | + decode_save_opc(s); \ | ||
454 | + egs = tcg_constant_i32(EGS); \ | ||
455 | + gen_helper_egs_check(egs, cpu_env); \ | ||
456 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
457 | + } \ | ||
458 | + \ | ||
459 | + data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
460 | + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ | ||
461 | + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ | ||
462 | + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ | ||
463 | + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ | ||
464 | + \ | ||
465 | + rd_v = tcg_temp_new_ptr(); \ | ||
466 | + rs2_v = tcg_temp_new_ptr(); \ | ||
467 | + uimm_v = tcg_constant_i32(a->rs1); \ | ||
468 | + desc = tcg_constant_i32( \ | ||
469 | + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); \ | ||
470 | + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ | ||
471 | + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ | ||
472 | + gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \ | ||
473 | + mark_vs_dirty(s); \ | ||
474 | + gen_set_label(over); \ | ||
475 | + return true; \ | ||
476 | + } \ | ||
477 | + return false; \ | ||
478 | + } | ||
479 | + | ||
480 | +static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a) | ||
481 | +{ | ||
482 | + int egw_bytes = ZVKNED_EGS << s->sew; | ||
483 | + return s->cfg_ptr->ext_zvkned == true && | ||
484 | + require_rvv(s) && | ||
485 | + vext_check_isa_ill(s) && | ||
486 | + MAXSZ(s) >= egw_bytes && | ||
487 | + s->sew == MO_32 && | ||
488 | + require_align(a->rd, s->lmul) && | ||
489 | + require_align(a->rs2, s->lmul); | ||
490 | +} | ||
491 | + | ||
492 | +static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a) | ||
493 | +{ | ||
494 | + int egw_bytes = ZVKNED_EGS << s->sew; | ||
495 | + return s->cfg_ptr->ext_zvkned == true && | ||
496 | + require_rvv(s) && | ||
497 | + vext_check_isa_ill(s) && | ||
498 | + MAXSZ(s) >= egw_bytes && | ||
499 | + s->sew == MO_32 && | ||
500 | + require_align(a->rd, s->lmul) && | ||
501 | + require_align(a->rs2, s->lmul); | ||
502 | +} | ||
503 | + | ||
504 | +GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS) | ||
505 | +GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS) | ||
506 | -- | ||
507 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
1 | 2 | ||
3 | This commit adds support for the Zvknh vector-crypto extension, which | ||
4 | consists of the following instructions: | ||
5 | |||
6 | * vsha2ms.vv | ||
7 | * vsha2c[hl].vv | ||
8 | |||
9 | Translation functions are defined in | ||
10 | `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in | ||
11 | `target/riscv/vcrypto_helper.c`. | ||
12 | |||
13 | Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
14 | Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | ||
15 | [max.chou@sifive.com: Replaced vstart checking by TCG op] | ||
16 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
17 | Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | ||
18 | Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
19 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
20 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
21 | [max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties] | ||
22 | [max.chou@sifive.com: Replaced SEW selection to happened during | ||
23 | translation] | ||
24 | Message-ID: <20230711165917.2629866-11-max.chou@sifive.com> | ||
25 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
26 | --- | ||
27 | target/riscv/cpu_cfg.h | 2 + | ||
28 | target/riscv/helper.h | 6 + | ||
29 | target/riscv/insn32.decode | 5 + | ||
30 | target/riscv/cpu.c | 13 +- | ||
31 | target/riscv/vcrypto_helper.c | 238 +++++++++++++++++++++++ | ||
32 | target/riscv/insn_trans/trans_rvvk.c.inc | 129 ++++++++++++ | ||
33 | 6 files changed, 390 insertions(+), 3 deletions(-) | ||
34 | |||
35 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/riscv/cpu_cfg.h | ||
38 | +++ b/target/riscv/cpu_cfg.h | ||
39 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
40 | bool ext_zvbb; | ||
41 | bool ext_zvbc; | ||
42 | bool ext_zvkned; | ||
43 | + bool ext_zvknha; | ||
44 | + bool ext_zvknhb; | ||
45 | bool ext_zmmul; | ||
46 | bool ext_zvfbfmin; | ||
47 | bool ext_zvfbfwma; | ||
48 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/riscv/helper.h | ||
51 | +++ b/target/riscv/helper.h | ||
52 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) | ||
53 | DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) | ||
54 | DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) | ||
55 | DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) | ||
56 | + | ||
57 | +DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) | ||
58 | +DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32) | ||
59 | +DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32) | ||
60 | +DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32) | ||
61 | +DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32) | ||
62 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/target/riscv/insn32.decode | ||
65 | +++ b/target/riscv/insn32.decode | ||
66 | @@ -XXX,XX +XXX,XX @@ vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 | ||
67 | vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 | ||
68 | vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
69 | vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
70 | + | ||
71 | +# *** Zvknh vector crypto extension *** | ||
72 | +vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
73 | +vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
74 | +vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
75 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/riscv/cpu.c | ||
78 | +++ b/target/riscv/cpu.c | ||
79 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
80 | ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), | ||
81 | ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), | ||
82 | ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), | ||
83 | + ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), | ||
84 | + ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), | ||
85 | ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), | ||
86 | ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), | ||
87 | ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), | ||
88 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
89 | * In principle Zve*x would also suffice here, were they supported | ||
90 | * in qemu | ||
91 | */ | ||
92 | - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f) { | ||
93 | + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) && | ||
94 | + !cpu->cfg.ext_zve32f) { | ||
95 | error_setg(errp, | ||
96 | "Vector crypto extensions require V or Zve* extensions"); | ||
97 | return; | ||
98 | } | ||
99 | |||
100 | - if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { | ||
101 | - error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions"); | ||
102 | + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { | ||
103 | + error_setg( | ||
104 | + errp, | ||
105 | + "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); | ||
106 | return; | ||
107 | } | ||
108 | |||
109 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
110 | DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), | ||
111 | DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), | ||
112 | DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), | ||
113 | + DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), | ||
114 | + DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), | ||
115 | |||
116 | DEFINE_PROP_END_OF_LIST(), | ||
117 | }; | ||
118 | diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c | ||
119 | index XXXXXXX..XXXXXXX 100644 | ||
120 | --- a/target/riscv/vcrypto_helper.c | ||
121 | +++ b/target/riscv/vcrypto_helper.c | ||
122 | @@ -XXX,XX +XXX,XX @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, | ||
123 | /* set tail elements to 1s */ | ||
124 | vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); | ||
125 | } | ||
126 | + | ||
127 | +static inline uint32_t sig0_sha256(uint32_t x) | ||
128 | +{ | ||
129 | + return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3); | ||
130 | +} | ||
131 | + | ||
132 | +static inline uint32_t sig1_sha256(uint32_t x) | ||
133 | +{ | ||
134 | + return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); | ||
135 | +} | ||
136 | + | ||
137 | +static inline uint64_t sig0_sha512(uint64_t x) | ||
138 | +{ | ||
139 | + return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); | ||
140 | +} | ||
141 | + | ||
142 | +static inline uint64_t sig1_sha512(uint64_t x) | ||
143 | +{ | ||
144 | + return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); | ||
145 | +} | ||
146 | + | ||
147 | +static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) | ||
148 | +{ | ||
149 | + uint32_t res[4]; | ||
150 | + res[0] = sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)]) + | ||
151 | + vd[H4(0)]; | ||
152 | + res[1] = sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)]) + | ||
153 | + vd[H4(1)]; | ||
154 | + res[2] = | ||
155 | + sig1_sha256(res[0]) + vs2[H4(3)] + sig0_sha256(vd[H4(3)]) + vd[H4(2)]; | ||
156 | + res[3] = | ||
157 | + sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4(3)]; | ||
158 | + vd[H4(3)] = res[3]; | ||
159 | + vd[H4(2)] = res[2]; | ||
160 | + vd[H4(1)] = res[1]; | ||
161 | + vd[H4(0)] = res[0]; | ||
162 | +} | ||
163 | + | ||
164 | +static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2) | ||
165 | +{ | ||
166 | + uint64_t res[4]; | ||
167 | + res[0] = sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0]; | ||
168 | + res[1] = sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1]; | ||
169 | + res[2] = sig1_sha512(res[0]) + vs2[3] + sig0_sha512(vd[3]) + vd[2]; | ||
170 | + res[3] = sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3]; | ||
171 | + vd[3] = res[3]; | ||
172 | + vd[2] = res[2]; | ||
173 | + vd[1] = res[1]; | ||
174 | + vd[0] = res[0]; | ||
175 | +} | ||
176 | + | ||
177 | +void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, | ||
178 | + uint32_t desc) | ||
179 | +{ | ||
180 | + uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); | ||
181 | + uint32_t esz = sew == MO_32 ? 4 : 8; | ||
182 | + uint32_t total_elems; | ||
183 | + uint32_t vta = vext_vta(desc); | ||
184 | + | ||
185 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
186 | + if (sew == MO_32) { | ||
187 | + vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * 4, | ||
188 | + ((uint32_t *)vs2) + i * 4); | ||
189 | + } else { | ||
190 | + /* If not 32 then SEW should be 64 */ | ||
191 | + vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * 4, | ||
192 | + ((uint64_t *)vs2) + i * 4); | ||
193 | + } | ||
194 | + } | ||
195 | + /* set tail elements to 1s */ | ||
196 | + total_elems = vext_get_total_elems(env, desc, esz); | ||
197 | + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); | ||
198 | + env->vstart = 0; | ||
199 | +} | ||
200 | + | ||
201 | +static inline uint64_t sum0_64(uint64_t x) | ||
202 | +{ | ||
203 | + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); | ||
204 | +} | ||
205 | + | ||
206 | +static inline uint32_t sum0_32(uint32_t x) | ||
207 | +{ | ||
208 | + return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22); | ||
209 | +} | ||
210 | + | ||
211 | +static inline uint64_t sum1_64(uint64_t x) | ||
212 | +{ | ||
213 | + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); | ||
214 | +} | ||
215 | + | ||
216 | +static inline uint32_t sum1_32(uint32_t x) | ||
217 | +{ | ||
218 | + return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25); | ||
219 | +} | ||
220 | + | ||
221 | +#define ch(x, y, z) ((x & y) ^ ((~x) & z)) | ||
222 | + | ||
223 | +#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) | ||
224 | + | ||
225 | +static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1) | ||
226 | +{ | ||
227 | + uint64_t a = vs2[3], b = vs2[2], e = vs2[1], f = vs2[0]; | ||
228 | + uint64_t c = vd[3], d = vd[2], g = vd[1], h = vd[0]; | ||
229 | + uint64_t W0 = vs1[0], W1 = vs1[1]; | ||
230 | + uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0; | ||
231 | + uint64_t T2 = sum0_64(a) + maj(a, b, c); | ||
232 | + | ||
233 | + h = g; | ||
234 | + g = f; | ||
235 | + f = e; | ||
236 | + e = d + T1; | ||
237 | + d = c; | ||
238 | + c = b; | ||
239 | + b = a; | ||
240 | + a = T1 + T2; | ||
241 | + | ||
242 | + T1 = h + sum1_64(e) + ch(e, f, g) + W1; | ||
243 | + T2 = sum0_64(a) + maj(a, b, c); | ||
244 | + h = g; | ||
245 | + g = f; | ||
246 | + f = e; | ||
247 | + e = d + T1; | ||
248 | + d = c; | ||
249 | + c = b; | ||
250 | + b = a; | ||
251 | + a = T1 + T2; | ||
252 | + | ||
253 | + vd[0] = f; | ||
254 | + vd[1] = e; | ||
255 | + vd[2] = b; | ||
256 | + vd[3] = a; | ||
257 | +} | ||
258 | + | ||
259 | +static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1) | ||
260 | +{ | ||
261 | + uint32_t a = vs2[H4(3)], b = vs2[H4(2)], e = vs2[H4(1)], f = vs2[H4(0)]; | ||
262 | + uint32_t c = vd[H4(3)], d = vd[H4(2)], g = vd[H4(1)], h = vd[H4(0)]; | ||
263 | + uint32_t W0 = vs1[H4(0)], W1 = vs1[H4(1)]; | ||
264 | + uint32_t T1 = h + sum1_32(e) + ch(e, f, g) + W0; | ||
265 | + uint32_t T2 = sum0_32(a) + maj(a, b, c); | ||
266 | + | ||
267 | + h = g; | ||
268 | + g = f; | ||
269 | + f = e; | ||
270 | + e = d + T1; | ||
271 | + d = c; | ||
272 | + c = b; | ||
273 | + b = a; | ||
274 | + a = T1 + T2; | ||
275 | + | ||
276 | + T1 = h + sum1_32(e) + ch(e, f, g) + W1; | ||
277 | + T2 = sum0_32(a) + maj(a, b, c); | ||
278 | + h = g; | ||
279 | + g = f; | ||
280 | + f = e; | ||
281 | + e = d + T1; | ||
282 | + d = c; | ||
283 | + c = b; | ||
284 | + b = a; | ||
285 | + a = T1 + T2; | ||
286 | + | ||
287 | + vd[H4(0)] = f; | ||
288 | + vd[H4(1)] = e; | ||
289 | + vd[H4(2)] = b; | ||
290 | + vd[H4(3)] = a; | ||
291 | +} | ||
292 | + | ||
293 | +void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, | ||
294 | + uint32_t desc) | ||
295 | +{ | ||
296 | + const uint32_t esz = 4; | ||
297 | + uint32_t total_elems; | ||
298 | + uint32_t vta = vext_vta(desc); | ||
299 | + | ||
300 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
301 | + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, | ||
302 | + ((uint32_t *)vs1) + 4 * i + 2); | ||
303 | + } | ||
304 | + | ||
305 | + /* set tail elements to 1s */ | ||
306 | + total_elems = vext_get_total_elems(env, desc, esz); | ||
307 | + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); | ||
308 | + env->vstart = 0; | ||
309 | +} | ||
310 | + | ||
311 | +void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, | ||
312 | + uint32_t desc) | ||
313 | +{ | ||
314 | + const uint32_t esz = 8; | ||
315 | + uint32_t total_elems; | ||
316 | + uint32_t vta = vext_vta(desc); | ||
317 | + | ||
318 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
319 | + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, | ||
320 | + ((uint64_t *)vs1) + 4 * i + 2); | ||
321 | + } | ||
322 | + | ||
323 | + /* set tail elements to 1s */ | ||
324 | + total_elems = vext_get_total_elems(env, desc, esz); | ||
325 | + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); | ||
326 | + env->vstart = 0; | ||
327 | +} | ||
328 | + | ||
329 | +void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, | ||
330 | + uint32_t desc) | ||
331 | +{ | ||
332 | + const uint32_t esz = 4; | ||
333 | + uint32_t total_elems; | ||
334 | + uint32_t vta = vext_vta(desc); | ||
335 | + | ||
336 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
337 | + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, | ||
338 | + (((uint32_t *)vs1) + 4 * i)); | ||
339 | + } | ||
340 | + | ||
341 | + /* set tail elements to 1s */ | ||
342 | + total_elems = vext_get_total_elems(env, desc, esz); | ||
343 | + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); | ||
344 | + env->vstart = 0; | ||
345 | +} | ||
346 | + | ||
347 | +void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, | ||
348 | + uint32_t desc) | ||
349 | +{ | ||
350 | + uint32_t esz = 8; | ||
351 | + uint32_t total_elems; | ||
352 | + uint32_t vta = vext_vta(desc); | ||
353 | + | ||
354 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
355 | + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, | ||
356 | + (((uint64_t *)vs1) + 4 * i)); | ||
357 | + } | ||
358 | + | ||
359 | + /* set tail elements to 1s */ | ||
360 | + total_elems = vext_get_total_elems(env, desc, esz); | ||
361 | + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); | ||
362 | + env->vstart = 0; | ||
363 | +} | ||
364 | diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
365 | index XXXXXXX..XXXXXXX 100644 | ||
366 | --- a/target/riscv/insn_trans/trans_rvvk.c.inc | ||
367 | +++ b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
368 | @@ -XXX,XX +XXX,XX @@ static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a) | ||
369 | |||
370 | GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS) | ||
371 | GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS) | ||
372 | + | ||
373 | +/* | ||
374 | + * Zvknh | ||
375 | + */ | ||
376 | + | ||
377 | +#define ZVKNH_EGS 4 | ||
378 | + | ||
379 | +#define GEN_VV_UNMASKED_TRANS(NAME, CHECK, EGS) \ | ||
380 | + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ | ||
381 | + { \ | ||
382 | + if (CHECK(s, a)) { \ | ||
383 | + uint32_t data = 0; \ | ||
384 | + TCGLabel *over = gen_new_label(); \ | ||
385 | + TCGv_i32 egs; \ | ||
386 | + \ | ||
387 | + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \ | ||
388 | + /* save opcode for unwinding in case we throw an exception */ \ | ||
389 | + decode_save_opc(s); \ | ||
390 | + egs = tcg_constant_i32(EGS); \ | ||
391 | + gen_helper_egs_check(egs, cpu_env); \ | ||
392 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ | ||
393 | + } \ | ||
394 | + \ | ||
395 | + data = FIELD_DP32(data, VDATA, VM, a->vm); \ | ||
396 | + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ | ||
397 | + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ | ||
398 | + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ | ||
399 | + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ | ||
400 | + \ | ||
401 | + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), \ | ||
402 | + vreg_ofs(s, a->rs2), cpu_env, \ | ||
403 | + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \ | ||
404 | + data, gen_helper_##NAME); \ | ||
405 | + \ | ||
406 | + mark_vs_dirty(s); \ | ||
407 | + gen_set_label(over); \ | ||
408 | + return true; \ | ||
409 | + } \ | ||
410 | + return false; \ | ||
411 | + } | ||
412 | + | ||
413 | +static bool vsha_check_sew(DisasContext *s) | ||
414 | +{ | ||
415 | + return (s->cfg_ptr->ext_zvknha == true && s->sew == MO_32) || | ||
416 | + (s->cfg_ptr->ext_zvknhb == true && | ||
417 | + (s->sew == MO_32 || s->sew == MO_64)); | ||
418 | +} | ||
419 | + | ||
420 | +static bool vsha_check(DisasContext *s, arg_rmrr *a) | ||
421 | +{ | ||
422 | + int egw_bytes = ZVKNH_EGS << s->sew; | ||
423 | + int mult = 1 << MAX(s->lmul, 0); | ||
424 | + return opivv_check(s, a) && | ||
425 | + vsha_check_sew(s) && | ||
426 | + MAXSZ(s) >= egw_bytes && | ||
427 | + !is_overlapped(a->rd, mult, a->rs1, mult) && | ||
428 | + !is_overlapped(a->rd, mult, a->rs2, mult) && | ||
429 | + s->lmul >= 0; | ||
430 | +} | ||
431 | + | ||
432 | +GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS) | ||
433 | + | ||
434 | +static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a) | ||
435 | +{ | ||
436 | + if (vsha_check(s, a)) { | ||
437 | + uint32_t data = 0; | ||
438 | + TCGLabel *over = gen_new_label(); | ||
439 | + TCGv_i32 egs; | ||
440 | + | ||
441 | + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { | ||
442 | + /* save opcode for unwinding in case we throw an exception */ | ||
443 | + decode_save_opc(s); | ||
444 | + egs = tcg_constant_i32(ZVKNH_EGS); | ||
445 | + gen_helper_egs_check(egs, cpu_env); | ||
446 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
447 | + } | ||
448 | + | ||
449 | + data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
450 | + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); | ||
451 | + data = FIELD_DP32(data, VDATA, VTA, s->vta); | ||
452 | + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); | ||
453 | + data = FIELD_DP32(data, VDATA, VMA, s->vma); | ||
454 | + | ||
455 | + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), | ||
456 | + vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, | ||
457 | + s->cfg_ptr->vlen / 8, data, | ||
458 | + s->sew == MO_32 ? | ||
459 | + gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv); | ||
460 | + | ||
461 | + mark_vs_dirty(s); | ||
462 | + gen_set_label(over); | ||
463 | + return true; | ||
464 | + } | ||
465 | + return false; | ||
466 | +} | ||
467 | + | ||
468 | +static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a) | ||
469 | +{ | ||
470 | + if (vsha_check(s, a)) { | ||
471 | + uint32_t data = 0; | ||
472 | + TCGLabel *over = gen_new_label(); | ||
473 | + TCGv_i32 egs; | ||
474 | + | ||
475 | + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { | ||
476 | + /* save opcode for unwinding in case we throw an exception */ | ||
477 | + decode_save_opc(s); | ||
478 | + egs = tcg_constant_i32(ZVKNH_EGS); | ||
479 | + gen_helper_egs_check(egs, cpu_env); | ||
480 | + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); | ||
481 | + } | ||
482 | + | ||
483 | + data = FIELD_DP32(data, VDATA, VM, a->vm); | ||
484 | + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); | ||
485 | + data = FIELD_DP32(data, VDATA, VTA, s->vta); | ||
486 | + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); | ||
487 | + data = FIELD_DP32(data, VDATA, VMA, s->vma); | ||
488 | + | ||
489 | + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), | ||
490 | + vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, | ||
491 | + s->cfg_ptr->vlen / 8, data, | ||
492 | + s->sew == MO_32 ? | ||
493 | + gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv); | ||
494 | + | ||
495 | + mark_vs_dirty(s); | ||
496 | + gen_set_label(over); | ||
497 | + return true; | ||
498 | + } | ||
499 | + return false; | ||
500 | +} | ||
501 | -- | ||
502 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | |
2 | |||
3 | This commit adds support for the Zvksh vector-crypto extension, which | ||
4 | consists of the following instructions: | ||
5 | |||
6 | * vsm3me.vv | ||
7 | * vsm3c.vi | ||
8 | |||
9 | Translation functions are defined in | ||
10 | `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in | ||
11 | `target/riscv/vcrypto_helper.c`. | ||
12 | |||
13 | Co-authored-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
14 | [max.chou@sifive.com: Replaced vstart checking by TCG op] | ||
15 | Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> | ||
16 | Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | ||
17 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
18 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
19 | [max.chou@sifive.com: Exposed x-zvksh property] | ||
20 | Message-ID: <20230711165917.2629866-12-max.chou@sifive.com> | ||
21 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
22 | --- | ||
23 | target/riscv/cpu_cfg.h | 1 + | ||
24 | target/riscv/helper.h | 3 + | ||
25 | target/riscv/insn32.decode | 4 + | ||
26 | target/riscv/cpu.c | 6 +- | ||
27 | target/riscv/vcrypto_helper.c | 134 +++++++++++++++++++++++ | ||
28 | target/riscv/insn_trans/trans_rvvk.c.inc | 31 ++++++ | ||
29 | 6 files changed, 177 insertions(+), 2 deletions(-) | ||
30 | |||
31 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/riscv/cpu_cfg.h | ||
34 | +++ b/target/riscv/cpu_cfg.h | ||
35 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
36 | bool ext_zvkned; | ||
37 | bool ext_zvknha; | ||
38 | bool ext_zvknhb; | ||
39 | + bool ext_zvksh; | ||
40 | bool ext_zmmul; | ||
41 | bool ext_zvfbfmin; | ||
42 | bool ext_zvfbfwma; | ||
43 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/riscv/helper.h | ||
46 | +++ b/target/riscv/helper.h | ||
47 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32) | ||
48 | DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32) | ||
49 | DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32) | ||
50 | DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32) | ||
51 | + | ||
52 | +DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) | ||
53 | +DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) | ||
54 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/riscv/insn32.decode | ||
57 | +++ b/target/riscv/insn32.decode | ||
58 | @@ -XXX,XX +XXX,XX @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
59 | vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
60 | vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
61 | vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
62 | + | ||
63 | +# *** Zvksh vector crypto extension *** | ||
64 | +vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
65 | +vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
66 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/riscv/cpu.c | ||
69 | +++ b/target/riscv/cpu.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
71 | ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), | ||
72 | ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), | ||
73 | ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), | ||
74 | + ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), | ||
75 | ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), | ||
76 | ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), | ||
77 | ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), | ||
78 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
79 | * In principle Zve*x would also suffice here, were they supported | ||
80 | * in qemu | ||
81 | */ | ||
82 | - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) && | ||
83 | - !cpu->cfg.ext_zve32f) { | ||
84 | + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || | ||
85 | + cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { | ||
86 | error_setg(errp, | ||
87 | "Vector crypto extensions require V or Zve* extensions"); | ||
88 | return; | ||
89 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
90 | DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), | ||
91 | DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), | ||
92 | DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), | ||
93 | + DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), | ||
94 | |||
95 | DEFINE_PROP_END_OF_LIST(), | ||
96 | }; | ||
97 | diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c | ||
98 | index XXXXXXX..XXXXXXX 100644 | ||
99 | --- a/target/riscv/vcrypto_helper.c | ||
100 | +++ b/target/riscv/vcrypto_helper.c | ||
101 | @@ -XXX,XX +XXX,XX @@ void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, | ||
102 | vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); | ||
103 | env->vstart = 0; | ||
104 | } | ||
105 | + | ||
106 | +static inline uint32_t p1(uint32_t x) | ||
107 | +{ | ||
108 | + return x ^ rol32(x, 15) ^ rol32(x, 23); | ||
109 | +} | ||
110 | + | ||
111 | +static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3, | ||
112 | + uint32_t m13, uint32_t m6) | ||
113 | +{ | ||
114 | + return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6; | ||
115 | +} | ||
116 | + | ||
117 | +void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, | ||
118 | + CPURISCVState *env, uint32_t desc) | ||
119 | +{ | ||
120 | + uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); | ||
121 | + uint32_t total_elems = vext_get_total_elems(env, desc, esz); | ||
122 | + uint32_t vta = vext_vta(desc); | ||
123 | + uint32_t *vd = vd_vptr; | ||
124 | + uint32_t *vs1 = vs1_vptr; | ||
125 | + uint32_t *vs2 = vs2_vptr; | ||
126 | + | ||
127 | + for (int i = env->vstart / 8; i < env->vl / 8; i++) { | ||
128 | + uint32_t w[24]; | ||
129 | + for (int j = 0; j < 8; j++) { | ||
130 | + w[j] = bswap32(vs1[H4((i * 8) + j)]); | ||
131 | + w[j + 8] = bswap32(vs2[H4((i * 8) + j)]); | ||
132 | + } | ||
133 | + for (int j = 0; j < 8; j++) { | ||
134 | + w[j + 16] = | ||
135 | + zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]); | ||
136 | + } | ||
137 | + for (int j = 0; j < 8; j++) { | ||
138 | + vd[(i * 8) + j] = bswap32(w[H4(j + 16)]); | ||
139 | + } | ||
140 | + } | ||
141 | + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); | ||
142 | + env->vstart = 0; | ||
143 | +} | ||
144 | + | ||
145 | +static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z) | ||
146 | +{ | ||
147 | + return x ^ y ^ z; | ||
148 | +} | ||
149 | + | ||
150 | +static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z) | ||
151 | +{ | ||
152 | + return (x & y) | (x & z) | (y & z); | ||
153 | +} | ||
154 | + | ||
155 | +static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) | ||
156 | +{ | ||
157 | + return (j <= 15) ? ff1(x, y, z) : ff2(x, y, z); | ||
158 | +} | ||
159 | + | ||
160 | +static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z) | ||
161 | +{ | ||
162 | + return x ^ y ^ z; | ||
163 | +} | ||
164 | + | ||
165 | +static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z) | ||
166 | +{ | ||
167 | + return (x & y) | (~x & z); | ||
168 | +} | ||
169 | + | ||
170 | +static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) | ||
171 | +{ | ||
172 | + return (j <= 15) ? gg1(x, y, z) : gg2(x, y, z); | ||
173 | +} | ||
174 | + | ||
175 | +static inline uint32_t t_j(uint32_t j) | ||
176 | +{ | ||
177 | + return (j <= 15) ? 0x79cc4519 : 0x7a879d8a; | ||
178 | +} | ||
179 | + | ||
180 | +static inline uint32_t p_0(uint32_t x) | ||
181 | +{ | ||
182 | + return x ^ rol32(x, 9) ^ rol32(x, 17); | ||
183 | +} | ||
184 | + | ||
185 | +static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm) | ||
186 | +{ | ||
187 | + uint32_t x0, x1; | ||
188 | + uint32_t j; | ||
189 | + uint32_t ss1, ss2, tt1, tt2; | ||
190 | + x0 = vs2[0] ^ vs2[4]; | ||
191 | + x1 = vs2[1] ^ vs2[5]; | ||
192 | + j = 2 * uimm; | ||
193 | + ss1 = rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7); | ||
194 | + ss2 = ss1 ^ rol32(vs1[0], 12); | ||
195 | + tt1 = ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0; | ||
196 | + tt2 = gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0]; | ||
197 | + vs1[3] = vs1[2]; | ||
198 | + vd[3] = rol32(vs1[1], 9); | ||
199 | + vs1[1] = vs1[0]; | ||
200 | + vd[1] = tt1; | ||
201 | + vs1[7] = vs1[6]; | ||
202 | + vd[7] = rol32(vs1[5], 19); | ||
203 | + vs1[5] = vs1[4]; | ||
204 | + vd[5] = p_0(tt2); | ||
205 | + j = 2 * uimm + 1; | ||
206 | + ss1 = rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7); | ||
207 | + ss2 = ss1 ^ rol32(vd[1], 12); | ||
208 | + tt1 = ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1; | ||
209 | + tt2 = gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1]; | ||
210 | + vd[2] = rol32(vs1[1], 9); | ||
211 | + vd[0] = tt1; | ||
212 | + vd[6] = rol32(vs1[5], 19); | ||
213 | + vd[4] = p_0(tt2); | ||
214 | +} | ||
215 | + | ||
216 | +void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, | ||
217 | + CPURISCVState *env, uint32_t desc) | ||
218 | +{ | ||
219 | + uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); | ||
220 | + uint32_t total_elems = vext_get_total_elems(env, desc, esz); | ||
221 | + uint32_t vta = vext_vta(desc); | ||
222 | + uint32_t *vd = vd_vptr; | ||
223 | + uint32_t *vs2 = vs2_vptr; | ||
224 | + uint32_t v1[8], v2[8], v3[8]; | ||
225 | + | ||
226 | + for (int i = env->vstart / 8; i < env->vl / 8; i++) { | ||
227 | + for (int k = 0; k < 8; k++) { | ||
228 | + v2[k] = bswap32(vd[H4(i * 8 + k)]); | ||
229 | + v3[k] = bswap32(vs2[H4(i * 8 + k)]); | ||
230 | + } | ||
231 | + sm3c(v1, v2, v3, uimm); | ||
232 | + for (int k = 0; k < 8; k++) { | ||
233 | + vd[i * 8 + k] = bswap32(v1[H4(k)]); | ||
234 | + } | ||
235 | + } | ||
236 | + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); | ||
237 | + env->vstart = 0; | ||
238 | +} | ||
239 | diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
240 | index XXXXXXX..XXXXXXX 100644 | ||
241 | --- a/target/riscv/insn_trans/trans_rvvk.c.inc | ||
242 | +++ b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
243 | @@ -XXX,XX +XXX,XX @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a) | ||
244 | } | ||
245 | return false; | ||
246 | } | ||
247 | + | ||
248 | +/* | ||
249 | + * Zvksh | ||
250 | + */ | ||
251 | + | ||
252 | +#define ZVKSH_EGS 8 | ||
253 | + | ||
254 | +static inline bool vsm3_check(DisasContext *s, arg_rmrr *a) | ||
255 | +{ | ||
256 | + int egw_bytes = ZVKSH_EGS << s->sew; | ||
257 | + int mult = 1 << MAX(s->lmul, 0); | ||
258 | + return s->cfg_ptr->ext_zvksh == true && | ||
259 | + require_rvv(s) && | ||
260 | + vext_check_isa_ill(s) && | ||
261 | + !is_overlapped(a->rd, mult, a->rs2, mult) && | ||
262 | + MAXSZ(s) >= egw_bytes && | ||
263 | + s->sew == MO_32; | ||
264 | +} | ||
265 | + | ||
266 | +static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a) | ||
267 | +{ | ||
268 | + return vsm3_check(s, a) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); | ||
269 | +} | ||
270 | + | ||
271 | +static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) | ||
272 | +{ | ||
273 | + return vsm3_check(s, a) && vext_check_ss(s, a->rd, a->rs2, a->vm); | ||
274 | +} | ||
275 | + | ||
276 | +GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) | ||
277 | +GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) | ||
278 | -- | ||
279 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | |
2 | |||
3 | This commit adds support for the Zvkg vector-crypto extension, which | ||
4 | consists of the following instructions: | ||
5 | |||
6 | * vgmul.vv | ||
7 | * vghsh.vv | ||
8 | |||
9 | Translation functions are defined in | ||
10 | `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in | ||
11 | `target/riscv/vcrypto_helper.c`. | ||
12 | |||
13 | Co-authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | ||
14 | [max.chou@sifive.com: Replaced vstart checking by TCG op] | ||
15 | Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> | ||
16 | Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> | ||
17 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
18 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
19 | [max.chou@sifive.com: Exposed x-zvkg property] | ||
20 | [max.chou@sifive.com: Replaced uint by int for cross win32 build] | ||
21 | Message-ID: <20230711165917.2629866-13-max.chou@sifive.com> | ||
22 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
23 | --- | ||
24 | target/riscv/cpu_cfg.h | 1 + | ||
25 | target/riscv/helper.h | 3 + | ||
26 | target/riscv/insn32.decode | 4 ++ | ||
27 | target/riscv/cpu.c | 6 +- | ||
28 | target/riscv/vcrypto_helper.c | 72 ++++++++++++++++++++++++ | ||
29 | target/riscv/insn_trans/trans_rvvk.c.inc | 30 ++++++++++ | ||
30 | 6 files changed, 114 insertions(+), 2 deletions(-) | ||
31 | |||
32 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/riscv/cpu_cfg.h | ||
35 | +++ b/target/riscv/cpu_cfg.h | ||
36 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
37 | bool ext_zve64d; | ||
38 | bool ext_zvbb; | ||
39 | bool ext_zvbc; | ||
40 | + bool ext_zvkg; | ||
41 | bool ext_zvkned; | ||
42 | bool ext_zvknha; | ||
43 | bool ext_zvknhb; | ||
44 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/riscv/helper.h | ||
47 | +++ b/target/riscv/helper.h | ||
48 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32) | ||
49 | |||
50 | DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) | ||
51 | DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) | ||
52 | + | ||
53 | +DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) | ||
54 | +DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) | ||
55 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/riscv/insn32.decode | ||
58 | +++ b/target/riscv/insn32.decode | ||
59 | @@ -XXX,XX +XXX,XX @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
60 | # *** Zvksh vector crypto extension *** | ||
61 | vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
62 | vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
63 | + | ||
64 | +# *** Zvkg vector crypto extension *** | ||
65 | +vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
66 | +vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 | ||
67 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/target/riscv/cpu.c | ||
70 | +++ b/target/riscv/cpu.c | ||
71 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
72 | ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), | ||
73 | ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), | ||
74 | ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), | ||
75 | + ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), | ||
76 | ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), | ||
77 | ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), | ||
78 | ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), | ||
79 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
80 | * In principle Zve*x would also suffice here, were they supported | ||
81 | * in qemu | ||
82 | */ | ||
83 | - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || | ||
84 | - cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { | ||
85 | + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || | ||
86 | + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { | ||
87 | error_setg(errp, | ||
88 | "Vector crypto extensions require V or Zve* extensions"); | ||
89 | return; | ||
90 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
91 | /* Vector cryptography extensions */ | ||
92 | DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), | ||
93 | DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), | ||
94 | + DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false), | ||
95 | DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), | ||
96 | DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), | ||
97 | DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), | ||
98 | diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/target/riscv/vcrypto_helper.c | ||
101 | +++ b/target/riscv/vcrypto_helper.c | ||
102 | @@ -XXX,XX +XXX,XX @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, | ||
103 | vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); | ||
104 | env->vstart = 0; | ||
105 | } | ||
106 | + | ||
107 | +void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, | ||
108 | + CPURISCVState *env, uint32_t desc) | ||
109 | +{ | ||
110 | + uint64_t *vd = vd_vptr; | ||
111 | + uint64_t *vs1 = vs1_vptr; | ||
112 | + uint64_t *vs2 = vs2_vptr; | ||
113 | + uint32_t vta = vext_vta(desc); | ||
114 | + uint32_t total_elems = vext_get_total_elems(env, desc, 4); | ||
115 | + | ||
116 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
117 | + uint64_t Y[2] = {vd[i * 2 + 0], vd[i * 2 + 1]}; | ||
118 | + uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; | ||
119 | + uint64_t X[2] = {vs1[i * 2 + 0], vs1[i * 2 + 1]}; | ||
120 | + uint64_t Z[2] = {0, 0}; | ||
121 | + | ||
122 | + uint64_t S[2] = {brev8(Y[0] ^ X[0]), brev8(Y[1] ^ X[1])}; | ||
123 | + | ||
124 | + for (int j = 0; j < 128; j++) { | ||
125 | + if ((S[j / 64] >> (j % 64)) & 1) { | ||
126 | + Z[0] ^= H[0]; | ||
127 | + Z[1] ^= H[1]; | ||
128 | + } | ||
129 | + bool reduce = ((H[1] >> 63) & 1); | ||
130 | + H[1] = H[1] << 1 | H[0] >> 63; | ||
131 | + H[0] = H[0] << 1; | ||
132 | + if (reduce) { | ||
133 | + H[0] ^= 0x87; | ||
134 | + } | ||
135 | + } | ||
136 | + | ||
137 | + vd[i * 2 + 0] = brev8(Z[0]); | ||
138 | + vd[i * 2 + 1] = brev8(Z[1]); | ||
139 | + } | ||
140 | + /* set tail elements to 1s */ | ||
141 | + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); | ||
142 | + env->vstart = 0; | ||
143 | +} | ||
144 | + | ||
145 | +void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, | ||
146 | + uint32_t desc) | ||
147 | +{ | ||
148 | + uint64_t *vd = vd_vptr; | ||
149 | + uint64_t *vs2 = vs2_vptr; | ||
150 | + uint32_t vta = vext_vta(desc); | ||
151 | + uint32_t total_elems = vext_get_total_elems(env, desc, 4); | ||
152 | + | ||
153 | + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { | ||
154 | + uint64_t Y[2] = {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])}; | ||
155 | + uint64_t H[2] = {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; | ||
156 | + uint64_t Z[2] = {0, 0}; | ||
157 | + | ||
158 | + for (int j = 0; j < 128; j++) { | ||
159 | + if ((Y[j / 64] >> (j % 64)) & 1) { | ||
160 | + Z[0] ^= H[0]; | ||
161 | + Z[1] ^= H[1]; | ||
162 | + } | ||
163 | + bool reduce = ((H[1] >> 63) & 1); | ||
164 | + H[1] = H[1] << 1 | H[0] >> 63; | ||
165 | + H[0] = H[0] << 1; | ||
166 | + if (reduce) { | ||
167 | + H[0] ^= 0x87; | ||
168 | + } | ||
169 | + } | ||
170 | + | ||
171 | + vd[i * 2 + 0] = brev8(Z[0]); | ||
172 | + vd[i * 2 + 1] = brev8(Z[1]); | ||
173 | + } | ||
174 | + /* set tail elements to 1s */ | ||
175 | + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); | ||
176 | + env->vstart = 0; | ||
177 | +} | ||
178 | diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
179 | index XXXXXXX..XXXXXXX 100644 | ||
180 | --- a/target/riscv/insn_trans/trans_rvvk.c.inc | ||
181 | +++ b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
182 | @@ -XXX,XX +XXX,XX @@ static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) | ||
183 | |||
184 | GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) | ||
185 | GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) | ||
186 | + | ||
187 | +/* | ||
188 | + * Zvkg | ||
189 | + */ | ||
190 | + | ||
191 | +#define ZVKG_EGS 4 | ||
192 | + | ||
193 | +static bool vgmul_check(DisasContext *s, arg_rmr *a) | ||
194 | +{ | ||
195 | + int egw_bytes = ZVKG_EGS << s->sew; | ||
196 | + return s->cfg_ptr->ext_zvkg == true && | ||
197 | + vext_check_isa_ill(s) && | ||
198 | + require_rvv(s) && | ||
199 | + MAXSZ(s) >= egw_bytes && | ||
200 | + vext_check_ss(s, a->rd, a->rs2, a->vm) && | ||
201 | + s->sew == MO_32; | ||
202 | +} | ||
203 | + | ||
204 | +GEN_V_UNMASKED_TRANS(vgmul_vv, vgmul_check, ZVKG_EGS) | ||
205 | + | ||
206 | +static bool vghsh_check(DisasContext *s, arg_rmrr *a) | ||
207 | +{ | ||
208 | + int egw_bytes = ZVKG_EGS << s->sew; | ||
209 | + return s->cfg_ptr->ext_zvkg == true && | ||
210 | + opivv_check(s, a) && | ||
211 | + MAXSZ(s) >= egw_bytes && | ||
212 | + s->sew == MO_32; | ||
213 | +} | ||
214 | + | ||
215 | +GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) | ||
216 | -- | ||
217 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Max Chou <max.chou@sifive.com> | ||
1 | 2 | ||
3 | Allows sharing of sm4_subword between different targets. | ||
4 | |||
5 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
6 | Reviewed-by: Frank Chang <frank.chang@sifive.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
9 | Message-ID: <20230711165917.2629866-14-max.chou@sifive.com> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | include/crypto/sm4.h | 8 ++++++++ | ||
13 | target/arm/tcg/crypto_helper.c | 10 ++-------- | ||
14 | 2 files changed, 10 insertions(+), 8 deletions(-) | ||
15 | |||
16 | diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/crypto/sm4.h | ||
19 | +++ b/include/crypto/sm4.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | |||
22 | extern const uint8_t sm4_sbox[256]; | ||
23 | |||
24 | +static inline uint32_t sm4_subword(uint32_t word) | ||
25 | +{ | ||
26 | + return sm4_sbox[word & 0xff] | | ||
27 | + sm4_sbox[(word >> 8) & 0xff] << 8 | | ||
28 | + sm4_sbox[(word >> 16) & 0xff] << 16 | | ||
29 | + sm4_sbox[(word >> 24) & 0xff] << 24; | ||
30 | +} | ||
31 | + | ||
32 | #endif | ||
33 | diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/tcg/crypto_helper.c | ||
36 | +++ b/target/arm/tcg/crypto_helper.c | ||
37 | @@ -XXX,XX +XXX,XX @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm) | ||
38 | CR_ST_WORD(d, (i + 3) % 4) ^ | ||
39 | CR_ST_WORD(n, i); | ||
40 | |||
41 | - t = sm4_sbox[t & 0xff] | | ||
42 | - sm4_sbox[(t >> 8) & 0xff] << 8 | | ||
43 | - sm4_sbox[(t >> 16) & 0xff] << 16 | | ||
44 | - sm4_sbox[(t >> 24) & 0xff] << 24; | ||
45 | + t = sm4_subword(t); | ||
46 | |||
47 | CR_ST_WORD(d, i) ^= t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18) ^ | ||
48 | rol32(t, 24); | ||
49 | @@ -XXX,XX +XXX,XX @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm) | ||
50 | CR_ST_WORD(d, (i + 3) % 4) ^ | ||
51 | CR_ST_WORD(m, i); | ||
52 | |||
53 | - t = sm4_sbox[t & 0xff] | | ||
54 | - sm4_sbox[(t >> 8) & 0xff] << 8 | | ||
55 | - sm4_sbox[(t >> 16) & 0xff] << 16 | | ||
56 | - sm4_sbox[(t >> 24) & 0xff] << 24; | ||
57 | + t = sm4_subword(t); | ||
58 | |||
59 | CR_ST_WORD(d, i) ^= t ^ rol32(t, 13) ^ rol32(t, 23); | ||
60 | } | ||
61 | -- | ||
62 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Yifei Jiang <jiangyifei@huawei.com> | 1 | From: Max Chou <max.chou@sifive.com> |
---|---|---|---|
2 | 2 | ||
3 | In the case of supporting H extension, add H extension description | 3 | Adds sm4_ck constant for use in sm4 cryptography across different targets. |
4 | to vmstate_riscv_cpu. | ||
5 | 4 | ||
6 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | 5 | Signed-off-by: Max Chou <max.chou@sifive.com> |
7 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | 6 | Reviewed-by: Frank Chang <frank.chang@sifive.com> |
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Signed-off-by: Max Chou <max.chou@sifive.com> |
9 | Message-id: 20201026115530.304-5-jiangyifei@huawei.com | 8 | Message-ID: <20230711165917.2629866-15-max.chou@sifive.com> |
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
11 | --- | 10 | --- |
12 | target/riscv/machine.c | 47 ++++++++++++++++++++++++++++++++++++++++++ | 11 | include/crypto/sm4.h | 1 + |
13 | 1 file changed, 47 insertions(+) | 12 | crypto/sm4.c | 10 ++++++++++ |
13 | 2 files changed, 11 insertions(+) | ||
14 | 14 | ||
15 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | 15 | diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/riscv/machine.c | 17 | --- a/include/crypto/sm4.h |
18 | +++ b/target/riscv/machine.c | 18 | +++ b/include/crypto/sm4.h |
19 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmp = { | 19 | @@ -XXX,XX +XXX,XX @@ |
20 | } | 20 | #define QEMU_SM4_H |
21 | |||
22 | extern const uint8_t sm4_sbox[256]; | ||
23 | +extern const uint32_t sm4_ck[32]; | ||
24 | |||
25 | static inline uint32_t sm4_subword(uint32_t word) | ||
26 | { | ||
27 | diff --git a/crypto/sm4.c b/crypto/sm4.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/crypto/sm4.c | ||
30 | +++ b/crypto/sm4.c | ||
31 | @@ -XXX,XX +XXX,XX @@ uint8_t const sm4_sbox[] = { | ||
32 | 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48, | ||
21 | }; | 33 | }; |
22 | 34 | ||
23 | +static bool hyper_needed(void *opaque) | 35 | +uint32_t const sm4_ck[] = { |
24 | +{ | 36 | + 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269, |
25 | + RISCVCPU *cpu = opaque; | 37 | + 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9, |
26 | + CPURISCVState *env = &cpu->env; | 38 | + 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249, |
27 | + | 39 | + 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9, |
28 | + return riscv_has_ext(env, RVH); | 40 | + 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229, |
29 | +} | 41 | + 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299, |
30 | + | 42 | + 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209, |
31 | +static const VMStateDescription vmstate_hyper = { | 43 | + 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 |
32 | + .name = "cpu/hyper", | ||
33 | + .version_id = 1, | ||
34 | + .minimum_version_id = 1, | ||
35 | + .needed = hyper_needed, | ||
36 | + .fields = (VMStateField[]) { | ||
37 | + VMSTATE_UINTTL(env.hstatus, RISCVCPU), | ||
38 | + VMSTATE_UINTTL(env.hedeleg, RISCVCPU), | ||
39 | + VMSTATE_UINTTL(env.hideleg, RISCVCPU), | ||
40 | + VMSTATE_UINTTL(env.hcounteren, RISCVCPU), | ||
41 | + VMSTATE_UINTTL(env.htval, RISCVCPU), | ||
42 | + VMSTATE_UINTTL(env.htinst, RISCVCPU), | ||
43 | + VMSTATE_UINTTL(env.hgatp, RISCVCPU), | ||
44 | + VMSTATE_UINT64(env.htimedelta, RISCVCPU), | ||
45 | + | ||
46 | + VMSTATE_UINT64(env.vsstatus, RISCVCPU), | ||
47 | + VMSTATE_UINTTL(env.vstvec, RISCVCPU), | ||
48 | + VMSTATE_UINTTL(env.vsscratch, RISCVCPU), | ||
49 | + VMSTATE_UINTTL(env.vsepc, RISCVCPU), | ||
50 | + VMSTATE_UINTTL(env.vscause, RISCVCPU), | ||
51 | + VMSTATE_UINTTL(env.vstval, RISCVCPU), | ||
52 | + VMSTATE_UINTTL(env.vsatp, RISCVCPU), | ||
53 | + | ||
54 | + VMSTATE_UINTTL(env.mtval2, RISCVCPU), | ||
55 | + VMSTATE_UINTTL(env.mtinst, RISCVCPU), | ||
56 | + | ||
57 | + VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), | ||
58 | + VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), | ||
59 | + VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), | ||
60 | + VMSTATE_UINTTL(env.scause_hs, RISCVCPU), | ||
61 | + VMSTATE_UINTTL(env.stval_hs, RISCVCPU), | ||
62 | + VMSTATE_UINTTL(env.satp_hs, RISCVCPU), | ||
63 | + VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), | ||
64 | + | ||
65 | + VMSTATE_END_OF_LIST() | ||
66 | + } | ||
67 | +}; | 44 | +}; |
68 | + | ||
69 | const VMStateDescription vmstate_riscv_cpu = { | ||
70 | .name = "cpu", | ||
71 | .version_id = 1, | ||
72 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = { | ||
73 | }, | ||
74 | .subsections = (const VMStateDescription * []) { | ||
75 | &vmstate_pmp, | ||
76 | + &vmstate_hyper, | ||
77 | NULL | ||
78 | } | ||
79 | }; | ||
80 | -- | 45 | -- |
81 | 2.28.0 | 46 | 2.41.0 |
82 | |||
83 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Max Chou <max.chou@sifive.com> | |
2 | |||
3 | This commit adds support for the Zvksed vector-crypto extension, which | ||
4 | consists of the following instructions: | ||
5 | |||
6 | * vsm4k.vi | ||
7 | * vsm4r.[vv,vs] | ||
8 | |||
9 | Translation functions are defined in | ||
10 | `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in | ||
11 | `target/riscv/vcrypto_helper.c`. | ||
12 | |||
13 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
14 | Reviewed-by: Frank Chang <frank.chang@sifive.com> | ||
15 | [lawrence.hunter@codethink.co.uk: Moved SM4 functions from | ||
16 | crypto_helper.c to vcrypto_helper.c] | ||
17 | [nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to | ||
18 | use macros, and minor style changes] | ||
19 | Signed-off-by: Max Chou <max.chou@sifive.com> | ||
20 | Message-ID: <20230711165917.2629866-16-max.chou@sifive.com> | ||
21 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
22 | --- | ||
23 | target/riscv/cpu_cfg.h | 1 + | ||
24 | target/riscv/helper.h | 4 + | ||
25 | target/riscv/insn32.decode | 5 + | ||
26 | target/riscv/cpu.c | 5 +- | ||
27 | target/riscv/vcrypto_helper.c | 127 +++++++++++++++++++++++ | ||
28 | target/riscv/insn_trans/trans_rvvk.c.inc | 43 ++++++++ | ||
29 | 6 files changed, 184 insertions(+), 1 deletion(-) | ||
30 | |||
31 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/riscv/cpu_cfg.h | ||
34 | +++ b/target/riscv/cpu_cfg.h | ||
35 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
36 | bool ext_zvkned; | ||
37 | bool ext_zvknha; | ||
38 | bool ext_zvknhb; | ||
39 | + bool ext_zvksed; | ||
40 | bool ext_zvksh; | ||
41 | bool ext_zmmul; | ||
42 | bool ext_zvfbfmin; | ||
43 | diff --git a/target/riscv/helper.h b/target/riscv/helper.h | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/riscv/helper.h | ||
46 | +++ b/target/riscv/helper.h | ||
47 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) | ||
48 | |||
49 | DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) | ||
50 | DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) | ||
51 | + | ||
52 | +DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32) | ||
53 | +DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32) | ||
54 | +DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32) | ||
55 | diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/riscv/insn32.decode | ||
58 | +++ b/target/riscv/insn32.decode | ||
59 | @@ -XXX,XX +XXX,XX @@ vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
60 | # *** Zvkg vector crypto extension *** | ||
61 | vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
62 | vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 | ||
63 | + | ||
64 | +# *** Zvksed vector crypto extension *** | ||
65 | +vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 | ||
66 | +vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 | ||
67 | +vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 | ||
68 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/target/riscv/cpu.c | ||
71 | +++ b/target/riscv/cpu.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
73 | ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), | ||
74 | ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), | ||
75 | ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), | ||
76 | + ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), | ||
77 | ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), | ||
78 | ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), | ||
79 | ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), | ||
80 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
81 | * in qemu | ||
82 | */ | ||
83 | if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || | ||
84 | - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { | ||
85 | + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) && | ||
86 | + !cpu->cfg.ext_zve32f) { | ||
87 | error_setg(errp, | ||
88 | "Vector crypto extensions require V or Zve* extensions"); | ||
89 | return; | ||
90 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
91 | DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), | ||
92 | DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), | ||
93 | DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), | ||
94 | + DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false), | ||
95 | DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), | ||
96 | |||
97 | DEFINE_PROP_END_OF_LIST(), | ||
98 | diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/target/riscv/vcrypto_helper.c | ||
101 | +++ b/target/riscv/vcrypto_helper.c | ||
102 | @@ -XXX,XX +XXX,XX @@ | ||
103 | #include "cpu.h" | ||
104 | #include "crypto/aes.h" | ||
105 | #include "crypto/aes-round.h" | ||
106 | +#include "crypto/sm4.h" | ||
107 | #include "exec/memop.h" | ||
108 | #include "exec/exec-all.h" | ||
109 | #include "exec/helper-proto.h" | ||
110 | @@ -XXX,XX +XXX,XX @@ void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, | ||
111 | vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); | ||
112 | env->vstart = 0; | ||
113 | } | ||
114 | + | ||
115 | +void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uimm5, CPURISCVState *env, | ||
116 | + uint32_t desc) | ||
117 | +{ | ||
118 | + const uint32_t egs = 4; | ||
119 | + uint32_t rnd = uimm5 & 0x7; | ||
120 | + uint32_t group_start = env->vstart / egs; | ||
121 | + uint32_t group_end = env->vl / egs; | ||
122 | + uint32_t esz = sizeof(uint32_t); | ||
123 | + uint32_t total_elems = vext_get_total_elems(env, desc, esz); | ||
124 | + | ||
125 | + for (uint32_t i = group_start; i < group_end; ++i) { | ||
126 | + uint32_t vstart = i * egs; | ||
127 | + uint32_t vend = (i + 1) * egs; | ||
128 | + uint32_t rk[4] = {0}; | ||
129 | + uint32_t tmp[8] = {0}; | ||
130 | + | ||
131 | + for (uint32_t j = vstart; j < vend; ++j) { | ||
132 | + rk[j - vstart] = *((uint32_t *)vs2 + H4(j)); | ||
133 | + } | ||
134 | + | ||
135 | + for (uint32_t j = 0; j < egs; ++j) { | ||
136 | + tmp[j] = rk[j]; | ||
137 | + } | ||
138 | + | ||
139 | + for (uint32_t j = 0; j < egs; ++j) { | ||
140 | + uint32_t b, s; | ||
141 | + b = tmp[j + 1] ^ tmp[j + 2] ^ tmp[j + 3] ^ sm4_ck[rnd * 4 + j]; | ||
142 | + | ||
143 | + s = sm4_subword(b); | ||
144 | + | ||
145 | + tmp[j + 4] = tmp[j] ^ (s ^ rol32(s, 13) ^ rol32(s, 23)); | ||
146 | + } | ||
147 | + | ||
148 | + for (uint32_t j = vstart; j < vend; ++j) { | ||
149 | + *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)]; | ||
150 | + } | ||
151 | + } | ||
152 | + | ||
153 | + env->vstart = 0; | ||
154 | + /* set tail elements to 1s */ | ||
155 | + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz); | ||
156 | +} | ||
157 | + | ||
158 | +static void do_sm4_round(uint32_t *rk, uint32_t *buf) | ||
159 | +{ | ||
160 | + const uint32_t egs = 4; | ||
161 | + uint32_t s, b; | ||
162 | + | ||
163 | + for (uint32_t j = egs; j < egs * 2; ++j) { | ||
164 | + b = buf[j - 3] ^ buf[j - 2] ^ buf[j - 1] ^ rk[j - 4]; | ||
165 | + | ||
166 | + s = sm4_subword(b); | ||
167 | + | ||
168 | + buf[j] = buf[j - 4] ^ (s ^ rol32(s, 2) ^ rol32(s, 10) ^ rol32(s, 18) ^ | ||
169 | + rol32(s, 24)); | ||
170 | + } | ||
171 | +} | ||
172 | + | ||
173 | +void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) | ||
174 | +{ | ||
175 | + const uint32_t egs = 4; | ||
176 | + uint32_t group_start = env->vstart / egs; | ||
177 | + uint32_t group_end = env->vl / egs; | ||
178 | + uint32_t esz = sizeof(uint32_t); | ||
179 | + uint32_t total_elems = vext_get_total_elems(env, desc, esz); | ||
180 | + | ||
181 | + for (uint32_t i = group_start; i < group_end; ++i) { | ||
182 | + uint32_t vstart = i * egs; | ||
183 | + uint32_t vend = (i + 1) * egs; | ||
184 | + uint32_t rk[4] = {0}; | ||
185 | + uint32_t tmp[8] = {0}; | ||
186 | + | ||
187 | + for (uint32_t j = vstart; j < vend; ++j) { | ||
188 | + rk[j - vstart] = *((uint32_t *)vs2 + H4(j)); | ||
189 | + } | ||
190 | + | ||
191 | + for (uint32_t j = vstart; j < vend; ++j) { | ||
192 | + tmp[j - vstart] = *((uint32_t *)vd + H4(j)); | ||
193 | + } | ||
194 | + | ||
195 | + do_sm4_round(rk, tmp); | ||
196 | + | ||
197 | + for (uint32_t j = vstart; j < vend; ++j) { | ||
198 | + *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)]; | ||
199 | + } | ||
200 | + } | ||
201 | + | ||
202 | + env->vstart = 0; | ||
203 | + /* set tail elements to 1s */ | ||
204 | + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz); | ||
205 | +} | ||
206 | + | ||
207 | +void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) | ||
208 | +{ | ||
209 | + const uint32_t egs = 4; | ||
210 | + uint32_t group_start = env->vstart / egs; | ||
211 | + uint32_t group_end = env->vl / egs; | ||
212 | + uint32_t esz = sizeof(uint32_t); | ||
213 | + uint32_t total_elems = vext_get_total_elems(env, desc, esz); | ||
214 | + | ||
215 | + for (uint32_t i = group_start; i < group_end; ++i) { | ||
216 | + uint32_t vstart = i * egs; | ||
217 | + uint32_t vend = (i + 1) * egs; | ||
218 | + uint32_t rk[4] = {0}; | ||
219 | + uint32_t tmp[8] = {0}; | ||
220 | + | ||
221 | + for (uint32_t j = 0; j < egs; ++j) { | ||
222 | + rk[j] = *((uint32_t *)vs2 + H4(j)); | ||
223 | + } | ||
224 | + | ||
225 | + for (uint32_t j = vstart; j < vend; ++j) { | ||
226 | + tmp[j - vstart] = *((uint32_t *)vd + H4(j)); | ||
227 | + } | ||
228 | + | ||
229 | + do_sm4_round(rk, tmp); | ||
230 | + | ||
231 | + for (uint32_t j = vstart; j < vend; ++j) { | ||
232 | + *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)]; | ||
233 | + } | ||
234 | + } | ||
235 | + | ||
236 | + env->vstart = 0; | ||
237 | + /* set tail elements to 1s */ | ||
238 | + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz); | ||
239 | +} | ||
240 | diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
241 | index XXXXXXX..XXXXXXX 100644 | ||
242 | --- a/target/riscv/insn_trans/trans_rvvk.c.inc | ||
243 | +++ b/target/riscv/insn_trans/trans_rvvk.c.inc | ||
244 | @@ -XXX,XX +XXX,XX @@ static bool vghsh_check(DisasContext *s, arg_rmrr *a) | ||
245 | } | ||
246 | |||
247 | GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) | ||
248 | + | ||
249 | +/* | ||
250 | + * Zvksed | ||
251 | + */ | ||
252 | + | ||
253 | +#define ZVKSED_EGS 4 | ||
254 | + | ||
255 | +static bool zvksed_check(DisasContext *s) | ||
256 | +{ | ||
257 | + int egw_bytes = ZVKSED_EGS << s->sew; | ||
258 | + return s->cfg_ptr->ext_zvksed == true && | ||
259 | + require_rvv(s) && | ||
260 | + vext_check_isa_ill(s) && | ||
261 | + MAXSZ(s) >= egw_bytes && | ||
262 | + s->sew == MO_32; | ||
263 | +} | ||
264 | + | ||
265 | +static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a) | ||
266 | +{ | ||
267 | + return zvksed_check(s) && | ||
268 | + require_align(a->rd, s->lmul) && | ||
269 | + require_align(a->rs2, s->lmul); | ||
270 | +} | ||
271 | + | ||
272 | +GEN_VI_UNMASKED_TRANS(vsm4k_vi, vsm4k_vi_check, ZVKSED_EGS) | ||
273 | + | ||
274 | +static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a) | ||
275 | +{ | ||
276 | + return zvksed_check(s) && | ||
277 | + require_align(a->rd, s->lmul) && | ||
278 | + require_align(a->rs2, s->lmul); | ||
279 | +} | ||
280 | + | ||
281 | +GEN_V_UNMASKED_TRANS(vsm4r_vv, vsm4r_vv_check, ZVKSED_EGS) | ||
282 | + | ||
283 | +static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a) | ||
284 | +{ | ||
285 | + return zvksed_check(s) && | ||
286 | + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && | ||
287 | + require_align(a->rd, s->lmul); | ||
288 | +} | ||
289 | + | ||
290 | +GEN_V_UNMASKED_TRANS(vsm4r_vs, vsm4r_vs_check, ZVKSED_EGS) | ||
291 | -- | ||
292 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Rob Bradford <rbradford@rivosinc.com> | ||
1 | 2 | ||
3 | These are WARL fields - zero out the bits for unavailable counters and | ||
4 | special case the TM bit in mcountinhibit which is hardwired to zero. | ||
5 | This patch achieves this by modifying the value written so that any use | ||
6 | of the field will see the correctly masked bits. | ||
7 | |||
8 | Tested by modifying OpenSBI to write max value to these CSRs and upon | ||
9 | subsequent read the appropriate number of bits for number of PMUs is | ||
10 | enabled and the TM bit is zero in mcountinhibit. | ||
11 | |||
12 | Signed-off-by: Rob Bradford <rbradford@rivosinc.com> | ||
13 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | Reviewed-by: Atish Patra <atishp@rivosinc.com> | ||
15 | Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com> | ||
16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | --- | ||
18 | target/riscv/csr.c | 11 +++++++++-- | ||
19 | 1 file changed, 9 insertions(+), 2 deletions(-) | ||
20 | |||
21 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/riscv/csr.c | ||
24 | +++ b/target/riscv/csr.c | ||
25 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, | ||
26 | { | ||
27 | int cidx; | ||
28 | PMUCTRState *counter; | ||
29 | + RISCVCPU *cpu = env_archcpu(env); | ||
30 | |||
31 | - env->mcountinhibit = val; | ||
32 | + /* WARL register - disable unavailable counters; TM bit is always 0 */ | ||
33 | + env->mcountinhibit = | ||
34 | + val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR); | ||
35 | |||
36 | /* Check if any other counter is also monitoring cycles/instructions */ | ||
37 | for (cidx = 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { | ||
38 | @@ -XXX,XX +XXX,XX @@ static RISCVException read_mcounteren(CPURISCVState *env, int csrno, | ||
39 | static RISCVException write_mcounteren(CPURISCVState *env, int csrno, | ||
40 | target_ulong val) | ||
41 | { | ||
42 | - env->mcounteren = val; | ||
43 | + RISCVCPU *cpu = env_archcpu(env); | ||
44 | + | ||
45 | + /* WARL register - disable unavailable counters */ | ||
46 | + env->mcounteren = val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_TM | | ||
47 | + COUNTEREN_IR); | ||
48 | return RISCV_EXCP_NONE; | ||
49 | } | ||
50 | |||
51 | -- | ||
52 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jason Chien <jason.chien@sifive.com> | ||
1 | 2 | ||
3 | RVA23 Profiles states: | ||
4 | The RVA23 profiles are intended to be used for 64-bit application | ||
5 | processors that will run rich OS stacks from standard binary OS | ||
6 | distributions and with a substantial number of third-party binary user | ||
7 | applications that will be supported over a considerable length of time | ||
8 | in the field. | ||
9 | |||
10 | The chapter 4 of the unprivileged spec introduces the Zihintntl extension | ||
11 | and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose | ||
12 | purpose is to enable application and operating system portability across | ||
13 | different implementations. Thus the DTS should contain the Zihintntl ISA | ||
14 | string in order to pass to software. | ||
15 | |||
16 | The unprivileged spec states: | ||
17 | Like any HINTs, these instructions may be freely ignored. Hence, although | ||
18 | they are described in terms of cache-based memory hierarchies, they do not | ||
19 | mandate the provision of caches. | ||
20 | |||
21 | These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2, | ||
22 | which QEMU already supports, and QEMU does not emulate cache. Therefore | ||
23 | these instructions can be considered as a no-op, and we only need to add | ||
24 | a new property for the Zihintntl extension. | ||
25 | |||
26 | Reviewed-by: Frank Chang <frank.chang@sifive.com> | ||
27 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
28 | Signed-off-by: Jason Chien <jason.chien@sifive.com> | ||
29 | Message-ID: <20230726074049.19505-2-jason.chien@sifive.com> | ||
30 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
31 | --- | ||
32 | target/riscv/cpu_cfg.h | 1 + | ||
33 | target/riscv/cpu.c | 2 ++ | ||
34 | 2 files changed, 3 insertions(+) | ||
35 | |||
36 | diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/riscv/cpu_cfg.h | ||
39 | +++ b/target/riscv/cpu_cfg.h | ||
40 | @@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig { | ||
41 | bool ext_icbom; | ||
42 | bool ext_icboz; | ||
43 | bool ext_zicond; | ||
44 | + bool ext_zihintntl; | ||
45 | bool ext_zihintpause; | ||
46 | bool ext_smstateen; | ||
47 | bool ext_sstc; | ||
48 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/riscv/cpu.c | ||
51 | +++ b/target/riscv/cpu.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static const struct isa_ext_data isa_edata_arr[] = { | ||
53 | ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), | ||
54 | ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), | ||
55 | ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), | ||
56 | + ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), | ||
57 | ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), | ||
58 | ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), | ||
59 | ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), | ||
60 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
61 | DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), | ||
62 | DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), | ||
63 | DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), | ||
64 | + DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true), | ||
65 | DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), | ||
66 | DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), | ||
67 | DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), | ||
68 | -- | ||
69 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
1 | 2 | ||
3 | Commit a47842d ("riscv: Add support for the Zfa extension") implemented the zfa extension. | ||
4 | However, it has some typos for fleq.d and fltq.d. Both of them misused the fltq.s | ||
5 | helper function. | ||
6 | |||
7 | Fixes: a47842d ("riscv: Add support for the Zfa extension") | ||
8 | Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
9 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
10 | Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> | ||
11 | Message-ID: <20230728003906.768-1-zhiwei_liu@linux.alibaba.com> | ||
12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | --- | ||
14 | target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++-- | ||
15 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
16 | |||
17 | diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_trans/trans_rvzfa.c.inc | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/riscv/insn_trans/trans_rvzfa.c.inc | ||
20 | +++ b/target/riscv/insn_trans/trans_rvzfa.c.inc | ||
21 | @@ -XXX,XX +XXX,XX @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a) | ||
22 | TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
23 | TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
24 | |||
25 | - gen_helper_fltq_s(dest, cpu_env, src1, src2); | ||
26 | + gen_helper_fleq_d(dest, cpu_env, src1, src2); | ||
27 | gen_set_gpr(ctx, a->rd, dest); | ||
28 | return true; | ||
29 | } | ||
30 | @@ -XXX,XX +XXX,XX @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a) | ||
31 | TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); | ||
32 | TCGv_i64 src2 = get_fpr_hs(ctx, a->rs2); | ||
33 | |||
34 | - gen_helper_fltq_s(dest, cpu_env, src1, src2); | ||
35 | + gen_helper_fltq_d(dest, cpu_env, src1, src2); | ||
36 | gen_set_gpr(ctx, a->rd, dest); | ||
37 | return true; | ||
38 | } | ||
39 | -- | ||
40 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jason Chien <jason.chien@sifive.com> | ||
1 | 2 | ||
3 | When writing the upper mtime, we should keep the original lower mtime | ||
4 | whose value is given by cpu_riscv_read_rtc() instead of | ||
5 | cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime. | ||
6 | |||
7 | Signed-off-by: Jason Chien <jason.chien@sifive.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-ID: <20230728082502.26439-1-jason.chien@sifive.com> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | hw/intc/riscv_aclint.c | 5 +++-- | ||
13 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
14 | |||
15 | diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/intc/riscv_aclint.c | ||
18 | +++ b/hw/intc/riscv_aclint.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, | ||
20 | return; | ||
21 | } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) { | ||
22 | uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); | ||
23 | + uint64_t rtc = cpu_riscv_read_rtc(mtimer); | ||
24 | |||
25 | if (addr == mtimer->time_base) { | ||
26 | if (size == 4) { | ||
27 | /* time_lo for RV32/RV64 */ | ||
28 | - mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r; | ||
29 | + mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r; | ||
30 | } else { | ||
31 | /* time for RV64 */ | ||
32 | mtimer->time_delta = value - rtc_r; | ||
33 | @@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, | ||
34 | } else { | ||
35 | if (size == 4) { | ||
36 | /* time_hi for RV32/RV64 */ | ||
37 | - mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r; | ||
38 | + mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) - rtc_r; | ||
39 | } else { | ||
40 | qemu_log_mask(LOG_GUEST_ERROR, | ||
41 | "aclint-mtimer: invalid time_hi write: %08x", | ||
42 | -- | ||
43 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jason Chien <jason.chien@sifive.com> | ||
1 | 2 | ||
3 | The variables whose values are given by cpu_riscv_read_rtc() should be named | ||
4 | "rtc". The variables whose value are given by cpu_riscv_read_rtc_raw() | ||
5 | should be named "rtc_r". | ||
6 | |||
7 | Signed-off-by: Jason Chien <jason.chien@sifive.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-ID: <20230728082502.26439-2-jason.chien@sifive.com> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | --- | ||
12 | hw/intc/riscv_aclint.c | 6 +++--- | ||
13 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
14 | |||
15 | diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/intc/riscv_aclint.c | ||
18 | +++ b/hw/intc/riscv_aclint.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, | ||
20 | uint64_t next; | ||
21 | uint64_t diff; | ||
22 | |||
23 | - uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); | ||
24 | + uint64_t rtc = cpu_riscv_read_rtc(mtimer); | ||
25 | |||
26 | /* Compute the relative hartid w.r.t the socket */ | ||
27 | hartid = hartid - mtimer->hartid_base; | ||
28 | |||
29 | mtimer->timecmp[hartid] = value; | ||
30 | - if (mtimer->timecmp[hartid] <= rtc_r) { | ||
31 | + if (mtimer->timecmp[hartid] <= rtc) { | ||
32 | /* | ||
33 | * If we're setting an MTIMECMP value in the "past", | ||
34 | * immediately raise the timer interrupt | ||
35 | @@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, | ||
36 | |||
37 | /* otherwise, set up the future timer interrupt */ | ||
38 | qemu_irq_lower(mtimer->timer_irqs[hartid]); | ||
39 | - diff = mtimer->timecmp[hartid] - rtc_r; | ||
40 | + diff = mtimer->timecmp[hartid] - rtc; | ||
41 | /* back to ns (note args switched in muldiv64) */ | ||
42 | uint64_t ns_diff = muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); | ||
43 | |||
44 | -- | ||
45 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
---|---|---|---|
2 | 2 | ||
3 | Somehow HSS needs to access address 0 [1] for the DDR calibration data | 3 | We should not use types dependend on host arch for target_ucontext. |
4 | which is in the chipset's reserved memory. Let's map it. | 4 | This bug is found when run rv32 applications. |
5 | 5 | ||
6 | [1] See the config_copy() calls in various places in ddr_setup() in | 6 | Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
7 | the HSS source codes. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | |
9 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 10 | Message-ID: <20230811055438.1945-1-zhiwei_liu@linux.alibaba.com> |
11 | Message-id: 1603863010-15807-9-git-send-email-bmeng.cn@gmail.com | ||
12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
13 | --- | 12 | --- |
14 | include/hw/riscv/microchip_pfsoc.h | 1 + | 13 | linux-user/riscv/signal.c | 4 ++-- |
15 | hw/riscv/microchip_pfsoc.c | 11 ++++++++++- | 14 | 1 file changed, 2 insertions(+), 2 deletions(-) |
16 | 2 files changed, 11 insertions(+), 1 deletion(-) | ||
17 | 15 | ||
18 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | 16 | diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c |
19 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/riscv/microchip_pfsoc.h | 18 | --- a/linux-user/riscv/signal.c |
21 | +++ b/include/hw/riscv/microchip_pfsoc.h | 19 | +++ b/linux-user/riscv/signal.c |
22 | @@ -XXX,XX +XXX,XX @@ typedef struct MicrochipIcicleKitState { | 20 | @@ -XXX,XX +XXX,XX @@ struct target_sigcontext { |
23 | TYPE_MICROCHIP_ICICLE_KIT_MACHINE) | 21 | }; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */ |
24 | 22 | ||
25 | enum { | 23 | struct target_ucontext { |
26 | + MICROCHIP_PFSOC_RSVD0, | 24 | - unsigned long uc_flags; |
27 | MICROCHIP_PFSOC_DEBUG, | 25 | - struct target_ucontext *uc_link; |
28 | MICROCHIP_PFSOC_E51_DTIM, | 26 | + abi_ulong uc_flags; |
29 | MICROCHIP_PFSOC_BUSERR_UNIT0, | 27 | + abi_ptr uc_link; |
30 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | 28 | target_stack_t uc_stack; |
31 | index XXXXXXX..XXXXXXX 100644 | 29 | target_sigset_t uc_sigmask; |
32 | --- a/hw/riscv/microchip_pfsoc.c | 30 | uint8_t __unused[1024 / 8 - sizeof(target_sigset_t)]; |
33 | +++ b/hw/riscv/microchip_pfsoc.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
35 | hwaddr base; | ||
36 | hwaddr size; | ||
37 | } microchip_pfsoc_memmap[] = { | ||
38 | - [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 }, | ||
39 | + [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, | ||
40 | + [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, | ||
41 | [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, | ||
42 | [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, | ||
43 | [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, | ||
44 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
45 | MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); | ||
46 | const struct MemmapEntry *memmap = microchip_pfsoc_memmap; | ||
47 | MemoryRegion *system_memory = get_system_memory(); | ||
48 | + MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); | ||
49 | MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); | ||
50 | MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); | ||
51 | MemoryRegion *envm_data = g_new(MemoryRegion, 1); | ||
52 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
53 | qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); | ||
54 | qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); | ||
55 | |||
56 | + /* Reserved Memory at address 0 */ | ||
57 | + memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", | ||
58 | + memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); | ||
59 | + memory_region_add_subregion(system_memory, | ||
60 | + memmap[MICROCHIP_PFSOC_RSVD0].base, | ||
61 | + rsvd0_mem); | ||
62 | + | ||
63 | /* E51 DTIM */ | ||
64 | memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", | ||
65 | memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); | ||
66 | -- | 31 | -- |
67 | 2.28.0 | 32 | 2.41.0 |
68 | 33 | ||
69 | 34 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Yong-Xuan Wang <yongxuan.wang@sifive.com> |
---|---|---|---|
2 | 2 | ||
3 | Previously IOSCB_CFG was created as an unimplemented device. With | 3 | In this patch, we create the APLIC and IMSIC FDT helper functions and |
4 | the new IOSCB model, its memory range is already covered by the | 4 | remove M mode AIA devices when using KVM acceleration. |
5 | IOSCB hence remove the previous unimplemented device creation in | ||
6 | the SoC codes. | ||
7 | 5 | ||
8 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 6 | Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> |
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Reviewed-by: Jim Shu <jim.shu@sifive.com> |
10 | Message-id: 1603863010-15807-6-git-send-email-bmeng.cn@gmail.com | 8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
9 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
10 | Message-ID: <20230727102439.22554-2-yongxuan.wang@sifive.com> | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
12 | --- | 12 | --- |
13 | include/hw/riscv/microchip_pfsoc.h | 4 +++- | 13 | hw/riscv/virt.c | 290 +++++++++++++++++++++++------------------------- |
14 | hw/riscv/microchip_pfsoc.c | 13 ++++++++----- | 14 | 1 file changed, 137 insertions(+), 153 deletions(-) |
15 | hw/riscv/Kconfig | 1 + | ||
16 | 3 files changed, 12 insertions(+), 6 deletions(-) | ||
17 | 15 | ||
18 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | 16 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
19 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/riscv/microchip_pfsoc.h | 18 | --- a/hw/riscv/virt.c |
21 | +++ b/include/hw/riscv/microchip_pfsoc.h | 19 | +++ b/hw/riscv/virt.c |
22 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static uint32_t imsic_num_bits(uint32_t count) |
23 | #include "hw/char/mchp_pfsoc_mmuart.h" | 21 | return ret; |
24 | #include "hw/dma/sifive_pdma.h" | ||
25 | #include "hw/misc/mchp_pfsoc_dmc.h" | ||
26 | +#include "hw/misc/mchp_pfsoc_ioscb.h" | ||
27 | #include "hw/net/cadence_gem.h" | ||
28 | #include "hw/sd/cadence_sdhci.h" | ||
29 | |||
30 | @@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState { | ||
31 | DeviceState *plic; | ||
32 | MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; | ||
33 | MchpPfSoCDdrCfgState ddr_cfg; | ||
34 | + MchpPfSoCIoscbState ioscb; | ||
35 | MchpPfSoCMMUartState *serial0; | ||
36 | MchpPfSoCMMUartState *serial1; | ||
37 | MchpPfSoCMMUartState *serial2; | ||
38 | @@ -XXX,XX +XXX,XX @@ enum { | ||
39 | MICROCHIP_PFSOC_GPIO2, | ||
40 | MICROCHIP_PFSOC_ENVM_CFG, | ||
41 | MICROCHIP_PFSOC_ENVM_DATA, | ||
42 | - MICROCHIP_PFSOC_IOSCB_CFG, | ||
43 | + MICROCHIP_PFSOC_IOSCB, | ||
44 | MICROCHIP_PFSOC_DRAM, | ||
45 | }; | ||
46 | |||
47 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/riscv/microchip_pfsoc.c | ||
50 | +++ b/hw/riscv/microchip_pfsoc.c | ||
51 | @@ -XXX,XX +XXX,XX @@ | ||
52 | * 5) SiFive Platform DMA (Direct Memory Access Controller) | ||
53 | * 6) GEM (Gigabit Ethernet MAC Controller) | ||
54 | * 7) DMC (DDR Memory Controller) | ||
55 | + * 8) IOSCB modules | ||
56 | * | ||
57 | * This board currently generates devicetree dynamically that indicates at least | ||
58 | * two harts and up to five harts. | ||
59 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
60 | [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, | ||
61 | [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, | ||
62 | [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, | ||
63 | - [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, | ||
64 | + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, | ||
65 | [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, | ||
66 | }; | ||
67 | |||
68 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj) | ||
69 | |||
70 | object_initialize_child(obj, "sd-controller", &s->sdhci, | ||
71 | TYPE_CADENCE_SDHCI); | ||
72 | + | ||
73 | + object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); | ||
74 | } | 22 | } |
75 | 23 | ||
76 | static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | 24 | -static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, |
77 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | 25 | - uint32_t *phandle, uint32_t *intc_phandles, |
78 | memmap[MICROCHIP_PFSOC_ENVM_DATA].base, | 26 | - uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) |
79 | envm_data); | 27 | +static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, |
80 | 28 | + uint32_t *intc_phandles, uint32_t msi_phandle, | |
81 | - /* IOSCBCFG */ | 29 | + bool m_mode, uint32_t imsic_guest_bits) |
82 | - create_unimplemented_device("microchip.pfsoc.ioscb.cfg", | 30 | { |
83 | - memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, | 31 | int cpu, socket; |
84 | - memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); | 32 | char *imsic_name; |
85 | + /* IOSCB */ | 33 | MachineState *ms = MACHINE(s); |
86 | + sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); | 34 | int socket_count = riscv_socket_count(ms); |
87 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, | 35 | - uint32_t imsic_max_hart_per_socket, imsic_guest_bits; |
88 | + memmap[MICROCHIP_PFSOC_IOSCB].base); | 36 | + uint32_t imsic_max_hart_per_socket; |
37 | uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; | ||
38 | |||
39 | - *msi_m_phandle = (*phandle)++; | ||
40 | - *msi_s_phandle = (*phandle)++; | ||
41 | imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); | ||
42 | imsic_regs = g_new0(uint32_t, socket_count * 4); | ||
43 | |||
44 | - /* M-level IMSIC node */ | ||
45 | for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | ||
46 | imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | ||
47 | - imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); | ||
48 | + imsic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); | ||
49 | } | ||
50 | - imsic_max_hart_per_socket = 0; | ||
51 | - for (socket = 0; socket < socket_count; socket++) { | ||
52 | - imsic_addr = memmap[VIRT_IMSIC_M].base + | ||
53 | - socket * VIRT_IMSIC_GROUP_MAX_SIZE; | ||
54 | - imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; | ||
55 | - imsic_regs[socket * 4 + 0] = 0; | ||
56 | - imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); | ||
57 | - imsic_regs[socket * 4 + 2] = 0; | ||
58 | - imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); | ||
59 | - if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { | ||
60 | - imsic_max_hart_per_socket = s->soc[socket].num_harts; | ||
61 | - } | ||
62 | - } | ||
63 | - imsic_name = g_strdup_printf("/soc/imsics@%lx", | ||
64 | - (unsigned long)memmap[VIRT_IMSIC_M].base); | ||
65 | - qemu_fdt_add_subnode(ms->fdt, imsic_name); | ||
66 | - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", | ||
67 | - "riscv,imsics"); | ||
68 | - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", | ||
69 | - FDT_IMSIC_INT_CELLS); | ||
70 | - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", | ||
71 | - NULL, 0); | ||
72 | - qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", | ||
73 | - NULL, 0); | ||
74 | - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", | ||
75 | - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); | ||
76 | - qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, | ||
77 | - socket_count * sizeof(uint32_t) * 4); | ||
78 | - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", | ||
79 | - VIRT_IRQCHIP_NUM_MSIS); | ||
80 | - if (socket_count > 1) { | ||
81 | - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", | ||
82 | - imsic_num_bits(imsic_max_hart_per_socket)); | ||
83 | - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", | ||
84 | - imsic_num_bits(socket_count)); | ||
85 | - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", | ||
86 | - IMSIC_MMIO_GROUP_MIN_SHIFT); | ||
87 | - } | ||
88 | - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); | ||
89 | - | ||
90 | - g_free(imsic_name); | ||
91 | |||
92 | - /* S-level IMSIC node */ | ||
93 | - for (cpu = 0; cpu < ms->smp.cpus; cpu++) { | ||
94 | - imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | ||
95 | - imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); | ||
96 | - } | ||
97 | - imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); | ||
98 | imsic_max_hart_per_socket = 0; | ||
99 | for (socket = 0; socket < socket_count; socket++) { | ||
100 | - imsic_addr = memmap[VIRT_IMSIC_S].base + | ||
101 | - socket * VIRT_IMSIC_GROUP_MAX_SIZE; | ||
102 | + imsic_addr = base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; | ||
103 | imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * | ||
104 | s->soc[socket].num_harts; | ||
105 | imsic_regs[socket * 4 + 0] = 0; | ||
106 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, | ||
107 | imsic_max_hart_per_socket = s->soc[socket].num_harts; | ||
108 | } | ||
109 | } | ||
110 | - imsic_name = g_strdup_printf("/soc/imsics@%lx", | ||
111 | - (unsigned long)memmap[VIRT_IMSIC_S].base); | ||
112 | + | ||
113 | + imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_addr); | ||
114 | qemu_fdt_add_subnode(ms->fdt, imsic_name); | ||
115 | - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", | ||
116 | - "riscv,imsics"); | ||
117 | + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); | ||
118 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", | ||
119 | - FDT_IMSIC_INT_CELLS); | ||
120 | - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", | ||
121 | - NULL, 0); | ||
122 | - qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", | ||
123 | - NULL, 0); | ||
124 | + FDT_IMSIC_INT_CELLS); | ||
125 | + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); | ||
126 | + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); | ||
127 | qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", | ||
128 | - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); | ||
129 | + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); | ||
130 | qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, | ||
131 | - socket_count * sizeof(uint32_t) * 4); | ||
132 | + socket_count * sizeof(uint32_t) * 4); | ||
133 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", | ||
134 | - VIRT_IRQCHIP_NUM_MSIS); | ||
135 | + VIRT_IRQCHIP_NUM_MSIS); | ||
136 | + | ||
137 | if (imsic_guest_bits) { | ||
138 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", | ||
139 | - imsic_guest_bits); | ||
140 | + imsic_guest_bits); | ||
141 | } | ||
142 | + | ||
143 | if (socket_count > 1) { | ||
144 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", | ||
145 | - imsic_num_bits(imsic_max_hart_per_socket)); | ||
146 | + imsic_num_bits(imsic_max_hart_per_socket)); | ||
147 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", | ||
148 | - imsic_num_bits(socket_count)); | ||
149 | + imsic_num_bits(socket_count)); | ||
150 | qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", | ||
151 | - IMSIC_MMIO_GROUP_MIN_SHIFT); | ||
152 | + IMSIC_MMIO_GROUP_MIN_SHIFT); | ||
153 | } | ||
154 | - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); | ||
155 | - g_free(imsic_name); | ||
156 | + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); | ||
157 | |||
158 | + g_free(imsic_name); | ||
159 | g_free(imsic_regs); | ||
160 | g_free(imsic_cells); | ||
89 | } | 161 | } |
90 | 162 | ||
91 | static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) | 163 | -static void create_fdt_socket_aplic(RISCVVirtState *s, |
92 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig | 164 | - const MemMapEntry *memmap, int socket, |
93 | index XXXXXXX..XXXXXXX 100644 | 165 | - uint32_t msi_m_phandle, |
94 | --- a/hw/riscv/Kconfig | 166 | - uint32_t msi_s_phandle, |
95 | +++ b/hw/riscv/Kconfig | 167 | - uint32_t *phandle, |
96 | @@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC | 168 | - uint32_t *intc_phandles, |
97 | bool | 169 | - uint32_t *aplic_phandles) |
98 | select CADENCE_SDHCI | 170 | +static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, |
99 | select MCHP_PFSOC_DMC | 171 | + uint32_t *phandle, uint32_t *intc_phandles, |
100 | + select MCHP_PFSOC_IOSCB | 172 | + uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) |
101 | select MCHP_PFSOC_MMUART | 173 | +{ |
102 | select MSI_NONBROKEN | 174 | + *msi_m_phandle = (*phandle)++; |
103 | select SIFIVE_CLINT | 175 | + *msi_s_phandle = (*phandle)++; |
176 | + | ||
177 | + if (!kvm_enabled()) { | ||
178 | + /* M-level IMSIC node */ | ||
179 | + create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, | ||
180 | + *msi_m_phandle, true, 0); | ||
181 | + } | ||
182 | + | ||
183 | + /* S-level IMSIC node */ | ||
184 | + create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, | ||
185 | + *msi_s_phandle, false, | ||
186 | + imsic_num_bits(s->aia_guests + 1)); | ||
187 | + | ||
188 | +} | ||
189 | + | ||
190 | +static void create_fdt_one_aplic(RISCVVirtState *s, int socket, | ||
191 | + unsigned long aplic_addr, uint32_t aplic_size, | ||
192 | + uint32_t msi_phandle, | ||
193 | + uint32_t *intc_phandles, | ||
194 | + uint32_t aplic_phandle, | ||
195 | + uint32_t aplic_child_phandle, | ||
196 | + bool m_mode) | ||
197 | { | ||
198 | int cpu; | ||
199 | char *aplic_name; | ||
200 | uint32_t *aplic_cells; | ||
201 | - unsigned long aplic_addr; | ||
202 | MachineState *ms = MACHINE(s); | ||
203 | - uint32_t aplic_m_phandle, aplic_s_phandle; | ||
204 | |||
205 | - aplic_m_phandle = (*phandle)++; | ||
206 | - aplic_s_phandle = (*phandle)++; | ||
207 | aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); | ||
208 | |||
209 | - /* M-level APLIC node */ | ||
210 | for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { | ||
211 | aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | ||
212 | - aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); | ||
213 | + aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); | ||
214 | } | ||
215 | - aplic_addr = memmap[VIRT_APLIC_M].base + | ||
216 | - (memmap[VIRT_APLIC_M].size * socket); | ||
217 | + | ||
218 | aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); | ||
219 | qemu_fdt_add_subnode(ms->fdt, aplic_name); | ||
220 | qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); | ||
221 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, | ||
222 | - "#interrupt-cells", FDT_APLIC_INT_CELLS); | ||
223 | + "#interrupt-cells", FDT_APLIC_INT_CELLS); | ||
224 | qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); | ||
225 | + | ||
226 | if (s->aia_type == VIRT_AIA_TYPE_APLIC) { | ||
227 | qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", | ||
228 | - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); | ||
229 | + aplic_cells, | ||
230 | + s->soc[socket].num_harts * sizeof(uint32_t) * 2); | ||
231 | } else { | ||
232 | - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", | ||
233 | - msi_m_phandle); | ||
234 | + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); | ||
235 | } | ||
236 | + | ||
237 | qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", | ||
238 | - 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); | ||
239 | + 0x0, aplic_addr, 0x0, aplic_size); | ||
240 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", | ||
241 | - VIRT_IRQCHIP_NUM_SOURCES); | ||
242 | - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", | ||
243 | - aplic_s_phandle); | ||
244 | - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", | ||
245 | - aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); | ||
246 | + VIRT_IRQCHIP_NUM_SOURCES); | ||
247 | + | ||
248 | + if (aplic_child_phandle) { | ||
249 | + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", | ||
250 | + aplic_child_phandle); | ||
251 | + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", | ||
252 | + aplic_child_phandle, 0x1, | ||
253 | + VIRT_IRQCHIP_NUM_SOURCES); | ||
254 | + } | ||
255 | + | ||
256 | riscv_socket_fdt_write_id(ms, aplic_name, socket); | ||
257 | - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); | ||
258 | + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); | ||
259 | + | ||
260 | g_free(aplic_name); | ||
261 | + g_free(aplic_cells); | ||
262 | +} | ||
263 | |||
264 | - /* S-level APLIC node */ | ||
265 | - for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { | ||
266 | - aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | ||
267 | - aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); | ||
268 | +static void create_fdt_socket_aplic(RISCVVirtState *s, | ||
269 | + const MemMapEntry *memmap, int socket, | ||
270 | + uint32_t msi_m_phandle, | ||
271 | + uint32_t msi_s_phandle, | ||
272 | + uint32_t *phandle, | ||
273 | + uint32_t *intc_phandles, | ||
274 | + uint32_t *aplic_phandles) | ||
275 | +{ | ||
276 | + char *aplic_name; | ||
277 | + unsigned long aplic_addr; | ||
278 | + MachineState *ms = MACHINE(s); | ||
279 | + uint32_t aplic_m_phandle, aplic_s_phandle; | ||
280 | + | ||
281 | + aplic_m_phandle = (*phandle)++; | ||
282 | + aplic_s_phandle = (*phandle)++; | ||
283 | + | ||
284 | + if (!kvm_enabled()) { | ||
285 | + /* M-level APLIC node */ | ||
286 | + aplic_addr = memmap[VIRT_APLIC_M].base + | ||
287 | + (memmap[VIRT_APLIC_M].size * socket); | ||
288 | + create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, | ||
289 | + msi_m_phandle, intc_phandles, | ||
290 | + aplic_m_phandle, aplic_s_phandle, | ||
291 | + true); | ||
292 | } | ||
293 | + | ||
294 | + /* S-level APLIC node */ | ||
295 | aplic_addr = memmap[VIRT_APLIC_S].base + | ||
296 | (memmap[VIRT_APLIC_S].size * socket); | ||
297 | + create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, | ||
298 | + msi_s_phandle, intc_phandles, | ||
299 | + aplic_s_phandle, 0, | ||
300 | + false); | ||
301 | + | ||
302 | aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); | ||
303 | - qemu_fdt_add_subnode(ms->fdt, aplic_name); | ||
304 | - qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); | ||
305 | - qemu_fdt_setprop_cell(ms->fdt, aplic_name, | ||
306 | - "#interrupt-cells", FDT_APLIC_INT_CELLS); | ||
307 | - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); | ||
308 | - if (s->aia_type == VIRT_AIA_TYPE_APLIC) { | ||
309 | - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", | ||
310 | - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); | ||
311 | - } else { | ||
312 | - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", | ||
313 | - msi_s_phandle); | ||
314 | - } | ||
315 | - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", | ||
316 | - 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); | ||
317 | - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", | ||
318 | - VIRT_IRQCHIP_NUM_SOURCES); | ||
319 | - riscv_socket_fdt_write_id(ms, aplic_name, socket); | ||
320 | - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); | ||
321 | |||
322 | if (!socket) { | ||
323 | platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, | ||
324 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s, | ||
325 | |||
326 | g_free(aplic_name); | ||
327 | |||
328 | - g_free(aplic_cells); | ||
329 | aplic_phandles[socket] = aplic_s_phandle; | ||
330 | } | ||
331 | |||
332 | @@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, | ||
333 | int i; | ||
334 | hwaddr addr; | ||
335 | uint32_t guest_bits; | ||
336 | - DeviceState *aplic_m; | ||
337 | - bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; | ||
338 | + DeviceState *aplic_s = NULL; | ||
339 | + DeviceState *aplic_m = NULL; | ||
340 | + bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; | ||
341 | |||
342 | if (msimode) { | ||
343 | - /* Per-socket M-level IMSICs */ | ||
344 | - addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; | ||
345 | - for (i = 0; i < hart_count; i++) { | ||
346 | - riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), | ||
347 | - base_hartid + i, true, 1, | ||
348 | - VIRT_IRQCHIP_NUM_MSIS); | ||
349 | + if (!kvm_enabled()) { | ||
350 | + /* Per-socket M-level IMSICs */ | ||
351 | + addr = memmap[VIRT_IMSIC_M].base + | ||
352 | + socket * VIRT_IMSIC_GROUP_MAX_SIZE; | ||
353 | + for (i = 0; i < hart_count; i++) { | ||
354 | + riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), | ||
355 | + base_hartid + i, true, 1, | ||
356 | + VIRT_IRQCHIP_NUM_MSIS); | ||
357 | + } | ||
358 | } | ||
359 | |||
360 | /* Per-socket S-level IMSICs */ | ||
361 | @@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, | ||
362 | } | ||
363 | } | ||
364 | |||
365 | - /* Per-socket M-level APLIC */ | ||
366 | - aplic_m = riscv_aplic_create( | ||
367 | - memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, | ||
368 | - memmap[VIRT_APLIC_M].size, | ||
369 | - (msimode) ? 0 : base_hartid, | ||
370 | - (msimode) ? 0 : hart_count, | ||
371 | - VIRT_IRQCHIP_NUM_SOURCES, | ||
372 | - VIRT_IRQCHIP_NUM_PRIO_BITS, | ||
373 | - msimode, true, NULL); | ||
374 | - | ||
375 | - if (aplic_m) { | ||
376 | - /* Per-socket S-level APLIC */ | ||
377 | - riscv_aplic_create( | ||
378 | - memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, | ||
379 | - memmap[VIRT_APLIC_S].size, | ||
380 | - (msimode) ? 0 : base_hartid, | ||
381 | - (msimode) ? 0 : hart_count, | ||
382 | - VIRT_IRQCHIP_NUM_SOURCES, | ||
383 | - VIRT_IRQCHIP_NUM_PRIO_BITS, | ||
384 | - msimode, false, aplic_m); | ||
385 | + if (!kvm_enabled()) { | ||
386 | + /* Per-socket M-level APLIC */ | ||
387 | + aplic_m = riscv_aplic_create(memmap[VIRT_APLIC_M].base + | ||
388 | + socket * memmap[VIRT_APLIC_M].size, | ||
389 | + memmap[VIRT_APLIC_M].size, | ||
390 | + (msimode) ? 0 : base_hartid, | ||
391 | + (msimode) ? 0 : hart_count, | ||
392 | + VIRT_IRQCHIP_NUM_SOURCES, | ||
393 | + VIRT_IRQCHIP_NUM_PRIO_BITS, | ||
394 | + msimode, true, NULL); | ||
395 | } | ||
396 | |||
397 | - return aplic_m; | ||
398 | + /* Per-socket S-level APLIC */ | ||
399 | + aplic_s = riscv_aplic_create(memmap[VIRT_APLIC_S].base + | ||
400 | + socket * memmap[VIRT_APLIC_S].size, | ||
401 | + memmap[VIRT_APLIC_S].size, | ||
402 | + (msimode) ? 0 : base_hartid, | ||
403 | + (msimode) ? 0 : hart_count, | ||
404 | + VIRT_IRQCHIP_NUM_SOURCES, | ||
405 | + VIRT_IRQCHIP_NUM_PRIO_BITS, | ||
406 | + msimode, false, aplic_m); | ||
407 | + | ||
408 | + return kvm_enabled() ? aplic_s : aplic_m; | ||
409 | } | ||
410 | |||
411 | static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) | ||
104 | -- | 412 | -- |
105 | 2.28.0 | 413 | 2.41.0 |
106 | |||
107 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Yong-Xuan Wang <yongxuan.wang@sifive.com> |
---|---|---|---|
2 | 2 | ||
3 | When system memory is larger than 1 GiB (high memory), PolarFire SoC | 3 | We check the in-kernel irqchip support when using KVM acceleration. |
4 | maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is | ||
5 | aliased to the same 1 GiB low memory with different cache attributes. | ||
6 | 4 | ||
7 | At present QEMU maps the system memory contiguously from 0x8000_0000. | 5 | Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> |
8 | This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is | 6 | Reviewed-by: Jim Shu <jim.shu@sifive.com> |
9 | the alias to the high memory, and even physical memory is only 1 GiB, | 7 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
10 | the HSS codes still tries to probe the high memory alias address. | 8 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> |
11 | It seems there is no issue on the real hardware, so we will have to | 9 | Message-ID: <20230727102439.22554-3-yongxuan.wang@sifive.com> |
12 | take that into the consideration in our emulation. Due to this, we | ||
13 | we increase the default system memory size to 1537 MiB (the minimum | ||
14 | required high memory size by HSS) so that user gets notified an error | ||
15 | when less than 1537 MiB is specified. | ||
16 | |||
17 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | ||
18 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
19 | Message-id: 20201101170538.3732-1-bmeng.cn@gmail.com | ||
20 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
21 | --- | 11 | --- |
22 | include/hw/riscv/microchip_pfsoc.h | 5 ++- | 12 | target/riscv/kvm.c | 10 +++++++++- |
23 | hw/riscv/microchip_pfsoc.c | 50 ++++++++++++++++++++++++++---- | 13 | 1 file changed, 9 insertions(+), 1 deletion(-) |
24 | 2 files changed, 48 insertions(+), 7 deletions(-) | ||
25 | 14 | ||
26 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | 15 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c |
27 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/include/hw/riscv/microchip_pfsoc.h | 17 | --- a/target/riscv/kvm.c |
29 | +++ b/include/hw/riscv/microchip_pfsoc.h | 18 | +++ b/target/riscv/kvm.c |
30 | @@ -XXX,XX +XXX,XX @@ enum { | 19 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s) |
31 | MICROCHIP_PFSOC_ENVM_CFG, | 20 | |
32 | MICROCHIP_PFSOC_ENVM_DATA, | 21 | int kvm_arch_irqchip_create(KVMState *s) |
33 | MICROCHIP_PFSOC_IOSCB, | 22 | { |
34 | - MICROCHIP_PFSOC_DRAM, | 23 | - return 0; |
35 | + MICROCHIP_PFSOC_DRAM_LO, | 24 | + if (kvm_kernel_irqchip_split()) { |
36 | + MICROCHIP_PFSOC_DRAM_LO_ALIAS, | 25 | + error_report("-machine kernel_irqchip=split is not supported on RISC-V."); |
37 | + MICROCHIP_PFSOC_DRAM_HI, | 26 | + exit(1); |
38 | + MICROCHIP_PFSOC_DRAM_HI_ALIAS | 27 | + } |
39 | }; | ||
40 | |||
41 | enum { | ||
42 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/hw/riscv/microchip_pfsoc.c | ||
45 | +++ b/hw/riscv/microchip_pfsoc.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry { | ||
47 | [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, | ||
48 | [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, | ||
49 | [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, | ||
50 | - [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, | ||
51 | + [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, | ||
52 | + [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, | ||
53 | + [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, | ||
54 | + [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, | ||
55 | }; | ||
56 | |||
57 | static void microchip_pfsoc_soc_instance_init(Object *obj) | ||
58 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine) | ||
59 | const struct MemmapEntry *memmap = microchip_pfsoc_memmap; | ||
60 | MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); | ||
61 | MemoryRegion *system_memory = get_system_memory(); | ||
62 | - MemoryRegion *main_mem = g_new(MemoryRegion, 1); | ||
63 | + MemoryRegion *mem_low = g_new(MemoryRegion, 1); | ||
64 | + MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); | ||
65 | + MemoryRegion *mem_high = g_new(MemoryRegion, 1); | ||
66 | + MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); | ||
67 | + uint64_t mem_high_size; | ||
68 | DriveInfo *dinfo = drive_get_next(IF_SD); | ||
69 | |||
70 | /* Sanity check on RAM size */ | ||
71 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine) | ||
72 | qdev_realize(DEVICE(&s->soc), NULL, &error_abort); | ||
73 | |||
74 | /* Register RAM */ | ||
75 | - memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram", | ||
76 | - machine->ram_size, &error_fatal); | ||
77 | + memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low", | ||
78 | + memmap[MICROCHIP_PFSOC_DRAM_LO].size, | ||
79 | + &error_fatal); | ||
80 | + memory_region_init_alias(mem_low_alias, NULL, | ||
81 | + "microchip.icicle.kit.ram_low.alias", | ||
82 | + mem_low, 0, | ||
83 | + memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size); | ||
84 | + memory_region_add_subregion(system_memory, | ||
85 | + memmap[MICROCHIP_PFSOC_DRAM_LO].base, | ||
86 | + mem_low); | ||
87 | memory_region_add_subregion(system_memory, | ||
88 | - memmap[MICROCHIP_PFSOC_DRAM].base, main_mem); | ||
89 | + memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, | ||
90 | + mem_low_alias); | ||
91 | + | ||
92 | + mem_high_size = machine->ram_size - 1 * GiB; | ||
93 | + | ||
94 | + memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high", | ||
95 | + mem_high_size, &error_fatal); | ||
96 | + memory_region_init_alias(mem_high_alias, NULL, | ||
97 | + "microchip.icicle.kit.ram_high.alias", | ||
98 | + mem_high, 0, mem_high_size); | ||
99 | + memory_region_add_subregion(system_memory, | ||
100 | + memmap[MICROCHIP_PFSOC_DRAM_HI].base, | ||
101 | + mem_high); | ||
102 | + memory_region_add_subregion(system_memory, | ||
103 | + memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, | ||
104 | + mem_high_alias); | ||
105 | |||
106 | /* Load the firmware */ | ||
107 | riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); | ||
108 | @@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) | ||
109 | MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; | ||
110 | mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; | ||
111 | mc->default_cpus = mc->min_cpus; | ||
112 | - mc->default_ram_size = 1 * GiB; | ||
113 | + | 28 | + |
114 | + /* | 29 | + /* |
115 | + * Map 513 MiB high memory, the mimimum required high memory size, because | 30 | + * We can create the VAIA using the newer device control API. |
116 | + * HSS will do memory test against the high memory address range regardless | ||
117 | + * of physical memory installed. | ||
118 | + * | ||
119 | + * See memory_tests() in mss_ddr.c in the HSS source code. | ||
120 | + */ | 31 | + */ |
121 | + mc->default_ram_size = 1537 * MiB; | 32 | + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); |
122 | } | 33 | } |
123 | 34 | ||
124 | static const TypeInfo microchip_icicle_kit_machine_typeinfo = { | 35 | int kvm_arch_process_async_events(CPUState *cs) |
125 | -- | 36 | -- |
126 | 2.28.0 | 37 | 2.41.0 |
127 | |||
128 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Yong-Xuan Wang <yongxuan.wang@sifive.com> | ||
1 | 2 | ||
3 | We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up | ||
4 | the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. | ||
5 | We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia" | ||
6 | parameter is passed along with --accel in QEMU command-line. | ||
7 | 1) "riscv-aia=emul": IMSIC is emulated by hypervisor | ||
8 | 2) "riscv-aia=hwaccel": use hardware guest IMSIC | ||
9 | 3) "riscv-aia=auto": use the hardware guest IMSICs whenever available | ||
10 | otherwise we fallback to software emulation. | ||
11 | |||
12 | Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> | ||
13 | Reviewed-by: Jim Shu <jim.shu@sifive.com> | ||
14 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
15 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
16 | Message-ID: <20230727102439.22554-4-yongxuan.wang@sifive.com> | ||
17 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
18 | --- | ||
19 | target/riscv/kvm_riscv.h | 4 + | ||
20 | target/riscv/kvm.c | 186 +++++++++++++++++++++++++++++++++++++++ | ||
21 | 2 files changed, 190 insertions(+) | ||
22 | |||
23 | diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/riscv/kvm_riscv.h | ||
26 | +++ b/target/riscv/kvm_riscv.h | ||
27 | @@ -XXX,XX +XXX,XX @@ | ||
28 | void kvm_riscv_init_user_properties(Object *cpu_obj); | ||
29 | void kvm_riscv_reset_vcpu(RISCVCPU *cpu); | ||
30 | void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); | ||
31 | +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, | ||
32 | + uint64_t aia_irq_num, uint64_t aia_msi_num, | ||
33 | + uint64_t aplic_base, uint64_t imsic_base, | ||
34 | + uint64_t guest_num); | ||
35 | |||
36 | #endif | ||
37 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/riscv/kvm.c | ||
40 | +++ b/target/riscv/kvm.c | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | #include "exec/address-spaces.h" | ||
43 | #include "hw/boards.h" | ||
44 | #include "hw/irq.h" | ||
45 | +#include "hw/intc/riscv_imsic.h" | ||
46 | #include "qemu/log.h" | ||
47 | #include "hw/loader.h" | ||
48 | #include "kvm_riscv.h" | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | #include "chardev/char-fe.h" | ||
51 | #include "migration/migration.h" | ||
52 | #include "sysemu/runstate.h" | ||
53 | +#include "hw/riscv/numa.h" | ||
54 | |||
55 | static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, | ||
56 | uint64_t idx) | ||
57 | @@ -XXX,XX +XXX,XX @@ bool kvm_arch_cpu_check_are_resettable(void) | ||
58 | return true; | ||
59 | } | ||
60 | |||
61 | +static int aia_mode; | ||
62 | + | ||
63 | +static const char *kvm_aia_mode_str(uint64_t mode) | ||
64 | +{ | ||
65 | + switch (mode) { | ||
66 | + case KVM_DEV_RISCV_AIA_MODE_EMUL: | ||
67 | + return "emul"; | ||
68 | + case KVM_DEV_RISCV_AIA_MODE_HWACCEL: | ||
69 | + return "hwaccel"; | ||
70 | + case KVM_DEV_RISCV_AIA_MODE_AUTO: | ||
71 | + default: | ||
72 | + return "auto"; | ||
73 | + }; | ||
74 | +} | ||
75 | + | ||
76 | +static char *riscv_get_kvm_aia(Object *obj, Error **errp) | ||
77 | +{ | ||
78 | + return g_strdup(kvm_aia_mode_str(aia_mode)); | ||
79 | +} | ||
80 | + | ||
81 | +static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) | ||
82 | +{ | ||
83 | + if (!strcmp(val, "emul")) { | ||
84 | + aia_mode = KVM_DEV_RISCV_AIA_MODE_EMUL; | ||
85 | + } else if (!strcmp(val, "hwaccel")) { | ||
86 | + aia_mode = KVM_DEV_RISCV_AIA_MODE_HWACCEL; | ||
87 | + } else if (!strcmp(val, "auto")) { | ||
88 | + aia_mode = KVM_DEV_RISCV_AIA_MODE_AUTO; | ||
89 | + } else { | ||
90 | + error_setg(errp, "Invalid KVM AIA mode"); | ||
91 | + error_append_hint(errp, "Valid values are emul, hwaccel, and auto.\n"); | ||
92 | + } | ||
93 | +} | ||
94 | + | ||
95 | void kvm_arch_accel_class_init(ObjectClass *oc) | ||
96 | { | ||
97 | + object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, | ||
98 | + riscv_set_kvm_aia); | ||
99 | + object_class_property_set_description(oc, "riscv-aia", | ||
100 | + "Set KVM AIA mode. Valid values are " | ||
101 | + "emul, hwaccel, and auto. Default " | ||
102 | + "is auto."); | ||
103 | + object_property_set_default_str(object_class_property_find(oc, "riscv-aia"), | ||
104 | + "auto"); | ||
105 | +} | ||
106 | + | ||
107 | +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, | ||
108 | + uint64_t aia_irq_num, uint64_t aia_msi_num, | ||
109 | + uint64_t aplic_base, uint64_t imsic_base, | ||
110 | + uint64_t guest_num) | ||
111 | +{ | ||
112 | + int ret, i; | ||
113 | + int aia_fd = -1; | ||
114 | + uint64_t default_aia_mode; | ||
115 | + uint64_t socket_count = riscv_socket_count(machine); | ||
116 | + uint64_t max_hart_per_socket = 0; | ||
117 | + uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; | ||
118 | + uint64_t socket_bits, hart_bits, guest_bits; | ||
119 | + | ||
120 | + aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); | ||
121 | + | ||
122 | + if (aia_fd < 0) { | ||
123 | + error_report("Unable to create in-kernel irqchip"); | ||
124 | + exit(1); | ||
125 | + } | ||
126 | + | ||
127 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, | ||
128 | + KVM_DEV_RISCV_AIA_CONFIG_MODE, | ||
129 | + &default_aia_mode, false, NULL); | ||
130 | + if (ret < 0) { | ||
131 | + error_report("KVM AIA: failed to get current KVM AIA mode"); | ||
132 | + exit(1); | ||
133 | + } | ||
134 | + qemu_log("KVM AIA: default mode is %s\n", | ||
135 | + kvm_aia_mode_str(default_aia_mode)); | ||
136 | + | ||
137 | + if (default_aia_mode != aia_mode) { | ||
138 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, | ||
139 | + KVM_DEV_RISCV_AIA_CONFIG_MODE, | ||
140 | + &aia_mode, true, NULL); | ||
141 | + if (ret < 0) | ||
142 | + warn_report("KVM AIA: failed to set KVM AIA mode"); | ||
143 | + else | ||
144 | + qemu_log("KVM AIA: set current mode to %s\n", | ||
145 | + kvm_aia_mode_str(aia_mode)); | ||
146 | + } | ||
147 | + | ||
148 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, | ||
149 | + KVM_DEV_RISCV_AIA_CONFIG_SRCS, | ||
150 | + &aia_irq_num, true, NULL); | ||
151 | + if (ret < 0) { | ||
152 | + error_report("KVM AIA: failed to set number of input irq lines"); | ||
153 | + exit(1); | ||
154 | + } | ||
155 | + | ||
156 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, | ||
157 | + KVM_DEV_RISCV_AIA_CONFIG_IDS, | ||
158 | + &aia_msi_num, true, NULL); | ||
159 | + if (ret < 0) { | ||
160 | + error_report("KVM AIA: failed to set number of msi"); | ||
161 | + exit(1); | ||
162 | + } | ||
163 | + | ||
164 | + socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1; | ||
165 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, | ||
166 | + KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, | ||
167 | + &socket_bits, true, NULL); | ||
168 | + if (ret < 0) { | ||
169 | + error_report("KVM AIA: failed to set group_bits"); | ||
170 | + exit(1); | ||
171 | + } | ||
172 | + | ||
173 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, | ||
174 | + KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, | ||
175 | + &group_shift, true, NULL); | ||
176 | + if (ret < 0) { | ||
177 | + error_report("KVM AIA: failed to set group_shift"); | ||
178 | + exit(1); | ||
179 | + } | ||
180 | + | ||
181 | + guest_bits = guest_num == 0 ? 0 : | ||
182 | + find_last_bit(&guest_num, BITS_PER_LONG) + 1; | ||
183 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, | ||
184 | + KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, | ||
185 | + &guest_bits, true, NULL); | ||
186 | + if (ret < 0) { | ||
187 | + error_report("KVM AIA: failed to set guest_bits"); | ||
188 | + exit(1); | ||
189 | + } | ||
190 | + | ||
191 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, | ||
192 | + KVM_DEV_RISCV_AIA_ADDR_APLIC, | ||
193 | + &aplic_base, true, NULL); | ||
194 | + if (ret < 0) { | ||
195 | + error_report("KVM AIA: failed to set the base address of APLIC"); | ||
196 | + exit(1); | ||
197 | + } | ||
198 | + | ||
199 | + for (socket = 0; socket < socket_count; socket++) { | ||
200 | + socket_imsic_base = imsic_base + socket * (1U << group_shift); | ||
201 | + hart_count = riscv_socket_hart_count(machine, socket); | ||
202 | + base_hart = riscv_socket_first_hartid(machine, socket); | ||
203 | + | ||
204 | + if (max_hart_per_socket < hart_count) { | ||
205 | + max_hart_per_socket = hart_count; | ||
206 | + } | ||
207 | + | ||
208 | + for (i = 0; i < hart_count; i++) { | ||
209 | + imsic_addr = socket_imsic_base + i * IMSIC_HART_SIZE(guest_bits); | ||
210 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, | ||
211 | + KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_hart), | ||
212 | + &imsic_addr, true, NULL); | ||
213 | + if (ret < 0) { | ||
214 | + error_report("KVM AIA: failed to set the IMSIC address for hart %d", i); | ||
215 | + exit(1); | ||
216 | + } | ||
217 | + } | ||
218 | + } | ||
219 | + | ||
220 | + hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; | ||
221 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, | ||
222 | + KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, | ||
223 | + &hart_bits, true, NULL); | ||
224 | + if (ret < 0) { | ||
225 | + error_report("KVM AIA: failed to set hart_bits"); | ||
226 | + exit(1); | ||
227 | + } | ||
228 | + | ||
229 | + if (kvm_has_gsi_routing()) { | ||
230 | + for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { | ||
231 | + /* KVM AIA only has one APLIC instance */ | ||
232 | + kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); | ||
233 | + } | ||
234 | + kvm_gsi_routing_allowed = true; | ||
235 | + kvm_irqchip_commit_routes(kvm_state); | ||
236 | + } | ||
237 | + | ||
238 | + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, | ||
239 | + KVM_DEV_RISCV_AIA_CTRL_INIT, | ||
240 | + NULL, true, NULL); | ||
241 | + if (ret < 0) { | ||
242 | + error_report("KVM AIA: initialized fail"); | ||
243 | + exit(1); | ||
244 | + } | ||
245 | + | ||
246 | + kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); | ||
247 | } | ||
248 | -- | ||
249 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Yifei Jiang <jiangyifei@huawei.com> | 1 | From: Yong-Xuan Wang <yongxuan.wang@sifive.com> |
---|---|---|---|
2 | 2 | ||
3 | Add sifive_plic vmstate for supporting sifive_plic migration. | 3 | KVM AIA can't emulate APLIC only. When "aia=aplic" parameter is passed, |
4 | Current vmstate framework only supports one structure parameter | 4 | APLIC devices is emulated by QEMU. For "aia=aplic-imsic", remove the |
5 | as num field to describe variable length arrays, so introduce | 5 | mmio operations of APLIC when using KVM AIA and send wired interrupt |
6 | num_enables. | 6 | signal via KVM_IRQ_LINE API. |
7 | After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API | ||
8 | when the IMSICs receive mmio write requests. | ||
7 | 9 | ||
8 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | 10 | Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> |
9 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | 11 | Reviewed-by: Jim Shu <jim.shu@sifive.com> |
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
11 | Message-id: 20201026115530.304-7-jiangyifei@huawei.com | 13 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> |
14 | Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com> | ||
12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
13 | --- | 16 | --- |
14 | include/hw/intc/sifive_plic.h | 1 + | 17 | hw/intc/riscv_aplic.c | 56 ++++++++++++++++++++++++++++++------------- |
15 | hw/intc/sifive_plic.c | 26 +++++++++++++++++++++++++- | 18 | hw/intc/riscv_imsic.c | 25 +++++++++++++++---- |
16 | 2 files changed, 26 insertions(+), 1 deletion(-) | 19 | 2 files changed, 61 insertions(+), 20 deletions(-) |
17 | 20 | ||
18 | diff --git a/include/hw/intc/sifive_plic.h b/include/hw/intc/sifive_plic.h | 21 | diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c |
19 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/intc/sifive_plic.h | 23 | --- a/hw/intc/riscv_aplic.c |
21 | +++ b/include/hw/intc/sifive_plic.h | 24 | +++ b/hw/intc/riscv_aplic.c |
22 | @@ -XXX,XX +XXX,XX @@ struct SiFivePLICState { | ||
23 | uint32_t num_addrs; | ||
24 | uint32_t num_harts; | ||
25 | uint32_t bitfield_words; | ||
26 | + uint32_t num_enables; | ||
27 | PLICAddr *addr_config; | ||
28 | uint32_t *source_priority; | ||
29 | uint32_t *target_priority; | ||
30 | diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/intc/sifive_plic.c | ||
33 | +++ b/hw/intc/sifive_plic.c | ||
34 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ |
35 | #include "hw/intc/sifive_plic.h" | 26 | #include "hw/irq.h" |
36 | #include "target/riscv/cpu.h" | 27 | #include "target/riscv/cpu.h" |
37 | #include "sysemu/sysemu.h" | 28 | #include "sysemu/sysemu.h" |
38 | +#include "migration/vmstate.h" | 29 | +#include "sysemu/kvm.h" |
39 | 30 | #include "migration/vmstate.h" | |
40 | #define RISCV_DEBUG_PLIC 0 | 31 | |
41 | 32 | #define APLIC_MAX_IDC (1UL << 14) | |
42 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) | 33 | @@ -XXX,XX +XXX,XX @@ |
43 | TYPE_SIFIVE_PLIC, plic->aperture_size); | 34 | |
44 | parse_hart_config(plic); | 35 | #define APLIC_IDC_CLAIMI 0x1c |
45 | plic->bitfield_words = (plic->num_sources + 31) >> 5; | 36 | |
46 | + plic->num_enables = plic->bitfield_words * plic->num_addrs; | 37 | +/* |
47 | plic->source_priority = g_new0(uint32_t, plic->num_sources); | 38 | + * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use |
48 | plic->target_priority = g_new(uint32_t, plic->num_addrs); | 39 | + * APLIC Wired. |
49 | plic->pending = g_new0(uint32_t, plic->bitfield_words); | 40 | + */ |
50 | plic->claimed = g_new0(uint32_t, plic->bitfield_words); | 41 | +static bool is_kvm_aia(bool msimode) |
51 | - plic->enable = g_new0(uint32_t, plic->bitfield_words * plic->num_addrs); | 42 | +{ |
52 | + plic->enable = g_new0(uint32_t, plic->num_enables); | 43 | + return kvm_irqchip_in_kernel() && msimode; |
53 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio); | 44 | +} |
54 | qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources); | 45 | + |
55 | 46 | static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic, | |
56 | @@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp) | 47 | uint32_t word) |
57 | msi_nonbroken = true; | 48 | { |
49 | @@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc) | ||
50 | return topi; | ||
58 | } | 51 | } |
59 | 52 | ||
60 | +static const VMStateDescription vmstate_sifive_plic = { | 53 | +static void riscv_kvm_aplic_request(void *opaque, int irq, int level) |
61 | + .name = "riscv_sifive_plic", | 54 | +{ |
62 | + .version_id = 1, | 55 | + kvm_set_irq(kvm_state, irq, !!level); |
63 | + .minimum_version_id = 1, | 56 | +} |
64 | + .fields = (VMStateField[]) { | 57 | + |
65 | + VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState, | 58 | static void riscv_aplic_request(void *opaque, int irq, int level) |
66 | + num_sources, 0, | 59 | { |
67 | + vmstate_info_uint32, uint32_t), | 60 | bool update = false; |
68 | + VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState, | 61 | @@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) |
69 | + num_addrs, 0, | 62 | uint32_t i; |
70 | + vmstate_info_uint32, uint32_t), | 63 | RISCVAPLICState *aplic = RISCV_APLIC(dev); |
71 | + VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0, | 64 | |
72 | + vmstate_info_uint32, uint32_t), | 65 | - aplic->bitfield_words = (aplic->num_irqs + 31) >> 5; |
73 | + VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0, | 66 | - aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs); |
74 | + vmstate_info_uint32, uint32_t), | 67 | - aplic->state = g_new0(uint32_t, aplic->num_irqs); |
75 | + VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0, | 68 | - aplic->target = g_new0(uint32_t, aplic->num_irqs); |
76 | + vmstate_info_uint32, uint32_t), | 69 | - if (!aplic->msimode) { |
77 | + VMSTATE_END_OF_LIST() | 70 | - for (i = 0; i < aplic->num_irqs; i++) { |
71 | - aplic->target[i] = 1; | ||
72 | + if (!is_kvm_aia(aplic->msimode)) { | ||
73 | + aplic->bitfield_words = (aplic->num_irqs + 31) >> 5; | ||
74 | + aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs); | ||
75 | + aplic->state = g_new0(uint32_t, aplic->num_irqs); | ||
76 | + aplic->target = g_new0(uint32_t, aplic->num_irqs); | ||
77 | + if (!aplic->msimode) { | ||
78 | + for (i = 0; i < aplic->num_irqs; i++) { | ||
79 | + aplic->target[i] = 1; | ||
80 | + } | ||
81 | } | ||
82 | - } | ||
83 | - aplic->idelivery = g_new0(uint32_t, aplic->num_harts); | ||
84 | - aplic->iforce = g_new0(uint32_t, aplic->num_harts); | ||
85 | - aplic->ithreshold = g_new0(uint32_t, aplic->num_harts); | ||
86 | + aplic->idelivery = g_new0(uint32_t, aplic->num_harts); | ||
87 | + aplic->iforce = g_new0(uint32_t, aplic->num_harts); | ||
88 | + aplic->ithreshold = g_new0(uint32_t, aplic->num_harts); | ||
89 | |||
90 | - memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic, | ||
91 | - TYPE_RISCV_APLIC, aplic->aperture_size); | ||
92 | - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); | ||
93 | + memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, | ||
94 | + aplic, TYPE_RISCV_APLIC, aplic->aperture_size); | ||
95 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); | ||
96 | + } | ||
97 | |||
98 | /* | ||
99 | * Only root APLICs have hardware IRQ lines. All non-root APLICs | ||
100 | * have IRQ lines delegated by their parent APLIC. | ||
101 | */ | ||
102 | if (!aplic->parent) { | ||
103 | - qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); | ||
104 | + if (is_kvm_aia(aplic->msimode)) { | ||
105 | + qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs); | ||
106 | + } else { | ||
107 | + qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); | ||
78 | + } | 108 | + } |
79 | +}; | 109 | } |
110 | |||
111 | /* Create output IRQ lines for non-MSI mode */ | ||
112 | @@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, | ||
113 | qdev_prop_set_bit(dev, "mmode", mmode); | ||
114 | |||
115 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
116 | - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); | ||
80 | + | 117 | + |
81 | static void sifive_plic_class_init(ObjectClass *klass, void *data) | 118 | + if (!is_kvm_aia(msimode)) { |
82 | { | 119 | + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); |
83 | DeviceClass *dc = DEVICE_CLASS(klass); | 120 | + } |
84 | 121 | ||
85 | device_class_set_props(dc, sifive_plic_properties); | 122 | if (parent) { |
86 | dc->realize = sifive_plic_realize; | 123 | riscv_aplic_add_child(parent, dev); |
87 | + dc->vmsd = &vmstate_sifive_plic; | 124 | diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c |
88 | } | 125 | index XXXXXXX..XXXXXXX 100644 |
89 | 126 | --- a/hw/intc/riscv_imsic.c | |
90 | static const TypeInfo sifive_plic_info = { | 127 | +++ b/hw/intc/riscv_imsic.c |
128 | @@ -XXX,XX +XXX,XX @@ | ||
129 | #include "target/riscv/cpu.h" | ||
130 | #include "target/riscv/cpu_bits.h" | ||
131 | #include "sysemu/sysemu.h" | ||
132 | +#include "sysemu/kvm.h" | ||
133 | #include "migration/vmstate.h" | ||
134 | |||
135 | #define IMSIC_MMIO_PAGE_LE 0x00 | ||
136 | @@ -XXX,XX +XXX,XX @@ static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value, | ||
137 | goto err; | ||
138 | } | ||
139 | |||
140 | +#if defined(CONFIG_KVM) | ||
141 | + if (kvm_irqchip_in_kernel()) { | ||
142 | + struct kvm_msi msi; | ||
143 | + | ||
144 | + msi.address_lo = extract64(imsic->mmio.addr + addr, 0, 32); | ||
145 | + msi.address_hi = extract64(imsic->mmio.addr + addr, 32, 32); | ||
146 | + msi.data = le32_to_cpu(value); | ||
147 | + | ||
148 | + kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); | ||
149 | + | ||
150 | + return; | ||
151 | + } | ||
152 | +#endif | ||
153 | + | ||
154 | /* Writes only supported for MSI little-endian registers */ | ||
155 | page = addr >> IMSIC_MMIO_PAGE_SHIFT; | ||
156 | if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) { | ||
157 | @@ -XXX,XX +XXX,XX @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp) | ||
158 | CPUState *cpu = cpu_by_arch_id(imsic->hartid); | ||
159 | CPURISCVState *env = cpu ? cpu->env_ptr : NULL; | ||
160 | |||
161 | - imsic->num_eistate = imsic->num_pages * imsic->num_irqs; | ||
162 | - imsic->eidelivery = g_new0(uint32_t, imsic->num_pages); | ||
163 | - imsic->eithreshold = g_new0(uint32_t, imsic->num_pages); | ||
164 | - imsic->eistate = g_new0(uint32_t, imsic->num_eistate); | ||
165 | + if (!kvm_irqchip_in_kernel()) { | ||
166 | + imsic->num_eistate = imsic->num_pages * imsic->num_irqs; | ||
167 | + imsic->eidelivery = g_new0(uint32_t, imsic->num_pages); | ||
168 | + imsic->eithreshold = g_new0(uint32_t, imsic->num_pages); | ||
169 | + imsic->eistate = g_new0(uint32_t, imsic->num_eistate); | ||
170 | + } | ||
171 | |||
172 | memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, | ||
173 | imsic, TYPE_RISCV_IMSIC, | ||
91 | -- | 174 | -- |
92 | 2.28.0 | 175 | 2.41.0 |
93 | |||
94 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Yong-Xuan Wang <yongxuan.wang@sifive.com> |
---|---|---|---|
2 | 2 | ||
3 | This creates a model for PolarFire SoC IOSCB [1] module. It actually | 3 | Select KVM AIA when the host kernel has in-kernel AIA chip support. |
4 | contains lots of sub-modules like various PLLs to control different | 4 | Since KVM AIA only has one APLIC instance, we map the QEMU APLIC |
5 | peripherals. Only the mininum capabilities are emulated to make the | 5 | devices to KVM APLIC. |
6 | HSS DDR memory initialization codes happy. Lots of sub-modules are | ||
7 | created as an unimplemented devices. | ||
8 | 6 | ||
9 | [1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in | 7 | Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> |
10 | https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map | 8 | Reviewed-by: Jim Shu <jim.shu@sifive.com> |
11 | 9 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | |
12 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 10 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> |
13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Message-ID: <20230727102439.22554-6-yongxuan.wang@sifive.com> |
14 | Message-id: 1603863010-15807-5-git-send-email-bmeng.cn@gmail.com | ||
15 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
16 | --- | 13 | --- |
17 | include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++ | 14 | hw/riscv/virt.c | 94 +++++++++++++++++++++++++++++++++---------------- |
18 | hw/misc/mchp_pfsoc_ioscb.c | 242 +++++++++++++++++++++++++++++ | 15 | 1 file changed, 63 insertions(+), 31 deletions(-) |
19 | MAINTAINERS | 2 + | ||
20 | hw/misc/Kconfig | 3 + | ||
21 | hw/misc/meson.build | 1 + | ||
22 | 5 files changed, 298 insertions(+) | ||
23 | create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h | ||
24 | create mode 100644 hw/misc/mchp_pfsoc_ioscb.c | ||
25 | 16 | ||
26 | diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h | 17 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
27 | new file mode 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
28 | index XXXXXXX..XXXXXXX | 19 | --- a/hw/riscv/virt.c |
29 | --- /dev/null | 20 | +++ b/hw/riscv/virt.c |
30 | +++ b/include/hw/misc/mchp_pfsoc_ioscb.h | ||
31 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ |
32 | +/* | 22 | #include "hw/riscv/virt.h" |
33 | + * Microchip PolarFire SoC IOSCB module emulation | 23 | #include "hw/riscv/boot.h" |
34 | + * | 24 | #include "hw/riscv/numa.h" |
35 | + * Copyright (c) 2020 Wind River Systems, Inc. | 25 | +#include "kvm_riscv.h" |
36 | + * | 26 | #include "hw/intc/riscv_aclint.h" |
37 | + * Author: | 27 | #include "hw/intc/riscv_aplic.h" |
38 | + * Bin Meng <bin.meng@windriver.com> | 28 | #include "hw/intc/riscv_imsic.h" |
39 | + * | ||
40 | + * This program is free software; you can redistribute it and/or | ||
41 | + * modify it under the terms of the GNU General Public License as | ||
42 | + * published by the Free Software Foundation; either version 2 or | ||
43 | + * (at your option) version 3 of the License. | ||
44 | + * | ||
45 | + * This program is distributed in the hope that it will be useful, | ||
46 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
47 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
48 | + * GNU General Public License for more details. | ||
49 | + * | ||
50 | + * You should have received a copy of the GNU General Public License along | ||
51 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
52 | + */ | ||
53 | + | ||
54 | +#ifndef MCHP_PFSOC_IOSCB_H | ||
55 | +#define MCHP_PFSOC_IOSCB_H | ||
56 | + | ||
57 | +typedef struct MchpPfSoCIoscbState { | ||
58 | + SysBusDevice parent; | ||
59 | + MemoryRegion container; | ||
60 | + MemoryRegion lane01; | ||
61 | + MemoryRegion lane23; | ||
62 | + MemoryRegion ctrl; | ||
63 | + MemoryRegion cfg; | ||
64 | + MemoryRegion pll_mss; | ||
65 | + MemoryRegion cfm_mss; | ||
66 | + MemoryRegion pll_ddr; | ||
67 | + MemoryRegion bc_ddr; | ||
68 | + MemoryRegion io_calib_ddr; | ||
69 | + MemoryRegion pll_sgmii; | ||
70 | + MemoryRegion dll_sgmii; | ||
71 | + MemoryRegion cfm_sgmii; | ||
72 | + MemoryRegion bc_sgmii; | ||
73 | + MemoryRegion io_calib_sgmii; | ||
74 | +} MchpPfSoCIoscbState; | ||
75 | + | ||
76 | +#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb" | ||
77 | + | ||
78 | +#define MCHP_PFSOC_IOSCB(obj) \ | ||
79 | + OBJECT_CHECK(MchpPfSoCIoscbState, (obj), TYPE_MCHP_PFSOC_IOSCB) | ||
80 | + | ||
81 | +#endif /* MCHP_PFSOC_IOSCB_H */ | ||
82 | diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c | ||
83 | new file mode 100644 | ||
84 | index XXXXXXX..XXXXXXX | ||
85 | --- /dev/null | ||
86 | +++ b/hw/misc/mchp_pfsoc_ioscb.c | ||
87 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ |
88 | +/* | 30 | #error "Can't accommodate all IMSIC groups in address space" |
89 | + * Microchip PolarFire SoC IOSCB module emulation | 31 | #endif |
90 | + * | 32 | |
91 | + * Copyright (c) 2020 Wind River Systems, Inc. | 33 | +/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ |
92 | + * | 34 | +static bool virt_use_kvm_aia(RISCVVirtState *s) |
93 | + * Author: | ||
94 | + * Bin Meng <bin.meng@windriver.com> | ||
95 | + * | ||
96 | + * This program is free software; you can redistribute it and/or | ||
97 | + * modify it under the terms of the GNU General Public License as | ||
98 | + * published by the Free Software Foundation; either version 2 or | ||
99 | + * (at your option) version 3 of the License. | ||
100 | + * | ||
101 | + * This program is distributed in the hope that it will be useful, | ||
102 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
103 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
104 | + * GNU General Public License for more details. | ||
105 | + * | ||
106 | + * You should have received a copy of the GNU General Public License along | ||
107 | + * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
108 | + */ | ||
109 | + | ||
110 | +#include "qemu/osdep.h" | ||
111 | +#include "qemu/bitops.h" | ||
112 | +#include "qemu/log.h" | ||
113 | +#include "qapi/error.h" | ||
114 | +#include "hw/hw.h" | ||
115 | +#include "hw/sysbus.h" | ||
116 | +#include "hw/misc/mchp_pfsoc_ioscb.h" | ||
117 | + | ||
118 | +/* | ||
119 | + * The whole IOSCB module registers map into the system address at 0x3000_0000, | ||
120 | + * named as "System Port 0 (AXI-D0)". | ||
121 | + */ | ||
122 | +#define IOSCB_WHOLE_REG_SIZE 0x10000000 | ||
123 | +#define IOSCB_SUBMOD_REG_SIZE 0x1000 | ||
124 | + | ||
125 | +/* | ||
126 | + * There are many sub-modules in the IOSCB module. | ||
127 | + * See Microchip PolarFire SoC documentation (Register_Map.zip), | ||
128 | + * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm | ||
129 | + * | ||
130 | + * The following are sub-modules offsets that are of concern. | ||
131 | + */ | ||
132 | +#define IOSCB_LANE01_BASE 0x06500000 | ||
133 | +#define IOSCB_LANE23_BASE 0x06510000 | ||
134 | +#define IOSCB_CTRL_BASE 0x07020000 | ||
135 | +#define IOSCB_CFG_BASE 0x07080000 | ||
136 | +#define IOSCB_PLL_MSS_BASE 0x0E001000 | ||
137 | +#define IOSCB_CFM_MSS_BASE 0x0E002000 | ||
138 | +#define IOSCB_PLL_DDR_BASE 0x0E010000 | ||
139 | +#define IOSCB_BC_DDR_BASE 0x0E020000 | ||
140 | +#define IOSCB_IO_CALIB_DDR_BASE 0x0E040000 | ||
141 | +#define IOSCB_PLL_SGMII_BASE 0x0E080000 | ||
142 | +#define IOSCB_DLL_SGMII_BASE 0x0E100000 | ||
143 | +#define IOSCB_CFM_SGMII_BASE 0x0E200000 | ||
144 | +#define IOSCB_BC_SGMII_BASE 0x0E400000 | ||
145 | +#define IOSCB_IO_CALIB_SGMII_BASE 0x0E800000 | ||
146 | + | ||
147 | +static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset, | ||
148 | + unsigned size) | ||
149 | +{ | 35 | +{ |
150 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | 36 | + return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; |
151 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
152 | + __func__, size, offset); | ||
153 | + | ||
154 | + return 0; | ||
155 | +} | 37 | +} |
156 | + | 38 | + |
157 | +static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset, | 39 | static const MemMapEntry virt_memmap[] = { |
158 | + uint64_t value, unsigned size) | 40 | [VIRT_DEBUG] = { 0x0, 0x100 }, |
159 | +{ | 41 | [VIRT_MROM] = { 0x1000, 0xf000 }, |
160 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " | 42 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket, |
161 | + "(size %d, value 0x%" PRIx64 | 43 | uint32_t *intc_phandles, |
162 | + ", offset 0x%" HWADDR_PRIx ")\n", | 44 | uint32_t aplic_phandle, |
163 | + __func__, size, value, offset); | 45 | uint32_t aplic_child_phandle, |
164 | +} | 46 | - bool m_mode) |
47 | + bool m_mode, int num_harts) | ||
48 | { | ||
49 | int cpu; | ||
50 | char *aplic_name; | ||
51 | uint32_t *aplic_cells; | ||
52 | MachineState *ms = MACHINE(s); | ||
53 | |||
54 | - aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); | ||
55 | + aplic_cells = g_new0(uint32_t, num_harts * 2); | ||
56 | |||
57 | - for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { | ||
58 | + for (cpu = 0; cpu < num_harts; cpu++) { | ||
59 | aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); | ||
60 | aplic_cells[cpu * 2 + 1] = cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_S_EXT); | ||
61 | } | ||
62 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket, | ||
63 | |||
64 | if (s->aia_type == VIRT_AIA_TYPE_APLIC) { | ||
65 | qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", | ||
66 | - aplic_cells, | ||
67 | - s->soc[socket].num_harts * sizeof(uint32_t) * 2); | ||
68 | + aplic_cells, num_harts * sizeof(uint32_t) * 2); | ||
69 | } else { | ||
70 | qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle); | ||
71 | } | ||
72 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s, | ||
73 | uint32_t msi_s_phandle, | ||
74 | uint32_t *phandle, | ||
75 | uint32_t *intc_phandles, | ||
76 | - uint32_t *aplic_phandles) | ||
77 | + uint32_t *aplic_phandles, | ||
78 | + int num_harts) | ||
79 | { | ||
80 | char *aplic_name; | ||
81 | unsigned long aplic_addr; | ||
82 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s, | ||
83 | create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].size, | ||
84 | msi_m_phandle, intc_phandles, | ||
85 | aplic_m_phandle, aplic_s_phandle, | ||
86 | - true); | ||
87 | + true, num_harts); | ||
88 | } | ||
89 | |||
90 | /* S-level APLIC node */ | ||
91 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_aplic(RISCVVirtState *s, | ||
92 | create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, | ||
93 | msi_s_phandle, intc_phandles, | ||
94 | aplic_s_phandle, 0, | ||
95 | - false); | ||
96 | + false, num_harts); | ||
97 | |||
98 | aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); | ||
99 | |||
100 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, | ||
101 | *msi_pcie_phandle = msi_s_phandle; | ||
102 | } | ||
103 | |||
104 | - phandle_pos = ms->smp.cpus; | ||
105 | - for (socket = (socket_count - 1); socket >= 0; socket--) { | ||
106 | - phandle_pos -= s->soc[socket].num_harts; | ||
107 | - | ||
108 | - if (s->aia_type == VIRT_AIA_TYPE_NONE) { | ||
109 | - create_fdt_socket_plic(s, memmap, socket, phandle, | ||
110 | - &intc_phandles[phandle_pos], xplic_phandles); | ||
111 | - } else { | ||
112 | - create_fdt_socket_aplic(s, memmap, socket, | ||
113 | - msi_m_phandle, msi_s_phandle, phandle, | ||
114 | - &intc_phandles[phandle_pos], xplic_phandles); | ||
115 | + /* KVM AIA only has one APLIC instance */ | ||
116 | + if (virt_use_kvm_aia(s)) { | ||
117 | + create_fdt_socket_aplic(s, memmap, 0, | ||
118 | + msi_m_phandle, msi_s_phandle, phandle, | ||
119 | + &intc_phandles[0], xplic_phandles, | ||
120 | + ms->smp.cpus); | ||
121 | + } else { | ||
122 | + phandle_pos = ms->smp.cpus; | ||
123 | + for (socket = (socket_count - 1); socket >= 0; socket--) { | ||
124 | + phandle_pos -= s->soc[socket].num_harts; | ||
165 | + | 125 | + |
166 | +static const MemoryRegionOps mchp_pfsoc_dummy_ops = { | 126 | + if (s->aia_type == VIRT_AIA_TYPE_NONE) { |
167 | + .read = mchp_pfsoc_dummy_read, | 127 | + create_fdt_socket_plic(s, memmap, socket, phandle, |
168 | + .write = mchp_pfsoc_dummy_write, | 128 | + &intc_phandles[phandle_pos], |
169 | + .endianness = DEVICE_LITTLE_ENDIAN, | 129 | + xplic_phandles); |
170 | +}; | 130 | + } else { |
171 | + | 131 | + create_fdt_socket_aplic(s, memmap, socket, |
172 | +/* All PLL modules in IOSCB have the same register layout */ | 132 | + msi_m_phandle, msi_s_phandle, phandle, |
173 | + | 133 | + &intc_phandles[phandle_pos], |
174 | +#define PLL_CTRL 0x04 | 134 | + xplic_phandles, |
175 | + | 135 | + s->soc[socket].num_harts); |
176 | +static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset, | 136 | + } |
177 | + unsigned size) | 137 | } |
178 | +{ | 138 | } |
179 | + uint32_t val = 0; | 139 | |
180 | + | 140 | g_free(intc_phandles); |
181 | + switch (offset) { | 141 | |
182 | + case PLL_CTRL: | 142 | - for (socket = 0; socket < socket_count; socket++) { |
183 | + /* PLL is locked */ | 143 | - if (socket == 0) { |
184 | + val = BIT(25); | 144 | - *irq_mmio_phandle = xplic_phandles[socket]; |
185 | + break; | 145 | - *irq_virtio_phandle = xplic_phandles[socket]; |
186 | + default: | 146 | - *irq_pcie_phandle = xplic_phandles[socket]; |
187 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | 147 | - } |
188 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | 148 | - if (socket == 1) { |
189 | + __func__, size, offset); | 149 | - *irq_virtio_phandle = xplic_phandles[socket]; |
190 | + break; | 150 | - *irq_pcie_phandle = xplic_phandles[socket]; |
151 | - } | ||
152 | - if (socket == 2) { | ||
153 | - *irq_pcie_phandle = xplic_phandles[socket]; | ||
154 | + if (virt_use_kvm_aia(s)) { | ||
155 | + *irq_mmio_phandle = xplic_phandles[0]; | ||
156 | + *irq_virtio_phandle = xplic_phandles[0]; | ||
157 | + *irq_pcie_phandle = xplic_phandles[0]; | ||
158 | + } else { | ||
159 | + for (socket = 0; socket < socket_count; socket++) { | ||
160 | + if (socket == 0) { | ||
161 | + *irq_mmio_phandle = xplic_phandles[socket]; | ||
162 | + *irq_virtio_phandle = xplic_phandles[socket]; | ||
163 | + *irq_pcie_phandle = xplic_phandles[socket]; | ||
164 | + } | ||
165 | + if (socket == 1) { | ||
166 | + *irq_virtio_phandle = xplic_phandles[socket]; | ||
167 | + *irq_pcie_phandle = xplic_phandles[socket]; | ||
168 | + } | ||
169 | + if (socket == 2) { | ||
170 | + *irq_pcie_phandle = xplic_phandles[socket]; | ||
171 | + } | ||
172 | } | ||
173 | } | ||
174 | |||
175 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) | ||
176 | } | ||
177 | } | ||
178 | |||
179 | + if (virt_use_kvm_aia(s)) { | ||
180 | + kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, | ||
181 | + VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, | ||
182 | + memmap[VIRT_APLIC_S].base, | ||
183 | + memmap[VIRT_IMSIC_S].base, | ||
184 | + s->aia_guests); | ||
191 | + } | 185 | + } |
192 | + | 186 | + |
193 | + return val; | 187 | if (riscv_is_32bit(&s->soc[0])) { |
194 | +} | 188 | #if HOST_LONG_BITS == 64 |
195 | + | 189 | /* limit RAM size in a 32-bit system */ |
196 | +static const MemoryRegionOps mchp_pfsoc_pll_ops = { | ||
197 | + .read = mchp_pfsoc_pll_read, | ||
198 | + .write = mchp_pfsoc_dummy_write, | ||
199 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
200 | +}; | ||
201 | + | ||
202 | +/* IO_CALIB_DDR submodule */ | ||
203 | + | ||
204 | +#define IO_CALIB_DDR_IOC_REG1 0x08 | ||
205 | + | ||
206 | +static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset, | ||
207 | + unsigned size) | ||
208 | +{ | ||
209 | + uint32_t val = 0; | ||
210 | + | ||
211 | + switch (offset) { | ||
212 | + case IO_CALIB_DDR_IOC_REG1: | ||
213 | + /* calibration completed */ | ||
214 | + val = BIT(2); | ||
215 | + break; | ||
216 | + default: | ||
217 | + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " | ||
218 | + "(size %d, offset 0x%" HWADDR_PRIx ")\n", | ||
219 | + __func__, size, offset); | ||
220 | + break; | ||
221 | + } | ||
222 | + | ||
223 | + return val; | ||
224 | +} | ||
225 | + | ||
226 | +static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = { | ||
227 | + .read = mchp_pfsoc_io_calib_ddr_read, | ||
228 | + .write = mchp_pfsoc_dummy_write, | ||
229 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
230 | +}; | ||
231 | + | ||
232 | +static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp) | ||
233 | +{ | ||
234 | + MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev); | ||
235 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
236 | + | ||
237 | + memory_region_init(&s->container, OBJECT(s), | ||
238 | + "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE); | ||
239 | + sysbus_init_mmio(sbd, &s->container); | ||
240 | + | ||
241 | + /* add subregions for all sub-modules in IOSCB */ | ||
242 | + | ||
243 | + memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
244 | + "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE); | ||
245 | + memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01); | ||
246 | + | ||
247 | + memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
248 | + "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE); | ||
249 | + memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23); | ||
250 | + | ||
251 | + memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
252 | + "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE); | ||
253 | + memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl); | ||
254 | + | ||
255 | + memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
256 | + "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE); | ||
257 | + memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg); | ||
258 | + | ||
259 | + memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s, | ||
260 | + "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE); | ||
261 | + memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss); | ||
262 | + | ||
263 | + memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
264 | + "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE); | ||
265 | + memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss); | ||
266 | + | ||
267 | + memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s, | ||
268 | + "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE); | ||
269 | + memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr); | ||
270 | + | ||
271 | + memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
272 | + "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE); | ||
273 | + memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr); | ||
274 | + | ||
275 | + memory_region_init_io(&s->io_calib_ddr, OBJECT(s), | ||
276 | + &mchp_pfsoc_io_calib_ddr_ops, s, | ||
277 | + "mchp.pfsoc.ioscb.io_calib_ddr", | ||
278 | + IOSCB_SUBMOD_REG_SIZE); | ||
279 | + memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE, | ||
280 | + &s->io_calib_ddr); | ||
281 | + | ||
282 | + memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s, | ||
283 | + "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE); | ||
284 | + memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE, | ||
285 | + &s->pll_sgmii); | ||
286 | + | ||
287 | + memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
288 | + "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE); | ||
289 | + memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE, | ||
290 | + &s->dll_sgmii); | ||
291 | + | ||
292 | + memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
293 | + "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE); | ||
294 | + memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE, | ||
295 | + &s->cfm_sgmii); | ||
296 | + | ||
297 | + memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s, | ||
298 | + "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE); | ||
299 | + memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE, | ||
300 | + &s->bc_sgmii); | ||
301 | + | ||
302 | + memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, | ||
303 | + s, "mchp.pfsoc.ioscb.io_calib_sgmii", | ||
304 | + IOSCB_SUBMOD_REG_SIZE); | ||
305 | + memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE, | ||
306 | + &s->io_calib_sgmii); | ||
307 | +} | ||
308 | + | ||
309 | +static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data) | ||
310 | +{ | ||
311 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
312 | + | ||
313 | + dc->desc = "Microchip PolarFire SoC IOSCB modules"; | ||
314 | + dc->realize = mchp_pfsoc_ioscb_realize; | ||
315 | +} | ||
316 | + | ||
317 | +static const TypeInfo mchp_pfsoc_ioscb_info = { | ||
318 | + .name = TYPE_MCHP_PFSOC_IOSCB, | ||
319 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
320 | + .instance_size = sizeof(MchpPfSoCIoscbState), | ||
321 | + .class_init = mchp_pfsoc_ioscb_class_init, | ||
322 | +}; | ||
323 | + | ||
324 | +static void mchp_pfsoc_ioscb_register_types(void) | ||
325 | +{ | ||
326 | + type_register_static(&mchp_pfsoc_ioscb_info); | ||
327 | +} | ||
328 | + | ||
329 | +type_init(mchp_pfsoc_ioscb_register_types) | ||
330 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
331 | index XXXXXXX..XXXXXXX 100644 | ||
332 | --- a/MAINTAINERS | ||
333 | +++ b/MAINTAINERS | ||
334 | @@ -XXX,XX +XXX,XX @@ S: Supported | ||
335 | F: hw/riscv/microchip_pfsoc.c | ||
336 | F: hw/char/mchp_pfsoc_mmuart.c | ||
337 | F: hw/misc/mchp_pfsoc_dmc.c | ||
338 | +F: hw/misc/mchp_pfsoc_ioscb.c | ||
339 | F: include/hw/riscv/microchip_pfsoc.h | ||
340 | F: include/hw/char/mchp_pfsoc_mmuart.h | ||
341 | F: include/hw/misc/mchp_pfsoc_dmc.h | ||
342 | +F: include/hw/misc/mchp_pfsoc_ioscb.h | ||
343 | |||
344 | RX Machines | ||
345 | ----------- | ||
346 | diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig | ||
347 | index XXXXXXX..XXXXXXX 100644 | ||
348 | --- a/hw/misc/Kconfig | ||
349 | +++ b/hw/misc/Kconfig | ||
350 | @@ -XXX,XX +XXX,XX @@ config AVR_POWER | ||
351 | config MCHP_PFSOC_DMC | ||
352 | bool | ||
353 | |||
354 | +config MCHP_PFSOC_IOSCB | ||
355 | + bool | ||
356 | + | ||
357 | config SIFIVE_TEST | ||
358 | bool | ||
359 | |||
360 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
361 | index XXXXXXX..XXXXXXX 100644 | ||
362 | --- a/hw/misc/meson.build | ||
363 | +++ b/hw/misc/meson.build | ||
364 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) | ||
365 | |||
366 | # RISC-V devices | ||
367 | softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) | ||
368 | +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c')) | ||
369 | softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) | ||
370 | softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) | ||
371 | softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) | ||
372 | -- | 190 | -- |
373 | 2.28.0 | 191 | 2.41.0 |
374 | |||
375 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Conor Dooley <conor.dooley@microchip.com> | ||
1 | 2 | ||
3 | On a dtb dumped from the virt machine, dt-validate complains: | ||
4 | soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], 'compatible': ['riscv,pmu']} should not be valid under {'type': 'object'} | ||
5 | from schema $id: http://devicetree.org/schemas/simple-bus.yaml# | ||
6 | That's pretty cryptic, but running the dtb back through dtc produces | ||
7 | something a lot more reasonable: | ||
8 | Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property | ||
9 | |||
10 | Moving the riscv,pmu node out of the soc bus solves the problem. | ||
11 | |||
12 | Signed-off-by: Conor Dooley <conor.dooley@microchip.com> | ||
13 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
15 | Message-ID: <20230727-groom-decline-2c57ce42841c@spud> | ||
16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | --- | ||
18 | hw/riscv/virt.c | 2 +- | ||
19 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
20 | |||
21 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/hw/riscv/virt.c | ||
24 | +++ b/hw/riscv/virt.c | ||
25 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_pmu(RISCVVirtState *s) | ||
26 | MachineState *ms = MACHINE(s); | ||
27 | RISCVCPU hart = s->soc[0].harts[0]; | ||
28 | |||
29 | - pmu_name = g_strdup_printf("/soc/pmu"); | ||
30 | + pmu_name = g_strdup_printf("/pmu"); | ||
31 | qemu_fdt_add_subnode(ms->fdt, pmu_name); | ||
32 | qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); | ||
33 | riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); | ||
34 | -- | ||
35 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Yifei Jiang <jiangyifei@huawei.com> | 1 | From: Weiwei Li <liweiwei@iscas.ac.cn> |
---|---|---|---|
2 | 2 | ||
3 | mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. | 3 | The Svadu specification updated the name of the *envcfg bit from |
4 | This patch expands mstatus and vsstatus to uint64_t instead of | 4 | HADE to ADUE. |
5 | target_ulong so that it can be saved as one unit and reduce some | ||
6 | ifdefs in the code. | ||
7 | 5 | ||
8 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | 6 | Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> |
9 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | 7 | Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> |
8 | Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
9 | Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
11 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | Message-id: 20201026115530.304-2-jiangyifei@huawei.com | ||
13 | --- | 11 | --- |
14 | target/riscv/cpu.h | 24 +++++++++++------------- | 12 | target/riscv/cpu_bits.h | 8 ++++---- |
15 | target/riscv/cpu_bits.h | 19 ++++--------------- | 13 | target/riscv/cpu.c | 4 ++-- |
16 | target/riscv/cpu.c | 8 +++++--- | 14 | target/riscv/cpu_helper.c | 6 +++--- |
17 | target/riscv/cpu_helper.c | 35 +++++++---------------------------- | 15 | target/riscv/csr.c | 12 ++++++------ |
18 | target/riscv/csr.c | 18 ++++++++++-------- | 16 | 4 files changed, 15 insertions(+), 15 deletions(-) |
19 | target/riscv/op_helper.c | 11 ++++------- | ||
20 | 6 files changed, 41 insertions(+), 74 deletions(-) | ||
21 | 17 | ||
22 | diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/target/riscv/cpu.h | ||
25 | +++ b/target/riscv/cpu.h | ||
26 | @@ -XXX,XX +XXX,XX @@ struct CPURISCVState { | ||
27 | target_ulong resetvec; | ||
28 | |||
29 | target_ulong mhartid; | ||
30 | - target_ulong mstatus; | ||
31 | + /* | ||
32 | + * For RV32 this is 32-bit mstatus and 32-bit mstatush. | ||
33 | + * For RV64 this is a 64-bit mstatus. | ||
34 | + */ | ||
35 | + uint64_t mstatus; | ||
36 | |||
37 | target_ulong mip; | ||
38 | |||
39 | -#ifdef TARGET_RISCV32 | ||
40 | - target_ulong mstatush; | ||
41 | -#endif | ||
42 | - | ||
43 | uint32_t miclaim; | ||
44 | |||
45 | target_ulong mie; | ||
46 | @@ -XXX,XX +XXX,XX @@ struct CPURISCVState { | ||
47 | uint64_t htimedelta; | ||
48 | |||
49 | /* Virtual CSRs */ | ||
50 | - target_ulong vsstatus; | ||
51 | + /* | ||
52 | + * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. | ||
53 | + * For RV64 this is a 64-bit vsstatus. | ||
54 | + */ | ||
55 | + uint64_t vsstatus; | ||
56 | target_ulong vstvec; | ||
57 | target_ulong vsscratch; | ||
58 | target_ulong vsepc; | ||
59 | target_ulong vscause; | ||
60 | target_ulong vstval; | ||
61 | target_ulong vsatp; | ||
62 | -#ifdef TARGET_RISCV32 | ||
63 | - target_ulong vsstatush; | ||
64 | -#endif | ||
65 | |||
66 | target_ulong mtval2; | ||
67 | target_ulong mtinst; | ||
68 | @@ -XXX,XX +XXX,XX @@ struct CPURISCVState { | ||
69 | target_ulong scause_hs; | ||
70 | target_ulong stval_hs; | ||
71 | target_ulong satp_hs; | ||
72 | - target_ulong mstatus_hs; | ||
73 | -#ifdef TARGET_RISCV32 | ||
74 | - target_ulong mstatush_hs; | ||
75 | -#endif | ||
76 | + uint64_t mstatus_hs; | ||
77 | |||
78 | target_ulong scounteren; | ||
79 | target_ulong mcounteren; | ||
80 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h | 18 | diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h |
81 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
82 | --- a/target/riscv/cpu_bits.h | 20 | --- a/target/riscv/cpu_bits.h |
83 | +++ b/target/riscv/cpu_bits.h | 21 | +++ b/target/riscv/cpu_bits.h |
84 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ typedef enum RISCVException { |
85 | #define TARGET_RISCV_CPU_BITS_H | 23 | #define MENVCFG_CBIE (3UL << 4) |
86 | 24 | #define MENVCFG_CBCFE BIT(6) | |
87 | #define get_field(reg, mask) (((reg) & \ | 25 | #define MENVCFG_CBZE BIT(7) |
88 | - (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) | 26 | -#define MENVCFG_HADE (1ULL << 61) |
89 | -#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ | 27 | +#define MENVCFG_ADUE (1ULL << 61) |
90 | - (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ | 28 | #define MENVCFG_PBMTE (1ULL << 62) |
91 | - (target_ulong)(mask))) | 29 | #define MENVCFG_STCE (1ULL << 63) |
92 | + (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) | 30 | |
93 | +#define set_field(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ | 31 | /* For RV32 */ |
94 | + (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ | 32 | -#define MENVCFGH_HADE BIT(29) |
95 | + (uint64_t)(mask))) | 33 | +#define MENVCFGH_ADUE BIT(29) |
96 | 34 | #define MENVCFGH_PBMTE BIT(30) | |
97 | /* Floating point round mode */ | 35 | #define MENVCFGH_STCE BIT(31) |
98 | #define FSR_RD_SHIFT 5 | 36 | |
99 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ typedef enum RISCVException { |
100 | #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ | 38 | #define HENVCFG_CBIE MENVCFG_CBIE |
101 | #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ | 39 | #define HENVCFG_CBCFE MENVCFG_CBCFE |
102 | #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ | 40 | #define HENVCFG_CBZE MENVCFG_CBZE |
103 | -#if defined(TARGET_RISCV64) | 41 | -#define HENVCFG_HADE MENVCFG_HADE |
104 | #define MSTATUS_GVA 0x4000000000ULL | 42 | +#define HENVCFG_ADUE MENVCFG_ADUE |
105 | #define MSTATUS_MPV 0x8000000000ULL | 43 | #define HENVCFG_PBMTE MENVCFG_PBMTE |
106 | -#elif defined(TARGET_RISCV32) | 44 | #define HENVCFG_STCE MENVCFG_STCE |
107 | -#define MSTATUS_GVA 0x00000040 | 45 | |
108 | -#define MSTATUS_MPV 0x00000080 | 46 | /* For RV32 */ |
109 | -#endif | 47 | -#define HENVCFGH_HADE MENVCFGH_HADE |
110 | - | 48 | +#define HENVCFGH_ADUE MENVCFGH_ADUE |
111 | -#ifdef TARGET_RISCV32 | 49 | #define HENVCFGH_PBMTE MENVCFGH_PBMTE |
112 | -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV) | 50 | #define HENVCFGH_STCE MENVCFGH_STCE |
113 | -#else | 51 | |
114 | -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV) | ||
115 | -#endif | ||
116 | |||
117 | #define MSTATUS64_UXL 0x0000000300000000ULL | ||
118 | #define MSTATUS64_SXL 0x0000000C00000000ULL | ||
119 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | 52 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c |
120 | index XXXXXXX..XXXXXXX 100644 | 53 | index XXXXXXX..XXXXXXX 100644 |
121 | --- a/target/riscv/cpu.c | 54 | --- a/target/riscv/cpu.c |
122 | +++ b/target/riscv/cpu.c | 55 | +++ b/target/riscv/cpu.c |
123 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) | 56 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj) |
124 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); | 57 | env->two_stage_lookup = false; |
125 | #ifndef CONFIG_USER_ONLY | 58 | |
126 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); | 59 | env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | |
127 | - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); | 60 | - (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); |
128 | + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); | 61 | + (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); |
129 | #ifdef TARGET_RISCV32 | 62 | env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | |
130 | - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); | 63 | - (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); |
131 | + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", | 64 | + (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); |
132 | + (target_ulong)(env->mstatus >> 32)); | 65 | |
133 | #endif | 66 | /* Initialized default priorities of local interrupts. */ |
134 | if (riscv_has_ext(env, RVH)) { | 67 | for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { |
135 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); | ||
136 | - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus); | ||
137 | + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", | ||
138 | + (target_ulong)env->vsstatus); | ||
139 | } | ||
140 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); | ||
141 | qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); | ||
142 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c | 68 | diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c |
143 | index XXXXXXX..XXXXXXX 100644 | 69 | index XXXXXXX..XXXXXXX 100644 |
144 | --- a/target/riscv/cpu_helper.c | 70 | --- a/target/riscv/cpu_helper.c |
145 | +++ b/target/riscv/cpu_helper.c | 71 | +++ b/target/riscv/cpu_helper.c |
146 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) | 72 | @@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, |
147 | |||
148 | void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) | ||
149 | { | ||
150 | - target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | | ||
151 | - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; | ||
152 | + uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | | ||
153 | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | | ||
154 | + MSTATUS64_UXL; | ||
155 | bool current_virt = riscv_cpu_virt_enabled(env); | ||
156 | |||
157 | g_assert(riscv_has_ext(env, RVH)); | ||
158 | |||
159 | -#if defined(TARGET_RISCV64) | ||
160 | - mstatus_mask |= MSTATUS64_UXL; | ||
161 | -#endif | ||
162 | - | ||
163 | if (current_virt) { | ||
164 | /* Current V=1 and we are about to change to V=0 */ | ||
165 | env->vsstatus = env->mstatus & mstatus_mask; | ||
166 | env->mstatus &= ~mstatus_mask; | ||
167 | env->mstatus |= env->mstatus_hs; | ||
168 | |||
169 | -#if defined(TARGET_RISCV32) | ||
170 | - env->vsstatush = env->mstatush; | ||
171 | - env->mstatush |= env->mstatush_hs; | ||
172 | -#endif | ||
173 | - | ||
174 | env->vstvec = env->stvec; | ||
175 | env->stvec = env->stvec_hs; | ||
176 | |||
177 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) | ||
178 | env->mstatus &= ~mstatus_mask; | ||
179 | env->mstatus |= env->vsstatus; | ||
180 | |||
181 | -#if defined(TARGET_RISCV32) | ||
182 | - env->mstatush_hs = env->mstatush; | ||
183 | - env->mstatush |= env->vsstatush; | ||
184 | -#endif | ||
185 | - | ||
186 | env->stvec_hs = env->stvec; | ||
187 | env->stvec = env->vstvec; | ||
188 | |||
189 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | ||
190 | if (riscv_has_ext(env, RVH) && env->priv == PRV_M && | ||
191 | access_type != MMU_INST_FETCH && | ||
192 | get_field(env->mstatus, MSTATUS_MPRV) && | ||
193 | - MSTATUS_MPV_ISSET(env)) { | ||
194 | + get_field(env->mstatus, MSTATUS_MPV)) { | ||
195 | riscv_cpu_set_two_stage_lookup(env, true); | ||
196 | } | 73 | } |
197 | 74 | ||
198 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, | 75 | bool pbmte = env->menvcfg & MENVCFG_PBMTE; |
199 | if (riscv_has_ext(env, RVH) && env->priv == PRV_M && | 76 | - bool hade = env->menvcfg & MENVCFG_HADE; |
200 | access_type != MMU_INST_FETCH && | 77 | + bool adue = env->menvcfg & MENVCFG_ADUE; |
201 | get_field(env->mstatus, MSTATUS_MPRV) && | 78 | |
202 | - MSTATUS_MPV_ISSET(env)) { | 79 | if (first_stage && two_stage && env->virt_enabled) { |
203 | + get_field(env->mstatus, MSTATUS_MPV)) { | 80 | pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); |
204 | riscv_cpu_set_two_stage_lookup(env, false); | 81 | - hade = hade && (env->henvcfg & HENVCFG_HADE); |
82 | + adue = adue && (env->henvcfg & HENVCFG_ADUE); | ||
205 | } | 83 | } |
206 | 84 | ||
207 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | 85 | int ptshift = (levels - 1) * ptidxbits; |
208 | RISCVCPU *cpu = RISCV_CPU(cs); | 86 | @@ -XXX,XX +XXX,XX @@ restart: |
209 | CPURISCVState *env = &cpu->env; | 87 | |
210 | bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env); | 88 | /* Page table updates need to be atomic with MTTCG enabled */ |
211 | - target_ulong s; | 89 | if (updated_pte != pte && !is_debug) { |
212 | + uint64_t s; | 90 | - if (!hade) { |
213 | 91 | + if (!adue) { | |
214 | /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide | 92 | return TRANSLATE_FAIL; |
215 | * so we mask off the MSB and separate into trap type and cause. | 93 | } |
216 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs) | ||
217 | if (riscv_cpu_virt_enabled(env)) { | ||
218 | riscv_cpu_swap_hypervisor_regs(env); | ||
219 | } | ||
220 | -#ifdef TARGET_RISCV32 | ||
221 | - env->mstatush = set_field(env->mstatush, MSTATUS_MPV, | ||
222 | - riscv_cpu_virt_enabled(env)); | ||
223 | - if (riscv_cpu_virt_enabled(env) && tval) { | ||
224 | - env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1); | ||
225 | - } | ||
226 | -#else | ||
227 | env->mstatus = set_field(env->mstatus, MSTATUS_MPV, | ||
228 | - riscv_cpu_virt_enabled(env)); | ||
229 | + riscv_cpu_virt_enabled(env)); | ||
230 | if (riscv_cpu_virt_enabled(env) && tval) { | ||
231 | env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); | ||
232 | } | ||
233 | -#endif | ||
234 | |||
235 | mtval2 = env->guest_phys_fault_addr; | ||
236 | 94 | ||
237 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 95 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
238 | index XXXXXXX..XXXXXXX 100644 | 96 | index XXXXXXX..XXXXXXX 100644 |
239 | --- a/target/riscv/csr.c | 97 | --- a/target/riscv/csr.c |
240 | +++ b/target/riscv/csr.c | 98 | +++ b/target/riscv/csr.c |
241 | @@ -XXX,XX +XXX,XX @@ static int validate_vm(CPURISCVState *env, target_ulong vm) | 99 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno, |
242 | 100 | if (riscv_cpu_mxl(env) == MXL_RV64) { | |
243 | static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) | 101 | mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | |
102 | (cfg->ext_sstc ? MENVCFG_STCE : 0) | | ||
103 | - (cfg->ext_svadu ? MENVCFG_HADE : 0); | ||
104 | + (cfg->ext_svadu ? MENVCFG_ADUE : 0); | ||
105 | } | ||
106 | env->menvcfg = (env->menvcfg & ~mask) | (val & mask); | ||
107 | |||
108 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, | ||
109 | const RISCVCPUConfig *cfg = riscv_cpu_cfg(env); | ||
110 | uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | | ||
111 | (cfg->ext_sstc ? MENVCFG_STCE : 0) | | ||
112 | - (cfg->ext_svadu ? MENVCFG_HADE : 0); | ||
113 | + (cfg->ext_svadu ? MENVCFG_ADUE : 0); | ||
114 | uint64_t valh = (uint64_t)val << 32; | ||
115 | |||
116 | env->menvcfg = (env->menvcfg & ~mask) | (valh & mask); | ||
117 | @@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno, | ||
118 | * henvcfg.stce is read_only 0 when menvcfg.stce = 0 | ||
119 | * henvcfg.hade is read_only 0 when menvcfg.hade = 0 | ||
120 | */ | ||
121 | - *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) | | ||
122 | + *val = env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | | ||
123 | env->menvcfg); | ||
124 | return RISCV_EXCP_NONE; | ||
125 | } | ||
126 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, | ||
127 | } | ||
128 | |||
129 | if (riscv_cpu_mxl(env) == MXL_RV64) { | ||
130 | - mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE); | ||
131 | + mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE); | ||
132 | } | ||
133 | |||
134 | env->henvcfg = (env->henvcfg & ~mask) | (val & mask); | ||
135 | @@ -XXX,XX +XXX,XX @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, | ||
136 | return ret; | ||
137 | } | ||
138 | |||
139 | - *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE) | | ||
140 | + *val = (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE) | | ||
141 | env->menvcfg)) >> 32; | ||
142 | return RISCV_EXCP_NONE; | ||
143 | } | ||
144 | @@ -XXX,XX +XXX,XX @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, | ||
145 | target_ulong val) | ||
244 | { | 146 | { |
245 | - target_ulong mstatus = env->mstatus; | 147 | uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | |
246 | - target_ulong mask = 0; | 148 | - HENVCFG_HADE); |
247 | + uint64_t mstatus = env->mstatus; | 149 | + HENVCFG_ADUE); |
248 | + uint64_t mask = 0; | 150 | uint64_t valh = (uint64_t)val << 32; |
249 | int dirty; | 151 | RISCVException ret; |
250 | |||
251 | /* flush tlb on mstatus fields that affect VM */ | ||
252 | @@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
253 | #ifdef TARGET_RISCV32 | ||
254 | static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) | ||
255 | { | ||
256 | - *val = env->mstatush; | ||
257 | + *val = env->mstatus >> 32; | ||
258 | return 0; | ||
259 | } | ||
260 | |||
261 | static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) | ||
262 | { | ||
263 | - if ((val ^ env->mstatush) & (MSTATUS_MPV)) { | ||
264 | + uint64_t valh = (uint64_t)val << 32; | ||
265 | + uint64_t mask = MSTATUS_MPV | MSTATUS_GVA; | ||
266 | + | ||
267 | + if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { | ||
268 | tlb_flush(env_cpu(env)); | ||
269 | } | ||
270 | |||
271 | - val &= MSTATUS_MPV | MSTATUS_GVA; | ||
272 | - | ||
273 | - env->mstatush = val; | ||
274 | + env->mstatus = (env->mstatus & ~mask) | (valh & mask); | ||
275 | |||
276 | return 0; | ||
277 | } | ||
278 | @@ -XXX,XX +XXX,XX @@ static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) | ||
279 | |||
280 | static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) | ||
281 | { | ||
282 | - env->vsstatus = val; | ||
283 | + uint64_t mask = (target_ulong)-1; | ||
284 | + env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val; | ||
285 | return 0; | ||
286 | } | ||
287 | |||
288 | diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c | ||
289 | index XXXXXXX..XXXXXXX 100644 | ||
290 | --- a/target/riscv/op_helper.c | ||
291 | +++ b/target/riscv/op_helper.c | ||
292 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, | ||
293 | |||
294 | target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) | ||
295 | { | ||
296 | - target_ulong prev_priv, prev_virt, mstatus; | ||
297 | + uint64_t mstatus; | ||
298 | + target_ulong prev_priv, prev_virt; | ||
299 | |||
300 | if (!(env->priv >= PRV_S)) { | ||
301 | riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); | ||
302 | @@ -XXX,XX +XXX,XX @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) | ||
303 | riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); | ||
304 | } | ||
305 | |||
306 | - target_ulong mstatus = env->mstatus; | ||
307 | + uint64_t mstatus = env->mstatus; | ||
308 | target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); | ||
309 | - target_ulong prev_virt = MSTATUS_MPV_ISSET(env); | ||
310 | + target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); | ||
311 | mstatus = set_field(mstatus, MSTATUS_MIE, | ||
312 | get_field(mstatus, MSTATUS_MPIE)); | ||
313 | mstatus = set_field(mstatus, MSTATUS_MPIE, 1); | ||
314 | mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); | ||
315 | -#ifdef TARGET_RISCV32 | ||
316 | - env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0); | ||
317 | -#else | ||
318 | mstatus = set_field(mstatus, MSTATUS_MPV, 0); | ||
319 | -#endif | ||
320 | env->mstatus = mstatus; | ||
321 | riscv_cpu_set_mode(env, prev_priv); | ||
322 | 152 | ||
323 | -- | 153 | -- |
324 | 2.28.0 | 154 | 2.41.0 |
325 | |||
326 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
1 | 2 | ||
3 | In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times | ||
4 | longer to boot than the 'rv64' KVM CPU. | ||
5 | |||
6 | The reason is an unintended behavior of riscv_cpu_satp_mode_finalize() | ||
7 | when satp_mode.supported = 0, i.e. when cpu_init() does not set | ||
8 | satp_mode_max_supported(). satp_mode_max_from_map(map) does: | ||
9 | |||
10 | 31 - __builtin_clz(map) | ||
11 | |||
12 | This means that, if satp_mode.supported = 0, satp_mode_supported_max | ||
13 | wil be '31 - 32'. But this is C, so satp_mode_supported_max will gladly | ||
14 | set it to UINT_MAX (4294967295). After that, if the user didn't set a | ||
15 | satp_mode, set_satp_mode_default_map(cpu) will make | ||
16 | |||
17 | cfg.satp_mode.map = cfg.satp_mode.supported | ||
18 | |||
19 | So satp_mode.map = 0. And then satp_mode_map_max will be set to | ||
20 | satp_mode_max_from_map(cpu->cfg.satp_mode.map), i.e. also UINT_MAX. The | ||
21 | guard "satp_mode_map_max > satp_mode_supported_max" doesn't protect us | ||
22 | here since both are UINT_MAX. | ||
23 | |||
24 | And finally we have 2 loops: | ||
25 | |||
26 | for (int i = satp_mode_map_max - 1; i >= 0; --i) { | ||
27 | |||
28 | Which are, in fact, 2 loops from UINT_MAX -1 to -1. This is where the | ||
29 | extra delay when booting the 'host' CPU is coming from. | ||
30 | |||
31 | Commit 43d1de32f8 already set a precedence for satp_mode.supported = 0 | ||
32 | in a different manner. We're doing the same here. If supported == 0, | ||
33 | interpret as 'the CPU wants the OS to handle satp mode alone' and skip | ||
34 | satp_mode_finalize(). | ||
35 | |||
36 | We'll also put a guard in satp_mode_max_from_map() to assert out if map | ||
37 | is 0 since the function is not ready to deal with it. | ||
38 | |||
39 | Cc: Alexandre Ghiti <alexghiti@rivosinc.com> | ||
40 | Fixes: 6f23aaeb9b ("riscv: Allow user to set the satp mode") | ||
41 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
42 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
43 | Message-ID: <20230817152903.694926-1-dbarboza@ventanamicro.com> | ||
44 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
45 | --- | ||
46 | target/riscv/cpu.c | 23 ++++++++++++++++++++--- | ||
47 | 1 file changed, 20 insertions(+), 3 deletions(-) | ||
48 | |||
49 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/riscv/cpu.c | ||
52 | +++ b/target/riscv/cpu.c | ||
53 | @@ -XXX,XX +XXX,XX @@ static uint8_t satp_mode_from_str(const char *satp_mode_str) | ||
54 | |||
55 | uint8_t satp_mode_max_from_map(uint32_t map) | ||
56 | { | ||
57 | + /* | ||
58 | + * 'map = 0' will make us return (31 - 32), which C will | ||
59 | + * happily overflow to UINT_MAX. There's no good result to | ||
60 | + * return if 'map = 0' (e.g. returning 0 will be ambiguous | ||
61 | + * with the result for 'map = 1'). | ||
62 | + * | ||
63 | + * Assert out if map = 0. Callers will have to deal with | ||
64 | + * it outside of this function. | ||
65 | + */ | ||
66 | + g_assert(map > 0); | ||
67 | + | ||
68 | /* map here has at least one bit set, so no problem with clz */ | ||
69 | return 31 - __builtin_clz(map); | ||
70 | } | ||
71 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) | ||
72 | static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) | ||
73 | { | ||
74 | bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; | ||
75 | - uint8_t satp_mode_map_max; | ||
76 | - uint8_t satp_mode_supported_max = | ||
77 | - satp_mode_max_from_map(cpu->cfg.satp_mode.supported); | ||
78 | + uint8_t satp_mode_map_max, satp_mode_supported_max; | ||
79 | + | ||
80 | + /* The CPU wants the OS to decide which satp mode to use */ | ||
81 | + if (cpu->cfg.satp_mode.supported == 0) { | ||
82 | + return; | ||
83 | + } | ||
84 | + | ||
85 | + satp_mode_supported_max = | ||
86 | + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); | ||
87 | |||
88 | if (cpu->cfg.satp_mode.map == 0) { | ||
89 | if (cpu->cfg.satp_mode.init == 0) { | ||
90 | -- | ||
91 | 2.41.0 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Vineet Gupta <vineetg@rivosinc.com> | ||
1 | 2 | ||
3 | zicond is now codegen supported in both llvm and gcc. | ||
4 | |||
5 | This change allows seamless enabling/testing of zicond in downstream | ||
6 | projects. e.g. currently riscv-gnu-toolchain parses elf attributes | ||
7 | to create a cmdline for qemu but fails short of enabling it because of | ||
8 | the "x-" prefix. | ||
9 | |||
10 | Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> | ||
11 | Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com> | ||
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
14 | --- | ||
15 | target/riscv/cpu.c | 2 +- | ||
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/riscv/cpu.c | ||
21 | +++ b/target/riscv/cpu.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
23 | DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), | ||
24 | DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), | ||
25 | DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), | ||
26 | + DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false), | ||
27 | |||
28 | /* Vendor-specific custom extensions */ | ||
29 | DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), | ||
30 | @@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_extensions[] = { | ||
31 | DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), | ||
32 | |||
33 | /* These are experimental so mark with 'x-' */ | ||
34 | - DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), | ||
35 | |||
36 | /* ePMP 0.9.3 */ | ||
37 | DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), | ||
38 | -- | ||
39 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Anup Patel <anup.patel@wdc.com> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
---|---|---|---|
2 | 2 | ||
3 | Extend virt machine to allow passing custom DTB using "-dtb" | 3 | A build with --enable-debug and without KVM will fail as follows: |
4 | command-line parameter. This will help users pass modified DTB | ||
5 | to virt machine. | ||
6 | 4 | ||
7 | Signed-off-by: Anup Patel <anup.patel@wdc.com> | 5 | /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function `virt_machine_init': |
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 6 | ./qemu/build/../hw/riscv/virt.c:1465: undefined reference to `kvm_riscv_aia_create' |
9 | Message-id: 20201022053225.2596110-2-anup.patel@wdc.com | 7 | |
8 | This happens because the code block with "if virt_use_kvm_aia(s)" isn't | ||
9 | being ignored by the debug build, resulting in an undefined reference to | ||
10 | a KVM only function. | ||
11 | |||
12 | Add a 'kvm_enabled()' conditional together with virt_use_kvm_aia() will | ||
13 | make the compiler crop the kvm_riscv_aia_create() call entirely from a | ||
14 | non-KVM build. Note that adding the 'kvm_enabled()' conditional inside | ||
15 | virt_use_kvm_aia() won't fix the build because this function would need | ||
16 | to be inlined multiple times to make the compiler zero out the entire | ||
17 | block. | ||
18 | |||
19 | While we're at it, use kvm_enabled() in all instances where | ||
20 | virt_use_kvm_aia() is checked to allow the compiler to elide these other | ||
21 | kvm-only instances as well. | ||
22 | |||
23 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
24 | Fixes: dbdb99948e ("target/riscv: select KVM AIA in riscv virt machine") | ||
25 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
26 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
27 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
28 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
29 | Message-ID: <20230830133503.711138-2-dbarboza@ventanamicro.com> | ||
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 30 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
11 | --- | 31 | --- |
12 | hw/riscv/virt.c | 27 ++++++++++++++++++++------- | 32 | hw/riscv/virt.c | 6 +++--- |
13 | 1 file changed, 20 insertions(+), 7 deletions(-) | 33 | 1 file changed, 3 insertions(+), 3 deletions(-) |
14 | 34 | ||
15 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c | 35 | diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c |
16 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/riscv/virt.c | 37 | --- a/hw/riscv/virt.c |
18 | +++ b/hw/riscv/virt.c | 38 | +++ b/hw/riscv/virt.c |
19 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | 39 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, |
20 | { | ||
21 | void *fdt; | ||
22 | int i, cpu, socket; | ||
23 | + const char *dtb_filename; | ||
24 | MachineState *mc = MACHINE(s); | ||
25 | uint64_t addr, size; | ||
26 | uint32_t *clint_cells, *plic_cells; | ||
27 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | ||
28 | hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; | ||
29 | hwaddr flashbase = virt_memmap[VIRT_FLASH].base; | ||
30 | |||
31 | - fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
32 | - if (!fdt) { | ||
33 | - error_report("create_device_tree() failed"); | ||
34 | - exit(1); | ||
35 | + dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); | ||
36 | + if (dtb_filename) { | ||
37 | + fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size); | ||
38 | + if (!fdt) { | ||
39 | + error_report("load_device_tree() failed"); | ||
40 | + exit(1); | ||
41 | + } | ||
42 | + goto update_bootargs; | ||
43 | + } else { | ||
44 | + fdt = s->fdt = create_device_tree(&s->fdt_size); | ||
45 | + if (!fdt) { | ||
46 | + error_report("create_device_tree() failed"); | ||
47 | + exit(1); | ||
48 | + } | ||
49 | } | 40 | } |
50 | 41 | ||
51 | qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); | 42 | /* KVM AIA only has one APLIC instance */ |
52 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | 43 | - if (virt_use_kvm_aia(s)) { |
53 | 44 | + if (kvm_enabled() && virt_use_kvm_aia(s)) { | |
54 | qemu_fdt_add_subnode(fdt, "/chosen"); | 45 | create_fdt_socket_aplic(s, memmap, 0, |
55 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); | 46 | msi_m_phandle, msi_s_phandle, phandle, |
56 | - if (cmdline) { | 47 | &intc_phandles[0], xplic_phandles, |
57 | - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | 48 | @@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, |
58 | - } | 49 | |
59 | g_free(name); | 50 | g_free(intc_phandles); |
60 | 51 | ||
61 | name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); | 52 | - if (virt_use_kvm_aia(s)) { |
62 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, | 53 | + if (kvm_enabled() && virt_use_kvm_aia(s)) { |
63 | 2, flashbase + flashsize, 2, flashsize); | 54 | *irq_mmio_phandle = xplic_phandles[0]; |
64 | qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4); | 55 | *irq_virtio_phandle = xplic_phandles[0]; |
65 | g_free(name); | 56 | *irq_pcie_phandle = xplic_phandles[0]; |
66 | + | 57 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine) |
67 | +update_bootargs: | 58 | } |
68 | + if (cmdline) { | 59 | } |
69 | + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | 60 | |
70 | + } | 61 | - if (virt_use_kvm_aia(s)) { |
71 | } | 62 | + if (kvm_enabled() && virt_use_kvm_aia(s)) { |
72 | 63 | kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, | |
73 | static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, | 64 | VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, |
65 | memmap[VIRT_APLIC_S].base, | ||
74 | -- | 66 | -- |
75 | 2.28.0 | 67 | 2.41.0 |
76 | 68 | ||
77 | 69 | diff view generated by jsdifflib |
1 | From: Yifei Jiang <jiangyifei@huawei.com> | 1 | From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
---|---|---|---|
2 | 2 | ||
3 | In the case of supporting V extension, add V extension description | 3 | Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM |
4 | to vmstate_riscv_cpu. | 4 | environment with the following error: |
5 | 5 | ||
6 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | 6 | /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in function `riscv_kvm_aplic_request': |
7 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | 7 | ./qemu/build/../hw/intc/riscv_aplic.c:486: undefined reference to `kvm_set_irq' |
8 | collect2: error: ld returned 1 exit status | ||
9 | |||
10 | This happens because the debug build will poke into the | ||
11 | 'if (is_kvm_aia(aplic->msimode))' block and fail to find a reference to | ||
12 | the KVM only function riscv_kvm_aplic_request(). | ||
13 | |||
14 | There are multiple solutions to fix this. We'll go with the same | ||
15 | solution from the previous patch, i.e. add a kvm_enabled() conditional | ||
16 | to filter out the block. But there's a catch: riscv_kvm_aplic_request() | ||
17 | is a local function that would end up being used if the compiler crops | ||
18 | the block, and this won't work. Quoting Richard Henderson's explanation | ||
19 | in [1]: | ||
20 | |||
21 | "(...) the compiler won't eliminate entire unused functions with -O0" | ||
22 | |||
23 | We'll solve it by moving riscv_kvm_aplic_request() to kvm.c and add its | ||
24 | declaration in kvm_riscv.h, where all other KVM specific public | ||
25 | functions are already declared. Other archs handles KVM specific code in | ||
26 | this manner and we expect to do the same from now on. | ||
27 | |||
28 | [1] https://lore.kernel.org/qemu-riscv/d2f1ad02-eb03-138f-9d08-db676deeed05@linaro.org/ | ||
29 | |||
30 | Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> | ||
31 | Reviewed-by: Andrew Jones <ajones@ventanamicro.com> | ||
32 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 33 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 34 | Message-ID: <20230830133503.711138-3-dbarboza@ventanamicro.com> |
10 | Message-id: 20201026115530.304-6-jiangyifei@huawei.com | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 35 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
12 | --- | 36 | --- |
13 | target/riscv/machine.c | 25 +++++++++++++++++++++++++ | 37 | target/riscv/kvm_riscv.h | 1 + |
14 | 1 file changed, 25 insertions(+) | 38 | hw/intc/riscv_aplic.c | 8 ++------ |
39 | target/riscv/kvm.c | 5 +++++ | ||
40 | 3 files changed, 8 insertions(+), 6 deletions(-) | ||
15 | 41 | ||
16 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | 42 | diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h |
17 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/riscv/machine.c | 44 | --- a/target/riscv/kvm_riscv.h |
19 | +++ b/target/riscv/machine.c | 45 | +++ b/target/riscv/kvm_riscv.h |
20 | @@ -XXX,XX +XXX,XX @@ static bool hyper_needed(void *opaque) | 46 | @@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, |
21 | return riscv_has_ext(env, RVH); | 47 | uint64_t aia_irq_num, uint64_t aia_msi_num, |
48 | uint64_t aplic_base, uint64_t imsic_base, | ||
49 | uint64_t guest_num); | ||
50 | +void riscv_kvm_aplic_request(void *opaque, int irq, int level); | ||
51 | |||
52 | #endif | ||
53 | diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/hw/intc/riscv_aplic.c | ||
56 | +++ b/hw/intc/riscv_aplic.c | ||
57 | @@ -XXX,XX +XXX,XX @@ | ||
58 | #include "target/riscv/cpu.h" | ||
59 | #include "sysemu/sysemu.h" | ||
60 | #include "sysemu/kvm.h" | ||
61 | +#include "kvm_riscv.h" | ||
62 | #include "migration/vmstate.h" | ||
63 | |||
64 | #define APLIC_MAX_IDC (1UL << 14) | ||
65 | @@ -XXX,XX +XXX,XX @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState *aplic, uint32_t idc) | ||
66 | return topi; | ||
22 | } | 67 | } |
23 | 68 | ||
24 | +static bool vector_needed(void *opaque) | 69 | -static void riscv_kvm_aplic_request(void *opaque, int irq, int level) |
70 | -{ | ||
71 | - kvm_set_irq(kvm_state, irq, !!level); | ||
72 | -} | ||
73 | - | ||
74 | static void riscv_aplic_request(void *opaque, int irq, int level) | ||
75 | { | ||
76 | bool update = false; | ||
77 | @@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) | ||
78 | * have IRQ lines delegated by their parent APLIC. | ||
79 | */ | ||
80 | if (!aplic->parent) { | ||
81 | - if (is_kvm_aia(aplic->msimode)) { | ||
82 | + if (kvm_enabled() && is_kvm_aia(aplic->msimode)) { | ||
83 | qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs); | ||
84 | } else { | ||
85 | qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); | ||
86 | diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/target/riscv/kvm.c | ||
89 | +++ b/target/riscv/kvm.c | ||
90 | @@ -XXX,XX +XXX,XX @@ | ||
91 | #include "sysemu/runstate.h" | ||
92 | #include "hw/riscv/numa.h" | ||
93 | |||
94 | +void riscv_kvm_aplic_request(void *opaque, int irq, int level) | ||
25 | +{ | 95 | +{ |
26 | + RISCVCPU *cpu = opaque; | 96 | + kvm_set_irq(kvm_state, irq, !!level); |
27 | + CPURISCVState *env = &cpu->env; | ||
28 | + | ||
29 | + return riscv_has_ext(env, RVV); | ||
30 | +} | 97 | +} |
31 | + | 98 | + |
32 | +static const VMStateDescription vmstate_vector = { | 99 | static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, |
33 | + .name = "cpu/vector", | 100 | uint64_t idx) |
34 | + .version_id = 1, | 101 | { |
35 | + .minimum_version_id = 1, | ||
36 | + .needed = vector_needed, | ||
37 | + .fields = (VMStateField[]) { | ||
38 | + VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), | ||
39 | + VMSTATE_UINTTL(env.vxrm, RISCVCPU), | ||
40 | + VMSTATE_UINTTL(env.vxsat, RISCVCPU), | ||
41 | + VMSTATE_UINTTL(env.vl, RISCVCPU), | ||
42 | + VMSTATE_UINTTL(env.vstart, RISCVCPU), | ||
43 | + VMSTATE_UINTTL(env.vtype, RISCVCPU), | ||
44 | + VMSTATE_END_OF_LIST() | ||
45 | + } | ||
46 | +}; | ||
47 | + | ||
48 | static const VMStateDescription vmstate_hyper = { | ||
49 | .name = "cpu/hyper", | ||
50 | .version_id = 1, | ||
51 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = { | ||
52 | .subsections = (const VMStateDescription * []) { | ||
53 | &vmstate_pmp, | ||
54 | &vmstate_hyper, | ||
55 | + &vmstate_vector, | ||
56 | NULL | ||
57 | } | ||
58 | }; | ||
59 | -- | 102 | -- |
60 | 2.28.0 | 103 | 2.41.0 |
61 | 104 | ||
62 | 105 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Robbin Ehn <rehn@rivosinc.com> | ||
1 | 2 | ||
3 | This patch adds the new extensions in | ||
4 | linux 6.5 to the hwprobe syscall. | ||
5 | |||
6 | And fixes RVC check to OR with correct value. | ||
7 | The previous variable contains 0 therefore it | ||
8 | did work. | ||
9 | |||
10 | Signed-off-by: Robbin Ehn <rehn@rivosinc.com> | ||
11 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Message-ID: <bc82203b72d7efb30f1b4a8f9eb3d94699799dc8.camel@rivosinc.com> | ||
14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
15 | --- | ||
16 | linux-user/syscall.c | 14 +++++++++++++- | ||
17 | 1 file changed, 13 insertions(+), 1 deletion(-) | ||
18 | |||
19 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/linux-user/syscall.c | ||
22 | +++ b/linux-user/syscall.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count) | ||
24 | #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 | ||
25 | #define RISCV_HWPROBE_IMA_FD (1 << 0) | ||
26 | #define RISCV_HWPROBE_IMA_C (1 << 1) | ||
27 | +#define RISCV_HWPROBE_IMA_V (1 << 2) | ||
28 | +#define RISCV_HWPROBE_EXT_ZBA (1 << 3) | ||
29 | +#define RISCV_HWPROBE_EXT_ZBB (1 << 4) | ||
30 | +#define RISCV_HWPROBE_EXT_ZBS (1 << 5) | ||
31 | |||
32 | #define RISCV_HWPROBE_KEY_CPUPERF_0 5 | ||
33 | #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) | ||
34 | @@ -XXX,XX +XXX,XX @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env, | ||
35 | riscv_has_ext(env, RVD) ? | ||
36 | RISCV_HWPROBE_IMA_FD : 0; | ||
37 | value |= riscv_has_ext(env, RVC) ? | ||
38 | - RISCV_HWPROBE_IMA_C : pair->value; | ||
39 | + RISCV_HWPROBE_IMA_C : 0; | ||
40 | + value |= riscv_has_ext(env, RVV) ? | ||
41 | + RISCV_HWPROBE_IMA_V : 0; | ||
42 | + value |= cfg->ext_zba ? | ||
43 | + RISCV_HWPROBE_EXT_ZBA : 0; | ||
44 | + value |= cfg->ext_zbb ? | ||
45 | + RISCV_HWPROBE_EXT_ZBB : 0; | ||
46 | + value |= cfg->ext_zbs ? | ||
47 | + RISCV_HWPROBE_EXT_ZBS : 0; | ||
48 | __put_user(value, &pair->value); | ||
49 | break; | ||
50 | case RISCV_HWPROBE_KEY_CPUPERF_0: | ||
51 | -- | ||
52 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Bin Meng <bin.meng@windriver.com> | 1 | From: Ard Biesheuvel <ardb@kernel.org> |
---|---|---|---|
2 | 2 | ||
3 | Previously SYSREG was created as an unimplemented device. Now that | 3 | Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to |
4 | we have a simple SYSREG module, connect it. | 4 | implement the first half of the key schedule derivation. This does not |
5 | actually involve shifting rows, so clone the same value into all four | ||
6 | columns of the AES vector to counter that operation. | ||
5 | 7 | ||
6 | Signed-off-by: Bin Meng <bin.meng@windriver.com> | 8 | Cc: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Cc: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 1603863010-15807-8-git-send-email-bmeng.cn@gmail.com | 10 | Cc: Palmer Dabbelt <palmer@dabbelt.com> |
11 | Cc: Alistair Francis <alistair.francis@wdc.com> | ||
12 | Signed-off-by: Ard Biesheuvel <ardb@kernel.org> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-ID: <20230831154118.138727-1-ardb@kernel.org> | ||
9 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
10 | --- | 17 | --- |
11 | include/hw/riscv/microchip_pfsoc.h | 2 ++ | 18 | target/riscv/crypto_helper.c | 17 +++++------------ |
12 | hw/riscv/microchip_pfsoc.c | 9 ++++++--- | 19 | 1 file changed, 5 insertions(+), 12 deletions(-) |
13 | hw/riscv/Kconfig | 1 + | ||
14 | 3 files changed, 9 insertions(+), 3 deletions(-) | ||
15 | 20 | ||
16 | diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h | 21 | diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/riscv/microchip_pfsoc.h | 23 | --- a/target/riscv/crypto_helper.c |
19 | +++ b/include/hw/riscv/microchip_pfsoc.h | 24 | +++ b/target/riscv/crypto_helper.c |
20 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum) |
21 | #include "hw/dma/sifive_pdma.h" | 26 | |
22 | #include "hw/misc/mchp_pfsoc_dmc.h" | 27 | uint8_t enc_rnum = rnum; |
23 | #include "hw/misc/mchp_pfsoc_ioscb.h" | 28 | uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF; |
24 | +#include "hw/misc/mchp_pfsoc_sysreg.h" | 29 | - uint8_t rcon_ = 0; |
25 | #include "hw/net/cadence_gem.h" | 30 | - target_ulong result; |
26 | #include "hw/sd/cadence_sdhci.h" | 31 | + AESState t, rc = {}; |
27 | 32 | ||
28 | @@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState { | 33 | if (enc_rnum != 0xA) { |
29 | MchpPfSoCMMUartState *serial2; | 34 | temp = ror32(temp, 8); /* Rotate right by 8 */ |
30 | MchpPfSoCMMUartState *serial3; | 35 | - rcon_ = round_consts[enc_rnum]; |
31 | MchpPfSoCMMUartState *serial4; | 36 | + rc.w[0] = rc.w[1] = round_consts[enc_rnum]; |
32 | + MchpPfSoCSysregState sysreg; | ||
33 | SiFivePDMAState dma; | ||
34 | CadenceGEMState gem0; | ||
35 | CadenceGEMState gem1; | ||
36 | diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/riscv/microchip_pfsoc.c | ||
39 | +++ b/hw/riscv/microchip_pfsoc.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj) | ||
41 | object_initialize_child(obj, "dma-controller", &s->dma, | ||
42 | TYPE_SIFIVE_PDMA); | ||
43 | |||
44 | + object_initialize_child(obj, "sysreg", &s->sysreg, | ||
45 | + TYPE_MCHP_PFSOC_SYSREG); | ||
46 | + | ||
47 | object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, | ||
48 | TYPE_MCHP_PFSOC_DDR_SGMII_PHY); | ||
49 | object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, | ||
50 | @@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) | ||
51 | } | 37 | } |
52 | 38 | ||
53 | /* SYSREG */ | 39 | - temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) | |
54 | - create_unimplemented_device("microchip.pfsoc.sysreg", | 40 | - ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) | |
55 | - memmap[MICROCHIP_PFSOC_SYSREG].base, | 41 | - ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) | |
56 | - memmap[MICROCHIP_PFSOC_SYSREG].size); | 42 | - ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0); |
57 | + sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); | 43 | + t.w[0] = t.w[1] = t.w[2] = t.w[3] = temp; |
58 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, | 44 | + aesenc_SB_SR_AK(&t, &t, &rc, false); |
59 | + memmap[MICROCHIP_PFSOC_SYSREG].base); | 45 | |
60 | 46 | - temp ^= rcon_; | |
61 | /* MPUCFG */ | 47 | - |
62 | create_unimplemented_device("microchip.pfsoc.mpucfg", | 48 | - result = ((uint64_t)temp << 32) | temp; |
63 | diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig | 49 | - |
64 | index XXXXXXX..XXXXXXX 100644 | 50 | - return result; |
65 | --- a/hw/riscv/Kconfig | 51 | + return t.d[0]; |
66 | +++ b/hw/riscv/Kconfig | 52 | } |
67 | @@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC | 53 | |
68 | select MCHP_PFSOC_DMC | 54 | target_ulong HELPER(aes64im)(target_ulong rs1) |
69 | select MCHP_PFSOC_IOSCB | ||
70 | select MCHP_PFSOC_MMUART | ||
71 | + select MCHP_PFSOC_SYSREG | ||
72 | select MSI_NONBROKEN | ||
73 | select SIFIVE_CLINT | ||
74 | select SIFIVE_PDMA | ||
75 | -- | 55 | -- |
76 | 2.28.0 | 56 | 2.41.0 |
77 | 57 | ||
78 | 58 | diff view generated by jsdifflib |
1 | From: Yifei Jiang <jiangyifei@huawei.com> | 1 | From: Akihiko Odaki <akihiko.odaki@daynix.com> |
---|---|---|---|
2 | 2 | ||
3 | In the case of supporting PMP feature, add PMP state description | 3 | riscv_trigger_init() had been called on reset events that can happen |
4 | to vmstate_riscv_cpu. | 4 | several times for a CPU and it allocated timers for itrigger. If old |
5 | timers were present, they were simply overwritten by the new timers, | ||
6 | resulting in a memory leak. | ||
5 | 7 | ||
6 | 'vmstate_pmp_addr' and 'num_rules' could be regenerated by | 8 | Divide riscv_trigger_init() into two functions, namely |
7 | pmp_update_rule(). But there exists the problem of updating | 9 | riscv_trigger_realize() and riscv_trigger_reset() and call them in |
8 | num_rules repeatedly in pmp_update_rule(). So here extracts | 10 | appropriate timing. The timer allocation will happen only once for a |
9 | pmp_update_rule_addr() and pmp_update_rule_nums() to update | 11 | CPU in riscv_trigger_realize(). |
10 | 'vmstate_pmp_addr' and 'num_rules' respectively. | ||
11 | 12 | ||
12 | Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> | 13 | Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled") |
13 | Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> | 14 | Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> |
15 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
16 | Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | ||
14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 17 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
15 | Message-id: 20201026115530.304-4-jiangyifei@huawei.com | 18 | Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com> |
16 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 19 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
17 | --- | 20 | --- |
18 | target/riscv/pmp.h | 2 ++ | 21 | target/riscv/debug.h | 3 ++- |
19 | target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++ | 22 | target/riscv/cpu.c | 8 +++++++- |
20 | target/riscv/pmp.c | 29 ++++++++++++++---------- | 23 | target/riscv/debug.c | 15 ++++++++++++--- |
21 | 3 files changed, 70 insertions(+), 11 deletions(-) | 24 | 3 files changed, 21 insertions(+), 5 deletions(-) |
22 | 25 | ||
23 | diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h | 26 | diff --git a/target/riscv/debug.h b/target/riscv/debug.h |
24 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/riscv/pmp.h | 28 | --- a/target/riscv/debug.h |
26 | +++ b/target/riscv/pmp.h | 29 | +++ b/target/riscv/debug.h |
27 | @@ -XXX,XX +XXX,XX @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, | 30 | @@ -XXX,XX +XXX,XX @@ void riscv_cpu_debug_excp_handler(CPUState *cs); |
28 | target_ulong size, pmp_priv_t priv, target_ulong mode); | 31 | bool riscv_cpu_debug_check_breakpoint(CPUState *cs); |
29 | bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, | 32 | bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); |
30 | target_ulong *tlb_size); | 33 | |
31 | +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); | 34 | -void riscv_trigger_init(CPURISCVState *env); |
32 | +void pmp_update_rule_nums(CPURISCVState *env); | 35 | +void riscv_trigger_realize(CPURISCVState *env); |
33 | 36 | +void riscv_trigger_reset_hold(CPURISCVState *env); | |
34 | #endif | 37 | |
35 | diff --git a/target/riscv/machine.c b/target/riscv/machine.c | 38 | bool riscv_itrigger_enabled(CPURISCVState *env); |
39 | void riscv_itrigger_update_priv(CPURISCVState *env); | ||
40 | diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/target/riscv/machine.c | 42 | --- a/target/riscv/cpu.c |
38 | +++ b/target/riscv/machine.c | 43 | +++ b/target/riscv/cpu.c |
39 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj) |
40 | #include "sysemu/kvm.h" | 45 | |
41 | #include "migration/cpu.h" | 46 | #ifndef CONFIG_USER_ONLY |
42 | 47 | if (cpu->cfg.debug) { | |
43 | +static bool pmp_needed(void *opaque) | 48 | - riscv_trigger_init(env); |
44 | +{ | 49 | + riscv_trigger_reset_hold(env); |
45 | + RISCVCPU *cpu = opaque; | 50 | } |
46 | + CPURISCVState *env = &cpu->env; | 51 | |
52 | if (kvm_enabled()) { | ||
53 | @@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) | ||
54 | |||
55 | riscv_cpu_register_gdb_regs_for_features(cs); | ||
56 | |||
57 | +#ifndef CONFIG_USER_ONLY | ||
58 | + if (cpu->cfg.debug) { | ||
59 | + riscv_trigger_realize(&cpu->env); | ||
60 | + } | ||
61 | +#endif | ||
47 | + | 62 | + |
48 | + return riscv_feature(env, RISCV_FEATURE_PMP); | 63 | qemu_init_vcpu(cs); |
49 | +} | 64 | cpu_reset(cs); |
50 | + | 65 | |
51 | +static int pmp_post_load(void *opaque, int version_id) | 66 | diff --git a/target/riscv/debug.c b/target/riscv/debug.c |
52 | +{ | ||
53 | + RISCVCPU *cpu = opaque; | ||
54 | + CPURISCVState *env = &cpu->env; | ||
55 | + int i; | ||
56 | + | ||
57 | + for (i = 0; i < MAX_RISCV_PMPS; i++) { | ||
58 | + pmp_update_rule_addr(env, i); | ||
59 | + } | ||
60 | + pmp_update_rule_nums(env); | ||
61 | + | ||
62 | + return 0; | ||
63 | +} | ||
64 | + | ||
65 | +static const VMStateDescription vmstate_pmp_entry = { | ||
66 | + .name = "cpu/pmp/entry", | ||
67 | + .version_id = 1, | ||
68 | + .minimum_version_id = 1, | ||
69 | + .fields = (VMStateField[]) { | ||
70 | + VMSTATE_UINTTL(addr_reg, pmp_entry_t), | ||
71 | + VMSTATE_UINT8(cfg_reg, pmp_entry_t), | ||
72 | + VMSTATE_END_OF_LIST() | ||
73 | + } | ||
74 | +}; | ||
75 | + | ||
76 | +static const VMStateDescription vmstate_pmp = { | ||
77 | + .name = "cpu/pmp", | ||
78 | + .version_id = 1, | ||
79 | + .minimum_version_id = 1, | ||
80 | + .needed = pmp_needed, | ||
81 | + .post_load = pmp_post_load, | ||
82 | + .fields = (VMStateField[]) { | ||
83 | + VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, | ||
84 | + 0, vmstate_pmp_entry, pmp_entry_t), | ||
85 | + VMSTATE_END_OF_LIST() | ||
86 | + } | ||
87 | +}; | ||
88 | + | ||
89 | const VMStateDescription vmstate_riscv_cpu = { | ||
90 | .name = "cpu", | ||
91 | .version_id = 1, | ||
92 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = { | ||
93 | VMSTATE_UINT64(env.timecmp, RISCVCPU), | ||
94 | |||
95 | VMSTATE_END_OF_LIST() | ||
96 | + }, | ||
97 | + .subsections = (const VMStateDescription * []) { | ||
98 | + &vmstate_pmp, | ||
99 | + NULL | ||
100 | } | ||
101 | }; | ||
102 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | ||
103 | index XXXXXXX..XXXXXXX 100644 | 67 | index XXXXXXX..XXXXXXX 100644 |
104 | --- a/target/riscv/pmp.c | 68 | --- a/target/riscv/debug.c |
105 | +++ b/target/riscv/pmp.c | 69 | +++ b/target/riscv/debug.c |
106 | @@ -XXX,XX +XXX,XX @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) | 70 | @@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) |
107 | } | 71 | return false; |
108 | } | 72 | } |
109 | 73 | ||
110 | - | 74 | -void riscv_trigger_init(CPURISCVState *env) |
111 | -/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' | 75 | +void riscv_trigger_realize(CPURISCVState *env) |
112 | - * end address values. | ||
113 | - * This function is called relatively infrequently whereas the check that | ||
114 | - * an address is within a pmp rule is called often, so optimise that one | ||
115 | - */ | ||
116 | -static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) | ||
117 | +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) | ||
118 | { | ||
119 | - int i; | ||
120 | - | ||
121 | - env->pmp_state.num_rules = 0; | ||
122 | - | ||
123 | uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg; | ||
124 | target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; | ||
125 | target_ulong prev_addr = 0u; | ||
126 | @@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) | ||
127 | |||
128 | env->pmp_state.addr[pmp_index].sa = sa; | ||
129 | env->pmp_state.addr[pmp_index].ea = ea; | ||
130 | +} | ||
131 | |||
132 | +void pmp_update_rule_nums(CPURISCVState *env) | ||
133 | +{ | 76 | +{ |
134 | + int i; | 77 | + int i; |
135 | + | 78 | + |
136 | + env->pmp_state.num_rules = 0; | 79 | + for (i = 0; i < RV_MAX_TRIGGERS; i++) { |
137 | for (i = 0; i < MAX_RISCV_PMPS; i++) { | 80 | + env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
138 | const uint8_t a_field = | 81 | + riscv_itrigger_timer_cb, env); |
139 | pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); | 82 | + } |
140 | @@ -XXX,XX +XXX,XX @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) | 83 | +} |
84 | + | ||
85 | +void riscv_trigger_reset_hold(CPURISCVState *env) | ||
86 | { | ||
87 | target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); | ||
88 | int i; | ||
89 | @@ -XXX,XX +XXX,XX @@ void riscv_trigger_init(CPURISCVState *env) | ||
90 | env->tdata3[i] = 0; | ||
91 | env->cpu_breakpoint[i] = NULL; | ||
92 | env->cpu_watchpoint[i] = NULL; | ||
93 | - env->itrigger_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL, | ||
94 | - riscv_itrigger_timer_cb, env); | ||
95 | + timer_del(env->itrigger_timer[i]); | ||
141 | } | 96 | } |
142 | } | 97 | } |
143 | |||
144 | +/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' | ||
145 | + * end address values. | ||
146 | + * This function is called relatively infrequently whereas the check that | ||
147 | + * an address is within a pmp rule is called often, so optimise that one | ||
148 | + */ | ||
149 | +static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) | ||
150 | +{ | ||
151 | + pmp_update_rule_addr(env, pmp_index); | ||
152 | + pmp_update_rule_nums(env); | ||
153 | +} | ||
154 | + | ||
155 | static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) | ||
156 | { | ||
157 | int result = 0; | ||
158 | -- | 98 | -- |
159 | 2.28.0 | 99 | 2.41.0 |
160 | 100 | ||
161 | 101 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Leon Schuermann <leons@opentitan.org> | ||
1 | 2 | ||
3 | When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP | ||
4 | configuration lock bits must not apply. While this behavior is | ||
5 | implemented for the pmpcfgX CSRs, this bit is not respected for | ||
6 | changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR | ||
7 | writes work even on locked regions when the global rule-lock bypass is | ||
8 | enabled. | ||
9 | |||
10 | Signed-off-by: Leon Schuermann <leons@opentitan.org> | ||
11 | Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com> | ||
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Message-ID: <20230829215046.1430463-1-leon@is.currently.online> | ||
14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
15 | --- | ||
16 | target/riscv/pmp.c | 4 ++++ | ||
17 | 1 file changed, 4 insertions(+) | ||
18 | |||
19 | diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/riscv/pmp.c | ||
22 | +++ b/target/riscv/pmp.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static inline uint8_t pmp_get_a_field(uint8_t cfg) | ||
24 | */ | ||
25 | static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index) | ||
26 | { | ||
27 | + /* mseccfg.RLB is set */ | ||
28 | + if (MSECCFG_RLB_ISSET(env)) { | ||
29 | + return 0; | ||
30 | + } | ||
31 | |||
32 | if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) { | ||
33 | return 1; | ||
34 | -- | ||
35 | 2.41.0 | diff view generated by jsdifflib |
1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | 1 | From: Tommy Wu <tommy.wu@sifive.com> |
---|---|---|---|
2 | 2 | ||
3 | Fix code style. Space required before the open parenthesis '('. | 3 | According to the new spec, when vsiselect has a reserved value, attempts |
4 | from M-mode or HS-mode to access vsireg, or from VS-mode to access | ||
5 | sireg, should preferably raise an illegal instruction exception. | ||
4 | 6 | ||
5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | 7 | Signed-off-by: Tommy Wu <tommy.wu@sifive.com> |
6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | 8 | Reviewed-by: Frank Chang <frank.chang@sifive.com> |
7 | Reported-by: Euler Robot <euler.robot@huawei.com> | 9 | Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com> |
8 | Reviewed-by: Bin Meng <bin.meng@windriver.com> | ||
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
10 | Message-id: 20201030004815.4172849-1-zhangxinhao1@huawei.com | ||
11 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
12 | --- | 11 | --- |
13 | target/riscv/csr.c | 2 +- | 12 | target/riscv/csr.c | 7 +++++-- |
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 13 | 1 file changed, 5 insertions(+), 2 deletions(-) |
15 | 14 | ||
16 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c | 15 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/riscv/csr.c | 17 | --- a/target/riscv/csr.c |
19 | +++ b/target/riscv/csr.c | 18 | +++ b/target/riscv/csr.c |
20 | @@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) | 19 | @@ -XXX,XX +XXX,XX @@ static int rmw_iprio(target_ulong xlen, |
21 | if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { | 20 | static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, |
22 | return -RISCV_EXCP_ILLEGAL_INST; | 21 | target_ulong new_val, target_ulong wr_mask) |
23 | } else { | 22 | { |
24 | - if((val ^ env->satp) & SATP_ASID) { | 23 | - bool virt; |
25 | + if ((val ^ env->satp) & SATP_ASID) { | 24 | + bool virt, isel_reserved; |
26 | tlb_flush(env_cpu(env)); | 25 | uint8_t *iprio; |
27 | } | 26 | int ret = -EINVAL; |
28 | env->satp = val; | 27 | target_ulong priv, isel, vgein; |
28 | @@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, | ||
29 | |||
30 | /* Decode register details from CSR number */ | ||
31 | virt = false; | ||
32 | + isel_reserved = false; | ||
33 | switch (csrno) { | ||
34 | case CSR_MIREG: | ||
35 | iprio = env->miprio; | ||
36 | @@ -XXX,XX +XXX,XX @@ static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, | ||
37 | riscv_cpu_mxl_bits(env)), | ||
38 | val, new_val, wr_mask); | ||
39 | } | ||
40 | + } else { | ||
41 | + isel_reserved = true; | ||
42 | } | ||
43 | |||
44 | done: | ||
45 | if (ret) { | ||
46 | - return (env->virt_enabled && virt) ? | ||
47 | + return (env->virt_enabled && virt && !isel_reserved) ? | ||
48 | RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; | ||
49 | } | ||
50 | return RISCV_EXCP_NONE; | ||
29 | -- | 51 | -- |
30 | 2.28.0 | 52 | 2.41.0 |
31 | |||
32 | diff view generated by jsdifflib |
1 | From: Anup Patel <anup.patel@wdc.com> | 1 | From: Nikita Shubin <n.shubin@yadro.com> |
---|---|---|---|
2 | 2 | ||
3 | Extend sifive_u machine to allow passing custom DTB using "-dtb" | 3 | As per ISA: |
4 | command-line parameter. This will help users pass modified DTB | ||
5 | or Linux SiFive DTB to sifive_u machine. | ||
6 | 4 | ||
7 | Signed-off-by: Anup Patel <anup.patel@wdc.com> | 5 | "For CSRRWI, if rd=x0, then the instruction shall not read the CSR and |
6 | shall not cause any of the side effects that might occur on a CSR read." | ||
7 | |||
8 | trans_csrrwi() and trans_csrrw() call do_csrw() if rd=x0, do_csrw() calls | ||
9 | riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value. | ||
10 | |||
11 | Signed-off-by: Nikita Shubin <n.shubin@yadro.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
9 | Message-id: 20201022053225.2596110-1-anup.patel@wdc.com | 13 | Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me> |
10 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | 14 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
11 | --- | 15 | --- |
12 | hw/riscv/sifive_u.c | 28 ++++++++++++++++++++-------- | 16 | target/riscv/csr.c | 24 +++++++++++++++--------- |
13 | 1 file changed, 20 insertions(+), 8 deletions(-) | 17 | 1 file changed, 15 insertions(+), 9 deletions(-) |
14 | 18 | ||
15 | diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c | 19 | diff --git a/target/riscv/csr.c b/target/riscv/csr.c |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/riscv/sifive_u.c | 21 | --- a/target/riscv/csr.c |
18 | +++ b/hw/riscv/sifive_u.c | 22 | +++ b/target/riscv/csr.c |
19 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, | 23 | @@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno, |
20 | int cpu; | 24 | target_ulong write_mask) |
21 | uint32_t *cells; | 25 | { |
22 | char *nodename; | 26 | RISCVException ret; |
23 | + const char *dtb_filename; | 27 | - target_ulong old_value; |
24 | char ethclk_names[] = "pclk\0hclk"; | 28 | + target_ulong old_value = 0; |
25 | uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; | 29 | |
26 | uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; | 30 | /* execute combined read/write operation if it exists */ |
27 | 31 | if (csr_ops[csrno].op) { | |
28 | - fdt = s->fdt = create_device_tree(&s->fdt_size); | 32 | return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask); |
29 | - if (!fdt) { | 33 | } |
30 | - error_report("create_device_tree() failed"); | 34 | |
31 | - exit(1); | 35 | - /* if no accessor exists then return failure */ |
32 | + dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); | 36 | - if (!csr_ops[csrno].read) { |
33 | + if (dtb_filename) { | 37 | - return RISCV_EXCP_ILLEGAL_INST; |
34 | + fdt = s->fdt = load_device_tree(dtb_filename, &s->fdt_size); | 38 | - } |
35 | + if (!fdt) { | 39 | - /* read old value */ |
36 | + error_report("load_device_tree() failed"); | 40 | - ret = csr_ops[csrno].read(env, csrno, &old_value); |
37 | + exit(1); | 41 | - if (ret != RISCV_EXCP_NONE) { |
42 | - return ret; | ||
43 | + /* | ||
44 | + * ret_value == NULL means that rd=x0 and we're coming from helper_csrw() | ||
45 | + * and we can't throw side effects caused by CSR reads. | ||
46 | + */ | ||
47 | + if (ret_value) { | ||
48 | + /* if no accessor exists then return failure */ | ||
49 | + if (!csr_ops[csrno].read) { | ||
50 | + return RISCV_EXCP_ILLEGAL_INST; | ||
38 | + } | 51 | + } |
39 | + goto update_bootargs; | 52 | + /* read old value */ |
40 | + } else { | 53 | + ret = csr_ops[csrno].read(env, csrno, &old_value); |
41 | + fdt = s->fdt = create_device_tree(&s->fdt_size); | 54 | + if (ret != RISCV_EXCP_NONE) { |
42 | + if (!fdt) { | 55 | + return ret; |
43 | + error_report("create_device_tree() failed"); | ||
44 | + exit(1); | ||
45 | + } | 56 | + } |
46 | } | 57 | } |
47 | 58 | ||
48 | qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); | 59 | /* write value if writable and write mask set, otherwise drop writes */ |
49 | @@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, | ||
50 | |||
51 | qemu_fdt_add_subnode(fdt, "/chosen"); | ||
52 | qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); | ||
53 | - if (cmdline) { | ||
54 | - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
55 | - } | ||
56 | - | ||
57 | qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); | ||
58 | |||
59 | g_free(nodename); | ||
60 | + | ||
61 | +update_bootargs: | ||
62 | + if (cmdline) { | ||
63 | + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); | ||
64 | + } | ||
65 | } | ||
66 | |||
67 | static void sifive_u_machine_reset(void *opaque, int n, int level) | ||
68 | -- | 60 | -- |
69 | 2.28.0 | 61 | 2.41.0 |
70 | |||
71 | diff view generated by jsdifflib |