1
Small pile of bug fixes for rc1. I've included my patches to get
1
Hi; here's the first arm pullreq for 9.1.
2
our docs building with Sphinx 3, just for convenience...
2
3
3
This includes the reset method function signature change, so it has
4
some chance of compile failures due to merge conflicts if some other
5
pullreq added a device reset method and that pullreq got applied
6
before this one. If so, the changes needed to fix those up can be
7
created by running the spatch rune described in the commit message of
8
the "hw, target: Add ResetType argument to hold and exit phase
9
methods" commit.
10
11
thanks
4
-- PMM
12
-- PMM
5
13
6
The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96:
14
The following changes since commit 5da72194df36535d773c8bdc951529ecd5e31707:
7
15
8
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000)
16
Merge tag 'pull-tcg-20240424' of https://gitlab.com/rth7680/qemu into staging (2024-04-24 15:51:49 -0700)
9
17
10
are available in the Git repository at:
18
are available in the Git repository at:
11
19
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102
20
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240425
13
21
14
for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a:
22
for you to fetch changes up to 214652da123e3821657a64691ee556281e9f6238:
15
23
16
tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000)
24
tests/qtest: Add tests for the STM32L4x5 USART (2024-04-25 10:21:59 +0100)
17
25
18
----------------------------------------------------------------
26
----------------------------------------------------------------
19
target-arm queue:
27
target-arm queue:
20
* target/arm: Fix Neon emulation bugs on big-endian hosts
28
* Implement FEAT_NMI and NMI support in the GICv3
21
* target/arm: fix handling of HCR.FB
29
* hw/dma: avoid apparent overflow in soc_dma_set_request
22
* target/arm: fix LORID_EL1 access check
30
* linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code
23
* disas/capstone: Fix monitor disassembly of >32 bytes
31
* Add ResetType argument to Resettable hold and exit phase methods
24
* hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
32
* Add RESET_TYPE_SNAPSHOT_LOAD ResetType
25
* hw/arm/boot: fix SVE for EL3 direct kernel boot
33
* Implement STM32L4x5 USART
26
* hw/display/omap_lcdc: Fix potential NULL pointer dereference
27
* hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
28
* target/arm: Get correct MMU index for other-security-state
29
* configure: Test that gio libs from pkg-config work
30
* hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
31
* docs: Fix building with Sphinx 3
32
* tests/qtest/npcm7xx_rng-test: Disable randomness tests
33
34
34
----------------------------------------------------------------
35
----------------------------------------------------------------
35
AlexChen (2):
36
Anastasia Belova (1):
36
hw/display/omap_lcdc: Fix potential NULL pointer dereference
37
hw/dma: avoid apparent overflow in soc_dma_set_request
37
hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
38
39
Arnaud Minier (5):
40
hw/char: Implement STM32L4x5 USART skeleton
41
hw/char/stm32l4x5_usart: Enable serial read and write
42
hw/char/stm32l4x5_usart: Add options for serial parameters setting
43
hw/arm: Add the USART to the stm32l4x5 SoC
44
tests/qtest: Add tests for the STM32L4x5 USART
45
46
Jinjie Ruan (22):
47
target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI
48
target/arm: Add PSTATE.ALLINT
49
target/arm: Add support for FEAT_NMI, Non-maskable Interrupt
50
target/arm: Implement ALLINT MSR (immediate)
51
target/arm: Support MSR access to ALLINT
52
target/arm: Add support for Non-maskable Interrupt
53
target/arm: Add support for NMI in arm_phys_excp_target_el()
54
target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI
55
target/arm: Handle PSTATE.ALLINT on taking an exception
56
hw/intc/arm_gicv3: Add external IRQ lines for NMI
57
hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPU
58
target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()
59
hw/intc/arm_gicv3: Add has-nmi property to GICv3 device
60
hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3
61
hw/intc/arm_gicv3: Add irq non-maskable property
62
hw/intc/arm_gicv3_redist: Implement GICR_INMIR0
63
hw/intc/arm_gicv3: Implement GICD_INMIR
64
hw/intc/arm_gicv3: Implement NMI interrupt priority
65
hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()
66
hw/intc/arm_gicv3: Report the VINMI interrupt
67
target/arm: Add FEAT_NMI to max
68
hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI
38
69
39
Peter Maydell (9):
70
Peter Maydell (9):
40
target/arm: Fix float16 pairwise Neon ops on big-endian hosts
71
hw/intc/arm_gicv3: Add NMI handling CPU interface registers
41
target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
72
hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()
42
disas/capstone: Fix monitor disassembly of >32 bytes
73
linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code
43
target/arm: Get correct MMU index for other-security-state
74
hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr
44
configure: Test that gio libs from pkg-config work
75
allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset
45
hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
76
scripts/coccinelle: New script to add ResetType to hold and exit phases
46
scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
77
hw, target: Add ResetType argument to hold and exit phase methods
47
qemu-option-trace.rst.inc: Don't use option:: markup
78
docs/devel/reset: Update to new API for hold and exit phase methods
48
tests/qtest/npcm7xx_rng-test: Disable randomness tests
79
reset: Add RESET_TYPE_SNAPSHOT_LOAD
49
80
50
Philippe Mathieu-Daudé (1):
81
MAINTAINERS | 1 +
51
hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
82
docs/devel/reset.rst | 25 +-
52
83
docs/system/arm/b-l475e-iot01a.rst | 2 +-
53
Richard Henderson (11):
84
docs/system/arm/emulation.rst | 1 +
54
target/arm: Introduce neon_full_reg_offset
85
scripts/coccinelle/reset-type.cocci | 133 ++++++++
55
target/arm: Move neon_element_offset to translate.c
86
hw/intc/gicv3_internal.h | 13 +
56
target/arm: Use neon_element_offset in neon_load/store_reg
87
include/hw/arm/stm32l4x5_soc.h | 7 +
57
target/arm: Use neon_element_offset in vfp_reg_offset
88
include/hw/char/stm32l4x5_usart.h | 67 ++++
58
target/arm: Add read/write_neon_element32
89
include/hw/intc/arm_gic_common.h | 2 +
59
target/arm: Expand read/write_neon_element32 to all MemOp
90
include/hw/intc/arm_gicv3_common.h | 14 +
60
target/arm: Rename neon_load_reg32 to vfp_load_reg32
91
include/hw/resettable.h | 5 +-
61
target/arm: Add read/write_neon_element64
92
linux-user/flat.h | 5 +-
62
target/arm: Rename neon_load_reg64 to vfp_load_reg64
93
target/arm/cpu-features.h | 5 +
63
target/arm: Simplify do_long_3d and do_2scalar_long
94
target/arm/cpu-qom.h | 5 +-
64
target/arm: Improve do_prewiden_3d
95
target/arm/cpu.h | 9 +
65
96
target/arm/internals.h | 21 ++
66
Rémi Denis-Courmont (3):
97
target/arm/tcg/helper-a64.h | 1 +
67
target/arm: fix handling of HCR.FB
98
target/arm/tcg/a64.decode | 1 +
68
target/arm: fix LORID_EL1 access check
99
hw/adc/npcm7xx_adc.c | 2 +-
69
hw/arm/boot: fix SVE for EL3 direct kernel boot
100
hw/arm/pxa2xx_pic.c | 2 +-
70
101
hw/arm/smmu-common.c | 2 +-
71
docs/qemu-option-trace.rst.inc | 6 +-
102
hw/arm/smmuv3.c | 4 +-
72
configure | 10 +-
103
hw/arm/stellaris.c | 10 +-
73
include/hw/intc/arm_gicv3_common.h | 1 -
104
hw/arm/stm32l4x5_soc.c | 83 ++++-
74
disas/capstone.c | 2 +-
105
hw/arm/virt.c | 29 +-
75
hw/arm/boot.c | 3 +
106
hw/audio/asc.c | 2 +-
76
hw/arm/smmuv3.c | 3 +-
107
hw/char/cadence_uart.c | 2 +-
77
hw/display/exynos4210_fimd.c | 4 +-
108
hw/char/sifive_uart.c | 2 +-
78
hw/display/omap_lcdc.c | 10 +-
109
hw/char/stm32l4x5_usart.c | 637 ++++++++++++++++++++++++++++++++++++
79
hw/intc/arm_gicv3_cpuif.c | 5 +-
110
hw/core/cpu-common.c | 2 +-
80
target/arm/helper.c | 24 +-
111
hw/core/qdev.c | 4 +-
81
target/arm/m_helper.c | 3 +-
112
hw/core/reset.c | 17 +-
82
target/arm/translate.c | 153 +++++++++---
113
hw/core/resettable.c | 8 +-
83
target/arm/vec_helper.c | 12 +-
114
hw/display/virtio-vga.c | 4 +-
84
tests/qtest/npcm7xx_rng-test.c | 14 +-
115
hw/dma/soc_dma.c | 4 +-
85
scripts/kernel-doc | 18 +-
116
hw/gpio/npcm7xx_gpio.c | 2 +-
86
target/arm/translate-neon.c.inc | 472 ++++++++++++++++++++-----------------
117
hw/gpio/pl061.c | 2 +-
87
target/arm/translate-vfp.c.inc | 341 +++++++++++----------------
118
hw/gpio/stm32l4x5_gpio.c | 2 +-
88
17 files changed, 588 insertions(+), 493 deletions(-)
119
hw/hyperv/vmbus.c | 2 +-
89
120
hw/i2c/allwinner-i2c.c | 5 +-
121
hw/i2c/npcm7xx_smbus.c | 2 +-
122
hw/input/adb.c | 2 +-
123
hw/input/ps2.c | 12 +-
124
hw/intc/arm_gic_common.c | 2 +-
125
hw/intc/arm_gic_kvm.c | 4 +-
126
hw/intc/arm_gicv3.c | 67 +++-
127
hw/intc/arm_gicv3_common.c | 50 ++-
128
hw/intc/arm_gicv3_cpuif.c | 268 ++++++++++++++-
129
hw/intc/arm_gicv3_dist.c | 36 ++
130
hw/intc/arm_gicv3_its.c | 4 +-
131
hw/intc/arm_gicv3_its_common.c | 2 +-
132
hw/intc/arm_gicv3_its_kvm.c | 4 +-
133
hw/intc/arm_gicv3_kvm.c | 9 +-
134
hw/intc/arm_gicv3_redist.c | 22 ++
135
hw/intc/xics.c | 2 +-
136
hw/m68k/q800-glue.c | 2 +-
137
hw/misc/djmemc.c | 2 +-
138
hw/misc/iosb.c | 2 +-
139
hw/misc/mac_via.c | 8 +-
140
hw/misc/macio/cuda.c | 4 +-
141
hw/misc/macio/pmu.c | 4 +-
142
hw/misc/mos6522.c | 2 +-
143
hw/misc/npcm7xx_clk.c | 13 +-
144
hw/misc/npcm7xx_gcr.c | 12 +-
145
hw/misc/npcm7xx_mft.c | 2 +-
146
hw/misc/npcm7xx_pwm.c | 2 +-
147
hw/misc/stm32l4x5_exti.c | 2 +-
148
hw/misc/stm32l4x5_rcc.c | 10 +-
149
hw/misc/stm32l4x5_syscfg.c | 2 +-
150
hw/misc/xlnx-versal-cframe-reg.c | 2 +-
151
hw/misc/xlnx-versal-crl.c | 2 +-
152
hw/misc/xlnx-versal-pmc-iou-slcr.c | 2 +-
153
hw/misc/xlnx-versal-trng.c | 2 +-
154
hw/misc/xlnx-versal-xramc.c | 2 +-
155
hw/misc/xlnx-zynqmp-apu-ctrl.c | 2 +-
156
hw/misc/xlnx-zynqmp-crf.c | 2 +-
157
hw/misc/zynq_slcr.c | 4 +-
158
hw/net/can/xlnx-zynqmp-can.c | 2 +-
159
hw/net/e1000.c | 2 +-
160
hw/net/e1000e.c | 2 +-
161
hw/net/igb.c | 2 +-
162
hw/net/igbvf.c | 2 +-
163
hw/nvram/xlnx-bbram.c | 2 +-
164
hw/nvram/xlnx-versal-efuse-ctrl.c | 2 +-
165
hw/nvram/xlnx-zynqmp-efuse.c | 2 +-
166
hw/pci-bridge/cxl_root_port.c | 4 +-
167
hw/pci-bridge/pcie_root_port.c | 2 +-
168
hw/pci-host/bonito.c | 2 +-
169
hw/pci-host/pnv_phb.c | 4 +-
170
hw/pci-host/pnv_phb3_msi.c | 4 +-
171
hw/pci/pci.c | 4 +-
172
hw/rtc/mc146818rtc.c | 2 +-
173
hw/s390x/css-bridge.c | 2 +-
174
hw/sensor/adm1266.c | 2 +-
175
hw/sensor/adm1272.c | 4 +-
176
hw/sensor/isl_pmbus_vr.c | 10 +-
177
hw/sensor/max31785.c | 2 +-
178
hw/sensor/max34451.c | 2 +-
179
hw/ssi/npcm7xx_fiu.c | 2 +-
180
hw/timer/etraxfs_timer.c | 2 +-
181
hw/timer/npcm7xx_timer.c | 2 +-
182
hw/usb/hcd-dwc2.c | 8 +-
183
hw/usb/xlnx-versal-usb2-ctrl-regs.c | 2 +-
184
hw/virtio/virtio-pci.c | 2 +-
185
linux-user/flatload.c | 293 +----------------
186
target/arm/cpu.c | 151 ++++++++-
187
target/arm/helper.c | 101 +++++-
188
target/arm/tcg/cpu64.c | 1 +
189
target/arm/tcg/helper-a64.c | 16 +-
190
target/arm/tcg/translate-a64.c | 19 ++
191
target/avr/cpu.c | 4 +-
192
target/cris/cpu.c | 4 +-
193
target/hexagon/cpu.c | 4 +-
194
target/i386/cpu.c | 4 +-
195
target/loongarch/cpu.c | 4 +-
196
target/m68k/cpu.c | 4 +-
197
target/microblaze/cpu.c | 4 +-
198
target/mips/cpu.c | 4 +-
199
target/openrisc/cpu.c | 4 +-
200
target/ppc/cpu_init.c | 4 +-
201
target/riscv/cpu.c | 4 +-
202
target/rx/cpu.c | 4 +-
203
target/sh4/cpu.c | 4 +-
204
target/sparc/cpu.c | 4 +-
205
target/tricore/cpu.c | 4 +-
206
target/xtensa/cpu.c | 4 +-
207
tests/qtest/stm32l4x5_usart-test.c | 315 ++++++++++++++++++
208
hw/arm/Kconfig | 1 +
209
hw/char/Kconfig | 3 +
210
hw/char/meson.build | 1 +
211
hw/char/trace-events | 12 +
212
hw/intc/trace-events | 2 +
213
tests/qtest/meson.build | 4 +-
214
133 files changed, 2239 insertions(+), 537 deletions(-)
215
create mode 100644 scripts/coccinelle/reset-type.cocci
216
create mode 100644 include/hw/char/stm32l4x5_usart.h
217
create mode 100644 hw/char/stm32l4x5_usart.c
218
create mode 100644 tests/qtest/stm32l4x5_usart-test.c
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
The only uses of this function are for loading VFP
3
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and
4
single-precision values, and nothing to do with NEON.
4
HCRX_VFNMI. When the feature is enabled, allow these bits to be written in
5
HCRX_EL2.
5
6
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Message-id: 20201030022618.785675-8-richard.henderson@linaro.org
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20240407081733.3231820-2-ruanjinjie@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/translate.c | 4 +-
13
target/arm/cpu-features.h | 5 +++++
12
target/arm/translate-vfp.c.inc | 184 ++++++++++++++++-----------------
14
target/arm/helper.c | 8 +++++++-
13
2 files changed, 94 insertions(+), 94 deletions(-)
15
2 files changed, 12 insertions(+), 1 deletion(-)
14
16
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
19
--- a/target/arm/cpu-features.h
18
+++ b/target/arm/translate.c
20
+++ b/target/arm/cpu-features.h
19
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg)
21
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
20
tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
22
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
21
}
23
}
22
24
23
-static inline void neon_load_reg32(TCGv_i32 var, int reg)
25
+static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id)
24
+static inline void vfp_load_reg32(TCGv_i32 var, int reg)
26
+{
27
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) != 0;
28
+}
29
+
30
static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
25
{
31
{
26
tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
32
return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
27
}
33
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
34
index XXXXXXX..XXXXXXX 100644
29
-static inline void neon_store_reg32(TCGv_i32 var, int reg)
35
--- a/target/arm/helper.c
30
+static inline void vfp_store_reg32(TCGv_i32 var, int reg)
36
+++ b/target/arm/helper.c
37
@@ -XXX,XX +XXX,XX @@ bool el_is_in_host(CPUARMState *env, int el)
38
static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
39
uint64_t value)
31
{
40
{
32
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
41
+ ARMCPU *cpu = env_archcpu(env);
33
}
42
uint64_t valid_mask = 0;
34
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
43
35
index XXXXXXX..XXXXXXX 100644
44
/* FEAT_MOPS adds MSCEn and MCE2 */
36
--- a/target/arm/translate-vfp.c.inc
45
- if (cpu_isar_feature(aa64_mops, env_archcpu(env))) {
37
+++ b/target/arm/translate-vfp.c.inc
46
+ if (cpu_isar_feature(aa64_mops, cpu)) {
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
47
valid_mask |= HCRX_MSCEN | HCRX_MCE2;
39
frn = tcg_temp_new_i32();
40
frm = tcg_temp_new_i32();
41
dest = tcg_temp_new_i32();
42
- neon_load_reg32(frn, rn);
43
- neon_load_reg32(frm, rm);
44
+ vfp_load_reg32(frn, rn);
45
+ vfp_load_reg32(frm, rm);
46
switch (a->cc) {
47
case 0: /* eq: Z */
48
tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
49
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
50
if (sz == 1) {
51
tcg_gen_andi_i32(dest, dest, 0xffff);
52
}
53
- neon_store_reg32(dest, rd);
54
+ vfp_store_reg32(dest, rd);
55
tcg_temp_free_i32(frn);
56
tcg_temp_free_i32(frm);
57
tcg_temp_free_i32(dest);
58
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
59
TCGv_i32 tcg_res;
60
tcg_op = tcg_temp_new_i32();
61
tcg_res = tcg_temp_new_i32();
62
- neon_load_reg32(tcg_op, rm);
63
+ vfp_load_reg32(tcg_op, rm);
64
if (sz == 1) {
65
gen_helper_rinth(tcg_res, tcg_op, fpst);
66
} else {
67
gen_helper_rints(tcg_res, tcg_op, fpst);
68
}
69
- neon_store_reg32(tcg_res, rd);
70
+ vfp_store_reg32(tcg_res, rd);
71
tcg_temp_free_i32(tcg_op);
72
tcg_temp_free_i32(tcg_res);
73
}
48
}
74
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
49
75
gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
50
+ /* FEAT_NMI adds TALLINT, VINMI and VFNMI */
76
}
51
+ if (cpu_isar_feature(aa64_nmi, cpu)) {
77
tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
52
+ valid_mask |= HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI;
78
- neon_store_reg32(tcg_tmp, rd);
53
+ }
79
+ vfp_store_reg32(tcg_tmp, rd);
54
+
80
tcg_temp_free_i32(tcg_tmp);
55
/* Clear RES0 bits. */
81
tcg_temp_free_i64(tcg_res);
56
env->cp15.hcrx_el2 = value & valid_mask;
82
tcg_temp_free_i64(tcg_double);
83
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
84
TCGv_i32 tcg_single, tcg_res;
85
tcg_single = tcg_temp_new_i32();
86
tcg_res = tcg_temp_new_i32();
87
- neon_load_reg32(tcg_single, rm);
88
+ vfp_load_reg32(tcg_single, rm);
89
if (sz == 1) {
90
if (is_signed) {
91
gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst);
92
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
93
gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
94
}
95
}
96
- neon_store_reg32(tcg_res, rd);
97
+ vfp_store_reg32(tcg_res, rd);
98
tcg_temp_free_i32(tcg_res);
99
tcg_temp_free_i32(tcg_single);
100
}
101
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
102
if (a->l) {
103
/* VFP to general purpose register */
104
tmp = tcg_temp_new_i32();
105
- neon_load_reg32(tmp, a->vn);
106
+ vfp_load_reg32(tmp, a->vn);
107
tcg_gen_andi_i32(tmp, tmp, 0xffff);
108
store_reg(s, a->rt, tmp);
109
} else {
110
/* general purpose register to VFP */
111
tmp = load_reg(s, a->rt);
112
tcg_gen_andi_i32(tmp, tmp, 0xffff);
113
- neon_store_reg32(tmp, a->vn);
114
+ vfp_store_reg32(tmp, a->vn);
115
tcg_temp_free_i32(tmp);
116
}
117
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
119
if (a->l) {
120
/* VFP to general purpose register */
121
tmp = tcg_temp_new_i32();
122
- neon_load_reg32(tmp, a->vn);
123
+ vfp_load_reg32(tmp, a->vn);
124
if (a->rt == 15) {
125
/* Set the 4 flag bits in the CPSR. */
126
gen_set_nzcv(tmp);
127
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
128
} else {
129
/* general purpose register to VFP */
130
tmp = load_reg(s, a->rt);
131
- neon_store_reg32(tmp, a->vn);
132
+ vfp_store_reg32(tmp, a->vn);
133
tcg_temp_free_i32(tmp);
134
}
135
136
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
137
if (a->op) {
138
/* fpreg to gpreg */
139
tmp = tcg_temp_new_i32();
140
- neon_load_reg32(tmp, a->vm);
141
+ vfp_load_reg32(tmp, a->vm);
142
store_reg(s, a->rt, tmp);
143
tmp = tcg_temp_new_i32();
144
- neon_load_reg32(tmp, a->vm + 1);
145
+ vfp_load_reg32(tmp, a->vm + 1);
146
store_reg(s, a->rt2, tmp);
147
} else {
148
/* gpreg to fpreg */
149
tmp = load_reg(s, a->rt);
150
- neon_store_reg32(tmp, a->vm);
151
+ vfp_store_reg32(tmp, a->vm);
152
tcg_temp_free_i32(tmp);
153
tmp = load_reg(s, a->rt2);
154
- neon_store_reg32(tmp, a->vm + 1);
155
+ vfp_store_reg32(tmp, a->vm + 1);
156
tcg_temp_free_i32(tmp);
157
}
158
159
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
160
if (a->op) {
161
/* fpreg to gpreg */
162
tmp = tcg_temp_new_i32();
163
- neon_load_reg32(tmp, a->vm * 2);
164
+ vfp_load_reg32(tmp, a->vm * 2);
165
store_reg(s, a->rt, tmp);
166
tmp = tcg_temp_new_i32();
167
- neon_load_reg32(tmp, a->vm * 2 + 1);
168
+ vfp_load_reg32(tmp, a->vm * 2 + 1);
169
store_reg(s, a->rt2, tmp);
170
} else {
171
/* gpreg to fpreg */
172
tmp = load_reg(s, a->rt);
173
- neon_store_reg32(tmp, a->vm * 2);
174
+ vfp_store_reg32(tmp, a->vm * 2);
175
tcg_temp_free_i32(tmp);
176
tmp = load_reg(s, a->rt2);
177
- neon_store_reg32(tmp, a->vm * 2 + 1);
178
+ vfp_store_reg32(tmp, a->vm * 2 + 1);
179
tcg_temp_free_i32(tmp);
180
}
181
182
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a)
183
tmp = tcg_temp_new_i32();
184
if (a->l) {
185
gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
186
- neon_store_reg32(tmp, a->vd);
187
+ vfp_store_reg32(tmp, a->vd);
188
} else {
189
- neon_load_reg32(tmp, a->vd);
190
+ vfp_load_reg32(tmp, a->vd);
191
gen_aa32_st16(s, tmp, addr, get_mem_index(s));
192
}
193
tcg_temp_free_i32(tmp);
194
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
195
tmp = tcg_temp_new_i32();
196
if (a->l) {
197
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
198
- neon_store_reg32(tmp, a->vd);
199
+ vfp_store_reg32(tmp, a->vd);
200
} else {
201
- neon_load_reg32(tmp, a->vd);
202
+ vfp_load_reg32(tmp, a->vd);
203
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
204
}
205
tcg_temp_free_i32(tmp);
206
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
207
if (a->l) {
208
/* load */
209
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
210
- neon_store_reg32(tmp, a->vd + i);
211
+ vfp_store_reg32(tmp, a->vd + i);
212
} else {
213
/* store */
214
- neon_load_reg32(tmp, a->vd + i);
215
+ vfp_load_reg32(tmp, a->vd + i);
216
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
217
}
218
tcg_gen_addi_i32(addr, addr, offset);
219
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
220
fd = tcg_temp_new_i32();
221
fpst = fpstatus_ptr(FPST_FPCR);
222
223
- neon_load_reg32(f0, vn);
224
- neon_load_reg32(f1, vm);
225
+ vfp_load_reg32(f0, vn);
226
+ vfp_load_reg32(f1, vm);
227
228
for (;;) {
229
if (reads_vd) {
230
- neon_load_reg32(fd, vd);
231
+ vfp_load_reg32(fd, vd);
232
}
233
fn(fd, f0, f1, fpst);
234
- neon_store_reg32(fd, vd);
235
+ vfp_store_reg32(fd, vd);
236
237
if (veclen == 0) {
238
break;
239
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
240
veclen--;
241
vd = vfp_advance_sreg(vd, delta_d);
242
vn = vfp_advance_sreg(vn, delta_d);
243
- neon_load_reg32(f0, vn);
244
+ vfp_load_reg32(f0, vn);
245
if (delta_m) {
246
vm = vfp_advance_sreg(vm, delta_m);
247
- neon_load_reg32(f1, vm);
248
+ vfp_load_reg32(f1, vm);
249
}
250
}
251
252
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn,
253
fd = tcg_temp_new_i32();
254
fpst = fpstatus_ptr(FPST_FPCR_F16);
255
256
- neon_load_reg32(f0, vn);
257
- neon_load_reg32(f1, vm);
258
+ vfp_load_reg32(f0, vn);
259
+ vfp_load_reg32(f1, vm);
260
261
if (reads_vd) {
262
- neon_load_reg32(fd, vd);
263
+ vfp_load_reg32(fd, vd);
264
}
265
fn(fd, f0, f1, fpst);
266
- neon_store_reg32(fd, vd);
267
+ vfp_store_reg32(fd, vd);
268
269
tcg_temp_free_i32(f0);
270
tcg_temp_free_i32(f1);
271
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
272
f0 = tcg_temp_new_i32();
273
fd = tcg_temp_new_i32();
274
275
- neon_load_reg32(f0, vm);
276
+ vfp_load_reg32(f0, vm);
277
278
for (;;) {
279
fn(fd, f0);
280
- neon_store_reg32(fd, vd);
281
+ vfp_store_reg32(fd, vd);
282
283
if (veclen == 0) {
284
break;
285
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
286
/* single source one-many */
287
while (veclen--) {
288
vd = vfp_advance_sreg(vd, delta_d);
289
- neon_store_reg32(fd, vd);
290
+ vfp_store_reg32(fd, vd);
291
}
292
break;
293
}
294
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
295
veclen--;
296
vd = vfp_advance_sreg(vd, delta_d);
297
vm = vfp_advance_sreg(vm, delta_m);
298
- neon_load_reg32(f0, vm);
299
+ vfp_load_reg32(f0, vm);
300
}
301
302
tcg_temp_free_i32(f0);
303
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
304
}
305
306
f0 = tcg_temp_new_i32();
307
- neon_load_reg32(f0, vm);
308
+ vfp_load_reg32(f0, vm);
309
fn(f0, f0);
310
- neon_store_reg32(f0, vd);
311
+ vfp_store_reg32(f0, vd);
312
tcg_temp_free_i32(f0);
313
314
return true;
315
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
316
vm = tcg_temp_new_i32();
317
vd = tcg_temp_new_i32();
318
319
- neon_load_reg32(vn, a->vn);
320
- neon_load_reg32(vm, a->vm);
321
+ vfp_load_reg32(vn, a->vn);
322
+ vfp_load_reg32(vm, a->vm);
323
if (neg_n) {
324
/* VFNMS, VFMS */
325
gen_helper_vfp_negh(vn, vn);
326
}
327
- neon_load_reg32(vd, a->vd);
328
+ vfp_load_reg32(vd, a->vd);
329
if (neg_d) {
330
/* VFNMA, VFNMS */
331
gen_helper_vfp_negh(vd, vd);
332
}
333
fpst = fpstatus_ptr(FPST_FPCR_F16);
334
gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst);
335
- neon_store_reg32(vd, a->vd);
336
+ vfp_store_reg32(vd, a->vd);
337
338
tcg_temp_free_ptr(fpst);
339
tcg_temp_free_i32(vn);
340
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
341
vm = tcg_temp_new_i32();
342
vd = tcg_temp_new_i32();
343
344
- neon_load_reg32(vn, a->vn);
345
- neon_load_reg32(vm, a->vm);
346
+ vfp_load_reg32(vn, a->vn);
347
+ vfp_load_reg32(vm, a->vm);
348
if (neg_n) {
349
/* VFNMS, VFMS */
350
gen_helper_vfp_negs(vn, vn);
351
}
352
- neon_load_reg32(vd, a->vd);
353
+ vfp_load_reg32(vd, a->vd);
354
if (neg_d) {
355
/* VFNMA, VFNMS */
356
gen_helper_vfp_negs(vd, vd);
357
}
358
fpst = fpstatus_ptr(FPST_FPCR);
359
gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
360
- neon_store_reg32(vd, a->vd);
361
+ vfp_store_reg32(vd, a->vd);
362
363
tcg_temp_free_ptr(fpst);
364
tcg_temp_free_i32(vn);
365
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a)
366
}
367
368
fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm));
369
- neon_store_reg32(fd, a->vd);
370
+ vfp_store_reg32(fd, a->vd);
371
tcg_temp_free_i32(fd);
372
return true;
373
}
374
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
375
fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
376
377
for (;;) {
378
- neon_store_reg32(fd, vd);
379
+ vfp_store_reg32(fd, vd);
380
381
if (veclen == 0) {
382
break;
383
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a)
384
vd = tcg_temp_new_i32();
385
vm = tcg_temp_new_i32();
386
387
- neon_load_reg32(vd, a->vd);
388
+ vfp_load_reg32(vd, a->vd);
389
if (a->z) {
390
tcg_gen_movi_i32(vm, 0);
391
} else {
392
- neon_load_reg32(vm, a->vm);
393
+ vfp_load_reg32(vm, a->vm);
394
}
395
396
if (a->e) {
397
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
398
vd = tcg_temp_new_i32();
399
vm = tcg_temp_new_i32();
400
401
- neon_load_reg32(vd, a->vd);
402
+ vfp_load_reg32(vd, a->vd);
403
if (a->z) {
404
tcg_gen_movi_i32(vm, 0);
405
} else {
406
- neon_load_reg32(vm, a->vm);
407
+ vfp_load_reg32(vm, a->vm);
408
}
409
410
if (a->e) {
411
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
412
/* The T bit tells us if we want the low or high 16 bits of Vm */
413
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
414
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
415
- neon_store_reg32(tmp, a->vd);
416
+ vfp_store_reg32(tmp, a->vd);
417
tcg_temp_free_i32(ahp_mode);
418
tcg_temp_free_ptr(fpst);
419
tcg_temp_free_i32(tmp);
420
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
421
ahp_mode = get_ahp_flag();
422
tmp = tcg_temp_new_i32();
423
424
- neon_load_reg32(tmp, a->vm);
425
+ vfp_load_reg32(tmp, a->vm);
426
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
427
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
428
tcg_temp_free_i32(ahp_mode);
429
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a)
430
}
431
432
tmp = tcg_temp_new_i32();
433
- neon_load_reg32(tmp, a->vm);
434
+ vfp_load_reg32(tmp, a->vm);
435
fpst = fpstatus_ptr(FPST_FPCR_F16);
436
gen_helper_rinth(tmp, tmp, fpst);
437
- neon_store_reg32(tmp, a->vd);
438
+ vfp_store_reg32(tmp, a->vd);
439
tcg_temp_free_ptr(fpst);
440
tcg_temp_free_i32(tmp);
441
return true;
442
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
443
}
444
445
tmp = tcg_temp_new_i32();
446
- neon_load_reg32(tmp, a->vm);
447
+ vfp_load_reg32(tmp, a->vm);
448
fpst = fpstatus_ptr(FPST_FPCR);
449
gen_helper_rints(tmp, tmp, fpst);
450
- neon_store_reg32(tmp, a->vd);
451
+ vfp_store_reg32(tmp, a->vd);
452
tcg_temp_free_ptr(fpst);
453
tcg_temp_free_i32(tmp);
454
return true;
455
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
456
}
457
458
tmp = tcg_temp_new_i32();
459
- neon_load_reg32(tmp, a->vm);
460
+ vfp_load_reg32(tmp, a->vm);
461
fpst = fpstatus_ptr(FPST_FPCR_F16);
462
tcg_rmode = tcg_const_i32(float_round_to_zero);
463
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
464
gen_helper_rinth(tmp, tmp, fpst);
465
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
466
- neon_store_reg32(tmp, a->vd);
467
+ vfp_store_reg32(tmp, a->vd);
468
tcg_temp_free_ptr(fpst);
469
tcg_temp_free_i32(tcg_rmode);
470
tcg_temp_free_i32(tmp);
471
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
472
}
473
474
tmp = tcg_temp_new_i32();
475
- neon_load_reg32(tmp, a->vm);
476
+ vfp_load_reg32(tmp, a->vm);
477
fpst = fpstatus_ptr(FPST_FPCR);
478
tcg_rmode = tcg_const_i32(float_round_to_zero);
479
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
480
gen_helper_rints(tmp, tmp, fpst);
481
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
482
- neon_store_reg32(tmp, a->vd);
483
+ vfp_store_reg32(tmp, a->vd);
484
tcg_temp_free_ptr(fpst);
485
tcg_temp_free_i32(tcg_rmode);
486
tcg_temp_free_i32(tmp);
487
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a)
488
}
489
490
tmp = tcg_temp_new_i32();
491
- neon_load_reg32(tmp, a->vm);
492
+ vfp_load_reg32(tmp, a->vm);
493
fpst = fpstatus_ptr(FPST_FPCR_F16);
494
gen_helper_rinth_exact(tmp, tmp, fpst);
495
- neon_store_reg32(tmp, a->vd);
496
+ vfp_store_reg32(tmp, a->vd);
497
tcg_temp_free_ptr(fpst);
498
tcg_temp_free_i32(tmp);
499
return true;
500
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
501
}
502
503
tmp = tcg_temp_new_i32();
504
- neon_load_reg32(tmp, a->vm);
505
+ vfp_load_reg32(tmp, a->vm);
506
fpst = fpstatus_ptr(FPST_FPCR);
507
gen_helper_rints_exact(tmp, tmp, fpst);
508
- neon_store_reg32(tmp, a->vd);
509
+ vfp_store_reg32(tmp, a->vd);
510
tcg_temp_free_ptr(fpst);
511
tcg_temp_free_i32(tmp);
512
return true;
513
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
514
515
vm = tcg_temp_new_i32();
516
vd = tcg_temp_new_i64();
517
- neon_load_reg32(vm, a->vm);
518
+ vfp_load_reg32(vm, a->vm);
519
gen_helper_vfp_fcvtds(vd, vm, cpu_env);
520
neon_store_reg64(vd, a->vd);
521
tcg_temp_free_i32(vm);
522
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
523
vm = tcg_temp_new_i64();
524
neon_load_reg64(vm, a->vm);
525
gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
526
- neon_store_reg32(vd, a->vd);
527
+ vfp_store_reg32(vd, a->vd);
528
tcg_temp_free_i32(vd);
529
tcg_temp_free_i64(vm);
530
return true;
531
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
532
}
533
534
vm = tcg_temp_new_i32();
535
- neon_load_reg32(vm, a->vm);
536
+ vfp_load_reg32(vm, a->vm);
537
fpst = fpstatus_ptr(FPST_FPCR_F16);
538
if (a->s) {
539
/* i32 -> f16 */
540
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
541
/* u32 -> f16 */
542
gen_helper_vfp_uitoh(vm, vm, fpst);
543
}
544
- neon_store_reg32(vm, a->vd);
545
+ vfp_store_reg32(vm, a->vd);
546
tcg_temp_free_i32(vm);
547
tcg_temp_free_ptr(fpst);
548
return true;
549
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
550
}
551
552
vm = tcg_temp_new_i32();
553
- neon_load_reg32(vm, a->vm);
554
+ vfp_load_reg32(vm, a->vm);
555
fpst = fpstatus_ptr(FPST_FPCR);
556
if (a->s) {
557
/* i32 -> f32 */
558
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
559
/* u32 -> f32 */
560
gen_helper_vfp_uitos(vm, vm, fpst);
561
}
562
- neon_store_reg32(vm, a->vd);
563
+ vfp_store_reg32(vm, a->vd);
564
tcg_temp_free_i32(vm);
565
tcg_temp_free_ptr(fpst);
566
return true;
567
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
568
569
vm = tcg_temp_new_i32();
570
vd = tcg_temp_new_i64();
571
- neon_load_reg32(vm, a->vm);
572
+ vfp_load_reg32(vm, a->vm);
573
fpst = fpstatus_ptr(FPST_FPCR);
574
if (a->s) {
575
/* i32 -> f64 */
576
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
577
vd = tcg_temp_new_i32();
578
neon_load_reg64(vm, a->vm);
579
gen_helper_vjcvt(vd, vm, cpu_env);
580
- neon_store_reg32(vd, a->vd);
581
+ vfp_store_reg32(vd, a->vd);
582
tcg_temp_free_i64(vm);
583
tcg_temp_free_i32(vd);
584
return true;
585
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
586
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
587
588
vd = tcg_temp_new_i32();
589
- neon_load_reg32(vd, a->vd);
590
+ vfp_load_reg32(vd, a->vd);
591
592
fpst = fpstatus_ptr(FPST_FPCR_F16);
593
shift = tcg_const_i32(frac_bits);
594
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
595
g_assert_not_reached();
596
}
597
598
- neon_store_reg32(vd, a->vd);
599
+ vfp_store_reg32(vd, a->vd);
600
tcg_temp_free_i32(vd);
601
tcg_temp_free_i32(shift);
602
tcg_temp_free_ptr(fpst);
603
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
604
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
605
606
vd = tcg_temp_new_i32();
607
- neon_load_reg32(vd, a->vd);
608
+ vfp_load_reg32(vd, a->vd);
609
610
fpst = fpstatus_ptr(FPST_FPCR);
611
shift = tcg_const_i32(frac_bits);
612
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
613
g_assert_not_reached();
614
}
615
616
- neon_store_reg32(vd, a->vd);
617
+ vfp_store_reg32(vd, a->vd);
618
tcg_temp_free_i32(vd);
619
tcg_temp_free_i32(shift);
620
tcg_temp_free_ptr(fpst);
621
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
622
623
fpst = fpstatus_ptr(FPST_FPCR_F16);
624
vm = tcg_temp_new_i32();
625
- neon_load_reg32(vm, a->vm);
626
+ vfp_load_reg32(vm, a->vm);
627
628
if (a->s) {
629
if (a->rz) {
630
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
631
gen_helper_vfp_touih(vm, vm, fpst);
632
}
633
}
634
- neon_store_reg32(vm, a->vd);
635
+ vfp_store_reg32(vm, a->vd);
636
tcg_temp_free_i32(vm);
637
tcg_temp_free_ptr(fpst);
638
return true;
639
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
640
641
fpst = fpstatus_ptr(FPST_FPCR);
642
vm = tcg_temp_new_i32();
643
- neon_load_reg32(vm, a->vm);
644
+ vfp_load_reg32(vm, a->vm);
645
646
if (a->s) {
647
if (a->rz) {
648
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
649
gen_helper_vfp_touis(vm, vm, fpst);
650
}
651
}
652
- neon_store_reg32(vm, a->vd);
653
+ vfp_store_reg32(vm, a->vd);
654
tcg_temp_free_i32(vm);
655
tcg_temp_free_ptr(fpst);
656
return true;
657
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
658
gen_helper_vfp_touid(vd, vm, fpst);
659
}
660
}
661
- neon_store_reg32(vd, a->vd);
662
+ vfp_store_reg32(vd, a->vd);
663
tcg_temp_free_i32(vd);
664
tcg_temp_free_i64(vm);
665
tcg_temp_free_ptr(fpst);
666
@@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a)
667
/* Insert low half of Vm into high half of Vd */
668
rm = tcg_temp_new_i32();
669
rd = tcg_temp_new_i32();
670
- neon_load_reg32(rm, a->vm);
671
- neon_load_reg32(rd, a->vd);
672
+ vfp_load_reg32(rm, a->vm);
673
+ vfp_load_reg32(rd, a->vd);
674
tcg_gen_deposit_i32(rd, rd, rm, 16, 16);
675
- neon_store_reg32(rd, a->vd);
676
+ vfp_store_reg32(rd, a->vd);
677
tcg_temp_free_i32(rm);
678
tcg_temp_free_i32(rd);
679
return true;
680
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a)
681
682
/* Set Vd to high half of Vm */
683
rm = tcg_temp_new_i32();
684
- neon_load_reg32(rm, a->vm);
685
+ vfp_load_reg32(rm, a->vm);
686
tcg_gen_shri_i32(rm, rm, 16);
687
- neon_store_reg32(rm, a->vd);
688
+ vfp_store_reg32(rm, a->vd);
689
tcg_temp_free_i32(rm);
690
return true;
691
}
57
}
692
--
58
--
693
2.20.1
59
2.34.1
694
695
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to
4
ELx, with or without superpriority is masked. As Richard suggested, place
5
ALLINT bit in PSTATE in env->pstate.
6
7
In the pseudocode, AArch64.ExceptionReturn() calls SetPSTATEFromPSR(), which
8
treats PSTATE.ALLINT as one of the bits which are reinstated from SPSR to
9
PSTATE regardless of whether this is an illegal exception return or not. So
10
handle PSTATE.ALLINT the same way as PSTATE.DAIF in the illegal_return exit
11
path of the exception_return helper. With the change, exception entry and
12
return are automatically handled.
13
14
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20240407081733.3231820-3-ruanjinjie@huawei.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/cpu.h | 1 +
21
target/arm/tcg/helper-a64.c | 4 ++--
22
2 files changed, 3 insertions(+), 2 deletions(-)
23
24
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpu.h
27
+++ b/target/arm/cpu.h
28
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
29
#define PSTATE_D (1U << 9)
30
#define PSTATE_BTYPE (3U << 10)
31
#define PSTATE_SSBS (1U << 12)
32
+#define PSTATE_ALLINT (1U << 13)
33
#define PSTATE_IL (1U << 20)
34
#define PSTATE_SS (1U << 21)
35
#define PSTATE_PAN (1U << 22)
36
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/tcg/helper-a64.c
39
+++ b/target/arm/tcg/helper-a64.c
40
@@ -XXX,XX +XXX,XX @@ illegal_return:
41
*/
42
env->pstate |= PSTATE_IL;
43
env->pc = new_pc;
44
- spsr &= PSTATE_NZCV | PSTATE_DAIF;
45
- spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
46
+ spsr &= PSTATE_NZCV | PSTATE_DAIF | PSTATE_ALLINT;
47
+ spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF | PSTATE_ALLINT);
48
pstate_write(env, spsr);
49
if (!arm_singlestep_active(env)) {
50
env->pstate &= ~PSTATE_SS;
51
--
52
2.34.1
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in
4
ARMv8.8-A and ARM v9.3-A.
5
6
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20240407081733.3231820-4-ruanjinjie@huawei.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/internals.h | 3 +++
13
1 file changed, 3 insertions(+)
14
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
18
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
20
if (isar_feature_aa64_mte(id)) {
21
valid |= PSTATE_TCO;
22
}
23
+ if (isar_feature_aa64_nmi(id)) {
24
+ valid |= PSTATE_ALLINT;
25
+ }
26
27
return valid;
28
}
29
--
30
2.34.1
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
This function makes it clear that we're talking about the whole
3
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The
4
register, and not the 32-bit piece at index 0. This fixes a bug
4
EL0 check is necessary to ALLINT, and the EL1 check is necessary when
5
when running on a big-endian host.
5
imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the
6
unconditional write to pc and use raise_exception_ra to unwind.
6
7
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
8
Message-id: 20201030022618.785675-2-richard.henderson@linaro.org
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20240407081733.3231820-5-ruanjinjie@huawei.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/translate.c | 8 ++++++
14
target/arm/tcg/helper-a64.h | 1 +
13
target/arm/translate-neon.c.inc | 44 ++++++++++++++++-----------------
15
target/arm/tcg/a64.decode | 1 +
14
target/arm/translate-vfp.c.inc | 2 +-
16
target/arm/tcg/helper-a64.c | 12 ++++++++++++
15
3 files changed, 31 insertions(+), 23 deletions(-)
17
target/arm/tcg/translate-a64.c | 19 +++++++++++++++++++
18
4 files changed, 33 insertions(+)
16
19
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
20
diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate.c
22
--- a/target/arm/tcg/helper-a64.h
20
+++ b/target/arm/translate.c
23
+++ b/target/arm/tcg/helper-a64.h
21
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
24
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
22
unallocated_encoding(s);
25
DEF_HELPER_2(msr_i_spsel, void, env, i32)
26
DEF_HELPER_2(msr_i_daifset, void, env, i32)
27
DEF_HELPER_2(msr_i_daifclear, void, env, i32)
28
+DEF_HELPER_1(msr_set_allint_el1, void, env)
29
DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
30
DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
31
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
32
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/tcg/a64.decode
35
+++ b/target/arm/tcg/a64.decode
36
@@ -XXX,XX +XXX,XX @@ MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i
37
MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i
38
MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i
39
MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i
40
+MSR_i_ALLINT 1101 0101 0000 0 001 0100 000 imm:1 000 11111
41
MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
42
43
# MRS, MSR (register), SYS, SYSL. These are all essentially the
44
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/tcg/helper-a64.c
47
+++ b/target/arm/tcg/helper-a64.c
48
@@ -XXX,XX +XXX,XX @@ void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm)
49
update_spsel(env, imm);
23
}
50
}
24
51
25
+/*
52
+void HELPER(msr_set_allint_el1)(CPUARMState *env)
26
+ * Return the offset of a "full" NEON Dreg.
27
+ */
28
+static long neon_full_reg_offset(unsigned reg)
29
+{
53
+{
30
+ return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
54
+ /* ALLINT update to PSTATE. */
55
+ if (arm_hcrx_el2_eff(env) & HCRX_TALLINT) {
56
+ raise_exception_ra(env, EXCP_UDEF,
57
+ syn_aa64_sysregtrap(0, 1, 0, 4, 1, 0x1f, 0), 2,
58
+ GETPC());
59
+ }
60
+
61
+ env->pstate |= PSTATE_ALLINT;
31
+}
62
+}
32
+
63
+
33
static inline long vfp_reg_offset(bool dp, unsigned reg)
64
static void daif_check(CPUARMState *env, uint32_t op,
65
uint32_t imm, uintptr_t ra)
34
{
66
{
35
if (dp) {
67
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
36
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
37
index XXXXXXX..XXXXXXX 100644
68
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/translate-neon.c.inc
69
--- a/target/arm/tcg/translate-a64.c
39
+++ b/target/arm/translate-neon.c.inc
70
+++ b/target/arm/tcg/translate-a64.c
40
@@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size)
71
@@ -XXX,XX +XXX,XX @@ static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a)
41
ofs ^= 8 - element_size;
42
}
43
#endif
44
- return neon_reg_offset(reg, 0) + ofs;
45
+ return neon_full_reg_offset(reg) + ofs;
46
}
47
48
static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
49
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
50
* We cannot write 16 bytes at once because the
51
* destination is unaligned.
52
*/
53
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
54
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
55
8, 8, tmp);
56
- tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
57
- neon_reg_offset(vd, 0), 8, 8);
58
+ tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1),
59
+ neon_full_reg_offset(vd), 8, 8);
60
} else {
61
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
62
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
63
vec_size, vec_size, tmp);
64
}
65
tcg_gen_addi_i32(addr, addr, 1 << size);
66
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
67
static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
68
{
69
int vec_size = a->q ? 16 : 8;
70
- int rd_ofs = neon_reg_offset(a->vd, 0);
71
- int rn_ofs = neon_reg_offset(a->vn, 0);
72
- int rm_ofs = neon_reg_offset(a->vm, 0);
73
+ int rd_ofs = neon_full_reg_offset(a->vd);
74
+ int rn_ofs = neon_full_reg_offset(a->vn);
75
+ int rm_ofs = neon_full_reg_offset(a->vm);
76
77
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
78
return false;
79
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
80
{
81
/* Handle a 2-reg-shift insn which can be vectorized. */
82
int vec_size = a->q ? 16 : 8;
83
- int rd_ofs = neon_reg_offset(a->vd, 0);
84
- int rm_ofs = neon_reg_offset(a->vm, 0);
85
+ int rd_ofs = neon_full_reg_offset(a->vd);
86
+ int rm_ofs = neon_full_reg_offset(a->vm);
87
88
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
89
return false;
90
@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
91
{
92
/* FP operations in 2-reg-and-shift group */
93
int vec_size = a->q ? 16 : 8;
94
- int rd_ofs = neon_reg_offset(a->vd, 0);
95
- int rm_ofs = neon_reg_offset(a->vm, 0);
96
+ int rd_ofs = neon_full_reg_offset(a->vd);
97
+ int rm_ofs = neon_full_reg_offset(a->vm);
98
TCGv_ptr fpst;
99
100
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
101
@@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
102
return true;
103
}
104
105
- reg_ofs = neon_reg_offset(a->vd, 0);
106
+ reg_ofs = neon_full_reg_offset(a->vd);
107
vec_size = a->q ? 16 : 8;
108
imm = asimd_imm_const(a->imm, a->cmode, a->op);
109
110
@@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
111
return true;
112
}
113
114
- tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0),
115
- neon_reg_offset(a->vn, 0),
116
- neon_reg_offset(a->vm, 0),
117
+ tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd),
118
+ neon_full_reg_offset(a->vn),
119
+ neon_full_reg_offset(a->vm),
120
16, 16, 0, fn_gvec);
121
return true;
72
return true;
122
}
73
}
123
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
74
75
+static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a)
76
+{
77
+ if (!dc_isar_feature(aa64_nmi, s) || s->current_el == 0) {
78
+ return false;
79
+ }
80
+
81
+ if (a->imm == 0) {
82
+ clear_pstate_bits(PSTATE_ALLINT);
83
+ } else if (s->current_el > 1) {
84
+ set_pstate_bits(PSTATE_ALLINT);
85
+ } else {
86
+ gen_helper_msr_set_allint_el1(tcg_env);
87
+ }
88
+
89
+ /* Exit the cpu loop to re-evaluate pending IRQs. */
90
+ s->base.is_jmp = DISAS_UPDATE_EXIT;
91
+ return true;
92
+}
93
+
94
static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a)
124
{
95
{
125
/* Two registers and a scalar, using gvec */
96
if (!dc_isar_feature(aa64_sme, s) || a->mask == 0) {
126
int vec_size = a->q ? 16 : 8;
127
- int rd_ofs = neon_reg_offset(a->vd, 0);
128
- int rn_ofs = neon_reg_offset(a->vn, 0);
129
+ int rd_ofs = neon_full_reg_offset(a->vd);
130
+ int rn_ofs = neon_full_reg_offset(a->vn);
131
int rm_ofs;
132
int idx;
133
TCGv_ptr fpstatus;
134
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
135
/* a->vm is M:Vm, which encodes both register and index */
136
idx = extract32(a->vm, a->size + 2, 2);
137
a->vm = extract32(a->vm, 0, a->size + 2);
138
- rm_ofs = neon_reg_offset(a->vm, 0);
139
+ rm_ofs = neon_full_reg_offset(a->vm);
140
141
fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD);
142
tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus,
143
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
144
return true;
145
}
146
147
- tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0),
148
+ tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd),
149
neon_element_offset(a->vm, a->index, a->size),
150
a->q ? 16 : 8, a->q ? 16 : 8);
151
return true;
152
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
153
static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
154
{
155
int vec_size = a->q ? 16 : 8;
156
- int rd_ofs = neon_reg_offset(a->vd, 0);
157
- int rm_ofs = neon_reg_offset(a->vm, 0);
158
+ int rd_ofs = neon_full_reg_offset(a->vd);
159
+ int rm_ofs = neon_full_reg_offset(a->vm);
160
161
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
162
return false;
163
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
164
index XXXXXXX..XXXXXXX 100644
165
--- a/target/arm/translate-vfp.c.inc
166
+++ b/target/arm/translate-vfp.c.inc
167
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
168
}
169
170
tmp = load_reg(s, a->rt);
171
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
172
+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn),
173
vec_size, vec_size, tmp);
174
tcg_temp_free_i32(tmp);
175
176
--
97
--
177
2.20.1
98
2.34.1
178
179
diff view generated by jsdifflib
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
Secure mode is not exempted from checking SCR_EL3.TLOR, and in the
3
Support ALLINT msr access as follow:
4
future HCR_EL2.TLOR when S-EL2 is enabled.
4
    mrs <xt>, ALLINT    // read allint
5
    msr ALLINT, <xt>    // write allint with imm
5
6
6
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
7
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20240407081733.3231820-6-ruanjinjie@huawei.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/helper.c | 19 +++++--------------
13
target/arm/helper.c | 35 +++++++++++++++++++++++++++++++++++
11
1 file changed, 5 insertions(+), 14 deletions(-)
14
1 file changed, 35 insertions(+)
12
15
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
18
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
19
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo rme_mte_reginfo[] = {
21
.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 5,
22
.access = PL3_W, .type = ARM_CP_NOP },
23
};
24
+
25
+static void aa64_allint_write(CPUARMState *env, const ARMCPRegInfo *ri,
26
+ uint64_t value)
27
+{
28
+ env->pstate = (env->pstate & ~PSTATE_ALLINT) | (value & PSTATE_ALLINT);
29
+}
30
+
31
+static uint64_t aa64_allint_read(CPUARMState *env, const ARMCPRegInfo *ri)
32
+{
33
+ return env->pstate & PSTATE_ALLINT;
34
+}
35
+
36
+static CPAccessResult aa64_allint_access(CPUARMState *env,
37
+ const ARMCPRegInfo *ri, bool isread)
38
+{
39
+ if (!isread && arm_current_el(env) == 1 &&
40
+ (arm_hcrx_el2_eff(env) & HCRX_TALLINT)) {
41
+ return CP_ACCESS_TRAP_EL2;
42
+ }
43
+ return CP_ACCESS_OK;
44
+}
45
+
46
+static const ARMCPRegInfo nmi_reginfo[] = {
47
+ { .name = "ALLINT", .state = ARM_CP_STATE_AA64,
48
+ .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 4, .crm = 3,
49
+ .type = ARM_CP_NO_RAW,
50
+ .access = PL1_RW, .accessfn = aa64_allint_access,
51
+ .fieldoffset = offsetof(CPUARMState, pstate),
52
+ .writefn = aa64_allint_write, .readfn = aa64_allint_read,
53
+ .resetfn = arm_cp_reset_ignore },
54
+};
55
#endif /* TARGET_AARCH64 */
56
57
static void define_pmu_regs(ARMCPU *cpu)
58
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
59
if (cpu_isar_feature(aa64_nv2, cpu)) {
60
define_arm_cp_regs(cpu, nv2_reginfo);
61
}
62
+
63
+ if (cpu_isar_feature(aa64_nmi, cpu)) {
64
+ define_arm_cp_regs(cpu, nmi_reginfo);
65
+ }
18
#endif
66
#endif
19
67
20
/* Shared logic between LORID and the rest of the LOR* registers.
68
if (cpu_isar_feature(any_predinv, cpu)) {
21
- * Secure state has already been delt with.
22
+ * Secure state exclusion has already been dealt with.
23
*/
24
-static CPAccessResult access_lor_ns(CPUARMState *env)
25
+static CPAccessResult access_lor_ns(CPUARMState *env,
26
+ const ARMCPRegInfo *ri, bool isread)
27
{
28
int el = arm_current_el(env);
29
30
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env)
31
return CP_ACCESS_OK;
32
}
33
34
-static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,
35
- bool isread)
36
-{
37
- if (arm_is_secure_below_el3(env)) {
38
- /* Access ok in secure mode. */
39
- return CP_ACCESS_OK;
40
- }
41
- return access_lor_ns(env);
42
-}
43
-
44
static CPAccessResult access_lor_other(CPUARMState *env,
45
const ARMCPRegInfo *ri, bool isread)
46
{
47
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env,
48
/* Access denied in secure mode. */
49
return CP_ACCESS_TRAP;
50
}
51
- return access_lor_ns(env);
52
+ return access_lor_ns(env, ri, isread);
53
}
54
55
/*
56
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
57
.type = ARM_CP_CONST, .resetvalue = 0 },
58
{ .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
59
.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
60
- .access = PL1_R, .accessfn = access_lorid,
61
+ .access = PL1_R, .accessfn = access_lor_ns,
62
.type = ARM_CP_CONST, .resetvalue = 0 },
63
REGINFO_SENTINEL
64
};
65
--
69
--
66
2.20.1
70
2.34.1
67
68
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
We can use proper widening loads to extend 32-bit inputs,
3
This only implements the external delivery method via the GICv3.
4
and skip the "widenfn" step.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Message-id: 20201030022618.785675-12-richard.henderson@linaro.org
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20240407081733.3231820-7-ruanjinjie@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate.c | 6 +++
11
target/arm/cpu-qom.h | 5 +-
12
target/arm/translate-neon.c.inc | 66 ++++++++++++++++++---------------
12
target/arm/cpu.h | 6 ++
13
2 files changed, 43 insertions(+), 29 deletions(-)
13
target/arm/internals.h | 18 +++++
14
target/arm/cpu.c | 147 ++++++++++++++++++++++++++++++++++++++---
15
target/arm/helper.c | 33 +++++++--
16
5 files changed, 193 insertions(+), 16 deletions(-)
14
17
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
20
--- a/target/arm/cpu-qom.h
18
+++ b/target/arm/translate.c
21
+++ b/target/arm/cpu-qom.h
19
@@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
22
@@ -XXX,XX +XXX,XX @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
20
long off = neon_element_offset(reg, ele, memop);
23
#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
21
24
#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
22
switch (memop) {
25
23
+ case MO_SL:
26
-/* Meanings of the ARMCPU object's four inbound GPIO lines */
24
+ tcg_gen_ld32s_i64(dest, cpu_env, off);
27
+/* Meanings of the ARMCPU object's seven inbound GPIO lines */
25
+ break;
28
#define ARM_CPU_IRQ 0
26
+ case MO_UL:
29
#define ARM_CPU_FIQ 1
27
+ tcg_gen_ld32u_i64(dest, cpu_env, off);
30
#define ARM_CPU_VIRQ 2
28
+ break;
31
#define ARM_CPU_VFIQ 3
29
case MO_Q:
32
+#define ARM_CPU_NMI 4
30
tcg_gen_ld_i64(dest, cpu_env, off);
33
+#define ARM_CPU_VINMI 5
31
break;
34
+#define ARM_CPU_VFNMI 6
32
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
35
36
/* For M profile, some registers are banked secure vs non-secure;
37
* these are represented as a 2-element array where the first element
38
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
33
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate-neon.c.inc
40
--- a/target/arm/cpu.h
35
+++ b/target/arm/translate-neon.c.inc
41
+++ b/target/arm/cpu.h
36
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
42
@@ -XXX,XX +XXX,XX @@
37
static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
43
#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
38
NeonGenWidenFn *widenfn,
44
#define EXCP_VSERR 24
39
NeonGenTwo64OpFn *opfn,
45
#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */
40
- bool src1_wide)
46
+#define EXCP_NMI 26
41
+ int src1_mop, int src2_mop)
47
+#define EXCP_VINMI 27
48
+#define EXCP_VFNMI 28
49
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
50
51
#define ARMV7M_EXCP_RESET 1
52
@@ -XXX,XX +XXX,XX @@
53
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
54
#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
55
#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
56
+#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_4
57
+#define CPU_INTERRUPT_VINMI CPU_INTERRUPT_TGT_EXT_0
58
+#define CPU_INTERRUPT_VFNMI CPU_INTERRUPT_TGT_INT_1
59
60
/* The usual mapping for an AArch64 system register to its AArch32
61
* counterpart is for the 32 bit world to have access to the lower
62
diff --git a/target/arm/internals.h b/target/arm/internals.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/internals.h
65
+++ b/target/arm/internals.h
66
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
67
*/
68
void arm_cpu_update_vfiq(ARMCPU *cpu);
69
70
+/**
71
+ * arm_cpu_update_vinmi: Update CPU_INTERRUPT_VINMI bit in cs->interrupt_request
72
+ *
73
+ * Update the CPU_INTERRUPT_VINMI bit in cs->interrupt_request, following
74
+ * a change to either the input VNMI line from the GIC or the HCRX_EL2.VINMI.
75
+ * Must be called with the BQL held.
76
+ */
77
+void arm_cpu_update_vinmi(ARMCPU *cpu);
78
+
79
+/**
80
+ * arm_cpu_update_vfnmi: Update CPU_INTERRUPT_VFNMI bit in cs->interrupt_request
81
+ *
82
+ * Update the CPU_INTERRUPT_VFNMI bit in cs->interrupt_request, following
83
+ * a change to the HCRX_EL2.VFNMI.
84
+ * Must be called with the BQL held.
85
+ */
86
+void arm_cpu_update_vfnmi(ARMCPU *cpu);
87
+
88
/**
89
* arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
90
*
91
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/arm/cpu.c
94
+++ b/target/arm/cpu.c
95
@@ -XXX,XX +XXX,XX @@ void arm_restore_state_to_opc(CPUState *cs,
96
}
97
#endif /* CONFIG_TCG */
98
99
+/*
100
+ * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with
101
+ * IRQ without Superpriority. Moreover, if the GIC is configured so that
102
+ * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see
103
+ * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
104
+ * unconditionally.
105
+ */
106
static bool arm_cpu_has_work(CPUState *cs)
42
{
107
{
43
/* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */
108
ARMCPU *cpu = ARM_CPU(cs);
44
TCGv_i64 rn0_64, rn1_64, rm_64;
109
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
45
- TCGv_i32 rm;
110
return (cpu->power_state != PSCI_OFF)
46
111
&& cs->interrupt_request &
47
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
112
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
48
return false;
113
+ | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI
49
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
114
| CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
115
| CPU_INTERRUPT_EXITTB);
116
}
117
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
118
CPUARMState *env = cpu_env(cs);
119
bool pstate_unmasked;
120
bool unmasked = false;
121
+ bool allIntMask = false;
122
123
/*
124
* Don't take exceptions if they target a lower EL.
125
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
50
return false;
126
return false;
51
}
127
}
52
128
53
- if (!widenfn || !opfn) {
129
+ if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
54
+ if (!opfn) {
130
+ env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) {
55
/* size == 3 case, which is an entirely different insn group */
131
+ allIntMask = env->pstate & PSTATE_ALLINT ||
56
return false;
132
+ ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) &&
133
+ (env->pstate & PSTATE_SP));
134
+ }
135
+
136
switch (excp_idx) {
137
+ case EXCP_NMI:
138
+ pstate_unmasked = !allIntMask;
139
+ break;
140
+
141
+ case EXCP_VINMI:
142
+ if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
143
+ /* VINMIs are only taken when hypervized. */
144
+ return false;
145
+ }
146
+ return !allIntMask;
147
+ case EXCP_VFNMI:
148
+ if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
149
+ /* VFNMIs are only taken when hypervized. */
150
+ return false;
151
+ }
152
+ return !allIntMask;
153
case EXCP_FIQ:
154
- pstate_unmasked = !(env->daif & PSTATE_F);
155
+ pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask);
156
break;
157
158
case EXCP_IRQ:
159
- pstate_unmasked = !(env->daif & PSTATE_I);
160
+ pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask);
161
break;
162
163
case EXCP_VFIQ:
164
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
165
/* VFIQs are only taken when hypervized. */
166
return false;
167
}
168
- return !(env->daif & PSTATE_F);
169
+ return !(env->daif & PSTATE_F) && (!allIntMask);
170
case EXCP_VIRQ:
171
if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
172
/* VIRQs are only taken when hypervized. */
173
return false;
174
}
175
- return !(env->daif & PSTATE_I);
176
+ return !(env->daif & PSTATE_I) && (!allIntMask);
177
case EXCP_VSERR:
178
if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
179
/* VIRQs are only taken when hypervized. */
180
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
181
182
/* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
183
184
+ if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
185
+ (arm_sctlr(env, cur_el) & SCTLR_NMI)) {
186
+ if (interrupt_request & CPU_INTERRUPT_NMI) {
187
+ excp_idx = EXCP_NMI;
188
+ target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
189
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
190
+ cur_el, secure, hcr_el2)) {
191
+ goto found;
192
+ }
193
+ }
194
+ if (interrupt_request & CPU_INTERRUPT_VINMI) {
195
+ excp_idx = EXCP_VINMI;
196
+ target_el = 1;
197
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
198
+ cur_el, secure, hcr_el2)) {
199
+ goto found;
200
+ }
201
+ }
202
+ if (interrupt_request & CPU_INTERRUPT_VFNMI) {
203
+ excp_idx = EXCP_VFNMI;
204
+ target_el = 1;
205
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
206
+ cur_el, secure, hcr_el2)) {
207
+ goto found;
208
+ }
209
+ }
210
+ } else {
211
+ /*
212
+ * NMI disabled: interrupts with superpriority are handled
213
+ * as if they didn't have it
214
+ */
215
+ if (interrupt_request & CPU_INTERRUPT_NMI) {
216
+ interrupt_request |= CPU_INTERRUPT_HARD;
217
+ }
218
+ if (interrupt_request & CPU_INTERRUPT_VINMI) {
219
+ interrupt_request |= CPU_INTERRUPT_VIRQ;
220
+ }
221
+ if (interrupt_request & CPU_INTERRUPT_VFNMI) {
222
+ interrupt_request |= CPU_INTERRUPT_VFIQ;
223
+ }
224
+ }
225
+
226
if (interrupt_request & CPU_INTERRUPT_FIQ) {
227
excp_idx = EXCP_FIQ;
228
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
229
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu)
230
CPUARMState *env = &cpu->env;
231
CPUState *cs = CPU(cpu);
232
233
- bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
234
+ bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
235
+ !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
236
(env->irq_line_state & CPU_INTERRUPT_VIRQ);
237
238
if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
239
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
240
CPUARMState *env = &cpu->env;
241
CPUState *cs = CPU(cpu);
242
243
- bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
244
+ bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) &&
245
+ !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) ||
246
(env->irq_line_state & CPU_INTERRUPT_VFIQ);
247
248
if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
249
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
57
}
250
}
58
251
}
59
- if ((a->vd & 1) || (src1_wide && (a->vn & 1))) {
252
60
+ if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) {
253
+void arm_cpu_update_vinmi(ARMCPU *cpu)
61
return false;
254
+{
255
+ /*
256
+ * Update the interrupt level for VINMI, which is the logical OR of
257
+ * the HCRX_EL2.VINMI bit and the input line level from the GIC.
258
+ */
259
+ CPUARMState *env = &cpu->env;
260
+ CPUState *cs = CPU(cpu);
261
+
262
+ bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
263
+ (arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
264
+ (env->irq_line_state & CPU_INTERRUPT_VINMI);
265
+
266
+ if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) {
267
+ if (new_state) {
268
+ cpu_interrupt(cs, CPU_INTERRUPT_VINMI);
269
+ } else {
270
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI);
271
+ }
272
+ }
273
+}
274
+
275
+void arm_cpu_update_vfnmi(ARMCPU *cpu)
276
+{
277
+ /*
278
+ * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit.
279
+ */
280
+ CPUARMState *env = &cpu->env;
281
+ CPUState *cs = CPU(cpu);
282
+
283
+ bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) &&
284
+ (arm_hcrx_el2_eff(env) & HCRX_VFNMI);
285
+
286
+ if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) {
287
+ if (new_state) {
288
+ cpu_interrupt(cs, CPU_INTERRUPT_VFNMI);
289
+ } else {
290
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI);
291
+ }
292
+ }
293
+}
294
+
295
void arm_cpu_update_vserr(ARMCPU *cpu)
296
{
297
/*
298
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_set_irq(void *opaque, int irq, int level)
299
[ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
300
[ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
301
[ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
302
- [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
303
+ [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ,
304
+ [ARM_CPU_NMI] = CPU_INTERRUPT_NMI,
305
+ [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI,
306
};
307
308
if (!arm_feature(env, ARM_FEATURE_EL2) &&
309
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_set_irq(void *opaque, int irq, int level)
310
case ARM_CPU_VFIQ:
311
arm_cpu_update_vfiq(cpu);
312
break;
313
+ case ARM_CPU_VINMI:
314
+ arm_cpu_update_vinmi(cpu);
315
+ break;
316
case ARM_CPU_IRQ:
317
case ARM_CPU_FIQ:
318
+ case ARM_CPU_NMI:
319
if (level) {
320
cpu_interrupt(cs, mask[irq]);
321
} else {
322
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
323
#else
324
/* Our inbound IRQ and FIQ lines */
325
if (kvm_enabled()) {
326
- /* VIRQ and VFIQ are unused with KVM but we add them to maintain
327
- * the same interface as non-KVM CPUs.
328
+ /*
329
+ * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add
330
+ * them to maintain the same interface as non-KVM CPUs.
331
*/
332
- qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
333
+ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6);
334
} else {
335
- qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
336
+ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6);
62
}
337
}
63
338
64
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
339
qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
65
rn1_64 = tcg_temp_new_i64();
340
diff --git a/target/arm/helper.c b/target/arm/helper.c
66
rm_64 = tcg_temp_new_i64();
341
index XXXXXXX..XXXXXXX 100644
67
342
--- a/target/arm/helper.c
68
- if (src1_wide) {
343
+++ b/target/arm/helper.c
69
- read_neon_element64(rn0_64, a->vn, 0, MO_64);
344
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
70
+ if (src1_mop >= 0) {
345
* and the state of the input lines from the GIC. (This requires
71
+ read_neon_element64(rn0_64, a->vn, 0, src1_mop);
346
* that we have the BQL, which is done by marking the
72
} else {
347
* reginfo structs as ARM_CP_IO.)
73
TCGv_i32 tmp = tcg_temp_new_i32();
348
- * Note that if a write to HCR pends a VIRQ or VFIQ it is never
74
read_neon_element32(tmp, a->vn, 0, MO_32);
349
- * possible for it to be taken immediately, because VIRQ and
75
widenfn(rn0_64, tmp);
350
- * VFIQ are masked unless running at EL0 or EL1, and HCR
76
tcg_temp_free_i32(tmp);
351
- * can only be written at EL2.
77
}
352
+ * Note that if a write to HCR pends a VIRQ or VFIQ or VINMI or
78
- rm = tcg_temp_new_i32();
353
+ * VFNMI, it is never possible for it to be taken immediately
79
- read_neon_element32(rm, a->vm, 0, MO_32);
354
+ * because VIRQ, VFIQ, VINMI and VFNMI are masked unless running
80
+ if (src2_mop >= 0) {
355
+ * at EL0 or EL1, and HCR can only be written at EL2.
81
+ read_neon_element64(rm_64, a->vm, 0, src2_mop);
82
+ } else {
83
+ TCGv_i32 tmp = tcg_temp_new_i32();
84
+ read_neon_element32(tmp, a->vm, 0, MO_32);
85
+ widenfn(rm_64, tmp);
86
+ tcg_temp_free_i32(tmp);
87
+ }
88
89
- widenfn(rm_64, rm);
90
- tcg_temp_free_i32(rm);
91
opfn(rn0_64, rn0_64, rm_64);
92
93
/*
94
* Load second pass inputs before storing the first pass result, to
95
* avoid incorrect results if a narrow input overlaps with the result.
96
*/
356
*/
97
- if (src1_wide) {
357
g_assert(bql_locked());
98
- read_neon_element64(rn1_64, a->vn, 1, MO_64);
358
arm_cpu_update_virq(cpu);
99
+ if (src1_mop >= 0) {
359
arm_cpu_update_vfiq(cpu);
100
+ read_neon_element64(rn1_64, a->vn, 1, src1_mop);
360
arm_cpu_update_vserr(cpu);
101
} else {
361
+ if (cpu_isar_feature(aa64_nmi, cpu)) {
102
TCGv_i32 tmp = tcg_temp_new_i32();
362
+ arm_cpu_update_vinmi(cpu);
103
read_neon_element32(tmp, a->vn, 1, MO_32);
363
+ arm_cpu_update_vfnmi(cpu);
104
widenfn(rn1_64, tmp);
364
+ }
105
tcg_temp_free_i32(tmp);
106
}
107
- rm = tcg_temp_new_i32();
108
- read_neon_element32(rm, a->vm, 1, MO_32);
109
+ if (src2_mop >= 0) {
110
+ read_neon_element64(rm_64, a->vm, 1, src2_mop);
111
+ } else {
112
+ TCGv_i32 tmp = tcg_temp_new_i32();
113
+ read_neon_element32(tmp, a->vm, 1, MO_32);
114
+ widenfn(rm_64, tmp);
115
+ tcg_temp_free_i32(tmp);
116
+ }
117
118
write_neon_element64(rn0_64, a->vd, 0, MO_64);
119
120
- widenfn(rm_64, rm);
121
- tcg_temp_free_i32(rm);
122
opfn(rn1_64, rn1_64, rm_64);
123
write_neon_element64(rn1_64, a->vd, 1, MO_64);
124
125
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
126
return true;
127
}
365
}
128
366
129
-#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \
367
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
130
+#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \
368
@@ -XXX,XX +XXX,XX @@ static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri,
131
static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
369
132
{ \
370
/* Clear RES0 bits. */
133
static NeonGenWidenFn * const widenfn[] = { \
371
env->cp15.hcrx_el2 = value & valid_mask;
134
gen_helper_neon_widen_##S##8, \
372
+
135
gen_helper_neon_widen_##S##16, \
373
+ /*
136
- tcg_gen_##EXT##_i32_i64, \
374
+ * Updates to VINMI and VFNMI require us to update the status of
137
- NULL, \
375
+ * virtual NMI, which are the logical OR of these bits
138
+ NULL, NULL, \
376
+ * and the state of the input lines from the GIC. (This requires
139
}; \
377
+ * that we have the BQL, which is done by marking the
140
static NeonGenTwo64OpFn * const addfn[] = { \
378
+ * reginfo structs as ARM_CP_IO.)
141
gen_helper_neon_##OP##l_u16, \
379
+ * Note that if a write to HCRX pends a VINMI or VFNMI it is never
142
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
380
+ * possible for it to be taken immediately, because VINMI and
143
tcg_gen_##OP##_i64, \
381
+ * VFNMI are masked unless running at EL0 or EL1, and HCRX
144
NULL, \
382
+ * can only be written at EL2.
145
}; \
383
+ */
146
- return do_prewiden_3d(s, a, widenfn[a->size], \
384
+ if (cpu_isar_feature(aa64_nmi, cpu)) {
147
- addfn[a->size], SRC1WIDE); \
385
+ g_assert(bql_locked());
148
+ int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1; \
386
+ arm_cpu_update_vinmi(cpu);
149
+ return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \
387
+ arm_cpu_update_vfnmi(cpu);
150
+ SRC1WIDE ? MO_Q : narrow_mop, \
388
+ }
151
+ narrow_mop); \
389
}
152
}
390
153
391
static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri,
154
-DO_PREWIDEN(VADDL_S, s, ext, add, false)
392
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri,
155
-DO_PREWIDEN(VADDL_U, u, extu, add, false)
393
156
-DO_PREWIDEN(VSUBL_S, s, ext, sub, false)
394
static const ARMCPRegInfo hcrx_el2_reginfo = {
157
-DO_PREWIDEN(VSUBL_U, u, extu, sub, false)
395
.name = "HCRX_EL2", .state = ARM_CP_STATE_AA64,
158
-DO_PREWIDEN(VADDW_S, s, ext, add, true)
396
+ .type = ARM_CP_IO,
159
-DO_PREWIDEN(VADDW_U, u, extu, add, true)
397
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 2,
160
-DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
398
.access = PL2_RW, .writefn = hcrx_write, .accessfn = access_hxen,
161
-DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
399
.nv2_redirect_offset = 0xa0,
162
+DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN)
400
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
163
+DO_PREWIDEN(VADDL_U, u, add, false, 0)
401
[EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
164
+DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN)
402
[EXCP_VSERR] = "Virtual SERR",
165
+DO_PREWIDEN(VSUBL_U, u, sub, false, 0)
403
[EXCP_GPC] = "Granule Protection Check",
166
+DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN)
404
+ [EXCP_NMI] = "NMI",
167
+DO_PREWIDEN(VADDW_U, u, add, true, 0)
405
+ [EXCP_VINMI] = "Virtual IRQ NMI",
168
+DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN)
406
+ [EXCP_VFNMI] = "Virtual FIQ NMI",
169
+DO_PREWIDEN(VSUBW_U, u, sub, true, 0)
407
};
170
408
171
static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
409
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
172
NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
173
--
410
--
174
2.20.1
411
2.34.1
175
176
diff view generated by jsdifflib
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
HCR should be applied when NS is set, not when it is cleared.
3
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
4
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
5
arm_phys_excp_target_el().
4
6
5
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
7
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20240407081733.3231820-8-ruanjinjie@huawei.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
12
---
9
target/arm/helper.c | 5 ++---
13
target/arm/helper.c | 1 +
10
1 file changed, 2 insertions(+), 3 deletions(-)
14
1 file changed, 1 insertion(+)
11
15
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.c
18
--- a/target/arm/helper.c
15
+++ b/target/arm/helper.c
19
+++ b/target/arm/helper.c
16
@@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
17
21
hcr_el2 = arm_hcr_el2_eff(env);
18
/*
22
switch (excp_idx) {
19
* Non-IS variants of TLB operations are upgraded to
23
case EXCP_IRQ:
20
- * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
24
+ case EXCP_NMI:
21
+ * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
25
scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
22
* force broadcast of these operations.
26
hcr = hcr_el2 & HCR_IMO;
23
*/
27
break;
24
static bool tlb_force_broadcast(CPUARMState *env)
25
{
26
- return (env->cp15.hcr_el2 & HCR_FB) &&
27
- arm_current_el(env) == 1 && arm_is_secure_below_el3(env);
28
+ return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
29
}
30
31
static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
32
--
28
--
33
2.20.1
29
2.34.1
34
35
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or
4
CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With
5
CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set.
6
7
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20240407081733.3231820-9-ruanjinjie@huawei.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.h | 2 ++
14
target/arm/helper.c | 13 +++++++++++++
15
2 files changed, 15 insertions(+)
16
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
22
#define CPSR_N (1U << 31)
23
#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
24
#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
25
+#define ISR_FS (1U << 9)
26
+#define ISR_IS (1U << 10)
27
28
#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
29
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
35
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
36
ret |= CPSR_I;
37
}
38
+ if (cs->interrupt_request & CPU_INTERRUPT_VINMI) {
39
+ ret |= ISR_IS;
40
+ ret |= CPSR_I;
41
+ }
42
} else {
43
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
44
ret |= CPSR_I;
45
}
46
+
47
+ if (cs->interrupt_request & CPU_INTERRUPT_NMI) {
48
+ ret |= ISR_IS;
49
+ ret |= CPSR_I;
50
+ }
51
}
52
53
if (hcr_el2 & HCR_FMO) {
54
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
55
ret |= CPSR_F;
56
}
57
+ if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) {
58
+ ret |= ISR_FS;
59
+ ret |= CPSR_F;
60
+ }
61
} else {
62
if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
63
ret |= CPSR_F;
64
--
65
2.34.1
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
The only uses of this function are for loading VFP
3
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the
4
double-precision values, and nothing to do with NEON.
4
SCTLR_ELx.SPINTMASK bit.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Message-id: 20201030022618.785675-10-richard.henderson@linaro.org
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20240407081733.3231820-10-ruanjinjie@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate.c | 8 ++--
12
target/arm/helper.c | 8 ++++++++
12
target/arm/translate-vfp.c.inc | 84 +++++++++++++++++-----------------
13
1 file changed, 8 insertions(+)
13
2 files changed, 46 insertions(+), 46 deletions(-)
14
14
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
17
--- a/target/arm/helper.c
18
+++ b/target/arm/translate.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
19
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
20
}
21
}
22
23
-static inline void neon_load_reg64(TCGv_i64 var, int reg)
24
+static inline void vfp_load_reg64(TCGv_i64 var, int reg)
25
{
26
- tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
27
+ tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
28
}
29
30
-static inline void neon_store_reg64(TCGv_i64 var, int reg)
31
+static inline void vfp_store_reg64(TCGv_i64 var, int reg)
32
{
33
- tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
34
+ tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
35
}
36
37
static inline void vfp_load_reg32(TCGv_i32 var, int reg)
38
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/translate-vfp.c.inc
41
+++ b/target/arm/translate-vfp.c.inc
42
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
43
tcg_gen_ext_i32_i64(nf, cpu_NF);
44
tcg_gen_ext_i32_i64(vf, cpu_VF);
45
46
- neon_load_reg64(frn, rn);
47
- neon_load_reg64(frm, rm);
48
+ vfp_load_reg64(frn, rn);
49
+ vfp_load_reg64(frm, rm);
50
switch (a->cc) {
51
case 0: /* eq: Z */
52
tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
53
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
54
tcg_temp_free_i64(tmp);
55
break;
56
}
57
- neon_store_reg64(dest, rd);
58
+ vfp_store_reg64(dest, rd);
59
tcg_temp_free_i64(frn);
60
tcg_temp_free_i64(frm);
61
tcg_temp_free_i64(dest);
62
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
63
TCGv_i64 tcg_res;
64
tcg_op = tcg_temp_new_i64();
65
tcg_res = tcg_temp_new_i64();
66
- neon_load_reg64(tcg_op, rm);
67
+ vfp_load_reg64(tcg_op, rm);
68
gen_helper_rintd(tcg_res, tcg_op, fpst);
69
- neon_store_reg64(tcg_res, rd);
70
+ vfp_store_reg64(tcg_res, rd);
71
tcg_temp_free_i64(tcg_op);
72
tcg_temp_free_i64(tcg_res);
73
} else {
74
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
75
tcg_double = tcg_temp_new_i64();
76
tcg_res = tcg_temp_new_i64();
77
tcg_tmp = tcg_temp_new_i32();
78
- neon_load_reg64(tcg_double, rm);
79
+ vfp_load_reg64(tcg_double, rm);
80
if (is_signed) {
81
gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
82
} else {
83
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
84
tmp = tcg_temp_new_i64();
85
if (a->l) {
86
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
87
- neon_store_reg64(tmp, a->vd);
88
+ vfp_store_reg64(tmp, a->vd);
89
} else {
90
- neon_load_reg64(tmp, a->vd);
91
+ vfp_load_reg64(tmp, a->vd);
92
gen_aa32_st64(s, tmp, addr, get_mem_index(s));
93
}
94
tcg_temp_free_i64(tmp);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
96
if (a->l) {
97
/* load */
98
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
99
- neon_store_reg64(tmp, a->vd + i);
100
+ vfp_store_reg64(tmp, a->vd + i);
101
} else {
102
/* store */
103
- neon_load_reg64(tmp, a->vd + i);
104
+ vfp_load_reg64(tmp, a->vd + i);
105
gen_aa32_st64(s, tmp, addr, get_mem_index(s));
106
}
107
tcg_gen_addi_i32(addr, addr, offset);
108
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
109
fd = tcg_temp_new_i64();
110
fpst = fpstatus_ptr(FPST_FPCR);
111
112
- neon_load_reg64(f0, vn);
113
- neon_load_reg64(f1, vm);
114
+ vfp_load_reg64(f0, vn);
115
+ vfp_load_reg64(f1, vm);
116
117
for (;;) {
118
if (reads_vd) {
119
- neon_load_reg64(fd, vd);
120
+ vfp_load_reg64(fd, vd);
121
}
122
fn(fd, f0, f1, fpst);
123
- neon_store_reg64(fd, vd);
124
+ vfp_store_reg64(fd, vd);
125
126
if (veclen == 0) {
127
break;
128
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
129
veclen--;
130
vd = vfp_advance_dreg(vd, delta_d);
131
vn = vfp_advance_dreg(vn, delta_d);
132
- neon_load_reg64(f0, vn);
133
+ vfp_load_reg64(f0, vn);
134
if (delta_m) {
135
vm = vfp_advance_dreg(vm, delta_m);
136
- neon_load_reg64(f1, vm);
137
+ vfp_load_reg64(f1, vm);
138
}
20
}
139
}
21
}
140
22
141
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
23
+ if (cpu_isar_feature(aa64_nmi, cpu)) {
142
f0 = tcg_temp_new_i64();
24
+ if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPINTMASK)) {
143
fd = tcg_temp_new_i64();
25
+ new_mode |= PSTATE_ALLINT;
144
26
+ } else {
145
- neon_load_reg64(f0, vm);
27
+ new_mode &= ~PSTATE_ALLINT;
146
+ vfp_load_reg64(f0, vm);
28
+ }
147
29
+ }
148
for (;;) {
30
+
149
fn(fd, f0);
31
pstate_write(env, PSTATE_DAIF | new_mode);
150
- neon_store_reg64(fd, vd);
32
env->aarch64 = true;
151
+ vfp_store_reg64(fd, vd);
33
aarch64_restore_sp(env, new_el);
152
153
if (veclen == 0) {
154
break;
155
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
156
/* single source one-many */
157
while (veclen--) {
158
vd = vfp_advance_dreg(vd, delta_d);
159
- neon_store_reg64(fd, vd);
160
+ vfp_store_reg64(fd, vd);
161
}
162
break;
163
}
164
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
165
veclen--;
166
vd = vfp_advance_dreg(vd, delta_d);
167
vd = vfp_advance_dreg(vm, delta_m);
168
- neon_load_reg64(f0, vm);
169
+ vfp_load_reg64(f0, vm);
170
}
171
172
tcg_temp_free_i64(f0);
173
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
174
vm = tcg_temp_new_i64();
175
vd = tcg_temp_new_i64();
176
177
- neon_load_reg64(vn, a->vn);
178
- neon_load_reg64(vm, a->vm);
179
+ vfp_load_reg64(vn, a->vn);
180
+ vfp_load_reg64(vm, a->vm);
181
if (neg_n) {
182
/* VFNMS, VFMS */
183
gen_helper_vfp_negd(vn, vn);
184
}
185
- neon_load_reg64(vd, a->vd);
186
+ vfp_load_reg64(vd, a->vd);
187
if (neg_d) {
188
/* VFNMA, VFNMS */
189
gen_helper_vfp_negd(vd, vd);
190
}
191
fpst = fpstatus_ptr(FPST_FPCR);
192
gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
193
- neon_store_reg64(vd, a->vd);
194
+ vfp_store_reg64(vd, a->vd);
195
196
tcg_temp_free_ptr(fpst);
197
tcg_temp_free_i64(vn);
198
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
199
fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
200
201
for (;;) {
202
- neon_store_reg64(fd, vd);
203
+ vfp_store_reg64(fd, vd);
204
205
if (veclen == 0) {
206
break;
207
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
208
vd = tcg_temp_new_i64();
209
vm = tcg_temp_new_i64();
210
211
- neon_load_reg64(vd, a->vd);
212
+ vfp_load_reg64(vd, a->vd);
213
if (a->z) {
214
tcg_gen_movi_i64(vm, 0);
215
} else {
216
- neon_load_reg64(vm, a->vm);
217
+ vfp_load_reg64(vm, a->vm);
218
}
219
220
if (a->e) {
221
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
222
tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
223
vd = tcg_temp_new_i64();
224
gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
225
- neon_store_reg64(vd, a->vd);
226
+ vfp_store_reg64(vd, a->vd);
227
tcg_temp_free_i32(ahp_mode);
228
tcg_temp_free_ptr(fpst);
229
tcg_temp_free_i32(tmp);
230
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
231
tmp = tcg_temp_new_i32();
232
vm = tcg_temp_new_i64();
233
234
- neon_load_reg64(vm, a->vm);
235
+ vfp_load_reg64(vm, a->vm);
236
gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
237
tcg_temp_free_i64(vm);
238
tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
239
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
240
}
241
242
tmp = tcg_temp_new_i64();
243
- neon_load_reg64(tmp, a->vm);
244
+ vfp_load_reg64(tmp, a->vm);
245
fpst = fpstatus_ptr(FPST_FPCR);
246
gen_helper_rintd(tmp, tmp, fpst);
247
- neon_store_reg64(tmp, a->vd);
248
+ vfp_store_reg64(tmp, a->vd);
249
tcg_temp_free_ptr(fpst);
250
tcg_temp_free_i64(tmp);
251
return true;
252
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
253
}
254
255
tmp = tcg_temp_new_i64();
256
- neon_load_reg64(tmp, a->vm);
257
+ vfp_load_reg64(tmp, a->vm);
258
fpst = fpstatus_ptr(FPST_FPCR);
259
tcg_rmode = tcg_const_i32(float_round_to_zero);
260
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
261
gen_helper_rintd(tmp, tmp, fpst);
262
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
263
- neon_store_reg64(tmp, a->vd);
264
+ vfp_store_reg64(tmp, a->vd);
265
tcg_temp_free_ptr(fpst);
266
tcg_temp_free_i64(tmp);
267
tcg_temp_free_i32(tcg_rmode);
268
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
269
}
270
271
tmp = tcg_temp_new_i64();
272
- neon_load_reg64(tmp, a->vm);
273
+ vfp_load_reg64(tmp, a->vm);
274
fpst = fpstatus_ptr(FPST_FPCR);
275
gen_helper_rintd_exact(tmp, tmp, fpst);
276
- neon_store_reg64(tmp, a->vd);
277
+ vfp_store_reg64(tmp, a->vd);
278
tcg_temp_free_ptr(fpst);
279
tcg_temp_free_i64(tmp);
280
return true;
281
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
282
vd = tcg_temp_new_i64();
283
vfp_load_reg32(vm, a->vm);
284
gen_helper_vfp_fcvtds(vd, vm, cpu_env);
285
- neon_store_reg64(vd, a->vd);
286
+ vfp_store_reg64(vd, a->vd);
287
tcg_temp_free_i32(vm);
288
tcg_temp_free_i64(vd);
289
return true;
290
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
291
292
vd = tcg_temp_new_i32();
293
vm = tcg_temp_new_i64();
294
- neon_load_reg64(vm, a->vm);
295
+ vfp_load_reg64(vm, a->vm);
296
gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
297
vfp_store_reg32(vd, a->vd);
298
tcg_temp_free_i32(vd);
299
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
300
/* u32 -> f64 */
301
gen_helper_vfp_uitod(vd, vm, fpst);
302
}
303
- neon_store_reg64(vd, a->vd);
304
+ vfp_store_reg64(vd, a->vd);
305
tcg_temp_free_i32(vm);
306
tcg_temp_free_i64(vd);
307
tcg_temp_free_ptr(fpst);
308
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
309
310
vm = tcg_temp_new_i64();
311
vd = tcg_temp_new_i32();
312
- neon_load_reg64(vm, a->vm);
313
+ vfp_load_reg64(vm, a->vm);
314
gen_helper_vjcvt(vd, vm, cpu_env);
315
vfp_store_reg32(vd, a->vd);
316
tcg_temp_free_i64(vm);
317
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
318
frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
319
320
vd = tcg_temp_new_i64();
321
- neon_load_reg64(vd, a->vd);
322
+ vfp_load_reg64(vd, a->vd);
323
324
fpst = fpstatus_ptr(FPST_FPCR);
325
shift = tcg_const_i32(frac_bits);
326
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
327
g_assert_not_reached();
328
}
329
330
- neon_store_reg64(vd, a->vd);
331
+ vfp_store_reg64(vd, a->vd);
332
tcg_temp_free_i64(vd);
333
tcg_temp_free_i32(shift);
334
tcg_temp_free_ptr(fpst);
335
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
336
fpst = fpstatus_ptr(FPST_FPCR);
337
vm = tcg_temp_new_i64();
338
vd = tcg_temp_new_i32();
339
- neon_load_reg64(vm, a->vm);
340
+ vfp_load_reg64(vm, a->vm);
341
342
if (a->s) {
343
if (a->rz) {
344
--
34
--
345
2.20.1
35
2.34.1
346
347
diff view generated by jsdifflib
1
In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
into the GICv3CPUState struct's maintenance_irq field. This will
3
only work if the board happens to have already wired up the CPU
4
maintenance IRQ before the GIC was realized. Unfortunately this is
5
not the case for the 'virt' board, and so the value that gets copied
6
is NULL (since a qemu_irq is really a pointer to an IRQState struct
7
under the hood). The effect is that the CPU interface code never
8
actually raises the maintenance interrupt line.
9
2
10
Instead, since the GICv3CPUState has a pointer to the CPUState, make
3
Augment the GICv3's QOM device interface by adding one
11
the dereference at the point where we want to raise the interrupt, to
4
new set of sysbus IRQ line, to signal NMI to each CPU.
12
avoid an implicit requirement on board code to wire things up in a
13
particular order.
14
5
15
Reported-by: Jose Martins <josemartins90@gmail.com>
6
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20201009153904.28529-1-peter.maydell@linaro.org
18
Reviewed-by: Luc Michel <luc@lmichel.fr>
19
---
11
---
20
include/hw/intc/arm_gicv3_common.h | 1 -
12
include/hw/intc/arm_gic_common.h | 2 ++
21
hw/intc/arm_gicv3_cpuif.c | 5 ++---
13
include/hw/intc/arm_gicv3_common.h | 2 ++
22
2 files changed, 2 insertions(+), 4 deletions(-)
14
hw/intc/arm_gicv3_common.c | 6 ++++++
15
3 files changed, 10 insertions(+)
23
16
17
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/intc/arm_gic_common.h
20
+++ b/include/hw/intc/arm_gic_common.h
21
@@ -XXX,XX +XXX,XX @@ struct GICState {
22
qemu_irq parent_fiq[GIC_NCPU];
23
qemu_irq parent_virq[GIC_NCPU];
24
qemu_irq parent_vfiq[GIC_NCPU];
25
+ qemu_irq parent_nmi[GIC_NCPU];
26
+ qemu_irq parent_vnmi[GIC_NCPU];
27
qemu_irq maintenance_irq[GIC_NCPU];
28
29
/* GICD_CTLR; for a GIC with the security extensions the NS banked version
24
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
30
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
25
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/intc/arm_gicv3_common.h
32
--- a/include/hw/intc/arm_gicv3_common.h
27
+++ b/include/hw/intc/arm_gicv3_common.h
33
+++ b/include/hw/intc/arm_gicv3_common.h
28
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
34
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
29
qemu_irq parent_fiq;
35
qemu_irq parent_fiq;
30
qemu_irq parent_virq;
36
qemu_irq parent_virq;
31
qemu_irq parent_vfiq;
37
qemu_irq parent_vfiq;
32
- qemu_irq maintenance_irq;
38
+ qemu_irq parent_nmi;
39
+ qemu_irq parent_vnmi;
33
40
34
/* Redistributor */
41
/* Redistributor */
35
uint32_t level; /* Current IRQ level */
42
uint32_t level; /* Current IRQ level */
36
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
43
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
37
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/intc/arm_gicv3_cpuif.c
45
--- a/hw/intc/arm_gicv3_common.c
39
+++ b/hw/intc/arm_gicv3_cpuif.c
46
+++ b/hw/intc/arm_gicv3_common.c
40
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
47
@@ -XXX,XX +XXX,XX @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
41
int irqlevel = 0;
48
for (i = 0; i < s->num_cpu; i++) {
42
int fiqlevel = 0;
49
sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
43
int maintlevel = 0;
50
}
44
+ ARMCPU *cpu = ARM_CPU(cs->cpu);
51
+ for (i = 0; i < s->num_cpu; i++) {
45
52
+ sysbus_init_irq(sbd, &s->cpu[i].parent_nmi);
46
idx = hppvi_index(cs);
53
+ }
47
trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx);
54
+ for (i = 0; i < s->num_cpu; i++) {
48
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
55
+ sysbus_init_irq(sbd, &s->cpu[i].parent_vnmi);
49
56
+ }
50
qemu_set_irq(cs->parent_vfiq, fiqlevel);
57
51
qemu_set_irq(cs->parent_virq, irqlevel);
58
memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
52
- qemu_set_irq(cs->maintenance_irq, maintlevel);
59
"gicv3_dist", 0x10000);
53
+ qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel);
54
}
55
56
static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
57
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
58
&& cpu->gic_num_lrs) {
59
int j;
60
61
- cs->maintenance_irq = cpu->gicv3_maintenance_interrupt;
62
-
63
cs->num_list_regs = cpu->gic_num_lrs;
64
cs->vpribits = cpu->gic_vpribits;
65
cs->vprebits = cpu->gic_vprebits;
66
--
60
--
67
2.20.1
61
2.34.1
68
69
diff view generated by jsdifflib
1
The kerneldoc script currently emits Sphinx markup for a macro with
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
arguments that uses the c:function directive. This is correct for
3
Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow
4
documentation of macros with arguments and c:function is not picky
5
about the syntax of what it is passed. However, in Sphinx 3 the
6
c:macro directive was enhanced to support macros with arguments,
7
and c:function was made more picky about what syntax it accepted.
8
2
9
When kerneldoc is told that it needs to produce output for Sphinx
3
Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it
10
3 or later, make it emit c:function only for functions and c:macro
4
is not GICv2.
11
for macros with arguments. We assume that anything with a return
12
type is a function and anything without is a macro.
13
5
14
This fixes the Sphinx error:
6
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20240407081733.3231820-12-ruanjinjie@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/virt.c | 10 +++++++++-
12
1 file changed, 9 insertions(+), 1 deletion(-)
15
13
16
/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
17
If declarator-id with parameters (e.g., 'void f(int arg)'):
15
index XXXXXXX..XXXXXXX 100644
18
Invalid C declaration: Expected identifier in nested name. [error at 25]
16
--- a/hw/arm/virt.c
19
DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME)
17
+++ b/hw/arm/virt.c
20
-------------------------^
18
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
21
If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'):
19
22
Error in declarator or parameters
20
/* Wire the outputs from each CPU's generic timer and the GICv3
23
Invalid C declaration: Expecting "(" in parameters. [error at 39]
21
* maintenance interrupt signal to the appropriate GIC PPI inputs,
24
DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME)
22
- * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
25
---------------------------------------^
23
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
26
24
+ * CPU's inputs.
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
*/
28
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
26
for (i = 0; i < smp_cpus; i++) {
29
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
27
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
30
Message-id: 20201030174700.7204-2-peter.maydell@linaro.org
28
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
31
---
29
qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
32
scripts/kernel-doc | 18 +++++++++++++++++-
30
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
33
1 file changed, 17 insertions(+), 1 deletion(-)
31
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
34
32
+
35
diff --git a/scripts/kernel-doc b/scripts/kernel-doc
33
+ if (vms->gic_version != VIRT_GIC_VERSION_2) {
36
index XXXXXXX..XXXXXXX 100755
34
+ sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,
37
--- a/scripts/kernel-doc
35
+ qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
38
+++ b/scripts/kernel-doc
36
+ sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,
39
@@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) {
37
+ qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
40
    output_highlight_rst($args{'purpose'});
41
    $start = "\n\n**Syntax**\n\n ``";
42
} else {
43
-    print ".. c:function:: ";
44
+ if ((split(/\./, $sphinx_version))[0] >= 3) {
45
+ # Sphinx 3 and later distinguish macros and functions and
46
+ # complain if you use c:function with something that's not
47
+ # syntactically valid as a function declaration.
48
+ # We assume that anything with a return type is a function
49
+ # and anything without is a macro.
50
+ if ($args{'functiontype'} ne "") {
51
+ print ".. c:function:: ";
52
+ } else {
53
+ print ".. c:macro:: ";
54
+ }
55
+ } else {
56
+ # Older Sphinx don't support documenting macros that take
57
+ # arguments with c:macro, and don't complain about the use
58
+ # of c:function for this.
59
+ print ".. c:function:: ";
60
+ }
38
+ }
61
}
39
}
62
if ($args{'functiontype'} ne "") {
40
63
    $start .= $args{'functiontype'} . " " . $args{'function'} . " (";
41
fdt_add_gic_node(vms);
64
--
42
--
65
2.20.1
43
2.34.1
66
67
diff view generated by jsdifflib
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so
3
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
4
that SVE will not trap to EL3.
4
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
5
behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the
6
GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority)
7
come from the hcrx_el2.HCRX_VFNMI bit.
5
8
6
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
9
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201030151541.11976-1-remi@remlab.net
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20240407081733.3231820-13-ruanjinjie@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
hw/arm/boot.c | 3 +++
15
target/arm/helper.c | 3 +++
12
1 file changed, 3 insertions(+)
16
1 file changed, 3 insertions(+)
13
17
14
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/boot.c
20
--- a/target/arm/helper.c
17
+++ b/hw/arm/boot.c
21
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
22
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
19
if (cpu_isar_feature(aa64_mte, cpu)) {
23
break;
20
env->cp15.scr_el3 |= SCR_ATA;
24
case EXCP_IRQ:
21
}
25
case EXCP_VIRQ:
22
+ if (cpu_isar_feature(aa64_sve, cpu)) {
26
+ case EXCP_NMI:
23
+ env->cp15.cptr_el[3] |= CPTR_EZ;
27
+ case EXCP_VINMI:
24
+ }
28
addr += 0x80;
25
/* AArch64 kernels never boot in secure mode */
29
break;
26
assert(!info->secure_boot);
30
case EXCP_FIQ:
27
/* This hook is only supported for AArch32 currently:
31
case EXCP_VFIQ:
32
+ case EXCP_VFNMI:
33
addr += 0x100;
34
break;
35
case EXCP_VSERR:
28
--
36
--
29
2.20.1
37
2.34.1
30
31
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
Add a property has-nmi to the GICv3 device, and use this to set
4
the NMI bit in the GICD_TYPER register. This isn't visible to
5
guests yet because the property defaults to false and we won't
6
set it in the board code until we've landed all of the changes
7
needed to implement FEAT_GICV3_NMI.
8
9
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20240407081733.3231820-14-ruanjinjie@huawei.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/intc/gicv3_internal.h | 1 +
16
include/hw/intc/arm_gicv3_common.h | 1 +
17
hw/intc/arm_gicv3_common.c | 1 +
18
hw/intc/arm_gicv3_dist.c | 2 ++
19
4 files changed, 5 insertions(+)
20
21
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/intc/gicv3_internal.h
24
+++ b/hw/intc/gicv3_internal.h
25
@@ -XXX,XX +XXX,XX @@
26
#define GICD_CTLR_E1NWF (1U << 7)
27
#define GICD_CTLR_RWP (1U << 31)
28
29
+#define GICD_TYPER_NMI_SHIFT 9
30
#define GICD_TYPER_LPIS_SHIFT 17
31
32
/* 16 bits EventId */
33
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/include/hw/intc/arm_gicv3_common.h
36
+++ b/include/hw/intc/arm_gicv3_common.h
37
@@ -XXX,XX +XXX,XX @@ struct GICv3State {
38
uint32_t num_irq;
39
uint32_t revision;
40
bool lpi_enable;
41
+ bool nmi_support;
42
bool security_extn;
43
bool force_8bit_prio;
44
bool irq_reset_nonsecure;
45
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/arm_gicv3_common.c
48
+++ b/hw/intc/arm_gicv3_common.c
49
@@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = {
50
DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
51
DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
52
DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
53
+ DEFINE_PROP_BOOL("has-nmi", GICv3State, nmi_support, 0),
54
DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
55
/*
56
* Compatibility property: force 8 bits of physical priority, even
57
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/intc/arm_gicv3_dist.c
60
+++ b/hw/intc/arm_gicv3_dist.c
61
@@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
62
* by GICD_TYPER.IDbits)
63
* MBIS == 0 (message-based SPIs not supported)
64
* SecurityExtn == 1 if security extns supported
65
+ * NMI = 1 if Non-maskable interrupt property is supported
66
* CPUNumber == 0 since for us ARE is always 1
67
* ITLinesNumber == (((max SPI IntID + 1) / 32) - 1)
68
*/
69
@@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
70
bool dvis = s->revision >= 4;
71
72
*data = (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) |
73
+ (s->nmi_support << GICD_TYPER_NMI_SHIFT) |
74
(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
75
(0xf << 19) | itlinesnumber;
76
return true;
77
--
78
2.34.1
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
So far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it
4
an error to try to set has-nmi=true for the KVM GICv3.
5
6
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Message-id: 20240407081733.3231820-15-ruanjinjie@huawei.com
8
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/intc/arm_gicv3_kvm.c | 5 +++++
12
1 file changed, 5 insertions(+)
13
14
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gicv3_kvm.c
17
+++ b/hw/intc/arm_gicv3_kvm.c
18
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
19
return;
20
}
21
22
+ if (s->nmi_support) {
23
+ error_setg(errp, "NMI is not supported with the in-kernel GIC");
24
+ return;
25
+ }
26
+
27
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
28
29
for (i = 0; i < s->num_cpu; i++) {
30
--
31
2.34.1
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
A SPI, PPI or SGI interrupt can have non-maskable property. So maintain
4
non-maskable property in PendingIrq and GICR/GICD. Since add new device
5
state, it also needs to be migrated, so also save NMI info in
6
vmstate_gicv3_cpu and vmstate_gicv3.
7
8
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
9
Acked-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
include/hw/intc/arm_gicv3_common.h | 4 ++++
15
hw/intc/arm_gicv3_common.c | 38 ++++++++++++++++++++++++++++++
16
2 files changed, 42 insertions(+)
17
18
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/intc/arm_gicv3_common.h
21
+++ b/include/hw/intc/arm_gicv3_common.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct {
23
int irq;
24
uint8_t prio;
25
int grp;
26
+ bool nmi;
27
} PendingIrq;
28
29
struct GICv3CPUState {
30
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
31
uint32_t gicr_ienabler0;
32
uint32_t gicr_ipendr0;
33
uint32_t gicr_iactiver0;
34
+ uint32_t gicr_inmir0;
35
uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
36
uint32_t gicr_igrpmodr0;
37
uint32_t gicr_nsacr;
38
@@ -XXX,XX +XXX,XX @@ struct GICv3State {
39
GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */
40
GIC_DECLARE_BITMAP(level); /* Current level */
41
GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
42
+ GIC_DECLARE_BITMAP(nmi); /* GICD_INMIR */
43
uint8_t gicd_ipriority[GICV3_MAXIRQ];
44
uint64_t gicd_irouter[GICV3_MAXIRQ];
45
/* Cached information: pointer to the cpu i/f for the CPUs specified
46
@@ -XXX,XX +XXX,XX @@ GICV3_BITMAP_ACCESSORS(pending)
47
GICV3_BITMAP_ACCESSORS(active)
48
GICV3_BITMAP_ACCESSORS(level)
49
GICV3_BITMAP_ACCESSORS(edge_trigger)
50
+GICV3_BITMAP_ACCESSORS(nmi)
51
52
#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
53
typedef struct ARMGICv3CommonClass ARMGICv3CommonClass;
54
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/intc/arm_gicv3_common.c
57
+++ b/hw/intc/arm_gicv3_common.c
58
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_gicv3_gicv4 = {
59
}
60
};
61
62
+static bool gicv3_cpu_nmi_needed(void *opaque)
63
+{
64
+ GICv3CPUState *cs = opaque;
65
+
66
+ return cs->gic->nmi_support;
67
+}
68
+
69
+static const VMStateDescription vmstate_gicv3_cpu_nmi = {
70
+ .name = "arm_gicv3_cpu/nmi",
71
+ .version_id = 1,
72
+ .minimum_version_id = 1,
73
+ .needed = gicv3_cpu_nmi_needed,
74
+ .fields = (const VMStateField[]) {
75
+ VMSTATE_UINT32(gicr_inmir0, GICv3CPUState),
76
+ VMSTATE_END_OF_LIST()
77
+ }
78
+};
79
+
80
static const VMStateDescription vmstate_gicv3_cpu = {
81
.name = "arm_gicv3_cpu",
82
.version_id = 1,
83
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = {
84
&vmstate_gicv3_cpu_virt,
85
&vmstate_gicv3_cpu_sre_el1,
86
&vmstate_gicv3_gicv4,
87
+ &vmstate_gicv3_cpu_nmi,
88
NULL
89
}
90
};
91
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = {
92
}
93
};
94
95
+static bool gicv3_nmi_needed(void *opaque)
96
+{
97
+ GICv3State *cs = opaque;
98
+
99
+ return cs->nmi_support;
100
+}
101
+
102
+const VMStateDescription vmstate_gicv3_gicd_nmi = {
103
+ .name = "arm_gicv3/gicd_nmi",
104
+ .version_id = 1,
105
+ .minimum_version_id = 1,
106
+ .needed = gicv3_nmi_needed,
107
+ .fields = (const VMStateField[]) {
108
+ VMSTATE_UINT32_ARRAY(nmi, GICv3State, GICV3_BMP_SIZE),
109
+ VMSTATE_END_OF_LIST()
110
+ }
111
+};
112
+
113
static const VMStateDescription vmstate_gicv3 = {
114
.name = "arm_gicv3",
115
.version_id = 1,
116
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
117
},
118
.subsections = (const VMStateDescription * const []) {
119
&vmstate_gicv3_gicd_no_migration_shift_bug,
120
+ &vmstate_gicv3_gicd_nmi,
121
NULL
122
}
123
};
124
--
125
2.34.1
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
Add GICR_INMIR0 register and support access GICR_INMIR0.
4
5
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/intc/gicv3_internal.h | 1 +
12
hw/intc/arm_gicv3_redist.c | 19 +++++++++++++++++++
13
2 files changed, 20 insertions(+)
14
15
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/gicv3_internal.h
18
+++ b/hw/intc/gicv3_internal.h
19
@@ -XXX,XX +XXX,XX @@
20
#define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04)
21
#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
22
#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
23
+#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80)
24
25
/* VLPI redistributor registers, offsets from VLPI_base */
26
#define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70)
27
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/intc/arm_gicv3_redist.c
30
+++ b/hw/intc/arm_gicv3_redist.c
31
@@ -XXX,XX +XXX,XX @@ static int gicr_ns_access(GICv3CPUState *cs, int irq)
32
return extract32(cs->gicr_nsacr, irq * 2, 2);
33
}
34
35
+static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
36
+ uint32_t *reg, uint32_t val)
37
+{
38
+ /* Helper routine to implement writing to a "set" register */
39
+ val &= mask_group(cs, attrs);
40
+ *reg = val;
41
+ gicv3_redist_update(cs);
42
+}
43
+
44
static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
45
uint32_t *reg, uint32_t val)
46
{
47
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
48
*data = value;
49
return MEMTX_OK;
50
}
51
+ case GICR_INMIR0:
52
+ *data = cs->gic->nmi_support ?
53
+ gicr_read_bitmap_reg(cs, attrs, cs->gicr_inmir0) : 0;
54
+ return MEMTX_OK;
55
case GICR_ICFGR0:
56
case GICR_ICFGR1:
57
{
58
@@ -XXX,XX +XXX,XX @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
59
gicv3_redist_update(cs);
60
return MEMTX_OK;
61
}
62
+ case GICR_INMIR0:
63
+ if (cs->gic->nmi_support) {
64
+ gicr_write_bitmap_reg(cs, attrs, &cs->gicr_inmir0, value);
65
+ }
66
+ return MEMTX_OK;
67
+
68
case GICR_ICFGR0:
69
/* Register is all RAZ/WI or RAO/WI bits */
70
return MEMTX_OK;
71
--
72
2.34.1
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0.
4
5
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/intc/gicv3_internal.h | 2 ++
12
hw/intc/arm_gicv3_dist.c | 34 ++++++++++++++++++++++++++++++++++
13
2 files changed, 36 insertions(+)
14
15
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/gicv3_internal.h
18
+++ b/hw/intc/gicv3_internal.h
19
@@ -XXX,XX +XXX,XX @@
20
#define GICD_SGIR 0x0F00
21
#define GICD_CPENDSGIR 0x0F10
22
#define GICD_SPENDSGIR 0x0F20
23
+#define GICD_INMIR 0x0F80
24
+#define GICD_INMIRnE 0x3B00
25
#define GICD_IROUTER 0x6000
26
#define GICD_IDREGS 0xFFD0
27
28
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/intc/arm_gicv3_dist.c
31
+++ b/hw/intc/arm_gicv3_dist.c
32
@@ -XXX,XX +XXX,XX @@ static int gicd_ns_access(GICv3State *s, int irq)
33
return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2);
34
}
35
36
+static void gicd_write_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
37
+ uint32_t *bmp, maskfn *maskfn,
38
+ int offset, uint32_t val)
39
+{
40
+ /*
41
+ * Helper routine to implement writing to a "set" register
42
+ * (GICD_INMIR, etc).
43
+ * Semantics implemented here:
44
+ * RAZ/WI for SGIs, PPIs, unimplemented IRQs
45
+ * Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI.
46
+ * offset should be the offset in bytes of the register from the start
47
+ * of its group.
48
+ */
49
+ int irq = offset * 8;
50
+
51
+ if (irq < GIC_INTERNAL || irq >= s->num_irq) {
52
+ return;
53
+ }
54
+ val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
55
+ *gic_bmp_ptr32(bmp, irq) = val;
56
+ gicv3_update(s, irq, 32);
57
+}
58
+
59
static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
60
uint32_t *bmp,
61
maskfn *maskfn,
62
@@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
63
/* RAZ/WI since affinity routing is always enabled */
64
*data = 0;
65
return true;
66
+ case GICD_INMIR ... GICD_INMIR + 0x7f:
67
+ *data = (!s->nmi_support) ? 0 :
68
+ gicd_read_bitmap_reg(s, attrs, s->nmi, NULL,
69
+ offset - GICD_INMIR);
70
+ return true;
71
case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
72
{
73
uint64_t r;
74
@@ -XXX,XX +XXX,XX @@ static bool gicd_writel(GICv3State *s, hwaddr offset,
75
case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
76
/* RAZ/WI since affinity routing is always enabled */
77
return true;
78
+ case GICD_INMIR ... GICD_INMIR + 0x7f:
79
+ if (s->nmi_support) {
80
+ gicd_write_bitmap_reg(s, attrs, s->nmi, NULL,
81
+ offset - GICD_INMIR, value);
82
+ }
83
+ return true;
84
case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
85
{
86
uint64_t r;
87
--
88
2.34.1
diff view generated by jsdifflib
New patch
1
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
1
2
3
When introduce NMI interrupt, there are some updates to the semantics for the
4
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
5
should return 1022 if the intid has non-maskable property. And for
6
ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have
7
non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1
8
register.
9
10
And the APR and RPR has NMI bits which should be handled correctly.
11
12
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
[PMM: Separate out whether cpuif supports NMI from whether the
15
GIC proper (IRI) supports NMI]
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/intc/gicv3_internal.h | 5 +
21
include/hw/intc/arm_gicv3_common.h | 7 ++
22
hw/intc/arm_gicv3_cpuif.c | 147 ++++++++++++++++++++++++++++-
23
hw/intc/trace-events | 1 +
24
4 files changed, 155 insertions(+), 5 deletions(-)
25
26
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/intc/gicv3_internal.h
29
+++ b/hw/intc/gicv3_internal.h
30
@@ -XXX,XX +XXX,XX @@ FIELD(GICR_VPENDBASER, VALID, 63, 1)
31
#define ICC_CTLR_EL3_A3V (1U << 15)
32
#define ICC_CTLR_EL3_NDS (1U << 17)
33
34
+#define ICC_AP1R_EL1_NMI (1ULL << 63)
35
+#define ICC_RPR_EL1_NSNMI (1ULL << 62)
36
+#define ICC_RPR_EL1_NMI (1ULL << 63)
37
+
38
#define ICH_VMCR_EL2_VENG0_SHIFT 0
39
#define ICH_VMCR_EL2_VENG0 (1U << ICH_VMCR_EL2_VENG0_SHIFT)
40
#define ICH_VMCR_EL2_VENG1_SHIFT 1
41
@@ -XXX,XX +XXX,XX @@ FIELD(VTE, RDBASE, 42, RDBASE_PROCNUM_LENGTH)
42
/* Special interrupt IDs */
43
#define INTID_SECURE 1020
44
#define INTID_NONSECURE 1021
45
+#define INTID_NMI 1022
46
#define INTID_SPURIOUS 1023
47
48
/* Functions internal to the emulated GICv3 */
49
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
50
index XXXXXXX..XXXXXXX 100644
51
--- a/include/hw/intc/arm_gicv3_common.h
52
+++ b/include/hw/intc/arm_gicv3_common.h
53
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
54
55
/* This is temporary working state, to avoid a malloc in gicv3_update() */
56
bool seenbetter;
57
+
58
+ /*
59
+ * Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The
60
+ * CPU interface may support NMIs even when the GIC proper (what the
61
+ * spec calls the IRI; the redistributors and distributor) does not.
62
+ */
63
+ bool nmi_support;
64
};
65
66
/*
67
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/hw/intc/arm_gicv3_cpuif.c
70
+++ b/hw/intc/arm_gicv3_cpuif.c
71
@@ -XXX,XX +XXX,XX @@
72
#include "hw/irq.h"
73
#include "cpu.h"
74
#include "target/arm/cpregs.h"
75
+#include "target/arm/cpu-features.h"
76
#include "sysemu/tcg.h"
77
#include "sysemu/qtest.h"
78
79
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
80
return intid;
81
}
82
83
+static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
84
+{
85
+ /* todo */
86
+ uint64_t intid = INTID_SPURIOUS;
87
+ return intid;
88
+}
89
+
90
static uint32_t icc_fullprio_mask(GICv3CPUState *cs)
91
{
92
/*
93
@@ -XXX,XX +XXX,XX @@ static int icc_highest_active_prio(GICv3CPUState *cs)
94
*/
95
int i;
96
97
+ if (cs->nmi_support) {
98
+ /*
99
+ * If an NMI is active this takes precedence over anything else
100
+ * for priority purposes; the NMI bit is only in the AP1R0 bit.
101
+ * We return here the effective priority of the NMI, which is
102
+ * either 0x0 or 0x80. Callers will need to check NMI again for
103
+ * purposes of either setting the RPR register bits or for
104
+ * prioritization of NMI vs non-NMI.
105
+ */
106
+ if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) {
107
+ return 0;
108
+ }
109
+ if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) {
110
+ return (cs->gic->gicd_ctlr & GICD_CTLR_DS) ? 0 : 0x80;
111
+ }
112
+ }
113
+
114
for (i = 0; i < icc_num_aprs(cs); i++) {
115
uint32_t apr = cs->icc_apr[GICV3_G0][i] |
116
cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i];
117
@@ -XXX,XX +XXX,XX @@ static bool icc_hppi_can_preempt(GICv3CPUState *cs)
118
*/
119
int rprio;
120
uint32_t mask;
121
+ ARMCPU *cpu = ARM_CPU(cs->cpu);
122
+ CPUARMState *env = &cpu->env;
123
124
if (icc_no_enabled_hppi(cs)) {
125
return false;
126
}
127
128
- if (cs->hppi.prio >= cs->icc_pmr_el1) {
129
+ if (cs->hppi.nmi) {
130
+ if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
131
+ cs->hppi.grp == GICV3_G1NS) {
132
+ if (cs->icc_pmr_el1 < 0x80) {
133
+ return false;
134
+ }
135
+ if (arm_is_secure(env) && cs->icc_pmr_el1 == 0x80) {
136
+ return false;
137
+ }
138
+ }
139
+ } else if (cs->hppi.prio >= cs->icc_pmr_el1) {
140
/* Priority mask masks this interrupt */
141
return false;
142
}
143
@@ -XXX,XX +XXX,XX @@ static bool icc_hppi_can_preempt(GICv3CPUState *cs)
144
return true;
145
}
146
147
+ if (cs->hppi.nmi && (cs->hppi.prio & mask) == (rprio & mask)) {
148
+ if (!(cs->icc_apr[cs->hppi.grp][0] & ICC_AP1R_EL1_NMI)) {
149
+ return true;
150
+ }
151
+ }
152
+
153
return false;
154
}
155
156
@@ -XXX,XX +XXX,XX @@ static void icc_activate_irq(GICv3CPUState *cs, int irq)
157
int aprbit = prio >> (8 - cs->prebits);
158
int regno = aprbit / 32;
159
int regbit = aprbit % 32;
160
+ bool nmi = cs->hppi.nmi;
161
162
- cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit);
163
+ if (nmi) {
164
+ cs->icc_apr[cs->hppi.grp][regno] |= ICC_AP1R_EL1_NMI;
165
+ } else {
166
+ cs->icc_apr[cs->hppi.grp][regno] |= (1 << regbit);
167
+ }
168
169
if (irq < GIC_INTERNAL) {
170
cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1);
171
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_iar0_read(CPUARMState *env, const ARMCPRegInfo *ri)
172
static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
173
{
174
GICv3CPUState *cs = icc_cs_from_env(env);
175
+ int el = arm_current_el(env);
176
uint64_t intid;
177
178
if (icv_access(env, HCR_IMO)) {
179
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_iar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
180
}
181
182
if (!gicv3_intid_is_special(intid)) {
183
- icc_activate_irq(cs, intid);
184
+ if (cs->hppi.nmi && env->cp15.sctlr_el[el] & SCTLR_NMI) {
185
+ intid = INTID_NMI;
186
+ } else {
187
+ icc_activate_irq(cs, intid);
188
+ }
189
}
190
191
trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid);
192
return intid;
193
}
194
195
+static uint64_t icc_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
196
+{
197
+ GICv3CPUState *cs = icc_cs_from_env(env);
198
+ uint64_t intid;
199
+
200
+ if (icv_access(env, HCR_IMO)) {
201
+ return icv_nmiar1_read(env, ri);
202
+ }
203
+
204
+ if (!icc_hppi_can_preempt(cs)) {
205
+ intid = INTID_SPURIOUS;
206
+ } else {
207
+ intid = icc_hppir1_value(cs, env);
208
+ }
209
+
210
+ if (!gicv3_intid_is_special(intid)) {
211
+ if (!cs->hppi.nmi) {
212
+ intid = INTID_SPURIOUS;
213
+ } else {
214
+ icc_activate_irq(cs, intid);
215
+ }
216
+ }
217
+
218
+ trace_gicv3_icc_nmiar1_read(gicv3_redist_affid(cs), intid);
219
+ return intid;
220
+}
221
+
222
static void icc_drop_prio(GICv3CPUState *cs, int grp)
223
{
224
/* Drop the priority of the currently active interrupt in
225
@@ -XXX,XX +XXX,XX @@ static void icc_drop_prio(GICv3CPUState *cs, int grp)
226
if (!*papr) {
227
continue;
228
}
229
+
230
+ if (i == 0 && cs->nmi_support && (*papr & ICC_AP1R_EL1_NMI)) {
231
+ *papr &= (~ICC_AP1R_EL1_NMI);
232
+ break;
233
+ }
234
+
235
/* Clear the lowest set bit */
236
*papr &= *papr - 1;
237
break;
238
@@ -XXX,XX +XXX,XX @@ static int icc_highest_active_group(GICv3CPUState *cs)
239
*/
240
int i;
241
242
+ if (cs->nmi_support) {
243
+ if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) {
244
+ return GICV3_G1;
245
+ }
246
+ if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) {
247
+ return GICV3_G1NS;
248
+ }
249
+ }
250
+
251
for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) {
252
int g0ctz = ctz32(cs->icc_apr[GICV3_G0][i]);
253
int g1ctz = ctz32(cs->icc_apr[GICV3_G1][i]);
254
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
255
return;
256
}
257
258
- cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU;
259
+ if (cs->nmi_support) {
260
+ cs->icc_apr[grp][regno] = value & (0xFFFFFFFFU | ICC_AP1R_EL1_NMI);
261
+ } else {
262
+ cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU;
263
+ }
264
gicv3_cpuif_update(cs);
265
}
266
267
@@ -XXX,XX +XXX,XX @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
268
static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
269
{
270
GICv3CPUState *cs = icc_cs_from_env(env);
271
- int prio;
272
+ uint64_t prio;
273
274
if (icv_access(env, HCR_FMO | HCR_IMO)) {
275
return icv_rpr_read(env, ri);
276
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
277
}
278
}
279
280
+ if (cs->nmi_support) {
281
+ /* NMI info is reported in the high bits of RPR */
282
+ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env)) {
283
+ if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) {
284
+ prio |= ICC_RPR_EL1_NMI;
285
+ }
286
+ } else {
287
+ if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) {
288
+ prio |= ICC_RPR_EL1_NSNMI;
289
+ }
290
+ if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) {
291
+ prio |= ICC_RPR_EL1_NMI;
292
+ }
293
+ }
294
+ }
295
+
296
trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio);
297
return prio;
298
}
299
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo gicv3_cpuif_icc_apxr23_reginfo[] = {
300
},
301
};
302
303
+static const ARMCPRegInfo gicv3_cpuif_gicv3_nmi_reginfo[] = {
304
+ { .name = "ICC_NMIAR1_EL1", .state = ARM_CP_STATE_BOTH,
305
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 5,
306
+ .type = ARM_CP_IO | ARM_CP_NO_RAW,
307
+ .access = PL1_R, .accessfn = gicv3_irq_access,
308
+ .readfn = icc_nmiar1_read,
309
+ },
310
+};
311
+
312
static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
313
{
314
GICv3CPUState *cs = icc_cs_from_env(env);
315
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
316
*/
317
define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
318
319
+ /*
320
+ * If the CPU implements FEAT_NMI and FEAT_GICv3 it must also
321
+ * implement FEAT_GICv3_NMI, which is the CPU interface part
322
+ * of NMI support. This is distinct from whether the GIC proper
323
+ * (redistributors and distributor) have NMI support. In QEMU
324
+ * that is a property of the GIC device in s->nmi_support;
325
+ * cs->nmi_support indicates the CPU interface's support.
326
+ */
327
+ if (cpu_isar_feature(aa64_nmi, cpu)) {
328
+ cs->nmi_support = true;
329
+ define_arm_cp_regs(cpu, gicv3_cpuif_gicv3_nmi_reginfo);
330
+ }
331
+
332
/*
333
* The CPU implementation specifies the number of supported
334
* bits of physical priority. For backwards compatibility
335
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
336
index XXXXXXX..XXXXXXX 100644
337
--- a/hw/intc/trace-events
338
+++ b/hw/intc/trace-events
339
@@ -XXX,XX +XXX,XX @@ gicv3_cpuif_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f
340
gicv3_icc_generate_sgi(uint32_t cpuid, int irq, int irm, uint32_t aff, uint32_t targetlist) "GICv3 CPU i/f 0x%x generating SGI %d IRM %d target affinity 0x%xxx targetlist 0x%x"
341
gicv3_icc_iar0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR0 read cpu 0x%x value 0x%" PRIx64
342
gicv3_icc_iar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_IAR1 read cpu 0x%x value 0x%" PRIx64
343
+gicv3_icc_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_NMIAR1 read cpu 0x%x value 0x%" PRIx64
344
gicv3_icc_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICC_EOIR%d write cpu 0x%x value 0x%" PRIx64
345
gicv3_icc_hppir0_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR0 read cpu 0x%x value 0x%" PRIx64
346
gicv3_icc_hppir1_read(uint32_t cpu, uint64_t val) "GICv3 ICC_HPPIR1 read cpu 0x%x value 0x%" PRIx64
347
--
348
2.34.1
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for
2
2
ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit.
3
We can then use this to improve VMOV (scalar to gp) and
3
4
VMOV (gp to scalar) so that we simply perform the memory
4
If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI
5
operation that we wanted, rather than inserting or
5
bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit
6
extracting from a 32-bit quantity.
6
should be set or clear according to the Non-maskable property. And the RPR
7
7
priority should also update the NMI bit according to the APR priority NMI bit.
8
These were the last uses of neon_load/store_reg, so remove them.
8
9
9
By the way, add gicv3_icv_nmiar1_read trace event.
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
11
Message-id: 20201030022618.785675-7-richard.henderson@linaro.org
11
If the hpp irq is a NMI, the icv iar read should return 1022 and trap for
12
NMI again
13
14
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
[PMM: use cs->nmi_support instead of cs->gic->nmi_support]
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
20
---
15
target/arm/translate.c | 50 +++++++++++++-----------
21
hw/intc/gicv3_internal.h | 4 ++
16
target/arm/translate-vfp.c.inc | 71 +++++-----------------------------
22
hw/intc/arm_gicv3_cpuif.c | 105 +++++++++++++++++++++++++++++++++-----
17
2 files changed, 37 insertions(+), 84 deletions(-)
23
hw/intc/trace-events | 1 +
18
24
3 files changed, 98 insertions(+), 12 deletions(-)
19
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
26
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
20
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate.c
28
--- a/hw/intc/gicv3_internal.h
22
+++ b/target/arm/translate.c
29
+++ b/hw/intc/gicv3_internal.h
23
@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
30
@@ -XXX,XX +XXX,XX @@ FIELD(GICR_VPENDBASER, VALID, 63, 1)
24
* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
31
#define ICH_LR_EL2_PRIORITY_SHIFT 48
25
* where 0 is the least significant end of the register.
32
#define ICH_LR_EL2_PRIORITY_LENGTH 8
26
*/
33
#define ICH_LR_EL2_PRIORITY_MASK (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT)
27
-static long neon_element_offset(int reg, int element, MemOp size)
34
+#define ICH_LR_EL2_NMI (1ULL << 59)
28
+static long neon_element_offset(int reg, int element, MemOp memop)
35
#define ICH_LR_EL2_GROUP (1ULL << 60)
29
{
36
#define ICH_LR_EL2_HW (1ULL << 61)
30
- int element_size = 1 << size;
37
#define ICH_LR_EL2_STATE_SHIFT 62
31
+ int element_size = 1 << (memop & MO_SIZE);
38
@@ -XXX,XX +XXX,XX @@ FIELD(GICR_VPENDBASER, VALID, 63, 1)
32
int ofs = element * element_size;
39
#define ICH_VTR_EL2_PREBITS_SHIFT 26
33
#ifdef HOST_WORDS_BIGENDIAN
40
#define ICH_VTR_EL2_PRIBITS_SHIFT 29
34
/*
41
35
@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
42
+#define ICV_AP1R_EL1_NMI (1ULL << 63)
43
+#define ICV_RPR_EL1_NMI (1ULL << 63)
44
+
45
/* ITS Registers */
46
47
FIELD(GITS_BASER, SIZE, 0, 8)
48
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/intc/arm_gicv3_cpuif.c
51
+++ b/hw/intc/arm_gicv3_cpuif.c
52
@@ -XXX,XX +XXX,XX @@ static int ich_highest_active_virt_prio(GICv3CPUState *cs)
53
int i;
54
int aprmax = ich_num_aprs(cs);
55
56
+ if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) {
57
+ return 0x0;
58
+ }
59
+
60
for (i = 0; i < aprmax; i++) {
61
uint32_t apr = cs->ich_apr[GICV3_G0][i] |
62
cs->ich_apr[GICV3_G1NS][i];
63
@@ -XXX,XX +XXX,XX @@ static int hppvi_index(GICv3CPUState *cs)
64
* correct behaviour.
65
*/
66
int prio = 0xff;
67
+ bool nmi = false;
68
69
if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) {
70
/* Both groups disabled, definitely nothing to do */
71
@@ -XXX,XX +XXX,XX @@ static int hppvi_index(GICv3CPUState *cs)
72
73
for (i = 0; i < cs->num_list_regs; i++) {
74
uint64_t lr = cs->ich_lr_el2[i];
75
+ bool thisnmi;
76
int thisprio;
77
78
if (ich_lr_state(lr) != ICH_LR_EL2_STATE_PENDING) {
79
@@ -XXX,XX +XXX,XX @@ static int hppvi_index(GICv3CPUState *cs)
80
}
81
}
82
83
+ thisnmi = lr & ICH_LR_EL2_NMI;
84
thisprio = ich_lr_prio(lr);
85
86
- if (thisprio < prio) {
87
+ if ((thisprio < prio) || ((thisprio == prio) && (thisnmi & (!nmi)))) {
88
prio = thisprio;
89
+ nmi = thisnmi;
90
idx = i;
91
}
36
}
92
}
37
}
93
@@ -XXX,XX +XXX,XX @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
38
94
* equivalent of these checks.
39
-static TCGv_i32 neon_load_reg(int reg, int pass)
95
*/
40
-{
96
int grp;
41
- TCGv_i32 tmp = tcg_temp_new_i32();
97
+ bool is_nmi;
42
- tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
98
uint32_t mask, prio, rprio, vpmr;
43
- return tmp;
99
44
-}
100
if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) {
45
-
101
@@ -XXX,XX +XXX,XX @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
46
-static void neon_store_reg(int reg, int pass, TCGv_i32 var)
102
*/
47
-{
103
48
- tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
104
prio = ich_lr_prio(lr);
49
- tcg_temp_free_i32(var);
105
+ is_nmi = lr & ICH_LR_EL2_NMI;
50
-}
106
vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
51
-
107
ICH_VMCR_EL2_VPMR_LENGTH);
52
static inline void neon_load_reg64(TCGv_i64 var, int reg)
108
53
{
109
- if (prio >= vpmr) {
54
tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
110
+ if (!is_nmi && prio >= vpmr) {
55
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
111
/* Priority mask masks this interrupt */
56
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
57
}
58
59
-static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
60
+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
61
{
62
- long off = neon_element_offset(reg, ele, size);
63
+ long off = neon_element_offset(reg, ele, memop);
64
65
- switch (size) {
66
- case MO_32:
67
+ switch (memop) {
68
+ case MO_SB:
69
+ tcg_gen_ld8s_i32(dest, cpu_env, off);
70
+ break;
71
+ case MO_UB:
72
+ tcg_gen_ld8u_i32(dest, cpu_env, off);
73
+ break;
74
+ case MO_SW:
75
+ tcg_gen_ld16s_i32(dest, cpu_env, off);
76
+ break;
77
+ case MO_UW:
78
+ tcg_gen_ld16u_i32(dest, cpu_env, off);
79
+ break;
80
+ case MO_UL:
81
+ case MO_SL:
82
tcg_gen_ld_i32(dest, cpu_env, off);
83
break;
84
default:
85
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
86
}
87
}
88
89
-static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
90
+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
91
{
92
- long off = neon_element_offset(reg, ele, size);
93
+ long off = neon_element_offset(reg, ele, memop);
94
95
- switch (size) {
96
+ switch (memop) {
97
+ case MO_8:
98
+ tcg_gen_st8_i32(src, cpu_env, off);
99
+ break;
100
+ case MO_16:
101
+ tcg_gen_st16_i32(src, cpu_env, off);
102
+ break;
103
case MO_32:
104
tcg_gen_st_i32(src, cpu_env, off);
105
break;
106
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-vfp.c.inc
109
+++ b/target/arm/translate-vfp.c.inc
110
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
111
{
112
/* VMOV scalar to general purpose register */
113
TCGv_i32 tmp;
114
- int pass;
115
- uint32_t offset;
116
117
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
118
- if (a->size == 2
119
+ /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
120
+ if (a->size == MO_32
121
? !dc_isar_feature(aa32_fpsp_v2, s)
122
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
123
return false;
124
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
125
return false;
112
return false;
126
}
113
}
127
114
@@ -XXX,XX +XXX,XX @@ static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr)
128
- offset = a->index << a->size;
129
- pass = extract32(offset, 2, 1);
130
- offset = extract32(offset, 0, 2) * 8;
131
-
132
if (!vfp_access_check(s)) {
133
return true;
115
return true;
134
}
116
}
135
117
136
- tmp = neon_load_reg(a->vn, pass);
118
+ if ((prio & mask) == (rprio & mask) && is_nmi &&
137
- switch (a->size) {
119
+ !(cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI)) {
138
- case 0:
120
+ return true;
139
- if (offset) {
121
+ }
140
- tcg_gen_shri_i32(tmp, tmp, offset);
122
+
141
- }
123
return false;
142
- if (a->u) {
124
}
143
- gen_uxtb(tmp);
125
144
- } else {
126
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
145
- gen_sxtb(tmp);
127
146
- }
128
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
147
- break;
129
148
- case 1:
130
- cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
149
- if (a->u) {
131
+ if (cs->nmi_support) {
150
- if (offset) {
132
+ cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI);
151
- tcg_gen_shri_i32(tmp, tmp, 16);
133
+ } else {
152
- } else {
134
+ cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
153
- gen_uxth(tmp);
135
+ }
154
- }
136
155
- } else {
137
gicv3_cpuif_virt_irq_fiq_update(cs);
156
- if (offset) {
138
return;
157
- tcg_gen_sari_i32(tmp, tmp, 16);
139
@@ -XXX,XX +XXX,XX @@ static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
158
- } else {
140
static uint64_t icv_rpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
159
- gen_sxth(tmp);
160
- }
161
- }
162
- break;
163
- case 2:
164
- break;
165
- }
166
+ tmp = tcg_temp_new_i32();
167
+ read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN));
168
store_reg(s, a->rt, tmp);
169
170
return true;
171
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
172
static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
173
{
141
{
174
/* VMOV general purpose register to scalar */
142
GICv3CPUState *cs = icc_cs_from_env(env);
175
- TCGv_i32 tmp, tmp2;
143
- int prio = ich_highest_active_virt_prio(cs);
176
- int pass;
144
+ uint64_t prio = ich_highest_active_virt_prio(cs);
177
- uint32_t offset;
145
+
178
+ TCGv_i32 tmp;
146
+ if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) {
179
147
+ prio |= ICV_RPR_EL1_NMI;
180
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
148
+ }
181
- if (a->size == 2
149
182
+ /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
150
trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio);
183
+ if (a->size == MO_32
151
return prio;
184
? !dc_isar_feature(aa32_fpsp_v2, s)
152
@@ -XXX,XX +XXX,XX @@ static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp)
185
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
153
*/
186
return false;
154
uint32_t mask = icv_gprio_mask(cs, grp);
187
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
155
int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask;
188
return false;
156
+ bool nmi = cs->ich_lr_el2[idx] & ICH_LR_EL2_NMI;
157
int aprbit = prio >> (8 - cs->vprebits);
158
int regno = aprbit / 32;
159
int regbit = aprbit % 32;
160
161
cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
162
cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT;
163
- cs->ich_apr[grp][regno] |= (1 << regbit);
164
+
165
+ if (nmi) {
166
+ cs->ich_apr[grp][regno] |= ICV_AP1R_EL1_NMI;
167
+ } else {
168
+ cs->ich_apr[grp][regno] |= (1 << regbit);
169
+ }
170
}
171
172
static void icv_activate_vlpi(GICv3CPUState *cs)
173
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
174
int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
175
int idx = hppvi_index(cs);
176
uint64_t intid = INTID_SPURIOUS;
177
+ int el = arm_current_el(env);
178
179
if (idx == HPPVI_INDEX_VLPI) {
180
if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) {
181
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
182
} else if (idx >= 0) {
183
uint64_t lr = cs->ich_lr_el2[idx];
184
int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
185
+ bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI;
186
187
if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) {
188
intid = ich_lr_vintid(lr);
189
if (!gicv3_intid_is_special(intid)) {
190
- icv_activate_irq(cs, idx, grp);
191
+ if (!nmi) {
192
+ icv_activate_irq(cs, idx, grp);
193
+ } else {
194
+ intid = INTID_NMI;
195
+ }
196
} else {
197
/* Interrupt goes from Pending to Invalid */
198
cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
199
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri)
200
201
static uint64_t icv_nmiar1_read(CPUARMState *env, const ARMCPRegInfo *ri)
202
{
203
- /* todo */
204
+ GICv3CPUState *cs = icc_cs_from_env(env);
205
+ int idx = hppvi_index(cs);
206
uint64_t intid = INTID_SPURIOUS;
207
+
208
+ if (idx >= 0 && idx != HPPVI_INDEX_VLPI) {
209
+ uint64_t lr = cs->ich_lr_el2[idx];
210
+ int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
211
+
212
+ if ((thisgrp == GICV3_G1NS) && icv_hppi_can_preempt(cs, lr)) {
213
+ intid = ich_lr_vintid(lr);
214
+ if (!gicv3_intid_is_special(intid)) {
215
+ if (lr & ICH_LR_EL2_NMI) {
216
+ icv_activate_irq(cs, idx, GICV3_G1NS);
217
+ } else {
218
+ intid = INTID_SPURIOUS;
219
+ }
220
+ } else {
221
+ /* Interrupt goes from Pending to Invalid */
222
+ cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT;
223
+ /*
224
+ * We will now return the (bogus) ID from the list register,
225
+ * as per the pseudocode.
226
+ */
227
+ }
228
+ }
229
+ }
230
+
231
+ trace_gicv3_icv_nmiar1_read(gicv3_redist_affid(cs), intid);
232
+
233
+ gicv3_cpuif_virt_update(cs);
234
+
235
return intid;
236
}
237
238
@@ -XXX,XX +XXX,XX @@ static void icv_increment_eoicount(GICv3CPUState *cs)
239
ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1);
240
}
241
242
-static int icv_drop_prio(GICv3CPUState *cs)
243
+static int icv_drop_prio(GICv3CPUState *cs, bool *nmi)
244
{
245
/* Drop the priority of the currently active virtual interrupt
246
* (favouring group 0 if there is a set active bit at
247
@@ -XXX,XX +XXX,XX @@ static int icv_drop_prio(GICv3CPUState *cs)
248
continue;
249
}
250
251
+ if (i == 0 && cs->nmi_support && (*papr1 & ICV_AP1R_EL1_NMI)) {
252
+ *papr1 &= (~ICV_AP1R_EL1_NMI);
253
+ *nmi = true;
254
+ return 0xff;
255
+ }
256
+
257
/* We can't just use the bit-twiddling hack icc_drop_prio() does
258
* because we need to return the bit number we cleared so
259
* it can be compared against the list register's priority field.
260
@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
261
int irq = value & 0xffffff;
262
int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS;
263
int idx, dropprio;
264
+ bool nmi = false;
265
266
trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
267
gicv3_redist_affid(cs), value);
268
@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
269
* error checks" (because that lets us avoid scanning the AP
270
* registers twice).
271
*/
272
- dropprio = icv_drop_prio(cs);
273
- if (dropprio == 0xff) {
274
+ dropprio = icv_drop_prio(cs, &nmi);
275
+ if (dropprio == 0xff && !nmi) {
276
/* No active interrupt. It is CONSTRAINED UNPREDICTABLE
277
* whether the list registers are checked in this
278
* situation; we choose not to.
279
@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
280
uint64_t lr = cs->ich_lr_el2[idx];
281
int thisgrp = (lr & ICH_LR_EL2_GROUP) ? GICV3_G1NS : GICV3_G0;
282
int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp);
283
+ bool thisnmi = lr & ICH_LR_EL2_NMI;
284
285
- if (thisgrp == grp && lr_gprio == dropprio) {
286
+ if (thisgrp == grp && (lr_gprio == dropprio || (thisnmi & nmi))) {
287
if (!icv_eoi_split(env, cs) || irq >= GICV3_LPI_INTID_START) {
288
/*
289
* Priority drop and deactivate not split: deactivate irq now.
290
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
291
292
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
293
294
- cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
295
+ if (cs->nmi_support) {
296
+ cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI);
297
+ } else {
298
+ cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
299
+ }
300
gicv3_cpuif_virt_irq_fiq_update(cs);
301
}
302
303
@@ -XXX,XX +XXX,XX @@ static void ich_lr_write(CPUARMState *env, const ARMCPRegInfo *ri,
304
8 - cs->vpribits, 0);
189
}
305
}
190
306
191
- offset = a->index << a->size;
307
+ /* Enforce RES0 bit in NMI field when FEAT_GICv3_NMI is not implemented */
192
- pass = extract32(offset, 2, 1);
308
+ if (!cs->nmi_support) {
193
- offset = extract32(offset, 0, 2) * 8;
309
+ value &= ~ICH_LR_EL2_NMI;
194
-
310
+ }
195
if (!vfp_access_check(s)) {
311
+
196
return true;
312
cs->ich_lr_el2[regno] = value;
197
}
313
gicv3_cpuif_virt_update(cs);
198
314
}
199
tmp = load_reg(s, a->rt);
315
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
200
- switch (a->size) {
316
index XXXXXXX..XXXXXXX 100644
201
- case 0:
317
--- a/hw/intc/trace-events
202
- tmp2 = neon_load_reg(a->vn, pass);
318
+++ b/hw/intc/trace-events
203
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
319
@@ -XXX,XX +XXX,XX @@ gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu 0x%x valu
204
- tcg_temp_free_i32(tmp2);
320
gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d read cpu 0x%x value 0x%" PRIx64
205
- break;
321
gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu 0x%x value 0x%" PRIx64
206
- case 1:
322
gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu 0x%x value 0x%" PRIx64
207
- tmp2 = neon_load_reg(a->vn, pass);
323
+gicv3_icv_nmiar1_read(uint32_t cpu, uint64_t val) "GICv3 ICV_NMIAR1 read cpu 0x%x value 0x%" PRIx64
208
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
324
gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu 0x%x value 0x%" PRIx64
209
- tcg_temp_free_i32(tmp2);
325
gicv3_cpuif_virt_update(uint32_t cpuid, int idx, int hppvlpi, int grp, int prio) "GICv3 CPU i/f 0x%x virt HPPI update LR index %d HPPVLPI %d grp %d prio %d"
210
- break;
326
gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel) "GICv3 CPU i/f 0x%x virt HPPI update: setting FIQ %d IRQ %d"
211
- case 2:
212
- break;
213
- }
214
- neon_store_reg(a->vn, pass, tmp);
215
+ write_neon_element32(tmp, a->vn, a->index, a->size);
216
+ tcg_temp_free_i32(tmp);
217
218
return true;
219
}
220
--
327
--
221
2.20.1
328
2.34.1
222
223
diff view generated by jsdifflib
1
From: AlexChen <alex.chen@huawei.com>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before
3
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is
4
being check if it is valid, which may lead to NULL pointer dereference.
4
higher than 0x80, otherwise it is higher than 0x0. And save the interrupt
5
So move the assignment to surface after checking that the omap_lcd is valid
5
non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR
6
and move surface_bits_per_pixel(surface) to after the surface assignment.
6
and GICD can deliver NMI, it is both necessary to check whether the pending
7
irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset.
7
8
8
Reported-by: Euler Robot <euler.robot@huawei.com>
9
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
9
Signed-off-by: AlexChen <alex.chen@huawei.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 5F9CDB8A.9000001@huawei.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
---
14
hw/display/omap_lcdc.c | 10 +++++++---
15
hw/intc/arm_gicv3.c | 67 +++++++++++++++++++++++++++++++++-----
15
1 file changed, 7 insertions(+), 3 deletions(-)
16
hw/intc/arm_gicv3_common.c | 3 ++
17
hw/intc/arm_gicv3_redist.c | 3 ++
18
3 files changed, 64 insertions(+), 9 deletions(-)
16
19
17
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
20
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
18
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/display/omap_lcdc.c
22
--- a/hw/intc/arm_gicv3.c
20
+++ b/hw/display/omap_lcdc.c
23
+++ b/hw/intc/arm_gicv3.c
21
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
24
@@ -XXX,XX +XXX,XX @@
22
static void omap_update_display(void *opaque)
25
#include "hw/intc/arm_gicv3.h"
26
#include "gicv3_internal.h"
27
28
-static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
29
+static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi)
23
{
30
{
24
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
31
/* Return true if this IRQ at this priority should take
25
- DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
32
* precedence over the current recorded highest priority
26
+ DisplaySurface *surface;
33
@@ -XXX,XX +XXX,XX @@ static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
27
draw_line_func draw_line;
34
* is the same as this one (a property which the calling code
28
int size, height, first, last;
35
* relies on).
29
int width, linesize, step, bpp, frame_offset;
36
*/
30
hwaddr frame_base;
37
- if (prio < cs->hppi.prio) {
31
38
- return true;
32
- if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable ||
39
+ if (prio != cs->hppi.prio) {
33
- !surface_bits_per_pixel(surface)) {
40
+ return prio < cs->hppi.prio;
34
+ if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) {
41
}
35
+ return;
42
+
36
+ }
43
+ /*
37
+
44
+ * The same priority IRQ with non-maskable property should signal to
38
+ surface = qemu_console_surface(omap_lcd->con);
45
+ * the CPU as it have the priority higher than the labelled 0x80 or 0x00.
39
+ if (!surface_bits_per_pixel(surface)) {
46
+ */
47
+ if (nmi != cs->hppi.nmi) {
48
+ return nmi;
49
+ }
50
+
51
/* If multiple pending interrupts have the same priority then it is an
52
* IMPDEF choice which of them to signal to the CPU. We choose to
53
* signal the one with the lowest interrupt number.
54
*/
55
- if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
56
+ if (irq <= cs->hppi.irq) {
57
return true;
58
}
59
return false;
60
@@ -XXX,XX +XXX,XX @@ static uint32_t gicr_int_pending(GICv3CPUState *cs)
61
return pend;
62
}
63
64
+static bool gicv3_get_priority(GICv3CPUState *cs, bool is_redist, int irq,
65
+ uint8_t *prio)
66
+{
67
+ uint32_t nmi = 0x0;
68
+
69
+ if (is_redist) {
70
+ nmi = extract32(cs->gicr_inmir0, irq, 1);
71
+ } else {
72
+ nmi = *gic_bmp_ptr32(cs->gic->nmi, irq);
73
+ nmi = nmi & (1 << (irq & 0x1f));
74
+ }
75
+
76
+ if (nmi) {
77
+ /* DS = 0 & Non-secure NMI */
78
+ if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
79
+ ((is_redist && extract32(cs->gicr_igroupr0, irq, 1)) ||
80
+ (!is_redist && gicv3_gicd_group_test(cs->gic, irq)))) {
81
+ *prio = 0x80;
82
+ } else {
83
+ *prio = 0x0;
84
+ }
85
+
86
+ return true;
87
+ }
88
+
89
+ if (is_redist) {
90
+ *prio = cs->gicr_ipriorityr[irq];
91
+ } else {
92
+ *prio = cs->gic->gicd_ipriority[irq];
93
+ }
94
+
95
+ return false;
96
+}
97
+
98
/* Update the interrupt status after state in a redistributor
99
* or CPU interface has changed, but don't tell the CPU i/f.
100
*/
101
@@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
102
uint8_t prio;
103
int i;
104
uint32_t pend;
105
+ bool nmi = false;
106
107
/* Find out which redistributor interrupts are eligible to be
108
* signaled to the CPU interface.
109
@@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
110
if (!(pend & (1 << i))) {
111
continue;
112
}
113
- prio = cs->gicr_ipriorityr[i];
114
- if (irqbetter(cs, i, prio)) {
115
+ nmi = gicv3_get_priority(cs, true, i, &prio);
116
+ if (irqbetter(cs, i, prio, nmi)) {
117
cs->hppi.irq = i;
118
cs->hppi.prio = prio;
119
+ cs->hppi.nmi = nmi;
120
seenbetter = true;
121
}
122
}
123
@@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
124
if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
125
(cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) &&
126
(cs->hpplpi.prio != 0xff)) {
127
- if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
128
+ if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio, cs->hpplpi.nmi)) {
129
cs->hppi.irq = cs->hpplpi.irq;
130
cs->hppi.prio = cs->hpplpi.prio;
131
+ cs->hppi.nmi = cs->hpplpi.nmi;
132
cs->hppi.grp = cs->hpplpi.grp;
133
seenbetter = true;
134
}
135
@@ -XXX,XX +XXX,XX @@ static void gicv3_update_noirqset(GICv3State *s, int start, int len)
136
int i;
137
uint8_t prio;
138
uint32_t pend = 0;
139
+ bool nmi = false;
140
141
assert(start >= GIC_INTERNAL);
142
assert(len > 0);
143
@@ -XXX,XX +XXX,XX @@ static void gicv3_update_noirqset(GICv3State *s, int start, int len)
144
*/
145
continue;
146
}
147
- prio = s->gicd_ipriority[i];
148
- if (irqbetter(cs, i, prio)) {
149
+ nmi = gicv3_get_priority(cs, false, i, &prio);
150
+ if (irqbetter(cs, i, prio, nmi)) {
151
cs->hppi.irq = i;
152
cs->hppi.prio = prio;
153
+ cs->hppi.nmi = nmi;
154
cs->seenbetter = true;
155
}
156
}
157
@@ -XXX,XX +XXX,XX @@ void gicv3_full_update_noirqset(GICv3State *s)
158
159
for (i = 0; i < s->num_cpu; i++) {
160
s->cpu[i].hppi.prio = 0xff;
161
+ s->cpu[i].hppi.nmi = false;
162
}
163
164
/* Note that we can guarantee that these functions will not
165
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
166
index XXXXXXX..XXXXXXX 100644
167
--- a/hw/intc/arm_gicv3_common.c
168
+++ b/hw/intc/arm_gicv3_common.c
169
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_reset_hold(Object *obj)
170
memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
171
172
cs->hppi.prio = 0xff;
173
+ cs->hppi.nmi = false;
174
cs->hpplpi.prio = 0xff;
175
+ cs->hpplpi.nmi = false;
176
cs->hppvlpi.prio = 0xff;
177
+ cs->hppvlpi.nmi = false;
178
179
/* State in the CPU interface must *not* be reset here, because it
180
* is part of the CPU's reset domain, not the GIC device's.
181
diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
182
index XXXXXXX..XXXXXXX 100644
183
--- a/hw/intc/arm_gicv3_redist.c
184
+++ b/hw/intc/arm_gicv3_redist.c
185
@@ -XXX,XX +XXX,XX @@ static void update_for_one_lpi(GICv3CPUState *cs, int irq,
186
((prio == hpp->prio) && (irq <= hpp->irq))) {
187
hpp->irq = irq;
188
hpp->prio = prio;
189
+ hpp->nmi = false;
190
/* LPIs and vLPIs are always non-secure Grp1 interrupts */
191
hpp->grp = GICV3_G1NS;
192
}
193
@@ -XXX,XX +XXX,XX @@ static void update_for_all_lpis(GICv3CPUState *cs, uint64_t ptbase,
194
int i, bit;
195
196
hpp->prio = 0xff;
197
+ hpp->nmi = false;
198
199
for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) {
200
address_space_read(as, ptbase + i, MEMTXATTRS_UNSPECIFIED, &pend, 1);
201
@@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_vlpi_only(GICv3CPUState *cs)
202
203
if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) {
204
cs->hppvlpi.prio = 0xff;
205
+ cs->hppvlpi.nmi = false;
40
return;
206
return;
41
}
207
}
42
208
43
--
209
--
44
2.20.1
210
2.34.1
45
46
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
In CPU Interface, if the IRQ has the non-maskable property, report NMI to
4
the corresponding PE.
5
6
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20240407081733.3231820-22-ruanjinjie@huawei.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/intc/arm_gicv3_cpuif.c | 4 ++++
13
1 file changed, 4 insertions(+)
14
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_cpuif.c
18
+++ b/hw/intc/arm_gicv3_cpuif.c
19
@@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_update(GICv3CPUState *cs)
20
/* Tell the CPU about its highest priority pending interrupt */
21
int irqlevel = 0;
22
int fiqlevel = 0;
23
+ int nmilevel = 0;
24
ARMCPU *cpu = ARM_CPU(cs->cpu);
25
CPUARMState *env = &cpu->env;
26
27
@@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_update(GICv3CPUState *cs)
28
29
if (isfiq) {
30
fiqlevel = 1;
31
+ } else if (cs->hppi.nmi) {
32
+ nmilevel = 1;
33
} else {
34
irqlevel = 1;
35
}
36
@@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_update(GICv3CPUState *cs)
37
38
qemu_set_irq(cs->parent_fiq, fiqlevel);
39
qemu_set_irq(cs->parent_irq, irqlevel);
40
+ qemu_set_irq(cs->parent_nmi, nmilevel);
41
}
42
43
static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
44
--
45
2.34.1
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
These are the only users of neon_reg_offset, so remove that.
3
In vCPU Interface, if the vIRQ has the non-maskable property, report
4
vINMI to the corresponding vPE.
4
5
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
6
Message-id: 20201030022618.785675-4-richard.henderson@linaro.org
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20240407081733.3231820-23-ruanjinjie@huawei.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate.c | 14 ++------------
12
hw/intc/arm_gicv3_cpuif.c | 14 ++++++++++++--
11
1 file changed, 2 insertions(+), 12 deletions(-)
13
1 file changed, 12 insertions(+), 2 deletions(-)
12
14
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
17
--- a/hw/intc/arm_gicv3_cpuif.c
16
+++ b/target/arm/translate.c
18
+++ b/hw/intc/arm_gicv3_cpuif.c
17
@@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg)
19
@@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
18
}
20
int idx;
21
int irqlevel = 0;
22
int fiqlevel = 0;
23
+ int nmilevel = 0;
24
25
idx = hppvi_index(cs);
26
trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx,
27
@@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
28
uint64_t lr = cs->ich_lr_el2[idx];
29
30
if (icv_hppi_can_preempt(cs, lr)) {
31
- /* Virtual interrupts are simple: G0 are always FIQ, and G1 IRQ */
32
+ /*
33
+ * Virtual interrupts are simple: G0 are always FIQ, and G1 are
34
+ * IRQ or NMI which depends on the ICH_LR<n>_EL2.NMI to have
35
+ * non-maskable property.
36
+ */
37
if (lr & ICH_LR_EL2_GROUP) {
38
- irqlevel = 1;
39
+ if (lr & ICH_LR_EL2_NMI) {
40
+ nmilevel = 1;
41
+ } else {
42
+ irqlevel = 1;
43
+ }
44
} else {
45
fiqlevel = 1;
46
}
47
@@ -XXX,XX +XXX,XX @@ void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs)
48
trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel);
49
qemu_set_irq(cs->parent_vfiq, fiqlevel);
50
qemu_set_irq(cs->parent_virq, irqlevel);
51
+ qemu_set_irq(cs->parent_vnmi, nmilevel);
19
}
52
}
20
53
21
-/* Return the offset of a 32-bit piece of a NEON register.
54
static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
22
- zero is the least significant end of the register. */
23
-static inline long
24
-neon_reg_offset (int reg, int n)
25
-{
26
- int sreg;
27
- sreg = reg * 2 + n;
28
- return vfp_reg_offset(0, sreg);
29
-}
30
-
31
static TCGv_i32 neon_load_reg(int reg, int pass)
32
{
33
TCGv_i32 tmp = tcg_temp_new_i32();
34
- tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
35
+ tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
36
return tmp;
37
}
38
39
static void neon_store_reg(int reg, int pass, TCGv_i32 var)
40
{
41
- tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
42
+ tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
43
tcg_temp_free_i32(var);
44
}
45
46
--
55
--
47
2.20.1
56
2.34.1
48
49
diff view generated by jsdifflib
New patch
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
1
2
3
Enable FEAT_NMI on the 'max' CPU.
4
5
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20240407081733.3231820-24-ruanjinjie@huawei.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/emulation.rst | 1 +
12
target/arm/tcg/cpu64.c | 1 +
13
2 files changed, 2 insertions(+)
14
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
18
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
- FEAT_MTE (Memory Tagging Extension)
21
- FEAT_MTE2 (Memory Tagging Extension)
22
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
23
+- FEAT_NMI (Non-maskable Interrupt)
24
- FEAT_NV (Nested Virtualization)
25
- FEAT_NV2 (Enhanced nested virtualization support)
26
- FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm)
27
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/tcg/cpu64.c
30
+++ b/target/arm/tcg/cpu64.c
31
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
32
t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
33
t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
34
t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
35
+ t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
36
cpu->isar.id_aa64pfr1 = t;
37
38
t = cpu->isar.id_aa64mmfr0;
39
--
40
2.34.1
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jinjie Ruan <ruanjinjie@huawei.com>
2
2
3
This will shortly have users outside of translate-neon.c.inc.
3
If the CPU implements FEAT_NMI, then turn on the NMI support in the
4
GICv3 too. It's permitted to have a configuration with FEAT_NMI in
5
the CPU (and thus NMI support in the CPU interfaces too) but no NMI
6
support in the distributor and redistributor, but this isn't a very
7
useful setup as it's close to having no NMI support at all.
4
8
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
We don't need to gate the enabling of NMI in the GIC behind a
6
Message-id: 20201030022618.785675-3-richard.henderson@linaro.org
10
machine version property, because none of our current CPUs
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
implement FEAT_NMI, and '-cpu max' is not something we maintain
12
migration compatibility across versions for. So we can always
13
enable the GIC NMI support when the CPU has it.
14
15
Neither hvf nor KVM support NMI in the GIC yet, so we don't enable
16
it unless we're using TCG.
17
18
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20240407081733.3231820-25-ruanjinjie@huawei.com
21
[PMM: Update comment and commit message]
22
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
24
---
10
target/arm/translate.c | 20 ++++++++++++++++++++
25
hw/arm/virt.c | 19 +++++++++++++++++++
11
target/arm/translate-neon.c.inc | 19 -------------------
26
1 file changed, 19 insertions(+)
12
2 files changed, 20 insertions(+), 19 deletions(-)
13
27
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
28
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
30
--- a/hw/arm/virt.c
17
+++ b/target/arm/translate.c
31
+++ b/hw/arm/virt.c
18
@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
32
@@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms)
19
return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
33
vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
20
}
34
}
21
35
22
+/*
36
+/*
23
+ * Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
37
+ * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
24
+ * where 0 is the least significant end of the register.
38
+ * It's permitted to have a configuration with NMI in the CPU (and thus the
39
+ * GICv3 CPU interface) but not in the distributor/redistributors, but it's
40
+ * not very useful.
25
+ */
41
+ */
26
+static long neon_element_offset(int reg, int element, MemOp size)
42
+static bool gicv3_nmi_present(VirtMachineState *vms)
27
+{
43
+{
28
+ int element_size = 1 << size;
44
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
29
+ int ofs = element * element_size;
45
+
30
+#ifdef HOST_WORDS_BIGENDIAN
46
+ return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) &&
31
+ /*
47
+ (vms->gic_version != VIRT_GIC_VERSION_2);
32
+ * Calculate the offset assuming fully little-endian,
33
+ * then XOR to account for the order of the 8-byte units.
34
+ */
35
+ if (element_size < 8) {
36
+ ofs ^= 8 - element_size;
37
+ }
38
+#endif
39
+ return neon_full_reg_offset(reg) + ofs;
40
+}
48
+}
41
+
49
+
42
static inline long vfp_reg_offset(bool dp, unsigned reg)
50
static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
43
{
51
{
44
if (dp) {
52
MachineState *ms = MACHINE(vms);
45
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
53
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
46
index XXXXXXX..XXXXXXX 100644
54
vms->virt);
47
--- a/target/arm/translate-neon.c.inc
55
}
48
+++ b/target/arm/translate-neon.c.inc
56
}
49
@@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x)
57
+
50
#include "decode-neon-ls.c.inc"
58
+ if (gicv3_nmi_present(vms)) {
51
#include "decode-neon-shared.c.inc"
59
+ qdev_prop_set_bit(vms->gic, "has-nmi", true);
52
60
+ }
53
-/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
61
+
54
- * where 0 is the least significant end of the register.
62
gicbusdev = SYS_BUS_DEVICE(vms->gic);
55
- */
63
sysbus_realize_and_unref(gicbusdev, &error_fatal);
56
-static inline long
64
sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
57
-neon_element_offset(int reg, int element, MemOp size)
58
-{
59
- int element_size = 1 << size;
60
- int ofs = element * element_size;
61
-#ifdef HOST_WORDS_BIGENDIAN
62
- /* Calculate the offset assuming fully little-endian,
63
- * then XOR to account for the order of the 8-byte units.
64
- */
65
- if (element_size < 8) {
66
- ofs ^= 8 - element_size;
67
- }
68
-#endif
69
- return neon_full_reg_offset(reg) + ofs;
70
-}
71
-
72
static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
73
{
74
long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
75
--
65
--
76
2.20.1
66
2.34.1
77
78
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Anastasia Belova <abelova@astralinux.ru>
2
2
3
In both cases, we can sink the write-back and perform
3
In soc_dma_set_request() we try to set a bit in a uint64_t, but we
4
the accumulate into the normal destination temps.
4
do it with "1 << ch->num", which can't set any bits past 31;
5
any use for a channel number of 32 or more would fail due to
6
integer overflow.
5
7
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
This doesn't happen in practice for our current use of this code,
7
Message-id: 20201030022618.785675-11-richard.henderson@linaro.org
9
because the worst case is when we call soc_dma_init() with an
10
argument of 32 for the number of channels, and QEMU builds with
11
-fwrapv so the shift into the sign bit is well-defined. However,
12
it's obviously not the intended behaviour of the code.
13
14
Add casts to force the shift to be done as 64-bit arithmetic,
15
allowing up to 64 channels.
16
17
Found by Linux Verification Center (linuxtesting.org) with SVACE.
18
19
Fixes: afbb5194d4 ("Handle on-chip DMA controllers in one place, convert OMAP DMA to use it.")
20
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
21
Message-id: 20240409115301.21829-1-abelova@astralinux.ru
22
[PMM: Edit commit message to clarify that this doesn't actually
23
bite us in our current usage of this code.]
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
26
---
11
target/arm/translate-neon.c.inc | 23 +++++++++--------------
27
hw/dma/soc_dma.c | 4 ++--
12
1 file changed, 9 insertions(+), 14 deletions(-)
28
1 file changed, 2 insertions(+), 2 deletions(-)
13
29
14
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
30
diff --git a/hw/dma/soc_dma.c b/hw/dma/soc_dma.c
15
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-neon.c.inc
32
--- a/hw/dma/soc_dma.c
17
+++ b/target/arm/translate-neon.c.inc
33
+++ b/hw/dma/soc_dma.c
18
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
34
@@ -XXX,XX +XXX,XX @@ void soc_dma_set_request(struct soc_dma_ch_s *ch, int level)
19
if (accfn) {
35
dma->enabled_count += level - ch->enable;
20
tmp = tcg_temp_new_i64();
36
21
read_neon_element64(tmp, a->vd, 0, MO_64);
37
if (level)
22
- accfn(tmp, tmp, rd0);
38
- dma->ch_enable_mask |= 1 << ch->num;
23
- write_neon_element64(tmp, a->vd, 0, MO_64);
39
+ dma->ch_enable_mask |= (uint64_t)1 << ch->num;
24
+ accfn(rd0, tmp, rd0);
40
else
25
read_neon_element64(tmp, a->vd, 1, MO_64);
41
- dma->ch_enable_mask &= ~(1 << ch->num);
26
- accfn(tmp, tmp, rd1);
42
+ dma->ch_enable_mask &= ~((uint64_t)1 << ch->num);
27
- write_neon_element64(tmp, a->vd, 1, MO_64);
43
28
+ accfn(rd1, tmp, rd1);
44
if (level != ch->enable) {
29
tcg_temp_free_i64(tmp);
45
soc_dma_ch_freq_update(dma);
30
- } else {
31
- write_neon_element64(rd0, a->vd, 0, MO_64);
32
- write_neon_element64(rd1, a->vd, 1, MO_64);
33
}
34
35
+ write_neon_element64(rd0, a->vd, 0, MO_64);
36
+ write_neon_element64(rd1, a->vd, 1, MO_64);
37
tcg_temp_free_i64(rd0);
38
tcg_temp_free_i64(rd1);
39
40
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
41
if (accfn) {
42
TCGv_i64 t64 = tcg_temp_new_i64();
43
read_neon_element64(t64, a->vd, 0, MO_64);
44
- accfn(t64, t64, rn0_64);
45
- write_neon_element64(t64, a->vd, 0, MO_64);
46
+ accfn(rn0_64, t64, rn0_64);
47
read_neon_element64(t64, a->vd, 1, MO_64);
48
- accfn(t64, t64, rn1_64);
49
- write_neon_element64(t64, a->vd, 1, MO_64);
50
+ accfn(rn1_64, t64, rn1_64);
51
tcg_temp_free_i64(t64);
52
- } else {
53
- write_neon_element64(rn0_64, a->vd, 0, MO_64);
54
- write_neon_element64(rn1_64, a->vd, 1, MO_64);
55
}
56
+
57
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
58
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
59
tcg_temp_free_i64(rn0_64);
60
tcg_temp_free_i64(rn1_64);
61
return true;
62
--
46
--
63
2.20.1
47
2.34.1
64
65
diff view generated by jsdifflib
1
Sphinx 3.2 is pickier than earlier versions about the option:: markup,
1
Ever since the bFLT format support was added in 2006, there has been
2
and complains about our usage in qemu-option-trace.rst:
2
a chunk of code in the file guarded by CONFIG_BINFMT_SHARED_FLAT
3
3
which is supposedly for shared library support. This is not enabled
4
../../docs/qemu-option-trace.rst.inc:4:Malformed option description
4
and it's not possible to enable it, because if you do you'll run into
5
'[enable=]PATTERN', should look like "opt", "-opt args", "--opt args",
5
the "#error needs checking" in the calc_reloc() function.
6
"/opt args" or "+opt args"
6
7
7
Similarly, CONFIG_BINFMT_ZFLAT exists but can't be enabled because of
8
In this file, we're really trying to document the different parts of
8
an "#error code needs checking" in load_flat_file().
9
the top-level --trace option, which qemu-nbd.rst and qemu-img.rst
9
10
have already introduced with an option:: markup. So it's not right
10
This code is obviously unfinished and has never been used; nobody in
11
to use option:: here anyway. Switch to a different markup
11
the intervening 18 years has complained about this or fixed it, so
12
(definition lists) which gives about the same formatted output.
12
just delete the dead code. If anybody ever wants the feature they
13
13
can always pull it out of git, or (perhaps better) write it from
14
(Unlike option::, this markup doesn't produce index entries; but
14
scratch based on the current Linux bFLT loader rather than the one of
15
at the moment we don't do anything much with indexes anyway, and
15
18 years ago.
16
in any case I think it doesn't make much sense to have individual
17
index entries for the sub-parts of the --trace option.)
18
16
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
21
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
19
Message-id: 20240411115313.680433-1-peter.maydell@linaro.org
22
Message-id: 20201030174700.7204-3-peter.maydell@linaro.org
23
---
20
---
24
docs/qemu-option-trace.rst.inc | 6 +++---
21
linux-user/flat.h | 5 +-
25
1 file changed, 3 insertions(+), 3 deletions(-)
22
linux-user/flatload.c | 293 ++----------------------------------------
26
23
2 files changed, 11 insertions(+), 287 deletions(-)
27
diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc
24
25
diff --git a/linux-user/flat.h b/linux-user/flat.h
28
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
29
--- a/docs/qemu-option-trace.rst.inc
27
--- a/linux-user/flat.h
30
+++ b/docs/qemu-option-trace.rst.inc
28
+++ b/linux-user/flat.h
31
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@
32
30
33
Specify tracing options.
31
#define    FLAT_VERSION            0x00000004L
34
32
35
-.. option:: [enable=]PATTERN
33
-#ifdef CONFIG_BINFMT_SHARED_FLAT
36
+``[enable=]PATTERN``
34
-#define    MAX_SHARED_LIBS            (4)
37
35
-#else
38
Immediately enable events matching *PATTERN*
36
+/* QEMU doesn't support bflt shared libraries */
39
(either event name or a globbing pattern). This option is only
37
#define    MAX_SHARED_LIBS            (1)
40
@@ -XXX,XX +XXX,XX @@ Specify tracing options.
38
-#endif
41
39
42
Use :option:`-trace help` to print a list of names of trace points.
40
/*
43
41
* To make everything easier to port and manage cross platform
44
-.. option:: events=FILE
42
diff --git a/linux-user/flatload.c b/linux-user/flatload.c
45
+``events=FILE``
43
index XXXXXXX..XXXXXXX 100644
46
44
--- a/linux-user/flatload.c
47
Immediately enable events listed in *FILE*.
45
+++ b/linux-user/flatload.c
48
The file must contain one event name (as listed in the ``trace-events-all``
46
@@ -XXX,XX +XXX,XX @@
49
@@ -XXX,XX +XXX,XX @@ Specify tracing options.
47
*    JAN/99 -- coded full program relocation (gerg@snapgear.com)
50
available if QEMU has been compiled with the ``simple``, ``log`` or
48
*/
51
``ftrace`` tracing backend.
49
52
50
-/* ??? ZFLAT and shared library support is currently disabled. */
53
-.. option:: file=FILE
51
-
54
+``file=FILE``
52
/****************************************************************************/
55
53
56
Log output traces to *FILE*.
54
#include "qemu/osdep.h"
57
This option is only available if QEMU has been compiled with
55
@@ -XXX,XX +XXX,XX @@ struct lib_info {
56
short loaded;        /* Has this library been loaded? */
57
};
58
59
-#ifdef CONFIG_BINFMT_SHARED_FLAT
60
-static int load_flat_shared_library(int id, struct lib_info *p);
61
-#endif
62
-
63
struct linux_binprm;
64
65
/****************************************************************************/
66
@@ -XXX,XX +XXX,XX @@ static int target_pread(int fd, abi_ulong ptr, abi_ulong len,
67
unlock_user(buf, ptr, len);
68
return ret;
69
}
70
-/****************************************************************************/
71
-
72
-#ifdef CONFIG_BINFMT_ZFLAT
73
-
74
-#include <linux/zlib.h>
75
-
76
-#define LBUFSIZE    4000
77
-
78
-/* gzip flag byte */
79
-#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
80
-#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
81
-#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
82
-#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
83
-#define COMMENT 0x10 /* bit 4 set: file comment present */
84
-#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
85
-#define RESERVED 0xC0 /* bit 6,7: reserved */
86
-
87
-static int decompress_exec(
88
-    struct linux_binprm *bprm,
89
-    unsigned long offset,
90
-    char *dst,
91
-    long len,
92
-    int fd)
93
-{
94
-    unsigned char *buf;
95
-    z_stream strm;
96
-    loff_t fpos;
97
-    int ret, retval;
98
-
99
-    DBG_FLT("decompress_exec(offset=%x,buf=%x,len=%x)\n",(int)offset, (int)dst, (int)len);
100
-
101
-    memset(&strm, 0, sizeof(strm));
102
-    strm.workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
103
-    if (strm.workspace == NULL) {
104
-        DBG_FLT("binfmt_flat: no memory for decompress workspace\n");
105
-        return -ENOMEM;
106
-    }
107
-    buf = kmalloc(LBUFSIZE, GFP_KERNEL);
108
-    if (buf == NULL) {
109
-        DBG_FLT("binfmt_flat: no memory for read buffer\n");
110
-        retval = -ENOMEM;
111
-        goto out_free;
112
-    }
113
-
114
-    /* Read in first chunk of data and parse gzip header. */
115
-    fpos = offset;
116
-    ret = bprm->file->f_op->read(bprm->file, buf, LBUFSIZE, &fpos);
117
-
118
-    strm.next_in = buf;
119
-    strm.avail_in = ret;
120
-    strm.total_in = 0;
121
-
122
-    retval = -ENOEXEC;
123
-
124
-    /* Check minimum size -- gzip header */
125
-    if (ret < 10) {
126
-        DBG_FLT("binfmt_flat: file too small?\n");
127
-        goto out_free_buf;
128
-    }
129
-
130
-    /* Check gzip magic number */
131
-    if ((buf[0] != 037) || ((buf[1] != 0213) && (buf[1] != 0236))) {
132
-        DBG_FLT("binfmt_flat: unknown compression magic?\n");
133
-        goto out_free_buf;
134
-    }
135
-
136
-    /* Check gzip method */
137
-    if (buf[2] != 8) {
138
-        DBG_FLT("binfmt_flat: unknown compression method?\n");
139
-        goto out_free_buf;
140
-    }
141
-    /* Check gzip flags */
142
-    if ((buf[3] & ENCRYPTED) || (buf[3] & CONTINUATION) ||
143
-     (buf[3] & RESERVED)) {
144
-        DBG_FLT("binfmt_flat: unknown flags?\n");
145
-        goto out_free_buf;
146
-    }
147
-
148
-    ret = 10;
149
-    if (buf[3] & EXTRA_FIELD) {
150
-        ret += 2 + buf[10] + (buf[11] << 8);
151
-        if (unlikely(LBUFSIZE == ret)) {
152
-            DBG_FLT("binfmt_flat: buffer overflow (EXTRA)?\n");
153
-            goto out_free_buf;
154
-        }
155
-    }
156
-    if (buf[3] & ORIG_NAME) {
157
-        for (; ret < LBUFSIZE && (buf[ret] != 0); ret++)
158
-            ;
159
-        if (unlikely(LBUFSIZE == ret)) {
160
-            DBG_FLT("binfmt_flat: buffer overflow (ORIG_NAME)?\n");
161
-            goto out_free_buf;
162
-        }
163
-    }
164
-    if (buf[3] & COMMENT) {
165
-        for (; ret < LBUFSIZE && (buf[ret] != 0); ret++)
166
-            ;
167
-        if (unlikely(LBUFSIZE == ret)) {
168
-            DBG_FLT("binfmt_flat: buffer overflow (COMMENT)?\n");
169
-            goto out_free_buf;
170
-        }
171
-    }
172
-
173
-    strm.next_in += ret;
174
-    strm.avail_in -= ret;
175
-
176
-    strm.next_out = dst;
177
-    strm.avail_out = len;
178
-    strm.total_out = 0;
179
-
180
-    if (zlib_inflateInit2(&strm, -MAX_WBITS) != Z_OK) {
181
-        DBG_FLT("binfmt_flat: zlib init failed?\n");
182
-        goto out_free_buf;
183
-    }
184
-
185
-    while ((ret = zlib_inflate(&strm, Z_NO_FLUSH)) == Z_OK) {
186
-        ret = bprm->file->f_op->read(bprm->file, buf, LBUFSIZE, &fpos);
187
-        if (ret <= 0)
188
-            break;
189
- if (is_error(ret)) {
190
-            break;
191
- }
192
-        len -= ret;
193
-
194
-        strm.next_in = buf;
195
-        strm.avail_in = ret;
196
-        strm.total_in = 0;
197
-    }
198
-
199
-    if (ret < 0) {
200
-        DBG_FLT("binfmt_flat: decompression failed (%d), %s\n",
201
-            ret, strm.msg);
202
-        goto out_zlib;
203
-    }
204
-
205
-    retval = 0;
206
-out_zlib:
207
-    zlib_inflateEnd(&strm);
208
-out_free_buf:
209
-    kfree(buf);
210
-out_free:
211
-    kfree(strm.workspace);
212
-out:
213
-    return retval;
214
-}
215
-
216
-#endif /* CONFIG_BINFMT_ZFLAT */
217
218
/****************************************************************************/
219
220
@@ -XXX,XX +XXX,XX @@ calc_reloc(abi_ulong r, struct lib_info *p, int curid, int internalp)
221
abi_ulong text_len;
222
abi_ulong start_code;
223
224
-#ifdef CONFIG_BINFMT_SHARED_FLAT
225
-#error needs checking
226
- if (r == 0)
227
- id = curid;    /* Relocs of 0 are always self referring */
228
- else {
229
- id = (r >> 24) & 0xff;    /* Find ID for this reloc */
230
- r &= 0x00ffffff;    /* Trim ID off here */
231
- }
232
- if (id >= MAX_SHARED_LIBS) {
233
- fprintf(stderr, "BINFMT_FLAT: reference 0x%x to shared library %d\n",
234
- (unsigned) r, id);
235
- goto failed;
236
- }
237
- if (curid != id) {
238
- if (internalp) {
239
- fprintf(stderr, "BINFMT_FLAT: reloc address 0x%x not "
240
- "in same module (%d != %d)\n",
241
- (unsigned) r, curid, id);
242
- goto failed;
243
- } else if (!p[id].loaded && is_error(load_flat_shared_library(id, p))) {
244
- fprintf(stderr, "BINFMT_FLAT: failed to load library %d\n", id);
245
- goto failed;
246
- }
247
- /* Check versioning information (i.e. time stamps) */
248
- if (p[id].build_date && p[curid].build_date
249
- && p[curid].build_date < p[id].build_date) {
250
- fprintf(stderr, "BINFMT_FLAT: library %d is younger than %d\n",
251
- id, curid);
252
- goto failed;
253
- }
254
- }
255
-#else
256
id = 0;
257
-#endif
258
259
start_brk = p[id].start_brk;
260
start_data = p[id].start_data;
261
@@ -XXX,XX +XXX,XX @@ static int load_flat_file(struct linux_binprm * bprm,
262
if (rev == OLD_FLAT_VERSION && flat_old_ram_flag(flags))
263
flags = FLAT_FLAG_RAM;
264
265
-#ifndef CONFIG_BINFMT_ZFLAT
266
if (flags & (FLAT_FLAG_GZIP|FLAT_FLAG_GZDATA)) {
267
- fprintf(stderr, "Support for ZFLAT executables is not enabled\n");
268
+ fprintf(stderr, "ZFLAT executables are not supported\n");
269
return -ENOEXEC;
270
}
271
-#endif
272
273
/*
274
* calculate the extra space we need to map in
275
@@ -XXX,XX +XXX,XX @@ static int load_flat_file(struct linux_binprm * bprm,
276
(int)(data_len + bss_len + stack_len), (int)datapos);
277
278
fpos = ntohl(hdr->data_start);
279
-#ifdef CONFIG_BINFMT_ZFLAT
280
- if (flags & FLAT_FLAG_GZDATA) {
281
- result = decompress_exec(bprm, fpos, (char *) datapos,
282
- data_len + (relocs * sizeof(abi_ulong)))
283
- } else
284
-#endif
285
- {
286
- result = target_pread(bprm->src.fd, datapos,
287
- data_len + (relocs * sizeof(abi_ulong)),
288
- fpos);
289
- }
290
+ result = target_pread(bprm->src.fd, datapos,
291
+ data_len + (relocs * sizeof(abi_ulong)),
292
+ fpos);
293
if (result < 0) {
294
fprintf(stderr, "Unable to read data+bss\n");
295
return result;
296
@@ -XXX,XX +XXX,XX @@ static int load_flat_file(struct linux_binprm * bprm,
297
datapos = realdatastart + indx_len;
298
reloc = (textpos + ntohl(hdr->reloc_start) + indx_len);
299
300
-#ifdef CONFIG_BINFMT_ZFLAT
301
-#error code needs checking
302
- /*
303
- * load it all in and treat it like a RAM load from now on
304
- */
305
- if (flags & FLAT_FLAG_GZIP) {
306
- result = decompress_exec(bprm, sizeof (struct flat_hdr),
307
- (((char *) textpos) + sizeof (struct flat_hdr)),
308
- (text_len + data_len + (relocs * sizeof(unsigned long))
309
- - sizeof (struct flat_hdr)),
310
- 0);
311
- memmove((void *) datapos, (void *) realdatastart,
312
- data_len + (relocs * sizeof(unsigned long)));
313
- } else if (flags & FLAT_FLAG_GZDATA) {
314
- fpos = 0;
315
- result = bprm->file->f_op->read(bprm->file,
316
- (char *) textpos, text_len, &fpos);
317
- if (!is_error(result)) {
318
- result = decompress_exec(bprm, text_len, (char *) datapos,
319
- data_len + (relocs * sizeof(unsigned long)), 0);
320
- }
321
- }
322
- else
323
-#endif
324
- {
325
- result = target_pread(bprm->src.fd, textpos,
326
- text_len, 0);
327
- if (result >= 0) {
328
- result = target_pread(bprm->src.fd, datapos,
329
- data_len + (relocs * sizeof(abi_ulong)),
330
- ntohl(hdr->data_start));
331
- }
332
+ result = target_pread(bprm->src.fd, textpos,
333
+ text_len, 0);
334
+ if (result >= 0) {
335
+ result = target_pread(bprm->src.fd, datapos,
336
+ data_len + (relocs * sizeof(abi_ulong)),
337
+ ntohl(hdr->data_start));
338
}
339
if (result < 0) {
340
fprintf(stderr, "Unable to read code+data+bss\n");
341
@@ -XXX,XX +XXX,XX @@ static int load_flat_file(struct linux_binprm * bprm,
342
343
344
/****************************************************************************/
345
-#ifdef CONFIG_BINFMT_SHARED_FLAT
346
-
347
-/*
348
- * Load a shared library into memory. The library gets its own data
349
- * segment (including bss) but not argv/argc/environ.
350
- */
351
-
352
-static int load_flat_shared_library(int id, struct lib_info *libs)
353
-{
354
-    struct linux_binprm bprm;
355
-    int res;
356
-    char buf[16];
357
-
358
-    /* Create the file name */
359
-    sprintf(buf, "/lib/lib%d.so", id);
360
-
361
-    /* Open the file up */
362
-    bprm.filename = buf;
363
-    bprm.file = open_exec(bprm.filename);
364
-    res = PTR_ERR(bprm.file);
365
-    if (IS_ERR(bprm.file))
366
-        return res;
367
-
368
-    res = prepare_binprm(&bprm);
369
-
370
- if (!is_error(res)) {
371
-        res = load_flat_file(&bprm, libs, id, NULL);
372
- }
373
-    if (bprm.file) {
374
-        allow_write_access(bprm.file);
375
-        fput(bprm.file);
376
-        bprm.file = NULL;
377
-    }
378
-    return(res);
379
-}
380
-
381
-#endif /* CONFIG_BINFMT_SHARED_FLAT */
382
-
383
int load_flt_binary(struct linux_binprm *bprm, struct image_info *info)
384
{
385
struct lib_info libinfo[MAX_SHARED_LIBS];
386
@@ -XXX,XX +XXX,XX @@ int load_flt_binary(struct linux_binprm *bprm, struct image_info *info)
387
*/
388
start_addr = libinfo[0].entry;
389
390
-#ifdef CONFIG_BINFMT_SHARED_FLAT
391
-#error here
392
- for (i = MAX_SHARED_LIBS-1; i>0; i--) {
393
- if (libinfo[i].loaded) {
394
- /* Push previous first to call address */
395
- --sp;
396
- if (put_user_ual(start_addr, sp))
397
- return -EFAULT;
398
- start_addr = libinfo[i].entry;
399
- }
400
- }
401
-#endif
402
-
403
/* Stash our initial stack pointer into the mm structure */
404
info->start_code = libinfo[0].start_code;
405
info->end_code = libinfo[0].start_code + libinfo[0].text_len;
58
--
406
--
59
2.20.1
407
2.34.1
60
408
61
409
diff view generated by jsdifflib
1
The randomness tests in the NPCM7xx RNG test fail intermittently
1
The npcm7xx_clk and npcm7xx_gcr device reset methods look at
2
but fairly frequently. On my machine running the test in a loop:
2
the ResetType argument and only handle RESET_TYPE_COLD,
3
while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done
3
producing a warning if another reset type is passed. This
4
is different from how every other three-phase-reset method
5
we have works, and makes it difficult to add new reset types.
4
6
5
will fail in less than a minute with an error like:
7
A better pattern is "assume that any reset type you don't know
6
ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs:
8
about should be handled like RESET_TYPE_COLD"; switch these
7
assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01)
9
devices to do that. Then adding a new reset type will only
8
10
need to touch those devices where its behaviour really needs
9
(Failures have been observed on all 4 of the randomness tests,
11
to be different from the standard cold reset.
10
not just first_byte_runs.)
11
12
It's not clear why these tests are failing like this, but intermittent
13
failures make CI and merge testing awkward, so disable running them
14
unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when
15
running the test suite, until we work out the cause.
16
12
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20201102152454.8287-1-peter.maydell@linaro.org
15
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
20
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
16
Reviewed-by: Luc Michel <luc.michel@amd.com>
17
Message-id: 20240412160809.1260625-2-peter.maydell@linaro.org
21
---
18
---
22
tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++----
19
hw/misc/npcm7xx_clk.c | 13 +++----------
23
1 file changed, 10 insertions(+), 4 deletions(-)
20
hw/misc/npcm7xx_gcr.c | 12 ++++--------
21
2 files changed, 7 insertions(+), 18 deletions(-)
24
22
25
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
23
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
26
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/qtest/npcm7xx_rng-test.c
25
--- a/hw/misc/npcm7xx_clk.c
28
+++ b/tests/qtest/npcm7xx_rng-test.c
26
+++ b/hw/misc/npcm7xx_clk.c
29
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
27
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
30
28
31
qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);
29
QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
32
qtest_add_func("npcm7xx_rng/rosel", test_rosel);
30
33
- qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
31
- switch (type) {
34
- qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
32
- case RESET_TYPE_COLD:
35
- qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
33
- memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
36
- qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
34
- s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
37
+ /*
35
- npcm7xx_clk_update_all_clocks(s);
38
+ * These tests fail intermittently; only run them on explicit
36
- return;
39
+ * request until we figure out why.
37
- }
40
+ */
38
-
41
+ if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) {
39
+ memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
42
+ qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
40
+ s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
43
+ qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
41
+ npcm7xx_clk_update_all_clocks(s);
44
+ qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
42
/*
45
+ qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
43
* A small number of registers need to be reset on a core domain reset,
46
+ }
44
* but no such reset type exists yet.
47
45
*/
48
qtest_start("-machine npcm750-evb");
46
- qemu_log_mask(LOG_UNIMP, "%s: reset type %d not implemented.",
49
ret = g_test_run();
47
- __func__, type);
48
}
49
50
static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
51
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/misc/npcm7xx_gcr.c
54
+++ b/hw/misc/npcm7xx_gcr.c
55
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
56
57
QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
58
59
- switch (type) {
60
- case RESET_TYPE_COLD:
61
- memcpy(s->regs, cold_reset_values, sizeof(s->regs));
62
- s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron;
63
- s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr;
64
- s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
65
- break;
66
- }
67
+ memcpy(s->regs, cold_reset_values, sizeof(s->regs));
68
+ s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron;
69
+ s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr;
70
+ s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
71
}
72
73
static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
50
--
74
--
51
2.20.1
75
2.34.1
52
76
53
77
diff view generated by jsdifflib
1
In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to
1
Rather than directly calling the device's implementation of its 'hold'
2
armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el().
2
reset phase, call device_cold_reset(). This means we don't have to
3
This is incorrect when the security state being queried is not the
3
adjust this callsite when we add another argument to the function
4
current one, because arm_current_el() uses the current security state
4
signature for the hold and exit reset methods.
5
to determine which of the banked CONTROL.nPRIV bits to look at.
6
The effect was that if (for instance) Secure state was in privileged
7
mode but Non-Secure was not then we would return the wrong MMU index.
8
9
The only places where we are using this function in a way that could
10
trigger this bug are for the stack loads during a v8M function-return
11
and for the instruction fetch of a v8M SG insn.
12
13
Fix the bug by expanding out the M-profile version of the
14
arm_current_el() logic inline so it can use the passed in secstate
15
rather than env->v7m.secure.
16
5
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20201022164408.13214-1-peter.maydell@linaro.org
8
Reviewed-by: Luc Michel <luc.michel@amd.com>
9
Message-id: 20240412160809.1260625-3-peter.maydell@linaro.org
20
---
10
---
21
target/arm/m_helper.c | 3 ++-
11
hw/i2c/allwinner-i2c.c | 3 +--
22
1 file changed, 2 insertions(+), 1 deletion(-)
12
hw/sensor/adm1272.c | 2 +-
13
2 files changed, 2 insertions(+), 3 deletions(-)
23
14
24
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
15
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/m_helper.c
17
--- a/hw/i2c/allwinner-i2c.c
27
+++ b/target/arm/m_helper.c
18
+++ b/hw/i2c/allwinner-i2c.c
28
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
19
@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
29
/* Return the MMU index for a v7M CPU in the specified security state */
20
break;
30
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
21
case TWI_SRST_REG:
31
{
22
if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) {
32
- bool priv = arm_current_el(env) != 0;
23
- /* Perform reset */
33
+ bool priv = arm_v7m_is_handler_mode(env) ||
24
- allwinner_i2c_reset_hold(OBJECT(s));
34
+ !(env->v7m.control[secstate] & 1);
25
+ device_cold_reset(DEVICE(s));
35
26
}
36
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
27
s->srst = value & TWI_SRST_MASK;
37
}
28
break;
29
diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/sensor/adm1272.c
32
+++ b/hw/sensor/adm1272.c
33
@@ -XXX,XX +XXX,XX @@ static int adm1272_write_data(PMBusDevice *pmdev, const uint8_t *buf,
34
break;
35
36
case ADM1272_MFR_POWER_CYCLE:
37
- adm1272_exit_reset((Object *)s);
38
+ device_cold_reset(DEVICE(s));
39
break;
40
41
case ADM1272_HYSTERESIS_LOW:
38
--
42
--
39
2.20.1
43
2.34.1
40
41
diff view generated by jsdifflib
1
On some hosts (eg Ubuntu Bionic) pkg-config returns a set of
1
We pass a ResetType argument to the Resettable class enter phase
2
libraries for gio-2.0 which don't actually work when compiling
2
method, but we don't pass it to hold and exit, even though the
3
statically. (Specifically, the returned library string includes
3
callsites have it readily available. This means that if a device
4
-lmount, but not -lblkid which -lmount depends upon, so linking
4
cared about the ResetType it would need to record it in the enter
5
fails due to missing symbols.)
5
phase method to use later on. We should pass the type to all three
6
of the phase methods to avoid having to do that.
6
7
7
Check that the libraries work, and don't enable gio if they don't,
8
This coccinelle script adds the ResetType argument to the hold and
8
in the same way we do for gnutls.
9
exit phases of the Resettable interface.
10
11
The first part of the script (rules holdfn_assigned, holdfn_defined,
12
exitfn_assigned, exitfn_defined) update implementations of the
13
interface within device models, both to change the signature of their
14
method implementations and to pass on the reset type when they invoke
15
reset on some other device.
16
17
The second part of the script is various special cases:
18
* method callsites in resettable_phase_hold(), resettable_phase_exit()
19
and device_phases_reset()
20
* updating the typedefs for the methods
21
* isl_pmbus_vr.c has some code where one device's reset method directly
22
calls the implementation of a different device's method
9
23
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
25
Reviewed-by: Luc Michel <luc.michel@amd.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
26
Message-id: 20240412160809.1260625-4-peter.maydell@linaro.org
13
Message-id: 20200928160402.7961-1-peter.maydell@linaro.org
14
---
27
---
15
configure | 10 +++++++++-
28
scripts/coccinelle/reset-type.cocci | 133 ++++++++++++++++++++++++++++
16
1 file changed, 9 insertions(+), 1 deletion(-)
29
1 file changed, 133 insertions(+)
30
create mode 100644 scripts/coccinelle/reset-type.cocci
17
31
18
diff --git a/configure b/configure
32
diff --git a/scripts/coccinelle/reset-type.cocci b/scripts/coccinelle/reset-type.cocci
19
index XXXXXXX..XXXXXXX 100755
33
new file mode 100644
20
--- a/configure
34
index XXXXXXX..XXXXXXX
21
+++ b/configure
35
--- /dev/null
22
@@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then
36
+++ b/scripts/coccinelle/reset-type.cocci
23
fi
37
@@ -XXX,XX +XXX,XX @@
24
38
+// Convert device code using three-phase reset to add a ResetType
25
if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
39
+// argument to implementations of ResettableHoldPhase and
26
- gio=yes
40
+// ResettableEnterPhase methods.
27
gio_cflags=$($pkg_config --cflags gio-2.0)
41
+//
28
gio_libs=$($pkg_config --libs gio-2.0)
42
+// Copyright Linaro Ltd 2024
29
gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0)
43
+// SPDX-License-Identifier: GPL-2.0-or-later
30
if [ ! -x "$gdbus_codegen" ]; then
44
+//
31
gdbus_codegen=
45
+// for dir in include hw target; do \
32
fi
46
+// spatch --macro-file scripts/cocci-macro-file.h \
33
+ # Check that the libraries actually work -- Ubuntu 18.04 ships
47
+// --sp-file scripts/coccinelle/reset-type.cocci \
34
+ # with pkg-config --static --libs data for gio-2.0 that is missing
48
+// --keep-comments --smpl-spacing --in-place --include-headers \
35
+ # -lblkid and will give a link error.
49
+// --dir $dir; done
36
+ write_c_skeleton
50
+//
37
+ if compile_prog "" "gio_libs" ; then
51
+// This coccinelle script aims to produce a complete change that needs
38
+ gio=yes
52
+// no human interaction, so as well as the generic "update device
39
+ else
53
+// implementations of the hold and exit phase methods" it includes
40
+ gio=no
54
+// the special-case transformations needed for the core code and for
41
+ fi
55
+// one device model that does something a bit nonstandard. Those
42
else
56
+// special cases are at the end of the file.
43
gio=no
57
+
44
fi
58
+// Look for where we use a function as a ResettableHoldPhase method,
59
+// either by directly assigning it to phases.hold or by calling
60
+// resettable_class_set_parent_phases, and remember the function name.
61
+@ holdfn_assigned @
62
+identifier enterfn, holdfn, exitfn;
63
+identifier rc;
64
+expression e;
65
+@@
66
+ResettableClass *rc;
67
+...
68
+(
69
+ rc->phases.hold = holdfn;
70
+|
71
+ resettable_class_set_parent_phases(rc, enterfn, holdfn, exitfn, e);
72
+)
73
+
74
+// Look for the definition of the function we found in holdfn_assigned,
75
+// and add the new argument. If the function calls a hold function
76
+// itself (probably chaining to the parent class reset) then add the
77
+// new argument there too.
78
+@ holdfn_defined @
79
+identifier holdfn_assigned.holdfn;
80
+typedef Object;
81
+identifier obj;
82
+expression parent;
83
+@@
84
+-holdfn(Object *obj)
85
++holdfn(Object *obj, ResetType type)
86
+{
87
+ <...
88
+- parent.hold(obj)
89
++ parent.hold(obj, type)
90
+ ...>
91
+}
92
+
93
+// Similarly for ResettableExitPhase.
94
+@ exitfn_assigned @
95
+identifier enterfn, holdfn, exitfn;
96
+identifier rc;
97
+expression e;
98
+@@
99
+ResettableClass *rc;
100
+...
101
+(
102
+ rc->phases.exit = exitfn;
103
+|
104
+ resettable_class_set_parent_phases(rc, enterfn, holdfn, exitfn, e);
105
+)
106
+@ exitfn_defined @
107
+identifier exitfn_assigned.exitfn;
108
+typedef Object;
109
+identifier obj;
110
+expression parent;
111
+@@
112
+-exitfn(Object *obj)
113
++exitfn(Object *obj, ResetType type)
114
+{
115
+ <...
116
+- parent.exit(obj)
117
++ parent.exit(obj, type)
118
+ ...>
119
+}
120
+
121
+// SPECIAL CASES ONLY BELOW HERE
122
+// We use a python scripted constraint on the position of the match
123
+// to ensure that they only match in a particular function. See
124
+// https://public-inbox.org/git/alpine.DEB.2.21.1808240652370.2344@hadrien/
125
+// which recommends this as the way to do "match only in this function".
126
+
127
+// Special case: isl_pmbus_vr.c has some reset methods calling others directly
128
+@ isl_pmbus_vr @
129
+identifier obj;
130
+@@
131
+- isl_pmbus_vr_exit_reset(obj);
132
++ isl_pmbus_vr_exit_reset(obj, type);
133
+
134
+// Special case: device_phases_reset() needs to pass RESET_TYPE_COLD
135
+@ device_phases_reset_hold @
136
+expression obj;
137
+identifier rc;
138
+identifier phase;
139
+position p : script:python() { p[0].current_element == "device_phases_reset" };
140
+@@
141
+- rc->phases.phase(obj)@p
142
++ rc->phases.phase(obj, RESET_TYPE_COLD)
143
+
144
+// Special case: in resettable_phase_hold() and resettable_phase_exit()
145
+// we need to pass through the ResetType argument to the method being called
146
+@ resettable_phase_hold @
147
+expression obj;
148
+identifier rc;
149
+position p : script:python() { p[0].current_element == "resettable_phase_hold" };
150
+@@
151
+- rc->phases.hold(obj)@p
152
++ rc->phases.hold(obj, type)
153
+@ resettable_phase_exit @
154
+expression obj;
155
+identifier rc;
156
+position p : script:python() { p[0].current_element == "resettable_phase_exit" };
157
+@@
158
+- rc->phases.exit(obj)@p
159
++ rc->phases.exit(obj, type)
160
+// Special case: the typedefs for the methods need to declare the new argument
161
+@ phase_typedef_hold @
162
+identifier obj;
163
+@@
164
+- typedef void (*ResettableHoldPhase)(Object *obj);
165
++ typedef void (*ResettableHoldPhase)(Object *obj, ResetType type);
166
+@ phase_typedef_exit @
167
+identifier obj;
168
+@@
169
+- typedef void (*ResettableExitPhase)(Object *obj);
170
++ typedef void (*ResettableExitPhase)(Object *obj, ResetType type);
45
--
171
--
46
2.20.1
172
2.34.1
47
48
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
We pass a ResetType argument to the Resettable class enter
2
phase method, but we don't pass it to hold and exit, even though
3
the callsites have it readily available. This means that if
4
a device cared about the ResetType it would need to record it
5
in the enter phase method to use later on. Pass the type to
6
all three of the phase methods to avoid having to do that.
2
7
3
Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
8
Commit created with
4
This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):
5
9
6
CID 1432363 (#1 of 1): Unintentional integer overflow:
10
for dir in hw target include; do \
11
spatch --macro-file scripts/cocci-macro-file.h \
12
--sp-file scripts/coccinelle/reset-type.cocci \
13
--keep-comments --smpl-spacing --in-place \
14
--include-headers --dir $dir; done
7
15
8
overflow_before_widen:
16
and no manual edits.
9
Potentially overflowing expression 1 << scale with type int
10
(32 bits, signed) is evaluated using 32-bit arithmetic, and
11
then used in a context that expects an expression of type
12
hwaddr (64 bits, unsigned).
13
17
14
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Acked-by: Eric Auger <eric.auger@redhat.com>
16
Message-id: 20201030144617.1535064-1-philmd@redhat.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Luc Michel <luc.michel@amd.com>
22
Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org
19
---
23
---
20
hw/arm/smmuv3.c | 3 ++-
24
include/hw/resettable.h | 4 ++--
21
1 file changed, 2 insertions(+), 1 deletion(-)
25
hw/adc/npcm7xx_adc.c | 2 +-
26
hw/arm/pxa2xx_pic.c | 2 +-
27
hw/arm/smmu-common.c | 2 +-
28
hw/arm/smmuv3.c | 4 ++--
29
hw/arm/stellaris.c | 10 +++++-----
30
hw/audio/asc.c | 2 +-
31
hw/char/cadence_uart.c | 2 +-
32
hw/char/sifive_uart.c | 2 +-
33
hw/core/cpu-common.c | 2 +-
34
hw/core/qdev.c | 4 ++--
35
hw/core/reset.c | 2 +-
36
hw/core/resettable.c | 4 ++--
37
hw/display/virtio-vga.c | 4 ++--
38
hw/gpio/npcm7xx_gpio.c | 2 +-
39
hw/gpio/pl061.c | 2 +-
40
hw/gpio/stm32l4x5_gpio.c | 2 +-
41
hw/hyperv/vmbus.c | 2 +-
42
hw/i2c/allwinner-i2c.c | 2 +-
43
hw/i2c/npcm7xx_smbus.c | 2 +-
44
hw/input/adb.c | 2 +-
45
hw/input/ps2.c | 12 ++++++------
46
hw/intc/arm_gic_common.c | 2 +-
47
hw/intc/arm_gic_kvm.c | 4 ++--
48
hw/intc/arm_gicv3_common.c | 2 +-
49
hw/intc/arm_gicv3_its.c | 4 ++--
50
hw/intc/arm_gicv3_its_common.c | 2 +-
51
hw/intc/arm_gicv3_its_kvm.c | 4 ++--
52
hw/intc/arm_gicv3_kvm.c | 4 ++--
53
hw/intc/xics.c | 2 +-
54
hw/m68k/q800-glue.c | 2 +-
55
hw/misc/djmemc.c | 2 +-
56
hw/misc/iosb.c | 2 +-
57
hw/misc/mac_via.c | 8 ++++----
58
hw/misc/macio/cuda.c | 4 ++--
59
hw/misc/macio/pmu.c | 4 ++--
60
hw/misc/mos6522.c | 2 +-
61
hw/misc/npcm7xx_mft.c | 2 +-
62
hw/misc/npcm7xx_pwm.c | 2 +-
63
hw/misc/stm32l4x5_exti.c | 2 +-
64
hw/misc/stm32l4x5_rcc.c | 10 +++++-----
65
hw/misc/stm32l4x5_syscfg.c | 2 +-
66
hw/misc/xlnx-versal-cframe-reg.c | 2 +-
67
hw/misc/xlnx-versal-crl.c | 2 +-
68
hw/misc/xlnx-versal-pmc-iou-slcr.c | 2 +-
69
hw/misc/xlnx-versal-trng.c | 2 +-
70
hw/misc/xlnx-versal-xramc.c | 2 +-
71
hw/misc/xlnx-zynqmp-apu-ctrl.c | 2 +-
72
hw/misc/xlnx-zynqmp-crf.c | 2 +-
73
hw/misc/zynq_slcr.c | 4 ++--
74
hw/net/can/xlnx-zynqmp-can.c | 2 +-
75
hw/net/e1000.c | 2 +-
76
hw/net/e1000e.c | 2 +-
77
hw/net/igb.c | 2 +-
78
hw/net/igbvf.c | 2 +-
79
hw/nvram/xlnx-bbram.c | 2 +-
80
hw/nvram/xlnx-versal-efuse-ctrl.c | 2 +-
81
hw/nvram/xlnx-zynqmp-efuse.c | 2 +-
82
hw/pci-bridge/cxl_root_port.c | 4 ++--
83
hw/pci-bridge/pcie_root_port.c | 2 +-
84
hw/pci-host/bonito.c | 2 +-
85
hw/pci-host/pnv_phb.c | 4 ++--
86
hw/pci-host/pnv_phb3_msi.c | 4 ++--
87
hw/pci/pci.c | 4 ++--
88
hw/rtc/mc146818rtc.c | 2 +-
89
hw/s390x/css-bridge.c | 2 +-
90
hw/sensor/adm1266.c | 2 +-
91
hw/sensor/adm1272.c | 2 +-
92
hw/sensor/isl_pmbus_vr.c | 10 +++++-----
93
hw/sensor/max31785.c | 2 +-
94
hw/sensor/max34451.c | 2 +-
95
hw/ssi/npcm7xx_fiu.c | 2 +-
96
hw/timer/etraxfs_timer.c | 2 +-
97
hw/timer/npcm7xx_timer.c | 2 +-
98
hw/usb/hcd-dwc2.c | 8 ++++----
99
hw/usb/xlnx-versal-usb2-ctrl-regs.c | 2 +-
100
hw/virtio/virtio-pci.c | 2 +-
101
target/arm/cpu.c | 4 ++--
102
target/avr/cpu.c | 4 ++--
103
target/cris/cpu.c | 4 ++--
104
target/hexagon/cpu.c | 4 ++--
105
target/i386/cpu.c | 4 ++--
106
target/loongarch/cpu.c | 4 ++--
107
target/m68k/cpu.c | 4 ++--
108
target/microblaze/cpu.c | 4 ++--
109
target/mips/cpu.c | 4 ++--
110
target/openrisc/cpu.c | 4 ++--
111
target/ppc/cpu_init.c | 4 ++--
112
target/riscv/cpu.c | 4 ++--
113
target/rx/cpu.c | 4 ++--
114
target/sh4/cpu.c | 4 ++--
115
target/sparc/cpu.c | 4 ++--
116
target/tricore/cpu.c | 4 ++--
117
target/xtensa/cpu.c | 4 ++--
118
94 files changed, 150 insertions(+), 150 deletions(-)
22
119
120
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
121
index XXXXXXX..XXXXXXX 100644
122
--- a/include/hw/resettable.h
123
+++ b/include/hw/resettable.h
124
@@ -XXX,XX +XXX,XX @@ typedef enum ResetType {
125
* the callback.
126
*/
127
typedef void (*ResettableEnterPhase)(Object *obj, ResetType type);
128
-typedef void (*ResettableHoldPhase)(Object *obj);
129
-typedef void (*ResettableExitPhase)(Object *obj);
130
+typedef void (*ResettableHoldPhase)(Object *obj, ResetType type);
131
+typedef void (*ResettableExitPhase)(Object *obj, ResetType type);
132
typedef ResettableState * (*ResettableGetState)(Object *obj);
133
typedef void (*ResettableTrFunction)(Object *obj);
134
typedef ResettableTrFunction (*ResettableGetTrFunction)(Object *obj);
135
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
136
index XXXXXXX..XXXXXXX 100644
137
--- a/hw/adc/npcm7xx_adc.c
138
+++ b/hw/adc/npcm7xx_adc.c
139
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
140
npcm7xx_adc_reset(s);
141
}
142
143
-static void npcm7xx_adc_hold_reset(Object *obj)
144
+static void npcm7xx_adc_hold_reset(Object *obj, ResetType type)
145
{
146
NPCM7xxADCState *s = NPCM7XX_ADC(obj);
147
148
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
149
index XXXXXXX..XXXXXXX 100644
150
--- a/hw/arm/pxa2xx_pic.c
151
+++ b/hw/arm/pxa2xx_pic.c
152
@@ -XXX,XX +XXX,XX @@ static int pxa2xx_pic_post_load(void *opaque, int version_id)
153
return 0;
154
}
155
156
-static void pxa2xx_pic_reset_hold(Object *obj)
157
+static void pxa2xx_pic_reset_hold(Object *obj, ResetType type)
158
{
159
PXA2xxPICState *s = PXA2XX_PIC(obj);
160
161
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
162
index XXXXXXX..XXXXXXX 100644
163
--- a/hw/arm/smmu-common.c
164
+++ b/hw/arm/smmu-common.c
165
@@ -XXX,XX +XXX,XX @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
166
}
167
}
168
169
-static void smmu_base_reset_hold(Object *obj)
170
+static void smmu_base_reset_hold(Object *obj, ResetType type)
171
{
172
SMMUState *s = ARM_SMMU(obj);
173
23
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
174
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
24
index XXXXXXX..XXXXXXX 100644
175
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/smmuv3.c
176
--- a/hw/arm/smmuv3.c
26
+++ b/hw/arm/smmuv3.c
177
+++ b/hw/arm/smmuv3.c
178
@@ -XXX,XX +XXX,XX @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
179
}
180
}
181
182
-static void smmu_reset_hold(Object *obj)
183
+static void smmu_reset_hold(Object *obj, ResetType type)
184
{
185
SMMUv3State *s = ARM_SMMUV3(obj);
186
SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
187
188
if (c->parent_phases.hold) {
189
- c->parent_phases.hold(obj);
190
+ c->parent_phases.hold(obj, type);
191
}
192
193
smmuv3_init_regs(s);
194
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
195
index XXXXXXX..XXXXXXX 100644
196
--- a/hw/arm/stellaris.c
197
+++ b/hw/arm/stellaris.c
198
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_reset_enter(Object *obj, ResetType type)
199
s->dcgc[0] = 1;
200
}
201
202
-static void stellaris_sys_reset_hold(Object *obj)
203
+static void stellaris_sys_reset_hold(Object *obj, ResetType type)
204
{
205
ssys_state *s = STELLARIS_SYS(obj);
206
207
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_reset_hold(Object *obj)
208
ssys_calculate_system_clock(s, true);
209
}
210
211
-static void stellaris_sys_reset_exit(Object *obj)
212
+static void stellaris_sys_reset_exit(Object *obj, ResetType type)
213
{
214
}
215
216
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset_enter(Object *obj, ResetType type)
217
i2c_end_transfer(s->bus);
218
}
219
220
-static void stellaris_i2c_reset_hold(Object *obj)
221
+static void stellaris_i2c_reset_hold(Object *obj, ResetType type)
222
{
223
stellaris_i2c_state *s = STELLARIS_I2C(obj);
224
225
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset_hold(Object *obj)
226
s->mcr = 0;
227
}
228
229
-static void stellaris_i2c_reset_exit(Object *obj)
230
+static void stellaris_i2c_reset_exit(Object *obj, ResetType type)
231
{
232
stellaris_i2c_state *s = STELLARIS_I2C(obj);
233
234
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
235
}
236
}
237
238
-static void stellaris_adc_reset_hold(Object *obj)
239
+static void stellaris_adc_reset_hold(Object *obj, ResetType type)
240
{
241
StellarisADCState *s = STELLARIS_ADC(obj);
242
int n;
243
diff --git a/hw/audio/asc.c b/hw/audio/asc.c
244
index XXXXXXX..XXXXXXX 100644
245
--- a/hw/audio/asc.c
246
+++ b/hw/audio/asc.c
247
@@ -XXX,XX +XXX,XX @@ static void asc_fifo_init(ASCFIFOState *fs, int index)
248
g_free(name);
249
}
250
251
-static void asc_reset_hold(Object *obj)
252
+static void asc_reset_hold(Object *obj, ResetType type)
253
{
254
ASCState *s = ASC(obj);
255
256
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
257
index XXXXXXX..XXXXXXX 100644
258
--- a/hw/char/cadence_uart.c
259
+++ b/hw/char/cadence_uart.c
260
@@ -XXX,XX +XXX,XX @@ static void cadence_uart_reset_init(Object *obj, ResetType type)
261
s->r[R_TTRIG] = 0x00000020;
262
}
263
264
-static void cadence_uart_reset_hold(Object *obj)
265
+static void cadence_uart_reset_hold(Object *obj, ResetType type)
266
{
267
CadenceUARTState *s = CADENCE_UART(obj);
268
269
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
270
index XXXXXXX..XXXXXXX 100644
271
--- a/hw/char/sifive_uart.c
272
+++ b/hw/char/sifive_uart.c
273
@@ -XXX,XX +XXX,XX @@ static void sifive_uart_reset_enter(Object *obj, ResetType type)
274
s->rx_fifo_len = 0;
275
}
276
277
-static void sifive_uart_reset_hold(Object *obj)
278
+static void sifive_uart_reset_hold(Object *obj, ResetType type)
279
{
280
SiFiveUARTState *s = SIFIVE_UART(obj);
281
qemu_irq_lower(s->irq);
282
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
283
index XXXXXXX..XXXXXXX 100644
284
--- a/hw/core/cpu-common.c
285
+++ b/hw/core/cpu-common.c
286
@@ -XXX,XX +XXX,XX @@ void cpu_reset(CPUState *cpu)
287
trace_cpu_reset(cpu->cpu_index);
288
}
289
290
-static void cpu_common_reset_hold(Object *obj)
291
+static void cpu_common_reset_hold(Object *obj, ResetType type)
292
{
293
CPUState *cpu = CPU(obj);
294
CPUClass *cc = CPU_GET_CLASS(cpu);
295
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
296
index XXXXXXX..XXXXXXX 100644
297
--- a/hw/core/qdev.c
298
+++ b/hw/core/qdev.c
299
@@ -XXX,XX +XXX,XX @@ static void device_phases_reset(DeviceState *dev)
300
rc->phases.enter(OBJECT(dev), RESET_TYPE_COLD);
301
}
302
if (rc->phases.hold) {
303
- rc->phases.hold(OBJECT(dev));
304
+ rc->phases.hold(OBJECT(dev), RESET_TYPE_COLD);
305
}
306
if (rc->phases.exit) {
307
- rc->phases.exit(OBJECT(dev));
308
+ rc->phases.exit(OBJECT(dev), RESET_TYPE_COLD);
309
}
310
}
311
312
diff --git a/hw/core/reset.c b/hw/core/reset.c
313
index XXXXXXX..XXXXXXX 100644
314
--- a/hw/core/reset.c
315
+++ b/hw/core/reset.c
316
@@ -XXX,XX +XXX,XX @@ static ResettableState *legacy_reset_get_state(Object *obj)
317
return &lr->reset_state;
318
}
319
320
-static void legacy_reset_hold(Object *obj)
321
+static void legacy_reset_hold(Object *obj, ResetType type)
322
{
323
LegacyReset *lr = LEGACY_RESET(obj);
324
325
diff --git a/hw/core/resettable.c b/hw/core/resettable.c
326
index XXXXXXX..XXXXXXX 100644
327
--- a/hw/core/resettable.c
328
+++ b/hw/core/resettable.c
329
@@ -XXX,XX +XXX,XX @@ static void resettable_phase_hold(Object *obj, void *opaque, ResetType type)
330
trace_resettable_transitional_function(obj, obj_typename);
331
tr_func(obj);
332
} else if (rc->phases.hold) {
333
- rc->phases.hold(obj);
334
+ rc->phases.hold(obj, type);
335
}
336
}
337
trace_resettable_phase_hold_end(obj, obj_typename, s->count);
338
@@ -XXX,XX +XXX,XX @@ static void resettable_phase_exit(Object *obj, void *opaque, ResetType type)
339
if (--s->count == 0) {
340
trace_resettable_phase_exit_exec(obj, obj_typename, !!rc->phases.exit);
341
if (rc->phases.exit && !resettable_get_tr_func(rc, obj)) {
342
- rc->phases.exit(obj);
343
+ rc->phases.exit(obj, type);
344
}
345
}
346
s->exit_phase_in_progress = false;
347
diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c
348
index XXXXXXX..XXXXXXX 100644
349
--- a/hw/display/virtio-vga.c
350
+++ b/hw/display/virtio-vga.c
351
@@ -XXX,XX +XXX,XX @@ static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
352
}
353
}
354
355
-static void virtio_vga_base_reset_hold(Object *obj)
356
+static void virtio_vga_base_reset_hold(Object *obj, ResetType type)
357
{
358
VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(obj);
359
VirtIOVGABase *vvga = VIRTIO_VGA_BASE(obj);
360
361
/* reset virtio-gpu */
362
if (klass->parent_phases.hold) {
363
- klass->parent_phases.hold(obj);
364
+ klass->parent_phases.hold(obj, type);
365
}
366
367
/* reset vga */
368
diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
369
index XXXXXXX..XXXXXXX 100644
370
--- a/hw/gpio/npcm7xx_gpio.c
371
+++ b/hw/gpio/npcm7xx_gpio.c
372
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type)
373
s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc;
374
}
375
376
-static void npcm7xx_gpio_hold_reset(Object *obj)
377
+static void npcm7xx_gpio_hold_reset(Object *obj, ResetType type)
378
{
379
NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
380
381
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
382
index XXXXXXX..XXXXXXX 100644
383
--- a/hw/gpio/pl061.c
384
+++ b/hw/gpio/pl061.c
385
@@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type)
386
s->amsel = 0;
387
}
388
389
-static void pl061_hold_reset(Object *obj)
390
+static void pl061_hold_reset(Object *obj, ResetType type)
391
{
392
PL061State *s = PL061(obj);
393
int i, level;
394
diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c
395
index XXXXXXX..XXXXXXX 100644
396
--- a/hw/gpio/stm32l4x5_gpio.c
397
+++ b/hw/gpio/stm32l4x5_gpio.c
398
@@ -XXX,XX +XXX,XX @@ static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
399
return extract32(s->otyper, pin, 1) == 0;
400
}
401
402
-static void stm32l4x5_gpio_reset_hold(Object *obj)
403
+static void stm32l4x5_gpio_reset_hold(Object *obj, ResetType type)
404
{
405
Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
406
407
diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c
408
index XXXXXXX..XXXXXXX 100644
409
--- a/hw/hyperv/vmbus.c
410
+++ b/hw/hyperv/vmbus.c
411
@@ -XXX,XX +XXX,XX @@ static void vmbus_unrealize(BusState *bus)
412
qemu_mutex_destroy(&vmbus->rx_queue_lock);
413
}
414
415
-static void vmbus_reset_hold(Object *obj)
416
+static void vmbus_reset_hold(Object *obj, ResetType type)
417
{
418
vmbus_deinit(VMBUS(obj));
419
}
420
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
421
index XXXXXXX..XXXXXXX 100644
422
--- a/hw/i2c/allwinner-i2c.c
423
+++ b/hw/i2c/allwinner-i2c.c
424
@@ -XXX,XX +XXX,XX @@ static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s)
425
return s->cntr & TWI_CNTR_INT_EN;
426
}
427
428
-static void allwinner_i2c_reset_hold(Object *obj)
429
+static void allwinner_i2c_reset_hold(Object *obj, ResetType type)
430
{
431
AWI2CState *s = AW_I2C(obj);
432
433
diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c
434
index XXXXXXX..XXXXXXX 100644
435
--- a/hw/i2c/npcm7xx_smbus.c
436
+++ b/hw/i2c/npcm7xx_smbus.c
437
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_smbus_enter_reset(Object *obj, ResetType type)
438
s->rx_cur = 0;
439
}
440
441
-static void npcm7xx_smbus_hold_reset(Object *obj)
442
+static void npcm7xx_smbus_hold_reset(Object *obj, ResetType type)
443
{
444
NPCM7xxSMBusState *s = NPCM7XX_SMBUS(obj);
445
446
diff --git a/hw/input/adb.c b/hw/input/adb.c
447
index XXXXXXX..XXXXXXX 100644
448
--- a/hw/input/adb.c
449
+++ b/hw/input/adb.c
450
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_adb_bus = {
451
}
452
};
453
454
-static void adb_bus_reset_hold(Object *obj)
455
+static void adb_bus_reset_hold(Object *obj, ResetType type)
456
{
457
ADBBusState *adb_bus = ADB_BUS(obj);
458
459
diff --git a/hw/input/ps2.c b/hw/input/ps2.c
460
index XXXXXXX..XXXXXXX 100644
461
--- a/hw/input/ps2.c
462
+++ b/hw/input/ps2.c
463
@@ -XXX,XX +XXX,XX @@ void ps2_write_mouse(PS2MouseState *s, int val)
464
}
465
}
466
467
-static void ps2_reset_hold(Object *obj)
468
+static void ps2_reset_hold(Object *obj, ResetType type)
469
{
470
PS2State *s = PS2_DEVICE(obj);
471
472
@@ -XXX,XX +XXX,XX @@ static void ps2_reset_hold(Object *obj)
473
ps2_reset_queue(s);
474
}
475
476
-static void ps2_reset_exit(Object *obj)
477
+static void ps2_reset_exit(Object *obj, ResetType type)
478
{
479
PS2State *s = PS2_DEVICE(obj);
480
481
@@ -XXX,XX +XXX,XX @@ static void ps2_common_post_load(PS2State *s)
482
q->cwptr = ccount ? (q->rptr + ccount) & (PS2_BUFFER_SIZE - 1) : -1;
483
}
484
485
-static void ps2_kbd_reset_hold(Object *obj)
486
+static void ps2_kbd_reset_hold(Object *obj, ResetType type)
487
{
488
PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj);
489
PS2KbdState *s = PS2_KBD_DEVICE(obj);
490
@@ -XXX,XX +XXX,XX @@ static void ps2_kbd_reset_hold(Object *obj)
491
trace_ps2_kbd_reset(s);
492
493
if (ps2dc->parent_phases.hold) {
494
- ps2dc->parent_phases.hold(obj);
495
+ ps2dc->parent_phases.hold(obj, type);
496
}
497
498
s->scan_enabled = 1;
499
@@ -XXX,XX +XXX,XX @@ static void ps2_kbd_reset_hold(Object *obj)
500
s->modifiers = 0;
501
}
502
503
-static void ps2_mouse_reset_hold(Object *obj)
504
+static void ps2_mouse_reset_hold(Object *obj, ResetType type)
505
{
506
PS2DeviceClass *ps2dc = PS2_DEVICE_GET_CLASS(obj);
507
PS2MouseState *s = PS2_MOUSE_DEVICE(obj);
508
@@ -XXX,XX +XXX,XX @@ static void ps2_mouse_reset_hold(Object *obj)
509
trace_ps2_mouse_reset(s);
510
511
if (ps2dc->parent_phases.hold) {
512
- ps2dc->parent_phases.hold(obj);
513
+ ps2dc->parent_phases.hold(obj, type);
514
}
515
516
s->mouse_status = 0;
517
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
518
index XXXXXXX..XXXXXXX 100644
519
--- a/hw/intc/arm_gic_common.c
520
+++ b/hw/intc/arm_gic_common.c
521
@@ -XXX,XX +XXX,XX @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int cidx,
522
}
523
}
524
525
-static void arm_gic_common_reset_hold(Object *obj)
526
+static void arm_gic_common_reset_hold(Object *obj, ResetType type)
527
{
528
GICState *s = ARM_GIC_COMMON(obj);
529
int i, j;
530
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
531
index XXXXXXX..XXXXXXX 100644
532
--- a/hw/intc/arm_gic_kvm.c
533
+++ b/hw/intc/arm_gic_kvm.c
534
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_get(GICState *s)
535
}
536
}
537
538
-static void kvm_arm_gic_reset_hold(Object *obj)
539
+static void kvm_arm_gic_reset_hold(Object *obj, ResetType type)
540
{
541
GICState *s = ARM_GIC_COMMON(obj);
542
KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
543
544
if (kgc->parent_phases.hold) {
545
- kgc->parent_phases.hold(obj);
546
+ kgc->parent_phases.hold(obj, type);
547
}
548
549
if (kvm_arm_gic_can_save_restore(s)) {
550
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
551
index XXXXXXX..XXXXXXX 100644
552
--- a/hw/intc/arm_gicv3_common.c
553
+++ b/hw/intc/arm_gicv3_common.c
554
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_finalize(Object *obj)
555
g_free(s->redist_region_count);
556
}
557
558
-static void arm_gicv3_common_reset_hold(Object *obj)
559
+static void arm_gicv3_common_reset_hold(Object *obj, ResetType type)
560
{
561
GICv3State *s = ARM_GICV3_COMMON(obj);
562
int i;
563
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
564
index XXXXXXX..XXXXXXX 100644
565
--- a/hw/intc/arm_gicv3_its.c
566
+++ b/hw/intc/arm_gicv3_its.c
567
@@ -XXX,XX +XXX,XX @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
568
}
569
}
570
571
-static void gicv3_its_reset_hold(Object *obj)
572
+static void gicv3_its_reset_hold(Object *obj, ResetType type)
573
{
574
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
575
GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
576
577
if (c->parent_phases.hold) {
578
- c->parent_phases.hold(obj);
579
+ c->parent_phases.hold(obj, type);
580
}
581
582
/* Quiescent bit reset to 1 */
583
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
584
index XXXXXXX..XXXXXXX 100644
585
--- a/hw/intc/arm_gicv3_its_common.c
586
+++ b/hw/intc/arm_gicv3_its_common.c
587
@@ -XXX,XX +XXX,XX @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
588
msi_nonbroken = true;
589
}
590
591
-static void gicv3_its_common_reset_hold(Object *obj)
592
+static void gicv3_its_common_reset_hold(Object *obj, ResetType type)
593
{
594
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
595
596
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
597
index XXXXXXX..XXXXXXX 100644
598
--- a/hw/intc/arm_gicv3_its_kvm.c
599
+++ b/hw/intc/arm_gicv3_its_kvm.c
600
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
601
GITS_CTLR, &s->ctlr, true, &error_abort);
602
}
603
604
-static void kvm_arm_its_reset_hold(Object *obj)
605
+static void kvm_arm_its_reset_hold(Object *obj, ResetType type)
606
{
607
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
608
KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
609
int i;
610
611
if (c->parent_phases.hold) {
612
- c->parent_phases.hold(obj);
613
+ c->parent_phases.hold(obj, type);
614
}
615
616
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
617
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
618
index XXXXXXX..XXXXXXX 100644
619
--- a/hw/intc/arm_gicv3_kvm.c
620
+++ b/hw/intc/arm_gicv3_kvm.c
621
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
622
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
623
}
624
625
-static void kvm_arm_gicv3_reset_hold(Object *obj)
626
+static void kvm_arm_gicv3_reset_hold(Object *obj, ResetType type)
627
{
628
GICv3State *s = ARM_GICV3_COMMON(obj);
629
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
630
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_reset_hold(Object *obj)
631
DPRINTF("Reset\n");
632
633
if (kgc->parent_phases.hold) {
634
- kgc->parent_phases.hold(obj);
635
+ kgc->parent_phases.hold(obj, type);
636
}
637
638
if (s->migration_blocker) {
639
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
640
index XXXXXXX..XXXXXXX 100644
641
--- a/hw/intc/xics.c
642
+++ b/hw/intc/xics.c
643
@@ -XXX,XX +XXX,XX @@ static void ics_reset_irq(ICSIRQState *irq)
644
irq->saved_priority = 0xff;
645
}
646
647
-static void ics_reset_hold(Object *obj)
648
+static void ics_reset_hold(Object *obj, ResetType type)
649
{
650
ICSState *ics = ICS(obj);
651
g_autofree uint8_t *flags = g_malloc(ics->nr_irqs);
652
diff --git a/hw/m68k/q800-glue.c b/hw/m68k/q800-glue.c
653
index XXXXXXX..XXXXXXX 100644
654
--- a/hw/m68k/q800-glue.c
655
+++ b/hw/m68k/q800-glue.c
656
@@ -XXX,XX +XXX,XX @@ static void glue_nmi_release(void *opaque)
657
GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0);
658
}
659
660
-static void glue_reset_hold(Object *obj)
661
+static void glue_reset_hold(Object *obj, ResetType type)
662
{
663
GLUEState *s = GLUE(obj);
664
665
diff --git a/hw/misc/djmemc.c b/hw/misc/djmemc.c
666
index XXXXXXX..XXXXXXX 100644
667
--- a/hw/misc/djmemc.c
668
+++ b/hw/misc/djmemc.c
669
@@ -XXX,XX +XXX,XX @@ static void djmemc_init(Object *obj)
670
sysbus_init_mmio(sbd, &s->mem_regs);
671
}
672
673
-static void djmemc_reset_hold(Object *obj)
674
+static void djmemc_reset_hold(Object *obj, ResetType type)
675
{
676
DJMEMCState *s = DJMEMC(obj);
677
678
diff --git a/hw/misc/iosb.c b/hw/misc/iosb.c
679
index XXXXXXX..XXXXXXX 100644
680
--- a/hw/misc/iosb.c
681
+++ b/hw/misc/iosb.c
682
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps iosb_mmio_ops = {
683
.endianness = DEVICE_BIG_ENDIAN,
684
};
685
686
-static void iosb_reset_hold(Object *obj)
687
+static void iosb_reset_hold(Object *obj, ResetType type)
688
{
689
IOSBState *s = IOSB(obj);
690
691
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
692
index XXXXXXX..XXXXXXX 100644
693
--- a/hw/misc/mac_via.c
694
+++ b/hw/misc/mac_via.c
695
@@ -XXX,XX +XXX,XX @@ static int via1_post_load(void *opaque, int version_id)
696
}
697
698
/* VIA 1 */
699
-static void mos6522_q800_via1_reset_hold(Object *obj)
700
+static void mos6522_q800_via1_reset_hold(Object *obj, ResetType type)
701
{
702
MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(obj);
703
MOS6522State *ms = MOS6522(v1s);
704
@@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via1_reset_hold(Object *obj)
705
ADBBusState *adb_bus = &v1s->adb_bus;
706
707
if (mdc->parent_phases.hold) {
708
- mdc->parent_phases.hold(obj);
709
+ mdc->parent_phases.hold(obj, type);
710
}
711
712
ms->timers[0].frequency = VIA_TIMER_FREQ;
713
@@ -XXX,XX +XXX,XX @@ static void mos6522_q800_via2_portB_write(MOS6522State *s)
714
}
715
}
716
717
-static void mos6522_q800_via2_reset_hold(Object *obj)
718
+static void mos6522_q800_via2_reset_hold(Object *obj, ResetType type)
719
{
720
MOS6522State *ms = MOS6522(obj);
721
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
722
723
if (mdc->parent_phases.hold) {
724
- mdc->parent_phases.hold(obj);
725
+ mdc->parent_phases.hold(obj, type);
726
}
727
728
ms->timers[0].frequency = VIA_TIMER_FREQ;
729
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
730
index XXXXXXX..XXXXXXX 100644
731
--- a/hw/misc/macio/cuda.c
732
+++ b/hw/misc/macio/cuda.c
733
@@ -XXX,XX +XXX,XX @@ static void mos6522_cuda_portB_write(MOS6522State *s)
734
cuda_update(cs);
735
}
736
737
-static void mos6522_cuda_reset_hold(Object *obj)
738
+static void mos6522_cuda_reset_hold(Object *obj, ResetType type)
739
{
740
MOS6522State *ms = MOS6522(obj);
741
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
742
743
if (mdc->parent_phases.hold) {
744
- mdc->parent_phases.hold(obj);
745
+ mdc->parent_phases.hold(obj, type);
746
}
747
748
ms->timers[0].frequency = CUDA_TIMER_FREQ;
749
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
750
index XXXXXXX..XXXXXXX 100644
751
--- a/hw/misc/macio/pmu.c
752
+++ b/hw/misc/macio/pmu.c
753
@@ -XXX,XX +XXX,XX @@ static void mos6522_pmu_portB_write(MOS6522State *s)
754
pmu_update(ps);
755
}
756
757
-static void mos6522_pmu_reset_hold(Object *obj)
758
+static void mos6522_pmu_reset_hold(Object *obj, ResetType type)
759
{
760
MOS6522State *ms = MOS6522(obj);
761
MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj);
762
@@ -XXX,XX +XXX,XX @@ static void mos6522_pmu_reset_hold(Object *obj)
763
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
764
765
if (mdc->parent_phases.hold) {
766
- mdc->parent_phases.hold(obj);
767
+ mdc->parent_phases.hold(obj, type);
768
}
769
770
ms->timers[0].frequency = VIA_TIMER_FREQ;
771
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
772
index XXXXXXX..XXXXXXX 100644
773
--- a/hw/misc/mos6522.c
774
+++ b/hw/misc/mos6522.c
775
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_mos6522 = {
776
}
777
};
778
779
-static void mos6522_reset_hold(Object *obj)
780
+static void mos6522_reset_hold(Object *obj, ResetType type)
781
{
782
MOS6522State *s = MOS6522(obj);
783
784
diff --git a/hw/misc/npcm7xx_mft.c b/hw/misc/npcm7xx_mft.c
785
index XXXXXXX..XXXXXXX 100644
786
--- a/hw/misc/npcm7xx_mft.c
787
+++ b/hw/misc/npcm7xx_mft.c
788
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mft_enter_reset(Object *obj, ResetType type)
789
npcm7xx_mft_reset(s);
790
}
791
792
-static void npcm7xx_mft_hold_reset(Object *obj)
793
+static void npcm7xx_mft_hold_reset(Object *obj, ResetType type)
794
{
795
NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
796
797
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
798
index XXXXXXX..XXXXXXX 100644
799
--- a/hw/misc/npcm7xx_pwm.c
800
+++ b/hw/misc/npcm7xx_pwm.c
801
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
802
s->piir = 0x00000000;
803
}
804
805
-static void npcm7xx_pwm_hold_reset(Object *obj)
806
+static void npcm7xx_pwm_hold_reset(Object *obj, ResetType type)
807
{
808
NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
809
int i;
810
diff --git a/hw/misc/stm32l4x5_exti.c b/hw/misc/stm32l4x5_exti.c
811
index XXXXXXX..XXXXXXX 100644
812
--- a/hw/misc/stm32l4x5_exti.c
813
+++ b/hw/misc/stm32l4x5_exti.c
814
@@ -XXX,XX +XXX,XX @@ static unsigned configurable_mask(unsigned bank)
815
return valid_mask(bank) & ~exti_romask[bank];
816
}
817
818
-static void stm32l4x5_exti_reset_hold(Object *obj)
819
+static void stm32l4x5_exti_reset_hold(Object *obj, ResetType type)
820
{
821
Stm32l4x5ExtiState *s = STM32L4X5_EXTI(obj);
822
823
diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c
824
index XXXXXXX..XXXXXXX 100644
825
--- a/hw/misc/stm32l4x5_rcc.c
826
+++ b/hw/misc/stm32l4x5_rcc.c
827
@@ -XXX,XX +XXX,XX @@ static void clock_mux_reset_enter(Object *obj, ResetType type)
828
set_clock_mux_init_info(s, s->id);
829
}
830
831
-static void clock_mux_reset_hold(Object *obj)
832
+static void clock_mux_reset_hold(Object *obj, ResetType type)
833
{
834
RccClockMuxState *s = RCC_CLOCK_MUX(obj);
835
clock_mux_update(s, true);
836
}
837
838
-static void clock_mux_reset_exit(Object *obj)
839
+static void clock_mux_reset_exit(Object *obj, ResetType type)
840
{
841
RccClockMuxState *s = RCC_CLOCK_MUX(obj);
842
clock_mux_update(s, false);
843
@@ -XXX,XX +XXX,XX @@ static void pll_reset_enter(Object *obj, ResetType type)
844
set_pll_init_info(s, s->id);
845
}
846
847
-static void pll_reset_hold(Object *obj)
848
+static void pll_reset_hold(Object *obj, ResetType type)
849
{
850
RccPllState *s = RCC_PLL(obj);
851
pll_update(s, true);
852
}
853
854
-static void pll_reset_exit(Object *obj)
855
+static void pll_reset_exit(Object *obj, ResetType type)
856
{
857
RccPllState *s = RCC_PLL(obj);
858
pll_update(s, false);
859
@@ -XXX,XX +XXX,XX @@ static void rcc_update_csr(Stm32l4x5RccState *s)
860
rcc_update_irq(s);
861
}
862
863
-static void stm32l4x5_rcc_reset_hold(Object *obj)
864
+static void stm32l4x5_rcc_reset_hold(Object *obj, ResetType type)
865
{
866
Stm32l4x5RccState *s = STM32L4X5_RCC(obj);
867
s->cr = 0x00000063;
868
diff --git a/hw/misc/stm32l4x5_syscfg.c b/hw/misc/stm32l4x5_syscfg.c
869
index XXXXXXX..XXXXXXX 100644
870
--- a/hw/misc/stm32l4x5_syscfg.c
871
+++ b/hw/misc/stm32l4x5_syscfg.c
27
@@ -XXX,XX +XXX,XX @@
872
@@ -XXX,XX +XXX,XX @@
873
874
#define NUM_LINES_PER_EXTICR_REG 4
875
876
-static void stm32l4x5_syscfg_hold_reset(Object *obj)
877
+static void stm32l4x5_syscfg_hold_reset(Object *obj, ResetType type)
878
{
879
Stm32l4x5SyscfgState *s = STM32L4X5_SYSCFG(obj);
880
881
diff --git a/hw/misc/xlnx-versal-cframe-reg.c b/hw/misc/xlnx-versal-cframe-reg.c
882
index XXXXXXX..XXXXXXX 100644
883
--- a/hw/misc/xlnx-versal-cframe-reg.c
884
+++ b/hw/misc/xlnx-versal-cframe-reg.c
885
@@ -XXX,XX +XXX,XX @@ static void cframe_reg_reset_enter(Object *obj, ResetType type)
886
}
887
}
888
889
-static void cframe_reg_reset_hold(Object *obj)
890
+static void cframe_reg_reset_hold(Object *obj, ResetType type)
891
{
892
XlnxVersalCFrameReg *s = XLNX_VERSAL_CFRAME_REG(obj);
893
894
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
895
index XXXXXXX..XXXXXXX 100644
896
--- a/hw/misc/xlnx-versal-crl.c
897
+++ b/hw/misc/xlnx-versal-crl.c
898
@@ -XXX,XX +XXX,XX @@ static void crl_reset_enter(Object *obj, ResetType type)
899
}
900
}
901
902
-static void crl_reset_hold(Object *obj)
903
+static void crl_reset_hold(Object *obj, ResetType type)
904
{
905
XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
906
907
diff --git a/hw/misc/xlnx-versal-pmc-iou-slcr.c b/hw/misc/xlnx-versal-pmc-iou-slcr.c
908
index XXXXXXX..XXXXXXX 100644
909
--- a/hw/misc/xlnx-versal-pmc-iou-slcr.c
910
+++ b/hw/misc/xlnx-versal-pmc-iou-slcr.c
911
@@ -XXX,XX +XXX,XX @@ static void xlnx_versal_pmc_iou_slcr_reset_init(Object *obj, ResetType type)
912
}
913
}
914
915
-static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj)
916
+static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj, ResetType type)
917
{
918
XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj);
919
920
diff --git a/hw/misc/xlnx-versal-trng.c b/hw/misc/xlnx-versal-trng.c
921
index XXXXXXX..XXXXXXX 100644
922
--- a/hw/misc/xlnx-versal-trng.c
923
+++ b/hw/misc/xlnx-versal-trng.c
924
@@ -XXX,XX +XXX,XX @@ static void trng_unrealize(DeviceState *dev)
925
s->prng = NULL;
926
}
927
928
-static void trng_reset_hold(Object *obj)
929
+static void trng_reset_hold(Object *obj, ResetType type)
930
{
931
trng_reset(XLNX_VERSAL_TRNG(obj));
932
}
933
diff --git a/hw/misc/xlnx-versal-xramc.c b/hw/misc/xlnx-versal-xramc.c
934
index XXXXXXX..XXXXXXX 100644
935
--- a/hw/misc/xlnx-versal-xramc.c
936
+++ b/hw/misc/xlnx-versal-xramc.c
937
@@ -XXX,XX +XXX,XX @@ static void xram_ctrl_reset_enter(Object *obj, ResetType type)
938
ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size);
939
}
940
941
-static void xram_ctrl_reset_hold(Object *obj)
942
+static void xram_ctrl_reset_hold(Object *obj, ResetType type)
943
{
944
XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
945
946
diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c
947
index XXXXXXX..XXXXXXX 100644
948
--- a/hw/misc/xlnx-zynqmp-apu-ctrl.c
949
+++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c
950
@@ -XXX,XX +XXX,XX @@ static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
951
s->cpu_in_wfi = 0;
952
}
953
954
-static void zynqmp_apu_reset_hold(Object *obj)
955
+static void zynqmp_apu_reset_hold(Object *obj, ResetType type)
956
{
957
XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
958
959
diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c
960
index XXXXXXX..XXXXXXX 100644
961
--- a/hw/misc/xlnx-zynqmp-crf.c
962
+++ b/hw/misc/xlnx-zynqmp-crf.c
963
@@ -XXX,XX +XXX,XX @@ static void crf_reset_enter(Object *obj, ResetType type)
964
}
965
}
966
967
-static void crf_reset_hold(Object *obj)
968
+static void crf_reset_hold(Object *obj, ResetType type)
969
{
970
XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
971
ir_update_irq(s);
972
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
973
index XXXXXXX..XXXXXXX 100644
974
--- a/hw/misc/zynq_slcr.c
975
+++ b/hw/misc/zynq_slcr.c
976
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset_init(Object *obj, ResetType type)
977
s->regs[R_DDRIOB + 12] = 0x00000021;
978
}
979
980
-static void zynq_slcr_reset_hold(Object *obj)
981
+static void zynq_slcr_reset_hold(Object *obj, ResetType type)
982
{
983
ZynqSLCRState *s = ZYNQ_SLCR(obj);
984
985
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset_hold(Object *obj)
986
zynq_slcr_propagate_clocks(s);
987
}
988
989
-static void zynq_slcr_reset_exit(Object *obj)
990
+static void zynq_slcr_reset_exit(Object *obj, ResetType type)
991
{
992
ZynqSLCRState *s = ZYNQ_SLCR(obj);
993
994
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
995
index XXXXXXX..XXXXXXX 100644
996
--- a/hw/net/can/xlnx-zynqmp-can.c
997
+++ b/hw/net/can/xlnx-zynqmp-can.c
998
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type)
999
ptimer_transaction_commit(s->can_timer);
1000
}
1001
1002
-static void xlnx_zynqmp_can_reset_hold(Object *obj)
1003
+static void xlnx_zynqmp_can_reset_hold(Object *obj, ResetType type)
1004
{
1005
XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
1006
unsigned int i;
1007
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
1008
index XXXXXXX..XXXXXXX 100644
1009
--- a/hw/net/e1000.c
1010
+++ b/hw/net/e1000.c
1011
@@ -XXX,XX +XXX,XX @@ static bool e1000_vet_init_need(void *opaque)
1012
return chkflag(VET);
1013
}
1014
1015
-static void e1000_reset_hold(Object *obj)
1016
+static void e1000_reset_hold(Object *obj, ResetType type)
1017
{
1018
E1000State *d = E1000(obj);
1019
E1000BaseClass *edc = E1000_GET_CLASS(d);
1020
diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
1021
index XXXXXXX..XXXXXXX 100644
1022
--- a/hw/net/e1000e.c
1023
+++ b/hw/net/e1000e.c
1024
@@ -XXX,XX +XXX,XX @@ static void e1000e_pci_uninit(PCIDevice *pci_dev)
1025
msi_uninit(pci_dev);
1026
}
1027
1028
-static void e1000e_qdev_reset_hold(Object *obj)
1029
+static void e1000e_qdev_reset_hold(Object *obj, ResetType type)
1030
{
1031
E1000EState *s = E1000E(obj);
1032
1033
diff --git a/hw/net/igb.c b/hw/net/igb.c
1034
index XXXXXXX..XXXXXXX 100644
1035
--- a/hw/net/igb.c
1036
+++ b/hw/net/igb.c
1037
@@ -XXX,XX +XXX,XX @@ static void igb_pci_uninit(PCIDevice *pci_dev)
1038
msi_uninit(pci_dev);
1039
}
1040
1041
-static void igb_qdev_reset_hold(Object *obj)
1042
+static void igb_qdev_reset_hold(Object *obj, ResetType type)
1043
{
1044
IGBState *s = IGB(obj);
1045
1046
diff --git a/hw/net/igbvf.c b/hw/net/igbvf.c
1047
index XXXXXXX..XXXXXXX 100644
1048
--- a/hw/net/igbvf.c
1049
+++ b/hw/net/igbvf.c
1050
@@ -XXX,XX +XXX,XX @@ static void igbvf_pci_realize(PCIDevice *dev, Error **errp)
1051
pcie_ari_init(dev, 0x150);
1052
}
1053
1054
-static void igbvf_qdev_reset_hold(Object *obj)
1055
+static void igbvf_qdev_reset_hold(Object *obj, ResetType type)
1056
{
1057
PCIDevice *vf = PCI_DEVICE(obj);
1058
1059
diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c
1060
index XXXXXXX..XXXXXXX 100644
1061
--- a/hw/nvram/xlnx-bbram.c
1062
+++ b/hw/nvram/xlnx-bbram.c
1063
@@ -XXX,XX +XXX,XX @@ static RegisterAccessInfo bbram_ctrl_regs_info[] = {
1064
}
1065
};
1066
1067
-static void bbram_ctrl_reset_hold(Object *obj)
1068
+static void bbram_ctrl_reset_hold(Object *obj, ResetType type)
1069
{
1070
XlnxBBRam *s = XLNX_BBRAM(obj);
1071
unsigned int i;
1072
diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c
1073
index XXXXXXX..XXXXXXX 100644
1074
--- a/hw/nvram/xlnx-versal-efuse-ctrl.c
1075
+++ b/hw/nvram/xlnx-versal-efuse-ctrl.c
1076
@@ -XXX,XX +XXX,XX @@ static void efuse_ctrl_register_reset(RegisterInfo *reg)
1077
register_reset(reg);
1078
}
1079
1080
-static void efuse_ctrl_reset_hold(Object *obj)
1081
+static void efuse_ctrl_reset_hold(Object *obj, ResetType type)
1082
{
1083
XlnxVersalEFuseCtrl *s = XLNX_VERSAL_EFUSE_CTRL(obj);
1084
unsigned int i;
1085
diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c
1086
index XXXXXXX..XXXXXXX 100644
1087
--- a/hw/nvram/xlnx-zynqmp-efuse.c
1088
+++ b/hw/nvram/xlnx-zynqmp-efuse.c
1089
@@ -XXX,XX +XXX,XX @@ static void zynqmp_efuse_register_reset(RegisterInfo *reg)
1090
register_reset(reg);
1091
}
1092
1093
-static void zynqmp_efuse_reset_hold(Object *obj)
1094
+static void zynqmp_efuse_reset_hold(Object *obj, ResetType type)
1095
{
1096
XlnxZynqMPEFuse *s = XLNX_ZYNQMP_EFUSE(obj);
1097
unsigned int i;
1098
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
1099
index XXXXXXX..XXXXXXX 100644
1100
--- a/hw/pci-bridge/cxl_root_port.c
1101
+++ b/hw/pci-bridge/cxl_root_port.c
1102
@@ -XXX,XX +XXX,XX @@ static void cxl_rp_realize(DeviceState *dev, Error **errp)
1103
component_bar);
1104
}
1105
1106
-static void cxl_rp_reset_hold(Object *obj)
1107
+static void cxl_rp_reset_hold(Object *obj, ResetType type)
1108
{
1109
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
1110
CXLRootPort *crp = CXL_ROOT_PORT(obj);
1111
1112
if (rpc->parent_phases.hold) {
1113
- rpc->parent_phases.hold(obj);
1114
+ rpc->parent_phases.hold(obj, type);
1115
}
1116
1117
latch_registers(crp);
1118
diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
1119
index XXXXXXX..XXXXXXX 100644
1120
--- a/hw/pci-bridge/pcie_root_port.c
1121
+++ b/hw/pci-bridge/pcie_root_port.c
1122
@@ -XXX,XX +XXX,XX @@ static void rp_write_config(PCIDevice *d, uint32_t address,
1123
pcie_aer_root_write_config(d, address, val, len, root_cmd);
1124
}
1125
1126
-static void rp_reset_hold(Object *obj)
1127
+static void rp_reset_hold(Object *obj, ResetType type)
1128
{
1129
PCIDevice *d = PCI_DEVICE(obj);
1130
DeviceState *qdev = DEVICE(obj);
1131
diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c
1132
index XXXXXXX..XXXXXXX 100644
1133
--- a/hw/pci-host/bonito.c
1134
+++ b/hw/pci-host/bonito.c
1135
@@ -XXX,XX +XXX,XX @@ static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
1136
}
1137
}
1138
1139
-static void bonito_reset_hold(Object *obj)
1140
+static void bonito_reset_hold(Object *obj, ResetType type)
1141
{
1142
PCIBonitoState *s = PCI_BONITO(obj);
1143
uint32_t val = 0;
1144
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
1145
index XXXXXXX..XXXXXXX 100644
1146
--- a/hw/pci-host/pnv_phb.c
1147
+++ b/hw/pci-host/pnv_phb.c
1148
@@ -XXX,XX +XXX,XX @@ static void pnv_phb_class_init(ObjectClass *klass, void *data)
1149
dc->user_creatable = true;
1150
}
1151
1152
-static void pnv_phb_root_port_reset_hold(Object *obj)
1153
+static void pnv_phb_root_port_reset_hold(Object *obj, ResetType type)
1154
{
1155
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
1156
PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj);
1157
@@ -XXX,XX +XXX,XX @@ static void pnv_phb_root_port_reset_hold(Object *obj)
1158
uint8_t *conf = d->config;
1159
1160
if (rpc->parent_phases.hold) {
1161
- rpc->parent_phases.hold(obj);
1162
+ rpc->parent_phases.hold(obj, type);
1163
}
1164
1165
if (phb_rp->version == 3) {
1166
diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c
1167
index XXXXXXX..XXXXXXX 100644
1168
--- a/hw/pci-host/pnv_phb3_msi.c
1169
+++ b/hw/pci-host/pnv_phb3_msi.c
1170
@@ -XXX,XX +XXX,XX @@ static void phb3_msi_resend(ICSState *ics)
1171
}
1172
}
1173
1174
-static void phb3_msi_reset_hold(Object *obj)
1175
+static void phb3_msi_reset_hold(Object *obj, ResetType type)
1176
{
1177
Phb3MsiState *msi = PHB3_MSI(obj);
1178
ICSStateClass *icsc = ICS_GET_CLASS(obj);
1179
1180
if (icsc->parent_phases.hold) {
1181
- icsc->parent_phases.hold(obj);
1182
+ icsc->parent_phases.hold(obj, type);
1183
}
1184
1185
memset(msi->rba, 0, sizeof(msi->rba));
1186
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
1187
index XXXXXXX..XXXXXXX 100644
1188
--- a/hw/pci/pci.c
1189
+++ b/hw/pci/pci.c
1190
@@ -XXX,XX +XXX,XX @@ bool pci_available = true;
1191
1192
static char *pcibus_get_dev_path(DeviceState *dev);
1193
static char *pcibus_get_fw_dev_path(DeviceState *dev);
1194
-static void pcibus_reset_hold(Object *obj);
1195
+static void pcibus_reset_hold(Object *obj, ResetType type);
1196
static bool pcie_has_upstream_port(PCIDevice *dev);
1197
1198
static Property pci_props[] = {
1199
@@ -XXX,XX +XXX,XX @@ void pci_device_reset(PCIDevice *dev)
1200
* Called via bus_cold_reset on RST# assert, after the devices
1201
* have been reset device_cold_reset-ed already.
28
*/
1202
*/
29
1203
-static void pcibus_reset_hold(Object *obj)
30
#include "qemu/osdep.h"
1204
+static void pcibus_reset_hold(Object *obj, ResetType type)
31
+#include "qemu/bitops.h"
1205
{
32
#include "hw/irq.h"
1206
PCIBus *bus = PCI_BUS(obj);
33
#include "hw/sysbus.h"
1207
int i;
34
#include "migration/vmstate.h"
1208
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
35
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
1209
index XXXXXXX..XXXXXXX 100644
36
scale = CMD_SCALE(cmd);
1210
--- a/hw/rtc/mc146818rtc.c
37
num = CMD_NUM(cmd);
1211
+++ b/hw/rtc/mc146818rtc.c
38
ttl = CMD_TTL(cmd);
1212
@@ -XXX,XX +XXX,XX @@ static void rtc_reset_enter(Object *obj, ResetType type)
39
- num_pages = (num + 1) * (1 << (scale));
1213
}
40
+ num_pages = (num + 1) * BIT_ULL(scale);
1214
}
41
}
1215
42
1216
-static void rtc_reset_hold(Object *obj)
43
if (type == SMMU_CMD_TLBI_NH_VA) {
1217
+static void rtc_reset_hold(Object *obj, ResetType type)
1218
{
1219
MC146818RtcState *s = MC146818_RTC(obj);
1220
1221
diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c
1222
index XXXXXXX..XXXXXXX 100644
1223
--- a/hw/s390x/css-bridge.c
1224
+++ b/hw/s390x/css-bridge.c
1225
@@ -XXX,XX +XXX,XX @@ static void ccw_device_unplug(HotplugHandler *hotplug_dev,
1226
qdev_unrealize(dev);
1227
}
1228
1229
-static void virtual_css_bus_reset_hold(Object *obj)
1230
+static void virtual_css_bus_reset_hold(Object *obj, ResetType type)
1231
{
1232
/* This should actually be modelled via the generic css */
1233
css_reset();
1234
diff --git a/hw/sensor/adm1266.c b/hw/sensor/adm1266.c
1235
index XXXXXXX..XXXXXXX 100644
1236
--- a/hw/sensor/adm1266.c
1237
+++ b/hw/sensor/adm1266.c
1238
@@ -XXX,XX +XXX,XX @@ static const uint8_t adm1266_ic_device_id[] = {0x03, 0x41, 0x12, 0x66};
1239
static const uint8_t adm1266_ic_device_rev[] = {0x08, 0x01, 0x08, 0x07, 0x0,
1240
0x0, 0x07, 0x41, 0x30};
1241
1242
-static void adm1266_exit_reset(Object *obj)
1243
+static void adm1266_exit_reset(Object *obj, ResetType type)
1244
{
1245
ADM1266State *s = ADM1266(obj);
1246
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
1247
diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c
1248
index XXXXXXX..XXXXXXX 100644
1249
--- a/hw/sensor/adm1272.c
1250
+++ b/hw/sensor/adm1272.c
1251
@@ -XXX,XX +XXX,XX @@ static uint32_t adm1272_direct_to_watts(uint16_t value)
1252
return pmbus_direct_mode2data(c, value);
1253
}
1254
1255
-static void adm1272_exit_reset(Object *obj)
1256
+static void adm1272_exit_reset(Object *obj, ResetType type)
1257
{
1258
ADM1272State *s = ADM1272(obj);
1259
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
1260
diff --git a/hw/sensor/isl_pmbus_vr.c b/hw/sensor/isl_pmbus_vr.c
1261
index XXXXXXX..XXXXXXX 100644
1262
--- a/hw/sensor/isl_pmbus_vr.c
1263
+++ b/hw/sensor/isl_pmbus_vr.c
1264
@@ -XXX,XX +XXX,XX @@ static void isl_pmbus_vr_set(Object *obj, Visitor *v, const char *name,
1265
pmbus_check_limits(pmdev);
1266
}
1267
1268
-static void isl_pmbus_vr_exit_reset(Object *obj)
1269
+static void isl_pmbus_vr_exit_reset(Object *obj, ResetType type)
1270
{
1271
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
1272
1273
@@ -XXX,XX +XXX,XX @@ static void isl_pmbus_vr_exit_reset(Object *obj)
1274
}
1275
1276
/* The raa228000 uses different direct mode coefficients from most isl devices */
1277
-static void raa228000_exit_reset(Object *obj)
1278
+static void raa228000_exit_reset(Object *obj, ResetType type)
1279
{
1280
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
1281
1282
- isl_pmbus_vr_exit_reset(obj);
1283
+ isl_pmbus_vr_exit_reset(obj, type);
1284
1285
pmdev->pages[0].read_iout = 0;
1286
pmdev->pages[0].read_pout = 0;
1287
@@ -XXX,XX +XXX,XX @@ static void raa228000_exit_reset(Object *obj)
1288
pmdev->pages[0].read_temperature_3 = 0;
1289
}
1290
1291
-static void isl69259_exit_reset(Object *obj)
1292
+static void isl69259_exit_reset(Object *obj, ResetType type)
1293
{
1294
ISLState *s = ISL69260(obj);
1295
static const uint8_t ic_device_id[] = {0x04, 0x00, 0x81, 0xD2, 0x49, 0x3c};
1296
g_assert(sizeof(ic_device_id) <= sizeof(s->ic_device_id));
1297
1298
- isl_pmbus_vr_exit_reset(obj);
1299
+ isl_pmbus_vr_exit_reset(obj, type);
1300
1301
s->ic_device_id_len = sizeof(ic_device_id);
1302
memcpy(s->ic_device_id, ic_device_id, sizeof(ic_device_id));
1303
diff --git a/hw/sensor/max31785.c b/hw/sensor/max31785.c
1304
index XXXXXXX..XXXXXXX 100644
1305
--- a/hw/sensor/max31785.c
1306
+++ b/hw/sensor/max31785.c
1307
@@ -XXX,XX +XXX,XX @@ static int max31785_write_data(PMBusDevice *pmdev, const uint8_t *buf,
1308
return 0;
1309
}
1310
1311
-static void max31785_exit_reset(Object *obj)
1312
+static void max31785_exit_reset(Object *obj, ResetType type)
1313
{
1314
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
1315
MAX31785State *s = MAX31785(obj);
1316
diff --git a/hw/sensor/max34451.c b/hw/sensor/max34451.c
1317
index XXXXXXX..XXXXXXX 100644
1318
--- a/hw/sensor/max34451.c
1319
+++ b/hw/sensor/max34451.c
1320
@@ -XXX,XX +XXX,XX @@ static inline void *memset_word(void *s, uint16_t c, size_t n)
1321
return s;
1322
}
1323
1324
-static void max34451_exit_reset(Object *obj)
1325
+static void max34451_exit_reset(Object *obj, ResetType type)
1326
{
1327
PMBusDevice *pmdev = PMBUS_DEVICE(obj);
1328
MAX34451State *s = MAX34451(obj);
1329
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
1330
index XXXXXXX..XXXXXXX 100644
1331
--- a/hw/ssi/npcm7xx_fiu.c
1332
+++ b/hw/ssi/npcm7xx_fiu.c
1333
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_enter_reset(Object *obj, ResetType type)
1334
s->regs[NPCM7XX_FIU_CFG] = 0x0000000b;
1335
}
1336
1337
-static void npcm7xx_fiu_hold_reset(Object *obj)
1338
+static void npcm7xx_fiu_hold_reset(Object *obj, ResetType type)
1339
{
1340
NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
1341
int i;
1342
diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
1343
index XXXXXXX..XXXXXXX 100644
1344
--- a/hw/timer/etraxfs_timer.c
1345
+++ b/hw/timer/etraxfs_timer.c
1346
@@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
1347
t->rw_intr_mask = 0;
1348
}
1349
1350
-static void etraxfs_timer_reset_hold(Object *obj)
1351
+static void etraxfs_timer_reset_hold(Object *obj, ResetType type)
1352
{
1353
ETRAXTimerState *t = ETRAX_TIMER(obj);
1354
1355
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
1356
index XXXXXXX..XXXXXXX 100644
1357
--- a/hw/timer/npcm7xx_timer.c
1358
+++ b/hw/timer/npcm7xx_timer.c
1359
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_expired(void *opaque)
1360
}
1361
}
1362
1363
-static void npcm7xx_timer_hold_reset(Object *obj)
1364
+static void npcm7xx_timer_hold_reset(Object *obj, ResetType type)
1365
{
1366
NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
1367
int i;
1368
diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c
1369
index XXXXXXX..XXXXXXX 100644
1370
--- a/hw/usb/hcd-dwc2.c
1371
+++ b/hw/usb/hcd-dwc2.c
1372
@@ -XXX,XX +XXX,XX @@ static void dwc2_reset_enter(Object *obj, ResetType type)
1373
}
1374
}
1375
1376
-static void dwc2_reset_hold(Object *obj)
1377
+static void dwc2_reset_hold(Object *obj, ResetType type)
1378
{
1379
DWC2Class *c = DWC2_USB_GET_CLASS(obj);
1380
DWC2State *s = DWC2_USB(obj);
1381
@@ -XXX,XX +XXX,XX @@ static void dwc2_reset_hold(Object *obj)
1382
trace_usb_dwc2_reset_hold();
1383
1384
if (c->parent_phases.hold) {
1385
- c->parent_phases.hold(obj);
1386
+ c->parent_phases.hold(obj, type);
1387
}
1388
1389
dwc2_update_irq(s);
1390
}
1391
1392
-static void dwc2_reset_exit(Object *obj)
1393
+static void dwc2_reset_exit(Object *obj, ResetType type)
1394
{
1395
DWC2Class *c = DWC2_USB_GET_CLASS(obj);
1396
DWC2State *s = DWC2_USB(obj);
1397
@@ -XXX,XX +XXX,XX @@ static void dwc2_reset_exit(Object *obj)
1398
trace_usb_dwc2_reset_exit();
1399
1400
if (c->parent_phases.exit) {
1401
- c->parent_phases.exit(obj);
1402
+ c->parent_phases.exit(obj, type);
1403
}
1404
1405
s->hprt0 = HPRT0_PWR;
1406
diff --git a/hw/usb/xlnx-versal-usb2-ctrl-regs.c b/hw/usb/xlnx-versal-usb2-ctrl-regs.c
1407
index XXXXXXX..XXXXXXX 100644
1408
--- a/hw/usb/xlnx-versal-usb2-ctrl-regs.c
1409
+++ b/hw/usb/xlnx-versal-usb2-ctrl-regs.c
1410
@@ -XXX,XX +XXX,XX @@ static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type)
1411
}
1412
}
1413
1414
-static void usb2_ctrl_regs_reset_hold(Object *obj)
1415
+static void usb2_ctrl_regs_reset_hold(Object *obj, ResetType type)
1416
{
1417
VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
1418
1419
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
1420
index XXXXXXX..XXXXXXX 100644
1421
--- a/hw/virtio/virtio-pci.c
1422
+++ b/hw/virtio/virtio-pci.c
1423
@@ -XXX,XX +XXX,XX @@ static void virtio_pci_reset(DeviceState *qdev)
1424
}
1425
}
1426
1427
-static void virtio_pci_bus_reset_hold(Object *obj)
1428
+static void virtio_pci_bus_reset_hold(Object *obj, ResetType type)
1429
{
1430
PCIDevice *dev = PCI_DEVICE(obj);
1431
DeviceState *qdev = DEVICE(obj);
1432
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
1433
index XXXXXXX..XXXXXXX 100644
1434
--- a/target/arm/cpu.c
1435
+++ b/target/arm/cpu.c
1436
@@ -XXX,XX +XXX,XX @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
1437
assert(oldvalue == newvalue);
1438
}
1439
1440
-static void arm_cpu_reset_hold(Object *obj)
1441
+static void arm_cpu_reset_hold(Object *obj, ResetType type)
1442
{
1443
CPUState *cs = CPU(obj);
1444
ARMCPU *cpu = ARM_CPU(cs);
1445
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
1446
CPUARMState *env = &cpu->env;
1447
1448
if (acc->parent_phases.hold) {
1449
- acc->parent_phases.hold(obj);
1450
+ acc->parent_phases.hold(obj, type);
1451
}
1452
1453
memset(env, 0, offsetof(CPUARMState, end_reset_fields));
1454
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
1455
index XXXXXXX..XXXXXXX 100644
1456
--- a/target/avr/cpu.c
1457
+++ b/target/avr/cpu.c
1458
@@ -XXX,XX +XXX,XX @@ static void avr_restore_state_to_opc(CPUState *cs,
1459
cpu_env(cs)->pc_w = data[0];
1460
}
1461
1462
-static void avr_cpu_reset_hold(Object *obj)
1463
+static void avr_cpu_reset_hold(Object *obj, ResetType type)
1464
{
1465
CPUState *cs = CPU(obj);
1466
AVRCPU *cpu = AVR_CPU(cs);
1467
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_reset_hold(Object *obj)
1468
CPUAVRState *env = &cpu->env;
1469
1470
if (mcc->parent_phases.hold) {
1471
- mcc->parent_phases.hold(obj);
1472
+ mcc->parent_phases.hold(obj, type);
1473
}
1474
1475
env->pc_w = 0;
1476
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
1477
index XXXXXXX..XXXXXXX 100644
1478
--- a/target/cris/cpu.c
1479
+++ b/target/cris/cpu.c
1480
@@ -XXX,XX +XXX,XX @@ static int cris_cpu_mmu_index(CPUState *cs, bool ifetch)
1481
return !!(cpu_env(cs)->pregs[PR_CCS] & U_FLAG);
1482
}
1483
1484
-static void cris_cpu_reset_hold(Object *obj)
1485
+static void cris_cpu_reset_hold(Object *obj, ResetType type)
1486
{
1487
CPUState *cs = CPU(obj);
1488
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
1489
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_reset_hold(Object *obj)
1490
uint32_t vr;
1491
1492
if (ccc->parent_phases.hold) {
1493
- ccc->parent_phases.hold(obj);
1494
+ ccc->parent_phases.hold(obj, type);
1495
}
1496
1497
vr = env->pregs[PR_VR];
1498
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
1499
index XXXXXXX..XXXXXXX 100644
1500
--- a/target/hexagon/cpu.c
1501
+++ b/target/hexagon/cpu.c
1502
@@ -XXX,XX +XXX,XX @@ static void hexagon_restore_state_to_opc(CPUState *cs,
1503
cpu_env(cs)->gpr[HEX_REG_PC] = data[0];
1504
}
1505
1506
-static void hexagon_cpu_reset_hold(Object *obj)
1507
+static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
1508
{
1509
CPUState *cs = CPU(obj);
1510
HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj);
1511
CPUHexagonState *env = cpu_env(cs);
1512
1513
if (mcc->parent_phases.hold) {
1514
- mcc->parent_phases.hold(obj);
1515
+ mcc->parent_phases.hold(obj, type);
1516
}
1517
1518
set_default_nan_mode(1, &env->fp_status);
1519
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
1520
index XXXXXXX..XXXXXXX 100644
1521
--- a/target/i386/cpu.c
1522
+++ b/target/i386/cpu.c
1523
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
1524
#endif
1525
}
1526
1527
-static void x86_cpu_reset_hold(Object *obj)
1528
+static void x86_cpu_reset_hold(Object *obj, ResetType type)
1529
{
1530
CPUState *cs = CPU(obj);
1531
X86CPU *cpu = X86_CPU(cs);
1532
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_reset_hold(Object *obj)
1533
int i;
1534
1535
if (xcc->parent_phases.hold) {
1536
- xcc->parent_phases.hold(obj);
1537
+ xcc->parent_phases.hold(obj, type);
1538
}
1539
1540
memset(env, 0, offsetof(CPUX86State, end_reset_fields));
1541
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
1542
index XXXXXXX..XXXXXXX 100644
1543
--- a/target/loongarch/cpu.c
1544
+++ b/target/loongarch/cpu.c
1545
@@ -XXX,XX +XXX,XX @@ static void loongarch_max_initfn(Object *obj)
1546
loongarch_la464_initfn(obj);
1547
}
1548
1549
-static void loongarch_cpu_reset_hold(Object *obj)
1550
+static void loongarch_cpu_reset_hold(Object *obj, ResetType type)
1551
{
1552
CPUState *cs = CPU(obj);
1553
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(obj);
1554
CPULoongArchState *env = cpu_env(cs);
1555
1556
if (lacc->parent_phases.hold) {
1557
- lacc->parent_phases.hold(obj);
1558
+ lacc->parent_phases.hold(obj, type);
1559
}
1560
1561
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
1562
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
1563
index XXXXXXX..XXXXXXX 100644
1564
--- a/target/m68k/cpu.c
1565
+++ b/target/m68k/cpu.c
1566
@@ -XXX,XX +XXX,XX @@ static void m68k_unset_feature(CPUM68KState *env, int feature)
1567
env->features &= ~BIT_ULL(feature);
1568
}
1569
1570
-static void m68k_cpu_reset_hold(Object *obj)
1571
+static void m68k_cpu_reset_hold(Object *obj, ResetType type)
1572
{
1573
CPUState *cs = CPU(obj);
1574
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
1575
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj)
1576
int i;
1577
1578
if (mcc->parent_phases.hold) {
1579
- mcc->parent_phases.hold(obj);
1580
+ mcc->parent_phases.hold(obj, type);
1581
}
1582
1583
memset(env, 0, offsetof(CPUM68KState, end_reset_fields));
1584
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
1585
index XXXXXXX..XXXXXXX 100644
1586
--- a/target/microblaze/cpu.c
1587
+++ b/target/microblaze/cpu.c
1588
@@ -XXX,XX +XXX,XX @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
1589
}
1590
#endif
1591
1592
-static void mb_cpu_reset_hold(Object *obj)
1593
+static void mb_cpu_reset_hold(Object *obj, ResetType type)
1594
{
1595
CPUState *cs = CPU(obj);
1596
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
1597
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj)
1598
CPUMBState *env = &cpu->env;
1599
1600
if (mcc->parent_phases.hold) {
1601
- mcc->parent_phases.hold(obj);
1602
+ mcc->parent_phases.hold(obj, type);
1603
}
1604
1605
memset(env, 0, offsetof(CPUMBState, end_reset_fields));
1606
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
1607
index XXXXXXX..XXXXXXX 100644
1608
--- a/target/mips/cpu.c
1609
+++ b/target/mips/cpu.c
1610
@@ -XXX,XX +XXX,XX @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc)
1611
1612
#include "cpu-defs.c.inc"
1613
1614
-static void mips_cpu_reset_hold(Object *obj)
1615
+static void mips_cpu_reset_hold(Object *obj, ResetType type)
1616
{
1617
CPUState *cs = CPU(obj);
1618
MIPSCPU *cpu = MIPS_CPU(cs);
1619
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_reset_hold(Object *obj)
1620
CPUMIPSState *env = &cpu->env;
1621
1622
if (mcc->parent_phases.hold) {
1623
- mcc->parent_phases.hold(obj);
1624
+ mcc->parent_phases.hold(obj, type);
1625
}
1626
1627
memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
1628
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
1629
index XXXXXXX..XXXXXXX 100644
1630
--- a/target/openrisc/cpu.c
1631
+++ b/target/openrisc/cpu.c
1632
@@ -XXX,XX +XXX,XX @@ static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
1633
info->print_insn = print_insn_or1k;
1634
}
1635
1636
-static void openrisc_cpu_reset_hold(Object *obj)
1637
+static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
1638
{
1639
CPUState *cs = CPU(obj);
1640
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
1641
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj);
1642
1643
if (occ->parent_phases.hold) {
1644
- occ->parent_phases.hold(obj);
1645
+ occ->parent_phases.hold(obj, type);
1646
}
1647
1648
memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
1649
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
1650
index XXXXXXX..XXXXXXX 100644
1651
--- a/target/ppc/cpu_init.c
1652
+++ b/target/ppc/cpu_init.c
1653
@@ -XXX,XX +XXX,XX @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
1654
return ppc_env_mmu_index(cpu_env(cs), ifetch);
1655
}
1656
1657
-static void ppc_cpu_reset_hold(Object *obj)
1658
+static void ppc_cpu_reset_hold(Object *obj, ResetType type)
1659
{
1660
CPUState *cs = CPU(obj);
1661
PowerPCCPU *cpu = POWERPC_CPU(cs);
1662
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj)
1663
int i;
1664
1665
if (pcc->parent_phases.hold) {
1666
- pcc->parent_phases.hold(obj);
1667
+ pcc->parent_phases.hold(obj, type);
1668
}
1669
1670
msr = (target_ulong)0;
1671
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
1672
index XXXXXXX..XXXXXXX 100644
1673
--- a/target/riscv/cpu.c
1674
+++ b/target/riscv/cpu.c
1675
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
1676
return riscv_env_mmu_index(cpu_env(cs), ifetch);
1677
}
1678
1679
-static void riscv_cpu_reset_hold(Object *obj)
1680
+static void riscv_cpu_reset_hold(Object *obj, ResetType type)
1681
{
1682
#ifndef CONFIG_USER_ONLY
1683
uint8_t iprio;
1684
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj)
1685
CPURISCVState *env = &cpu->env;
1686
1687
if (mcc->parent_phases.hold) {
1688
- mcc->parent_phases.hold(obj);
1689
+ mcc->parent_phases.hold(obj, type);
1690
}
1691
#ifndef CONFIG_USER_ONLY
1692
env->misa_mxl = mcc->misa_mxl_max;
1693
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
1694
index XXXXXXX..XXXXXXX 100644
1695
--- a/target/rx/cpu.c
1696
+++ b/target/rx/cpu.c
1697
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc)
1698
return 0;
1699
}
1700
1701
-static void rx_cpu_reset_hold(Object *obj)
1702
+static void rx_cpu_reset_hold(Object *obj, ResetType type)
1703
{
1704
CPUState *cs = CPU(obj);
1705
RXCPUClass *rcc = RX_CPU_GET_CLASS(obj);
1706
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj)
1707
uint32_t *resetvec;
1708
1709
if (rcc->parent_phases.hold) {
1710
- rcc->parent_phases.hold(obj);
1711
+ rcc->parent_phases.hold(obj, type);
1712
}
1713
1714
memset(env, 0, offsetof(CPURXState, end_reset_fields));
1715
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
1716
index XXXXXXX..XXXXXXX 100644
1717
--- a/target/sh4/cpu.c
1718
+++ b/target/sh4/cpu.c
1719
@@ -XXX,XX +XXX,XX @@ static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
1720
}
1721
}
1722
1723
-static void superh_cpu_reset_hold(Object *obj)
1724
+static void superh_cpu_reset_hold(Object *obj, ResetType type)
1725
{
1726
CPUState *cs = CPU(obj);
1727
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj);
1728
CPUSH4State *env = cpu_env(cs);
1729
1730
if (scc->parent_phases.hold) {
1731
- scc->parent_phases.hold(obj);
1732
+ scc->parent_phases.hold(obj, type);
1733
}
1734
1735
memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
1736
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
1737
index XXXXXXX..XXXXXXX 100644
1738
--- a/target/sparc/cpu.c
1739
+++ b/target/sparc/cpu.c
1740
@@ -XXX,XX +XXX,XX @@
1741
1742
//#define DEBUG_FEATURES
1743
1744
-static void sparc_cpu_reset_hold(Object *obj)
1745
+static void sparc_cpu_reset_hold(Object *obj, ResetType type)
1746
{
1747
CPUState *cs = CPU(obj);
1748
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
1749
CPUSPARCState *env = cpu_env(cs);
1750
1751
if (scc->parent_phases.hold) {
1752
- scc->parent_phases.hold(obj);
1753
+ scc->parent_phases.hold(obj, type);
1754
}
1755
1756
memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
1757
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
1758
index XXXXXXX..XXXXXXX 100644
1759
--- a/target/tricore/cpu.c
1760
+++ b/target/tricore/cpu.c
1761
@@ -XXX,XX +XXX,XX @@ static void tricore_restore_state_to_opc(CPUState *cs,
1762
cpu_env(cs)->PC = data[0];
1763
}
1764
1765
-static void tricore_cpu_reset_hold(Object *obj)
1766
+static void tricore_cpu_reset_hold(Object *obj, ResetType type)
1767
{
1768
CPUState *cs = CPU(obj);
1769
TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(obj);
1770
1771
if (tcc->parent_phases.hold) {
1772
- tcc->parent_phases.hold(obj);
1773
+ tcc->parent_phases.hold(obj, type);
1774
}
1775
1776
cpu_state_reset(cpu_env(cs));
1777
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
1778
index XXXXXXX..XXXXXXX 100644
1779
--- a/target/xtensa/cpu.c
1780
+++ b/target/xtensa/cpu.c
1781
@@ -XXX,XX +XXX,XX @@ bool xtensa_abi_call0(void)
1782
}
1783
#endif
1784
1785
-static void xtensa_cpu_reset_hold(Object *obj)
1786
+static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
1787
{
1788
CPUState *cs = CPU(obj);
1789
XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
1790
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj)
1791
XTENSA_OPTION_DFP_COPROCESSOR);
1792
1793
if (xcc->parent_phases.hold) {
1794
- xcc->parent_phases.hold(obj);
1795
+ xcc->parent_phases.hold(obj, type);
1796
}
1797
1798
env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
44
--
1799
--
45
2.20.1
1800
2.34.1
46
47
diff view generated by jsdifflib
1
In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error
1
Update the reset documentation's example code to match the new API
2
meant we were using the H4() address swizzler macro rather than the
2
for the hold and exit phase method APIs where they take a ResetType
3
H2() which is required for 2-byte data. This had no effect on
3
argument.
4
little-endian hosts but meant we put the result data into the
5
destination Dreg in the wrong order on big-endian hosts.
6
4
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20201028191712.4910-2-peter.maydell@linaro.org
8
Reviewed-by: Luc Michel <luc.michel@amd.com>
9
Message-id: 20240412160809.1260625-6-peter.maydell@linaro.org
11
---
10
---
12
target/arm/vec_helper.c | 8 ++++----
11
docs/devel/reset.rst | 8 ++++----
13
1 file changed, 4 insertions(+), 4 deletions(-)
12
1 file changed, 4 insertions(+), 4 deletions(-)
14
13
15
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
14
diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vec_helper.c
16
--- a/docs/devel/reset.rst
18
+++ b/target/arm/vec_helper.c
17
+++ b/docs/devel/reset.rst
19
@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)
18
@@ -XXX,XX +XXX,XX @@ in reset.
20
r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \
19
mydev->var = 0;
21
r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \
22
\
23
- d[H4(0)] = r0; \
24
- d[H4(1)] = r1; \
25
- d[H4(2)] = r2; \
26
- d[H4(3)] = r3; \
27
+ d[H2(0)] = r0; \
28
+ d[H2(1)] = r1; \
29
+ d[H2(2)] = r2; \
30
+ d[H2(3)] = r3; \
31
}
20
}
32
21
33
DO_NEON_PAIRWISE(neon_padd, add)
22
- static void mydev_reset_hold(Object *obj)
23
+ static void mydev_reset_hold(Object *obj, ResetType type)
24
{
25
MyDevClass *myclass = MYDEV_GET_CLASS(obj);
26
MyDevState *mydev = MYDEV(obj);
27
/* call parent class hold phase */
28
if (myclass->parent_phases.hold) {
29
- myclass->parent_phases.hold(obj);
30
+ myclass->parent_phases.hold(obj, type);
31
}
32
/* set an IO */
33
qemu_set_irq(mydev->irq, 1);
34
}
35
36
- static void mydev_reset_exit(Object *obj)
37
+ static void mydev_reset_exit(Object *obj, ResetType type)
38
{
39
MyDevClass *myclass = MYDEV_GET_CLASS(obj);
40
MyDevState *mydev = MYDEV(obj);
41
/* call parent class exit phase */
42
if (myclass->parent_phases.exit) {
43
- myclass->parent_phases.exit(obj);
44
+ myclass->parent_phases.exit(obj, type);
45
}
46
/* clear an IO */
47
qemu_set_irq(mydev->irq, 0);
34
--
48
--
35
2.20.1
49
2.34.1
36
50
37
51
diff view generated by jsdifflib
1
The helper functions for performing the udot/sdot operations against
1
Some devices and machines need to handle the reset before a vmsave
2
a scalar were not using an address-swizzling macro when converting
2
snapshot is loaded differently -- the main user is the handling of
3
the index of the scalar element into a pointer into the vm array.
3
RNG seed information, which does not want to put a new RNG seed into
4
This had no effect on little-endian hosts but meant we generated
4
a ROM blob when we are doing a snapshot load.
5
incorrect results on big-endian hosts.
6
5
7
For these insns, the index is indexing over group of 4 8-bit values,
6
Currently this kind of reset handling is supported only for:
8
so 32 bits per indexed entity, and H4() is therefore what we want.
7
* TYPE_MACHINE reset methods, which take a ShutdownCause argument
9
(For Neon the only possible input indexes are 0 and 1.)
8
* reset functions registered with qemu_register_reset_nosnapshotload
9
10
To allow a three-phase-reset device to also distinguish "snapshot
11
load" reset from the normal kind, add a new ResetType
12
RESET_TYPE_SNAPSHOT_LOAD. All our existing reset methods ignore
13
the reset type, so we don't need to update any device code.
14
15
Add the enum type, and make qemu_devices_reset() use the
16
right reset type for the ShutdownCause it is passed. This
17
allows us to get rid of the device_reset_reason global we
18
were using to implement qemu_register_reset_nosnapshotload().
10
19
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20201028191712.4910-3-peter.maydell@linaro.org
23
Reviewed-by: Luc Michel <luc.michel@amd.com>
24
Message-id: 20240412160809.1260625-7-peter.maydell@linaro.org
15
---
25
---
16
target/arm/vec_helper.c | 4 ++--
26
docs/devel/reset.rst | 17 ++++++++++++++---
17
1 file changed, 2 insertions(+), 2 deletions(-)
27
include/hw/resettable.h | 1 +
28
hw/core/reset.c | 15 ++++-----------
29
hw/core/resettable.c | 4 ----
30
4 files changed, 19 insertions(+), 18 deletions(-)
18
31
19
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
32
diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst
20
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/vec_helper.c
34
--- a/docs/devel/reset.rst
22
+++ b/target/arm/vec_helper.c
35
+++ b/docs/devel/reset.rst
23
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
36
@@ -XXX,XX +XXX,XX @@ instantly reset an object, without keeping it in reset state, just call
24
intptr_t index = simd_data(desc);
37
``resettable_reset()``. These functions take two parameters: a pointer to the
25
uint32_t *d = vd;
38
object to reset and a reset type.
26
int8_t *n = vn;
39
27
- int8_t *m_indexed = (int8_t *)vm + index * 4;
40
-Several types of reset will be supported. For now only cold reset is defined;
28
+ int8_t *m_indexed = (int8_t *)vm + H4(index) * 4;
41
-others may be added later. The Resettable interface handles reset types with an
29
42
-enum:
30
/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
43
+The Resettable interface handles reset types with an enum ``ResetType``:
31
* Otherwise opr_sz is a multiple of 16.
44
32
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
45
``RESET_TYPE_COLD``
33
intptr_t index = simd_data(desc);
46
Cold reset is supported by every resettable object. In QEMU, it means we reset
34
uint32_t *d = vd;
47
@@ -XXX,XX +XXX,XX @@ enum:
35
uint8_t *n = vn;
48
from what is a real hardware cold reset. It differs from other resets (like
36
- uint8_t *m_indexed = (uint8_t *)vm + index * 4;
49
warm or bus resets) which may keep certain parts untouched.
37
+ uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4;
50
38
51
+``RESET_TYPE_SNAPSHOT_LOAD``
39
/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
52
+ This is called for a reset which is being done to put the system into a
40
* Otherwise opr_sz is a multiple of 16.
53
+ clean state prior to loading a snapshot. (This corresponds to a reset
54
+ with ``SHUTDOWN_CAUSE_SNAPSHOT_LOAD``.) Almost all devices should treat
55
+ this the same as ``RESET_TYPE_COLD``. The main exception is devices which
56
+ have some non-deterministic state they want to reinitialize to a different
57
+ value on each cold reset, such as RNG seed information, and which they
58
+ must not reinitialize on a snapshot-load reset.
59
+
60
+Devices which implement reset methods must treat any unknown ``ResetType``
61
+as equivalent to ``RESET_TYPE_COLD``; this will reduce the amount of
62
+existing code we need to change if we add more types in future.
63
+
64
Calling ``resettable_reset()`` is equivalent to calling
65
``resettable_assert_reset()`` then ``resettable_release_reset()``. It is
66
possible to interleave multiple calls to these three functions. There may
67
diff --git a/include/hw/resettable.h b/include/hw/resettable.h
68
index XXXXXXX..XXXXXXX 100644
69
--- a/include/hw/resettable.h
70
+++ b/include/hw/resettable.h
71
@@ -XXX,XX +XXX,XX @@ typedef struct ResettableState ResettableState;
72
*/
73
typedef enum ResetType {
74
RESET_TYPE_COLD,
75
+ RESET_TYPE_SNAPSHOT_LOAD,
76
} ResetType;
77
78
/*
79
diff --git a/hw/core/reset.c b/hw/core/reset.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/core/reset.c
82
+++ b/hw/core/reset.c
83
@@ -XXX,XX +XXX,XX @@ static ResettableContainer *get_root_reset_container(void)
84
return root_reset_container;
85
}
86
87
-/*
88
- * Reason why the currently in-progress qemu_devices_reset() was called.
89
- * If we made at least SHUTDOWN_CAUSE_SNAPSHOT_LOAD have a corresponding
90
- * ResetType we could perhaps avoid the need for this global.
91
- */
92
-static ShutdownCause device_reset_reason;
93
-
94
/*
95
* This is an Object which implements Resettable simply to call the
96
* callback function in the hold phase.
97
@@ -XXX,XX +XXX,XX @@ static void legacy_reset_hold(Object *obj, ResetType type)
98
{
99
LegacyReset *lr = LEGACY_RESET(obj);
100
101
- if (device_reset_reason == SHUTDOWN_CAUSE_SNAPSHOT_LOAD &&
102
- lr->skip_on_snapshot_load) {
103
+ if (type == RESET_TYPE_SNAPSHOT_LOAD && lr->skip_on_snapshot_load) {
104
return;
105
}
106
lr->func(lr->opaque);
107
@@ -XXX,XX +XXX,XX @@ void qemu_unregister_resettable(Object *obj)
108
109
void qemu_devices_reset(ShutdownCause reason)
110
{
111
- device_reset_reason = reason;
112
+ ResetType type = (reason == SHUTDOWN_CAUSE_SNAPSHOT_LOAD) ?
113
+ RESET_TYPE_SNAPSHOT_LOAD : RESET_TYPE_COLD;
114
115
/* Reset the simulation */
116
- resettable_reset(OBJECT(get_root_reset_container()), RESET_TYPE_COLD);
117
+ resettable_reset(OBJECT(get_root_reset_container()), type);
118
}
119
diff --git a/hw/core/resettable.c b/hw/core/resettable.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/hw/core/resettable.c
122
+++ b/hw/core/resettable.c
123
@@ -XXX,XX +XXX,XX @@ void resettable_reset(Object *obj, ResetType type)
124
125
void resettable_assert_reset(Object *obj, ResetType type)
126
{
127
- /* TODO: change this assert when adding support for other reset types */
128
- assert(type == RESET_TYPE_COLD);
129
trace_resettable_reset_assert_begin(obj, type);
130
assert(!enter_phase_in_progress);
131
132
@@ -XXX,XX +XXX,XX @@ void resettable_assert_reset(Object *obj, ResetType type)
133
134
void resettable_release_reset(Object *obj, ResetType type)
135
{
136
- /* TODO: change this assert when adding support for other reset types */
137
- assert(type == RESET_TYPE_COLD);
138
trace_resettable_reset_release_begin(obj, type);
139
assert(!enter_phase_in_progress);
140
41
--
141
--
42
2.20.1
142
2.34.1
43
143
44
144
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Arnaud Minier <arnaud.minier@telecom-paris.fr>
2
2
3
Model these off the aa64 read/write_vec_element functions.
3
Add the basic infrastructure (register read/write, type...)
4
Use it within translate-neon.c.inc. The new functions do
4
to implement the STM32L4x5 USART.
5
not allocate or free temps, so this rearranges the calling
6
code a bit.
7
5
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Also create different types for the USART, UART and LPUART
9
Message-id: 20201030022618.785675-6-richard.henderson@linaro.org
7
of the STM32L4x5 to deduplicate code and enable the
8
implementation of different behaviors depending on the type.
9
10
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
11
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20240329174402.60382-2-arnaud.minier@telecom-paris.fr
14
[PMM: update to new reset hold method signature;
15
fixed a few checkpatch nits]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
17
---
13
target/arm/translate.c | 26 ++++
18
MAINTAINERS | 1 +
14
target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------
19
include/hw/char/stm32l4x5_usart.h | 66 +++++
15
2 files changed, 183 insertions(+), 99 deletions(-)
20
hw/char/stm32l4x5_usart.c | 396 ++++++++++++++++++++++++++++++
21
hw/char/Kconfig | 3 +
22
hw/char/meson.build | 1 +
23
hw/char/trace-events | 4 +
24
6 files changed, 471 insertions(+)
25
create mode 100644 include/hw/char/stm32l4x5_usart.h
26
create mode 100644 hw/char/stm32l4x5_usart.c
16
27
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
28
diff --git a/MAINTAINERS b/MAINTAINERS
18
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate.c
30
--- a/MAINTAINERS
20
+++ b/target/arm/translate.c
31
+++ b/MAINTAINERS
21
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
32
@@ -XXX,XX +XXX,XX @@ M: Inès Varhol <ines.varhol@telecom-paris.fr>
22
tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
33
L: qemu-arm@nongnu.org
23
}
34
S: Maintained
24
35
F: hw/arm/stm32l4x5_soc.c
25
+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
36
+F: hw/char/stm32l4x5_usart.c
26
+{
37
F: hw/misc/stm32l4x5_exti.c
27
+ long off = neon_element_offset(reg, ele, size);
38
F: hw/misc/stm32l4x5_syscfg.c
28
+
39
F: hw/misc/stm32l4x5_rcc.c
29
+ switch (size) {
40
diff --git a/include/hw/char/stm32l4x5_usart.h b/include/hw/char/stm32l4x5_usart.h
30
+ case MO_32:
41
new file mode 100644
31
+ tcg_gen_ld_i32(dest, cpu_env, off);
42
index XXXXXXX..XXXXXXX
43
--- /dev/null
44
+++ b/include/hw/char/stm32l4x5_usart.h
45
@@ -XXX,XX +XXX,XX @@
46
+/*
47
+ * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter)
48
+ *
49
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
50
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
51
+ *
52
+ * SPDX-License-Identifier: GPL-2.0-or-later
53
+ *
54
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
55
+ * See the COPYING file in the top-level directory.
56
+ *
57
+ * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart
58
+ * by Alistair Francis.
59
+ * The reference used is the STMicroElectronics RM0351 Reference manual
60
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
61
+ */
62
+
63
+#ifndef HW_STM32L4X5_USART_H
64
+#define HW_STM32L4X5_USART_H
65
+
66
+#include "hw/sysbus.h"
67
+#include "chardev/char-fe.h"
68
+#include "qom/object.h"
69
+
70
+#define TYPE_STM32L4X5_USART_BASE "stm32l4x5-usart-base"
71
+#define TYPE_STM32L4X5_USART "stm32l4x5-usart"
72
+#define TYPE_STM32L4X5_UART "stm32l4x5-uart"
73
+#define TYPE_STM32L4X5_LPUART "stm32l4x5-lpuart"
74
+OBJECT_DECLARE_TYPE(Stm32l4x5UsartBaseState, Stm32l4x5UsartBaseClass,
75
+ STM32L4X5_USART_BASE)
76
+
77
+typedef enum {
78
+ STM32L4x5_USART,
79
+ STM32L4x5_UART,
80
+ STM32L4x5_LPUART,
81
+} Stm32l4x5UsartType;
82
+
83
+struct Stm32l4x5UsartBaseState {
84
+ SysBusDevice parent_obj;
85
+
86
+ MemoryRegion mmio;
87
+
88
+ uint32_t cr1;
89
+ uint32_t cr2;
90
+ uint32_t cr3;
91
+ uint32_t brr;
92
+ uint32_t gtpr;
93
+ uint32_t rtor;
94
+ /* rqr is write-only */
95
+ uint32_t isr;
96
+ /* icr is a clear register */
97
+ uint32_t rdr;
98
+ uint32_t tdr;
99
+
100
+ Clock *clk;
101
+ CharBackend chr;
102
+ qemu_irq irq;
103
+};
104
+
105
+struct Stm32l4x5UsartBaseClass {
106
+ SysBusDeviceClass parent_class;
107
+
108
+ Stm32l4x5UsartType type;
109
+};
110
+
111
+#endif /* HW_STM32L4X5_USART_H */
112
diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
113
new file mode 100644
114
index XXXXXXX..XXXXXXX
115
--- /dev/null
116
+++ b/hw/char/stm32l4x5_usart.c
117
@@ -XXX,XX +XXX,XX @@
118
+/*
119
+ * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter)
120
+ *
121
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
122
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
123
+ *
124
+ * SPDX-License-Identifier: GPL-2.0-or-later
125
+ *
126
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
127
+ * See the COPYING file in the top-level directory.
128
+ *
129
+ * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart
130
+ * by Alistair Francis.
131
+ * The reference used is the STMicroElectronics RM0351 Reference manual
132
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
133
+ */
134
+
135
+#include "qemu/osdep.h"
136
+#include "qemu/log.h"
137
+#include "qemu/module.h"
138
+#include "qapi/error.h"
139
+#include "chardev/char-fe.h"
140
+#include "chardev/char-serial.h"
141
+#include "migration/vmstate.h"
142
+#include "hw/char/stm32l4x5_usart.h"
143
+#include "hw/clock.h"
144
+#include "hw/irq.h"
145
+#include "hw/qdev-clock.h"
146
+#include "hw/qdev-properties.h"
147
+#include "hw/qdev-properties-system.h"
148
+#include "hw/registerfields.h"
149
+#include "trace.h"
150
+
151
+
152
+REG32(CR1, 0x00)
153
+ FIELD(CR1, M1, 28, 1) /* Word length (part 2, see M0) */
154
+ FIELD(CR1, EOBIE, 27, 1) /* End of Block interrupt enable */
155
+ FIELD(CR1, RTOIE, 26, 1) /* Receiver timeout interrupt enable */
156
+ FIELD(CR1, DEAT, 21, 5) /* Driver Enable assertion time */
157
+ FIELD(CR1, DEDT, 16, 5) /* Driver Enable de-assertion time */
158
+ FIELD(CR1, OVER8, 15, 1) /* Oversampling mode */
159
+ FIELD(CR1, CMIE, 14, 1) /* Character match interrupt enable */
160
+ FIELD(CR1, MME, 13, 1) /* Mute mode enable */
161
+ FIELD(CR1, M0, 12, 1) /* Word length (part 1, see M1) */
162
+ FIELD(CR1, WAKE, 11, 1) /* Receiver wakeup method */
163
+ FIELD(CR1, PCE, 10, 1) /* Parity control enable */
164
+ FIELD(CR1, PS, 9, 1) /* Parity selection */
165
+ FIELD(CR1, PEIE, 8, 1) /* PE interrupt enable */
166
+ FIELD(CR1, TXEIE, 7, 1) /* TXE interrupt enable */
167
+ FIELD(CR1, TCIE, 6, 1) /* Transmission complete interrupt enable */
168
+ FIELD(CR1, RXNEIE, 5, 1) /* RXNE interrupt enable */
169
+ FIELD(CR1, IDLEIE, 4, 1) /* IDLE interrupt enable */
170
+ FIELD(CR1, TE, 3, 1) /* Transmitter enable */
171
+ FIELD(CR1, RE, 2, 1) /* Receiver enable */
172
+ FIELD(CR1, UESM, 1, 1) /* USART enable in Stop mode */
173
+ FIELD(CR1, UE, 0, 1) /* USART enable */
174
+REG32(CR2, 0x04)
175
+ FIELD(CR2, ADD_1, 28, 4) /* ADD[7:4] */
176
+ FIELD(CR2, ADD_0, 24, 1) /* ADD[3:0] */
177
+ FIELD(CR2, RTOEN, 23, 1) /* Receiver timeout enable */
178
+ FIELD(CR2, ABRMOD, 21, 2) /* Auto baud rate mode */
179
+ FIELD(CR2, ABREN, 20, 1) /* Auto baud rate enable */
180
+ FIELD(CR2, MSBFIRST, 19, 1) /* Most significant bit first */
181
+ FIELD(CR2, DATAINV, 18, 1) /* Binary data inversion */
182
+ FIELD(CR2, TXINV, 17, 1) /* TX pin active level inversion */
183
+ FIELD(CR2, RXINV, 16, 1) /* RX pin active level inversion */
184
+ FIELD(CR2, SWAP, 15, 1) /* Swap RX/TX pins */
185
+ FIELD(CR2, LINEN, 14, 1) /* LIN mode enable */
186
+ FIELD(CR2, STOP, 12, 2) /* STOP bits */
187
+ FIELD(CR2, CLKEN, 11, 1) /* Clock enable */
188
+ FIELD(CR2, CPOL, 10, 1) /* Clock polarity */
189
+ FIELD(CR2, CPHA, 9, 1) /* Clock phase */
190
+ FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */
191
+ FIELD(CR2, LBDIE, 6, 1) /* LIN break detection interrupt enable */
192
+ FIELD(CR2, LBDL, 5, 1) /* LIN break detection length */
193
+ FIELD(CR2, ADDM7, 4, 1) /* 7-bit / 4-bit Address Detection */
194
+
195
+REG32(CR3, 0x08)
196
+ /* TCBGTIE only on STM32L496xx/4A6xx devices */
197
+ FIELD(CR3, UCESM, 23, 1) /* USART Clock Enable in Stop Mode */
198
+ FIELD(CR3, WUFIE, 22, 1) /* Wakeup from Stop mode interrupt enable */
199
+ FIELD(CR3, WUS, 20, 2) /* Wakeup from Stop mode interrupt flag selection */
200
+ FIELD(CR3, SCARCNT, 17, 3) /* Smartcard auto-retry count */
201
+ FIELD(CR3, DEP, 15, 1) /* Driver enable polarity selection */
202
+ FIELD(CR3, DEM, 14, 1) /* Driver enable mode */
203
+ FIELD(CR3, DDRE, 13, 1) /* DMA Disable on Reception Error */
204
+ FIELD(CR3, OVRDIS, 12, 1) /* Overrun Disable */
205
+ FIELD(CR3, ONEBIT, 11, 1) /* One sample bit method enable */
206
+ FIELD(CR3, CTSIE, 10, 1) /* CTS interrupt enable */
207
+ FIELD(CR3, CTSE, 9, 1) /* CTS enable */
208
+ FIELD(CR3, RTSE, 8, 1) /* RTS enable */
209
+ FIELD(CR3, DMAT, 7, 1) /* DMA enable transmitter */
210
+ FIELD(CR3, DMAR, 6, 1) /* DMA enable receiver */
211
+ FIELD(CR3, SCEN, 5, 1) /* Smartcard mode enable */
212
+ FIELD(CR3, NACK, 4, 1) /* Smartcard NACK enable */
213
+ FIELD(CR3, HDSEL, 3, 1) /* Half-duplex selection */
214
+ FIELD(CR3, IRLP, 2, 1) /* IrDA low-power */
215
+ FIELD(CR3, IREN, 1, 1) /* IrDA mode enable */
216
+ FIELD(CR3, EIE, 0, 1) /* Error interrupt enable */
217
+REG32(BRR, 0x0C)
218
+ FIELD(BRR, BRR, 0, 16)
219
+REG32(GTPR, 0x10)
220
+ FIELD(GTPR, GT, 8, 8) /* Guard time value */
221
+ FIELD(GTPR, PSC, 0, 8) /* Prescaler value */
222
+REG32(RTOR, 0x14)
223
+ FIELD(RTOR, BLEN, 24, 8) /* Block Length */
224
+ FIELD(RTOR, RTO, 0, 24) /* Receiver timeout value */
225
+REG32(RQR, 0x18)
226
+ FIELD(RQR, TXFRQ, 4, 1) /* Transmit data flush request */
227
+ FIELD(RQR, RXFRQ, 3, 1) /* Receive data flush request */
228
+ FIELD(RQR, MMRQ, 2, 1) /* Mute mode request */
229
+ FIELD(RQR, SBKRQ, 1, 1) /* Send break request */
230
+ FIELD(RQR, ABBRRQ, 0, 1) /* Auto baud rate request */
231
+REG32(ISR, 0x1C)
232
+ /* TCBGT only for STM32L475xx/476xx/486xx devices */
233
+ FIELD(ISR, REACK, 22, 1) /* Receive enable acknowledge flag */
234
+ FIELD(ISR, TEACK, 21, 1) /* Transmit enable acknowledge flag */
235
+ FIELD(ISR, WUF, 20, 1) /* Wakeup from Stop mode flag */
236
+ FIELD(ISR, RWU, 19, 1) /* Receiver wakeup from Mute mode */
237
+ FIELD(ISR, SBKF, 18, 1) /* Send break flag */
238
+ FIELD(ISR, CMF, 17, 1) /* Character match flag */
239
+ FIELD(ISR, BUSY, 16, 1) /* Busy flag */
240
+ FIELD(ISR, ABRF, 15, 1) /* Auto Baud rate flag */
241
+ FIELD(ISR, ABRE, 14, 1) /* Auto Baud rate error */
242
+ FIELD(ISR, EOBF, 12, 1) /* End of block flag */
243
+ FIELD(ISR, RTOF, 11, 1) /* Receiver timeout */
244
+ FIELD(ISR, CTS, 10, 1) /* CTS flag */
245
+ FIELD(ISR, CTSIF, 9, 1) /* CTS interrupt flag */
246
+ FIELD(ISR, LBDF, 8, 1) /* LIN break detection flag */
247
+ FIELD(ISR, TXE, 7, 1) /* Transmit data register empty */
248
+ FIELD(ISR, TC, 6, 1) /* Transmission complete */
249
+ FIELD(ISR, RXNE, 5, 1) /* Read data register not empty */
250
+ FIELD(ISR, IDLE, 4, 1) /* Idle line detected */
251
+ FIELD(ISR, ORE, 3, 1) /* Overrun error */
252
+ FIELD(ISR, NF, 2, 1) /* START bit Noise detection flag */
253
+ FIELD(ISR, FE, 1, 1) /* Framing Error */
254
+ FIELD(ISR, PE, 0, 1) /* Parity Error */
255
+REG32(ICR, 0x20)
256
+ FIELD(ICR, WUCF, 20, 1) /* Wakeup from Stop mode clear flag */
257
+ FIELD(ICR, CMCF, 17, 1) /* Character match clear flag */
258
+ FIELD(ICR, EOBCF, 12, 1) /* End of block clear flag */
259
+ FIELD(ICR, RTOCF, 11, 1) /* Receiver timeout clear flag */
260
+ FIELD(ICR, CTSCF, 9, 1) /* CTS clear flag */
261
+ FIELD(ICR, LBDCF, 8, 1) /* LIN break detection clear flag */
262
+ /* TCBGTCF only on STM32L496xx/4A6xx devices */
263
+ FIELD(ICR, TCCF, 6, 1) /* Transmission complete clear flag */
264
+ FIELD(ICR, IDLECF, 4, 1) /* Idle line detected clear flag */
265
+ FIELD(ICR, ORECF, 3, 1) /* Overrun error clear flag */
266
+ FIELD(ICR, NCF, 2, 1) /* Noise detected clear flag */
267
+ FIELD(ICR, FECF, 1, 1) /* Framing error clear flag */
268
+ FIELD(ICR, PECF, 0, 1) /* Parity error clear flag */
269
+REG32(RDR, 0x24)
270
+ FIELD(RDR, RDR, 0, 9)
271
+REG32(TDR, 0x28)
272
+ FIELD(TDR, TDR, 0, 9)
273
+
274
+static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type)
275
+{
276
+ Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj);
277
+
278
+ s->cr1 = 0x00000000;
279
+ s->cr2 = 0x00000000;
280
+ s->cr3 = 0x00000000;
281
+ s->brr = 0x00000000;
282
+ s->gtpr = 0x00000000;
283
+ s->rtor = 0x00000000;
284
+ s->isr = 0x020000C0;
285
+ s->rdr = 0x00000000;
286
+ s->tdr = 0x00000000;
287
+}
288
+
289
+static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr,
290
+ unsigned int size)
291
+{
292
+ Stm32l4x5UsartBaseState *s = opaque;
293
+ uint64_t retvalue = 0;
294
+
295
+ switch (addr) {
296
+ case A_CR1:
297
+ retvalue = s->cr1;
298
+ break;
299
+ case A_CR2:
300
+ retvalue = s->cr2;
301
+ break;
302
+ case A_CR3:
303
+ retvalue = s->cr3;
304
+ break;
305
+ case A_BRR:
306
+ retvalue = FIELD_EX32(s->brr, BRR, BRR);
307
+ break;
308
+ case A_GTPR:
309
+ retvalue = s->gtpr;
310
+ break;
311
+ case A_RTOR:
312
+ retvalue = s->rtor;
313
+ break;
314
+ case A_RQR:
315
+ /* RQR is a write only register */
316
+ retvalue = 0x00000000;
317
+ break;
318
+ case A_ISR:
319
+ retvalue = s->isr;
320
+ break;
321
+ case A_ICR:
322
+ /* ICR is a clear register */
323
+ retvalue = 0x00000000;
324
+ break;
325
+ case A_RDR:
326
+ retvalue = FIELD_EX32(s->rdr, RDR, RDR);
327
+ /* Reset RXNE flag */
328
+ s->isr &= ~R_ISR_RXNE_MASK;
329
+ break;
330
+ case A_TDR:
331
+ retvalue = FIELD_EX32(s->tdr, TDR, TDR);
32
+ break;
332
+ break;
33
+ default:
333
+ default:
34
+ g_assert_not_reached();
334
+ qemu_log_mask(LOG_GUEST_ERROR,
335
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
336
+ break;
35
+ }
337
+ }
36
+}
338
+
37
+
339
+ trace_stm32l4x5_usart_read(addr, retvalue);
38
+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
340
+
39
+{
341
+ return retvalue;
40
+ long off = neon_element_offset(reg, ele, size);
342
+}
41
+
343
+
42
+ switch (size) {
344
+static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
43
+ case MO_32:
345
+ uint64_t val64, unsigned int size)
44
+ tcg_gen_st_i32(src, cpu_env, off);
346
+{
45
+ break;
347
+ Stm32l4x5UsartBaseState *s = opaque;
348
+ const uint32_t value = val64;
349
+
350
+ trace_stm32l4x5_usart_write(addr, value);
351
+
352
+ switch (addr) {
353
+ case A_CR1:
354
+ s->cr1 = value;
355
+ return;
356
+ case A_CR2:
357
+ s->cr2 = value;
358
+ return;
359
+ case A_CR3:
360
+ s->cr3 = value;
361
+ return;
362
+ case A_BRR:
363
+ s->brr = value;
364
+ return;
365
+ case A_GTPR:
366
+ s->gtpr = value;
367
+ return;
368
+ case A_RTOR:
369
+ s->rtor = value;
370
+ return;
371
+ case A_RQR:
372
+ return;
373
+ case A_ISR:
374
+ qemu_log_mask(LOG_GUEST_ERROR,
375
+ "%s: ISR is read only !\n", __func__);
376
+ return;
377
+ case A_ICR:
378
+ /* Clear the status flags */
379
+ s->isr &= ~value;
380
+ return;
381
+ case A_RDR:
382
+ qemu_log_mask(LOG_GUEST_ERROR,
383
+ "%s: RDR is read only !\n", __func__);
384
+ return;
385
+ case A_TDR:
386
+ s->tdr = value;
387
+ return;
46
+ default:
388
+ default:
47
+ g_assert_not_reached();
389
+ qemu_log_mask(LOG_GUEST_ERROR,
390
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
48
+ }
391
+ }
49
+}
392
+}
50
+
393
+
51
static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
394
+static const MemoryRegionOps stm32l4x5_usart_base_ops = {
52
{
395
+ .read = stm32l4x5_usart_base_read,
53
TCGv_ptr ret = tcg_temp_new_ptr();
396
+ .write = stm32l4x5_usart_base_write,
54
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
397
+ .endianness = DEVICE_NATIVE_ENDIAN,
398
+ .valid = {
399
+ .max_access_size = 4,
400
+ .min_access_size = 4,
401
+ .unaligned = false
402
+ },
403
+ .impl = {
404
+ .max_access_size = 4,
405
+ .min_access_size = 4,
406
+ .unaligned = false
407
+ },
408
+};
409
+
410
+static Property stm32l4x5_usart_base_properties[] = {
411
+ DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr),
412
+ DEFINE_PROP_END_OF_LIST(),
413
+};
414
+
415
+static void stm32l4x5_usart_base_init(Object *obj)
416
+{
417
+ Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj);
418
+
419
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
420
+
421
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_usart_base_ops, s,
422
+ TYPE_STM32L4X5_USART_BASE, 0x400);
423
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
424
+
425
+ s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
426
+}
427
+
428
+static const VMStateDescription vmstate_stm32l4x5_usart_base = {
429
+ .name = TYPE_STM32L4X5_USART_BASE,
430
+ .version_id = 1,
431
+ .minimum_version_id = 1,
432
+ .fields = (VMStateField[]) {
433
+ VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState),
434
+ VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState),
435
+ VMSTATE_UINT32(cr3, Stm32l4x5UsartBaseState),
436
+ VMSTATE_UINT32(brr, Stm32l4x5UsartBaseState),
437
+ VMSTATE_UINT32(gtpr, Stm32l4x5UsartBaseState),
438
+ VMSTATE_UINT32(rtor, Stm32l4x5UsartBaseState),
439
+ VMSTATE_UINT32(isr, Stm32l4x5UsartBaseState),
440
+ VMSTATE_UINT32(rdr, Stm32l4x5UsartBaseState),
441
+ VMSTATE_UINT32(tdr, Stm32l4x5UsartBaseState),
442
+ VMSTATE_CLOCK(clk, Stm32l4x5UsartBaseState),
443
+ VMSTATE_END_OF_LIST()
444
+ }
445
+};
446
+
447
+
448
+static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp)
449
+{
450
+ ERRP_GUARD();
451
+ Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(dev);
452
+ if (!clock_has_source(s->clk)) {
453
+ error_setg(errp, "USART clock must be wired up by SoC code");
454
+ return;
455
+ }
456
+}
457
+
458
+static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data)
459
+{
460
+ DeviceClass *dc = DEVICE_CLASS(klass);
461
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
462
+
463
+ rc->phases.hold = stm32l4x5_usart_base_reset_hold;
464
+ device_class_set_props(dc, stm32l4x5_usart_base_properties);
465
+ dc->realize = stm32l4x5_usart_base_realize;
466
+ dc->vmsd = &vmstate_stm32l4x5_usart_base;
467
+}
468
+
469
+static void stm32l4x5_usart_class_init(ObjectClass *oc, void *data)
470
+{
471
+ Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
472
+
473
+ subc->type = STM32L4x5_USART;
474
+}
475
+
476
+static void stm32l4x5_uart_class_init(ObjectClass *oc, void *data)
477
+{
478
+ Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
479
+
480
+ subc->type = STM32L4x5_UART;
481
+}
482
+
483
+static void stm32l4x5_lpuart_class_init(ObjectClass *oc, void *data)
484
+{
485
+ Stm32l4x5UsartBaseClass *subc = STM32L4X5_USART_BASE_CLASS(oc);
486
+
487
+ subc->type = STM32L4x5_LPUART;
488
+}
489
+
490
+static const TypeInfo stm32l4x5_usart_types[] = {
491
+ {
492
+ .name = TYPE_STM32L4X5_USART_BASE,
493
+ .parent = TYPE_SYS_BUS_DEVICE,
494
+ .instance_size = sizeof(Stm32l4x5UsartBaseState),
495
+ .instance_init = stm32l4x5_usart_base_init,
496
+ .class_init = stm32l4x5_usart_base_class_init,
497
+ .abstract = true,
498
+ }, {
499
+ .name = TYPE_STM32L4X5_USART,
500
+ .parent = TYPE_STM32L4X5_USART_BASE,
501
+ .class_init = stm32l4x5_usart_class_init,
502
+ }, {
503
+ .name = TYPE_STM32L4X5_UART,
504
+ .parent = TYPE_STM32L4X5_USART_BASE,
505
+ .class_init = stm32l4x5_uart_class_init,
506
+ }, {
507
+ .name = TYPE_STM32L4X5_LPUART,
508
+ .parent = TYPE_STM32L4X5_USART_BASE,
509
+ .class_init = stm32l4x5_lpuart_class_init,
510
+ }
511
+};
512
+
513
+DEFINE_TYPES(stm32l4x5_usart_types)
514
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
55
index XXXXXXX..XXXXXXX 100644
515
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/translate-neon.c.inc
516
--- a/hw/char/Kconfig
57
+++ b/target/arm/translate-neon.c.inc
517
+++ b/hw/char/Kconfig
58
@@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
518
@@ -XXX,XX +XXX,XX @@ config VIRTIO_SERIAL
59
* early. Since Q is 0 there are always just two passes, so instead
519
config STM32F2XX_USART
60
* of a complicated loop over each pass we just unroll.
520
bool
61
*/
521
62
- tmp = neon_load_reg(a->vn, 0);
522
+config STM32L4X5_USART
63
- tmp2 = neon_load_reg(a->vn, 1);
523
+ bool
64
+ tmp = tcg_temp_new_i32();
524
+
65
+ tmp2 = tcg_temp_new_i32();
525
config CMSDK_APB_UART
66
+ tmp3 = tcg_temp_new_i32();
526
bool
67
+
527
68
+ read_neon_element32(tmp, a->vn, 0, MO_32);
528
diff --git a/hw/char/meson.build b/hw/char/meson.build
69
+ read_neon_element32(tmp2, a->vn, 1, MO_32);
529
index XXXXXXX..XXXXXXX 100644
70
fn(tmp, tmp, tmp2);
530
--- a/hw/char/meson.build
71
- tcg_temp_free_i32(tmp2);
531
+++ b/hw/char/meson.build
72
532
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
73
- tmp3 = neon_load_reg(a->vm, 0);
533
system_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
74
- tmp2 = neon_load_reg(a->vm, 1);
534
system_ss.add(when: 'CONFIG_SH_SCI', if_true: files('sh_serial.c'))
75
+ read_neon_element32(tmp3, a->vm, 0, MO_32);
535
system_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
76
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
536
+system_ss.add(when: 'CONFIG_STM32L4X5_USART', if_true: files('stm32l4x5_usart.c'))
77
fn(tmp3, tmp3, tmp2);
537
system_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
78
- tcg_temp_free_i32(tmp2);
538
system_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
79
539
system_ss.add(when: 'CONFIG_GOLDFISH_TTY', if_true: files('goldfish_tty.c'))
80
- neon_store_reg(a->vd, 0, tmp);
540
diff --git a/hw/char/trace-events b/hw/char/trace-events
81
- neon_store_reg(a->vd, 1, tmp3);
541
index XXXXXXX..XXXXXXX 100644
82
+ write_neon_element32(tmp, a->vd, 0, MO_32);
542
--- a/hw/char/trace-events
83
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
543
+++ b/hw/char/trace-events
84
+
544
@@ -XXX,XX +XXX,XX @@ cadence_uart_baudrate(unsigned baudrate) "baudrate %u"
85
+ tcg_temp_free_i32(tmp);
545
sh_serial_read(char *id, unsigned size, uint64_t offs, uint64_t val) " %s size %d offs 0x%02" PRIx64 " -> 0x%02" PRIx64
86
+ tcg_temp_free_i32(tmp2);
546
sh_serial_write(char *id, unsigned size, uint64_t offs, uint64_t val) "%s size %d offs 0x%02" PRIx64 " <- 0x%02" PRIx64
87
+ tcg_temp_free_i32(tmp3);
547
88
return true;
548
+# stm32l4x5_usart.c
89
}
549
+stm32l4x5_usart_read(uint64_t addr, uint32_t data) "USART: Read <0x%" PRIx64 "> -> 0x%" PRIx32 ""
90
550
+stm32l4x5_usart_write(uint64_t addr, uint32_t data) "USART: Write <0x%" PRIx64 "> <- 0x%" PRIx32 ""
91
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
551
+
92
* 2-reg-and-shift operations, size < 3 case, where the
552
# xen_console.c
93
* helper needs to be passed cpu_env.
553
xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int port, unsigned int limit) "idx %u ring_ref %u port %u limit %u"
94
*/
554
xen_console_disconnect(unsigned int idx) "idx %u"
95
- TCGv_i32 constimm;
96
+ TCGv_i32 constimm, tmp;
97
int pass;
98
99
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
100
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
101
* by immediate using the variable shift operations.
102
*/
103
constimm = tcg_const_i32(dup_const(a->size, a->shift));
104
+ tmp = tcg_temp_new_i32();
105
106
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
107
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
108
+ read_neon_element32(tmp, a->vm, pass, MO_32);
109
fn(tmp, cpu_env, tmp, constimm);
110
- neon_store_reg(a->vd, pass, tmp);
111
+ write_neon_element32(tmp, a->vd, pass, MO_32);
112
}
113
+ tcg_temp_free_i32(tmp);
114
tcg_temp_free_i32(constimm);
115
return true;
116
}
117
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
118
constimm = tcg_const_i64(-a->shift);
119
rm1 = tcg_temp_new_i64();
120
rm2 = tcg_temp_new_i64();
121
+ rd = tcg_temp_new_i32();
122
123
/* Load both inputs first to avoid potential overwrite if rm == rd */
124
neon_load_reg64(rm1, a->vm);
125
neon_load_reg64(rm2, a->vm + 1);
126
127
shiftfn(rm1, rm1, constimm);
128
- rd = tcg_temp_new_i32();
129
narrowfn(rd, cpu_env, rm1);
130
- neon_store_reg(a->vd, 0, rd);
131
+ write_neon_element32(rd, a->vd, 0, MO_32);
132
133
shiftfn(rm2, rm2, constimm);
134
- rd = tcg_temp_new_i32();
135
narrowfn(rd, cpu_env, rm2);
136
- neon_store_reg(a->vd, 1, rd);
137
+ write_neon_element32(rd, a->vd, 1, MO_32);
138
139
+ tcg_temp_free_i32(rd);
140
tcg_temp_free_i64(rm1);
141
tcg_temp_free_i64(rm2);
142
tcg_temp_free_i64(constimm);
143
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
144
constimm = tcg_const_i32(imm);
145
146
/* Load all inputs first to avoid potential overwrite */
147
- rm1 = neon_load_reg(a->vm, 0);
148
- rm2 = neon_load_reg(a->vm, 1);
149
- rm3 = neon_load_reg(a->vm + 1, 0);
150
- rm4 = neon_load_reg(a->vm + 1, 1);
151
+ rm1 = tcg_temp_new_i32();
152
+ rm2 = tcg_temp_new_i32();
153
+ rm3 = tcg_temp_new_i32();
154
+ rm4 = tcg_temp_new_i32();
155
+ read_neon_element32(rm1, a->vm, 0, MO_32);
156
+ read_neon_element32(rm2, a->vm, 1, MO_32);
157
+ read_neon_element32(rm3, a->vm, 2, MO_32);
158
+ read_neon_element32(rm4, a->vm, 3, MO_32);
159
rtmp = tcg_temp_new_i64();
160
161
shiftfn(rm1, rm1, constimm);
162
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
163
tcg_temp_free_i32(rm2);
164
165
narrowfn(rm1, cpu_env, rtmp);
166
- neon_store_reg(a->vd, 0, rm1);
167
+ write_neon_element32(rm1, a->vd, 0, MO_32);
168
+ tcg_temp_free_i32(rm1);
169
170
shiftfn(rm3, rm3, constimm);
171
shiftfn(rm4, rm4, constimm);
172
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
173
174
narrowfn(rm3, cpu_env, rtmp);
175
tcg_temp_free_i64(rtmp);
176
- neon_store_reg(a->vd, 1, rm3);
177
+ write_neon_element32(rm3, a->vd, 1, MO_32);
178
+ tcg_temp_free_i32(rm3);
179
return true;
180
}
181
182
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
183
widen_mask = dup_const(a->size + 1, widen_mask);
184
}
185
186
- rm0 = neon_load_reg(a->vm, 0);
187
- rm1 = neon_load_reg(a->vm, 1);
188
+ rm0 = tcg_temp_new_i32();
189
+ rm1 = tcg_temp_new_i32();
190
+ read_neon_element32(rm0, a->vm, 0, MO_32);
191
+ read_neon_element32(rm1, a->vm, 1, MO_32);
192
tmp = tcg_temp_new_i64();
193
194
widenfn(tmp, rm0);
195
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
196
if (src1_wide) {
197
neon_load_reg64(rn0_64, a->vn);
198
} else {
199
- TCGv_i32 tmp = neon_load_reg(a->vn, 0);
200
+ TCGv_i32 tmp = tcg_temp_new_i32();
201
+ read_neon_element32(tmp, a->vn, 0, MO_32);
202
widenfn(rn0_64, tmp);
203
tcg_temp_free_i32(tmp);
204
}
205
- rm = neon_load_reg(a->vm, 0);
206
+ rm = tcg_temp_new_i32();
207
+ read_neon_element32(rm, a->vm, 0, MO_32);
208
209
widenfn(rm_64, rm);
210
tcg_temp_free_i32(rm);
211
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
212
if (src1_wide) {
213
neon_load_reg64(rn1_64, a->vn + 1);
214
} else {
215
- TCGv_i32 tmp = neon_load_reg(a->vn, 1);
216
+ TCGv_i32 tmp = tcg_temp_new_i32();
217
+ read_neon_element32(tmp, a->vn, 1, MO_32);
218
widenfn(rn1_64, tmp);
219
tcg_temp_free_i32(tmp);
220
}
221
- rm = neon_load_reg(a->vm, 1);
222
+ rm = tcg_temp_new_i32();
223
+ read_neon_element32(rm, a->vm, 1, MO_32);
224
225
neon_store_reg64(rn0_64, a->vd);
226
227
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
228
229
narrowfn(rd1, rn_64);
230
231
- neon_store_reg(a->vd, 0, rd0);
232
- neon_store_reg(a->vd, 1, rd1);
233
+ write_neon_element32(rd0, a->vd, 0, MO_32);
234
+ write_neon_element32(rd1, a->vd, 1, MO_32);
235
236
+ tcg_temp_free_i32(rd0);
237
+ tcg_temp_free_i32(rd1);
238
tcg_temp_free_i64(rn_64);
239
tcg_temp_free_i64(rm_64);
240
241
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
242
rd0 = tcg_temp_new_i64();
243
rd1 = tcg_temp_new_i64();
244
245
- rn = neon_load_reg(a->vn, 0);
246
- rm = neon_load_reg(a->vm, 0);
247
+ rn = tcg_temp_new_i32();
248
+ rm = tcg_temp_new_i32();
249
+ read_neon_element32(rn, a->vn, 0, MO_32);
250
+ read_neon_element32(rm, a->vm, 0, MO_32);
251
opfn(rd0, rn, rm);
252
- tcg_temp_free_i32(rn);
253
- tcg_temp_free_i32(rm);
254
255
- rn = neon_load_reg(a->vn, 1);
256
- rm = neon_load_reg(a->vm, 1);
257
+ read_neon_element32(rn, a->vn, 1, MO_32);
258
+ read_neon_element32(rm, a->vm, 1, MO_32);
259
opfn(rd1, rn, rm);
260
tcg_temp_free_i32(rn);
261
tcg_temp_free_i32(rm);
262
@@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var)
263
264
static inline TCGv_i32 neon_get_scalar(int size, int reg)
265
{
266
- TCGv_i32 tmp;
267
- if (size == 1) {
268
- tmp = neon_load_reg(reg & 7, reg >> 4);
269
+ TCGv_i32 tmp = tcg_temp_new_i32();
270
+ if (size == MO_16) {
271
+ read_neon_element32(tmp, reg & 7, reg >> 4, MO_32);
272
if (reg & 8) {
273
gen_neon_dup_high16(tmp);
274
} else {
275
gen_neon_dup_low16(tmp);
276
}
277
} else {
278
- tmp = neon_load_reg(reg & 15, reg >> 4);
279
+ read_neon_element32(tmp, reg & 15, reg >> 4, MO_32);
280
}
281
return tmp;
282
}
283
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
284
* perform an accumulation operation of that result into the
285
* destination.
286
*/
287
- TCGv_i32 scalar;
288
+ TCGv_i32 scalar, tmp;
289
int pass;
290
291
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
292
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
293
}
294
295
scalar = neon_get_scalar(a->size, a->vm);
296
+ tmp = tcg_temp_new_i32();
297
298
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
299
- TCGv_i32 tmp = neon_load_reg(a->vn, pass);
300
+ read_neon_element32(tmp, a->vn, pass, MO_32);
301
opfn(tmp, tmp, scalar);
302
if (accfn) {
303
- TCGv_i32 rd = neon_load_reg(a->vd, pass);
304
+ TCGv_i32 rd = tcg_temp_new_i32();
305
+ read_neon_element32(rd, a->vd, pass, MO_32);
306
accfn(tmp, rd, tmp);
307
tcg_temp_free_i32(rd);
308
}
309
- neon_store_reg(a->vd, pass, tmp);
310
+ write_neon_element32(tmp, a->vd, pass, MO_32);
311
}
312
+ tcg_temp_free_i32(tmp);
313
tcg_temp_free_i32(scalar);
314
return true;
315
}
316
@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
317
* performs a kind of fused op-then-accumulate using a helper
318
* function that takes all of rd, rn and the scalar at once.
319
*/
320
- TCGv_i32 scalar;
321
+ TCGv_i32 scalar, rn, rd;
322
int pass;
323
324
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
325
@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
326
}
327
328
scalar = neon_get_scalar(a->size, a->vm);
329
+ rn = tcg_temp_new_i32();
330
+ rd = tcg_temp_new_i32();
331
332
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
333
- TCGv_i32 rn = neon_load_reg(a->vn, pass);
334
- TCGv_i32 rd = neon_load_reg(a->vd, pass);
335
+ read_neon_element32(rn, a->vn, pass, MO_32);
336
+ read_neon_element32(rd, a->vd, pass, MO_32);
337
opfn(rd, cpu_env, rn, scalar, rd);
338
- tcg_temp_free_i32(rn);
339
- neon_store_reg(a->vd, pass, rd);
340
+ write_neon_element32(rd, a->vd, pass, MO_32);
341
}
342
+ tcg_temp_free_i32(rn);
343
+ tcg_temp_free_i32(rd);
344
tcg_temp_free_i32(scalar);
345
346
return true;
347
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
348
scalar = neon_get_scalar(a->size, a->vm);
349
350
/* Load all inputs before writing any outputs, in case of overlap */
351
- rn = neon_load_reg(a->vn, 0);
352
+ rn = tcg_temp_new_i32();
353
+ read_neon_element32(rn, a->vn, 0, MO_32);
354
rn0_64 = tcg_temp_new_i64();
355
opfn(rn0_64, rn, scalar);
356
- tcg_temp_free_i32(rn);
357
358
- rn = neon_load_reg(a->vn, 1);
359
+ read_neon_element32(rn, a->vn, 1, MO_32);
360
rn1_64 = tcg_temp_new_i64();
361
opfn(rn1_64, rn, scalar);
362
tcg_temp_free_i32(rn);
363
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
364
return false;
365
}
366
n <<= 3;
367
+ tmp = tcg_temp_new_i32();
368
if (a->op) {
369
- tmp = neon_load_reg(a->vd, 0);
370
+ read_neon_element32(tmp, a->vd, 0, MO_32);
371
} else {
372
- tmp = tcg_temp_new_i32();
373
tcg_gen_movi_i32(tmp, 0);
374
}
375
- tmp2 = neon_load_reg(a->vm, 0);
376
+ tmp2 = tcg_temp_new_i32();
377
+ read_neon_element32(tmp2, a->vm, 0, MO_32);
378
ptr1 = vfp_reg_ptr(true, a->vn);
379
tmp4 = tcg_const_i32(n);
380
gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
381
- tcg_temp_free_i32(tmp);
382
+
383
if (a->op) {
384
- tmp = neon_load_reg(a->vd, 1);
385
+ read_neon_element32(tmp, a->vd, 1, MO_32);
386
} else {
387
- tmp = tcg_temp_new_i32();
388
tcg_gen_movi_i32(tmp, 0);
389
}
390
- tmp3 = neon_load_reg(a->vm, 1);
391
+ tmp3 = tcg_temp_new_i32();
392
+ read_neon_element32(tmp3, a->vm, 1, MO_32);
393
gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
394
+ tcg_temp_free_i32(tmp);
395
tcg_temp_free_i32(tmp4);
396
tcg_temp_free_ptr(ptr1);
397
- neon_store_reg(a->vd, 0, tmp2);
398
- neon_store_reg(a->vd, 1, tmp3);
399
- tcg_temp_free_i32(tmp);
400
+
401
+ write_neon_element32(tmp2, a->vd, 0, MO_32);
402
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
403
+ tcg_temp_free_i32(tmp2);
404
+ tcg_temp_free_i32(tmp3);
405
return true;
406
}
407
408
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
409
static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
410
{
411
int pass, half;
412
+ TCGv_i32 tmp[2];
413
414
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
415
return false;
416
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
417
return true;
418
}
419
420
- for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
421
- TCGv_i32 tmp[2];
422
+ tmp[0] = tcg_temp_new_i32();
423
+ tmp[1] = tcg_temp_new_i32();
424
425
+ for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
426
for (half = 0; half < 2; half++) {
427
- tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
428
+ read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32);
429
switch (a->size) {
430
case 0:
431
tcg_gen_bswap32_i32(tmp[half], tmp[half]);
432
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
433
g_assert_not_reached();
434
}
435
}
436
- neon_store_reg(a->vd, pass * 2, tmp[1]);
437
- neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
438
+ write_neon_element32(tmp[1], a->vd, pass * 2, MO_32);
439
+ write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32);
440
}
441
+
442
+ tcg_temp_free_i32(tmp[0]);
443
+ tcg_temp_free_i32(tmp[1]);
444
return true;
445
}
446
447
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
448
rm0_64 = tcg_temp_new_i64();
449
rm1_64 = tcg_temp_new_i64();
450
rd_64 = tcg_temp_new_i64();
451
- tmp = neon_load_reg(a->vm, pass * 2);
452
+
453
+ tmp = tcg_temp_new_i32();
454
+ read_neon_element32(tmp, a->vm, pass * 2, MO_32);
455
widenfn(rm0_64, tmp);
456
- tcg_temp_free_i32(tmp);
457
- tmp = neon_load_reg(a->vm, pass * 2 + 1);
458
+ read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32);
459
widenfn(rm1_64, tmp);
460
tcg_temp_free_i32(tmp);
461
+
462
opfn(rd_64, rm0_64, rm1_64);
463
tcg_temp_free_i64(rm0_64);
464
tcg_temp_free_i64(rm1_64);
465
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
466
narrowfn(rd0, cpu_env, rm);
467
neon_load_reg64(rm, a->vm + 1);
468
narrowfn(rd1, cpu_env, rm);
469
- neon_store_reg(a->vd, 0, rd0);
470
- neon_store_reg(a->vd, 1, rd1);
471
+ write_neon_element32(rd0, a->vd, 0, MO_32);
472
+ write_neon_element32(rd1, a->vd, 1, MO_32);
473
+ tcg_temp_free_i32(rd0);
474
+ tcg_temp_free_i32(rd1);
475
tcg_temp_free_i64(rm);
476
return true;
477
}
478
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
479
}
480
481
rd = tcg_temp_new_i64();
482
+ rm0 = tcg_temp_new_i32();
483
+ rm1 = tcg_temp_new_i32();
484
485
- rm0 = neon_load_reg(a->vm, 0);
486
- rm1 = neon_load_reg(a->vm, 1);
487
+ read_neon_element32(rm0, a->vm, 0, MO_32);
488
+ read_neon_element32(rm1, a->vm, 1, MO_32);
489
490
widenfn(rd, rm0);
491
tcg_gen_shli_i64(rd, rd, 8 << a->size);
492
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
493
494
fpst = fpstatus_ptr(FPST_STD);
495
ahp = get_ahp_flag();
496
- tmp = neon_load_reg(a->vm, 0);
497
+ tmp = tcg_temp_new_i32();
498
+ read_neon_element32(tmp, a->vm, 0, MO_32);
499
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
500
- tmp2 = neon_load_reg(a->vm, 1);
501
+ tmp2 = tcg_temp_new_i32();
502
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
503
gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
504
tcg_gen_shli_i32(tmp2, tmp2, 16);
505
tcg_gen_or_i32(tmp2, tmp2, tmp);
506
- tcg_temp_free_i32(tmp);
507
- tmp = neon_load_reg(a->vm, 2);
508
+ read_neon_element32(tmp, a->vm, 2, MO_32);
509
gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
510
- tmp3 = neon_load_reg(a->vm, 3);
511
- neon_store_reg(a->vd, 0, tmp2);
512
+ tmp3 = tcg_temp_new_i32();
513
+ read_neon_element32(tmp3, a->vm, 3, MO_32);
514
+ write_neon_element32(tmp2, a->vd, 0, MO_32);
515
+ tcg_temp_free_i32(tmp2);
516
gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
517
tcg_gen_shli_i32(tmp3, tmp3, 16);
518
tcg_gen_or_i32(tmp3, tmp3, tmp);
519
- neon_store_reg(a->vd, 1, tmp3);
520
+ write_neon_element32(tmp3, a->vd, 1, MO_32);
521
+ tcg_temp_free_i32(tmp3);
522
tcg_temp_free_i32(tmp);
523
tcg_temp_free_i32(ahp);
524
tcg_temp_free_ptr(fpst);
525
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
526
fpst = fpstatus_ptr(FPST_STD);
527
ahp = get_ahp_flag();
528
tmp3 = tcg_temp_new_i32();
529
- tmp = neon_load_reg(a->vm, 0);
530
- tmp2 = neon_load_reg(a->vm, 1);
531
+ tmp2 = tcg_temp_new_i32();
532
+ tmp = tcg_temp_new_i32();
533
+ read_neon_element32(tmp, a->vm, 0, MO_32);
534
+ read_neon_element32(tmp2, a->vm, 1, MO_32);
535
tcg_gen_ext16u_i32(tmp3, tmp);
536
gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
537
- neon_store_reg(a->vd, 0, tmp3);
538
+ write_neon_element32(tmp3, a->vd, 0, MO_32);
539
tcg_gen_shri_i32(tmp, tmp, 16);
540
gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
541
- neon_store_reg(a->vd, 1, tmp);
542
- tmp3 = tcg_temp_new_i32();
543
+ write_neon_element32(tmp, a->vd, 1, MO_32);
544
+ tcg_temp_free_i32(tmp);
545
tcg_gen_ext16u_i32(tmp3, tmp2);
546
gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
547
- neon_store_reg(a->vd, 2, tmp3);
548
+ write_neon_element32(tmp3, a->vd, 2, MO_32);
549
+ tcg_temp_free_i32(tmp3);
550
tcg_gen_shri_i32(tmp2, tmp2, 16);
551
gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
552
- neon_store_reg(a->vd, 3, tmp2);
553
+ write_neon_element32(tmp2, a->vd, 3, MO_32);
554
+ tcg_temp_free_i32(tmp2);
555
tcg_temp_free_i32(ahp);
556
tcg_temp_free_ptr(fpst);
557
558
@@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
559
560
static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
561
{
562
+ TCGv_i32 tmp;
563
int pass;
564
565
/* Handle a 2-reg-misc operation by iterating 32 bits at a time */
566
@@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
567
return true;
568
}
569
570
+ tmp = tcg_temp_new_i32();
571
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
572
- TCGv_i32 tmp = neon_load_reg(a->vm, pass);
573
+ read_neon_element32(tmp, a->vm, pass, MO_32);
574
fn(tmp, tmp);
575
- neon_store_reg(a->vd, pass, tmp);
576
+ write_neon_element32(tmp, a->vd, pass, MO_32);
577
}
578
+ tcg_temp_free_i32(tmp);
579
580
return true;
581
}
582
@@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a)
583
return true;
584
}
585
586
- if (a->size == 2) {
587
+ tmp = tcg_temp_new_i32();
588
+ tmp2 = tcg_temp_new_i32();
589
+ if (a->size == MO_32) {
590
for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
591
- tmp = neon_load_reg(a->vm, pass);
592
- tmp2 = neon_load_reg(a->vd, pass + 1);
593
- neon_store_reg(a->vm, pass, tmp2);
594
- neon_store_reg(a->vd, pass + 1, tmp);
595
+ read_neon_element32(tmp, a->vm, pass, MO_32);
596
+ read_neon_element32(tmp2, a->vd, pass + 1, MO_32);
597
+ write_neon_element32(tmp2, a->vm, pass, MO_32);
598
+ write_neon_element32(tmp, a->vd, pass + 1, MO_32);
599
}
600
} else {
601
for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
602
- tmp = neon_load_reg(a->vm, pass);
603
- tmp2 = neon_load_reg(a->vd, pass);
604
- if (a->size == 0) {
605
+ read_neon_element32(tmp, a->vm, pass, MO_32);
606
+ read_neon_element32(tmp2, a->vd, pass, MO_32);
607
+ if (a->size == MO_8) {
608
gen_neon_trn_u8(tmp, tmp2);
609
} else {
610
gen_neon_trn_u16(tmp, tmp2);
611
}
612
- neon_store_reg(a->vm, pass, tmp2);
613
- neon_store_reg(a->vd, pass, tmp);
614
+ write_neon_element32(tmp2, a->vm, pass, MO_32);
615
+ write_neon_element32(tmp, a->vd, pass, MO_32);
616
}
617
}
618
+ tcg_temp_free_i32(tmp);
619
+ tcg_temp_free_i32(tmp2);
620
return true;
621
}
622
--
555
--
623
2.20.1
556
2.34.1
624
557
625
558
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Arnaud Minier <arnaud.minier@telecom-paris.fr>
2
2
3
This seems a bit more readable than using offsetof CPU_DoubleU.
3
Implement the ability to read and write characters to the
4
4
usart using the serial port.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
6
Message-id: 20201030022618.785675-5-richard.henderson@linaro.org
6
The character transmission is based on the
7
cmsdk-apb-uart implementation.
8
9
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
10
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20240329174402.60382-3-arnaud.minier@telecom-paris.fr
13
[PMM: fixed a few checkpatch nits]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
15
---
10
target/arm/translate.c | 13 ++++---------
16
include/hw/char/stm32l4x5_usart.h | 1 +
11
1 file changed, 4 insertions(+), 9 deletions(-)
17
hw/char/stm32l4x5_usart.c | 143 ++++++++++++++++++++++++++++++
12
18
hw/char/trace-events | 7 ++
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
3 files changed, 151 insertions(+)
20
21
diff --git a/include/hw/char/stm32l4x5_usart.h b/include/hw/char/stm32l4x5_usart.h
14
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate.c
23
--- a/include/hw/char/stm32l4x5_usart.h
16
+++ b/target/arm/translate.c
24
+++ b/include/hw/char/stm32l4x5_usart.h
17
@@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size)
25
@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5UsartBaseState {
18
return neon_full_reg_offset(reg) + ofs;
26
Clock *clk;
27
CharBackend chr;
28
qemu_irq irq;
29
+ guint watch_tag;
30
};
31
32
struct Stm32l4x5UsartBaseClass {
33
diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/char/stm32l4x5_usart.c
36
+++ b/hw/char/stm32l4x5_usart.c
37
@@ -XXX,XX +XXX,XX @@ REG32(RDR, 0x24)
38
REG32(TDR, 0x28)
39
FIELD(TDR, TDR, 0, 9)
40
41
+static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s)
42
+{
43
+ if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) ||
44
+ ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) ||
45
+ ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) ||
46
+ ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) ||
47
+ ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) ||
48
+ ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) ||
49
+ ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) ||
50
+ ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) ||
51
+ ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) ||
52
+ ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) ||
53
+ ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) ||
54
+ ((s->isr & R_ISR_ORE_MASK) &&
55
+ ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) ||
56
+ /* TODO: Handle NF ? */
57
+ ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) ||
58
+ ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) {
59
+ qemu_irq_raise(s->irq);
60
+ trace_stm32l4x5_usart_irq_raised(s->isr);
61
+ } else {
62
+ qemu_irq_lower(s->irq);
63
+ trace_stm32l4x5_usart_irq_lowered();
64
+ }
65
+}
66
+
67
+static int stm32l4x5_usart_base_can_receive(void *opaque)
68
+{
69
+ Stm32l4x5UsartBaseState *s = opaque;
70
+
71
+ if (!(s->isr & R_ISR_RXNE_MASK)) {
72
+ return 1;
73
+ }
74
+
75
+ return 0;
76
+}
77
+
78
+static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf,
79
+ int size)
80
+{
81
+ Stm32l4x5UsartBaseState *s = opaque;
82
+
83
+ if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) {
84
+ trace_stm32l4x5_usart_receiver_not_enabled(
85
+ FIELD_EX32(s->cr1, CR1, UE), FIELD_EX32(s->cr1, CR1, RE));
86
+ return;
87
+ }
88
+
89
+ /* Check if overrun detection is enabled and if there is an overrun */
90
+ if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) {
91
+ /*
92
+ * A character has been received while
93
+ * the previous has not been read = Overrun.
94
+ */
95
+ s->isr |= R_ISR_ORE_MASK;
96
+ trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf);
97
+ } else {
98
+ /* No overrun */
99
+ s->rdr = *buf;
100
+ s->isr |= R_ISR_RXNE_MASK;
101
+ trace_stm32l4x5_usart_rx(s->rdr);
102
+ }
103
+
104
+ stm32l4x5_update_irq(s);
105
+}
106
+
107
+/*
108
+ * Try to send tx data, and arrange to be called back later if
109
+ * we can't (ie the char backend is busy/blocking).
110
+ */
111
+static gboolean usart_transmit(void *do_not_use, GIOCondition cond,
112
+ void *opaque)
113
+{
114
+ Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(opaque);
115
+ int ret;
116
+ /* TODO: Handle 9 bits transmission */
117
+ uint8_t ch = s->tdr;
118
+
119
+ s->watch_tag = 0;
120
+
121
+ if (!(s->cr1 & R_CR1_TE_MASK) || (s->isr & R_ISR_TXE_MASK)) {
122
+ return G_SOURCE_REMOVE;
123
+ }
124
+
125
+ ret = qemu_chr_fe_write(&s->chr, &ch, 1);
126
+ if (ret <= 0) {
127
+ s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
128
+ usart_transmit, s);
129
+ if (!s->watch_tag) {
130
+ /*
131
+ * Most common reason to be here is "no chardev backend":
132
+ * just insta-drain the buffer, so the serial output
133
+ * goes into a void, rather than blocking the guest.
134
+ */
135
+ goto buffer_drained;
136
+ }
137
+ /* Transmit pending */
138
+ trace_stm32l4x5_usart_tx_pending();
139
+ return G_SOURCE_REMOVE;
140
+ }
141
+
142
+buffer_drained:
143
+ /* Character successfully sent */
144
+ trace_stm32l4x5_usart_tx(ch);
145
+ s->isr |= R_ISR_TC_MASK | R_ISR_TXE_MASK;
146
+ stm32l4x5_update_irq(s);
147
+ return G_SOURCE_REMOVE;
148
+}
149
+
150
+static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s)
151
+{
152
+ if (s->watch_tag) {
153
+ g_source_remove(s->watch_tag);
154
+ s->watch_tag = 0;
155
+ }
156
+}
157
+
158
static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type)
159
{
160
Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj);
161
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type)
162
s->isr = 0x020000C0;
163
s->rdr = 0x00000000;
164
s->tdr = 0x00000000;
165
+
166
+ usart_cancel_transmit(s);
167
+ stm32l4x5_update_irq(s);
168
+}
169
+
170
+static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value)
171
+{
172
+ /* TXFRQ */
173
+ /* Reset RXNE flag */
174
+ if (value & R_RQR_RXFRQ_MASK) {
175
+ s->isr &= ~R_ISR_RXNE_MASK;
176
+ }
177
+ /* MMRQ */
178
+ /* SBKRQ */
179
+ /* ABRRQ */
180
+ stm32l4x5_update_irq(s);
19
}
181
}
20
182
21
-static inline long vfp_reg_offset(bool dp, unsigned reg)
183
static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr,
22
+/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */
184
@@ -XXX,XX +XXX,XX @@ static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr,
23
+static long vfp_reg_offset(bool dp, unsigned reg)
185
retvalue = FIELD_EX32(s->rdr, RDR, RDR);
24
{
186
/* Reset RXNE flag */
25
if (dp) {
187
s->isr &= ~R_ISR_RXNE_MASK;
26
- return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
188
+ stm32l4x5_update_irq(s);
27
+ return neon_element_offset(reg, 0, MO_64);
189
break;
28
} else {
190
case A_TDR:
29
- long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]);
191
retvalue = FIELD_EX32(s->tdr, TDR, TDR);
30
- if (reg & 1) {
192
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
31
- ofs += offsetof(CPU_DoubleU, l.upper);
193
switch (addr) {
32
- } else {
194
case A_CR1:
33
- ofs += offsetof(CPU_DoubleU, l.lower);
195
s->cr1 = value;
34
- }
196
+ stm32l4x5_update_irq(s);
35
- return ofs;
197
return;
36
+ return neon_element_offset(reg >> 1, reg & 1, MO_32);
198
case A_CR2:
199
s->cr2 = value;
200
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
201
s->rtor = value;
202
return;
203
case A_RQR:
204
+ usart_update_rqr(s, value);
205
return;
206
case A_ISR:
207
qemu_log_mask(LOG_GUEST_ERROR,
208
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
209
case A_ICR:
210
/* Clear the status flags */
211
s->isr &= ~value;
212
+ stm32l4x5_update_irq(s);
213
return;
214
case A_RDR:
215
qemu_log_mask(LOG_GUEST_ERROR,
216
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
217
return;
218
case A_TDR:
219
s->tdr = value;
220
+ s->isr &= ~R_ISR_TXE_MASK;
221
+ usart_transmit(NULL, G_IO_OUT, s);
222
return;
223
default:
224
qemu_log_mask(LOG_GUEST_ERROR,
225
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp)
226
error_setg(errp, "USART clock must be wired up by SoC code");
227
return;
37
}
228
}
229
+
230
+ qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive,
231
+ stm32l4x5_usart_base_receive, NULL, NULL,
232
+ s, NULL, true);
38
}
233
}
39
234
235
static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data)
236
diff --git a/hw/char/trace-events b/hw/char/trace-events
237
index XXXXXXX..XXXXXXX 100644
238
--- a/hw/char/trace-events
239
+++ b/hw/char/trace-events
240
@@ -XXX,XX +XXX,XX @@ sh_serial_write(char *id, unsigned size, uint64_t offs, uint64_t val) "%s size %
241
# stm32l4x5_usart.c
242
stm32l4x5_usart_read(uint64_t addr, uint32_t data) "USART: Read <0x%" PRIx64 "> -> 0x%" PRIx32 ""
243
stm32l4x5_usart_write(uint64_t addr, uint32_t data) "USART: Write <0x%" PRIx64 "> <- 0x%" PRIx32 ""
244
+stm32l4x5_usart_rx(uint8_t c) "USART: got character 0x%x from backend"
245
+stm32l4x5_usart_tx(uint8_t c) "USART: character 0x%x sent to backend"
246
+stm32l4x5_usart_tx_pending(void) "USART: character send to backend pending"
247
+stm32l4x5_usart_irq_raised(uint32_t reg) "USART: IRQ raised: 0x%08"PRIx32
248
+stm32l4x5_usart_irq_lowered(void) "USART: IRQ lowered"
249
+stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received) "USART: Overrun detected, RDR='0x%x', received 0x%x"
250
+stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit) "USART: Receiver not enabled, UE=0x%x, RE=0x%x"
251
252
# xen_console.c
253
xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int port, unsigned int limit) "idx %u ring_ref %u port %u limit %u"
40
--
254
--
41
2.20.1
255
2.34.1
42
256
43
257
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Arnaud Minier <arnaud.minier@telecom-paris.fr>
2
2
3
Replace all uses of neon_load/store_reg64 within translate-neon.c.inc.
3
Add a function to change the settings of the
4
serial connection.
4
5
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
6
Message-id: 20201030022618.785675-9-richard.henderson@linaro.org
7
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20240329174402.60382-4-arnaud.minier@telecom-paris.fr
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate.c | 26 +++++++++
12
hw/char/stm32l4x5_usart.c | 98 +++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-neon.c.inc | 94 ++++++++++++++++-----------------
13
hw/char/trace-events | 1 +
12
2 files changed, 73 insertions(+), 47 deletions(-)
14
2 files changed, 99 insertions(+)
13
15
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
18
--- a/hw/char/stm32l4x5_usart.c
17
+++ b/target/arm/translate.c
19
+++ b/hw/char/stm32l4x5_usart.c
18
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
20
@@ -XXX,XX +XXX,XX @@ static void usart_cancel_transmit(Stm32l4x5UsartBaseState *s)
19
}
21
}
20
}
22
}
21
23
22
+static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
24
+static void stm32l4x5_update_params(Stm32l4x5UsartBaseState *s)
23
+{
25
+{
24
+ long off = neon_element_offset(reg, ele, memop);
26
+ int speed, parity, data_bits, stop_bits;
27
+ uint32_t value, usart_div;
28
+ QEMUSerialSetParams ssp;
25
+
29
+
26
+ switch (memop) {
30
+ /* Select the parity type */
27
+ case MO_Q:
31
+ if (s->cr1 & R_CR1_PCE_MASK) {
28
+ tcg_gen_ld_i64(dest, cpu_env, off);
32
+ if (s->cr1 & R_CR1_PS_MASK) {
33
+ parity = 'O';
34
+ } else {
35
+ parity = 'E';
36
+ }
37
+ } else {
38
+ parity = 'N';
39
+ }
40
+
41
+ /* Select the number of stop bits */
42
+ switch (FIELD_EX32(s->cr2, CR2, STOP)) {
43
+ case 0:
44
+ stop_bits = 1;
45
+ break;
46
+ case 2:
47
+ stop_bits = 2;
29
+ break;
48
+ break;
30
+ default:
49
+ default:
31
+ g_assert_not_reached();
50
+ qemu_log_mask(LOG_UNIMP,
51
+ "UNIMPLEMENTED: fractionnal stop bits; CR2[13:12] = %u",
52
+ FIELD_EX32(s->cr2, CR2, STOP));
53
+ return;
32
+ }
54
+ }
55
+
56
+ /* Select the length of the word */
57
+ switch ((FIELD_EX32(s->cr1, CR1, M1) << 1) | FIELD_EX32(s->cr1, CR1, M0)) {
58
+ case 0:
59
+ data_bits = 8;
60
+ break;
61
+ case 1:
62
+ data_bits = 9;
63
+ break;
64
+ case 2:
65
+ data_bits = 7;
66
+ break;
67
+ default:
68
+ qemu_log_mask(LOG_GUEST_ERROR,
69
+ "UNDEFINED: invalid word length, CR1.M = 0b11");
70
+ return;
71
+ }
72
+
73
+ /* Select the baud rate */
74
+ value = FIELD_EX32(s->brr, BRR, BRR);
75
+ if (value < 16) {
76
+ qemu_log_mask(LOG_GUEST_ERROR,
77
+ "UNDEFINED: BRR less than 16: %u", value);
78
+ return;
79
+ }
80
+
81
+ if (FIELD_EX32(s->cr1, CR1, OVER8) == 0) {
82
+ /*
83
+ * Oversampling by 16
84
+ * BRR = USARTDIV
85
+ */
86
+ usart_div = value;
87
+ } else {
88
+ /*
89
+ * Oversampling by 8
90
+ * - BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
91
+ * - BRR[3] must be kept cleared.
92
+ * - BRR[15:4] = USARTDIV[15:4]
93
+ * - The frequency is multiplied by 2
94
+ */
95
+ usart_div = ((value & 0xFFF0) | ((value & 0x0007) << 1)) / 2;
96
+ }
97
+
98
+ speed = clock_get_hz(s->clk) / usart_div;
99
+
100
+ ssp.speed = speed;
101
+ ssp.parity = parity;
102
+ ssp.data_bits = data_bits;
103
+ ssp.stop_bits = stop_bits;
104
+
105
+ qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
106
+
107
+ trace_stm32l4x5_usart_update_params(speed, parity, data_bits, stop_bits);
33
+}
108
+}
34
+
109
+
35
static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
110
static void stm32l4x5_usart_base_reset_hold(Object *obj, ResetType type)
36
{
111
{
37
long off = neon_element_offset(reg, ele, memop);
112
Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj);
38
@@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
113
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr,
39
}
114
switch (addr) {
115
case A_CR1:
116
s->cr1 = value;
117
+ stm32l4x5_update_params(s);
118
stm32l4x5_update_irq(s);
119
return;
120
case A_CR2:
121
s->cr2 = value;
122
+ stm32l4x5_update_params(s);
123
return;
124
case A_CR3:
125
s->cr3 = value;
126
return;
127
case A_BRR:
128
s->brr = value;
129
+ stm32l4x5_update_params(s);
130
return;
131
case A_GTPR:
132
s->gtpr = value;
133
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_usart_base_init(Object *obj)
134
s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
40
}
135
}
41
136
42
+static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
137
+static int stm32l4x5_usart_base_post_load(void *opaque, int version_id)
43
+{
138
+{
44
+ long off = neon_element_offset(reg, ele, memop);
139
+ Stm32l4x5UsartBaseState *s = (Stm32l4x5UsartBaseState *)opaque;
45
+
140
+
46
+ switch (memop) {
141
+ stm32l4x5_update_params(s);
47
+ case MO_64:
142
+ return 0;
48
+ tcg_gen_st_i64(src, cpu_env, off);
49
+ break;
50
+ default:
51
+ g_assert_not_reached();
52
+ }
53
+}
143
+}
54
+
144
+
55
static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
145
static const VMStateDescription vmstate_stm32l4x5_usart_base = {
56
{
146
.name = TYPE_STM32L4X5_USART_BASE,
57
TCGv_ptr ret = tcg_temp_new_ptr();
147
.version_id = 1,
58
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
148
.minimum_version_id = 1,
149
+ .post_load = stm32l4x5_usart_base_post_load,
150
.fields = (VMStateField[]) {
151
VMSTATE_UINT32(cr1, Stm32l4x5UsartBaseState),
152
VMSTATE_UINT32(cr2, Stm32l4x5UsartBaseState),
153
diff --git a/hw/char/trace-events b/hw/char/trace-events
59
index XXXXXXX..XXXXXXX 100644
154
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/translate-neon.c.inc
155
--- a/hw/char/trace-events
61
+++ b/target/arm/translate-neon.c.inc
156
+++ b/hw/char/trace-events
62
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
157
@@ -XXX,XX +XXX,XX @@ stm32l4x5_usart_irq_raised(uint32_t reg) "USART: IRQ raised: 0x%08"PRIx32
63
for (pass = 0; pass < a->q + 1; pass++) {
158
stm32l4x5_usart_irq_lowered(void) "USART: IRQ lowered"
64
TCGv_i64 tmp = tcg_temp_new_i64();
159
stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received) "USART: Overrun detected, RDR='0x%x', received 0x%x"
65
160
stm32l4x5_usart_receiver_not_enabled(uint8_t ue_bit, uint8_t re_bit) "USART: Receiver not enabled, UE=0x%x, RE=0x%x"
66
- neon_load_reg64(tmp, a->vm + pass);
161
+stm32l4x5_usart_update_params(int speed, uint8_t parity, int data, int stop) "USART: speed: %d, parity: %c, data bits: %d, stop bits: %d"
67
+ read_neon_element64(tmp, a->vm, pass, MO_64);
162
68
fn(tmp, cpu_env, tmp, constimm);
163
# xen_console.c
69
- neon_store_reg64(tmp, a->vd + pass);
164
xen_console_connect(unsigned int idx, unsigned int ring_ref, unsigned int port, unsigned int limit) "idx %u ring_ref %u port %u limit %u"
70
+ write_neon_element64(tmp, a->vd, pass, MO_64);
71
tcg_temp_free_i64(tmp);
72
}
73
tcg_temp_free_i64(constimm);
74
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
75
rd = tcg_temp_new_i32();
76
77
/* Load both inputs first to avoid potential overwrite if rm == rd */
78
- neon_load_reg64(rm1, a->vm);
79
- neon_load_reg64(rm2, a->vm + 1);
80
+ read_neon_element64(rm1, a->vm, 0, MO_64);
81
+ read_neon_element64(rm2, a->vm, 1, MO_64);
82
83
shiftfn(rm1, rm1, constimm);
84
narrowfn(rd, cpu_env, rm1);
85
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
86
tcg_gen_shli_i64(tmp, tmp, a->shift);
87
tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
88
}
89
- neon_store_reg64(tmp, a->vd);
90
+ write_neon_element64(tmp, a->vd, 0, MO_64);
91
92
widenfn(tmp, rm1);
93
tcg_temp_free_i32(rm1);
94
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
95
tcg_gen_shli_i64(tmp, tmp, a->shift);
96
tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
97
}
98
- neon_store_reg64(tmp, a->vd + 1);
99
+ write_neon_element64(tmp, a->vd, 1, MO_64);
100
tcg_temp_free_i64(tmp);
101
return true;
102
}
103
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
104
rm_64 = tcg_temp_new_i64();
105
106
if (src1_wide) {
107
- neon_load_reg64(rn0_64, a->vn);
108
+ read_neon_element64(rn0_64, a->vn, 0, MO_64);
109
} else {
110
TCGv_i32 tmp = tcg_temp_new_i32();
111
read_neon_element32(tmp, a->vn, 0, MO_32);
112
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
113
* avoid incorrect results if a narrow input overlaps with the result.
114
*/
115
if (src1_wide) {
116
- neon_load_reg64(rn1_64, a->vn + 1);
117
+ read_neon_element64(rn1_64, a->vn, 1, MO_64);
118
} else {
119
TCGv_i32 tmp = tcg_temp_new_i32();
120
read_neon_element32(tmp, a->vn, 1, MO_32);
121
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
122
rm = tcg_temp_new_i32();
123
read_neon_element32(rm, a->vm, 1, MO_32);
124
125
- neon_store_reg64(rn0_64, a->vd);
126
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
127
128
widenfn(rm_64, rm);
129
tcg_temp_free_i32(rm);
130
opfn(rn1_64, rn1_64, rm_64);
131
- neon_store_reg64(rn1_64, a->vd + 1);
132
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
133
134
tcg_temp_free_i64(rn0_64);
135
tcg_temp_free_i64(rn1_64);
136
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
137
rd0 = tcg_temp_new_i32();
138
rd1 = tcg_temp_new_i32();
139
140
- neon_load_reg64(rn_64, a->vn);
141
- neon_load_reg64(rm_64, a->vm);
142
+ read_neon_element64(rn_64, a->vn, 0, MO_64);
143
+ read_neon_element64(rm_64, a->vm, 0, MO_64);
144
145
opfn(rn_64, rn_64, rm_64);
146
147
narrowfn(rd0, rn_64);
148
149
- neon_load_reg64(rn_64, a->vn + 1);
150
- neon_load_reg64(rm_64, a->vm + 1);
151
+ read_neon_element64(rn_64, a->vn, 1, MO_64);
152
+ read_neon_element64(rm_64, a->vm, 1, MO_64);
153
154
opfn(rn_64, rn_64, rm_64);
155
156
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
157
/* Don't store results until after all loads: they might overlap */
158
if (accfn) {
159
tmp = tcg_temp_new_i64();
160
- neon_load_reg64(tmp, a->vd);
161
+ read_neon_element64(tmp, a->vd, 0, MO_64);
162
accfn(tmp, tmp, rd0);
163
- neon_store_reg64(tmp, a->vd);
164
- neon_load_reg64(tmp, a->vd + 1);
165
+ write_neon_element64(tmp, a->vd, 0, MO_64);
166
+ read_neon_element64(tmp, a->vd, 1, MO_64);
167
accfn(tmp, tmp, rd1);
168
- neon_store_reg64(tmp, a->vd + 1);
169
+ write_neon_element64(tmp, a->vd, 1, MO_64);
170
tcg_temp_free_i64(tmp);
171
} else {
172
- neon_store_reg64(rd0, a->vd);
173
- neon_store_reg64(rd1, a->vd + 1);
174
+ write_neon_element64(rd0, a->vd, 0, MO_64);
175
+ write_neon_element64(rd1, a->vd, 1, MO_64);
176
}
177
178
tcg_temp_free_i64(rd0);
179
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
180
181
if (accfn) {
182
TCGv_i64 t64 = tcg_temp_new_i64();
183
- neon_load_reg64(t64, a->vd);
184
+ read_neon_element64(t64, a->vd, 0, MO_64);
185
accfn(t64, t64, rn0_64);
186
- neon_store_reg64(t64, a->vd);
187
- neon_load_reg64(t64, a->vd + 1);
188
+ write_neon_element64(t64, a->vd, 0, MO_64);
189
+ read_neon_element64(t64, a->vd, 1, MO_64);
190
accfn(t64, t64, rn1_64);
191
- neon_store_reg64(t64, a->vd + 1);
192
+ write_neon_element64(t64, a->vd, 1, MO_64);
193
tcg_temp_free_i64(t64);
194
} else {
195
- neon_store_reg64(rn0_64, a->vd);
196
- neon_store_reg64(rn1_64, a->vd + 1);
197
+ write_neon_element64(rn0_64, a->vd, 0, MO_64);
198
+ write_neon_element64(rn1_64, a->vd, 1, MO_64);
199
}
200
tcg_temp_free_i64(rn0_64);
201
tcg_temp_free_i64(rn1_64);
202
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
203
right = tcg_temp_new_i64();
204
dest = tcg_temp_new_i64();
205
206
- neon_load_reg64(right, a->vn);
207
- neon_load_reg64(left, a->vm);
208
+ read_neon_element64(right, a->vn, 0, MO_64);
209
+ read_neon_element64(left, a->vm, 0, MO_64);
210
tcg_gen_extract2_i64(dest, right, left, a->imm * 8);
211
- neon_store_reg64(dest, a->vd);
212
+ write_neon_element64(dest, a->vd, 0, MO_64);
213
214
tcg_temp_free_i64(left);
215
tcg_temp_free_i64(right);
216
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
217
destright = tcg_temp_new_i64();
218
219
if (a->imm < 8) {
220
- neon_load_reg64(right, a->vn);
221
- neon_load_reg64(middle, a->vn + 1);
222
+ read_neon_element64(right, a->vn, 0, MO_64);
223
+ read_neon_element64(middle, a->vn, 1, MO_64);
224
tcg_gen_extract2_i64(destright, right, middle, a->imm * 8);
225
- neon_load_reg64(left, a->vm);
226
+ read_neon_element64(left, a->vm, 0, MO_64);
227
tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8);
228
} else {
229
- neon_load_reg64(right, a->vn + 1);
230
- neon_load_reg64(middle, a->vm);
231
+ read_neon_element64(right, a->vn, 1, MO_64);
232
+ read_neon_element64(middle, a->vm, 0, MO_64);
233
tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8);
234
- neon_load_reg64(left, a->vm + 1);
235
+ read_neon_element64(left, a->vm, 1, MO_64);
236
tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8);
237
}
238
239
- neon_store_reg64(destright, a->vd);
240
- neon_store_reg64(destleft, a->vd + 1);
241
+ write_neon_element64(destright, a->vd, 0, MO_64);
242
+ write_neon_element64(destleft, a->vd, 1, MO_64);
243
244
tcg_temp_free_i64(destright);
245
tcg_temp_free_i64(destleft);
246
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
247
248
if (accfn) {
249
TCGv_i64 tmp64 = tcg_temp_new_i64();
250
- neon_load_reg64(tmp64, a->vd + pass);
251
+ read_neon_element64(tmp64, a->vd, pass, MO_64);
252
accfn(rd_64, tmp64, rd_64);
253
tcg_temp_free_i64(tmp64);
254
}
255
- neon_store_reg64(rd_64, a->vd + pass);
256
+ write_neon_element64(rd_64, a->vd, pass, MO_64);
257
tcg_temp_free_i64(rd_64);
258
}
259
return true;
260
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
261
rd0 = tcg_temp_new_i32();
262
rd1 = tcg_temp_new_i32();
263
264
- neon_load_reg64(rm, a->vm);
265
+ read_neon_element64(rm, a->vm, 0, MO_64);
266
narrowfn(rd0, cpu_env, rm);
267
- neon_load_reg64(rm, a->vm + 1);
268
+ read_neon_element64(rm, a->vm, 1, MO_64);
269
narrowfn(rd1, cpu_env, rm);
270
write_neon_element32(rd0, a->vd, 0, MO_32);
271
write_neon_element32(rd1, a->vd, 1, MO_32);
272
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
273
274
widenfn(rd, rm0);
275
tcg_gen_shli_i64(rd, rd, 8 << a->size);
276
- neon_store_reg64(rd, a->vd);
277
+ write_neon_element64(rd, a->vd, 0, MO_64);
278
widenfn(rd, rm1);
279
tcg_gen_shli_i64(rd, rd, 8 << a->size);
280
- neon_store_reg64(rd, a->vd + 1);
281
+ write_neon_element64(rd, a->vd, 1, MO_64);
282
283
tcg_temp_free_i64(rd);
284
tcg_temp_free_i32(rm0);
285
@@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
286
rm = tcg_temp_new_i64();
287
rd = tcg_temp_new_i64();
288
for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
289
- neon_load_reg64(rm, a->vm + pass);
290
- neon_load_reg64(rd, a->vd + pass);
291
- neon_store_reg64(rm, a->vd + pass);
292
- neon_store_reg64(rd, a->vm + pass);
293
+ read_neon_element64(rm, a->vm, pass, MO_64);
294
+ read_neon_element64(rd, a->vd, pass, MO_64);
295
+ write_neon_element64(rm, a->vd, pass, MO_64);
296
+ write_neon_element64(rd, a->vm, pass, MO_64);
297
}
298
tcg_temp_free_i64(rm);
299
tcg_temp_free_i64(rd);
300
--
165
--
301
2.20.1
166
2.34.1
302
167
303
168
diff view generated by jsdifflib
1
From: AlexChen <alex.chen@huawei.com>
1
From: Arnaud Minier <arnaud.minier@telecom-paris.fr>
2
2
3
In exynos4210_fimd_update(), the pointer s is dereferinced before
3
Add the USART to the SoC and connect it to the other implemented devices.
4
being check if it is valid, which may lead to NULL pointer dereference.
4
5
So move the assignment to global_width after checking that the s is valid.
5
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
6
6
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
7
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20240329174402.60382-5-arnaud.minier@telecom-paris.fr
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
[PMM: fixed a few checkpatch nits]
10
Message-id: 5F9F8D88.9030102@huawei.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
hw/display/exynos4210_fimd.c | 4 +++-
12
docs/system/arm/b-l475e-iot01a.rst | 2 +-
14
1 file changed, 3 insertions(+), 1 deletion(-)
13
include/hw/arm/stm32l4x5_soc.h | 7 +++
15
14
hw/arm/stm32l4x5_soc.c | 83 +++++++++++++++++++++++++++---
16
diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c
15
hw/arm/Kconfig | 1 +
17
index XXXXXXX..XXXXXXX 100644
16
4 files changed, 86 insertions(+), 7 deletions(-)
18
--- a/hw/display/exynos4210_fimd.c
17
19
+++ b/hw/display/exynos4210_fimd.c
18
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
20
@@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque)
19
index XXXXXXX..XXXXXXX 100644
21
bool blend = false;
20
--- a/docs/system/arm/b-l475e-iot01a.rst
22
uint8_t *host_fb_addr;
21
+++ b/docs/system/arm/b-l475e-iot01a.rst
23
bool is_dirty = false;
22
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
24
- const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
23
- STM32L4x5 SYSCFG (System configuration controller)
25
+ int global_width;
24
- STM32L4x5 RCC (Reset and clock control)
26
25
- STM32L4x5 GPIOs (General-purpose I/Os)
27
if (!s || !s->console || !s->enabled ||
26
+- STM32L4x5 USARTs, UARTs and LPUART (Serial ports)
28
surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
27
29
return;
28
Missing devices
29
"""""""""""""""
30
31
The B-L475E-IOT01A does *not* support the following devices:
32
33
-- Serial ports (UART)
34
- Analog to Digital Converter (ADC)
35
- SPI controller
36
- Timer controller (TIMER)
37
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/include/hw/arm/stm32l4x5_soc.h
40
+++ b/include/hw/arm/stm32l4x5_soc.h
41
@@ -XXX,XX +XXX,XX @@
42
#include "hw/misc/stm32l4x5_exti.h"
43
#include "hw/misc/stm32l4x5_rcc.h"
44
#include "hw/gpio/stm32l4x5_gpio.h"
45
+#include "hw/char/stm32l4x5_usart.h"
46
#include "qom/object.h"
47
48
#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
49
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC)
50
51
#define NUM_EXTI_OR_GATES 4
52
53
+#define STM_NUM_USARTS 3
54
+#define STM_NUM_UARTS 2
55
+
56
struct Stm32l4x5SocState {
57
SysBusDevice parent_obj;
58
59
@@ -XXX,XX +XXX,XX @@ struct Stm32l4x5SocState {
60
Stm32l4x5SyscfgState syscfg;
61
Stm32l4x5RccState rcc;
62
Stm32l4x5GpioState gpio[NUM_GPIOS];
63
+ Stm32l4x5UsartBaseState usart[STM_NUM_USARTS];
64
+ Stm32l4x5UsartBaseState uart[STM_NUM_UARTS];
65
+ Stm32l4x5UsartBaseState lpuart;
66
67
MemoryRegion sram1;
68
MemoryRegion sram2;
69
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/arm/stm32l4x5_soc.c
72
+++ b/hw/arm/stm32l4x5_soc.c
73
@@ -XXX,XX +XXX,XX @@
74
#include "sysemu/sysemu.h"
75
#include "hw/or-irq.h"
76
#include "hw/arm/stm32l4x5_soc.h"
77
+#include "hw/char/stm32l4x5_usart.h"
78
#include "hw/gpio/stm32l4x5_gpio.h"
79
#include "hw/qdev-clock.h"
80
#include "hw/misc/unimp.h"
81
@@ -XXX,XX +XXX,XX @@ static const struct {
82
{ 0x48001C00, 0x0000000F, 0x00000000, 0x00000000 },
83
};
84
85
+static const hwaddr usart_addr[] = {
86
+ 0x40013800, /* "USART1", 0x400 */
87
+ 0x40004400, /* "USART2", 0x400 */
88
+ 0x40004800, /* "USART3", 0x400 */
89
+};
90
+static const hwaddr uart_addr[] = {
91
+ 0x40004C00, /* "UART4" , 0x400 */
92
+ 0x40005000 /* "UART5" , 0x400 */
93
+};
94
+
95
+#define LPUART_BASE_ADDRESS 0x40008000
96
+
97
+static const int usart_irq[] = { 37, 38, 39 };
98
+static const int uart_irq[] = { 52, 53 };
99
+#define LPUART_IRQ 70
100
+
101
static void stm32l4x5_soc_initfn(Object *obj)
102
{
103
Stm32l4x5SocState *s = STM32L4X5_SOC(obj);
104
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_initfn(Object *obj)
105
g_autofree char *name = g_strdup_printf("gpio%c", 'a' + i);
106
object_initialize_child(obj, name, &s->gpio[i], TYPE_STM32L4X5_GPIO);
30
}
107
}
31
+
108
+
32
+ global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
109
+ for (int i = 0; i < STM_NUM_USARTS; i++) {
33
exynos4210_update_resolution(s);
110
+ object_initialize_child(obj, "usart[*]", &s->usart[i],
34
surface = qemu_console_surface(s->console);
111
+ TYPE_STM32L4X5_USART);
35
112
+ }
113
+
114
+ for (int i = 0; i < STM_NUM_UARTS; i++) {
115
+ object_initialize_child(obj, "uart[*]", &s->uart[i],
116
+ TYPE_STM32L4X5_UART);
117
+ }
118
+ object_initialize_child(obj, "lpuart1", &s->lpuart,
119
+ TYPE_STM32L4X5_LPUART);
120
}
121
122
static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
123
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
124
sysbus_mmio_map(busdev, 0, RCC_BASE_ADDRESS);
125
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, RCC_IRQ));
126
127
+ /* USART devices */
128
+ for (int i = 0; i < STM_NUM_USARTS; i++) {
129
+ g_autofree char *name = g_strdup_printf("usart%d-out", i + 1);
130
+ dev = DEVICE(&(s->usart[i]));
131
+ qdev_prop_set_chr(dev, "chardev", serial_hd(i));
132
+ qdev_connect_clock_in(dev, "clk",
133
+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));
134
+ busdev = SYS_BUS_DEVICE(dev);
135
+ if (!sysbus_realize(busdev, errp)) {
136
+ return;
137
+ }
138
+ sysbus_mmio_map(busdev, 0, usart_addr[i]);
139
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
140
+ }
141
+
142
+ /*
143
+ * TODO: Connect the USARTs, UARTs and LPUART to the EXTI once the EXTI
144
+ * can handle other gpio-in than the gpios. (e.g. Direct Lines for the
145
+ * usarts)
146
+ */
147
+
148
+ /* UART devices */
149
+ for (int i = 0; i < STM_NUM_UARTS; i++) {
150
+ g_autofree char *name = g_strdup_printf("uart%d-out", STM_NUM_USARTS + i + 1);
151
+ dev = DEVICE(&(s->uart[i]));
152
+ qdev_prop_set_chr(dev, "chardev", serial_hd(STM_NUM_USARTS + i));
153
+ qdev_connect_clock_in(dev, "clk",
154
+ qdev_get_clock_out(DEVICE(&(s->rcc)), name));
155
+ busdev = SYS_BUS_DEVICE(dev);
156
+ if (!sysbus_realize(busdev, errp)) {
157
+ return;
158
+ }
159
+ sysbus_mmio_map(busdev, 0, uart_addr[i]);
160
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, uart_irq[i]));
161
+ }
162
+
163
+ /* LPUART device*/
164
+ dev = DEVICE(&(s->lpuart));
165
+ qdev_prop_set_chr(dev, "chardev", serial_hd(STM_NUM_USARTS + STM_NUM_UARTS));
166
+ qdev_connect_clock_in(dev, "clk",
167
+ qdev_get_clock_out(DEVICE(&(s->rcc)), "lpuart1-out"));
168
+ busdev = SYS_BUS_DEVICE(dev);
169
+ if (!sysbus_realize(busdev, errp)) {
170
+ return;
171
+ }
172
+ sysbus_mmio_map(busdev, 0, LPUART_BASE_ADDRESS);
173
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, LPUART_IRQ));
174
+
175
/* APB1 BUS */
176
create_unimplemented_device("TIM2", 0x40000000, 0x400);
177
create_unimplemented_device("TIM3", 0x40000400, 0x400);
178
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
179
create_unimplemented_device("SPI2", 0x40003800, 0x400);
180
create_unimplemented_device("SPI3", 0x40003C00, 0x400);
181
/* RESERVED: 0x40004000, 0x400 */
182
- create_unimplemented_device("USART2", 0x40004400, 0x400);
183
- create_unimplemented_device("USART3", 0x40004800, 0x400);
184
- create_unimplemented_device("UART4", 0x40004C00, 0x400);
185
- create_unimplemented_device("UART5", 0x40005000, 0x400);
186
create_unimplemented_device("I2C1", 0x40005400, 0x400);
187
create_unimplemented_device("I2C2", 0x40005800, 0x400);
188
create_unimplemented_device("I2C3", 0x40005C00, 0x400);
189
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
190
create_unimplemented_device("DAC1", 0x40007400, 0x400);
191
create_unimplemented_device("OPAMP", 0x40007800, 0x400);
192
create_unimplemented_device("LPTIM1", 0x40007C00, 0x400);
193
- create_unimplemented_device("LPUART1", 0x40008000, 0x400);
194
/* RESERVED: 0x40008400, 0x400 */
195
create_unimplemented_device("SWPMI1", 0x40008800, 0x400);
196
/* RESERVED: 0x40008C00, 0x800 */
197
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
198
create_unimplemented_device("TIM1", 0x40012C00, 0x400);
199
create_unimplemented_device("SPI1", 0x40013000, 0x400);
200
create_unimplemented_device("TIM8", 0x40013400, 0x400);
201
- create_unimplemented_device("USART1", 0x40013800, 0x400);
202
/* RESERVED: 0x40013C00, 0x400 */
203
create_unimplemented_device("TIM15", 0x40014000, 0x400);
204
create_unimplemented_device("TIM16", 0x40014400, 0x400);
205
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
206
index XXXXXXX..XXXXXXX 100644
207
--- a/hw/arm/Kconfig
208
+++ b/hw/arm/Kconfig
209
@@ -XXX,XX +XXX,XX @@ config STM32L4X5_SOC
210
select STM32L4X5_SYSCFG
211
select STM32L4X5_RCC
212
select STM32L4X5_GPIO
213
+ select STM32L4X5_USART
214
215
config XLNX_ZYNQMP_ARM
216
bool
36
--
217
--
37
2.20.1
218
2.34.1
38
219
39
220
diff view generated by jsdifflib
1
If we're using the capstone disassembler, disassembly of a run of
1
From: Arnaud Minier <arnaud.minier@telecom-paris.fr>
2
instructions more than 32 bytes long disassembles the wrong data for
2
3
instructions beyond the 32 byte mark:
3
Test:
4
4
- read/write from/to the usart registers
5
(qemu) xp /16x 0x100
5
- send/receive a character/string over the serial port
6
0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000
6
7
0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000
7
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
8
0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574
8
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
9
0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
(qemu) xp /16i 0x100
10
Message-id: 20240329174402.60382-6-arnaud.minier@telecom-paris.fr
11
0x00000100: 00000005 andeq r0, r0, r5
11
[PMM: fix checkpatch nits, remove commented out code]
12
0x00000104: 54410001 strbpl r0, [r1], #-1
13
0x00000108: 00000001 andeq r0, r0, r1
14
0x0000010c: 00001000 andeq r1, r0, r0
15
0x00000110: 00000000 andeq r0, r0, r0
16
0x00000114: 00000004 andeq r0, r0, r4
17
0x00000118: 54410002 strbpl r0, [r1], #-2
18
0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
19
0x00000120: 54410001 strbpl r0, [r1], #-1
20
0x00000124: 00000001 andeq r0, r0, r1
21
0x00000128: 00001000 andeq r1, r0, r0
22
0x0000012c: 00000000 andeq r0, r0, r0
23
0x00000130: 00000004 andeq r0, r0, r4
24
0x00000134: 54410002 strbpl r0, [r1], #-2
25
0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
26
0x0000013c: 00000000 andeq r0, r0, r0
27
28
Here the disassembly of 0x120..0x13f is using the data that is in
29
0x104..0x123.
30
31
This is caused by passing the wrong value to the read_memory_func().
32
The intention is that at this point in the loop the 'cap_buf' buffer
33
already contains 'csize' bytes of data for the instruction at guest
34
addr 'pc', and we want to read in an extra 'tsize' bytes. Those
35
extra bytes are therefore at 'pc + csize', not 'pc'. On the first
36
time through the loop 'csize' happens to be zero, so the initial read
37
of 32 bytes into cap_buf is correct and as long as the disassembly
38
never needs to read more data we return the correct information.
39
40
Use the correct guest address in the call to read_memory_func().
41
42
Cc: qemu-stable@nongnu.org
43
Fixes: https://bugs.launchpad.net/qemu/+bug/1900779
44
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
45
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
46
Message-id: 20201022132445.25039-1-peter.maydell@linaro.org
47
---
13
---
48
disas/capstone.c | 2 +-
14
tests/qtest/stm32l4x5_usart-test.c | 315 +++++++++++++++++++++++++++++
49
1 file changed, 1 insertion(+), 1 deletion(-)
15
tests/qtest/meson.build | 4 +-
50
16
2 files changed, 318 insertions(+), 1 deletion(-)
51
diff --git a/disas/capstone.c b/disas/capstone.c
17
create mode 100644 tests/qtest/stm32l4x5_usart-test.c
18
19
diff --git a/tests/qtest/stm32l4x5_usart-test.c b/tests/qtest/stm32l4x5_usart-test.c
20
new file mode 100644
21
index XXXXXXX..XXXXXXX
22
--- /dev/null
23
+++ b/tests/qtest/stm32l4x5_usart-test.c
24
@@ -XXX,XX +XXX,XX @@
25
+/*
26
+ * QTest testcase for STML4X5_USART
27
+ *
28
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
29
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
30
+ *
31
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
32
+ * See the COPYING file in the top-level directory.
33
+ */
34
+
35
+#include "qemu/osdep.h"
36
+#include "libqtest.h"
37
+#include "hw/misc/stm32l4x5_rcc_internals.h"
38
+#include "hw/registerfields.h"
39
+
40
+#define RCC_BASE_ADDR 0x40021000
41
+/* Use USART 1 ADDR, assume the others work the same */
42
+#define USART1_BASE_ADDR 0x40013800
43
+
44
+/* See stm32l4x5_usart for definitions */
45
+REG32(CR1, 0x00)
46
+ FIELD(CR1, M1, 28, 1)
47
+ FIELD(CR1, OVER8, 15, 1)
48
+ FIELD(CR1, M0, 12, 1)
49
+ FIELD(CR1, PCE, 10, 1)
50
+ FIELD(CR1, TXEIE, 7, 1)
51
+ FIELD(CR1, RXNEIE, 5, 1)
52
+ FIELD(CR1, TE, 3, 1)
53
+ FIELD(CR1, RE, 2, 1)
54
+ FIELD(CR1, UE, 0, 1)
55
+REG32(CR2, 0x04)
56
+REG32(CR3, 0x08)
57
+ FIELD(CR3, OVRDIS, 12, 1)
58
+REG32(BRR, 0x0C)
59
+REG32(GTPR, 0x10)
60
+REG32(RTOR, 0x14)
61
+REG32(RQR, 0x18)
62
+REG32(ISR, 0x1C)
63
+ FIELD(ISR, TXE, 7, 1)
64
+ FIELD(ISR, RXNE, 5, 1)
65
+ FIELD(ISR, ORE, 3, 1)
66
+REG32(ICR, 0x20)
67
+REG32(RDR, 0x24)
68
+REG32(TDR, 0x28)
69
+
70
+#define NVIC_ISPR1 0XE000E204
71
+#define NVIC_ICPR1 0xE000E284
72
+#define USART1_IRQ 37
73
+
74
+static bool check_nvic_pending(QTestState *qts, unsigned int n)
75
+{
76
+ /* No USART interrupts are less than 32 */
77
+ assert(n > 32);
78
+ n -= 32;
79
+ return qtest_readl(qts, NVIC_ISPR1) & (1 << n);
80
+}
81
+
82
+static bool clear_nvic_pending(QTestState *qts, unsigned int n)
83
+{
84
+ /* No USART interrupts are less than 32 */
85
+ assert(n > 32);
86
+ n -= 32;
87
+ qtest_writel(qts, NVIC_ICPR1, (1 << n));
88
+ return true;
89
+}
90
+
91
+/*
92
+ * Wait indefinitely for the flag to be updated.
93
+ * If this is run on a slow CI runner,
94
+ * the meson harness will timeout after 10 minutes for us.
95
+ */
96
+static bool usart_wait_for_flag(QTestState *qts, uint32_t event_addr,
97
+ uint32_t flag)
98
+{
99
+ while (true) {
100
+ if ((qtest_readl(qts, event_addr) & flag)) {
101
+ return true;
102
+ }
103
+ g_usleep(1000);
104
+ }
105
+
106
+ return false;
107
+}
108
+
109
+static void usart_receive_string(QTestState *qts, int sock_fd, const char *in,
110
+ char *out)
111
+{
112
+ int i, in_len = strlen(in);
113
+
114
+ g_assert_true(send(sock_fd, in, in_len, 0) == in_len);
115
+ for (i = 0; i < in_len; i++) {
116
+ g_assert_true(usart_wait_for_flag(qts,
117
+ USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK));
118
+ out[i] = qtest_readl(qts, USART1_BASE_ADDR + A_RDR);
119
+ }
120
+ out[i] = '\0';
121
+}
122
+
123
+static void usart_send_string(QTestState *qts, const char *in)
124
+{
125
+ int i, in_len = strlen(in);
126
+
127
+ for (i = 0; i < in_len; i++) {
128
+ qtest_writel(qts, USART1_BASE_ADDR + A_TDR, in[i]);
129
+ g_assert_true(usart_wait_for_flag(qts,
130
+ USART1_BASE_ADDR + A_ISR, R_ISR_TXE_MASK));
131
+ }
132
+}
133
+
134
+/* Init the RCC clocks to run at 80 MHz */
135
+static void init_clocks(QTestState *qts)
136
+{
137
+ uint32_t value;
138
+
139
+ /* MSIRANGE can be set only when MSI is OFF or READY */
140
+ qtest_writel(qts, (RCC_BASE_ADDR + A_CR), R_CR_MSION_MASK);
141
+
142
+ /* Clocking from MSI, in case MSI was not the default source */
143
+ qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0);
144
+
145
+ /*
146
+ * Update PLL and set MSI as the source clock.
147
+ * PLLM = 1 --> 000
148
+ * PLLN = 40 --> 40
149
+ * PPLLR = 2 --> 00
150
+ * PLLDIV = unused, PLLP = unused (SAI3), PLLQ = unused (48M1)
151
+ * SRC = MSI --> 01
152
+ */
153
+ qtest_writel(qts, (RCC_BASE_ADDR + A_PLLCFGR), R_PLLCFGR_PLLREN_MASK |
154
+ (40 << R_PLLCFGR_PLLN_SHIFT) |
155
+ (0b01 << R_PLLCFGR_PLLSRC_SHIFT));
156
+
157
+ /* PLL activation */
158
+
159
+ value = qtest_readl(qts, (RCC_BASE_ADDR + A_CR));
160
+ qtest_writel(qts, (RCC_BASE_ADDR + A_CR), value | R_CR_PLLON_MASK);
161
+
162
+ /* RCC_CFGR is OK by defaut */
163
+ qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0);
164
+
165
+ /* CCIPR : no periph clock by default */
166
+ qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0);
167
+
168
+ /* Switches on the PLL clock source */
169
+ value = qtest_readl(qts, (RCC_BASE_ADDR + A_CFGR));
170
+ qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), (value & ~R_CFGR_SW_MASK) |
171
+ (0b11 << R_CFGR_SW_SHIFT));
172
+
173
+ /* Enable SYSCFG clock enabled */
174
+ qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR), R_APB2ENR_SYSCFGEN_MASK);
175
+
176
+ /* Enable the IO port B clock (See p.252) */
177
+ qtest_writel(qts, (RCC_BASE_ADDR + A_AHB2ENR), R_AHB2ENR_GPIOBEN_MASK);
178
+
179
+ /* Enable the clock for USART1 (cf p.259) */
180
+ /* We rewrite SYSCFGEN to not disable it */
181
+ qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR),
182
+ R_APB2ENR_SYSCFGEN_MASK | R_APB2ENR_USART1EN_MASK);
183
+
184
+ /* TODO: Enable usart via gpio */
185
+
186
+ /* Set PCLK as the clock for USART1(cf p.272) i.e. reset both bits */
187
+ qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0);
188
+
189
+ /* Reset USART1 (see p.249) */
190
+ qtest_writel(qts, (RCC_BASE_ADDR + A_APB2RSTR), 1 << 14);
191
+ qtest_writel(qts, (RCC_BASE_ADDR + A_APB2RSTR), 0);
192
+}
193
+
194
+static void init_uart(QTestState *qts)
195
+{
196
+ uint32_t cr1;
197
+
198
+ init_clocks(qts);
199
+
200
+ /*
201
+ * For 115200 bauds, see p.1349.
202
+ * The clock has a frequency of 80Mhz,
203
+ * for 115200, we have to put a divider of 695 = 0x2B7.
204
+ */
205
+ qtest_writel(qts, (USART1_BASE_ADDR + A_BRR), 0x2B7);
206
+
207
+ /*
208
+ * Set the oversampling by 16,
209
+ * disable the parity control and
210
+ * set the word length to 8. (cf p.1377)
211
+ */
212
+ cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1));
213
+ cr1 &= ~(R_CR1_M1_MASK | R_CR1_M0_MASK | R_CR1_OVER8_MASK | R_CR1_PCE_MASK);
214
+ qtest_writel(qts, (USART1_BASE_ADDR + A_CR1), cr1);
215
+
216
+ /* Enable the transmitter, the receiver and the USART. */
217
+ qtest_writel(qts, (USART1_BASE_ADDR + A_CR1),
218
+ R_CR1_UE_MASK | R_CR1_RE_MASK | R_CR1_TE_MASK);
219
+}
220
+
221
+static void test_write_read(void)
222
+{
223
+ QTestState *qts = qtest_init("-M b-l475e-iot01a");
224
+
225
+ /* Test that we can write and retrieve a value from the device */
226
+ qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 0xFFFFFFFF);
227
+ const uint32_t tdr = qtest_readl(qts, USART1_BASE_ADDR + A_TDR);
228
+ g_assert_cmpuint(tdr, ==, 0x000001FF);
229
+}
230
+
231
+static void test_receive_char(void)
232
+{
233
+ int sock_fd;
234
+ uint32_t cr1;
235
+ QTestState *qts = qtest_init_with_serial("-M b-l475e-iot01a", &sock_fd);
236
+
237
+ init_uart(qts);
238
+
239
+ /* Try without initializing IRQ */
240
+ g_assert_true(send(sock_fd, "a", 1, 0) == 1);
241
+ usart_wait_for_flag(qts, USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK);
242
+ g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), ==, 'a');
243
+ g_assert_false(check_nvic_pending(qts, USART1_IRQ));
244
+
245
+ /* Now with the IRQ */
246
+ cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1));
247
+ cr1 |= R_CR1_RXNEIE_MASK;
248
+ qtest_writel(qts, USART1_BASE_ADDR + A_CR1, cr1);
249
+ g_assert_true(send(sock_fd, "b", 1, 0) == 1);
250
+ usart_wait_for_flag(qts, USART1_BASE_ADDR + A_ISR, R_ISR_RXNE_MASK);
251
+ g_assert_cmphex(qtest_readl(qts, USART1_BASE_ADDR + A_RDR), ==, 'b');
252
+ g_assert_true(check_nvic_pending(qts, USART1_IRQ));
253
+ clear_nvic_pending(qts, USART1_IRQ);
254
+
255
+ close(sock_fd);
256
+
257
+ qtest_quit(qts);
258
+}
259
+
260
+static void test_send_char(void)
261
+{
262
+ int sock_fd;
263
+ char s[1];
264
+ uint32_t cr1;
265
+ QTestState *qts = qtest_init_with_serial("-M b-l475e-iot01a", &sock_fd);
266
+
267
+ init_uart(qts);
268
+
269
+ /* Try without initializing IRQ */
270
+ qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 'c');
271
+ g_assert_true(recv(sock_fd, s, 1, 0) == 1);
272
+ g_assert_cmphex(s[0], ==, 'c');
273
+ g_assert_false(check_nvic_pending(qts, USART1_IRQ));
274
+
275
+ /* Now with the IRQ */
276
+ cr1 = qtest_readl(qts, (USART1_BASE_ADDR + A_CR1));
277
+ cr1 |= R_CR1_TXEIE_MASK;
278
+ qtest_writel(qts, USART1_BASE_ADDR + A_CR1, cr1);
279
+ qtest_writel(qts, USART1_BASE_ADDR + A_TDR, 'd');
280
+ g_assert_true(recv(sock_fd, s, 1, 0) == 1);
281
+ g_assert_cmphex(s[0], ==, 'd');
282
+ g_assert_true(check_nvic_pending(qts, USART1_IRQ));
283
+ clear_nvic_pending(qts, USART1_IRQ);
284
+
285
+ close(sock_fd);
286
+
287
+ qtest_quit(qts);
288
+}
289
+
290
+static void test_receive_str(void)
291
+{
292
+ int sock_fd;
293
+ char s[10];
294
+ QTestState *qts = qtest_init_with_serial("-M b-l475e-iot01a", &sock_fd);
295
+
296
+ init_uart(qts);
297
+
298
+ usart_receive_string(qts, sock_fd, "hello", s);
299
+ g_assert_true(memcmp(s, "hello", 5) == 0);
300
+
301
+ close(sock_fd);
302
+
303
+ qtest_quit(qts);
304
+}
305
+
306
+static void test_send_str(void)
307
+{
308
+ int sock_fd;
309
+ char s[10];
310
+ QTestState *qts = qtest_init_with_serial("-M b-l475e-iot01a", &sock_fd);
311
+
312
+ init_uart(qts);
313
+
314
+ usart_send_string(qts, "world");
315
+ g_assert_true(recv(sock_fd, s, 10, 0) == 5);
316
+ g_assert_true(memcmp(s, "world", 5) == 0);
317
+
318
+ close(sock_fd);
319
+
320
+ qtest_quit(qts);
321
+}
322
+
323
+int main(int argc, char **argv)
324
+{
325
+ int ret;
326
+
327
+ g_test_init(&argc, &argv, NULL);
328
+ g_test_set_nonfatal_assertions();
329
+
330
+ qtest_add_func("stm32l4x5/usart/write_read", test_write_read);
331
+ qtest_add_func("stm32l4x5/usart/receive_char", test_receive_char);
332
+ qtest_add_func("stm32l4x5/usart/send_char", test_send_char);
333
+ qtest_add_func("stm32l4x5/usart/receive_str", test_receive_str);
334
+ qtest_add_func("stm32l4x5/usart/send_str", test_send_str);
335
+ ret = g_test_run();
336
+
337
+ return ret;
338
+}
339
+
340
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
52
index XXXXXXX..XXXXXXX 100644
341
index XXXXXXX..XXXXXXX 100644
53
--- a/disas/capstone.c
342
--- a/tests/qtest/meson.build
54
+++ b/disas/capstone.c
343
+++ b/tests/qtest/meson.build
55
@@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
344
@@ -XXX,XX +XXX,XX @@ slow_qtests = {
56
345
'npcm7xx_pwm-test': 300,
57
/* Make certain that we can make progress. */
346
'npcm7xx_watchdog_timer-test': 120,
58
assert(tsize != 0);
347
'qom-test' : 900,
59
- info->read_memory_func(pc, cap_buf + csize, tsize, info);
348
+ 'stm32l4x5_usart-test' : 600,
60
+ info->read_memory_func(pc + csize, cap_buf + csize, tsize, info);
349
'test-hmp' : 240,
61
csize += tsize;
350
'pxe-test': 610,
62
351
'prom-env-test': 360,
63
if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
352
@@ -XXX,XX +XXX,XX @@ qtests_stm32l4x5 = \
353
['stm32l4x5_exti-test',
354
'stm32l4x5_syscfg-test',
355
'stm32l4x5_rcc-test',
356
- 'stm32l4x5_gpio-test']
357
+ 'stm32l4x5_gpio-test',
358
+ 'stm32l4x5_usart-test']
359
360
qtests_arm = \
361
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
64
--
362
--
65
2.20.1
363
2.34.1
66
364
67
365
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