1 | Small pile of bug fixes for rc1. I've included my patches to get | 1 | Hi; here's a relatively small target-arm queue, pretty much all |
---|---|---|---|
2 | our docs building with Sphinx 3, just for convenience... | 2 | bug fixes. (There are a few non-arm patches that I've thrown in |
3 | there too for my convenience :-)) | ||
3 | 4 | ||
5 | thanks | ||
4 | -- PMM | 6 | -- PMM |
5 | 7 | ||
6 | The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96: | 8 | The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1: |
7 | 9 | ||
8 | Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000) | 10 | Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into staging (2023-05-11 11:44:23 +0100) |
9 | 11 | ||
10 | are available in the Git repository at: | 12 | are available in the Git repository at: |
11 | 13 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230512 |
13 | 15 | ||
14 | for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a: | 16 | for you to fetch changes up to 478dccbb99db0bf8f00537dd0b4d0de88d5cb537: |
15 | 17 | ||
16 | tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000) | 18 | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check (2023-05-12 16:01:25 +0100) |
17 | 19 | ||
18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
19 | target-arm queue: | 21 | target-arm queue: |
20 | * target/arm: Fix Neon emulation bugs on big-endian hosts | 22 | * More refactoring of files into tcg/ |
21 | * target/arm: fix handling of HCR.FB | 23 | * Don't allow stage 2 page table walks to downgrade to NS |
22 | * target/arm: fix LORID_EL1 access check | 24 | * Fix handling of SW and NSW bits for stage 2 walks |
23 | * disas/capstone: Fix monitor disassembly of >32 bytes | 25 | * MAINTAINERS: Update Akihiko Odaki's email address |
24 | * hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) | 26 | * ui: Fix pixel colour channel order for PNG screenshots |
25 | * hw/arm/boot: fix SVE for EL3 direct kernel boot | 27 | * docs: Remove unused weirdly-named cross-reference targets |
26 | * hw/display/omap_lcdc: Fix potential NULL pointer dereference | 28 | * hw/mips/malta: Fix minor dead code issue |
27 | * hw/display/exynos4210_fimd: Fix potential NULL pointer dereference | 29 | * Fixes for the "allow CONFIG_TCG=n" changes |
28 | * target/arm: Get correct MMU index for other-security-state | 30 | * tests/qtest: Don't run cdrom boot tests if no accelerator is present |
29 | * configure: Test that gio libs from pkg-config work | 31 | * target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check |
30 | * hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work | ||
31 | * docs: Fix building with Sphinx 3 | ||
32 | * tests/qtest/npcm7xx_rng-test: Disable randomness tests | ||
33 | 32 | ||
34 | ---------------------------------------------------------------- | 33 | ---------------------------------------------------------------- |
35 | AlexChen (2): | 34 | Akihiko Odaki (1): |
36 | hw/display/omap_lcdc: Fix potential NULL pointer dereference | 35 | MAINTAINERS: Update Akihiko Odaki's email address |
37 | hw/display/exynos4210_fimd: Fix potential NULL pointer dereference | ||
38 | 36 | ||
39 | Peter Maydell (9): | 37 | Fabiano Rosas (3): |
40 | target/arm: Fix float16 pairwise Neon ops on big-endian hosts | 38 | target/arm: Select SEMIHOSTING when using TCG |
41 | target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts | 39 | target/arm: Select CONFIG_ARM_V7M when TCG is enabled |
42 | disas/capstone: Fix monitor disassembly of >32 bytes | 40 | tests/qtest: Don't run cdrom boot tests if no accelerator is present |
43 | target/arm: Get correct MMU index for other-security-state | ||
44 | configure: Test that gio libs from pkg-config work | ||
45 | hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work | ||
46 | scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments | ||
47 | qemu-option-trace.rst.inc: Don't use option:: markup | ||
48 | tests/qtest/npcm7xx_rng-test: Disable randomness tests | ||
49 | 41 | ||
50 | Philippe Mathieu-Daudé (1): | 42 | Peter Maydell (6): |
51 | hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) | 43 | target/arm: Don't allow stage 2 page table walks to downgrade to NS |
44 | target/arm: Fix handling of SW and NSW bits for stage 2 walks | ||
45 | ui: Fix pixel colour channel order for PNG screenshots | ||
46 | docs: Remove unused weirdly-named cross-reference targets | ||
47 | hw/mips/malta: Fix minor dead code issue | ||
48 | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check | ||
52 | 49 | ||
53 | Richard Henderson (11): | 50 | Richard Henderson (2): |
54 | target/arm: Introduce neon_full_reg_offset | 51 | target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ |
55 | target/arm: Move neon_element_offset to translate.c | 52 | target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ |
56 | target/arm: Use neon_element_offset in neon_load/store_reg | ||
57 | target/arm: Use neon_element_offset in vfp_reg_offset | ||
58 | target/arm: Add read/write_neon_element32 | ||
59 | target/arm: Expand read/write_neon_element32 to all MemOp | ||
60 | target/arm: Rename neon_load_reg32 to vfp_load_reg32 | ||
61 | target/arm: Add read/write_neon_element64 | ||
62 | target/arm: Rename neon_load_reg64 to vfp_load_reg64 | ||
63 | target/arm: Simplify do_long_3d and do_2scalar_long | ||
64 | target/arm: Improve do_prewiden_3d | ||
65 | 53 | ||
66 | Rémi Denis-Courmont (3): | 54 | MAINTAINERS | 4 +- |
67 | target/arm: fix handling of HCR.FB | 55 | docs/system/devices/igb.rst | 2 +- |
68 | target/arm: fix LORID_EL1 access check | 56 | docs/system/devices/ivshmem.rst | 2 - |
69 | hw/arm/boot: fix SVE for EL3 direct kernel boot | 57 | docs/system/devices/net.rst | 2 +- |
70 | 58 | docs/system/devices/usb.rst | 2 - | |
71 | docs/qemu-option-trace.rst.inc | 6 +- | 59 | docs/system/keys.rst | 2 +- |
72 | configure | 10 +- | 60 | docs/system/linuxboot.rst | 2 +- |
73 | include/hw/intc/arm_gicv3_common.h | 1 - | 61 | docs/system/target-i386.rst | 4 -- |
74 | disas/capstone.c | 2 +- | 62 | target/arm/helper.h | 8 +-- |
75 | hw/arm/boot.c | 3 + | 63 | target/arm/internals.h | 12 +++- |
76 | hw/arm/smmuv3.c | 3 +- | 64 | target/arm/{ => tcg}/arm_ldst.h | 0 |
77 | hw/display/exynos4210_fimd.c | 4 +- | 65 | target/arm/{ => tcg}/helper-a64.h | 0 |
78 | hw/display/omap_lcdc.c | 10 +- | 66 | target/arm/{ => tcg}/helper-mve.h | 0 |
79 | hw/intc/arm_gicv3_cpuif.c | 5 +- | 67 | target/arm/{ => tcg}/helper-sme.h | 0 |
80 | target/arm/helper.c | 24 +- | 68 | target/arm/{ => tcg}/helper-sve.h | 0 |
81 | target/arm/m_helper.c | 3 +- | 69 | target/arm/{ => tcg}/sve_ldst_internal.h | 0 |
82 | target/arm/translate.c | 153 +++++++++--- | 70 | target/arm/{ => tcg}/translate-a32.h | 0 |
83 | target/arm/vec_helper.c | 12 +- | 71 | hw/mips/malta.c | 5 +- |
84 | tests/qtest/npcm7xx_rng-test.c | 14 +- | 72 | target/arm/gdbstub64.c | 2 +- |
85 | scripts/kernel-doc | 18 +- | 73 | target/arm/helper.c | 15 ++++- |
86 | target/arm/translate-neon.c.inc | 472 ++++++++++++++++++++----------------- | 74 | target/arm/ptw.c | 95 +++++++++++++++++++------------- |
87 | target/arm/translate-vfp.c.inc | 341 +++++++++++---------------- | 75 | target/arm/tcg/pauth_helper.c | 6 +- |
88 | 17 files changed, 588 insertions(+), 493 deletions(-) | 76 | tests/qtest/cdrom-test.c | 10 ++++ |
89 | 77 | ui/console.c | 4 +- | |
78 | target/arm/Kconfig | 9 +-- | ||
79 | 25 files changed, 109 insertions(+), 77 deletions(-) | ||
80 | rename target/arm/{ => tcg}/arm_ldst.h (100%) | ||
81 | rename target/arm/{ => tcg}/helper-a64.h (100%) | ||
82 | rename target/arm/{ => tcg}/helper-mve.h (100%) | ||
83 | rename target/arm/{ => tcg}/helper-sme.h (100%) | ||
84 | rename target/arm/{ => tcg}/helper-sve.h (100%) | ||
85 | rename target/arm/{ => tcg}/sve_ldst_internal.h (100%) | ||
86 | rename target/arm/{ => tcg}/translate-a32.h (100%) | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | This function makes it clear that we're talking about the whole | ||
4 | register, and not the 32-bit piece at index 0. This fixes a bug | ||
5 | when running on a big-endian host. | ||
6 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20201030022618.785675-2-richard.henderson@linaro.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/translate.c | 8 ++++++ | ||
13 | target/arm/translate-neon.c.inc | 44 ++++++++++++++++----------------- | ||
14 | target/arm/translate-vfp.c.inc | 2 +- | ||
15 | 3 files changed, 31 insertions(+), 23 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/translate.c | ||
20 | +++ b/target/arm/translate.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm) | ||
22 | unallocated_encoding(s); | ||
23 | } | ||
24 | |||
25 | +/* | ||
26 | + * Return the offset of a "full" NEON Dreg. | ||
27 | + */ | ||
28 | +static long neon_full_reg_offset(unsigned reg) | ||
29 | +{ | ||
30 | + return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | ||
31 | +} | ||
32 | + | ||
33 | static inline long vfp_reg_offset(bool dp, unsigned reg) | ||
34 | { | ||
35 | if (dp) { | ||
36 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/translate-neon.c.inc | ||
39 | +++ b/target/arm/translate-neon.c.inc | ||
40 | @@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size) | ||
41 | ofs ^= 8 - element_size; | ||
42 | } | ||
43 | #endif | ||
44 | - return neon_reg_offset(reg, 0) + ofs; | ||
45 | + return neon_full_reg_offset(reg) + ofs; | ||
46 | } | ||
47 | |||
48 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | ||
49 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) | ||
50 | * We cannot write 16 bytes at once because the | ||
51 | * destination is unaligned. | ||
52 | */ | ||
53 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | ||
54 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), | ||
55 | 8, 8, tmp); | ||
56 | - tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), | ||
57 | - neon_reg_offset(vd, 0), 8, 8); | ||
58 | + tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1), | ||
59 | + neon_full_reg_offset(vd), 8, 8); | ||
60 | } else { | ||
61 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | ||
62 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), | ||
63 | vec_size, vec_size, tmp); | ||
64 | } | ||
65 | tcg_gen_addi_i32(addr, addr, 1 << size); | ||
66 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) | ||
67 | static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) | ||
68 | { | ||
69 | int vec_size = a->q ? 16 : 8; | ||
70 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
71 | - int rn_ofs = neon_reg_offset(a->vn, 0); | ||
72 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
73 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
74 | + int rn_ofs = neon_full_reg_offset(a->vn); | ||
75 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
76 | |||
77 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
78 | return false; | ||
79 | @@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) | ||
80 | { | ||
81 | /* Handle a 2-reg-shift insn which can be vectorized. */ | ||
82 | int vec_size = a->q ? 16 : 8; | ||
83 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
84 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
85 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
86 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
87 | |||
88 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
89 | return false; | ||
90 | @@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, | ||
91 | { | ||
92 | /* FP operations in 2-reg-and-shift group */ | ||
93 | int vec_size = a->q ? 16 : 8; | ||
94 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
95 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
96 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
97 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
98 | TCGv_ptr fpst; | ||
99 | |||
100 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
102 | return true; | ||
103 | } | ||
104 | |||
105 | - reg_ofs = neon_reg_offset(a->vd, 0); | ||
106 | + reg_ofs = neon_full_reg_offset(a->vd); | ||
107 | vec_size = a->q ? 16 : 8; | ||
108 | imm = asimd_imm_const(a->imm, a->cmode, a->op); | ||
109 | |||
110 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) | ||
111 | return true; | ||
112 | } | ||
113 | |||
114 | - tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), | ||
115 | - neon_reg_offset(a->vn, 0), | ||
116 | - neon_reg_offset(a->vm, 0), | ||
117 | + tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd), | ||
118 | + neon_full_reg_offset(a->vn), | ||
119 | + neon_full_reg_offset(a->vm), | ||
120 | 16, 16, 0, fn_gvec); | ||
121 | return true; | ||
122 | } | ||
123 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, | ||
124 | { | ||
125 | /* Two registers and a scalar, using gvec */ | ||
126 | int vec_size = a->q ? 16 : 8; | ||
127 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
128 | - int rn_ofs = neon_reg_offset(a->vn, 0); | ||
129 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
130 | + int rn_ofs = neon_full_reg_offset(a->vn); | ||
131 | int rm_ofs; | ||
132 | int idx; | ||
133 | TCGv_ptr fpstatus; | ||
134 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, | ||
135 | /* a->vm is M:Vm, which encodes both register and index */ | ||
136 | idx = extract32(a->vm, a->size + 2, 2); | ||
137 | a->vm = extract32(a->vm, 0, a->size + 2); | ||
138 | - rm_ofs = neon_reg_offset(a->vm, 0); | ||
139 | + rm_ofs = neon_full_reg_offset(a->vm); | ||
140 | |||
141 | fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD); | ||
142 | tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus, | ||
143 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
144 | return true; | ||
145 | } | ||
146 | |||
147 | - tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), | ||
148 | + tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd), | ||
149 | neon_element_offset(a->vm, a->index, a->size), | ||
150 | a->q ? 16 : 8, a->q ? 16 : 8); | ||
151 | return true; | ||
152 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
153 | static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) | ||
154 | { | ||
155 | int vec_size = a->q ? 16 : 8; | ||
156 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
157 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
158 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
159 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
160 | |||
161 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
162 | return false; | ||
163 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/target/arm/translate-vfp.c.inc | ||
166 | +++ b/target/arm/translate-vfp.c.inc | ||
167 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
168 | } | ||
169 | |||
170 | tmp = load_reg(s, a->rt); | ||
171 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), | ||
172 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn), | ||
173 | vec_size, vec_size, tmp); | ||
174 | tcg_temp_free_i32(tmp); | ||
175 | |||
176 | -- | ||
177 | 2.20.1 | ||
178 | |||
179 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Model these off the aa64 read/write_vec_element functions. | 3 | These files got missed when populating tcg/. |
4 | Use it within translate-neon.c.inc. The new functions do | 4 | Because they are included with "", no change to the users required. |
5 | not allocate or free temps, so this rearranges the calling | ||
6 | code a bit. | ||
7 | 5 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20201030022618.785675-6-richard.henderson@linaro.org | 7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Message-id: 20230504110412.1892411-2-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | target/arm/translate.c | 26 ++++ | 12 | target/arm/{ => tcg}/arm_ldst.h | 0 |
14 | target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------ | 13 | target/arm/{ => tcg}/sve_ldst_internal.h | 0 |
15 | 2 files changed, 183 insertions(+), 99 deletions(-) | 14 | target/arm/{ => tcg}/translate-a32.h | 0 |
15 | 3 files changed, 0 insertions(+), 0 deletions(-) | ||
16 | rename target/arm/{ => tcg}/arm_ldst.h (100%) | ||
17 | rename target/arm/{ => tcg}/sve_ldst_internal.h (100%) | ||
18 | rename target/arm/{ => tcg}/translate-a32.h (100%) | ||
16 | 19 | ||
17 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 20 | diff --git a/target/arm/arm_ldst.h b/target/arm/tcg/arm_ldst.h |
18 | index XXXXXXX..XXXXXXX 100644 | 21 | similarity index 100% |
19 | --- a/target/arm/translate.c | 22 | rename from target/arm/arm_ldst.h |
20 | +++ b/target/arm/translate.c | 23 | rename to target/arm/tcg/arm_ldst.h |
21 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg) | 24 | diff --git a/target/arm/sve_ldst_internal.h b/target/arm/tcg/sve_ldst_internal.h |
22 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | 25 | similarity index 100% |
23 | } | 26 | rename from target/arm/sve_ldst_internal.h |
24 | 27 | rename to target/arm/tcg/sve_ldst_internal.h | |
25 | +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) | 28 | diff --git a/target/arm/translate-a32.h b/target/arm/tcg/translate-a32.h |
26 | +{ | 29 | similarity index 100% |
27 | + long off = neon_element_offset(reg, ele, size); | 30 | rename from target/arm/translate-a32.h |
28 | + | 31 | rename to target/arm/tcg/translate-a32.h |
29 | + switch (size) { | ||
30 | + case MO_32: | ||
31 | + tcg_gen_ld_i32(dest, cpu_env, off); | ||
32 | + break; | ||
33 | + default: | ||
34 | + g_assert_not_reached(); | ||
35 | + } | ||
36 | +} | ||
37 | + | ||
38 | +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size) | ||
39 | +{ | ||
40 | + long off = neon_element_offset(reg, ele, size); | ||
41 | + | ||
42 | + switch (size) { | ||
43 | + case MO_32: | ||
44 | + tcg_gen_st_i32(src, cpu_env, off); | ||
45 | + break; | ||
46 | + default: | ||
47 | + g_assert_not_reached(); | ||
48 | + } | ||
49 | +} | ||
50 | + | ||
51 | static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
52 | { | ||
53 | TCGv_ptr ret = tcg_temp_new_ptr(); | ||
54 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/arm/translate-neon.c.inc | ||
57 | +++ b/target/arm/translate-neon.c.inc | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn) | ||
59 | * early. Since Q is 0 there are always just two passes, so instead | ||
60 | * of a complicated loop over each pass we just unroll. | ||
61 | */ | ||
62 | - tmp = neon_load_reg(a->vn, 0); | ||
63 | - tmp2 = neon_load_reg(a->vn, 1); | ||
64 | + tmp = tcg_temp_new_i32(); | ||
65 | + tmp2 = tcg_temp_new_i32(); | ||
66 | + tmp3 = tcg_temp_new_i32(); | ||
67 | + | ||
68 | + read_neon_element32(tmp, a->vn, 0, MO_32); | ||
69 | + read_neon_element32(tmp2, a->vn, 1, MO_32); | ||
70 | fn(tmp, tmp, tmp2); | ||
71 | - tcg_temp_free_i32(tmp2); | ||
72 | |||
73 | - tmp3 = neon_load_reg(a->vm, 0); | ||
74 | - tmp2 = neon_load_reg(a->vm, 1); | ||
75 | + read_neon_element32(tmp3, a->vm, 0, MO_32); | ||
76 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
77 | fn(tmp3, tmp3, tmp2); | ||
78 | - tcg_temp_free_i32(tmp2); | ||
79 | |||
80 | - neon_store_reg(a->vd, 0, tmp); | ||
81 | - neon_store_reg(a->vd, 1, tmp3); | ||
82 | + write_neon_element32(tmp, a->vd, 0, MO_32); | ||
83 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
84 | + | ||
85 | + tcg_temp_free_i32(tmp); | ||
86 | + tcg_temp_free_i32(tmp2); | ||
87 | + tcg_temp_free_i32(tmp3); | ||
88 | return true; | ||
89 | } | ||
90 | |||
91 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, | ||
92 | * 2-reg-and-shift operations, size < 3 case, where the | ||
93 | * helper needs to be passed cpu_env. | ||
94 | */ | ||
95 | - TCGv_i32 constimm; | ||
96 | + TCGv_i32 constimm, tmp; | ||
97 | int pass; | ||
98 | |||
99 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
100 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, | ||
101 | * by immediate using the variable shift operations. | ||
102 | */ | ||
103 | constimm = tcg_const_i32(dup_const(a->size, a->shift)); | ||
104 | + tmp = tcg_temp_new_i32(); | ||
105 | |||
106 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
107 | - TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
108 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
109 | fn(tmp, cpu_env, tmp, constimm); | ||
110 | - neon_store_reg(a->vd, pass, tmp); | ||
111 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
112 | } | ||
113 | + tcg_temp_free_i32(tmp); | ||
114 | tcg_temp_free_i32(constimm); | ||
115 | return true; | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, | ||
118 | constimm = tcg_const_i64(-a->shift); | ||
119 | rm1 = tcg_temp_new_i64(); | ||
120 | rm2 = tcg_temp_new_i64(); | ||
121 | + rd = tcg_temp_new_i32(); | ||
122 | |||
123 | /* Load both inputs first to avoid potential overwrite if rm == rd */ | ||
124 | neon_load_reg64(rm1, a->vm); | ||
125 | neon_load_reg64(rm2, a->vm + 1); | ||
126 | |||
127 | shiftfn(rm1, rm1, constimm); | ||
128 | - rd = tcg_temp_new_i32(); | ||
129 | narrowfn(rd, cpu_env, rm1); | ||
130 | - neon_store_reg(a->vd, 0, rd); | ||
131 | + write_neon_element32(rd, a->vd, 0, MO_32); | ||
132 | |||
133 | shiftfn(rm2, rm2, constimm); | ||
134 | - rd = tcg_temp_new_i32(); | ||
135 | narrowfn(rd, cpu_env, rm2); | ||
136 | - neon_store_reg(a->vd, 1, rd); | ||
137 | + write_neon_element32(rd, a->vd, 1, MO_32); | ||
138 | |||
139 | + tcg_temp_free_i32(rd); | ||
140 | tcg_temp_free_i64(rm1); | ||
141 | tcg_temp_free_i64(rm2); | ||
142 | tcg_temp_free_i64(constimm); | ||
143 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
144 | constimm = tcg_const_i32(imm); | ||
145 | |||
146 | /* Load all inputs first to avoid potential overwrite */ | ||
147 | - rm1 = neon_load_reg(a->vm, 0); | ||
148 | - rm2 = neon_load_reg(a->vm, 1); | ||
149 | - rm3 = neon_load_reg(a->vm + 1, 0); | ||
150 | - rm4 = neon_load_reg(a->vm + 1, 1); | ||
151 | + rm1 = tcg_temp_new_i32(); | ||
152 | + rm2 = tcg_temp_new_i32(); | ||
153 | + rm3 = tcg_temp_new_i32(); | ||
154 | + rm4 = tcg_temp_new_i32(); | ||
155 | + read_neon_element32(rm1, a->vm, 0, MO_32); | ||
156 | + read_neon_element32(rm2, a->vm, 1, MO_32); | ||
157 | + read_neon_element32(rm3, a->vm, 2, MO_32); | ||
158 | + read_neon_element32(rm4, a->vm, 3, MO_32); | ||
159 | rtmp = tcg_temp_new_i64(); | ||
160 | |||
161 | shiftfn(rm1, rm1, constimm); | ||
162 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
163 | tcg_temp_free_i32(rm2); | ||
164 | |||
165 | narrowfn(rm1, cpu_env, rtmp); | ||
166 | - neon_store_reg(a->vd, 0, rm1); | ||
167 | + write_neon_element32(rm1, a->vd, 0, MO_32); | ||
168 | + tcg_temp_free_i32(rm1); | ||
169 | |||
170 | shiftfn(rm3, rm3, constimm); | ||
171 | shiftfn(rm4, rm4, constimm); | ||
172 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
173 | |||
174 | narrowfn(rm3, cpu_env, rtmp); | ||
175 | tcg_temp_free_i64(rtmp); | ||
176 | - neon_store_reg(a->vd, 1, rm3); | ||
177 | + write_neon_element32(rm3, a->vd, 1, MO_32); | ||
178 | + tcg_temp_free_i32(rm3); | ||
179 | return true; | ||
180 | } | ||
181 | |||
182 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
183 | widen_mask = dup_const(a->size + 1, widen_mask); | ||
184 | } | ||
185 | |||
186 | - rm0 = neon_load_reg(a->vm, 0); | ||
187 | - rm1 = neon_load_reg(a->vm, 1); | ||
188 | + rm0 = tcg_temp_new_i32(); | ||
189 | + rm1 = tcg_temp_new_i32(); | ||
190 | + read_neon_element32(rm0, a->vm, 0, MO_32); | ||
191 | + read_neon_element32(rm1, a->vm, 1, MO_32); | ||
192 | tmp = tcg_temp_new_i64(); | ||
193 | |||
194 | widenfn(tmp, rm0); | ||
195 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
196 | if (src1_wide) { | ||
197 | neon_load_reg64(rn0_64, a->vn); | ||
198 | } else { | ||
199 | - TCGv_i32 tmp = neon_load_reg(a->vn, 0); | ||
200 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
201 | + read_neon_element32(tmp, a->vn, 0, MO_32); | ||
202 | widenfn(rn0_64, tmp); | ||
203 | tcg_temp_free_i32(tmp); | ||
204 | } | ||
205 | - rm = neon_load_reg(a->vm, 0); | ||
206 | + rm = tcg_temp_new_i32(); | ||
207 | + read_neon_element32(rm, a->vm, 0, MO_32); | ||
208 | |||
209 | widenfn(rm_64, rm); | ||
210 | tcg_temp_free_i32(rm); | ||
211 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
212 | if (src1_wide) { | ||
213 | neon_load_reg64(rn1_64, a->vn + 1); | ||
214 | } else { | ||
215 | - TCGv_i32 tmp = neon_load_reg(a->vn, 1); | ||
216 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
217 | + read_neon_element32(tmp, a->vn, 1, MO_32); | ||
218 | widenfn(rn1_64, tmp); | ||
219 | tcg_temp_free_i32(tmp); | ||
220 | } | ||
221 | - rm = neon_load_reg(a->vm, 1); | ||
222 | + rm = tcg_temp_new_i32(); | ||
223 | + read_neon_element32(rm, a->vm, 1, MO_32); | ||
224 | |||
225 | neon_store_reg64(rn0_64, a->vd); | ||
226 | |||
227 | @@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | ||
228 | |||
229 | narrowfn(rd1, rn_64); | ||
230 | |||
231 | - neon_store_reg(a->vd, 0, rd0); | ||
232 | - neon_store_reg(a->vd, 1, rd1); | ||
233 | + write_neon_element32(rd0, a->vd, 0, MO_32); | ||
234 | + write_neon_element32(rd1, a->vd, 1, MO_32); | ||
235 | |||
236 | + tcg_temp_free_i32(rd0); | ||
237 | + tcg_temp_free_i32(rd1); | ||
238 | tcg_temp_free_i64(rn_64); | ||
239 | tcg_temp_free_i64(rm_64); | ||
240 | |||
241 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
242 | rd0 = tcg_temp_new_i64(); | ||
243 | rd1 = tcg_temp_new_i64(); | ||
244 | |||
245 | - rn = neon_load_reg(a->vn, 0); | ||
246 | - rm = neon_load_reg(a->vm, 0); | ||
247 | + rn = tcg_temp_new_i32(); | ||
248 | + rm = tcg_temp_new_i32(); | ||
249 | + read_neon_element32(rn, a->vn, 0, MO_32); | ||
250 | + read_neon_element32(rm, a->vm, 0, MO_32); | ||
251 | opfn(rd0, rn, rm); | ||
252 | - tcg_temp_free_i32(rn); | ||
253 | - tcg_temp_free_i32(rm); | ||
254 | |||
255 | - rn = neon_load_reg(a->vn, 1); | ||
256 | - rm = neon_load_reg(a->vm, 1); | ||
257 | + read_neon_element32(rn, a->vn, 1, MO_32); | ||
258 | + read_neon_element32(rm, a->vm, 1, MO_32); | ||
259 | opfn(rd1, rn, rm); | ||
260 | tcg_temp_free_i32(rn); | ||
261 | tcg_temp_free_i32(rm); | ||
262 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var) | ||
263 | |||
264 | static inline TCGv_i32 neon_get_scalar(int size, int reg) | ||
265 | { | ||
266 | - TCGv_i32 tmp; | ||
267 | - if (size == 1) { | ||
268 | - tmp = neon_load_reg(reg & 7, reg >> 4); | ||
269 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
270 | + if (size == MO_16) { | ||
271 | + read_neon_element32(tmp, reg & 7, reg >> 4, MO_32); | ||
272 | if (reg & 8) { | ||
273 | gen_neon_dup_high16(tmp); | ||
274 | } else { | ||
275 | gen_neon_dup_low16(tmp); | ||
276 | } | ||
277 | } else { | ||
278 | - tmp = neon_load_reg(reg & 15, reg >> 4); | ||
279 | + read_neon_element32(tmp, reg & 15, reg >> 4, MO_32); | ||
280 | } | ||
281 | return tmp; | ||
282 | } | ||
283 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
284 | * perform an accumulation operation of that result into the | ||
285 | * destination. | ||
286 | */ | ||
287 | - TCGv_i32 scalar; | ||
288 | + TCGv_i32 scalar, tmp; | ||
289 | int pass; | ||
290 | |||
291 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
292 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
293 | } | ||
294 | |||
295 | scalar = neon_get_scalar(a->size, a->vm); | ||
296 | + tmp = tcg_temp_new_i32(); | ||
297 | |||
298 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
299 | - TCGv_i32 tmp = neon_load_reg(a->vn, pass); | ||
300 | + read_neon_element32(tmp, a->vn, pass, MO_32); | ||
301 | opfn(tmp, tmp, scalar); | ||
302 | if (accfn) { | ||
303 | - TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
304 | + TCGv_i32 rd = tcg_temp_new_i32(); | ||
305 | + read_neon_element32(rd, a->vd, pass, MO_32); | ||
306 | accfn(tmp, rd, tmp); | ||
307 | tcg_temp_free_i32(rd); | ||
308 | } | ||
309 | - neon_store_reg(a->vd, pass, tmp); | ||
310 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
311 | } | ||
312 | + tcg_temp_free_i32(tmp); | ||
313 | tcg_temp_free_i32(scalar); | ||
314 | return true; | ||
315 | } | ||
316 | @@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | ||
317 | * performs a kind of fused op-then-accumulate using a helper | ||
318 | * function that takes all of rd, rn and the scalar at once. | ||
319 | */ | ||
320 | - TCGv_i32 scalar; | ||
321 | + TCGv_i32 scalar, rn, rd; | ||
322 | int pass; | ||
323 | |||
324 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
325 | @@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | ||
326 | } | ||
327 | |||
328 | scalar = neon_get_scalar(a->size, a->vm); | ||
329 | + rn = tcg_temp_new_i32(); | ||
330 | + rd = tcg_temp_new_i32(); | ||
331 | |||
332 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
333 | - TCGv_i32 rn = neon_load_reg(a->vn, pass); | ||
334 | - TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
335 | + read_neon_element32(rn, a->vn, pass, MO_32); | ||
336 | + read_neon_element32(rd, a->vd, pass, MO_32); | ||
337 | opfn(rd, cpu_env, rn, scalar, rd); | ||
338 | - tcg_temp_free_i32(rn); | ||
339 | - neon_store_reg(a->vd, pass, rd); | ||
340 | + write_neon_element32(rd, a->vd, pass, MO_32); | ||
341 | } | ||
342 | + tcg_temp_free_i32(rn); | ||
343 | + tcg_temp_free_i32(rd); | ||
344 | tcg_temp_free_i32(scalar); | ||
345 | |||
346 | return true; | ||
347 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
348 | scalar = neon_get_scalar(a->size, a->vm); | ||
349 | |||
350 | /* Load all inputs before writing any outputs, in case of overlap */ | ||
351 | - rn = neon_load_reg(a->vn, 0); | ||
352 | + rn = tcg_temp_new_i32(); | ||
353 | + read_neon_element32(rn, a->vn, 0, MO_32); | ||
354 | rn0_64 = tcg_temp_new_i64(); | ||
355 | opfn(rn0_64, rn, scalar); | ||
356 | - tcg_temp_free_i32(rn); | ||
357 | |||
358 | - rn = neon_load_reg(a->vn, 1); | ||
359 | + read_neon_element32(rn, a->vn, 1, MO_32); | ||
360 | rn1_64 = tcg_temp_new_i64(); | ||
361 | opfn(rn1_64, rn, scalar); | ||
362 | tcg_temp_free_i32(rn); | ||
363 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
364 | return false; | ||
365 | } | ||
366 | n <<= 3; | ||
367 | + tmp = tcg_temp_new_i32(); | ||
368 | if (a->op) { | ||
369 | - tmp = neon_load_reg(a->vd, 0); | ||
370 | + read_neon_element32(tmp, a->vd, 0, MO_32); | ||
371 | } else { | ||
372 | - tmp = tcg_temp_new_i32(); | ||
373 | tcg_gen_movi_i32(tmp, 0); | ||
374 | } | ||
375 | - tmp2 = neon_load_reg(a->vm, 0); | ||
376 | + tmp2 = tcg_temp_new_i32(); | ||
377 | + read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
378 | ptr1 = vfp_reg_ptr(true, a->vn); | ||
379 | tmp4 = tcg_const_i32(n); | ||
380 | gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
381 | - tcg_temp_free_i32(tmp); | ||
382 | + | ||
383 | if (a->op) { | ||
384 | - tmp = neon_load_reg(a->vd, 1); | ||
385 | + read_neon_element32(tmp, a->vd, 1, MO_32); | ||
386 | } else { | ||
387 | - tmp = tcg_temp_new_i32(); | ||
388 | tcg_gen_movi_i32(tmp, 0); | ||
389 | } | ||
390 | - tmp3 = neon_load_reg(a->vm, 1); | ||
391 | + tmp3 = tcg_temp_new_i32(); | ||
392 | + read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
393 | gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
394 | + tcg_temp_free_i32(tmp); | ||
395 | tcg_temp_free_i32(tmp4); | ||
396 | tcg_temp_free_ptr(ptr1); | ||
397 | - neon_store_reg(a->vd, 0, tmp2); | ||
398 | - neon_store_reg(a->vd, 1, tmp3); | ||
399 | - tcg_temp_free_i32(tmp); | ||
400 | + | ||
401 | + write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
402 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
403 | + tcg_temp_free_i32(tmp2); | ||
404 | + tcg_temp_free_i32(tmp3); | ||
405 | return true; | ||
406 | } | ||
407 | |||
408 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
409 | static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
410 | { | ||
411 | int pass, half; | ||
412 | + TCGv_i32 tmp[2]; | ||
413 | |||
414 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
415 | return false; | ||
416 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
417 | return true; | ||
418 | } | ||
419 | |||
420 | - for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
421 | - TCGv_i32 tmp[2]; | ||
422 | + tmp[0] = tcg_temp_new_i32(); | ||
423 | + tmp[1] = tcg_temp_new_i32(); | ||
424 | |||
425 | + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
426 | for (half = 0; half < 2; half++) { | ||
427 | - tmp[half] = neon_load_reg(a->vm, pass * 2 + half); | ||
428 | + read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32); | ||
429 | switch (a->size) { | ||
430 | case 0: | ||
431 | tcg_gen_bswap32_i32(tmp[half], tmp[half]); | ||
432 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
433 | g_assert_not_reached(); | ||
434 | } | ||
435 | } | ||
436 | - neon_store_reg(a->vd, pass * 2, tmp[1]); | ||
437 | - neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); | ||
438 | + write_neon_element32(tmp[1], a->vd, pass * 2, MO_32); | ||
439 | + write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32); | ||
440 | } | ||
441 | + | ||
442 | + tcg_temp_free_i32(tmp[0]); | ||
443 | + tcg_temp_free_i32(tmp[1]); | ||
444 | return true; | ||
445 | } | ||
446 | |||
447 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
448 | rm0_64 = tcg_temp_new_i64(); | ||
449 | rm1_64 = tcg_temp_new_i64(); | ||
450 | rd_64 = tcg_temp_new_i64(); | ||
451 | - tmp = neon_load_reg(a->vm, pass * 2); | ||
452 | + | ||
453 | + tmp = tcg_temp_new_i32(); | ||
454 | + read_neon_element32(tmp, a->vm, pass * 2, MO_32); | ||
455 | widenfn(rm0_64, tmp); | ||
456 | - tcg_temp_free_i32(tmp); | ||
457 | - tmp = neon_load_reg(a->vm, pass * 2 + 1); | ||
458 | + read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32); | ||
459 | widenfn(rm1_64, tmp); | ||
460 | tcg_temp_free_i32(tmp); | ||
461 | + | ||
462 | opfn(rd_64, rm0_64, rm1_64); | ||
463 | tcg_temp_free_i64(rm0_64); | ||
464 | tcg_temp_free_i64(rm1_64); | ||
465 | @@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
466 | narrowfn(rd0, cpu_env, rm); | ||
467 | neon_load_reg64(rm, a->vm + 1); | ||
468 | narrowfn(rd1, cpu_env, rm); | ||
469 | - neon_store_reg(a->vd, 0, rd0); | ||
470 | - neon_store_reg(a->vd, 1, rd1); | ||
471 | + write_neon_element32(rd0, a->vd, 0, MO_32); | ||
472 | + write_neon_element32(rd1, a->vd, 1, MO_32); | ||
473 | + tcg_temp_free_i32(rd0); | ||
474 | + tcg_temp_free_i32(rd1); | ||
475 | tcg_temp_free_i64(rm); | ||
476 | return true; | ||
477 | } | ||
478 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
479 | } | ||
480 | |||
481 | rd = tcg_temp_new_i64(); | ||
482 | + rm0 = tcg_temp_new_i32(); | ||
483 | + rm1 = tcg_temp_new_i32(); | ||
484 | |||
485 | - rm0 = neon_load_reg(a->vm, 0); | ||
486 | - rm1 = neon_load_reg(a->vm, 1); | ||
487 | + read_neon_element32(rm0, a->vm, 0, MO_32); | ||
488 | + read_neon_element32(rm1, a->vm, 1, MO_32); | ||
489 | |||
490 | widenfn(rd, rm0); | ||
491 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
492 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) | ||
493 | |||
494 | fpst = fpstatus_ptr(FPST_STD); | ||
495 | ahp = get_ahp_flag(); | ||
496 | - tmp = neon_load_reg(a->vm, 0); | ||
497 | + tmp = tcg_temp_new_i32(); | ||
498 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
499 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
500 | - tmp2 = neon_load_reg(a->vm, 1); | ||
501 | + tmp2 = tcg_temp_new_i32(); | ||
502 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
503 | gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); | ||
504 | tcg_gen_shli_i32(tmp2, tmp2, 16); | ||
505 | tcg_gen_or_i32(tmp2, tmp2, tmp); | ||
506 | - tcg_temp_free_i32(tmp); | ||
507 | - tmp = neon_load_reg(a->vm, 2); | ||
508 | + read_neon_element32(tmp, a->vm, 2, MO_32); | ||
509 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
510 | - tmp3 = neon_load_reg(a->vm, 3); | ||
511 | - neon_store_reg(a->vd, 0, tmp2); | ||
512 | + tmp3 = tcg_temp_new_i32(); | ||
513 | + read_neon_element32(tmp3, a->vm, 3, MO_32); | ||
514 | + write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
515 | + tcg_temp_free_i32(tmp2); | ||
516 | gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); | ||
517 | tcg_gen_shli_i32(tmp3, tmp3, 16); | ||
518 | tcg_gen_or_i32(tmp3, tmp3, tmp); | ||
519 | - neon_store_reg(a->vd, 1, tmp3); | ||
520 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
521 | + tcg_temp_free_i32(tmp3); | ||
522 | tcg_temp_free_i32(tmp); | ||
523 | tcg_temp_free_i32(ahp); | ||
524 | tcg_temp_free_ptr(fpst); | ||
525 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
526 | fpst = fpstatus_ptr(FPST_STD); | ||
527 | ahp = get_ahp_flag(); | ||
528 | tmp3 = tcg_temp_new_i32(); | ||
529 | - tmp = neon_load_reg(a->vm, 0); | ||
530 | - tmp2 = neon_load_reg(a->vm, 1); | ||
531 | + tmp2 = tcg_temp_new_i32(); | ||
532 | + tmp = tcg_temp_new_i32(); | ||
533 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
534 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
535 | tcg_gen_ext16u_i32(tmp3, tmp); | ||
536 | gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
537 | - neon_store_reg(a->vd, 0, tmp3); | ||
538 | + write_neon_element32(tmp3, a->vd, 0, MO_32); | ||
539 | tcg_gen_shri_i32(tmp, tmp, 16); | ||
540 | gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); | ||
541 | - neon_store_reg(a->vd, 1, tmp); | ||
542 | - tmp3 = tcg_temp_new_i32(); | ||
543 | + write_neon_element32(tmp, a->vd, 1, MO_32); | ||
544 | + tcg_temp_free_i32(tmp); | ||
545 | tcg_gen_ext16u_i32(tmp3, tmp2); | ||
546 | gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
547 | - neon_store_reg(a->vd, 2, tmp3); | ||
548 | + write_neon_element32(tmp3, a->vd, 2, MO_32); | ||
549 | + tcg_temp_free_i32(tmp3); | ||
550 | tcg_gen_shri_i32(tmp2, tmp2, 16); | ||
551 | gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); | ||
552 | - neon_store_reg(a->vd, 3, tmp2); | ||
553 | + write_neon_element32(tmp2, a->vd, 3, MO_32); | ||
554 | + tcg_temp_free_i32(tmp2); | ||
555 | tcg_temp_free_i32(ahp); | ||
556 | tcg_temp_free_ptr(fpst); | ||
557 | |||
558 | @@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) | ||
559 | |||
560 | static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
561 | { | ||
562 | + TCGv_i32 tmp; | ||
563 | int pass; | ||
564 | |||
565 | /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ | ||
566 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
567 | return true; | ||
568 | } | ||
569 | |||
570 | + tmp = tcg_temp_new_i32(); | ||
571 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
572 | - TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
573 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
574 | fn(tmp, tmp); | ||
575 | - neon_store_reg(a->vd, pass, tmp); | ||
576 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
577 | } | ||
578 | + tcg_temp_free_i32(tmp); | ||
579 | |||
580 | return true; | ||
581 | } | ||
582 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a) | ||
583 | return true; | ||
584 | } | ||
585 | |||
586 | - if (a->size == 2) { | ||
587 | + tmp = tcg_temp_new_i32(); | ||
588 | + tmp2 = tcg_temp_new_i32(); | ||
589 | + if (a->size == MO_32) { | ||
590 | for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) { | ||
591 | - tmp = neon_load_reg(a->vm, pass); | ||
592 | - tmp2 = neon_load_reg(a->vd, pass + 1); | ||
593 | - neon_store_reg(a->vm, pass, tmp2); | ||
594 | - neon_store_reg(a->vd, pass + 1, tmp); | ||
595 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
596 | + read_neon_element32(tmp2, a->vd, pass + 1, MO_32); | ||
597 | + write_neon_element32(tmp2, a->vm, pass, MO_32); | ||
598 | + write_neon_element32(tmp, a->vd, pass + 1, MO_32); | ||
599 | } | ||
600 | } else { | ||
601 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
602 | - tmp = neon_load_reg(a->vm, pass); | ||
603 | - tmp2 = neon_load_reg(a->vd, pass); | ||
604 | - if (a->size == 0) { | ||
605 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
606 | + read_neon_element32(tmp2, a->vd, pass, MO_32); | ||
607 | + if (a->size == MO_8) { | ||
608 | gen_neon_trn_u8(tmp, tmp2); | ||
609 | } else { | ||
610 | gen_neon_trn_u16(tmp, tmp2); | ||
611 | } | ||
612 | - neon_store_reg(a->vm, pass, tmp2); | ||
613 | - neon_store_reg(a->vd, pass, tmp); | ||
614 | + write_neon_element32(tmp2, a->vm, pass, MO_32); | ||
615 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
616 | } | ||
617 | } | ||
618 | + tcg_temp_free_i32(tmp); | ||
619 | + tcg_temp_free_i32(tmp2); | ||
620 | return true; | ||
621 | } | ||
622 | -- | 32 | -- |
623 | 2.20.1 | 33 | 2.34.1 |
624 | 34 | ||
625 | 35 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This seems a bit more readable than using offsetof CPU_DoubleU. | 3 | While we cannot move the main "helper.h" out of target/arm/, |
4 | due to usage by generic code, we can move the sub-includes. | ||
4 | 5 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20201030022618.785675-5-richard.henderson@linaro.org | 7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Message-id: 20230504110412.1892411-3-richard.henderson@linaro.org |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | target/arm/translate.c | 13 ++++--------- | 12 | target/arm/helper.h | 8 ++++---- |
11 | 1 file changed, 4 insertions(+), 9 deletions(-) | 13 | target/arm/{ => tcg}/helper-a64.h | 0 |
14 | target/arm/{ => tcg}/helper-mve.h | 0 | ||
15 | target/arm/{ => tcg}/helper-sme.h | 0 | ||
16 | target/arm/{ => tcg}/helper-sve.h | 0 | ||
17 | 5 files changed, 4 insertions(+), 4 deletions(-) | ||
18 | rename target/arm/{ => tcg}/helper-a64.h (100%) | ||
19 | rename target/arm/{ => tcg}/helper-mve.h (100%) | ||
20 | rename target/arm/{ => tcg}/helper-sme.h (100%) | ||
21 | rename target/arm/{ => tcg}/helper-sve.h (100%) | ||
12 | 22 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 23 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
14 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 25 | --- a/target/arm/helper.h |
16 | +++ b/target/arm/translate.c | 26 | +++ b/target/arm/helper.h |
17 | @@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size) | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, |
18 | return neon_full_reg_offset(reg) + ofs; | 28 | void, ptr, ptr, ptr, ptr, i32) |
19 | } | 29 | |
20 | 30 | #ifdef TARGET_AARCH64 | |
21 | -static inline long vfp_reg_offset(bool dp, unsigned reg) | 31 | -#include "helper-a64.h" |
22 | +/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */ | 32 | -#include "helper-sve.h" |
23 | +static long vfp_reg_offset(bool dp, unsigned reg) | 33 | -#include "helper-sme.h" |
24 | { | 34 | +#include "tcg/helper-a64.h" |
25 | if (dp) { | 35 | +#include "tcg/helper-sve.h" |
26 | - return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | 36 | +#include "tcg/helper-sme.h" |
27 | + return neon_element_offset(reg, 0, MO_64); | 37 | #endif |
28 | } else { | 38 | |
29 | - long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]); | 39 | -#include "helper-mve.h" |
30 | - if (reg & 1) { | 40 | +#include "tcg/helper-mve.h" |
31 | - ofs += offsetof(CPU_DoubleU, l.upper); | 41 | diff --git a/target/arm/helper-a64.h b/target/arm/tcg/helper-a64.h |
32 | - } else { | 42 | similarity index 100% |
33 | - ofs += offsetof(CPU_DoubleU, l.lower); | 43 | rename from target/arm/helper-a64.h |
34 | - } | 44 | rename to target/arm/tcg/helper-a64.h |
35 | - return ofs; | 45 | diff --git a/target/arm/helper-mve.h b/target/arm/tcg/helper-mve.h |
36 | + return neon_element_offset(reg >> 1, reg & 1, MO_32); | 46 | similarity index 100% |
37 | } | 47 | rename from target/arm/helper-mve.h |
38 | } | 48 | rename to target/arm/tcg/helper-mve.h |
39 | 49 | diff --git a/target/arm/helper-sme.h b/target/arm/tcg/helper-sme.h | |
50 | similarity index 100% | ||
51 | rename from target/arm/helper-sme.h | ||
52 | rename to target/arm/tcg/helper-sme.h | ||
53 | diff --git a/target/arm/helper-sve.h b/target/arm/tcg/helper-sve.h | ||
54 | similarity index 100% | ||
55 | rename from target/arm/helper-sve.h | ||
56 | rename to target/arm/tcg/helper-sve.h | ||
40 | -- | 57 | -- |
41 | 2.20.1 | 58 | 2.34.1 |
42 | 59 | ||
43 | 60 | diff view generated by jsdifflib |
1 | In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to | 1 | Bit 63 in a Table descriptor is only the NSTable bit for stage 1 |
---|---|---|---|
2 | armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el(). | 2 | translations; in stage 2 it is RES0. We were incorrectly looking at |
3 | This is incorrect when the security state being queried is not the | 3 | it all the time. |
4 | current one, because arm_current_el() uses the current security state | ||
5 | to determine which of the banked CONTROL.nPRIV bits to look at. | ||
6 | The effect was that if (for instance) Secure state was in privileged | ||
7 | mode but Non-Secure was not then we would return the wrong MMU index. | ||
8 | 4 | ||
9 | The only places where we are using this function in a way that could | 5 | This causes problems if: |
10 | trigger this bug are for the stack loads during a v8M function-return | 6 | * the stage 2 table descriptor was incorrectly setting the RES0 bit |
11 | and for the instruction fetch of a v8M SG insn. | 7 | * we are doing a stage 2 translation in Secure address space for |
8 | a NonSecure stage 1 regime -- in this case we would incorrectly | ||
9 | do an immediate downgrade to NonSecure | ||
12 | 10 | ||
13 | Fix the bug by expanding out the M-profile version of the | 11 | A bug elsewhere in the code currently prevents us from getting |
14 | arm_current_el() logic inline so it can use the passed in secstate | 12 | to the second situation, but when we fix that it will be possible. |
15 | rather than env->v7m.secure. | ||
16 | 13 | ||
14 | Cc: qemu-stable@nongnu.org | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
19 | Message-id: 20201022164408.13214-1-peter.maydell@linaro.org | 17 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
18 | Message-id: 20230504135425.2748672-2-peter.maydell@linaro.org | ||
20 | --- | 19 | --- |
21 | target/arm/m_helper.c | 3 ++- | 20 | target/arm/ptw.c | 5 +++-- |
22 | 1 file changed, 2 insertions(+), 1 deletion(-) | 21 | 1 file changed, 3 insertions(+), 2 deletions(-) |
23 | 22 | ||
24 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 23 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
25 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/m_helper.c | 25 | --- a/target/arm/ptw.c |
27 | +++ b/target/arm/m_helper.c | 26 | +++ b/target/arm/ptw.c |
28 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | 27 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
29 | /* Return the MMU index for a v7M CPU in the specified security state */ | 28 | descaddrmask &= ~indexmask_grainsize; |
30 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 29 | |
31 | { | 30 | /* |
32 | - bool priv = arm_current_el(env) != 0; | 31 | - * Secure accesses start with the page table in secure memory and |
33 | + bool priv = arm_v7m_is_handler_mode(env) || | 32 | + * Secure stage 1 accesses start with the page table in secure memory and |
34 | + !(env->v7m.control[secstate] & 1); | 33 | * can be downgraded to non-secure at any step. Non-secure accesses |
35 | 34 | * remain non-secure. We implement this by just ORing in the NSTable/NS | |
36 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | 35 | * bits at each step. |
37 | } | 36 | + * Stage 2 never gets this kind of downgrade. |
37 | */ | ||
38 | tableattrs = is_secure ? 0 : (1 << 4); | ||
39 | |||
40 | next_level: | ||
41 | descaddr |= (address >> (stride * (4 - level))) & indexmask; | ||
42 | descaddr &= ~7ULL; | ||
43 | - nstable = extract32(tableattrs, 4, 1); | ||
44 | + nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); | ||
45 | if (nstable) { | ||
46 | /* | ||
47 | * Stage2_S -> Stage2 or Phys_S -> Phys_NS | ||
38 | -- | 48 | -- |
39 | 2.20.1 | 49 | 2.34.1 |
40 | 50 | ||
41 | 51 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | We currently don't correctly handle the VSTCR_EL2.SW and VTCR_EL2.NSW |
---|---|---|---|
2 | configuration bits. These allow configuration of whether the stage 2 | ||
3 | page table walks for Secure IPA and NonSecure IPA should do their | ||
4 | descriptor reads from Secure or NonSecure physical addresses. (This | ||
5 | is separate from how the translation table base address and other | ||
6 | parameters are set: an NS IPA always uses VTTBR_EL2 and VTCR_EL2 | ||
7 | for its base address and walk parameters, regardless of the NSW bit, | ||
8 | and similarly for Secure.) | ||
2 | 9 | ||
3 | This will shortly have users outside of translate-neon.c.inc. | 10 | Provide a new function ptw_idx_for_stage_2() which returns the |
11 | MMU index to use for descriptor reads, and use it to set up | ||
12 | the .in_ptw_idx wherever we call get_phys_addr_lpae(). | ||
4 | 13 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 14 | For a stage 2 walk, wherever we call get_phys_addr_lpae(): |
6 | Message-id: 20201030022618.785675-3-richard.henderson@linaro.org | 15 | * .in_ptw_idx should be ptw_idx_for_stage_2() of the .in_mmu_idx |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 16 | * .in_secure should be true if .in_mmu_idx is Stage2_S |
17 | |||
18 | This allows us to correct S1_ptw_translate() so that it consistently | ||
19 | always sets its (out_secure, out_phys) to the result it gets from the | ||
20 | S2 walk (either by calling get_phys_addr_lpae() or by TLB lookup). | ||
21 | This makes better conceptual sense because the S2 walk should return | ||
22 | us an (address space, address) tuple, not an address that we then | ||
23 | randomly assign to S or NS. | ||
24 | |||
25 | Our previous handling of SW and NSW was broken, so guest code | ||
26 | trying to use these bits to put the s2 page tables in the "other" | ||
27 | address space wouldn't work correctly. | ||
28 | |||
29 | Cc: qemu-stable@nongnu.org | ||
30 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1600 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 31 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
32 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
33 | Message-id: 20230504135425.2748672-3-peter.maydell@linaro.org | ||
9 | --- | 34 | --- |
10 | target/arm/translate.c | 20 ++++++++++++++++++++ | 35 | target/arm/ptw.c | 76 ++++++++++++++++++++++++++++++++---------------- |
11 | target/arm/translate-neon.c.inc | 19 ------------------- | 36 | 1 file changed, 51 insertions(+), 25 deletions(-) |
12 | 2 files changed, 20 insertions(+), 19 deletions(-) | ||
13 | 37 | ||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 38 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
15 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.c | 40 | --- a/target/arm/ptw.c |
17 | +++ b/target/arm/translate.c | 41 | +++ b/target/arm/ptw.c |
18 | @@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg) | 42 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) |
19 | return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | 43 | return stage_1_mmu_idx(arm_mmu_idx(env)); |
20 | } | 44 | } |
21 | 45 | ||
22 | +/* | 46 | +/* |
23 | + * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | 47 | + * Return where we should do ptw loads from for a stage 2 walk. |
24 | + * where 0 is the least significant end of the register. | 48 | + * This depends on whether the address we are looking up is a |
49 | + * Secure IPA or a NonSecure IPA, which we know from whether this is | ||
50 | + * Stage2 or Stage2_S. | ||
51 | + * If this is the Secure EL1&0 regime we need to check the NSW and SW bits. | ||
25 | + */ | 52 | + */ |
26 | +static long neon_element_offset(int reg, int element, MemOp size) | 53 | +static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx) |
27 | +{ | 54 | +{ |
28 | + int element_size = 1 << size; | 55 | + bool s2walk_secure; |
29 | + int ofs = element * element_size; | 56 | + |
30 | +#ifdef HOST_WORDS_BIGENDIAN | ||
31 | + /* | 57 | + /* |
32 | + * Calculate the offset assuming fully little-endian, | 58 | + * We're OK to check the current state of the CPU here because |
33 | + * then XOR to account for the order of the 8-byte units. | 59 | + * (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes |
60 | + * (2) there's no way to do a lookup that cares about Stage 2 for a | ||
61 | + * different security state to the current one for AArch64, and AArch32 | ||
62 | + * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do | ||
63 | + * an NS stage 1+2 lookup while the NS bit is 0.) | ||
34 | + */ | 64 | + */ |
35 | + if (element_size < 8) { | 65 | + if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) { |
36 | + ofs ^= 8 - element_size; | 66 | + return ARMMMUIdx_Phys_NS; |
37 | + } | 67 | + } |
38 | +#endif | 68 | + if (stage2idx == ARMMMUIdx_Stage2_S) { |
39 | + return neon_full_reg_offset(reg) + ofs; | 69 | + s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); |
70 | + } else { | ||
71 | + s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); | ||
72 | + } | ||
73 | + return s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; | ||
74 | + | ||
40 | +} | 75 | +} |
41 | + | 76 | + |
42 | static inline long vfp_reg_offset(bool dp, unsigned reg) | 77 | static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) |
43 | { | 78 | { |
44 | if (dp) { | 79 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; |
45 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | 80 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
46 | index XXXXXXX..XXXXXXX 100644 | 81 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; |
47 | --- a/target/arm/translate-neon.c.inc | 82 | ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; |
48 | +++ b/target/arm/translate-neon.c.inc | 83 | uint8_t pte_attrs; |
49 | @@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x) | 84 | - bool pte_secure; |
50 | #include "decode-neon-ls.c.inc" | 85 | |
51 | #include "decode-neon-shared.c.inc" | 86 | ptw->out_virt = addr; |
52 | 87 | ||
53 | -/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | 88 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
54 | - * where 0 is the least significant end of the register. | 89 | if (regime_is_stage2(s2_mmu_idx)) { |
55 | - */ | 90 | S1Translate s2ptw = { |
56 | -static inline long | 91 | .in_mmu_idx = s2_mmu_idx, |
57 | -neon_element_offset(int reg, int element, MemOp size) | 92 | - .in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS, |
58 | -{ | 93 | - .in_secure = is_secure, |
59 | - int element_size = 1 << size; | 94 | + .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), |
60 | - int ofs = element * element_size; | 95 | + .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, |
61 | -#ifdef HOST_WORDS_BIGENDIAN | 96 | .in_debug = true, |
62 | - /* Calculate the offset assuming fully little-endian, | 97 | }; |
63 | - * then XOR to account for the order of the 8-byte units. | 98 | GetPhysAddrResult s2 = { }; |
64 | - */ | 99 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
65 | - if (element_size < 8) { | 100 | } |
66 | - ofs ^= 8 - element_size; | 101 | ptw->out_phys = s2.f.phys_addr; |
102 | pte_attrs = s2.cacheattrs.attrs; | ||
103 | - pte_secure = s2.f.attrs.secure; | ||
104 | + ptw->out_secure = s2.f.attrs.secure; | ||
105 | } else { | ||
106 | /* Regime is physical. */ | ||
107 | ptw->out_phys = addr; | ||
108 | pte_attrs = 0; | ||
109 | - pte_secure = is_secure; | ||
110 | + ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; | ||
111 | } | ||
112 | ptw->out_host = NULL; | ||
113 | ptw->out_rw = false; | ||
114 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
115 | ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); | ||
116 | ptw->out_rw = full->prot & PAGE_WRITE; | ||
117 | pte_attrs = full->pte_attrs; | ||
118 | - pte_secure = full->attrs.secure; | ||
119 | + ptw->out_secure = full->attrs.secure; | ||
120 | #else | ||
121 | g_assert_not_reached(); | ||
122 | #endif | ||
123 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
124 | } | ||
125 | } | ||
126 | |||
127 | - /* Check if page table walk is to secure or non-secure PA space. */ | ||
128 | - ptw->out_secure = (is_secure | ||
129 | - && !(pte_secure | ||
130 | - ? env->cp15.vstcr_el2 & VSTCR_SW | ||
131 | - : env->cp15.vtcr_el2 & VTCR_NSW)); | ||
132 | ptw->out_be = regime_translation_big_endian(env, mmu_idx); | ||
133 | return true; | ||
134 | |||
135 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
136 | hwaddr ipa; | ||
137 | int s1_prot, s1_lgpgsz; | ||
138 | bool is_secure = ptw->in_secure; | ||
139 | - bool ret, ipa_secure, s2walk_secure; | ||
140 | + bool ret, ipa_secure; | ||
141 | ARMCacheAttrs cacheattrs1; | ||
142 | bool is_el0; | ||
143 | uint64_t hcr; | ||
144 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
145 | |||
146 | ipa = result->f.phys_addr; | ||
147 | ipa_secure = result->f.attrs.secure; | ||
148 | - if (is_secure) { | ||
149 | - /* Select TCR based on the NS bit from the S1 walk. */ | ||
150 | - s2walk_secure = !(ipa_secure | ||
151 | - ? env->cp15.vstcr_el2 & VSTCR_SW | ||
152 | - : env->cp15.vtcr_el2 & VTCR_NSW); | ||
153 | - } else { | ||
154 | - assert(!ipa_secure); | ||
155 | - s2walk_secure = false; | ||
67 | - } | 156 | - } |
68 | -#endif | 157 | |
69 | - return neon_full_reg_offset(reg) + ofs; | 158 | is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; |
70 | -} | 159 | - ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; |
71 | - | 160 | - ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; |
72 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | 161 | - ptw->in_secure = s2walk_secure; |
73 | { | 162 | + ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; |
74 | long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | 163 | + ptw->in_secure = ipa_secure; |
164 | + ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); | ||
165 | |||
166 | /* | ||
167 | * S1 is done, now do S2 translation. | ||
168 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
169 | ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
170 | break; | ||
171 | |||
172 | + case ARMMMUIdx_Stage2: | ||
173 | + case ARMMMUIdx_Stage2_S: | ||
174 | + /* | ||
175 | + * Second stage lookup uses physical for ptw; whether this is S or | ||
176 | + * NS may depend on the SW/NSW bits if this is a stage 2 lookup for | ||
177 | + * the Secure EL2&0 regime. | ||
178 | + */ | ||
179 | + ptw->in_ptw_idx = ptw_idx_for_stage_2(env, mmu_idx); | ||
180 | + break; | ||
181 | + | ||
182 | case ARMMMUIdx_E10_0: | ||
183 | s1_mmu_idx = ARMMMUIdx_Stage1_E0; | ||
184 | goto do_twostage; | ||
185 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
186 | /* fall through */ | ||
187 | |||
188 | default: | ||
189 | - /* Single stage and second stage uses physical for ptw. */ | ||
190 | + /* Single stage uses physical for ptw. */ | ||
191 | ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; | ||
192 | break; | ||
193 | } | ||
75 | -- | 194 | -- |
76 | 2.20.1 | 195 | 2.34.1 |
77 | |||
78 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | These are the only users of neon_reg_offset, so remove that. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20201030022618.785675-4-richard.henderson@linaro.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/translate.c | 14 ++------------ | ||
11 | 1 file changed, 2 insertions(+), 12 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/translate.c | ||
16 | +++ b/target/arm/translate.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg) | ||
18 | } | ||
19 | } | ||
20 | |||
21 | -/* Return the offset of a 32-bit piece of a NEON register. | ||
22 | - zero is the least significant end of the register. */ | ||
23 | -static inline long | ||
24 | -neon_reg_offset (int reg, int n) | ||
25 | -{ | ||
26 | - int sreg; | ||
27 | - sreg = reg * 2 + n; | ||
28 | - return vfp_reg_offset(0, sreg); | ||
29 | -} | ||
30 | - | ||
31 | static TCGv_i32 neon_load_reg(int reg, int pass) | ||
32 | { | ||
33 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
34 | - tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); | ||
35 | + tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); | ||
36 | return tmp; | ||
37 | } | ||
38 | |||
39 | static void neon_store_reg(int reg, int pass, TCGv_i32 var) | ||
40 | { | ||
41 | - tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); | ||
42 | + tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); | ||
43 | tcg_temp_free_i32(var); | ||
44 | } | ||
45 | |||
46 | -- | ||
47 | 2.20.1 | ||
48 | |||
49 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | We can then use this to improve VMOV (scalar to gp) and | ||
4 | VMOV (gp to scalar) so that we simply perform the memory | ||
5 | operation that we wanted, rather than inserting or | ||
6 | extracting from a 32-bit quantity. | ||
7 | |||
8 | These were the last uses of neon_load/store_reg, so remove them. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20201030022618.785675-7-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/translate.c | 50 +++++++++++++----------- | ||
16 | target/arm/translate-vfp.c.inc | 71 +++++----------------------------- | ||
17 | 2 files changed, 37 insertions(+), 84 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/translate.c | ||
22 | +++ b/target/arm/translate.c | ||
23 | @@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg) | ||
24 | * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
25 | * where 0 is the least significant end of the register. | ||
26 | */ | ||
27 | -static long neon_element_offset(int reg, int element, MemOp size) | ||
28 | +static long neon_element_offset(int reg, int element, MemOp memop) | ||
29 | { | ||
30 | - int element_size = 1 << size; | ||
31 | + int element_size = 1 << (memop & MO_SIZE); | ||
32 | int ofs = element * element_size; | ||
33 | #ifdef HOST_WORDS_BIGENDIAN | ||
34 | /* | ||
35 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) | ||
36 | } | ||
37 | } | ||
38 | |||
39 | -static TCGv_i32 neon_load_reg(int reg, int pass) | ||
40 | -{ | ||
41 | - TCGv_i32 tmp = tcg_temp_new_i32(); | ||
42 | - tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); | ||
43 | - return tmp; | ||
44 | -} | ||
45 | - | ||
46 | -static void neon_store_reg(int reg, int pass, TCGv_i32 var) | ||
47 | -{ | ||
48 | - tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); | ||
49 | - tcg_temp_free_i32(var); | ||
50 | -} | ||
51 | - | ||
52 | static inline void neon_load_reg64(TCGv_i64 var, int reg) | ||
53 | { | ||
54 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | ||
55 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg) | ||
56 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
57 | } | ||
58 | |||
59 | -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) | ||
60 | +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
61 | { | ||
62 | - long off = neon_element_offset(reg, ele, size); | ||
63 | + long off = neon_element_offset(reg, ele, memop); | ||
64 | |||
65 | - switch (size) { | ||
66 | - case MO_32: | ||
67 | + switch (memop) { | ||
68 | + case MO_SB: | ||
69 | + tcg_gen_ld8s_i32(dest, cpu_env, off); | ||
70 | + break; | ||
71 | + case MO_UB: | ||
72 | + tcg_gen_ld8u_i32(dest, cpu_env, off); | ||
73 | + break; | ||
74 | + case MO_SW: | ||
75 | + tcg_gen_ld16s_i32(dest, cpu_env, off); | ||
76 | + break; | ||
77 | + case MO_UW: | ||
78 | + tcg_gen_ld16u_i32(dest, cpu_env, off); | ||
79 | + break; | ||
80 | + case MO_UL: | ||
81 | + case MO_SL: | ||
82 | tcg_gen_ld_i32(dest, cpu_env, off); | ||
83 | break; | ||
84 | default: | ||
85 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) | ||
86 | } | ||
87 | } | ||
88 | |||
89 | -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size) | ||
90 | +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
91 | { | ||
92 | - long off = neon_element_offset(reg, ele, size); | ||
93 | + long off = neon_element_offset(reg, ele, memop); | ||
94 | |||
95 | - switch (size) { | ||
96 | + switch (memop) { | ||
97 | + case MO_8: | ||
98 | + tcg_gen_st8_i32(src, cpu_env, off); | ||
99 | + break; | ||
100 | + case MO_16: | ||
101 | + tcg_gen_st16_i32(src, cpu_env, off); | ||
102 | + break; | ||
103 | case MO_32: | ||
104 | tcg_gen_st_i32(src, cpu_env, off); | ||
105 | break; | ||
106 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/arm/translate-vfp.c.inc | ||
109 | +++ b/target/arm/translate-vfp.c.inc | ||
110 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
111 | { | ||
112 | /* VMOV scalar to general purpose register */ | ||
113 | TCGv_i32 tmp; | ||
114 | - int pass; | ||
115 | - uint32_t offset; | ||
116 | |||
117 | - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | ||
118 | - if (a->size == 2 | ||
119 | + /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */ | ||
120 | + if (a->size == MO_32 | ||
121 | ? !dc_isar_feature(aa32_fpsp_v2, s) | ||
122 | : !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
123 | return false; | ||
124 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
125 | return false; | ||
126 | } | ||
127 | |||
128 | - offset = a->index << a->size; | ||
129 | - pass = extract32(offset, 2, 1); | ||
130 | - offset = extract32(offset, 0, 2) * 8; | ||
131 | - | ||
132 | if (!vfp_access_check(s)) { | ||
133 | return true; | ||
134 | } | ||
135 | |||
136 | - tmp = neon_load_reg(a->vn, pass); | ||
137 | - switch (a->size) { | ||
138 | - case 0: | ||
139 | - if (offset) { | ||
140 | - tcg_gen_shri_i32(tmp, tmp, offset); | ||
141 | - } | ||
142 | - if (a->u) { | ||
143 | - gen_uxtb(tmp); | ||
144 | - } else { | ||
145 | - gen_sxtb(tmp); | ||
146 | - } | ||
147 | - break; | ||
148 | - case 1: | ||
149 | - if (a->u) { | ||
150 | - if (offset) { | ||
151 | - tcg_gen_shri_i32(tmp, tmp, 16); | ||
152 | - } else { | ||
153 | - gen_uxth(tmp); | ||
154 | - } | ||
155 | - } else { | ||
156 | - if (offset) { | ||
157 | - tcg_gen_sari_i32(tmp, tmp, 16); | ||
158 | - } else { | ||
159 | - gen_sxth(tmp); | ||
160 | - } | ||
161 | - } | ||
162 | - break; | ||
163 | - case 2: | ||
164 | - break; | ||
165 | - } | ||
166 | + tmp = tcg_temp_new_i32(); | ||
167 | + read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN)); | ||
168 | store_reg(s, a->rt, tmp); | ||
169 | |||
170 | return true; | ||
171 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
172 | static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
173 | { | ||
174 | /* VMOV general purpose register to scalar */ | ||
175 | - TCGv_i32 tmp, tmp2; | ||
176 | - int pass; | ||
177 | - uint32_t offset; | ||
178 | + TCGv_i32 tmp; | ||
179 | |||
180 | - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | ||
181 | - if (a->size == 2 | ||
182 | + /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */ | ||
183 | + if (a->size == MO_32 | ||
184 | ? !dc_isar_feature(aa32_fpsp_v2, s) | ||
185 | : !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
186 | return false; | ||
187 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
188 | return false; | ||
189 | } | ||
190 | |||
191 | - offset = a->index << a->size; | ||
192 | - pass = extract32(offset, 2, 1); | ||
193 | - offset = extract32(offset, 0, 2) * 8; | ||
194 | - | ||
195 | if (!vfp_access_check(s)) { | ||
196 | return true; | ||
197 | } | ||
198 | |||
199 | tmp = load_reg(s, a->rt); | ||
200 | - switch (a->size) { | ||
201 | - case 0: | ||
202 | - tmp2 = neon_load_reg(a->vn, pass); | ||
203 | - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); | ||
204 | - tcg_temp_free_i32(tmp2); | ||
205 | - break; | ||
206 | - case 1: | ||
207 | - tmp2 = neon_load_reg(a->vn, pass); | ||
208 | - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); | ||
209 | - tcg_temp_free_i32(tmp2); | ||
210 | - break; | ||
211 | - case 2: | ||
212 | - break; | ||
213 | - } | ||
214 | - neon_store_reg(a->vn, pass, tmp); | ||
215 | + write_neon_element32(tmp, a->vn, a->index, a->size); | ||
216 | + tcg_temp_free_i32(tmp); | ||
217 | |||
218 | return true; | ||
219 | } | ||
220 | -- | ||
221 | 2.20.1 | ||
222 | |||
223 | diff view generated by jsdifflib |
1 | From: AlexChen <alex.chen@huawei.com> | 1 | From: Akihiko Odaki <akihiko.odaki@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | In exynos4210_fimd_update(), the pointer s is dereferinced before | 3 | I am now employed by Daynix. Although my role as a reviewer of |
4 | being check if it is valid, which may lead to NULL pointer dereference. | 4 | macOS-related change is not very relevant to the employment, I decided |
5 | So move the assignment to global_width after checking that the s is valid. | 5 | to use the company email address to avoid confusions from different |
6 | addresses. | ||
6 | 7 | ||
7 | Reported-by: Euler Robot <euler.robot@huawei.com> | 8 | Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> |
8 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | 9 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Message-id: 5F9F8D88.9030102@huawei.com | 11 | Message-id: 20230506072333.32510-1-akihiko.odaki@daynix.com |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 13 | --- |
13 | hw/display/exynos4210_fimd.c | 4 +++- | 14 | MAINTAINERS | 4 ++-- |
14 | 1 file changed, 3 insertions(+), 1 deletion(-) | 15 | 1 file changed, 2 insertions(+), 2 deletions(-) |
15 | 16 | ||
16 | diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c | 17 | diff --git a/MAINTAINERS b/MAINTAINERS |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/display/exynos4210_fimd.c | 19 | --- a/MAINTAINERS |
19 | +++ b/hw/display/exynos4210_fimd.c | 20 | +++ b/MAINTAINERS |
20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque) | 21 | @@ -XXX,XX +XXX,XX @@ Core Audio framework backend |
21 | bool blend = false; | 22 | M: Gerd Hoffmann <kraxel@redhat.com> |
22 | uint8_t *host_fb_addr; | 23 | M: Philippe Mathieu-Daudé <philmd@linaro.org> |
23 | bool is_dirty = false; | 24 | R: Christian Schoenebeck <qemu_oss@crudebyte.com> |
24 | - const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; | 25 | -R: Akihiko Odaki <akihiko.odaki@gmail.com> |
25 | + int global_width; | 26 | +R: Akihiko Odaki <akihiko.odaki@daynix.com> |
26 | 27 | S: Odd Fixes | |
27 | if (!s || !s->console || !s->enabled || | 28 | F: audio/coreaudio.c |
28 | surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { | 29 | |
29 | return; | 30 | @@ -XXX,XX +XXX,XX @@ F: docs/devel/ui.rst |
30 | } | 31 | Cocoa graphics |
31 | + | 32 | M: Peter Maydell <peter.maydell@linaro.org> |
32 | + global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; | 33 | M: Philippe Mathieu-Daudé <philmd@linaro.org> |
33 | exynos4210_update_resolution(s); | 34 | -R: Akihiko Odaki <akihiko.odaki@gmail.com> |
34 | surface = qemu_console_surface(s->console); | 35 | +R: Akihiko Odaki <akihiko.odaki@daynix.com> |
36 | S: Odd Fixes | ||
37 | F: ui/cocoa.m | ||
35 | 38 | ||
36 | -- | 39 | -- |
37 | 2.20.1 | 40 | 2.34.1 |
38 | 41 | ||
39 | 42 | diff view generated by jsdifflib |
1 | If we're using the capstone disassembler, disassembly of a run of | 1 | When we take a PNG screenshot the ordering of the colour channels in |
---|---|---|---|
2 | instructions more than 32 bytes long disassembles the wrong data for | 2 | the data is not correct, resulting in the image having weird |
3 | instructions beyond the 32 byte mark: | 3 | colouring compared to the actual display. (Specifically, on a |
4 | little-endian host the blue and red channels are swapped; on | ||
5 | big-endian everything is wrong.) | ||
4 | 6 | ||
5 | (qemu) xp /16x 0x100 | 7 | This happens because the pixman idea of the pixel data and the libpng |
6 | 0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000 | 8 | idea differ. PIXMAN_a8r8g8b8 defines that pixels are 32-bit values, |
7 | 0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000 | 9 | with A in bits 24-31, R in bits 16-23, G in bits 8-15 and B in bits |
8 | 0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574 | 10 | 0-7. This means that on little-endian systems the bytes in memory |
9 | 0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000 | 11 | are |
10 | (qemu) xp /16i 0x100 | 12 | B G R A |
11 | 0x00000100: 00000005 andeq r0, r0, r5 | 13 | and on big-endian systems they are |
12 | 0x00000104: 54410001 strbpl r0, [r1], #-1 | 14 | A R G B |
13 | 0x00000108: 00000001 andeq r0, r0, r1 | ||
14 | 0x0000010c: 00001000 andeq r1, r0, r0 | ||
15 | 0x00000110: 00000000 andeq r0, r0, r0 | ||
16 | 0x00000114: 00000004 andeq r0, r0, r4 | ||
17 | 0x00000118: 54410002 strbpl r0, [r1], #-2 | ||
18 | 0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c | ||
19 | 0x00000120: 54410001 strbpl r0, [r1], #-1 | ||
20 | 0x00000124: 00000001 andeq r0, r0, r1 | ||
21 | 0x00000128: 00001000 andeq r1, r0, r0 | ||
22 | 0x0000012c: 00000000 andeq r0, r0, r0 | ||
23 | 0x00000130: 00000004 andeq r0, r0, r4 | ||
24 | 0x00000134: 54410002 strbpl r0, [r1], #-2 | ||
25 | 0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c | ||
26 | 0x0000013c: 00000000 andeq r0, r0, r0 | ||
27 | 15 | ||
28 | Here the disassembly of 0x120..0x13f is using the data that is in | 16 | libpng, on the other hand, thinks of pixels as being a series of |
29 | 0x104..0x123. | 17 | values for each channel, so its format PNG_COLOR_TYPE_RGB_ALPHA |
18 | always wants bytes in the order | ||
19 | R G B A | ||
30 | 20 | ||
31 | This is caused by passing the wrong value to the read_memory_func(). | 21 | This isn't the same as the pixman order for either big or little |
32 | The intention is that at this point in the loop the 'cap_buf' buffer | 22 | endian hosts. |
33 | already contains 'csize' bytes of data for the instruction at guest | ||
34 | addr 'pc', and we want to read in an extra 'tsize' bytes. Those | ||
35 | extra bytes are therefore at 'pc + csize', not 'pc'. On the first | ||
36 | time through the loop 'csize' happens to be zero, so the initial read | ||
37 | of 32 bytes into cap_buf is correct and as long as the disassembly | ||
38 | never needs to read more data we return the correct information. | ||
39 | 23 | ||
40 | Use the correct guest address in the call to read_memory_func(). | 24 | The alpha channel is also unnecessary bulk in the output PNG file, |
25 | because there is no alpha information in a screenshot. | ||
26 | |||
27 | To handle the endianness issue, we already define in ui/qemu-pixman.h | ||
28 | various PIXMAN_BE_* and PIXMAN_LE_* values that give consistent | ||
29 | byte-order pixel channel formats. So we can use PIXMAN_BE_r8g8b8 and | ||
30 | PNG_COLOR_TYPE_RGB, which both have an in-memory byte order of | ||
31 | R G B | ||
32 | and 3 bytes per pixel. | ||
33 | |||
34 | (PPM format screenshots get this right; they already use the | ||
35 | PIXMAN_BE_r8g8b8 format.) | ||
41 | 36 | ||
42 | Cc: qemu-stable@nongnu.org | 37 | Cc: qemu-stable@nongnu.org |
43 | Fixes: https://bugs.launchpad.net/qemu/+bug/1900779 | 38 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1622 |
39 | Fixes: 9a0a119a382867 ("Added parameter to take screenshot with screendump as PNG") | ||
44 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 40 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
45 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 41 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
46 | Message-id: 20201022132445.25039-1-peter.maydell@linaro.org | 42 | Message-id: 20230502135548.2451309-1-peter.maydell@linaro.org |
47 | --- | 43 | --- |
48 | disas/capstone.c | 2 +- | 44 | ui/console.c | 4 ++-- |
49 | 1 file changed, 1 insertion(+), 1 deletion(-) | 45 | 1 file changed, 2 insertions(+), 2 deletions(-) |
50 | 46 | ||
51 | diff --git a/disas/capstone.c b/disas/capstone.c | 47 | diff --git a/ui/console.c b/ui/console.c |
52 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
53 | --- a/disas/capstone.c | 49 | --- a/ui/console.c |
54 | +++ b/disas/capstone.c | 50 | +++ b/ui/console.c |
55 | @@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count) | 51 | @@ -XXX,XX +XXX,XX @@ static bool png_save(int fd, pixman_image_t *image, Error **errp) |
56 | 52 | png_struct *png_ptr; | |
57 | /* Make certain that we can make progress. */ | 53 | png_info *info_ptr; |
58 | assert(tsize != 0); | 54 | g_autoptr(pixman_image_t) linebuf = |
59 | - info->read_memory_func(pc, cap_buf + csize, tsize, info); | 55 | - qemu_pixman_linebuf_create(PIXMAN_a8r8g8b8, width); |
60 | + info->read_memory_func(pc + csize, cap_buf + csize, tsize, info); | 56 | + qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); |
61 | csize += tsize; | 57 | uint8_t *buf = (uint8_t *)pixman_image_get_data(linebuf); |
62 | 58 | FILE *f = fdopen(fd, "wb"); | |
63 | if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) { | 59 | int y; |
60 | @@ -XXX,XX +XXX,XX @@ static bool png_save(int fd, pixman_image_t *image, Error **errp) | ||
61 | png_init_io(png_ptr, f); | ||
62 | |||
63 | png_set_IHDR(png_ptr, info_ptr, width, height, 8, | ||
64 | - PNG_COLOR_TYPE_RGB_ALPHA, PNG_INTERLACE_NONE, | ||
65 | + PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE, | ||
66 | PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE); | ||
67 | |||
68 | png_write_info(png_ptr, info_ptr); | ||
64 | -- | 69 | -- |
65 | 2.20.1 | 70 | 2.34.1 |
66 | 71 | ||
67 | 72 | diff view generated by jsdifflib |
1 | The randomness tests in the NPCM7xx RNG test fail intermittently | 1 | In the doc sources, we have a few cross-reference targets with odd |
---|---|---|---|
2 | but fairly frequently. On my machine running the test in a loop: | 2 | names "pcsys_005fxyz". These are the legacy of the semi-automated |
3 | while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done | 3 | conversion of the old info docs to rST (the '005f' is because ASCII |
4 | 0x5f is '_' and the old info link names had underscores in them). | ||
4 | 5 | ||
5 | will fail in less than a minute with an error like: | 6 | Remove the targets which nothing links to, and rename the two targets |
6 | ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs: | 7 | which are used to something a bit more descriptive. |
7 | assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01) | ||
8 | |||
9 | (Failures have been observed on all 4 of the randomness tests, | ||
10 | not just first_byte_runs.) | ||
11 | |||
12 | It's not clear why these tests are failing like this, but intermittent | ||
13 | failures make CI and merge testing awkward, so disable running them | ||
14 | unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when | ||
15 | running the test suite, until we work out the cause. | ||
16 | 8 | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 10 | Message-id: 20230421163642.1151904-1-peter.maydell@linaro.org |
19 | Message-id: 20201102152454.8287-1-peter.maydell@linaro.org | 11 | Reviewed-by: Markus Armbruster <armbru@redhat.com> |
20 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
21 | --- | 12 | --- |
22 | tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++---- | 13 | docs/system/devices/igb.rst | 2 +- |
23 | 1 file changed, 10 insertions(+), 4 deletions(-) | 14 | docs/system/devices/ivshmem.rst | 2 -- |
15 | docs/system/devices/net.rst | 2 +- | ||
16 | docs/system/devices/usb.rst | 2 -- | ||
17 | docs/system/keys.rst | 2 +- | ||
18 | docs/system/linuxboot.rst | 2 +- | ||
19 | docs/system/target-i386.rst | 4 ---- | ||
20 | 7 files changed, 4 insertions(+), 12 deletions(-) | ||
24 | 21 | ||
25 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c | 22 | diff --git a/docs/system/devices/igb.rst b/docs/system/devices/igb.rst |
26 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/tests/qtest/npcm7xx_rng-test.c | 24 | --- a/docs/system/devices/igb.rst |
28 | +++ b/tests/qtest/npcm7xx_rng-test.c | 25 | +++ b/docs/system/devices/igb.rst |
29 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | 26 | @@ -XXX,XX +XXX,XX @@ Using igb |
30 | 27 | ========= | |
31 | qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable); | 28 | |
32 | qtest_add_func("npcm7xx_rng/rosel", test_rosel); | 29 | Using igb should be nothing different from using another network device. See |
33 | - qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit); | 30 | -:ref:`pcsys_005fnetwork` in general. |
34 | - qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); | 31 | +:ref:`Network_emulation` in general. |
35 | - qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit); | 32 | |
36 | - qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); | 33 | However, you may also need to perform additional steps to activate SR-IOV |
37 | + /* | 34 | feature on your guest. For Linux, refer to [4]_. |
38 | + * These tests fail intermittently; only run them on explicit | 35 | diff --git a/docs/system/devices/ivshmem.rst b/docs/system/devices/ivshmem.rst |
39 | + * request until we figure out why. | 36 | index XXXXXXX..XXXXXXX 100644 |
40 | + */ | 37 | --- a/docs/system/devices/ivshmem.rst |
41 | + if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) { | 38 | +++ b/docs/system/devices/ivshmem.rst |
42 | + qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit); | 39 | @@ -XXX,XX +XXX,XX @@ |
43 | + qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); | 40 | -.. _pcsys_005fivshmem: |
44 | + qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit); | 41 | - |
45 | + qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); | 42 | Inter-VM Shared Memory device |
46 | + } | 43 | ----------------------------- |
47 | 44 | ||
48 | qtest_start("-machine npcm750-evb"); | 45 | diff --git a/docs/system/devices/net.rst b/docs/system/devices/net.rst |
49 | ret = g_test_run(); | 46 | index XXXXXXX..XXXXXXX 100644 |
47 | --- a/docs/system/devices/net.rst | ||
48 | +++ b/docs/system/devices/net.rst | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | -.. _pcsys_005fnetwork: | ||
51 | +.. _Network_Emulation: | ||
52 | |||
53 | Network emulation | ||
54 | ----------------- | ||
55 | diff --git a/docs/system/devices/usb.rst b/docs/system/devices/usb.rst | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/docs/system/devices/usb.rst | ||
58 | +++ b/docs/system/devices/usb.rst | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | -.. _pcsys_005fusb: | ||
61 | - | ||
62 | USB emulation | ||
63 | ------------- | ||
64 | |||
65 | diff --git a/docs/system/keys.rst b/docs/system/keys.rst | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/docs/system/keys.rst | ||
68 | +++ b/docs/system/keys.rst | ||
69 | @@ -XXX,XX +XXX,XX @@ | ||
70 | -.. _pcsys_005fkeys: | ||
71 | +.. _GUI_keys: | ||
72 | |||
73 | Keys in the graphical frontends | ||
74 | ------------------------------- | ||
75 | diff --git a/docs/system/linuxboot.rst b/docs/system/linuxboot.rst | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/docs/system/linuxboot.rst | ||
78 | +++ b/docs/system/linuxboot.rst | ||
79 | @@ -XXX,XX +XXX,XX @@ virtual serial port and the QEMU monitor to the console with the | ||
80 | -append "root=/dev/hda console=ttyS0" -nographic | ||
81 | |||
82 | Use Ctrl-a c to switch between the serial console and the monitor (see | ||
83 | -:ref:`pcsys_005fkeys`). | ||
84 | +:ref:`GUI_keys`). | ||
85 | diff --git a/docs/system/target-i386.rst b/docs/system/target-i386.rst | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/docs/system/target-i386.rst | ||
88 | +++ b/docs/system/target-i386.rst | ||
89 | @@ -XXX,XX +XXX,XX @@ | ||
90 | x86 System emulator | ||
91 | ------------------- | ||
92 | |||
93 | -.. _pcsys_005fdevices: | ||
94 | - | ||
95 | Board-specific documentation | ||
96 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
97 | |||
98 | @@ -XXX,XX +XXX,XX @@ Architectural features | ||
99 | i386/sgx | ||
100 | i386/amd-memory-encryption | ||
101 | |||
102 | -.. _pcsys_005freq: | ||
103 | - | ||
104 | OS requirements | ||
105 | ~~~~~~~~~~~~~~~ | ||
106 | |||
50 | -- | 107 | -- |
51 | 2.20.1 | 108 | 2.34.1 |
52 | |||
53 | diff view generated by jsdifflib |
1 | Sphinx 3.2 is pickier than earlier versions about the option:: markup, | 1 | Coverity points out (in CID 1508390) that write_bootloader has |
---|---|---|---|
2 | and complains about our usage in qemu-option-trace.rst: | 2 | some dead code, where we assign to 'p' and then in the following |
3 | line assign to it again. This happened as a result of the | ||
4 | refactoring in commit cd5066f8618b. | ||
3 | 5 | ||
4 | ../../docs/qemu-option-trace.rst.inc:4:Malformed option description | 6 | Fix the dead code by removing the 'void *v' variable entirely and |
5 | '[enable=]PATTERN', should look like "opt", "-opt args", "--opt args", | 7 | instead adding a cast when calling bl_setup_gt64120_jump_kernel(), as |
6 | "/opt args" or "+opt args" | 8 | we do at its other callsite in write_bootloader_nanomips(). |
7 | |||
8 | In this file, we're really trying to document the different parts of | ||
9 | the top-level --trace option, which qemu-nbd.rst and qemu-img.rst | ||
10 | have already introduced with an option:: markup. So it's not right | ||
11 | to use option:: here anyway. Switch to a different markup | ||
12 | (definition lists) which gives about the same formatted output. | ||
13 | |||
14 | (Unlike option::, this markup doesn't produce index entries; but | ||
15 | at the moment we don't do anything much with indexes anyway, and | ||
16 | in any case I think it doesn't make much sense to have individual | ||
17 | index entries for the sub-parts of the --trace option.) | ||
18 | 9 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
21 | Tested-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
22 | Message-id: 20201030174700.7204-3-peter.maydell@linaro.org | ||
23 | --- | 12 | --- |
24 | docs/qemu-option-trace.rst.inc | 6 +++--- | 13 | hw/mips/malta.c | 5 +---- |
25 | 1 file changed, 3 insertions(+), 3 deletions(-) | 14 | 1 file changed, 1 insertion(+), 4 deletions(-) |
26 | 15 | ||
27 | diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc | 16 | diff --git a/hw/mips/malta.c b/hw/mips/malta.c |
28 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/docs/qemu-option-trace.rst.inc | 18 | --- a/hw/mips/malta.c |
30 | +++ b/docs/qemu-option-trace.rst.inc | 19 | +++ b/hw/mips/malta.c |
31 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, |
32 | 21 | uint64_t kernel_entry) | |
33 | Specify tracing options. | 22 | { |
34 | 23 | uint32_t *p; | |
35 | -.. option:: [enable=]PATTERN | 24 | - void *v; |
36 | +``[enable=]PATTERN`` | 25 | |
37 | 26 | /* Small bootloader */ | |
38 | Immediately enable events matching *PATTERN* | 27 | p = (uint32_t *)base; |
39 | (either event name or a globbing pattern). This option is only | 28 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, |
40 | @@ -XXX,XX +XXX,XX @@ Specify tracing options. | 29 | * |
41 | 30 | */ | |
42 | Use :option:`-trace help` to print a list of names of trace points. | 31 | |
43 | 32 | - v = p; | |
44 | -.. option:: events=FILE | 33 | - bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry); |
45 | +``events=FILE`` | 34 | - p = v; |
46 | 35 | + bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); | |
47 | Immediately enable events listed in *FILE*. | 36 | |
48 | The file must contain one event name (as listed in the ``trace-events-all`` | 37 | /* YAMON subroutines */ |
49 | @@ -XXX,XX +XXX,XX @@ Specify tracing options. | 38 | p = (uint32_t *) (base + 0x800); |
50 | available if QEMU has been compiled with the ``simple``, ``log`` or | ||
51 | ``ftrace`` tracing backend. | ||
52 | |||
53 | -.. option:: file=FILE | ||
54 | +``file=FILE`` | ||
55 | |||
56 | Log output traces to *FILE*. | ||
57 | This option is only available if QEMU has been compiled with | ||
58 | -- | 39 | -- |
59 | 2.20.1 | 40 | 2.34.1 |
60 | 41 | ||
61 | 42 | diff view generated by jsdifflib |
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so | 3 | Semihosting has been made a 'default y' entry in Kconfig, which does |
4 | that SVE will not trap to EL3. | 4 | not work because when building --without-default-devices, the |
5 | semihosting code would not be available. | ||
5 | 6 | ||
6 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 7 | Make semihosting unconditional when TCG is present. |
8 | |||
9 | Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only build") | ||
10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20201030151541.11976-1-remi@remlab.net | 12 | Message-id: 20230508181611.2621-2-farosas@suse.de |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | hw/arm/boot.c | 3 +++ | 15 | target/arm/Kconfig | 8 +------- |
12 | 1 file changed, 3 insertions(+) | 16 | 1 file changed, 1 insertion(+), 7 deletions(-) |
13 | 17 | ||
14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 18 | diff --git a/target/arm/Kconfig b/target/arm/Kconfig |
15 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/boot.c | 20 | --- a/target/arm/Kconfig |
17 | +++ b/hw/arm/boot.c | 21 | +++ b/target/arm/Kconfig |
18 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | 22 | @@ -XXX,XX +XXX,XX @@ |
19 | if (cpu_isar_feature(aa64_mte, cpu)) { | 23 | config ARM |
20 | env->cp15.scr_el3 |= SCR_ATA; | 24 | bool |
21 | } | 25 | + select ARM_COMPATIBLE_SEMIHOSTING if TCG |
22 | + if (cpu_isar_feature(aa64_sve, cpu)) { | 26 | |
23 | + env->cp15.cptr_el[3] |= CPTR_EZ; | 27 | config AARCH64 |
24 | + } | 28 | bool |
25 | /* AArch64 kernels never boot in secure mode */ | 29 | select ARM |
26 | assert(!info->secure_boot); | 30 | - |
27 | /* This hook is only supported for AArch32 currently: | 31 | -# This config exists just so we can make SEMIHOSTING default when TCG |
32 | -# is selected without also changing it for other architectures. | ||
33 | -config ARM_SEMIHOSTING | ||
34 | - bool | ||
35 | - default y if TCG && ARM | ||
36 | - select ARM_COMPATIBLE_SEMIHOSTING | ||
28 | -- | 37 | -- |
29 | 2.20.1 | 38 | 2.34.1 |
30 | |||
31 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. | 3 | We cannot allow this config to be disabled at the moment as not all of |
4 | This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): | 4 | the relevant code is protected by it. |
5 | 5 | ||
6 | CID 1432363 (#1 of 1): Unintentional integer overflow: | 6 | Commit 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a |
7 | KVM-only build") moved the CONFIGs of several boards to Kconfig, so it | ||
8 | is now possible that nothing selects ARM_V7M (e.g. when doing a | ||
9 | --without-default-devices build). | ||
7 | 10 | ||
8 | overflow_before_widen: | 11 | Return the CONFIG_ARM_V7M entry to a state where it is always selected |
9 | Potentially overflowing expression 1 << scale with type int | 12 | whenever TCG is available. |
10 | (32 bits, signed) is evaluated using 32-bit arithmetic, and | ||
11 | then used in a context that expects an expression of type | ||
12 | hwaddr (64 bits, unsigned). | ||
13 | 13 | ||
14 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 14 | Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only build") |
15 | Acked-by: Eric Auger <eric.auger@redhat.com> | 15 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
16 | Message-id: 20201030144617.1535064-1-philmd@redhat.com | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Message-id: 20230508181611.2621-3-farosas@suse.de |
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | --- | 19 | --- |
20 | hw/arm/smmuv3.c | 3 ++- | 20 | target/arm/Kconfig | 1 + |
21 | 1 file changed, 2 insertions(+), 1 deletion(-) | 21 | 1 file changed, 1 insertion(+) |
22 | 22 | ||
23 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | 23 | diff --git a/target/arm/Kconfig b/target/arm/Kconfig |
24 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/hw/arm/smmuv3.c | 25 | --- a/target/arm/Kconfig |
26 | +++ b/hw/arm/smmuv3.c | 26 | +++ b/target/arm/Kconfig |
27 | @@ -XXX,XX +XXX,XX @@ | 27 | @@ -XXX,XX +XXX,XX @@ |
28 | */ | 28 | config ARM |
29 | 29 | bool | |
30 | #include "qemu/osdep.h" | 30 | select ARM_COMPATIBLE_SEMIHOSTING if TCG |
31 | +#include "qemu/bitops.h" | 31 | + select ARM_V7M if TCG |
32 | #include "hw/irq.h" | 32 | |
33 | #include "hw/sysbus.h" | 33 | config AARCH64 |
34 | #include "migration/vmstate.h" | 34 | bool |
35 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) | ||
36 | scale = CMD_SCALE(cmd); | ||
37 | num = CMD_NUM(cmd); | ||
38 | ttl = CMD_TTL(cmd); | ||
39 | - num_pages = (num + 1) * (1 << (scale)); | ||
40 | + num_pages = (num + 1) * BIT_ULL(scale); | ||
41 | } | ||
42 | |||
43 | if (type == SMMU_CMD_TLBI_NH_VA) { | ||
44 | -- | 35 | -- |
45 | 2.20.1 | 36 | 2.34.1 |
46 | |||
47 | diff view generated by jsdifflib |
1 | From: AlexChen <alex.chen@huawei.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before | 3 | On a build configured with: --disable-tcg --enable-xen it is possible |
4 | being check if it is valid, which may lead to NULL pointer dereference. | 4 | to produce a QEMU binary with no TCG nor KVM support. Skip the cdrom |
5 | So move the assignment to surface after checking that the omap_lcd is valid | 5 | boot tests if that's the case. |
6 | and move surface_bits_per_pixel(surface) to after the surface assignment. | ||
7 | 6 | ||
8 | Reported-by: Euler Robot <euler.robot@huawei.com> | 7 | Fixes: 0c1ae3ff9d ("tests/qtest: Fix tests when no KVM or TCG are present") |
9 | Signed-off-by: AlexChen <alex.chen@huawei.com> | 8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
10 | Message-id: 5F9CDB8A.9000001@huawei.com | 9 | Reviewed-by: Thomas Huth <thuth@redhat.com> |
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Message-id: 20230508181611.2621-4-farosas@suse.de |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 12 | --- |
14 | hw/display/omap_lcdc.c | 10 +++++++--- | 13 | tests/qtest/cdrom-test.c | 10 ++++++++++ |
15 | 1 file changed, 7 insertions(+), 3 deletions(-) | 14 | 1 file changed, 10 insertions(+) |
16 | 15 | ||
17 | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c | 16 | diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c |
18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/display/omap_lcdc.c | 18 | --- a/tests/qtest/cdrom-test.c |
20 | +++ b/hw/display/omap_lcdc.c | 19 | +++ b/tests/qtest/cdrom-test.c |
21 | @@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) | 20 | @@ -XXX,XX +XXX,XX @@ static void test_cdboot(gconstpointer data) |
22 | static void omap_update_display(void *opaque) | 21 | |
22 | static void add_x86_tests(void) | ||
23 | { | 23 | { |
24 | struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; | 24 | + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) { |
25 | - DisplaySurface *surface = qemu_console_surface(omap_lcd->con); | 25 | + g_test_skip("No KVM or TCG accelerator available, skipping boot tests"); |
26 | + DisplaySurface *surface; | ||
27 | draw_line_func draw_line; | ||
28 | int size, height, first, last; | ||
29 | int width, linesize, step, bpp, frame_offset; | ||
30 | hwaddr frame_base; | ||
31 | |||
32 | - if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable || | ||
33 | - !surface_bits_per_pixel(surface)) { | ||
34 | + if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) { | ||
35 | + return; | 26 | + return; |
36 | + } | 27 | + } |
37 | + | 28 | + |
38 | + surface = qemu_console_surface(omap_lcd->con); | 29 | qtest_add_data_func("cdrom/boot/default", "-cdrom ", test_cdboot); |
39 | + if (!surface_bits_per_pixel(surface)) { | 30 | qtest_add_data_func("cdrom/boot/virtio-scsi", |
40 | return; | 31 | "-device virtio-scsi -device scsi-cd,drive=cdr " |
41 | } | 32 | @@ -XXX,XX +XXX,XX @@ static void add_x86_tests(void) |
42 | 33 | ||
34 | static void add_s390x_tests(void) | ||
35 | { | ||
36 | + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) { | ||
37 | + g_test_skip("No KVM or TCG accelerator available, skipping boot tests"); | ||
38 | + return; | ||
39 | + } | ||
40 | + | ||
41 | qtest_add_data_func("cdrom/boot/default", "-cdrom ", test_cdboot); | ||
42 | qtest_add_data_func("cdrom/boot/virtio-scsi", | ||
43 | "-device virtio-scsi -device scsi-cd,drive=cdr " | ||
43 | -- | 44 | -- |
44 | 2.20.1 | 45 | 2.34.1 |
45 | |||
46 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In check_s2_mmu_setup() we have a check that is attempting to |
---|---|---|---|
2 | implement the part of AArch64.S2MinTxSZ that is specific to when EL1 | ||
3 | is AArch32: | ||
2 | 4 | ||
3 | The only uses of this function are for loading VFP | 5 | if !s1aarch64 then |
4 | single-precision values, and nothing to do with NEON. | 6 | // EL1 is AArch32 |
7 | min_txsz = Min(min_txsz, 24); | ||
5 | 8 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Unfortunately we got this wrong in two ways: |
7 | Message-id: 20201030022618.785675-8-richard.henderson@linaro.org | 10 | |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | (1) The minimum txsz corresponds to a maximum inputsize, but we got |
12 | the sense of the comparison wrong and were faulting for all | ||
13 | inputsizes less than 40 bits | ||
14 | |||
15 | (2) We try to implement this as an extra check that happens after | ||
16 | we've done the same txsz checks we would do for an AArch64 EL1, but | ||
17 | in fact the pseudocode is *loosening* the requirements, so that txsz | ||
18 | values that would fault for an AArch64 EL1 do not fault for AArch32 | ||
19 | EL1, because it does Min(old_min, 24), not Max(old_min, 24). | ||
20 | |||
21 | You can see this also in the text of the Arm ARM in table D8-8, which | ||
22 | shows that where the implemented PA size is less than 40 bits an | ||
23 | AArch32 EL1 is still OK with a configured stage2 T0SZ for a 40 bit | ||
24 | IPA, whereas if EL1 is AArch64 then the T0SZ must be big enough to | ||
25 | constrain the IPA to the implemented PA size. | ||
26 | |||
27 | Because of part (2), we can't do this as a separate check, but | ||
28 | have to integrate it into aa64_va_parameters(). Add a new argument | ||
29 | to that function to indicate that EL1 is 32-bit. All the existing | ||
30 | callsites except the one in get_phys_addr_lpae() can pass 'false', | ||
31 | because they are either doing a lookup for a stage 1 regime or | ||
32 | else they don't care about the tsz/tsz_oob fields. | ||
33 | |||
34 | Cc: qemu-stable@nongnu.org | ||
35 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1627 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 36 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
37 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
38 | Message-id: 20230509092059.3176487-1-peter.maydell@linaro.org | ||
10 | --- | 39 | --- |
11 | target/arm/translate.c | 4 +- | 40 | target/arm/internals.h | 12 +++++++++++- |
12 | target/arm/translate-vfp.c.inc | 184 ++++++++++++++++----------------- | 41 | target/arm/gdbstub64.c | 2 +- |
13 | 2 files changed, 94 insertions(+), 94 deletions(-) | 42 | target/arm/helper.c | 15 +++++++++++++-- |
43 | target/arm/ptw.c | 14 ++------------ | ||
44 | target/arm/tcg/pauth_helper.c | 6 +++--- | ||
45 | 5 files changed, 30 insertions(+), 19 deletions(-) | ||
14 | 46 | ||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 47 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
16 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate.c | 49 | --- a/target/arm/internals.h |
18 | +++ b/target/arm/translate.c | 50 | +++ b/target/arm/internals.h |
19 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg) | 51 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters { |
20 | tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); | 52 | ARMGranuleSize gran : 2; |
53 | } ARMVAParameters; | ||
54 | |||
55 | +/** | ||
56 | + * aa64_va_parameters: Return parameters for an AArch64 virtual address | ||
57 | + * @env: CPU | ||
58 | + * @va: virtual address to look up | ||
59 | + * @mmu_idx: determines translation regime to use | ||
60 | + * @data: true if this is a data access | ||
61 | + * @el1_is_aa32: true if we are asking about stage 2 when EL1 is AArch32 | ||
62 | + * (ignored if @mmu_idx is for a stage 1 regime; only affects tsz/tsz_oob) | ||
63 | + */ | ||
64 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
65 | - ARMMMUIdx mmu_idx, bool data); | ||
66 | + ARMMMUIdx mmu_idx, bool data, | ||
67 | + bool el1_is_aa32); | ||
68 | |||
69 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); | ||
70 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); | ||
71 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/arm/gdbstub64.c | ||
74 | +++ b/target/arm/gdbstub64.c | ||
75 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
76 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
77 | ARMVAParameters param; | ||
78 | |||
79 | - param = aa64_va_parameters(env, -is_high, mmu_idx, is_data); | ||
80 | + param = aa64_va_parameters(env, -is_high, mmu_idx, is_data, false); | ||
81 | return gdb_get_reg64(buf, pauth_ptr_mask(param)); | ||
82 | } | ||
83 | default: | ||
84 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/target/arm/helper.c | ||
87 | +++ b/target/arm/helper.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, | ||
89 | unsigned int page_size_granule, page_shift, num, scale, exponent; | ||
90 | /* Extract one bit to represent the va selector in use. */ | ||
91 | uint64_t select = sextract64(value, 36, 1); | ||
92 | - ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); | ||
93 | + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true, false); | ||
94 | TLBIRange ret = { }; | ||
95 | ARMGranuleSize gran; | ||
96 | |||
97 | @@ -XXX,XX +XXX,XX @@ static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, | ||
21 | } | 98 | } |
22 | 99 | ||
23 | -static inline void neon_load_reg32(TCGv_i32 var, int reg) | 100 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
24 | +static inline void vfp_load_reg32(TCGv_i32 var, int reg) | 101 | - ARMMMUIdx mmu_idx, bool data) |
102 | + ARMMMUIdx mmu_idx, bool data, | ||
103 | + bool el1_is_aa32) | ||
25 | { | 104 | { |
26 | tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); | 105 | uint64_t tcr = regime_tcr(env, mmu_idx); |
27 | } | 106 | bool epd, hpd, tsz_oob, ds, ha, hd; |
28 | 107 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | |
29 | -static inline void neon_store_reg32(TCGv_i32 var, int reg) | ||
30 | +static inline void vfp_store_reg32(TCGv_i32 var, int reg) | ||
31 | { | ||
32 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | ||
33 | } | ||
34 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/translate-vfp.c.inc | ||
37 | +++ b/target/arm/translate-vfp.c.inc | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
39 | frn = tcg_temp_new_i32(); | ||
40 | frm = tcg_temp_new_i32(); | ||
41 | dest = tcg_temp_new_i32(); | ||
42 | - neon_load_reg32(frn, rn); | ||
43 | - neon_load_reg32(frm, rm); | ||
44 | + vfp_load_reg32(frn, rn); | ||
45 | + vfp_load_reg32(frm, rm); | ||
46 | switch (a->cc) { | ||
47 | case 0: /* eq: Z */ | ||
48 | tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, | ||
49 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
50 | if (sz == 1) { | ||
51 | tcg_gen_andi_i32(dest, dest, 0xffff); | ||
52 | } | ||
53 | - neon_store_reg32(dest, rd); | ||
54 | + vfp_store_reg32(dest, rd); | ||
55 | tcg_temp_free_i32(frn); | ||
56 | tcg_temp_free_i32(frm); | ||
57 | tcg_temp_free_i32(dest); | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
59 | TCGv_i32 tcg_res; | ||
60 | tcg_op = tcg_temp_new_i32(); | ||
61 | tcg_res = tcg_temp_new_i32(); | ||
62 | - neon_load_reg32(tcg_op, rm); | ||
63 | + vfp_load_reg32(tcg_op, rm); | ||
64 | if (sz == 1) { | ||
65 | gen_helper_rinth(tcg_res, tcg_op, fpst); | ||
66 | } else { | ||
67 | gen_helper_rints(tcg_res, tcg_op, fpst); | ||
68 | } | ||
69 | - neon_store_reg32(tcg_res, rd); | ||
70 | + vfp_store_reg32(tcg_res, rd); | ||
71 | tcg_temp_free_i32(tcg_op); | ||
72 | tcg_temp_free_i32(tcg_res); | ||
73 | } | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
75 | gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); | ||
76 | } | ||
77 | tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); | ||
78 | - neon_store_reg32(tcg_tmp, rd); | ||
79 | + vfp_store_reg32(tcg_tmp, rd); | ||
80 | tcg_temp_free_i32(tcg_tmp); | ||
81 | tcg_temp_free_i64(tcg_res); | ||
82 | tcg_temp_free_i64(tcg_double); | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
84 | TCGv_i32 tcg_single, tcg_res; | ||
85 | tcg_single = tcg_temp_new_i32(); | ||
86 | tcg_res = tcg_temp_new_i32(); | ||
87 | - neon_load_reg32(tcg_single, rm); | ||
88 | + vfp_load_reg32(tcg_single, rm); | ||
89 | if (sz == 1) { | ||
90 | if (is_signed) { | ||
91 | gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst); | ||
92 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
93 | gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); | ||
94 | } | ||
95 | } | ||
96 | - neon_store_reg32(tcg_res, rd); | ||
97 | + vfp_store_reg32(tcg_res, rd); | ||
98 | tcg_temp_free_i32(tcg_res); | ||
99 | tcg_temp_free_i32(tcg_single); | ||
100 | } | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) | ||
102 | if (a->l) { | ||
103 | /* VFP to general purpose register */ | ||
104 | tmp = tcg_temp_new_i32(); | ||
105 | - neon_load_reg32(tmp, a->vn); | ||
106 | + vfp_load_reg32(tmp, a->vn); | ||
107 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | ||
108 | store_reg(s, a->rt, tmp); | ||
109 | } else { | ||
110 | /* general purpose register to VFP */ | ||
111 | tmp = load_reg(s, a->rt); | ||
112 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | ||
113 | - neon_store_reg32(tmp, a->vn); | ||
114 | + vfp_store_reg32(tmp, a->vn); | ||
115 | tcg_temp_free_i32(tmp); | ||
116 | } | ||
117 | |||
118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) | ||
119 | if (a->l) { | ||
120 | /* VFP to general purpose register */ | ||
121 | tmp = tcg_temp_new_i32(); | ||
122 | - neon_load_reg32(tmp, a->vn); | ||
123 | + vfp_load_reg32(tmp, a->vn); | ||
124 | if (a->rt == 15) { | ||
125 | /* Set the 4 flag bits in the CPSR. */ | ||
126 | gen_set_nzcv(tmp); | ||
127 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) | ||
128 | } else { | ||
129 | /* general purpose register to VFP */ | ||
130 | tmp = load_reg(s, a->rt); | ||
131 | - neon_store_reg32(tmp, a->vn); | ||
132 | + vfp_store_reg32(tmp, a->vn); | ||
133 | tcg_temp_free_i32(tmp); | ||
134 | } | ||
135 | |||
136 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) | ||
137 | if (a->op) { | ||
138 | /* fpreg to gpreg */ | ||
139 | tmp = tcg_temp_new_i32(); | ||
140 | - neon_load_reg32(tmp, a->vm); | ||
141 | + vfp_load_reg32(tmp, a->vm); | ||
142 | store_reg(s, a->rt, tmp); | ||
143 | tmp = tcg_temp_new_i32(); | ||
144 | - neon_load_reg32(tmp, a->vm + 1); | ||
145 | + vfp_load_reg32(tmp, a->vm + 1); | ||
146 | store_reg(s, a->rt2, tmp); | ||
147 | } else { | ||
148 | /* gpreg to fpreg */ | ||
149 | tmp = load_reg(s, a->rt); | ||
150 | - neon_store_reg32(tmp, a->vm); | ||
151 | + vfp_store_reg32(tmp, a->vm); | ||
152 | tcg_temp_free_i32(tmp); | ||
153 | tmp = load_reg(s, a->rt2); | ||
154 | - neon_store_reg32(tmp, a->vm + 1); | ||
155 | + vfp_store_reg32(tmp, a->vm + 1); | ||
156 | tcg_temp_free_i32(tmp); | ||
157 | } | ||
158 | |||
159 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) | ||
160 | if (a->op) { | ||
161 | /* fpreg to gpreg */ | ||
162 | tmp = tcg_temp_new_i32(); | ||
163 | - neon_load_reg32(tmp, a->vm * 2); | ||
164 | + vfp_load_reg32(tmp, a->vm * 2); | ||
165 | store_reg(s, a->rt, tmp); | ||
166 | tmp = tcg_temp_new_i32(); | ||
167 | - neon_load_reg32(tmp, a->vm * 2 + 1); | ||
168 | + vfp_load_reg32(tmp, a->vm * 2 + 1); | ||
169 | store_reg(s, a->rt2, tmp); | ||
170 | } else { | ||
171 | /* gpreg to fpreg */ | ||
172 | tmp = load_reg(s, a->rt); | ||
173 | - neon_store_reg32(tmp, a->vm * 2); | ||
174 | + vfp_store_reg32(tmp, a->vm * 2); | ||
175 | tcg_temp_free_i32(tmp); | ||
176 | tmp = load_reg(s, a->rt2); | ||
177 | - neon_store_reg32(tmp, a->vm * 2 + 1); | ||
178 | + vfp_store_reg32(tmp, a->vm * 2 + 1); | ||
179 | tcg_temp_free_i32(tmp); | ||
180 | } | ||
181 | |||
182 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
183 | tmp = tcg_temp_new_i32(); | ||
184 | if (a->l) { | ||
185 | gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); | ||
186 | - neon_store_reg32(tmp, a->vd); | ||
187 | + vfp_store_reg32(tmp, a->vd); | ||
188 | } else { | ||
189 | - neon_load_reg32(tmp, a->vd); | ||
190 | + vfp_load_reg32(tmp, a->vd); | ||
191 | gen_aa32_st16(s, tmp, addr, get_mem_index(s)); | ||
192 | } | ||
193 | tcg_temp_free_i32(tmp); | ||
194 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
195 | tmp = tcg_temp_new_i32(); | ||
196 | if (a->l) { | ||
197 | gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
198 | - neon_store_reg32(tmp, a->vd); | ||
199 | + vfp_store_reg32(tmp, a->vd); | ||
200 | } else { | ||
201 | - neon_load_reg32(tmp, a->vd); | ||
202 | + vfp_load_reg32(tmp, a->vd); | ||
203 | gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
204 | } | ||
205 | tcg_temp_free_i32(tmp); | ||
206 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) | ||
207 | if (a->l) { | ||
208 | /* load */ | ||
209 | gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
210 | - neon_store_reg32(tmp, a->vd + i); | ||
211 | + vfp_store_reg32(tmp, a->vd + i); | ||
212 | } else { | ||
213 | /* store */ | ||
214 | - neon_load_reg32(tmp, a->vd + i); | ||
215 | + vfp_load_reg32(tmp, a->vd + i); | ||
216 | gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
217 | } | ||
218 | tcg_gen_addi_i32(addr, addr, offset); | ||
219 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
220 | fd = tcg_temp_new_i32(); | ||
221 | fpst = fpstatus_ptr(FPST_FPCR); | ||
222 | |||
223 | - neon_load_reg32(f0, vn); | ||
224 | - neon_load_reg32(f1, vm); | ||
225 | + vfp_load_reg32(f0, vn); | ||
226 | + vfp_load_reg32(f1, vm); | ||
227 | |||
228 | for (;;) { | ||
229 | if (reads_vd) { | ||
230 | - neon_load_reg32(fd, vd); | ||
231 | + vfp_load_reg32(fd, vd); | ||
232 | } | ||
233 | fn(fd, f0, f1, fpst); | ||
234 | - neon_store_reg32(fd, vd); | ||
235 | + vfp_store_reg32(fd, vd); | ||
236 | |||
237 | if (veclen == 0) { | ||
238 | break; | ||
239 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
240 | veclen--; | ||
241 | vd = vfp_advance_sreg(vd, delta_d); | ||
242 | vn = vfp_advance_sreg(vn, delta_d); | ||
243 | - neon_load_reg32(f0, vn); | ||
244 | + vfp_load_reg32(f0, vn); | ||
245 | if (delta_m) { | ||
246 | vm = vfp_advance_sreg(vm, delta_m); | ||
247 | - neon_load_reg32(f1, vm); | ||
248 | + vfp_load_reg32(f1, vm); | ||
249 | } | 108 | } |
250 | } | 109 | } |
251 | 110 | ||
252 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn, | 111 | + if (stage2 && el1_is_aa32) { |
253 | fd = tcg_temp_new_i32(); | 112 | + /* |
254 | fpst = fpstatus_ptr(FPST_FPCR_F16); | 113 | + * For AArch32 EL1 the min txsz (and thus max IPA size) requirements |
255 | 114 | + * are loosened: a configured IPA of 40 bits is permitted even if | |
256 | - neon_load_reg32(f0, vn); | 115 | + * the implemented PA is less than that (and so a 40 bit IPA would |
257 | - neon_load_reg32(f1, vm); | 116 | + * fault for an AArch64 EL1). See R_DTLMN. |
258 | + vfp_load_reg32(f0, vn); | 117 | + */ |
259 | + vfp_load_reg32(f1, vm); | 118 | + min_tsz = MIN(min_tsz, 24); |
260 | 119 | + } | |
261 | if (reads_vd) { | 120 | + |
262 | - neon_load_reg32(fd, vd); | 121 | if (tsz > max_tsz) { |
263 | + vfp_load_reg32(fd, vd); | 122 | tsz = max_tsz; |
264 | } | 123 | tsz_oob = true; |
265 | fn(fd, f0, f1, fpst); | 124 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
266 | - neon_store_reg32(fd, vd); | 125 | index XXXXXXX..XXXXXXX 100644 |
267 | + vfp_store_reg32(fd, vd); | 126 | --- a/target/arm/ptw.c |
268 | 127 | +++ b/target/arm/ptw.c | |
269 | tcg_temp_free_i32(f0); | 128 | @@ -XXX,XX +XXX,XX @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, |
270 | tcg_temp_free_i32(f1); | 129 | |
271 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | 130 | sl0 = extract32(tcr, 6, 2); |
272 | f0 = tcg_temp_new_i32(); | 131 | if (is_aa64) { |
273 | fd = tcg_temp_new_i32(); | 132 | - /* |
274 | 133 | - * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of | |
275 | - neon_load_reg32(f0, vm); | 134 | - * get_phys_addr_lpae, that used aa64_va_parameters which apply |
276 | + vfp_load_reg32(f0, vm); | 135 | - * to aarch64. If Stage1 is aarch32, the min_txsz is larger. |
277 | 136 | - * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to | |
278 | for (;;) { | 137 | - * inputsize is 64 - 24 = 40. |
279 | fn(fd, f0); | 138 | - */ |
280 | - neon_store_reg32(fd, vd); | 139 | - if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { |
281 | + vfp_store_reg32(fd, vd); | 140 | - goto fail; |
282 | 141 | - } | |
283 | if (veclen == 0) { | 142 | - |
284 | break; | 143 | /* |
285 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | 144 | * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, |
286 | /* single source one-many */ | 145 | * so interleave AArch64.S2StartLevel. |
287 | while (veclen--) { | 146 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
288 | vd = vfp_advance_sreg(vd, delta_d); | 147 | int ps; |
289 | - neon_store_reg32(fd, vd); | 148 | |
290 | + vfp_store_reg32(fd, vd); | 149 | param = aa64_va_parameters(env, address, mmu_idx, |
291 | } | 150 | - access_type != MMU_INST_FETCH); |
292 | break; | 151 | + access_type != MMU_INST_FETCH, |
293 | } | 152 | + !arm_el_is_aa64(env, 1)); |
294 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | 153 | level = 0; |
295 | veclen--; | 154 | |
296 | vd = vfp_advance_sreg(vd, delta_d); | 155 | /* |
297 | vm = vfp_advance_sreg(vm, delta_m); | 156 | diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c |
298 | - neon_load_reg32(f0, vm); | 157 | index XXXXXXX..XXXXXXX 100644 |
299 | + vfp_load_reg32(f0, vm); | 158 | --- a/target/arm/tcg/pauth_helper.c |
300 | } | 159 | +++ b/target/arm/tcg/pauth_helper.c |
301 | 160 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, | |
302 | tcg_temp_free_i32(f0); | 161 | ARMPACKey *key, bool data) |
303 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | 162 | { |
304 | } | 163 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); |
305 | 164 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); | |
306 | f0 = tcg_temp_new_i32(); | 165 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); |
307 | - neon_load_reg32(f0, vm); | 166 | uint64_t pac, ext_ptr, ext, test; |
308 | + vfp_load_reg32(f0, vm); | 167 | int bot_bit, top_bit; |
309 | fn(f0, f0); | 168 | |
310 | - neon_store_reg32(f0, vd); | 169 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, |
311 | + vfp_store_reg32(f0, vd); | 170 | ARMPACKey *key, bool data, int keynumber) |
312 | tcg_temp_free_i32(f0); | 171 | { |
313 | 172 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | |
314 | return true; | 173 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); |
315 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | 174 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); |
316 | vm = tcg_temp_new_i32(); | 175 | int bot_bit, top_bit; |
317 | vd = tcg_temp_new_i32(); | 176 | uint64_t pac, orig_ptr, test; |
318 | 177 | ||
319 | - neon_load_reg32(vn, a->vn); | 178 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, |
320 | - neon_load_reg32(vm, a->vm); | 179 | static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) |
321 | + vfp_load_reg32(vn, a->vn); | 180 | { |
322 | + vfp_load_reg32(vm, a->vm); | 181 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); |
323 | if (neg_n) { | 182 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); |
324 | /* VFNMS, VFMS */ | 183 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); |
325 | gen_helper_vfp_negh(vn, vn); | 184 | |
326 | } | 185 | return pauth_original_ptr(ptr, param); |
327 | - neon_load_reg32(vd, a->vd); | ||
328 | + vfp_load_reg32(vd, a->vd); | ||
329 | if (neg_d) { | ||
330 | /* VFNMA, VFNMS */ | ||
331 | gen_helper_vfp_negh(vd, vd); | ||
332 | } | ||
333 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
334 | gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst); | ||
335 | - neon_store_reg32(vd, a->vd); | ||
336 | + vfp_store_reg32(vd, a->vd); | ||
337 | |||
338 | tcg_temp_free_ptr(fpst); | ||
339 | tcg_temp_free_i32(vn); | ||
340 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | ||
341 | vm = tcg_temp_new_i32(); | ||
342 | vd = tcg_temp_new_i32(); | ||
343 | |||
344 | - neon_load_reg32(vn, a->vn); | ||
345 | - neon_load_reg32(vm, a->vm); | ||
346 | + vfp_load_reg32(vn, a->vn); | ||
347 | + vfp_load_reg32(vm, a->vm); | ||
348 | if (neg_n) { | ||
349 | /* VFNMS, VFMS */ | ||
350 | gen_helper_vfp_negs(vn, vn); | ||
351 | } | ||
352 | - neon_load_reg32(vd, a->vd); | ||
353 | + vfp_load_reg32(vd, a->vd); | ||
354 | if (neg_d) { | ||
355 | /* VFNMA, VFNMS */ | ||
356 | gen_helper_vfp_negs(vd, vd); | ||
357 | } | ||
358 | fpst = fpstatus_ptr(FPST_FPCR); | ||
359 | gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); | ||
360 | - neon_store_reg32(vd, a->vd); | ||
361 | + vfp_store_reg32(vd, a->vd); | ||
362 | |||
363 | tcg_temp_free_ptr(fpst); | ||
364 | tcg_temp_free_i32(vn); | ||
365 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
366 | } | ||
367 | |||
368 | fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm)); | ||
369 | - neon_store_reg32(fd, a->vd); | ||
370 | + vfp_store_reg32(fd, a->vd); | ||
371 | tcg_temp_free_i32(fd); | ||
372 | return true; | ||
373 | } | ||
374 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
375 | fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); | ||
376 | |||
377 | for (;;) { | ||
378 | - neon_store_reg32(fd, vd); | ||
379 | + vfp_store_reg32(fd, vd); | ||
380 | |||
381 | if (veclen == 0) { | ||
382 | break; | ||
383 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a) | ||
384 | vd = tcg_temp_new_i32(); | ||
385 | vm = tcg_temp_new_i32(); | ||
386 | |||
387 | - neon_load_reg32(vd, a->vd); | ||
388 | + vfp_load_reg32(vd, a->vd); | ||
389 | if (a->z) { | ||
390 | tcg_gen_movi_i32(vm, 0); | ||
391 | } else { | ||
392 | - neon_load_reg32(vm, a->vm); | ||
393 | + vfp_load_reg32(vm, a->vm); | ||
394 | } | ||
395 | |||
396 | if (a->e) { | ||
397 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a) | ||
398 | vd = tcg_temp_new_i32(); | ||
399 | vm = tcg_temp_new_i32(); | ||
400 | |||
401 | - neon_load_reg32(vd, a->vd); | ||
402 | + vfp_load_reg32(vd, a->vd); | ||
403 | if (a->z) { | ||
404 | tcg_gen_movi_i32(vm, 0); | ||
405 | } else { | ||
406 | - neon_load_reg32(vm, a->vm); | ||
407 | + vfp_load_reg32(vm, a->vm); | ||
408 | } | ||
409 | |||
410 | if (a->e) { | ||
411 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a) | ||
412 | /* The T bit tells us if we want the low or high 16 bits of Vm */ | ||
413 | tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); | ||
414 | gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); | ||
415 | - neon_store_reg32(tmp, a->vd); | ||
416 | + vfp_store_reg32(tmp, a->vd); | ||
417 | tcg_temp_free_i32(ahp_mode); | ||
418 | tcg_temp_free_ptr(fpst); | ||
419 | tcg_temp_free_i32(tmp); | ||
420 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) | ||
421 | ahp_mode = get_ahp_flag(); | ||
422 | tmp = tcg_temp_new_i32(); | ||
423 | |||
424 | - neon_load_reg32(tmp, a->vm); | ||
425 | + vfp_load_reg32(tmp, a->vm); | ||
426 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); | ||
427 | tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); | ||
428 | tcg_temp_free_i32(ahp_mode); | ||
429 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a) | ||
430 | } | ||
431 | |||
432 | tmp = tcg_temp_new_i32(); | ||
433 | - neon_load_reg32(tmp, a->vm); | ||
434 | + vfp_load_reg32(tmp, a->vm); | ||
435 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
436 | gen_helper_rinth(tmp, tmp, fpst); | ||
437 | - neon_store_reg32(tmp, a->vd); | ||
438 | + vfp_store_reg32(tmp, a->vd); | ||
439 | tcg_temp_free_ptr(fpst); | ||
440 | tcg_temp_free_i32(tmp); | ||
441 | return true; | ||
442 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) | ||
443 | } | ||
444 | |||
445 | tmp = tcg_temp_new_i32(); | ||
446 | - neon_load_reg32(tmp, a->vm); | ||
447 | + vfp_load_reg32(tmp, a->vm); | ||
448 | fpst = fpstatus_ptr(FPST_FPCR); | ||
449 | gen_helper_rints(tmp, tmp, fpst); | ||
450 | - neon_store_reg32(tmp, a->vd); | ||
451 | + vfp_store_reg32(tmp, a->vd); | ||
452 | tcg_temp_free_ptr(fpst); | ||
453 | tcg_temp_free_i32(tmp); | ||
454 | return true; | ||
455 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a) | ||
456 | } | ||
457 | |||
458 | tmp = tcg_temp_new_i32(); | ||
459 | - neon_load_reg32(tmp, a->vm); | ||
460 | + vfp_load_reg32(tmp, a->vm); | ||
461 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
462 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
463 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
464 | gen_helper_rinth(tmp, tmp, fpst); | ||
465 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
466 | - neon_store_reg32(tmp, a->vd); | ||
467 | + vfp_store_reg32(tmp, a->vd); | ||
468 | tcg_temp_free_ptr(fpst); | ||
469 | tcg_temp_free_i32(tcg_rmode); | ||
470 | tcg_temp_free_i32(tmp); | ||
471 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) | ||
472 | } | ||
473 | |||
474 | tmp = tcg_temp_new_i32(); | ||
475 | - neon_load_reg32(tmp, a->vm); | ||
476 | + vfp_load_reg32(tmp, a->vm); | ||
477 | fpst = fpstatus_ptr(FPST_FPCR); | ||
478 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
479 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
480 | gen_helper_rints(tmp, tmp, fpst); | ||
481 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
482 | - neon_store_reg32(tmp, a->vd); | ||
483 | + vfp_store_reg32(tmp, a->vd); | ||
484 | tcg_temp_free_ptr(fpst); | ||
485 | tcg_temp_free_i32(tcg_rmode); | ||
486 | tcg_temp_free_i32(tmp); | ||
487 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a) | ||
488 | } | ||
489 | |||
490 | tmp = tcg_temp_new_i32(); | ||
491 | - neon_load_reg32(tmp, a->vm); | ||
492 | + vfp_load_reg32(tmp, a->vm); | ||
493 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
494 | gen_helper_rinth_exact(tmp, tmp, fpst); | ||
495 | - neon_store_reg32(tmp, a->vd); | ||
496 | + vfp_store_reg32(tmp, a->vd); | ||
497 | tcg_temp_free_ptr(fpst); | ||
498 | tcg_temp_free_i32(tmp); | ||
499 | return true; | ||
500 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) | ||
501 | } | ||
502 | |||
503 | tmp = tcg_temp_new_i32(); | ||
504 | - neon_load_reg32(tmp, a->vm); | ||
505 | + vfp_load_reg32(tmp, a->vm); | ||
506 | fpst = fpstatus_ptr(FPST_FPCR); | ||
507 | gen_helper_rints_exact(tmp, tmp, fpst); | ||
508 | - neon_store_reg32(tmp, a->vd); | ||
509 | + vfp_store_reg32(tmp, a->vd); | ||
510 | tcg_temp_free_ptr(fpst); | ||
511 | tcg_temp_free_i32(tmp); | ||
512 | return true; | ||
513 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
514 | |||
515 | vm = tcg_temp_new_i32(); | ||
516 | vd = tcg_temp_new_i64(); | ||
517 | - neon_load_reg32(vm, a->vm); | ||
518 | + vfp_load_reg32(vm, a->vm); | ||
519 | gen_helper_vfp_fcvtds(vd, vm, cpu_env); | ||
520 | neon_store_reg64(vd, a->vd); | ||
521 | tcg_temp_free_i32(vm); | ||
522 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
523 | vm = tcg_temp_new_i64(); | ||
524 | neon_load_reg64(vm, a->vm); | ||
525 | gen_helper_vfp_fcvtsd(vd, vm, cpu_env); | ||
526 | - neon_store_reg32(vd, a->vd); | ||
527 | + vfp_store_reg32(vd, a->vd); | ||
528 | tcg_temp_free_i32(vd); | ||
529 | tcg_temp_free_i64(vm); | ||
530 | return true; | ||
531 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) | ||
532 | } | ||
533 | |||
534 | vm = tcg_temp_new_i32(); | ||
535 | - neon_load_reg32(vm, a->vm); | ||
536 | + vfp_load_reg32(vm, a->vm); | ||
537 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
538 | if (a->s) { | ||
539 | /* i32 -> f16 */ | ||
540 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) | ||
541 | /* u32 -> f16 */ | ||
542 | gen_helper_vfp_uitoh(vm, vm, fpst); | ||
543 | } | ||
544 | - neon_store_reg32(vm, a->vd); | ||
545 | + vfp_store_reg32(vm, a->vd); | ||
546 | tcg_temp_free_i32(vm); | ||
547 | tcg_temp_free_ptr(fpst); | ||
548 | return true; | ||
549 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
550 | } | ||
551 | |||
552 | vm = tcg_temp_new_i32(); | ||
553 | - neon_load_reg32(vm, a->vm); | ||
554 | + vfp_load_reg32(vm, a->vm); | ||
555 | fpst = fpstatus_ptr(FPST_FPCR); | ||
556 | if (a->s) { | ||
557 | /* i32 -> f32 */ | ||
558 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
559 | /* u32 -> f32 */ | ||
560 | gen_helper_vfp_uitos(vm, vm, fpst); | ||
561 | } | ||
562 | - neon_store_reg32(vm, a->vd); | ||
563 | + vfp_store_reg32(vm, a->vd); | ||
564 | tcg_temp_free_i32(vm); | ||
565 | tcg_temp_free_ptr(fpst); | ||
566 | return true; | ||
567 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
568 | |||
569 | vm = tcg_temp_new_i32(); | ||
570 | vd = tcg_temp_new_i64(); | ||
571 | - neon_load_reg32(vm, a->vm); | ||
572 | + vfp_load_reg32(vm, a->vm); | ||
573 | fpst = fpstatus_ptr(FPST_FPCR); | ||
574 | if (a->s) { | ||
575 | /* i32 -> f64 */ | ||
576 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
577 | vd = tcg_temp_new_i32(); | ||
578 | neon_load_reg64(vm, a->vm); | ||
579 | gen_helper_vjcvt(vd, vm, cpu_env); | ||
580 | - neon_store_reg32(vd, a->vd); | ||
581 | + vfp_store_reg32(vd, a->vd); | ||
582 | tcg_temp_free_i64(vm); | ||
583 | tcg_temp_free_i32(vd); | ||
584 | return true; | ||
585 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
586 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
587 | |||
588 | vd = tcg_temp_new_i32(); | ||
589 | - neon_load_reg32(vd, a->vd); | ||
590 | + vfp_load_reg32(vd, a->vd); | ||
591 | |||
592 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
593 | shift = tcg_const_i32(frac_bits); | ||
594 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
595 | g_assert_not_reached(); | ||
596 | } | ||
597 | |||
598 | - neon_store_reg32(vd, a->vd); | ||
599 | + vfp_store_reg32(vd, a->vd); | ||
600 | tcg_temp_free_i32(vd); | ||
601 | tcg_temp_free_i32(shift); | ||
602 | tcg_temp_free_ptr(fpst); | ||
603 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
604 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
605 | |||
606 | vd = tcg_temp_new_i32(); | ||
607 | - neon_load_reg32(vd, a->vd); | ||
608 | + vfp_load_reg32(vd, a->vd); | ||
609 | |||
610 | fpst = fpstatus_ptr(FPST_FPCR); | ||
611 | shift = tcg_const_i32(frac_bits); | ||
612 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
613 | g_assert_not_reached(); | ||
614 | } | ||
615 | |||
616 | - neon_store_reg32(vd, a->vd); | ||
617 | + vfp_store_reg32(vd, a->vd); | ||
618 | tcg_temp_free_i32(vd); | ||
619 | tcg_temp_free_i32(shift); | ||
620 | tcg_temp_free_ptr(fpst); | ||
621 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
622 | |||
623 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
624 | vm = tcg_temp_new_i32(); | ||
625 | - neon_load_reg32(vm, a->vm); | ||
626 | + vfp_load_reg32(vm, a->vm); | ||
627 | |||
628 | if (a->s) { | ||
629 | if (a->rz) { | ||
630 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
631 | gen_helper_vfp_touih(vm, vm, fpst); | ||
632 | } | ||
633 | } | ||
634 | - neon_store_reg32(vm, a->vd); | ||
635 | + vfp_store_reg32(vm, a->vd); | ||
636 | tcg_temp_free_i32(vm); | ||
637 | tcg_temp_free_ptr(fpst); | ||
638 | return true; | ||
639 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
640 | |||
641 | fpst = fpstatus_ptr(FPST_FPCR); | ||
642 | vm = tcg_temp_new_i32(); | ||
643 | - neon_load_reg32(vm, a->vm); | ||
644 | + vfp_load_reg32(vm, a->vm); | ||
645 | |||
646 | if (a->s) { | ||
647 | if (a->rz) { | ||
648 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
649 | gen_helper_vfp_touis(vm, vm, fpst); | ||
650 | } | ||
651 | } | ||
652 | - neon_store_reg32(vm, a->vd); | ||
653 | + vfp_store_reg32(vm, a->vd); | ||
654 | tcg_temp_free_i32(vm); | ||
655 | tcg_temp_free_ptr(fpst); | ||
656 | return true; | ||
657 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
658 | gen_helper_vfp_touid(vd, vm, fpst); | ||
659 | } | ||
660 | } | ||
661 | - neon_store_reg32(vd, a->vd); | ||
662 | + vfp_store_reg32(vd, a->vd); | ||
663 | tcg_temp_free_i32(vd); | ||
664 | tcg_temp_free_i64(vm); | ||
665 | tcg_temp_free_ptr(fpst); | ||
666 | @@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a) | ||
667 | /* Insert low half of Vm into high half of Vd */ | ||
668 | rm = tcg_temp_new_i32(); | ||
669 | rd = tcg_temp_new_i32(); | ||
670 | - neon_load_reg32(rm, a->vm); | ||
671 | - neon_load_reg32(rd, a->vd); | ||
672 | + vfp_load_reg32(rm, a->vm); | ||
673 | + vfp_load_reg32(rd, a->vd); | ||
674 | tcg_gen_deposit_i32(rd, rd, rm, 16, 16); | ||
675 | - neon_store_reg32(rd, a->vd); | ||
676 | + vfp_store_reg32(rd, a->vd); | ||
677 | tcg_temp_free_i32(rm); | ||
678 | tcg_temp_free_i32(rd); | ||
679 | return true; | ||
680 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a) | ||
681 | |||
682 | /* Set Vd to high half of Vm */ | ||
683 | rm = tcg_temp_new_i32(); | ||
684 | - neon_load_reg32(rm, a->vm); | ||
685 | + vfp_load_reg32(rm, a->vm); | ||
686 | tcg_gen_shri_i32(rm, rm, 16); | ||
687 | - neon_store_reg32(rm, a->vd); | ||
688 | + vfp_store_reg32(rm, a->vd); | ||
689 | tcg_temp_free_i32(rm); | ||
690 | return true; | ||
691 | } | 186 | } |
692 | -- | 187 | -- |
693 | 2.20.1 | 188 | 2.34.1 |
694 | |||
695 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | Replace all uses of neon_load/store_reg64 within translate-neon.c.inc. | ||
4 | |||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20201030022618.785675-9-richard.henderson@linaro.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/translate.c | 26 +++++++++ | ||
11 | target/arm/translate-neon.c.inc | 94 ++++++++++++++++----------------- | ||
12 | 2 files changed, 73 insertions(+), 47 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate.c | ||
17 | +++ b/target/arm/translate.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
19 | } | ||
20 | } | ||
21 | |||
22 | +static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
23 | +{ | ||
24 | + long off = neon_element_offset(reg, ele, memop); | ||
25 | + | ||
26 | + switch (memop) { | ||
27 | + case MO_Q: | ||
28 | + tcg_gen_ld_i64(dest, cpu_env, off); | ||
29 | + break; | ||
30 | + default: | ||
31 | + g_assert_not_reached(); | ||
32 | + } | ||
33 | +} | ||
34 | + | ||
35 | static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
36 | { | ||
37 | long off = neon_element_offset(reg, ele, memop); | ||
38 | @@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
39 | } | ||
40 | } | ||
41 | |||
42 | +static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
43 | +{ | ||
44 | + long off = neon_element_offset(reg, ele, memop); | ||
45 | + | ||
46 | + switch (memop) { | ||
47 | + case MO_64: | ||
48 | + tcg_gen_st_i64(src, cpu_env, off); | ||
49 | + break; | ||
50 | + default: | ||
51 | + g_assert_not_reached(); | ||
52 | + } | ||
53 | +} | ||
54 | + | ||
55 | static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | ||
56 | { | ||
57 | TCGv_ptr ret = tcg_temp_new_ptr(); | ||
58 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/translate-neon.c.inc | ||
61 | +++ b/target/arm/translate-neon.c.inc | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, | ||
63 | for (pass = 0; pass < a->q + 1; pass++) { | ||
64 | TCGv_i64 tmp = tcg_temp_new_i64(); | ||
65 | |||
66 | - neon_load_reg64(tmp, a->vm + pass); | ||
67 | + read_neon_element64(tmp, a->vm, pass, MO_64); | ||
68 | fn(tmp, cpu_env, tmp, constimm); | ||
69 | - neon_store_reg64(tmp, a->vd + pass); | ||
70 | + write_neon_element64(tmp, a->vd, pass, MO_64); | ||
71 | tcg_temp_free_i64(tmp); | ||
72 | } | ||
73 | tcg_temp_free_i64(constimm); | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, | ||
75 | rd = tcg_temp_new_i32(); | ||
76 | |||
77 | /* Load both inputs first to avoid potential overwrite if rm == rd */ | ||
78 | - neon_load_reg64(rm1, a->vm); | ||
79 | - neon_load_reg64(rm2, a->vm + 1); | ||
80 | + read_neon_element64(rm1, a->vm, 0, MO_64); | ||
81 | + read_neon_element64(rm2, a->vm, 1, MO_64); | ||
82 | |||
83 | shiftfn(rm1, rm1, constimm); | ||
84 | narrowfn(rd, cpu_env, rm1); | ||
85 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
86 | tcg_gen_shli_i64(tmp, tmp, a->shift); | ||
87 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | ||
88 | } | ||
89 | - neon_store_reg64(tmp, a->vd); | ||
90 | + write_neon_element64(tmp, a->vd, 0, MO_64); | ||
91 | |||
92 | widenfn(tmp, rm1); | ||
93 | tcg_temp_free_i32(rm1); | ||
94 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
95 | tcg_gen_shli_i64(tmp, tmp, a->shift); | ||
96 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | ||
97 | } | ||
98 | - neon_store_reg64(tmp, a->vd + 1); | ||
99 | + write_neon_element64(tmp, a->vd, 1, MO_64); | ||
100 | tcg_temp_free_i64(tmp); | ||
101 | return true; | ||
102 | } | ||
103 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
104 | rm_64 = tcg_temp_new_i64(); | ||
105 | |||
106 | if (src1_wide) { | ||
107 | - neon_load_reg64(rn0_64, a->vn); | ||
108 | + read_neon_element64(rn0_64, a->vn, 0, MO_64); | ||
109 | } else { | ||
110 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
111 | read_neon_element32(tmp, a->vn, 0, MO_32); | ||
112 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
113 | * avoid incorrect results if a narrow input overlaps with the result. | ||
114 | */ | ||
115 | if (src1_wide) { | ||
116 | - neon_load_reg64(rn1_64, a->vn + 1); | ||
117 | + read_neon_element64(rn1_64, a->vn, 1, MO_64); | ||
118 | } else { | ||
119 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
120 | read_neon_element32(tmp, a->vn, 1, MO_32); | ||
121 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
122 | rm = tcg_temp_new_i32(); | ||
123 | read_neon_element32(rm, a->vm, 1, MO_32); | ||
124 | |||
125 | - neon_store_reg64(rn0_64, a->vd); | ||
126 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
127 | |||
128 | widenfn(rm_64, rm); | ||
129 | tcg_temp_free_i32(rm); | ||
130 | opfn(rn1_64, rn1_64, rm_64); | ||
131 | - neon_store_reg64(rn1_64, a->vd + 1); | ||
132 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
133 | |||
134 | tcg_temp_free_i64(rn0_64); | ||
135 | tcg_temp_free_i64(rn1_64); | ||
136 | @@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | ||
137 | rd0 = tcg_temp_new_i32(); | ||
138 | rd1 = tcg_temp_new_i32(); | ||
139 | |||
140 | - neon_load_reg64(rn_64, a->vn); | ||
141 | - neon_load_reg64(rm_64, a->vm); | ||
142 | + read_neon_element64(rn_64, a->vn, 0, MO_64); | ||
143 | + read_neon_element64(rm_64, a->vm, 0, MO_64); | ||
144 | |||
145 | opfn(rn_64, rn_64, rm_64); | ||
146 | |||
147 | narrowfn(rd0, rn_64); | ||
148 | |||
149 | - neon_load_reg64(rn_64, a->vn + 1); | ||
150 | - neon_load_reg64(rm_64, a->vm + 1); | ||
151 | + read_neon_element64(rn_64, a->vn, 1, MO_64); | ||
152 | + read_neon_element64(rm_64, a->vm, 1, MO_64); | ||
153 | |||
154 | opfn(rn_64, rn_64, rm_64); | ||
155 | |||
156 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
157 | /* Don't store results until after all loads: they might overlap */ | ||
158 | if (accfn) { | ||
159 | tmp = tcg_temp_new_i64(); | ||
160 | - neon_load_reg64(tmp, a->vd); | ||
161 | + read_neon_element64(tmp, a->vd, 0, MO_64); | ||
162 | accfn(tmp, tmp, rd0); | ||
163 | - neon_store_reg64(tmp, a->vd); | ||
164 | - neon_load_reg64(tmp, a->vd + 1); | ||
165 | + write_neon_element64(tmp, a->vd, 0, MO_64); | ||
166 | + read_neon_element64(tmp, a->vd, 1, MO_64); | ||
167 | accfn(tmp, tmp, rd1); | ||
168 | - neon_store_reg64(tmp, a->vd + 1); | ||
169 | + write_neon_element64(tmp, a->vd, 1, MO_64); | ||
170 | tcg_temp_free_i64(tmp); | ||
171 | } else { | ||
172 | - neon_store_reg64(rd0, a->vd); | ||
173 | - neon_store_reg64(rd1, a->vd + 1); | ||
174 | + write_neon_element64(rd0, a->vd, 0, MO_64); | ||
175 | + write_neon_element64(rd1, a->vd, 1, MO_64); | ||
176 | } | ||
177 | |||
178 | tcg_temp_free_i64(rd0); | ||
179 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
180 | |||
181 | if (accfn) { | ||
182 | TCGv_i64 t64 = tcg_temp_new_i64(); | ||
183 | - neon_load_reg64(t64, a->vd); | ||
184 | + read_neon_element64(t64, a->vd, 0, MO_64); | ||
185 | accfn(t64, t64, rn0_64); | ||
186 | - neon_store_reg64(t64, a->vd); | ||
187 | - neon_load_reg64(t64, a->vd + 1); | ||
188 | + write_neon_element64(t64, a->vd, 0, MO_64); | ||
189 | + read_neon_element64(t64, a->vd, 1, MO_64); | ||
190 | accfn(t64, t64, rn1_64); | ||
191 | - neon_store_reg64(t64, a->vd + 1); | ||
192 | + write_neon_element64(t64, a->vd, 1, MO_64); | ||
193 | tcg_temp_free_i64(t64); | ||
194 | } else { | ||
195 | - neon_store_reg64(rn0_64, a->vd); | ||
196 | - neon_store_reg64(rn1_64, a->vd + 1); | ||
197 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
198 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
199 | } | ||
200 | tcg_temp_free_i64(rn0_64); | ||
201 | tcg_temp_free_i64(rn1_64); | ||
202 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
203 | right = tcg_temp_new_i64(); | ||
204 | dest = tcg_temp_new_i64(); | ||
205 | |||
206 | - neon_load_reg64(right, a->vn); | ||
207 | - neon_load_reg64(left, a->vm); | ||
208 | + read_neon_element64(right, a->vn, 0, MO_64); | ||
209 | + read_neon_element64(left, a->vm, 0, MO_64); | ||
210 | tcg_gen_extract2_i64(dest, right, left, a->imm * 8); | ||
211 | - neon_store_reg64(dest, a->vd); | ||
212 | + write_neon_element64(dest, a->vd, 0, MO_64); | ||
213 | |||
214 | tcg_temp_free_i64(left); | ||
215 | tcg_temp_free_i64(right); | ||
216 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
217 | destright = tcg_temp_new_i64(); | ||
218 | |||
219 | if (a->imm < 8) { | ||
220 | - neon_load_reg64(right, a->vn); | ||
221 | - neon_load_reg64(middle, a->vn + 1); | ||
222 | + read_neon_element64(right, a->vn, 0, MO_64); | ||
223 | + read_neon_element64(middle, a->vn, 1, MO_64); | ||
224 | tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); | ||
225 | - neon_load_reg64(left, a->vm); | ||
226 | + read_neon_element64(left, a->vm, 0, MO_64); | ||
227 | tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); | ||
228 | } else { | ||
229 | - neon_load_reg64(right, a->vn + 1); | ||
230 | - neon_load_reg64(middle, a->vm); | ||
231 | + read_neon_element64(right, a->vn, 1, MO_64); | ||
232 | + read_neon_element64(middle, a->vm, 0, MO_64); | ||
233 | tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8); | ||
234 | - neon_load_reg64(left, a->vm + 1); | ||
235 | + read_neon_element64(left, a->vm, 1, MO_64); | ||
236 | tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); | ||
237 | } | ||
238 | |||
239 | - neon_store_reg64(destright, a->vd); | ||
240 | - neon_store_reg64(destleft, a->vd + 1); | ||
241 | + write_neon_element64(destright, a->vd, 0, MO_64); | ||
242 | + write_neon_element64(destleft, a->vd, 1, MO_64); | ||
243 | |||
244 | tcg_temp_free_i64(destright); | ||
245 | tcg_temp_free_i64(destleft); | ||
246 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
247 | |||
248 | if (accfn) { | ||
249 | TCGv_i64 tmp64 = tcg_temp_new_i64(); | ||
250 | - neon_load_reg64(tmp64, a->vd + pass); | ||
251 | + read_neon_element64(tmp64, a->vd, pass, MO_64); | ||
252 | accfn(rd_64, tmp64, rd_64); | ||
253 | tcg_temp_free_i64(tmp64); | ||
254 | } | ||
255 | - neon_store_reg64(rd_64, a->vd + pass); | ||
256 | + write_neon_element64(rd_64, a->vd, pass, MO_64); | ||
257 | tcg_temp_free_i64(rd_64); | ||
258 | } | ||
259 | return true; | ||
260 | @@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
261 | rd0 = tcg_temp_new_i32(); | ||
262 | rd1 = tcg_temp_new_i32(); | ||
263 | |||
264 | - neon_load_reg64(rm, a->vm); | ||
265 | + read_neon_element64(rm, a->vm, 0, MO_64); | ||
266 | narrowfn(rd0, cpu_env, rm); | ||
267 | - neon_load_reg64(rm, a->vm + 1); | ||
268 | + read_neon_element64(rm, a->vm, 1, MO_64); | ||
269 | narrowfn(rd1, cpu_env, rm); | ||
270 | write_neon_element32(rd0, a->vd, 0, MO_32); | ||
271 | write_neon_element32(rd1, a->vd, 1, MO_32); | ||
272 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
273 | |||
274 | widenfn(rd, rm0); | ||
275 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
276 | - neon_store_reg64(rd, a->vd); | ||
277 | + write_neon_element64(rd, a->vd, 0, MO_64); | ||
278 | widenfn(rd, rm1); | ||
279 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
280 | - neon_store_reg64(rd, a->vd + 1); | ||
281 | + write_neon_element64(rd, a->vd, 1, MO_64); | ||
282 | |||
283 | tcg_temp_free_i64(rd); | ||
284 | tcg_temp_free_i32(rm0); | ||
285 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a) | ||
286 | rm = tcg_temp_new_i64(); | ||
287 | rd = tcg_temp_new_i64(); | ||
288 | for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
289 | - neon_load_reg64(rm, a->vm + pass); | ||
290 | - neon_load_reg64(rd, a->vd + pass); | ||
291 | - neon_store_reg64(rm, a->vd + pass); | ||
292 | - neon_store_reg64(rd, a->vm + pass); | ||
293 | + read_neon_element64(rm, a->vm, pass, MO_64); | ||
294 | + read_neon_element64(rd, a->vd, pass, MO_64); | ||
295 | + write_neon_element64(rm, a->vd, pass, MO_64); | ||
296 | + write_neon_element64(rd, a->vm, pass, MO_64); | ||
297 | } | ||
298 | tcg_temp_free_i64(rm); | ||
299 | tcg_temp_free_i64(rd); | ||
300 | -- | ||
301 | 2.20.1 | ||
302 | |||
303 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | The only uses of this function are for loading VFP | ||
4 | double-precision values, and nothing to do with NEON. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201030022618.785675-10-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate.c | 8 ++-- | ||
12 | target/arm/translate-vfp.c.inc | 84 +++++++++++++++++----------------- | ||
13 | 2 files changed, 46 insertions(+), 46 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate.c | ||
18 | +++ b/target/arm/translate.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) | ||
20 | } | ||
21 | } | ||
22 | |||
23 | -static inline void neon_load_reg64(TCGv_i64 var, int reg) | ||
24 | +static inline void vfp_load_reg64(TCGv_i64 var, int reg) | ||
25 | { | ||
26 | - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | ||
27 | + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
28 | } | ||
29 | |||
30 | -static inline void neon_store_reg64(TCGv_i64 var, int reg) | ||
31 | +static inline void vfp_store_reg64(TCGv_i64 var, int reg) | ||
32 | { | ||
33 | - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); | ||
34 | + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); | ||
35 | } | ||
36 | |||
37 | static inline void vfp_load_reg32(TCGv_i32 var, int reg) | ||
38 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/translate-vfp.c.inc | ||
41 | +++ b/target/arm/translate-vfp.c.inc | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
43 | tcg_gen_ext_i32_i64(nf, cpu_NF); | ||
44 | tcg_gen_ext_i32_i64(vf, cpu_VF); | ||
45 | |||
46 | - neon_load_reg64(frn, rn); | ||
47 | - neon_load_reg64(frm, rm); | ||
48 | + vfp_load_reg64(frn, rn); | ||
49 | + vfp_load_reg64(frm, rm); | ||
50 | switch (a->cc) { | ||
51 | case 0: /* eq: Z */ | ||
52 | tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, | ||
53 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
54 | tcg_temp_free_i64(tmp); | ||
55 | break; | ||
56 | } | ||
57 | - neon_store_reg64(dest, rd); | ||
58 | + vfp_store_reg64(dest, rd); | ||
59 | tcg_temp_free_i64(frn); | ||
60 | tcg_temp_free_i64(frm); | ||
61 | tcg_temp_free_i64(dest); | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
63 | TCGv_i64 tcg_res; | ||
64 | tcg_op = tcg_temp_new_i64(); | ||
65 | tcg_res = tcg_temp_new_i64(); | ||
66 | - neon_load_reg64(tcg_op, rm); | ||
67 | + vfp_load_reg64(tcg_op, rm); | ||
68 | gen_helper_rintd(tcg_res, tcg_op, fpst); | ||
69 | - neon_store_reg64(tcg_res, rd); | ||
70 | + vfp_store_reg64(tcg_res, rd); | ||
71 | tcg_temp_free_i64(tcg_op); | ||
72 | tcg_temp_free_i64(tcg_res); | ||
73 | } else { | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
75 | tcg_double = tcg_temp_new_i64(); | ||
76 | tcg_res = tcg_temp_new_i64(); | ||
77 | tcg_tmp = tcg_temp_new_i32(); | ||
78 | - neon_load_reg64(tcg_double, rm); | ||
79 | + vfp_load_reg64(tcg_double, rm); | ||
80 | if (is_signed) { | ||
81 | gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); | ||
82 | } else { | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) | ||
84 | tmp = tcg_temp_new_i64(); | ||
85 | if (a->l) { | ||
86 | gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); | ||
87 | - neon_store_reg64(tmp, a->vd); | ||
88 | + vfp_store_reg64(tmp, a->vd); | ||
89 | } else { | ||
90 | - neon_load_reg64(tmp, a->vd); | ||
91 | + vfp_load_reg64(tmp, a->vd); | ||
92 | gen_aa32_st64(s, tmp, addr, get_mem_index(s)); | ||
93 | } | ||
94 | tcg_temp_free_i64(tmp); | ||
95 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) | ||
96 | if (a->l) { | ||
97 | /* load */ | ||
98 | gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); | ||
99 | - neon_store_reg64(tmp, a->vd + i); | ||
100 | + vfp_store_reg64(tmp, a->vd + i); | ||
101 | } else { | ||
102 | /* store */ | ||
103 | - neon_load_reg64(tmp, a->vd + i); | ||
104 | + vfp_load_reg64(tmp, a->vd + i); | ||
105 | gen_aa32_st64(s, tmp, addr, get_mem_index(s)); | ||
106 | } | ||
107 | tcg_gen_addi_i32(addr, addr, offset); | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
109 | fd = tcg_temp_new_i64(); | ||
110 | fpst = fpstatus_ptr(FPST_FPCR); | ||
111 | |||
112 | - neon_load_reg64(f0, vn); | ||
113 | - neon_load_reg64(f1, vm); | ||
114 | + vfp_load_reg64(f0, vn); | ||
115 | + vfp_load_reg64(f1, vm); | ||
116 | |||
117 | for (;;) { | ||
118 | if (reads_vd) { | ||
119 | - neon_load_reg64(fd, vd); | ||
120 | + vfp_load_reg64(fd, vd); | ||
121 | } | ||
122 | fn(fd, f0, f1, fpst); | ||
123 | - neon_store_reg64(fd, vd); | ||
124 | + vfp_store_reg64(fd, vd); | ||
125 | |||
126 | if (veclen == 0) { | ||
127 | break; | ||
128 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
129 | veclen--; | ||
130 | vd = vfp_advance_dreg(vd, delta_d); | ||
131 | vn = vfp_advance_dreg(vn, delta_d); | ||
132 | - neon_load_reg64(f0, vn); | ||
133 | + vfp_load_reg64(f0, vn); | ||
134 | if (delta_m) { | ||
135 | vm = vfp_advance_dreg(vm, delta_m); | ||
136 | - neon_load_reg64(f1, vm); | ||
137 | + vfp_load_reg64(f1, vm); | ||
138 | } | ||
139 | } | ||
140 | |||
141 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
142 | f0 = tcg_temp_new_i64(); | ||
143 | fd = tcg_temp_new_i64(); | ||
144 | |||
145 | - neon_load_reg64(f0, vm); | ||
146 | + vfp_load_reg64(f0, vm); | ||
147 | |||
148 | for (;;) { | ||
149 | fn(fd, f0); | ||
150 | - neon_store_reg64(fd, vd); | ||
151 | + vfp_store_reg64(fd, vd); | ||
152 | |||
153 | if (veclen == 0) { | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
156 | /* single source one-many */ | ||
157 | while (veclen--) { | ||
158 | vd = vfp_advance_dreg(vd, delta_d); | ||
159 | - neon_store_reg64(fd, vd); | ||
160 | + vfp_store_reg64(fd, vd); | ||
161 | } | ||
162 | break; | ||
163 | } | ||
164 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
165 | veclen--; | ||
166 | vd = vfp_advance_dreg(vd, delta_d); | ||
167 | vd = vfp_advance_dreg(vm, delta_m); | ||
168 | - neon_load_reg64(f0, vm); | ||
169 | + vfp_load_reg64(f0, vm); | ||
170 | } | ||
171 | |||
172 | tcg_temp_free_i64(f0); | ||
173 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) | ||
174 | vm = tcg_temp_new_i64(); | ||
175 | vd = tcg_temp_new_i64(); | ||
176 | |||
177 | - neon_load_reg64(vn, a->vn); | ||
178 | - neon_load_reg64(vm, a->vm); | ||
179 | + vfp_load_reg64(vn, a->vn); | ||
180 | + vfp_load_reg64(vm, a->vm); | ||
181 | if (neg_n) { | ||
182 | /* VFNMS, VFMS */ | ||
183 | gen_helper_vfp_negd(vn, vn); | ||
184 | } | ||
185 | - neon_load_reg64(vd, a->vd); | ||
186 | + vfp_load_reg64(vd, a->vd); | ||
187 | if (neg_d) { | ||
188 | /* VFNMA, VFNMS */ | ||
189 | gen_helper_vfp_negd(vd, vd); | ||
190 | } | ||
191 | fpst = fpstatus_ptr(FPST_FPCR); | ||
192 | gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); | ||
193 | - neon_store_reg64(vd, a->vd); | ||
194 | + vfp_store_reg64(vd, a->vd); | ||
195 | |||
196 | tcg_temp_free_ptr(fpst); | ||
197 | tcg_temp_free_i64(vn); | ||
198 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
199 | fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); | ||
200 | |||
201 | for (;;) { | ||
202 | - neon_store_reg64(fd, vd); | ||
203 | + vfp_store_reg64(fd, vd); | ||
204 | |||
205 | if (veclen == 0) { | ||
206 | break; | ||
207 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) | ||
208 | vd = tcg_temp_new_i64(); | ||
209 | vm = tcg_temp_new_i64(); | ||
210 | |||
211 | - neon_load_reg64(vd, a->vd); | ||
212 | + vfp_load_reg64(vd, a->vd); | ||
213 | if (a->z) { | ||
214 | tcg_gen_movi_i64(vm, 0); | ||
215 | } else { | ||
216 | - neon_load_reg64(vm, a->vm); | ||
217 | + vfp_load_reg64(vm, a->vm); | ||
218 | } | ||
219 | |||
220 | if (a->e) { | ||
221 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) | ||
222 | tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); | ||
223 | vd = tcg_temp_new_i64(); | ||
224 | gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); | ||
225 | - neon_store_reg64(vd, a->vd); | ||
226 | + vfp_store_reg64(vd, a->vd); | ||
227 | tcg_temp_free_i32(ahp_mode); | ||
228 | tcg_temp_free_ptr(fpst); | ||
229 | tcg_temp_free_i32(tmp); | ||
230 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) | ||
231 | tmp = tcg_temp_new_i32(); | ||
232 | vm = tcg_temp_new_i64(); | ||
233 | |||
234 | - neon_load_reg64(vm, a->vm); | ||
235 | + vfp_load_reg64(vm, a->vm); | ||
236 | gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); | ||
237 | tcg_temp_free_i64(vm); | ||
238 | tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); | ||
239 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) | ||
240 | } | ||
241 | |||
242 | tmp = tcg_temp_new_i64(); | ||
243 | - neon_load_reg64(tmp, a->vm); | ||
244 | + vfp_load_reg64(tmp, a->vm); | ||
245 | fpst = fpstatus_ptr(FPST_FPCR); | ||
246 | gen_helper_rintd(tmp, tmp, fpst); | ||
247 | - neon_store_reg64(tmp, a->vd); | ||
248 | + vfp_store_reg64(tmp, a->vd); | ||
249 | tcg_temp_free_ptr(fpst); | ||
250 | tcg_temp_free_i64(tmp); | ||
251 | return true; | ||
252 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) | ||
253 | } | ||
254 | |||
255 | tmp = tcg_temp_new_i64(); | ||
256 | - neon_load_reg64(tmp, a->vm); | ||
257 | + vfp_load_reg64(tmp, a->vm); | ||
258 | fpst = fpstatus_ptr(FPST_FPCR); | ||
259 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
260 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
261 | gen_helper_rintd(tmp, tmp, fpst); | ||
262 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
263 | - neon_store_reg64(tmp, a->vd); | ||
264 | + vfp_store_reg64(tmp, a->vd); | ||
265 | tcg_temp_free_ptr(fpst); | ||
266 | tcg_temp_free_i64(tmp); | ||
267 | tcg_temp_free_i32(tcg_rmode); | ||
268 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) | ||
269 | } | ||
270 | |||
271 | tmp = tcg_temp_new_i64(); | ||
272 | - neon_load_reg64(tmp, a->vm); | ||
273 | + vfp_load_reg64(tmp, a->vm); | ||
274 | fpst = fpstatus_ptr(FPST_FPCR); | ||
275 | gen_helper_rintd_exact(tmp, tmp, fpst); | ||
276 | - neon_store_reg64(tmp, a->vd); | ||
277 | + vfp_store_reg64(tmp, a->vd); | ||
278 | tcg_temp_free_ptr(fpst); | ||
279 | tcg_temp_free_i64(tmp); | ||
280 | return true; | ||
281 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
282 | vd = tcg_temp_new_i64(); | ||
283 | vfp_load_reg32(vm, a->vm); | ||
284 | gen_helper_vfp_fcvtds(vd, vm, cpu_env); | ||
285 | - neon_store_reg64(vd, a->vd); | ||
286 | + vfp_store_reg64(vd, a->vd); | ||
287 | tcg_temp_free_i32(vm); | ||
288 | tcg_temp_free_i64(vd); | ||
289 | return true; | ||
290 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
291 | |||
292 | vd = tcg_temp_new_i32(); | ||
293 | vm = tcg_temp_new_i64(); | ||
294 | - neon_load_reg64(vm, a->vm); | ||
295 | + vfp_load_reg64(vm, a->vm); | ||
296 | gen_helper_vfp_fcvtsd(vd, vm, cpu_env); | ||
297 | vfp_store_reg32(vd, a->vd); | ||
298 | tcg_temp_free_i32(vd); | ||
299 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
300 | /* u32 -> f64 */ | ||
301 | gen_helper_vfp_uitod(vd, vm, fpst); | ||
302 | } | ||
303 | - neon_store_reg64(vd, a->vd); | ||
304 | + vfp_store_reg64(vd, a->vd); | ||
305 | tcg_temp_free_i32(vm); | ||
306 | tcg_temp_free_i64(vd); | ||
307 | tcg_temp_free_ptr(fpst); | ||
308 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
309 | |||
310 | vm = tcg_temp_new_i64(); | ||
311 | vd = tcg_temp_new_i32(); | ||
312 | - neon_load_reg64(vm, a->vm); | ||
313 | + vfp_load_reg64(vm, a->vm); | ||
314 | gen_helper_vjcvt(vd, vm, cpu_env); | ||
315 | vfp_store_reg32(vd, a->vd); | ||
316 | tcg_temp_free_i64(vm); | ||
317 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
318 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
319 | |||
320 | vd = tcg_temp_new_i64(); | ||
321 | - neon_load_reg64(vd, a->vd); | ||
322 | + vfp_load_reg64(vd, a->vd); | ||
323 | |||
324 | fpst = fpstatus_ptr(FPST_FPCR); | ||
325 | shift = tcg_const_i32(frac_bits); | ||
326 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
327 | g_assert_not_reached(); | ||
328 | } | ||
329 | |||
330 | - neon_store_reg64(vd, a->vd); | ||
331 | + vfp_store_reg64(vd, a->vd); | ||
332 | tcg_temp_free_i64(vd); | ||
333 | tcg_temp_free_i32(shift); | ||
334 | tcg_temp_free_ptr(fpst); | ||
335 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
336 | fpst = fpstatus_ptr(FPST_FPCR); | ||
337 | vm = tcg_temp_new_i64(); | ||
338 | vd = tcg_temp_new_i32(); | ||
339 | - neon_load_reg64(vm, a->vm); | ||
340 | + vfp_load_reg64(vm, a->vm); | ||
341 | |||
342 | if (a->s) { | ||
343 | if (a->rz) { | ||
344 | -- | ||
345 | 2.20.1 | ||
346 | |||
347 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | In both cases, we can sink the write-back and perform | ||
4 | the accumulate into the normal destination temps. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201030022618.785675-11-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate-neon.c.inc | 23 +++++++++-------------- | ||
12 | 1 file changed, 9 insertions(+), 14 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate-neon.c.inc | ||
17 | +++ b/target/arm/translate-neon.c.inc | ||
18 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
19 | if (accfn) { | ||
20 | tmp = tcg_temp_new_i64(); | ||
21 | read_neon_element64(tmp, a->vd, 0, MO_64); | ||
22 | - accfn(tmp, tmp, rd0); | ||
23 | - write_neon_element64(tmp, a->vd, 0, MO_64); | ||
24 | + accfn(rd0, tmp, rd0); | ||
25 | read_neon_element64(tmp, a->vd, 1, MO_64); | ||
26 | - accfn(tmp, tmp, rd1); | ||
27 | - write_neon_element64(tmp, a->vd, 1, MO_64); | ||
28 | + accfn(rd1, tmp, rd1); | ||
29 | tcg_temp_free_i64(tmp); | ||
30 | - } else { | ||
31 | - write_neon_element64(rd0, a->vd, 0, MO_64); | ||
32 | - write_neon_element64(rd1, a->vd, 1, MO_64); | ||
33 | } | ||
34 | |||
35 | + write_neon_element64(rd0, a->vd, 0, MO_64); | ||
36 | + write_neon_element64(rd1, a->vd, 1, MO_64); | ||
37 | tcg_temp_free_i64(rd0); | ||
38 | tcg_temp_free_i64(rd1); | ||
39 | |||
40 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
41 | if (accfn) { | ||
42 | TCGv_i64 t64 = tcg_temp_new_i64(); | ||
43 | read_neon_element64(t64, a->vd, 0, MO_64); | ||
44 | - accfn(t64, t64, rn0_64); | ||
45 | - write_neon_element64(t64, a->vd, 0, MO_64); | ||
46 | + accfn(rn0_64, t64, rn0_64); | ||
47 | read_neon_element64(t64, a->vd, 1, MO_64); | ||
48 | - accfn(t64, t64, rn1_64); | ||
49 | - write_neon_element64(t64, a->vd, 1, MO_64); | ||
50 | + accfn(rn1_64, t64, rn1_64); | ||
51 | tcg_temp_free_i64(t64); | ||
52 | - } else { | ||
53 | - write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
54 | - write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
55 | } | ||
56 | + | ||
57 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
58 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
59 | tcg_temp_free_i64(rn0_64); | ||
60 | tcg_temp_free_i64(rn1_64); | ||
61 | return true; | ||
62 | -- | ||
63 | 2.20.1 | ||
64 | |||
65 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | We can use proper widening loads to extend 32-bit inputs, | ||
4 | and skip the "widenfn" step. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201030022618.785675-12-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate.c | 6 +++ | ||
12 | target/arm/translate-neon.c.inc | 66 ++++++++++++++++++--------------- | ||
13 | 2 files changed, 43 insertions(+), 29 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate.c | ||
18 | +++ b/target/arm/translate.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | ||
20 | long off = neon_element_offset(reg, ele, memop); | ||
21 | |||
22 | switch (memop) { | ||
23 | + case MO_SL: | ||
24 | + tcg_gen_ld32s_i64(dest, cpu_env, off); | ||
25 | + break; | ||
26 | + case MO_UL: | ||
27 | + tcg_gen_ld32u_i64(dest, cpu_env, off); | ||
28 | + break; | ||
29 | case MO_Q: | ||
30 | tcg_gen_ld_i64(dest, cpu_env, off); | ||
31 | break; | ||
32 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/translate-neon.c.inc | ||
35 | +++ b/target/arm/translate-neon.c.inc | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) | ||
37 | static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
38 | NeonGenWidenFn *widenfn, | ||
39 | NeonGenTwo64OpFn *opfn, | ||
40 | - bool src1_wide) | ||
41 | + int src1_mop, int src2_mop) | ||
42 | { | ||
43 | /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */ | ||
44 | TCGv_i64 rn0_64, rn1_64, rm_64; | ||
45 | - TCGv_i32 rm; | ||
46 | |||
47 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
48 | return false; | ||
49 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
50 | return false; | ||
51 | } | ||
52 | |||
53 | - if (!widenfn || !opfn) { | ||
54 | + if (!opfn) { | ||
55 | /* size == 3 case, which is an entirely different insn group */ | ||
56 | return false; | ||
57 | } | ||
58 | |||
59 | - if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { | ||
60 | + if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) { | ||
61 | return false; | ||
62 | } | ||
63 | |||
64 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
65 | rn1_64 = tcg_temp_new_i64(); | ||
66 | rm_64 = tcg_temp_new_i64(); | ||
67 | |||
68 | - if (src1_wide) { | ||
69 | - read_neon_element64(rn0_64, a->vn, 0, MO_64); | ||
70 | + if (src1_mop >= 0) { | ||
71 | + read_neon_element64(rn0_64, a->vn, 0, src1_mop); | ||
72 | } else { | ||
73 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
74 | read_neon_element32(tmp, a->vn, 0, MO_32); | ||
75 | widenfn(rn0_64, tmp); | ||
76 | tcg_temp_free_i32(tmp); | ||
77 | } | ||
78 | - rm = tcg_temp_new_i32(); | ||
79 | - read_neon_element32(rm, a->vm, 0, MO_32); | ||
80 | + if (src2_mop >= 0) { | ||
81 | + read_neon_element64(rm_64, a->vm, 0, src2_mop); | ||
82 | + } else { | ||
83 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
84 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
85 | + widenfn(rm_64, tmp); | ||
86 | + tcg_temp_free_i32(tmp); | ||
87 | + } | ||
88 | |||
89 | - widenfn(rm_64, rm); | ||
90 | - tcg_temp_free_i32(rm); | ||
91 | opfn(rn0_64, rn0_64, rm_64); | ||
92 | |||
93 | /* | ||
94 | * Load second pass inputs before storing the first pass result, to | ||
95 | * avoid incorrect results if a narrow input overlaps with the result. | ||
96 | */ | ||
97 | - if (src1_wide) { | ||
98 | - read_neon_element64(rn1_64, a->vn, 1, MO_64); | ||
99 | + if (src1_mop >= 0) { | ||
100 | + read_neon_element64(rn1_64, a->vn, 1, src1_mop); | ||
101 | } else { | ||
102 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
103 | read_neon_element32(tmp, a->vn, 1, MO_32); | ||
104 | widenfn(rn1_64, tmp); | ||
105 | tcg_temp_free_i32(tmp); | ||
106 | } | ||
107 | - rm = tcg_temp_new_i32(); | ||
108 | - read_neon_element32(rm, a->vm, 1, MO_32); | ||
109 | + if (src2_mop >= 0) { | ||
110 | + read_neon_element64(rm_64, a->vm, 1, src2_mop); | ||
111 | + } else { | ||
112 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
113 | + read_neon_element32(tmp, a->vm, 1, MO_32); | ||
114 | + widenfn(rm_64, tmp); | ||
115 | + tcg_temp_free_i32(tmp); | ||
116 | + } | ||
117 | |||
118 | write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
119 | |||
120 | - widenfn(rm_64, rm); | ||
121 | - tcg_temp_free_i32(rm); | ||
122 | opfn(rn1_64, rn1_64, rm_64); | ||
123 | write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
124 | |||
125 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
126 | return true; | ||
127 | } | ||
128 | |||
129 | -#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ | ||
130 | +#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \ | ||
131 | static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ | ||
132 | { \ | ||
133 | static NeonGenWidenFn * const widenfn[] = { \ | ||
134 | gen_helper_neon_widen_##S##8, \ | ||
135 | gen_helper_neon_widen_##S##16, \ | ||
136 | - tcg_gen_##EXT##_i32_i64, \ | ||
137 | - NULL, \ | ||
138 | + NULL, NULL, \ | ||
139 | }; \ | ||
140 | static NeonGenTwo64OpFn * const addfn[] = { \ | ||
141 | gen_helper_neon_##OP##l_u16, \ | ||
142 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
143 | tcg_gen_##OP##_i64, \ | ||
144 | NULL, \ | ||
145 | }; \ | ||
146 | - return do_prewiden_3d(s, a, widenfn[a->size], \ | ||
147 | - addfn[a->size], SRC1WIDE); \ | ||
148 | + int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1; \ | ||
149 | + return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \ | ||
150 | + SRC1WIDE ? MO_Q : narrow_mop, \ | ||
151 | + narrow_mop); \ | ||
152 | } | ||
153 | |||
154 | -DO_PREWIDEN(VADDL_S, s, ext, add, false) | ||
155 | -DO_PREWIDEN(VADDL_U, u, extu, add, false) | ||
156 | -DO_PREWIDEN(VSUBL_S, s, ext, sub, false) | ||
157 | -DO_PREWIDEN(VSUBL_U, u, extu, sub, false) | ||
158 | -DO_PREWIDEN(VADDW_S, s, ext, add, true) | ||
159 | -DO_PREWIDEN(VADDW_U, u, extu, add, true) | ||
160 | -DO_PREWIDEN(VSUBW_S, s, ext, sub, true) | ||
161 | -DO_PREWIDEN(VSUBW_U, u, extu, sub, true) | ||
162 | +DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN) | ||
163 | +DO_PREWIDEN(VADDL_U, u, add, false, 0) | ||
164 | +DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN) | ||
165 | +DO_PREWIDEN(VSUBL_U, u, sub, false, 0) | ||
166 | +DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN) | ||
167 | +DO_PREWIDEN(VADDW_U, u, add, true, 0) | ||
168 | +DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN) | ||
169 | +DO_PREWIDEN(VSUBW_U, u, sub, true, 0) | ||
170 | |||
171 | static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | ||
172 | NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) | ||
173 | -- | ||
174 | 2.20.1 | ||
175 | |||
176 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error | ||
2 | meant we were using the H4() address swizzler macro rather than the | ||
3 | H2() which is required for 2-byte data. This had no effect on | ||
4 | little-endian hosts but meant we put the result data into the | ||
5 | destination Dreg in the wrong order on big-endian hosts. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 20201028191712.4910-2-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/vec_helper.c | 8 ++++---- | ||
13 | 1 file changed, 4 insertions(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/vec_helper.c | ||
18 | +++ b/target/arm/vec_helper.c | ||
19 | @@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t) | ||
20 | r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \ | ||
21 | r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \ | ||
22 | \ | ||
23 | - d[H4(0)] = r0; \ | ||
24 | - d[H4(1)] = r1; \ | ||
25 | - d[H4(2)] = r2; \ | ||
26 | - d[H4(3)] = r3; \ | ||
27 | + d[H2(0)] = r0; \ | ||
28 | + d[H2(1)] = r1; \ | ||
29 | + d[H2(2)] = r2; \ | ||
30 | + d[H2(3)] = r3; \ | ||
31 | } | ||
32 | |||
33 | DO_NEON_PAIRWISE(neon_padd, add) | ||
34 | -- | ||
35 | 2.20.1 | ||
36 | |||
37 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The helper functions for performing the udot/sdot operations against | ||
2 | a scalar were not using an address-swizzling macro when converting | ||
3 | the index of the scalar element into a pointer into the vm array. | ||
4 | This had no effect on little-endian hosts but meant we generated | ||
5 | incorrect results on big-endian hosts. | ||
6 | 1 | ||
7 | For these insns, the index is indexing over group of 4 8-bit values, | ||
8 | so 32 bits per indexed entity, and H4() is therefore what we want. | ||
9 | (For Neon the only possible input indexes are 0 and 1.) | ||
10 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 20201028191712.4910-3-peter.maydell@linaro.org | ||
15 | --- | ||
16 | target/arm/vec_helper.c | 4 ++-- | ||
17 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/vec_helper.c | ||
22 | +++ b/target/arm/vec_helper.c | ||
23 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) | ||
24 | intptr_t index = simd_data(desc); | ||
25 | uint32_t *d = vd; | ||
26 | int8_t *n = vn; | ||
27 | - int8_t *m_indexed = (int8_t *)vm + index * 4; | ||
28 | + int8_t *m_indexed = (int8_t *)vm + H4(index) * 4; | ||
29 | |||
30 | /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. | ||
31 | * Otherwise opr_sz is a multiple of 16. | ||
32 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) | ||
33 | intptr_t index = simd_data(desc); | ||
34 | uint32_t *d = vd; | ||
35 | uint8_t *n = vn; | ||
36 | - uint8_t *m_indexed = (uint8_t *)vm + index * 4; | ||
37 | + uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4; | ||
38 | |||
39 | /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. | ||
40 | * Otherwise opr_sz is a multiple of 16. | ||
41 | -- | ||
42 | 2.20.1 | ||
43 | |||
44 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
2 | 1 | ||
3 | HCR should be applied when NS is set, not when it is cleared. | ||
4 | |||
5 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | target/arm/helper.c | 5 ++--- | ||
10 | 1 file changed, 2 insertions(+), 3 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/helper.c | ||
15 | +++ b/target/arm/helper.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
17 | |||
18 | /* | ||
19 | * Non-IS variants of TLB operations are upgraded to | ||
20 | - * IS versions if we are at NS EL1 and HCR_EL2.FB is set to | ||
21 | + * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to | ||
22 | * force broadcast of these operations. | ||
23 | */ | ||
24 | static bool tlb_force_broadcast(CPUARMState *env) | ||
25 | { | ||
26 | - return (env->cp15.hcr_el2 & HCR_FB) && | ||
27 | - arm_current_el(env) == 1 && arm_is_secure_below_el3(env); | ||
28 | + return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); | ||
29 | } | ||
30 | |||
31 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
32 | -- | ||
33 | 2.20.1 | ||
34 | |||
35 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
2 | 1 | ||
3 | Secure mode is not exempted from checking SCR_EL3.TLOR, and in the | ||
4 | future HCR_EL2.TLOR when S-EL2 is enabled. | ||
5 | |||
6 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | target/arm/helper.c | 19 +++++-------------- | ||
11 | 1 file changed, 5 insertions(+), 14 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/helper.c | ||
16 | +++ b/target/arm/helper.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
18 | #endif | ||
19 | |||
20 | /* Shared logic between LORID and the rest of the LOR* registers. | ||
21 | - * Secure state has already been delt with. | ||
22 | + * Secure state exclusion has already been dealt with. | ||
23 | */ | ||
24 | -static CPAccessResult access_lor_ns(CPUARMState *env) | ||
25 | +static CPAccessResult access_lor_ns(CPUARMState *env, | ||
26 | + const ARMCPRegInfo *ri, bool isread) | ||
27 | { | ||
28 | int el = arm_current_el(env); | ||
29 | |||
30 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env) | ||
31 | return CP_ACCESS_OK; | ||
32 | } | ||
33 | |||
34 | -static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, | ||
35 | - bool isread) | ||
36 | -{ | ||
37 | - if (arm_is_secure_below_el3(env)) { | ||
38 | - /* Access ok in secure mode. */ | ||
39 | - return CP_ACCESS_OK; | ||
40 | - } | ||
41 | - return access_lor_ns(env); | ||
42 | -} | ||
43 | - | ||
44 | static CPAccessResult access_lor_other(CPUARMState *env, | ||
45 | const ARMCPRegInfo *ri, bool isread) | ||
46 | { | ||
47 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env, | ||
48 | /* Access denied in secure mode. */ | ||
49 | return CP_ACCESS_TRAP; | ||
50 | } | ||
51 | - return access_lor_ns(env); | ||
52 | + return access_lor_ns(env, ri, isread); | ||
53 | } | ||
54 | |||
55 | /* | ||
56 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = { | ||
57 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
58 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | ||
59 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | ||
60 | - .access = PL1_R, .accessfn = access_lorid, | ||
61 | + .access = PL1_R, .accessfn = access_lor_ns, | ||
62 | .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
63 | REGINFO_SENTINEL | ||
64 | }; | ||
65 | -- | ||
66 | 2.20.1 | ||
67 | |||
68 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | On some hosts (eg Ubuntu Bionic) pkg-config returns a set of | ||
2 | libraries for gio-2.0 which don't actually work when compiling | ||
3 | statically. (Specifically, the returned library string includes | ||
4 | -lmount, but not -lblkid which -lmount depends upon, so linking | ||
5 | fails due to missing symbols.) | ||
6 | 1 | ||
7 | Check that the libraries work, and don't enable gio if they don't, | ||
8 | in the same way we do for gnutls. | ||
9 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
13 | Message-id: 20200928160402.7961-1-peter.maydell@linaro.org | ||
14 | --- | ||
15 | configure | 10 +++++++++- | ||
16 | 1 file changed, 9 insertions(+), 1 deletion(-) | ||
17 | |||
18 | diff --git a/configure b/configure | ||
19 | index XXXXXXX..XXXXXXX 100755 | ||
20 | --- a/configure | ||
21 | +++ b/configure | ||
22 | @@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then | ||
23 | fi | ||
24 | |||
25 | if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then | ||
26 | - gio=yes | ||
27 | gio_cflags=$($pkg_config --cflags gio-2.0) | ||
28 | gio_libs=$($pkg_config --libs gio-2.0) | ||
29 | gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0) | ||
30 | if [ ! -x "$gdbus_codegen" ]; then | ||
31 | gdbus_codegen= | ||
32 | fi | ||
33 | + # Check that the libraries actually work -- Ubuntu 18.04 ships | ||
34 | + # with pkg-config --static --libs data for gio-2.0 that is missing | ||
35 | + # -lblkid and will give a link error. | ||
36 | + write_c_skeleton | ||
37 | + if compile_prog "" "gio_libs" ; then | ||
38 | + gio=yes | ||
39 | + else | ||
40 | + gio=no | ||
41 | + fi | ||
42 | else | ||
43 | gio=no | ||
44 | fi | ||
45 | -- | ||
46 | 2.20.1 | ||
47 | |||
48 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt | ||
2 | into the GICv3CPUState struct's maintenance_irq field. This will | ||
3 | only work if the board happens to have already wired up the CPU | ||
4 | maintenance IRQ before the GIC was realized. Unfortunately this is | ||
5 | not the case for the 'virt' board, and so the value that gets copied | ||
6 | is NULL (since a qemu_irq is really a pointer to an IRQState struct | ||
7 | under the hood). The effect is that the CPU interface code never | ||
8 | actually raises the maintenance interrupt line. | ||
9 | 1 | ||
10 | Instead, since the GICv3CPUState has a pointer to the CPUState, make | ||
11 | the dereference at the point where we want to raise the interrupt, to | ||
12 | avoid an implicit requirement on board code to wire things up in a | ||
13 | particular order. | ||
14 | |||
15 | Reported-by: Jose Martins <josemartins90@gmail.com> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Message-id: 20201009153904.28529-1-peter.maydell@linaro.org | ||
18 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
19 | --- | ||
20 | include/hw/intc/arm_gicv3_common.h | 1 - | ||
21 | hw/intc/arm_gicv3_cpuif.c | 5 ++--- | ||
22 | 2 files changed, 2 insertions(+), 4 deletions(-) | ||
23 | |||
24 | diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/include/hw/intc/arm_gicv3_common.h | ||
27 | +++ b/include/hw/intc/arm_gicv3_common.h | ||
28 | @@ -XXX,XX +XXX,XX @@ struct GICv3CPUState { | ||
29 | qemu_irq parent_fiq; | ||
30 | qemu_irq parent_virq; | ||
31 | qemu_irq parent_vfiq; | ||
32 | - qemu_irq maintenance_irq; | ||
33 | |||
34 | /* Redistributor */ | ||
35 | uint32_t level; /* Current IRQ level */ | ||
36 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
39 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
40 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) | ||
41 | int irqlevel = 0; | ||
42 | int fiqlevel = 0; | ||
43 | int maintlevel = 0; | ||
44 | + ARMCPU *cpu = ARM_CPU(cs->cpu); | ||
45 | |||
46 | idx = hppvi_index(cs); | ||
47 | trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); | ||
48 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) | ||
49 | |||
50 | qemu_set_irq(cs->parent_vfiq, fiqlevel); | ||
51 | qemu_set_irq(cs->parent_virq, irqlevel); | ||
52 | - qemu_set_irq(cs->maintenance_irq, maintlevel); | ||
53 | + qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); | ||
54 | } | ||
55 | |||
56 | static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
57 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) | ||
58 | && cpu->gic_num_lrs) { | ||
59 | int j; | ||
60 | |||
61 | - cs->maintenance_irq = cpu->gicv3_maintenance_interrupt; | ||
62 | - | ||
63 | cs->num_list_regs = cpu->gic_num_lrs; | ||
64 | cs->vpribits = cpu->gic_vpribits; | ||
65 | cs->vprebits = cpu->gic_vprebits; | ||
66 | -- | ||
67 | 2.20.1 | ||
68 | |||
69 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The kerneldoc script currently emits Sphinx markup for a macro with | ||
2 | arguments that uses the c:function directive. This is correct for | ||
3 | Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow | ||
4 | documentation of macros with arguments and c:function is not picky | ||
5 | about the syntax of what it is passed. However, in Sphinx 3 the | ||
6 | c:macro directive was enhanced to support macros with arguments, | ||
7 | and c:function was made more picky about what syntax it accepted. | ||
8 | 1 | ||
9 | When kerneldoc is told that it needs to produce output for Sphinx | ||
10 | 3 or later, make it emit c:function only for functions and c:macro | ||
11 | for macros with arguments. We assume that anything with a return | ||
12 | type is a function and anything without is a macro. | ||
13 | |||
14 | This fixes the Sphinx error: | ||
15 | |||
16 | /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator | ||
17 | If declarator-id with parameters (e.g., 'void f(int arg)'): | ||
18 | Invalid C declaration: Expected identifier in nested name. [error at 25] | ||
19 | DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) | ||
20 | -------------------------^ | ||
21 | If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'): | ||
22 | Error in declarator or parameters | ||
23 | Invalid C declaration: Expecting "(" in parameters. [error at 39] | ||
24 | DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) | ||
25 | ---------------------------------------^ | ||
26 | |||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | ||
29 | Tested-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
30 | Message-id: 20201030174700.7204-2-peter.maydell@linaro.org | ||
31 | --- | ||
32 | scripts/kernel-doc | 18 +++++++++++++++++- | ||
33 | 1 file changed, 17 insertions(+), 1 deletion(-) | ||
34 | |||
35 | diff --git a/scripts/kernel-doc b/scripts/kernel-doc | ||
36 | index XXXXXXX..XXXXXXX 100755 | ||
37 | --- a/scripts/kernel-doc | ||
38 | +++ b/scripts/kernel-doc | ||
39 | @@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) { | ||
40 | output_highlight_rst($args{'purpose'}); | ||
41 | $start = "\n\n**Syntax**\n\n ``"; | ||
42 | } else { | ||
43 | - print ".. c:function:: "; | ||
44 | + if ((split(/\./, $sphinx_version))[0] >= 3) { | ||
45 | + # Sphinx 3 and later distinguish macros and functions and | ||
46 | + # complain if you use c:function with something that's not | ||
47 | + # syntactically valid as a function declaration. | ||
48 | + # We assume that anything with a return type is a function | ||
49 | + # and anything without is a macro. | ||
50 | + if ($args{'functiontype'} ne "") { | ||
51 | + print ".. c:function:: "; | ||
52 | + } else { | ||
53 | + print ".. c:macro:: "; | ||
54 | + } | ||
55 | + } else { | ||
56 | + # Older Sphinx don't support documenting macros that take | ||
57 | + # arguments with c:macro, and don't complain about the use | ||
58 | + # of c:function for this. | ||
59 | + print ".. c:function:: "; | ||
60 | + } | ||
61 | } | ||
62 | if ($args{'functiontype'} ne "") { | ||
63 | $start .= $args{'functiontype'} . " " . $args{'function'} . " ("; | ||
64 | -- | ||
65 | 2.20.1 | ||
66 | |||
67 | diff view generated by jsdifflib |