Series comparison

-[PULL 00/26] target-arm queue
+[PULL 0/7] target-arm queue
-Small pile of bug fixes for rc1. I've included my patches to get
+Hi; this pull request has a collection of bug fixes for rc0.
-our docs building with Sphinx 3, just for convenience...
+The big one is the trusted firmware boot regression fix.
+thanks
 -- PMM
-The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96:
+The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:
-  Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000)
+  Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221104
-for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a:
+for you to fetch changes up to cead7fa4c06087c86c67c5ce815cc1ff0bfeac3a:
-  tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000)
+  target/arm: Two fixes for secure ptw (2022-11-04 10:58:58 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * target/arm: Fix Neon emulation bugs on big-endian hosts
+ * Fix regression booting Trusted Firmware
- * target/arm: fix handling of HCR.FB
+ * Honor HCR_E2H and HCR_TGE in ats_write64()
- * target/arm: fix LORID_EL1 access check
+ * Copy the entire vector in DO_ZIP
- * disas/capstone: Fix monitor disassembly of >32 bytes
+ * Fix Privileged Access Never (PAN) for aarch32
- * hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
+ * Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
- * hw/arm/boot: fix SVE for EL3 direct kernel boot
+ * Set SCR_EL3.HXEn when direct booting kernel
- * hw/display/omap_lcdc: Fix potential NULL pointer dereference
+ * Set SME and SVE EL3 vector lengths when direct booting kernel
  * hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
  * target/arm: Get correct MMU index for other-security-state
  * configure: Test that gio libs from pkg-config work
  * hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
  * docs: Fix building with Sphinx 3
  * tests/qtest/npcm7xx_rng-test: Disable randomness tests
 ----------------------------------------------------------------
-AlexChen (2):
+Ake Koomsin (1):
-      hw/display/omap_lcdc: Fix potential NULL pointer dereference
+      target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()
       hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
-Peter Maydell (9):
+Peter Maydell (3):
-      target/arm: Fix float16 pairwise Neon ops on big-endian hosts
+      hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel
-      target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
+      hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
-      disas/capstone: Fix monitor disassembly of >32 bytes
+      target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
       target/arm: Get correct MMU index for other-security-state
       configure: Test that gio libs from pkg-config work
       hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
       scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
       qemu-option-trace.rst.inc: Don't use option:: markup
       tests/qtest/npcm7xx_rng-test: Disable randomness tests
-Philippe Mathieu-Daudé (1):
+Richard Henderson (2):
-      hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
+      target/arm: Copy the entire vector in DO_ZIP
       target/arm: Two fixes for secure ptw
-Richard Henderson (11):
+Timofey Kutergin (1):
-      target/arm: Introduce neon_full_reg_offset
+      target/arm: Fix Privileged Access Never (PAN) for aarch32
       target/arm: Move neon_element_offset to translate.c
       target/arm: Use neon_element_offset in neon_load/store_reg
       target/arm: Use neon_element_offset in vfp_reg_offset
       target/arm: Add read/write_neon_element32
       target/arm: Expand read/write_neon_element32 to all MemOp
       target/arm: Rename neon_load_reg32 to vfp_load_reg32
       target/arm: Add read/write_neon_element64
       target/arm: Rename neon_load_reg64 to vfp_load_reg64
       target/arm: Simplify do_long_3d and do_2scalar_long
       target/arm: Improve do_prewiden_3d
-Rémi Denis-Courmont (3):
+ hw/arm/boot.c           |  5 ++++
-      target/arm: fix handling of HCR.FB
+ target/arm/helper.c     | 64 +++++++++++++++++++++++++++++--------------------
-      target/arm: fix LORID_EL1 access check
+ target/arm/ptw.c        | 50 ++++++++++++++++++++++++++++----------
-      hw/arm/boot: fix SVE for EL3 direct kernel boot
+ target/arm/sve_helper.c |  4 ++--
+files changed, 83 insertions(+), 40 deletions(-)
  docs/qemu-option-trace.rst.inc     |   6 +-
  configure                          |  10 +-
  include/hw/intc/arm_gicv3_common.h |   1 -
  disas/capstone.c                   |   2 +-
  hw/arm/boot.c                      |   3 +
  hw/arm/smmuv3.c                    |   3 +-
  hw/display/exynos4210_fimd.c       |   4 +-
  hw/display/omap_lcdc.c             |  10 +-
  hw/intc/arm_gicv3_cpuif.c          |   5 +-
  target/arm/helper.c                |  24 +-
  target/arm/m_helper.c              |   3 +-
  target/arm/translate.c             | 153 +++++++++---
  target/arm/vec_helper.c            |  12 +-
  tests/qtest/npcm7xx_rng-test.c     |  14 +-
  scripts/kernel-doc                 |  18 +-
  target/arm/translate-neon.c.inc    | 472 ++++++++++++++++++++-----------------
  target/arm/translate-vfp.c.inc     | 341 +++++++++++----------------
 files changed, 588 insertions(+), 493 deletions(-)

-[PULL 01/26] target/arm: Introduce neon_full_reg_offset
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This function makes it clear that we're talking about the whole
-register, and not the 32-bit piece at index 0.  This fixes a bug
-when running on a big-endian host.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-2-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate.c          |  8 ++++++
- target/arm/translate-neon.c.inc | 44 ++++++++++++++++-----------------
- target/arm/translate-vfp.c.inc  |  2 +-
-files changed, 31 insertions(+), 23 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
-     unallocated_encoding(s);
- }
-+/*
-+ * Return the offset of a "full" NEON Dreg.
-+ */
-+static long neon_full_reg_offset(unsigned reg)
-+{
-+    return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
-+}
-+
- static inline long vfp_reg_offset(bool dp, unsigned reg)
- {
-     if (dp) {
-diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c.inc
-+++ b/target/arm/translate-neon.c.inc
-@@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size)
-         ofs ^= 8 - element_size;
-     }
- #endif
--    return neon_reg_offset(reg, 0) + ofs;
-+    return neon_full_reg_offset(reg) + ofs;
- }
- static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
-              * We cannot write 16 bytes at once because the
-              * destination is unaligned.
-              */
--            tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
-+            tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
-, 8, tmp);
--            tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
--                             neon_reg_offset(vd, 0), 8, 8);
-+            tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1),
-+                             neon_full_reg_offset(vd), 8, 8);
-         } else {
--            tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
-+            tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
-                                  vec_size, vec_size, tmp);
-         }
-         tcg_gen_addi_i32(addr, addr, 1 << size);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
- static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
- {
-     int vec_size = a->q ? 16 : 8;
--    int rd_ofs = neon_reg_offset(a->vd, 0);
--    int rn_ofs = neon_reg_offset(a->vn, 0);
--    int rm_ofs = neon_reg_offset(a->vm, 0);
-+    int rd_ofs = neon_full_reg_offset(a->vd);
-+    int rn_ofs = neon_full_reg_offset(a->vn);
-+    int rm_ofs = neon_full_reg_offset(a->vm);
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-         return false;
-@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
- {
-     /* Handle a 2-reg-shift insn which can be vectorized. */
-     int vec_size = a->q ? 16 : 8;
--    int rd_ofs = neon_reg_offset(a->vd, 0);
--    int rm_ofs = neon_reg_offset(a->vm, 0);
-+    int rd_ofs = neon_full_reg_offset(a->vd);
-+    int rm_ofs = neon_full_reg_offset(a->vm);
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-         return false;
-@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
- {
-     /* FP operations in 2-reg-and-shift group */
-     int vec_size = a->q ? 16 : 8;
--    int rd_ofs = neon_reg_offset(a->vd, 0);
--    int rm_ofs = neon_reg_offset(a->vm, 0);
-+    int rd_ofs = neon_full_reg_offset(a->vd);
-+    int rm_ofs = neon_full_reg_offset(a->vm);
-     TCGv_ptr fpst;
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-@@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
-         return true;
-     }
--    reg_ofs = neon_reg_offset(a->vd, 0);
-+    reg_ofs = neon_full_reg_offset(a->vd);
-     vec_size = a->q ? 16 : 8;
-     imm = asimd_imm_const(a->imm, a->cmode, a->op);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
-         return true;
-     }
--    tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0),
--                       neon_reg_offset(a->vn, 0),
--                       neon_reg_offset(a->vm, 0),
-+    tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd),
-+                       neon_full_reg_offset(a->vn),
-+                       neon_full_reg_offset(a->vm),
-, 16, 0, fn_gvec);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
- {
-     /* Two registers and a scalar, using gvec */
-     int vec_size = a->q ? 16 : 8;
--    int rd_ofs = neon_reg_offset(a->vd, 0);
--    int rn_ofs = neon_reg_offset(a->vn, 0);
-+    int rd_ofs = neon_full_reg_offset(a->vd);
-+    int rn_ofs = neon_full_reg_offset(a->vn);
-     int rm_ofs;
-     int idx;
-     TCGv_ptr fpstatus;
-@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
-     /* a->vm is M:Vm, which encodes both register and index */
-     idx = extract32(a->vm, a->size + 2, 2);
-     a->vm = extract32(a->vm, 0, a->size + 2);
--    rm_ofs = neon_reg_offset(a->vm, 0);
-+    rm_ofs = neon_full_reg_offset(a->vm);
-     fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD);
-     tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus,
-@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
-         return true;
-     }
--    tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0),
-+    tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd),
-                          neon_element_offset(a->vm, a->index, a->size),
-                          a->q ? 16 : 8, a->q ? 16 : 8);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
- static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
- {
-     int vec_size = a->q ? 16 : 8;
--    int rd_ofs = neon_reg_offset(a->vd, 0);
--    int rm_ofs = neon_reg_offset(a->vm, 0);
-+    int rd_ofs = neon_full_reg_offset(a->vd);
-+    int rm_ofs = neon_full_reg_offset(a->vm);
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-         return false;
-diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-vfp.c.inc
-+++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
-     }
-     tmp = load_reg(s, a->rt);
--    tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
-+    tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn),
-                          vec_size, vec_size, tmp);
-     tcg_temp_free_i32(tmp);
---
-.20.1

-[PULL 02/26] target/arm: Move neon_element_offset to translate.c
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This will shortly have users outside of translate-neon.c.inc.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-3-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate.c          | 20 ++++++++++++++++++++
- target/arm/translate-neon.c.inc | 19 -------------------
-files changed, 20 insertions(+), 19 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
-     return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
- }
-+/*
-+ * Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
-+ * where 0 is the least significant end of the register.
-+ */
-+static long neon_element_offset(int reg, int element, MemOp size)
-+{
-+    int element_size = 1 << size;
-+    int ofs = element * element_size;
-+#ifdef HOST_WORDS_BIGENDIAN
-+    /*
-+     * Calculate the offset assuming fully little-endian,
-+     * then XOR to account for the order of the 8-byte units.
-+     */
-+    if (element_size < 8) {
-+        ofs ^= 8 - element_size;
-+    }
-+#endif
-+    return neon_full_reg_offset(reg) + ofs;
-+}
-+
- static inline long vfp_reg_offset(bool dp, unsigned reg)
- {
-     if (dp) {
-diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c.inc
-+++ b/target/arm/translate-neon.c.inc
-@@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x)
- #include "decode-neon-ls.c.inc"
- #include "decode-neon-shared.c.inc"
--/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
-- * where 0 is the least significant end of the register.
-- */
--static inline long
--neon_element_offset(int reg, int element, MemOp size)
--{
--    int element_size = 1 << size;
--    int ofs = element * element_size;
--#ifdef HOST_WORDS_BIGENDIAN
--    /* Calculate the offset assuming fully little-endian,
--     * then XOR to account for the order of the 8-byte units.
--     */
--    if (element_size < 8) {
--        ofs ^= 8 - element_size;
--    }
--#endif
--    return neon_full_reg_offset(reg) + ofs;
--}
--
- static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
- {
-     long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
---
-.20.1

-[PULL 03/26] target/arm: Use neon_element_offset in neon_load/store_reg
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-These are the only users of neon_reg_offset, so remove that.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-4-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate.c | 14 ++------------
-file changed, 2 insertions(+), 12 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg)
-     }
- }
--/* Return the offset of a 32-bit piece of a NEON register.
--   zero is the least significant end of the register.  */
--static inline long
--neon_reg_offset (int reg, int n)
--{
--    int sreg;
--    sreg = reg * 2 + n;
--    return vfp_reg_offset(0, sreg);
--}
--
- static TCGv_i32 neon_load_reg(int reg, int pass)
- {
-     TCGv_i32 tmp = tcg_temp_new_i32();
--    tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
-+    tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
-     return tmp;
- }
- static void neon_store_reg(int reg, int pass, TCGv_i32 var)
- {
--    tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
-+    tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
-     tcg_temp_free_i32(var);
- }
---
-.20.1

-[PULL 04/26] target/arm: Use neon_element_offset in vfp_reg_offset
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-This seems a bit more readable than using offsetof CPU_DoubleU.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-5-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate.c | 13 ++++---------
-file changed, 4 insertions(+), 9 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size)
-     return neon_full_reg_offset(reg) + ofs;
- }
--static inline long vfp_reg_offset(bool dp, unsigned reg)
-+/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */
-+static long vfp_reg_offset(bool dp, unsigned reg)
- {
-     if (dp) {
--        return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
-+        return neon_element_offset(reg, 0, MO_64);
-     } else {
--        long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]);
--        if (reg & 1) {
--            ofs += offsetof(CPU_DoubleU, l.upper);
--        } else {
--            ofs += offsetof(CPU_DoubleU, l.lower);
--        }
--        return ofs;
-+        return neon_element_offset(reg >> 1, reg & 1, MO_32);
-     }
- }
---
-.20.1

-[PULL 05/26] target/arm: Add read/write_neon_element32
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Model these off the aa64 read/write_vec_element functions.
-Use it within translate-neon.c.inc.  The new functions do
-not allocate or free temps, so this rearranges the calling
-code a bit.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-6-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate.c          |  26 ++++
- target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------
-files changed, 183 insertions(+), 99 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
-     tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
- }
-+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
-+{
-+    long off = neon_element_offset(reg, ele, size);
-+
-+    switch (size) {
-+    case MO_32:
-+        tcg_gen_ld_i32(dest, cpu_env, off);
-+        break;
-+    default:
-+        g_assert_not_reached();
-+    }
-+}
-+
-+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
-+{
-+    long off = neon_element_offset(reg, ele, size);
-+
-+    switch (size) {
-+    case MO_32:
-+        tcg_gen_st_i32(src, cpu_env, off);
-+        break;
-+    default:
-+        g_assert_not_reached();
-+    }
-+}
-+
- static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
- {
-     TCGv_ptr ret = tcg_temp_new_ptr();
-diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c.inc
-+++ b/target/arm/translate-neon.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
-      * early. Since Q is 0 there are always just two passes, so instead
-      * of a complicated loop over each pass we just unroll.
-      */
--    tmp = neon_load_reg(a->vn, 0);
--    tmp2 = neon_load_reg(a->vn, 1);
-+    tmp = tcg_temp_new_i32();
-+    tmp2 = tcg_temp_new_i32();
-+    tmp3 = tcg_temp_new_i32();
-+
-+    read_neon_element32(tmp, a->vn, 0, MO_32);
-+    read_neon_element32(tmp2, a->vn, 1, MO_32);
-     fn(tmp, tmp, tmp2);
--    tcg_temp_free_i32(tmp2);
--    tmp3 = neon_load_reg(a->vm, 0);
--    tmp2 = neon_load_reg(a->vm, 1);
-+    read_neon_element32(tmp3, a->vm, 0, MO_32);
-+    read_neon_element32(tmp2, a->vm, 1, MO_32);
-     fn(tmp3, tmp3, tmp2);
--    tcg_temp_free_i32(tmp2);
--    neon_store_reg(a->vd, 0, tmp);
--    neon_store_reg(a->vd, 1, tmp3);
-+    write_neon_element32(tmp, a->vd, 0, MO_32);
-+    write_neon_element32(tmp3, a->vd, 1, MO_32);
-+
-+    tcg_temp_free_i32(tmp);
-+    tcg_temp_free_i32(tmp2);
-+    tcg_temp_free_i32(tmp3);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
-      * 2-reg-and-shift operations, size < 3 case, where the
-      * helper needs to be passed cpu_env.
-      */
--    TCGv_i32 constimm;
-+    TCGv_i32 constimm, tmp;
-     int pass;
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
-      * by immediate using the variable shift operations.
-      */
-     constimm = tcg_const_i32(dup_const(a->size, a->shift));
-+    tmp = tcg_temp_new_i32();
-     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
--        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
-+        read_neon_element32(tmp, a->vm, pass, MO_32);
-         fn(tmp, cpu_env, tmp, constimm);
--        neon_store_reg(a->vd, pass, tmp);
-+        write_neon_element32(tmp, a->vd, pass, MO_32);
-     }
-+    tcg_temp_free_i32(tmp);
-     tcg_temp_free_i32(constimm);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
-     constimm = tcg_const_i64(-a->shift);
-     rm1 = tcg_temp_new_i64();
-     rm2 = tcg_temp_new_i64();
-+    rd = tcg_temp_new_i32();
-     /* Load both inputs first to avoid potential overwrite if rm == rd */
-     neon_load_reg64(rm1, a->vm);
-     neon_load_reg64(rm2, a->vm + 1);
-     shiftfn(rm1, rm1, constimm);
--    rd = tcg_temp_new_i32();
-     narrowfn(rd, cpu_env, rm1);
--    neon_store_reg(a->vd, 0, rd);
-+    write_neon_element32(rd, a->vd, 0, MO_32);
-     shiftfn(rm2, rm2, constimm);
--    rd = tcg_temp_new_i32();
-     narrowfn(rd, cpu_env, rm2);
--    neon_store_reg(a->vd, 1, rd);
-+    write_neon_element32(rd, a->vd, 1, MO_32);
-+    tcg_temp_free_i32(rd);
-     tcg_temp_free_i64(rm1);
-     tcg_temp_free_i64(rm2);
-     tcg_temp_free_i64(constimm);
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
-     constimm = tcg_const_i32(imm);
-     /* Load all inputs first to avoid potential overwrite */
--    rm1 = neon_load_reg(a->vm, 0);
--    rm2 = neon_load_reg(a->vm, 1);
--    rm3 = neon_load_reg(a->vm + 1, 0);
--    rm4 = neon_load_reg(a->vm + 1, 1);
-+    rm1 = tcg_temp_new_i32();
-+    rm2 = tcg_temp_new_i32();
-+    rm3 = tcg_temp_new_i32();
-+    rm4 = tcg_temp_new_i32();
-+    read_neon_element32(rm1, a->vm, 0, MO_32);
-+    read_neon_element32(rm2, a->vm, 1, MO_32);
-+    read_neon_element32(rm3, a->vm, 2, MO_32);
-+    read_neon_element32(rm4, a->vm, 3, MO_32);
-     rtmp = tcg_temp_new_i64();
-     shiftfn(rm1, rm1, constimm);
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
-     tcg_temp_free_i32(rm2);
-     narrowfn(rm1, cpu_env, rtmp);
--    neon_store_reg(a->vd, 0, rm1);
-+    write_neon_element32(rm1, a->vd, 0, MO_32);
-+    tcg_temp_free_i32(rm1);
-     shiftfn(rm3, rm3, constimm);
-     shiftfn(rm4, rm4, constimm);
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
-     narrowfn(rm3, cpu_env, rtmp);
-     tcg_temp_free_i64(rtmp);
--    neon_store_reg(a->vd, 1, rm3);
-+    write_neon_element32(rm3, a->vd, 1, MO_32);
-+    tcg_temp_free_i32(rm3);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
-         widen_mask = dup_const(a->size + 1, widen_mask);
-     }
--    rm0 = neon_load_reg(a->vm, 0);
--    rm1 = neon_load_reg(a->vm, 1);
-+    rm0 = tcg_temp_new_i32();
-+    rm1 = tcg_temp_new_i32();
-+    read_neon_element32(rm0, a->vm, 0, MO_32);
-+    read_neon_element32(rm1, a->vm, 1, MO_32);
-     tmp = tcg_temp_new_i64();
-     widenfn(tmp, rm0);
-@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
-     if (src1_wide) {
-         neon_load_reg64(rn0_64, a->vn);
-     } else {
--        TCGv_i32 tmp = neon_load_reg(a->vn, 0);
-+        TCGv_i32 tmp = tcg_temp_new_i32();
-+        read_neon_element32(tmp, a->vn, 0, MO_32);
-         widenfn(rn0_64, tmp);
-         tcg_temp_free_i32(tmp);
-     }
--    rm = neon_load_reg(a->vm, 0);
-+    rm = tcg_temp_new_i32();
-+    read_neon_element32(rm, a->vm, 0, MO_32);
-     widenfn(rm_64, rm);
-     tcg_temp_free_i32(rm);
-@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
-     if (src1_wide) {
-         neon_load_reg64(rn1_64, a->vn + 1);
-     } else {
--        TCGv_i32 tmp = neon_load_reg(a->vn, 1);
-+        TCGv_i32 tmp = tcg_temp_new_i32();
-+        read_neon_element32(tmp, a->vn, 1, MO_32);
-         widenfn(rn1_64, tmp);
-         tcg_temp_free_i32(tmp);
-     }
--    rm = neon_load_reg(a->vm, 1);
-+    rm = tcg_temp_new_i32();
-+    read_neon_element32(rm, a->vm, 1, MO_32);
-     neon_store_reg64(rn0_64, a->vd);
-@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
-     narrowfn(rd1, rn_64);
--    neon_store_reg(a->vd, 0, rd0);
--    neon_store_reg(a->vd, 1, rd1);
-+    write_neon_element32(rd0, a->vd, 0, MO_32);
-+    write_neon_element32(rd1, a->vd, 1, MO_32);
-+    tcg_temp_free_i32(rd0);
-+    tcg_temp_free_i32(rd1);
-     tcg_temp_free_i64(rn_64);
-     tcg_temp_free_i64(rm_64);
-@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
-     rd0 = tcg_temp_new_i64();
-     rd1 = tcg_temp_new_i64();
--    rn = neon_load_reg(a->vn, 0);
--    rm = neon_load_reg(a->vm, 0);
-+    rn = tcg_temp_new_i32();
-+    rm = tcg_temp_new_i32();
-+    read_neon_element32(rn, a->vn, 0, MO_32);
-+    read_neon_element32(rm, a->vm, 0, MO_32);
-     opfn(rd0, rn, rm);
--    tcg_temp_free_i32(rn);
--    tcg_temp_free_i32(rm);
--    rn = neon_load_reg(a->vn, 1);
--    rm = neon_load_reg(a->vm, 1);
-+    read_neon_element32(rn, a->vn, 1, MO_32);
-+    read_neon_element32(rm, a->vm, 1, MO_32);
-     opfn(rd1, rn, rm);
-     tcg_temp_free_i32(rn);
-     tcg_temp_free_i32(rm);
-@@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var)
- static inline TCGv_i32 neon_get_scalar(int size, int reg)
- {
--    TCGv_i32 tmp;
--    if (size == 1) {
--        tmp = neon_load_reg(reg & 7, reg >> 4);
-+    TCGv_i32 tmp = tcg_temp_new_i32();
-+    if (size == MO_16) {
-+        read_neon_element32(tmp, reg & 7, reg >> 4, MO_32);
-         if (reg & 8) {
-             gen_neon_dup_high16(tmp);
-         } else {
-             gen_neon_dup_low16(tmp);
-         }
-     } else {
--        tmp = neon_load_reg(reg & 15, reg >> 4);
-+        read_neon_element32(tmp, reg & 15, reg >> 4, MO_32);
-     }
-     return tmp;
- }
-@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
-      * perform an accumulation operation of that result into the
-      * destination.
-      */
--    TCGv_i32 scalar;
-+    TCGv_i32 scalar, tmp;
-     int pass;
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
-     }
-     scalar = neon_get_scalar(a->size, a->vm);
-+    tmp = tcg_temp_new_i32();
-     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
--        TCGv_i32 tmp = neon_load_reg(a->vn, pass);
-+        read_neon_element32(tmp, a->vn, pass, MO_32);
-         opfn(tmp, tmp, scalar);
-         if (accfn) {
--            TCGv_i32 rd = neon_load_reg(a->vd, pass);
-+            TCGv_i32 rd = tcg_temp_new_i32();
-+            read_neon_element32(rd, a->vd, pass, MO_32);
-             accfn(tmp, rd, tmp);
-             tcg_temp_free_i32(rd);
-         }
--        neon_store_reg(a->vd, pass, tmp);
-+        write_neon_element32(tmp, a->vd, pass, MO_32);
-     }
-+    tcg_temp_free_i32(tmp);
-     tcg_temp_free_i32(scalar);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
-      * performs a kind of fused op-then-accumulate using a helper
-      * function that takes all of rd, rn and the scalar at once.
-      */
--    TCGv_i32 scalar;
-+    TCGv_i32 scalar, rn, rd;
-     int pass;
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
-     }
-     scalar = neon_get_scalar(a->size, a->vm);
-+    rn = tcg_temp_new_i32();
-+    rd = tcg_temp_new_i32();
-     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
--        TCGv_i32 rn = neon_load_reg(a->vn, pass);
--        TCGv_i32 rd = neon_load_reg(a->vd, pass);
-+        read_neon_element32(rn, a->vn, pass, MO_32);
-+        read_neon_element32(rd, a->vd, pass, MO_32);
-         opfn(rd, cpu_env, rn, scalar, rd);
--        tcg_temp_free_i32(rn);
--        neon_store_reg(a->vd, pass, rd);
-+        write_neon_element32(rd, a->vd, pass, MO_32);
-     }
-+    tcg_temp_free_i32(rn);
-+    tcg_temp_free_i32(rd);
-     tcg_temp_free_i32(scalar);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
-     scalar = neon_get_scalar(a->size, a->vm);
-     /* Load all inputs before writing any outputs, in case of overlap */
--    rn = neon_load_reg(a->vn, 0);
-+    rn = tcg_temp_new_i32();
-+    read_neon_element32(rn, a->vn, 0, MO_32);
-     rn0_64 = tcg_temp_new_i64();
-     opfn(rn0_64, rn, scalar);
--    tcg_temp_free_i32(rn);
--    rn = neon_load_reg(a->vn, 1);
-+    read_neon_element32(rn, a->vn, 1, MO_32);
-     rn1_64 = tcg_temp_new_i64();
-     opfn(rn1_64, rn, scalar);
-     tcg_temp_free_i32(rn);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
-         return false;
-     }
-     n <<= 3;
-+    tmp = tcg_temp_new_i32();
-     if (a->op) {
--        tmp = neon_load_reg(a->vd, 0);
-+        read_neon_element32(tmp, a->vd, 0, MO_32);
-     } else {
--        tmp = tcg_temp_new_i32();
-         tcg_gen_movi_i32(tmp, 0);
-     }
--    tmp2 = neon_load_reg(a->vm, 0);
-+    tmp2 = tcg_temp_new_i32();
-+    read_neon_element32(tmp2, a->vm, 0, MO_32);
-     ptr1 = vfp_reg_ptr(true, a->vn);
-     tmp4 = tcg_const_i32(n);
-     gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
--    tcg_temp_free_i32(tmp);
-+
-     if (a->op) {
--        tmp = neon_load_reg(a->vd, 1);
-+        read_neon_element32(tmp, a->vd, 1, MO_32);
-     } else {
--        tmp = tcg_temp_new_i32();
-         tcg_gen_movi_i32(tmp, 0);
-     }
--    tmp3 = neon_load_reg(a->vm, 1);
-+    tmp3 = tcg_temp_new_i32();
-+    read_neon_element32(tmp3, a->vm, 1, MO_32);
-     gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
-+    tcg_temp_free_i32(tmp);
-     tcg_temp_free_i32(tmp4);
-     tcg_temp_free_ptr(ptr1);
--    neon_store_reg(a->vd, 0, tmp2);
--    neon_store_reg(a->vd, 1, tmp3);
--    tcg_temp_free_i32(tmp);
-+
-+    write_neon_element32(tmp2, a->vd, 0, MO_32);
-+    write_neon_element32(tmp3, a->vd, 1, MO_32);
-+    tcg_temp_free_i32(tmp2);
-+    tcg_temp_free_i32(tmp3);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
- static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
- {
-     int pass, half;
-+    TCGv_i32 tmp[2];
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-         return false;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
-         return true;
-     }
--    for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
--        TCGv_i32 tmp[2];
-+    tmp[0] = tcg_temp_new_i32();
-+    tmp[1] = tcg_temp_new_i32();
-+    for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
-         for (half = 0; half < 2; half++) {
--            tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
-+            read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32);
-             switch (a->size) {
-             case 0:
-                 tcg_gen_bswap32_i32(tmp[half], tmp[half]);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
-                 g_assert_not_reached();
-             }
-         }
--        neon_store_reg(a->vd, pass * 2, tmp[1]);
--        neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
-+        write_neon_element32(tmp[1], a->vd, pass * 2, MO_32);
-+        write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32);
-     }
-+
-+    tcg_temp_free_i32(tmp[0]);
-+    tcg_temp_free_i32(tmp[1]);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
-         rm0_64 = tcg_temp_new_i64();
-         rm1_64 = tcg_temp_new_i64();
-         rd_64 = tcg_temp_new_i64();
--        tmp = neon_load_reg(a->vm, pass * 2);
-+
-+        tmp = tcg_temp_new_i32();
-+        read_neon_element32(tmp, a->vm, pass * 2, MO_32);
-         widenfn(rm0_64, tmp);
--        tcg_temp_free_i32(tmp);
--        tmp = neon_load_reg(a->vm, pass * 2 + 1);
-+        read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32);
-         widenfn(rm1_64, tmp);
-         tcg_temp_free_i32(tmp);
-+
-         opfn(rd_64, rm0_64, rm1_64);
-         tcg_temp_free_i64(rm0_64);
-         tcg_temp_free_i64(rm1_64);
-@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
-     narrowfn(rd0, cpu_env, rm);
-     neon_load_reg64(rm, a->vm + 1);
-     narrowfn(rd1, cpu_env, rm);
--    neon_store_reg(a->vd, 0, rd0);
--    neon_store_reg(a->vd, 1, rd1);
-+    write_neon_element32(rd0, a->vd, 0, MO_32);
-+    write_neon_element32(rd1, a->vd, 1, MO_32);
-+    tcg_temp_free_i32(rd0);
-+    tcg_temp_free_i32(rd1);
-     tcg_temp_free_i64(rm);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
-     }
-     rd = tcg_temp_new_i64();
-+    rm0 = tcg_temp_new_i32();
-+    rm1 = tcg_temp_new_i32();
--    rm0 = neon_load_reg(a->vm, 0);
--    rm1 = neon_load_reg(a->vm, 1);
-+    read_neon_element32(rm0, a->vm, 0, MO_32);
-+    read_neon_element32(rm1, a->vm, 1, MO_32);
-     widenfn(rd, rm0);
-     tcg_gen_shli_i64(rd, rd, 8 << a->size);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
-     fpst = fpstatus_ptr(FPST_STD);
-     ahp = get_ahp_flag();
--    tmp = neon_load_reg(a->vm, 0);
-+    tmp = tcg_temp_new_i32();
-+    read_neon_element32(tmp, a->vm, 0, MO_32);
-     gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
--    tmp2 = neon_load_reg(a->vm, 1);
-+    tmp2 = tcg_temp_new_i32();
-+    read_neon_element32(tmp2, a->vm, 1, MO_32);
-     gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
-     tcg_gen_shli_i32(tmp2, tmp2, 16);
-     tcg_gen_or_i32(tmp2, tmp2, tmp);
--    tcg_temp_free_i32(tmp);
--    tmp = neon_load_reg(a->vm, 2);
-+    read_neon_element32(tmp, a->vm, 2, MO_32);
-     gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
--    tmp3 = neon_load_reg(a->vm, 3);
--    neon_store_reg(a->vd, 0, tmp2);
-+    tmp3 = tcg_temp_new_i32();
-+    read_neon_element32(tmp3, a->vm, 3, MO_32);
-+    write_neon_element32(tmp2, a->vd, 0, MO_32);
-+    tcg_temp_free_i32(tmp2);
-     gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
-     tcg_gen_shli_i32(tmp3, tmp3, 16);
-     tcg_gen_or_i32(tmp3, tmp3, tmp);
--    neon_store_reg(a->vd, 1, tmp3);
-+    write_neon_element32(tmp3, a->vd, 1, MO_32);
-+    tcg_temp_free_i32(tmp3);
-     tcg_temp_free_i32(tmp);
-     tcg_temp_free_i32(ahp);
-     tcg_temp_free_ptr(fpst);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
-     fpst = fpstatus_ptr(FPST_STD);
-     ahp = get_ahp_flag();
-     tmp3 = tcg_temp_new_i32();
--    tmp = neon_load_reg(a->vm, 0);
--    tmp2 = neon_load_reg(a->vm, 1);
-+    tmp2 = tcg_temp_new_i32();
-+    tmp = tcg_temp_new_i32();
-+    read_neon_element32(tmp, a->vm, 0, MO_32);
-+    read_neon_element32(tmp2, a->vm, 1, MO_32);
-     tcg_gen_ext16u_i32(tmp3, tmp);
-     gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
--    neon_store_reg(a->vd, 0, tmp3);
-+    write_neon_element32(tmp3, a->vd, 0, MO_32);
-     tcg_gen_shri_i32(tmp, tmp, 16);
-     gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
--    neon_store_reg(a->vd, 1, tmp);
--    tmp3 = tcg_temp_new_i32();
-+    write_neon_element32(tmp, a->vd, 1, MO_32);
-+    tcg_temp_free_i32(tmp);
-     tcg_gen_ext16u_i32(tmp3, tmp2);
-     gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
--    neon_store_reg(a->vd, 2, tmp3);
-+    write_neon_element32(tmp3, a->vd, 2, MO_32);
-+    tcg_temp_free_i32(tmp3);
-     tcg_gen_shri_i32(tmp2, tmp2, 16);
-     gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
--    neon_store_reg(a->vd, 3, tmp2);
-+    write_neon_element32(tmp2, a->vd, 3, MO_32);
-+    tcg_temp_free_i32(tmp2);
-     tcg_temp_free_i32(ahp);
-     tcg_temp_free_ptr(fpst);
-@@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
- static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
- {
-+    TCGv_i32 tmp;
-     int pass;
-     /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
-@@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
-         return true;
-     }
-+    tmp = tcg_temp_new_i32();
-     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
--        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
-+        read_neon_element32(tmp, a->vm, pass, MO_32);
-         fn(tmp, tmp);
--        neon_store_reg(a->vd, pass, tmp);
-+        write_neon_element32(tmp, a->vd, pass, MO_32);
-     }
-+    tcg_temp_free_i32(tmp);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a)
-         return true;
-     }
--    if (a->size == 2) {
-+    tmp = tcg_temp_new_i32();
-+    tmp2 = tcg_temp_new_i32();
-+    if (a->size == MO_32) {
-         for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
--            tmp = neon_load_reg(a->vm, pass);
--            tmp2 = neon_load_reg(a->vd, pass + 1);
--            neon_store_reg(a->vm, pass, tmp2);
--            neon_store_reg(a->vd, pass + 1, tmp);
-+            read_neon_element32(tmp, a->vm, pass, MO_32);
-+            read_neon_element32(tmp2, a->vd, pass + 1, MO_32);
-+            write_neon_element32(tmp2, a->vm, pass, MO_32);
-+            write_neon_element32(tmp, a->vd, pass + 1, MO_32);
-         }
-     } else {
-         for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
--            tmp = neon_load_reg(a->vm, pass);
--            tmp2 = neon_load_reg(a->vd, pass);
--            if (a->size == 0) {
-+            read_neon_element32(tmp, a->vm, pass, MO_32);
-+            read_neon_element32(tmp2, a->vd, pass, MO_32);
-+            if (a->size == MO_8) {
-                 gen_neon_trn_u8(tmp, tmp2);
-             } else {
-                 gen_neon_trn_u16(tmp, tmp2);
-             }
--            neon_store_reg(a->vm, pass, tmp2);
--            neon_store_reg(a->vd, pass, tmp);
-+            write_neon_element32(tmp2, a->vm, pass, MO_32);
-+            write_neon_element32(tmp, a->vd, pass, MO_32);
-         }
-     }
-+    tcg_temp_free_i32(tmp);
-+    tcg_temp_free_i32(tmp2);
-     return true;
- }
---
-.20.1

-[PULL 21/26] target/arm: Get correct MMU index for other-security-state
+[PULL 1/7] hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel
-In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to
+When we direct boot a kernel on a CPU which emulates EL3, we need
-armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el().
+to set up the EL3 system registers as the Linux kernel documentation
-This is incorrect when the security state being queried is not the
+specifies:
-current one, because arm_current_el() uses the current security state
+ https://www.kernel.org/doc/Documentation/arm64/booting.rst
 to determine which of the banked CONTROL.nPRIV bits to look at.
 The effect was that if (for instance) Secure state was in privileged
 mode but Non-Secure was not then we would return the wrong MMU index.
-The only places where we are using this function in a way that could
+For SVE and SME this includes:
-trigger this bug are for the stack loads during a v8M function-return
+    - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
-and for the instruction fetch of a v8M SG insn.
+      kernel is executed on.
     - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
       kernel will execute on.
-Fix the bug by expanding out the M-profile version of the
+Although we are technically compliant with this, the "same value" we
-arm_current_el() logic inline so it can use the passed in secstate
+currently use by default is the reset value of 0.  This will end up
-rather than env->v7m.secure.
+forcing the guest kernel's SVE and SME vector length to be only the
 smallest supported length.
 Initialize the vector length fields to their maximum possible value,
 which is 0xf. If the implementation doesn't actually support that
 vector length then the effective vector length will be constrained
 down to the maximum supported value at point of use.
 This allows the guest to use all the vector lengths the emulated CPU
 supports (by programming the _EL2 and _EL1 versions of these
 registers.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201022164408.13214-1-peter.maydell@linaro.org
+Message-id: 20221027140207.413084-2-peter.maydell@linaro.org
 ---
- target/arm/m_helper.c | 3 ++-
+ hw/arm/boot.c | 2 ++
-file changed, 2 insertions(+), 1 deletion(-)
+file changed, 2 insertions(+)
-diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/m_helper.c
+--- a/hw/arm/boot.c
-+++ b/target/arm/m_helper.c
++++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
- /* Return the MMU index for a v7M CPU in the specified security state */
+                     }
- ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+                     if (cpu_isar_feature(aa64_sve, cpu)) {
- {
+                         env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
--    bool priv = arm_current_el(env) != 0;
++                        env->vfp.zcr_el[3] = 0xf;
-+    bool priv = arm_v7m_is_handler_mode(env) ||
+                     }
-+        !(env->v7m.control[secstate] & 1);
+                     if (cpu_isar_feature(aa64_sme, cpu)) {
+                         env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
-     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+                         env->cp15.scr_el3 |= SCR_ENTP2;
- }
++                        env->vfp.smcr_el[3] = 0xf;
                      }
                      /* AArch64 kernels never boot in secure mode */
                      assert(!info->secure_boot);
 --
-.20.1
+.25.1

-[PULL 18/26] hw/arm/boot: fix SVE for EL3 direct kernel boot
+[PULL 2/7] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
-From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+When we direct boot a kernel on a CPU which emulates EL3, we need to
 set up the EL3 system registers as the Linux kernel documentation
 specifies:
      https://www.kernel.org/doc/Documentation/arm64/booting.rst
-When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so
+For CPUs with FEAT_HCX support this includes:
-that SVE will not trap to EL3.
+    - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
-Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+but we forgot to do this when implementing FEAT_HCX, which would mean
 that a guest trying to access the HCRX_EL2 register would crash.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030151541.11976-1-remi@remlab.net
+Message-id: 20221027140207.413084-3-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/arm/boot.c | 3 +++
 file changed, 3 insertions(+)
 diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/boot.c
 +++ b/hw/arm/boot.c
 @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
-                     if (cpu_isar_feature(aa64_mte, cpu)) {
+                         env->cp15.scr_el3 |= SCR_ENTP2;
-                         env->cp15.scr_el3 |= SCR_ATA;
+                         env->vfp.smcr_el[3] = 0xf;
                      }
-+                    if (cpu_isar_feature(aa64_sve, cpu)) {
++                    if (cpu_isar_feature(aa64_hcx, cpu)) {
-+                        env->cp15.cptr_el[3] |= CPTR_EZ;
++                        env->cp15.scr_el3 |= SCR_HXEN;
 +                    }
                      /* AArch64 kernels never boot in secure mode */
                      assert(!info->secure_boot);
                      /* This hook is only supported for AArch32 currently:
 --
-.20.1
+.25.1

-[PULL 15/26] target/arm: fix LORID_EL1 access check
+[PULL 3/7] target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
-From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+The HCR_EL2.TTLB bit is supposed to trap all EL1 execution of TLB
 maintenance instructions.  However we have added new TLB insns for
 FEAT_TLBIOS and FEAT_TLBIRANGE, and forgot to set their accessfn to
 access_ttlb.  Add the missing accessfns.
-Secure mode is not exempted from checking SCR_EL3.TLOR, and in the
-future HCR_EL2.TLOR when S-EL2 is enabled.
-Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- target/arm/helper.c | 19 +++++--------------
+ target/arm/helper.c | 36 ++++++++++++++++++------------------
-file changed, 5 insertions(+), 14 deletions(-)
+file changed, 18 insertions(+), 18 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
- #endif
+ static const ARMCPRegInfo tlbirange_reginfo[] = {
+     { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
- /* Shared logic between LORID and the rest of the LOR* registers.
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
-- * Secure state has already been delt with.
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
-+ * Secure state exclusion has already been dealt with.
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-  */
+       .writefn = tlbi_aa64_rvae1is_write },
--static CPAccessResult access_lor_ns(CPUARMState *env)
+     { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
-+static CPAccessResult access_lor_ns(CPUARMState *env,
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
-+                                    const ARMCPRegInfo *ri, bool isread)
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
- {
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-     int el = arm_current_el(env);
+       .writefn = tlbi_aa64_rvae1is_write },
+    { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env)
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
-     return CP_ACCESS_OK;
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
- }
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
+       .writefn = tlbi_aa64_rvae1is_write },
--static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,
+     { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
--                                   bool isread)
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
--{
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
--    if (arm_is_secure_below_el3(env)) {
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
--        /* Access ok in secure mode.  */
+       .writefn = tlbi_aa64_rvae1is_write },
--        return CP_ACCESS_OK;
+     { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
--    }
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
--    return access_lor_ns(env);
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
--}
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
--
+       .writefn = tlbi_aa64_rvae1is_write },
- static CPAccessResult access_lor_other(CPUARMState *env,
+     { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
-                                        const ARMCPRegInfo *ri, bool isread)
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
- {
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
-@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env,
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-         /* Access denied in secure mode.  */
+       .writefn = tlbi_aa64_rvae1is_write },
-         return CP_ACCESS_TRAP;
+    { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
-     }
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
--    return access_lor_ns(env);
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
-+    return access_lor_ns(env, ri, isread);
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
- }
+       .writefn = tlbi_aa64_rvae1is_write },
+     { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
- /*
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
-       .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-     { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
+       .writefn = tlbi_aa64_rvae1is_write },
-       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
+     { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
--      .access = PL1_R, .accessfn = access_lorid,
+       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
-+      .access = PL1_R, .accessfn = access_lor_ns,
+-      .access = PL1_W, .type = ARM_CP_NO_RAW,
-       .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
-     REGINFO_SENTINEL
+       .writefn = tlbi_aa64_rvae1_write },
- };
+     { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae1_write },
      { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_rvae1_write },
      { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
  static const ARMCPRegInfo tlbios_reginfo[] = {
      { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vmalle1is_write },
      { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vmalle1is_write },
      { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
 -      .access = PL1_W, .type = ARM_CP_NO_RAW,
 +      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
        .writefn = tlbi_aa64_vae1is_write },
      { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
 --
-.20.1
+.25.1

-[PULL 08/26] target/arm: Add read/write_neon_element64
+[PULL 4/7] target/arm: Fix Privileged Access Never (PAN) for aarch32
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Timofey Kutergin <tkutergin@gmail.com>
-Replace all uses of neon_load/store_reg64 within translate-neon.c.inc.
+When we implemented the PAN support we theoretically wanted
 to support it for both AArch32 and AArch64, but in practice
 several bugs made it essentially unusable with an AArch32
 guest. Fix all those problems:
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+    - Use CPSR.PAN to check for PAN state in aarch32 mode
-Message-id: 20201030022618.785675-9-richard.henderson@linaro.org
+    - throw permission fault during address translation when PAN is
       enabled and kernel tries to access user acessible page
     - ignore SCTLR_XP bit for armv7 and armv8 (conflicts with SCTLR_SPAN).
 Signed-off-by: Timofey Kutergin <tkutergin@gmail.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20221027112619.2205229-1-tkutergin@gmail.com
+[PMM: tweak commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c          | 26 +++++++++
+ target/arm/helper.c | 13 +++++++++++--
- target/arm/translate-neon.c.inc | 94 ++++++++++++++++-----------------
+ target/arm/ptw.c    | 35 ++++++++++++++++++++++++++++++-----
-files changed, 73 insertions(+), 47 deletions(-)
+files changed, 41 insertions(+), 7 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/helper.c
-+++ b/target/arm/translate.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
      }
  }
+ #endif
-+static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
 +static bool arm_pan_enabled(CPUARMState *env)
 +{
-+    long off = neon_element_offset(reg, ele, memop);
++    if (is_a64(env)) {
-+
++        return env->pstate & PSTATE_PAN;
-+    switch (memop) {
++    } else {
-+    case MO_Q:
++        return env->uncached_cpsr & CPSR_PAN;
 +        tcg_gen_ld_i64(dest, cpu_env, off);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
- static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
+ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
  {
-     long off = neon_element_offset(reg, ele, memop);
+     ARMMMUIdx idx;
-@@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
          }
          break;
      case 1:
 -        if (env->pstate & PSTATE_PAN) {
 +        if (arm_pan_enabled(env)) {
              idx = ARMMMUIdx_E10_1_PAN;
          } else {
              idx = ARMMMUIdx_E10_1;
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
      case 2:
          /* Note that TGE does not apply at EL2.  */
          if (arm_hcr_el2_eff(env) & HCR_E2H) {
 -            if (env->pstate & PSTATE_PAN) {
 +            if (arm_pan_enabled(env)) {
                  idx = ARMMMUIdx_E20_2_PAN;
              } else {
                  idx = ARMMMUIdx_E20_2;
 diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/ptw.c
 +++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
   * @mmu_idx:     MMU index indicating required translation regime
   * @ap:          The 3-bit access permissions (AP[2:0])
   * @domain_prot: The 2-bit domain access permissions
 + * @is_user: TRUE if accessing from PL0
   */
 -static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
 -                         int ap, int domain_prot)
 +static int ap_to_rw_prot_is_user(CPUARMState *env, ARMMMUIdx mmu_idx,
 +                         int ap, int domain_prot, bool is_user)
  {
 -    bool is_user = regime_is_user(env, mmu_idx);
 -
      if (domain_prot == 3) {
          return PAGE_READ | PAGE_WRITE;
      }
@@ -XXX,XX +XXX,XX @@ static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
      }
  }
-+static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
++/*
 + * Translate section/page access permissions to page R/W protection flags
 + * @env:         CPUARMState
 + * @mmu_idx:     MMU index indicating required translation regime
 + * @ap:          The 3-bit access permissions (AP[2:0])
 + * @domain_prot: The 2-bit domain access permissions
 + */
 +static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
 +                         int ap, int domain_prot)
 +{
-+    long off = neon_element_offset(reg, ele, memop);
++   return ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot,
-+
++                                regime_is_user(env, mmu_idx));
 +    switch (memop) {
 +    case MO_64:
 +        tcg_gen_st_i64(src, cpu_env, off);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
- static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
+ /*
- {
+  * Translate section/page access permissions to page R/W protection flags.
-     TCGv_ptr ret = tcg_temp_new_ptr();
+  * @ap:      The 2-bit simple AP (AP[2:1])
-diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
-index XXXXXXX..XXXXXXX 100644
+     hwaddr phys_addr;
---- a/target/arm/translate-neon.c.inc
+     uint32_t dacr;
-+++ b/target/arm/translate-neon.c.inc
+     bool ns;
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
++    int user_prot;
-     for (pass = 0; pass < a->q + 1; pass++) {
-         TCGv_i64 tmp = tcg_temp_new_i64();
+     /* Pagetable walk.  */
+     /* Lookup l1 descriptor.  */
--        neon_load_reg64(tmp, a->vm + pass);
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
-+        read_neon_element64(tmp, a->vm, pass, MO_64);
+                 goto do_fault;
-         fn(tmp, cpu_env, tmp, constimm);
+             }
--        neon_store_reg64(tmp, a->vd + pass);
+             result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
-+        write_neon_element64(tmp, a->vd, pass, MO_64);
++            user_prot = simple_ap_to_rw_prot_is_user(ap >> 1, 1);
-         tcg_temp_free_i64(tmp);
+         } else {
              result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
 +            user_prot = ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot, 1);
          }
          if (result->f.prot && !xn) {
              result->f.prot |= PAGE_EXEC;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
              fi->type = ARMFault_Permission;
              goto do_fault;
          }
 +        if (regime_is_pan(env, mmu_idx) &&
 +            !regime_is_user(env, mmu_idx) &&
 +            user_prot &&
 +            access_type != MMU_INST_FETCH) {
 +            /* Privileged Access Never fault */
 +            fi->type = ARMFault_Permission;
 +            goto do_fault;
 +        }
      }
-     tcg_temp_free_i64(constimm);
+     if (ns) {
-@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
+         /* The NS bit will (as required by the architecture) have no effect if
-     rd = tcg_temp_new_i32();
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
+     if (regime_using_lpae_format(env, mmu_idx)) {
-     /* Load both inputs first to avoid potential overwrite if rm == rd */
+         return get_phys_addr_lpae(env, ptw, address, access_type, false,
--    neon_load_reg64(rm1, a->vm);
+                                   result, fi);
--    neon_load_reg64(rm2, a->vm + 1);
+-    } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
-+    read_neon_element64(rm1, a->vm, 0, MO_64);
++    } else if (arm_feature(env, ARM_FEATURE_V7) ||
-+    read_neon_element64(rm2, a->vm, 1, MO_64);
++               regime_sctlr(env, mmu_idx) & SCTLR_XP) {
+         return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
      shiftfn(rm1, rm1, constimm);
      narrowfn(rd, cpu_env, rm1);
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
          tcg_gen_shli_i64(tmp, tmp, a->shift);
          tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
      }
 -    neon_store_reg64(tmp, a->vd);
 +    write_neon_element64(tmp, a->vd, 0, MO_64);
      widenfn(tmp, rm1);
      tcg_temp_free_i32(rm1);
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
          tcg_gen_shli_i64(tmp, tmp, a->shift);
          tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
      }
 -    neon_store_reg64(tmp, a->vd + 1);
 +    write_neon_element64(tmp, a->vd, 1, MO_64);
      tcg_temp_free_i64(tmp);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
      rm_64 = tcg_temp_new_i64();
      if (src1_wide) {
 -        neon_load_reg64(rn0_64, a->vn);
 +        read_neon_element64(rn0_64, a->vn, 0, MO_64);
      } else {
-         TCGv_i32 tmp = tcg_temp_new_i32();
+         return get_phys_addr_v5(env, ptw, address, access_type, result, fi);
          read_neon_element32(tmp, a->vn, 0, MO_32);
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
       * avoid incorrect results if a narrow input overlaps with the result.
       */
      if (src1_wide) {
 -        neon_load_reg64(rn1_64, a->vn + 1);
 +        read_neon_element64(rn1_64, a->vn, 1, MO_64);
      } else {
          TCGv_i32 tmp = tcg_temp_new_i32();
          read_neon_element32(tmp, a->vn, 1, MO_32);
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
      rm = tcg_temp_new_i32();
      read_neon_element32(rm, a->vm, 1, MO_32);
 -    neon_store_reg64(rn0_64, a->vd);
 +    write_neon_element64(rn0_64, a->vd, 0, MO_64);
      widenfn(rm_64, rm);
      tcg_temp_free_i32(rm);
      opfn(rn1_64, rn1_64, rm_64);
 -    neon_store_reg64(rn1_64, a->vd + 1);
 +    write_neon_element64(rn1_64, a->vd, 1, MO_64);
      tcg_temp_free_i64(rn0_64);
      tcg_temp_free_i64(rn1_64);
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
      rd0 = tcg_temp_new_i32();
      rd1 = tcg_temp_new_i32();
 -    neon_load_reg64(rn_64, a->vn);
 -    neon_load_reg64(rm_64, a->vm);
 +    read_neon_element64(rn_64, a->vn, 0, MO_64);
 +    read_neon_element64(rm_64, a->vm, 0, MO_64);
      opfn(rn_64, rn_64, rm_64);
      narrowfn(rd0, rn_64);
 -    neon_load_reg64(rn_64, a->vn + 1);
 -    neon_load_reg64(rm_64, a->vm + 1);
 +    read_neon_element64(rn_64, a->vn, 1, MO_64);
 +    read_neon_element64(rm_64, a->vm, 1, MO_64);
      opfn(rn_64, rn_64, rm_64);
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
      /* Don't store results until after all loads: they might overlap */
      if (accfn) {
          tmp = tcg_temp_new_i64();
 -        neon_load_reg64(tmp, a->vd);
 +        read_neon_element64(tmp, a->vd, 0, MO_64);
          accfn(tmp, tmp, rd0);
 -        neon_store_reg64(tmp, a->vd);
 -        neon_load_reg64(tmp, a->vd + 1);
 +        write_neon_element64(tmp, a->vd, 0, MO_64);
 +        read_neon_element64(tmp, a->vd, 1, MO_64);
          accfn(tmp, tmp, rd1);
 -        neon_store_reg64(tmp, a->vd + 1);
 +        write_neon_element64(tmp, a->vd, 1, MO_64);
          tcg_temp_free_i64(tmp);
      } else {
 -        neon_store_reg64(rd0, a->vd);
 -        neon_store_reg64(rd1, a->vd + 1);
 +        write_neon_element64(rd0, a->vd, 0, MO_64);
 +        write_neon_element64(rd1, a->vd, 1, MO_64);
      }
      tcg_temp_free_i64(rd0);
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
      if (accfn) {
          TCGv_i64 t64 = tcg_temp_new_i64();
 -        neon_load_reg64(t64, a->vd);
 +        read_neon_element64(t64, a->vd, 0, MO_64);
          accfn(t64, t64, rn0_64);
 -        neon_store_reg64(t64, a->vd);
 -        neon_load_reg64(t64, a->vd + 1);
 +        write_neon_element64(t64, a->vd, 0, MO_64);
 +        read_neon_element64(t64, a->vd, 1, MO_64);
          accfn(t64, t64, rn1_64);
 -        neon_store_reg64(t64, a->vd + 1);
 +        write_neon_element64(t64, a->vd, 1, MO_64);
          tcg_temp_free_i64(t64);
      } else {
 -        neon_store_reg64(rn0_64, a->vd);
 -        neon_store_reg64(rn1_64, a->vd + 1);
 +        write_neon_element64(rn0_64, a->vd, 0, MO_64);
 +        write_neon_element64(rn1_64, a->vd, 1, MO_64);
      }
      tcg_temp_free_i64(rn0_64);
      tcg_temp_free_i64(rn1_64);
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
          right = tcg_temp_new_i64();
          dest = tcg_temp_new_i64();
 -        neon_load_reg64(right, a->vn);
 -        neon_load_reg64(left, a->vm);
 +        read_neon_element64(right, a->vn, 0, MO_64);
 +        read_neon_element64(left, a->vm, 0, MO_64);
          tcg_gen_extract2_i64(dest, right, left, a->imm * 8);
 -        neon_store_reg64(dest, a->vd);
 +        write_neon_element64(dest, a->vd, 0, MO_64);
          tcg_temp_free_i64(left);
          tcg_temp_free_i64(right);
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
          destright = tcg_temp_new_i64();
          if (a->imm < 8) {
 -            neon_load_reg64(right, a->vn);
 -            neon_load_reg64(middle, a->vn + 1);
 +            read_neon_element64(right, a->vn, 0, MO_64);
 +            read_neon_element64(middle, a->vn, 1, MO_64);
              tcg_gen_extract2_i64(destright, right, middle, a->imm * 8);
 -            neon_load_reg64(left, a->vm);
 +            read_neon_element64(left, a->vm, 0, MO_64);
              tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8);
          } else {
 -            neon_load_reg64(right, a->vn + 1);
 -            neon_load_reg64(middle, a->vm);
 +            read_neon_element64(right, a->vn, 1, MO_64);
 +            read_neon_element64(middle, a->vm, 0, MO_64);
              tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8);
 -            neon_load_reg64(left, a->vm + 1);
 +            read_neon_element64(left, a->vm, 1, MO_64);
              tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8);
          }
 -        neon_store_reg64(destright, a->vd);
 -        neon_store_reg64(destleft, a->vd + 1);
 +        write_neon_element64(destright, a->vd, 0, MO_64);
 +        write_neon_element64(destleft, a->vd, 1, MO_64);
          tcg_temp_free_i64(destright);
          tcg_temp_free_i64(destleft);
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
          if (accfn) {
              TCGv_i64 tmp64 = tcg_temp_new_i64();
 -            neon_load_reg64(tmp64, a->vd + pass);
 +            read_neon_element64(tmp64, a->vd, pass, MO_64);
              accfn(rd_64, tmp64, rd_64);
              tcg_temp_free_i64(tmp64);
          }
 -        neon_store_reg64(rd_64, a->vd + pass);
 +        write_neon_element64(rd_64, a->vd, pass, MO_64);
          tcg_temp_free_i64(rd_64);
      }
      return true;
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
      rd0 = tcg_temp_new_i32();
      rd1 = tcg_temp_new_i32();
 -    neon_load_reg64(rm, a->vm);
 +    read_neon_element64(rm, a->vm, 0, MO_64);
      narrowfn(rd0, cpu_env, rm);
 -    neon_load_reg64(rm, a->vm + 1);
 +    read_neon_element64(rm, a->vm, 1, MO_64);
      narrowfn(rd1, cpu_env, rm);
      write_neon_element32(rd0, a->vd, 0, MO_32);
      write_neon_element32(rd1, a->vd, 1, MO_32);
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
      widenfn(rd, rm0);
      tcg_gen_shli_i64(rd, rd, 8 << a->size);
 -    neon_store_reg64(rd, a->vd);
 +    write_neon_element64(rd, a->vd, 0, MO_64);
      widenfn(rd, rm1);
      tcg_gen_shli_i64(rd, rd, 8 << a->size);
 -    neon_store_reg64(rd, a->vd + 1);
 +    write_neon_element64(rd, a->vd, 1, MO_64);
      tcg_temp_free_i64(rd);
      tcg_temp_free_i32(rm0);
@@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
      rm = tcg_temp_new_i64();
      rd = tcg_temp_new_i64();
      for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
 -        neon_load_reg64(rm, a->vm + pass);
 -        neon_load_reg64(rd, a->vd + pass);
 -        neon_store_reg64(rm, a->vd + pass);
 -        neon_store_reg64(rd, a->vm + pass);
 +        read_neon_element64(rm, a->vm, pass, MO_64);
 +        read_neon_element64(rd, a->vd, pass, MO_64);
 +        write_neon_element64(rm, a->vd, pass, MO_64);
 +        write_neon_element64(rd, a->vm, pass, MO_64);
      }
      tcg_temp_free_i64(rm);
      tcg_temp_free_i64(rd);
 --
-.20.1
+.25.1

-[PULL 06/26] target/arm: Expand read/write_neon_element32 to all MemOp
+[PULL 5/7] target/arm: Copy the entire vector in DO_ZIP
 From: Richard Henderson <richard.henderson@linaro.org>
-We can then use this to improve VMOV (scalar to gp) and
+With odd_ofs set, we weren't copying enough data.
 VMOV (gp to scalar) so that we simply perform the memory
 operation that we wanted, rather than inserting or
 extracting from a 32-bit quantity.
-These were the last uses of neon_load/store_reg, so remove them.
+Fixes: 09eb6d7025d1 ("target/arm: Move sve zip high_ofs into simd_data")
+Reported-by: Idan Horowitz <idan.horowitz@gmail.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-7-richard.henderson@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20221031054144.3574-1-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c         | 50 +++++++++++++-----------
+ target/arm/sve_helper.c | 4 ++--
- target/arm/translate-vfp.c.inc | 71 +++++-----------------------------
+file changed, 2 insertions(+), 2 deletions(-)
 files changed, 37 insertions(+), 84 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/sve_helper.c
-+++ b/target/arm/translate.c
++++ b/target/arm/sve_helper.c
-@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
+@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc)       \
-  * Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
+     /* We produce output faster than we consume input.               \
-  * where 0 is the least significant end of the register.
+        Therefore we must be mindful of possible overlap.  */         \
-  */
+     if (unlikely((vn - vd) < (uintptr_t)oprsz)) {                    \
--static long neon_element_offset(int reg, int element, MemOp size)
+-        vn = memcpy(&tmp_n, vn, oprsz_2);                            \
-+static long neon_element_offset(int reg, int element, MemOp memop)
++        vn = memcpy(&tmp_n, vn, oprsz);                              \
- {
+     }                                                                \
--    int element_size = 1 << size;
+     if (unlikely((vm - vd) < (uintptr_t)oprsz)) {                    \
-+    int element_size = 1 << (memop & MO_SIZE);
+-        vm = memcpy(&tmp_m, vm, oprsz_2);                            \
-     int ofs = element * element_size;
++        vm = memcpy(&tmp_m, vm, oprsz);                              \
- #ifdef HOST_WORDS_BIGENDIAN
+     }                                                                \
-     /*
+     for (i = 0; i < oprsz_2; i += sizeof(TYPE)) {                    \
-@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
+         *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + odd_ofs + H(i)); \
      }
  }
 -static TCGv_i32 neon_load_reg(int reg, int pass)
 -{
 -    TCGv_i32 tmp = tcg_temp_new_i32();
 -    tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
 -    return tmp;
 -}
 -
 -static void neon_store_reg(int reg, int pass, TCGv_i32 var)
 -{
 -    tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
 -    tcg_temp_free_i32(var);
 -}
 -
  static inline void neon_load_reg64(TCGv_i64 var, int reg)
  {
      tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
      tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
  }
 -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
 +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
  {
 -    long off = neon_element_offset(reg, ele, size);
 +    long off = neon_element_offset(reg, ele, memop);
 -    switch (size) {
 -    case MO_32:
 +    switch (memop) {
 +    case MO_SB:
 +        tcg_gen_ld8s_i32(dest, cpu_env, off);
 +        break;
 +    case MO_UB:
 +        tcg_gen_ld8u_i32(dest, cpu_env, off);
 +        break;
 +    case MO_SW:
 +        tcg_gen_ld16s_i32(dest, cpu_env, off);
 +        break;
 +    case MO_UW:
 +        tcg_gen_ld16u_i32(dest, cpu_env, off);
 +        break;
 +    case MO_UL:
 +    case MO_SL:
          tcg_gen_ld_i32(dest, cpu_env, off);
          break;
      default:
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
      }
  }
 -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
 +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
  {
 -    long off = neon_element_offset(reg, ele, size);
 +    long off = neon_element_offset(reg, ele, memop);
 -    switch (size) {
 +    switch (memop) {
 +    case MO_8:
 +        tcg_gen_st8_i32(src, cpu_env, off);
 +        break;
 +    case MO_16:
 +        tcg_gen_st16_i32(src, cpu_env, off);
 +        break;
      case MO_32:
          tcg_gen_st_i32(src, cpu_env, off);
          break;
 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-vfp.c.inc
 +++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
  {
      /* VMOV scalar to general purpose register */
      TCGv_i32 tmp;
 -    int pass;
 -    uint32_t offset;
 -    /* SIZE == 2 is a VFP instruction; otherwise NEON.  */
 -    if (a->size == 2
 +    /* SIZE == MO_32 is a VFP instruction; otherwise NEON.  */
 +    if (a->size == MO_32
          ? !dc_isar_feature(aa32_fpsp_v2, s)
          : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
          return false;
      }
 -    offset = a->index << a->size;
 -    pass = extract32(offset, 2, 1);
 -    offset = extract32(offset, 0, 2) * 8;
 -
      if (!vfp_access_check(s)) {
          return true;
      }
 -    tmp = neon_load_reg(a->vn, pass);
 -    switch (a->size) {
 -    case 0:
 -        if (offset) {
 -            tcg_gen_shri_i32(tmp, tmp, offset);
 -        }
 -        if (a->u) {
 -            gen_uxtb(tmp);
 -        } else {
 -            gen_sxtb(tmp);
 -        }
 -        break;
 -    case 1:
 -        if (a->u) {
 -            if (offset) {
 -                tcg_gen_shri_i32(tmp, tmp, 16);
 -            } else {
 -                gen_uxth(tmp);
 -            }
 -        } else {
 -            if (offset) {
 -                tcg_gen_sari_i32(tmp, tmp, 16);
 -            } else {
 -                gen_sxth(tmp);
 -            }
 -        }
 -        break;
 -    case 2:
 -        break;
 -    }
 +    tmp = tcg_temp_new_i32();
 +    read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN));
      store_reg(s, a->rt, tmp);
      return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
  static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
  {
      /* VMOV general purpose register to scalar */
 -    TCGv_i32 tmp, tmp2;
 -    int pass;
 -    uint32_t offset;
 +    TCGv_i32 tmp;
 -    /* SIZE == 2 is a VFP instruction; otherwise NEON.  */
 -    if (a->size == 2
 +    /* SIZE == MO_32 is a VFP instruction; otherwise NEON.  */
 +    if (a->size == MO_32
          ? !dc_isar_feature(aa32_fpsp_v2, s)
          : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
          return false;
      }
 -    offset = a->index << a->size;
 -    pass = extract32(offset, 2, 1);
 -    offset = extract32(offset, 0, 2) * 8;
 -
      if (!vfp_access_check(s)) {
          return true;
      }
      tmp = load_reg(s, a->rt);
 -    switch (a->size) {
 -    case 0:
 -        tmp2 = neon_load_reg(a->vn, pass);
 -        tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
 -        tcg_temp_free_i32(tmp2);
 -        break;
 -    case 1:
 -        tmp2 = neon_load_reg(a->vn, pass);
 -        tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
 -        tcg_temp_free_i32(tmp2);
 -        break;
 -    case 2:
 -        break;
 -    }
 -    neon_store_reg(a->vn, pass, tmp);
 +    write_neon_element32(tmp, a->vn, a->index, a->size);
 +    tcg_temp_free_i32(tmp);
      return true;
  }
 --
-.20.1
+.25.1

-[PULL 07/26] target/arm: Rename neon_load_reg32 to vfp_load_reg32
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The only uses of this function are for loading VFP
-single-precision values, and nothing to do with NEON.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-8-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate.c         |   4 +-
- target/arm/translate-vfp.c.inc | 184 ++++++++++++++++-----------------
-files changed, 94 insertions(+), 94 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg)
-     tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
- }
--static inline void neon_load_reg32(TCGv_i32 var, int reg)
-+static inline void vfp_load_reg32(TCGv_i32 var, int reg)
- {
-     tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
- }
--static inline void neon_store_reg32(TCGv_i32 var, int reg)
-+static inline void vfp_store_reg32(TCGv_i32 var, int reg)
- {
-     tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
- }
-diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-vfp.c.inc
-+++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
-         frn = tcg_temp_new_i32();
-         frm = tcg_temp_new_i32();
-         dest = tcg_temp_new_i32();
--        neon_load_reg32(frn, rn);
--        neon_load_reg32(frm, rm);
-+        vfp_load_reg32(frn, rn);
-+        vfp_load_reg32(frm, rm);
-         switch (a->cc) {
-         case 0: /* eq: Z */
-             tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
-         if (sz == 1) {
-             tcg_gen_andi_i32(dest, dest, 0xffff);
-         }
--        neon_store_reg32(dest, rd);
-+        vfp_store_reg32(dest, rd);
-         tcg_temp_free_i32(frn);
-         tcg_temp_free_i32(frm);
-         tcg_temp_free_i32(dest);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
-         TCGv_i32 tcg_res;
-         tcg_op = tcg_temp_new_i32();
-         tcg_res = tcg_temp_new_i32();
--        neon_load_reg32(tcg_op, rm);
-+        vfp_load_reg32(tcg_op, rm);
-         if (sz == 1) {
-             gen_helper_rinth(tcg_res, tcg_op, fpst);
-         } else {
-             gen_helper_rints(tcg_res, tcg_op, fpst);
-         }
--        neon_store_reg32(tcg_res, rd);
-+        vfp_store_reg32(tcg_res, rd);
-         tcg_temp_free_i32(tcg_op);
-         tcg_temp_free_i32(tcg_res);
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
-             gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
-         }
-         tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
--        neon_store_reg32(tcg_tmp, rd);
-+        vfp_store_reg32(tcg_tmp, rd);
-         tcg_temp_free_i32(tcg_tmp);
-         tcg_temp_free_i64(tcg_res);
-         tcg_temp_free_i64(tcg_double);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
-         TCGv_i32 tcg_single, tcg_res;
-         tcg_single = tcg_temp_new_i32();
-         tcg_res = tcg_temp_new_i32();
--        neon_load_reg32(tcg_single, rm);
-+        vfp_load_reg32(tcg_single, rm);
-         if (sz == 1) {
-             if (is_signed) {
-                 gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
-                 gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
-             }
-         }
--        neon_store_reg32(tcg_res, rd);
-+        vfp_store_reg32(tcg_res, rd);
-         tcg_temp_free_i32(tcg_res);
-         tcg_temp_free_i32(tcg_single);
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
-     if (a->l) {
-         /* VFP to general purpose register */
-         tmp = tcg_temp_new_i32();
--        neon_load_reg32(tmp, a->vn);
-+        vfp_load_reg32(tmp, a->vn);
-         tcg_gen_andi_i32(tmp, tmp, 0xffff);
-         store_reg(s, a->rt, tmp);
-     } else {
-         /* general purpose register to VFP */
-         tmp = load_reg(s, a->rt);
-         tcg_gen_andi_i32(tmp, tmp, 0xffff);
--        neon_store_reg32(tmp, a->vn);
-+        vfp_store_reg32(tmp, a->vn);
-         tcg_temp_free_i32(tmp);
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
-     if (a->l) {
-         /* VFP to general purpose register */
-         tmp = tcg_temp_new_i32();
--        neon_load_reg32(tmp, a->vn);
-+        vfp_load_reg32(tmp, a->vn);
-         if (a->rt == 15) {
-             /* Set the 4 flag bits in the CPSR.  */
-             gen_set_nzcv(tmp);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
-     } else {
-         /* general purpose register to VFP */
-         tmp = load_reg(s, a->rt);
--        neon_store_reg32(tmp, a->vn);
-+        vfp_store_reg32(tmp, a->vn);
-         tcg_temp_free_i32(tmp);
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
-     if (a->op) {
-         /* fpreg to gpreg */
-         tmp = tcg_temp_new_i32();
--        neon_load_reg32(tmp, a->vm);
-+        vfp_load_reg32(tmp, a->vm);
-         store_reg(s, a->rt, tmp);
-         tmp = tcg_temp_new_i32();
--        neon_load_reg32(tmp, a->vm + 1);
-+        vfp_load_reg32(tmp, a->vm + 1);
-         store_reg(s, a->rt2, tmp);
-     } else {
-         /* gpreg to fpreg */
-         tmp = load_reg(s, a->rt);
--        neon_store_reg32(tmp, a->vm);
-+        vfp_store_reg32(tmp, a->vm);
-         tcg_temp_free_i32(tmp);
-         tmp = load_reg(s, a->rt2);
--        neon_store_reg32(tmp, a->vm + 1);
-+        vfp_store_reg32(tmp, a->vm + 1);
-         tcg_temp_free_i32(tmp);
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
-     if (a->op) {
-         /* fpreg to gpreg */
-         tmp = tcg_temp_new_i32();
--        neon_load_reg32(tmp, a->vm * 2);
-+        vfp_load_reg32(tmp, a->vm * 2);
-         store_reg(s, a->rt, tmp);
-         tmp = tcg_temp_new_i32();
--        neon_load_reg32(tmp, a->vm * 2 + 1);
-+        vfp_load_reg32(tmp, a->vm * 2 + 1);
-         store_reg(s, a->rt2, tmp);
-     } else {
-         /* gpreg to fpreg */
-         tmp = load_reg(s, a->rt);
--        neon_store_reg32(tmp, a->vm * 2);
-+        vfp_store_reg32(tmp, a->vm * 2);
-         tcg_temp_free_i32(tmp);
-         tmp = load_reg(s, a->rt2);
--        neon_store_reg32(tmp, a->vm * 2 + 1);
-+        vfp_store_reg32(tmp, a->vm * 2 + 1);
-         tcg_temp_free_i32(tmp);
-     }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a)
-     tmp = tcg_temp_new_i32();
-     if (a->l) {
-         gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
--        neon_store_reg32(tmp, a->vd);
-+        vfp_store_reg32(tmp, a->vd);
-     } else {
--        neon_load_reg32(tmp, a->vd);
-+        vfp_load_reg32(tmp, a->vd);
-         gen_aa32_st16(s, tmp, addr, get_mem_index(s));
-     }
-     tcg_temp_free_i32(tmp);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
-     tmp = tcg_temp_new_i32();
-     if (a->l) {
-         gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
--        neon_store_reg32(tmp, a->vd);
-+        vfp_store_reg32(tmp, a->vd);
-     } else {
--        neon_load_reg32(tmp, a->vd);
-+        vfp_load_reg32(tmp, a->vd);
-         gen_aa32_st32(s, tmp, addr, get_mem_index(s));
-     }
-     tcg_temp_free_i32(tmp);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
-         if (a->l) {
-             /* load */
-             gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
--            neon_store_reg32(tmp, a->vd + i);
-+            vfp_store_reg32(tmp, a->vd + i);
-         } else {
-             /* store */
--            neon_load_reg32(tmp, a->vd + i);
-+            vfp_load_reg32(tmp, a->vd + i);
-             gen_aa32_st32(s, tmp, addr, get_mem_index(s));
-         }
-         tcg_gen_addi_i32(addr, addr, offset);
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
-     fd = tcg_temp_new_i32();
-     fpst = fpstatus_ptr(FPST_FPCR);
--    neon_load_reg32(f0, vn);
--    neon_load_reg32(f1, vm);
-+    vfp_load_reg32(f0, vn);
-+    vfp_load_reg32(f1, vm);
-     for (;;) {
-         if (reads_vd) {
--            neon_load_reg32(fd, vd);
-+            vfp_load_reg32(fd, vd);
-         }
-         fn(fd, f0, f1, fpst);
--        neon_store_reg32(fd, vd);
-+        vfp_store_reg32(fd, vd);
-         if (veclen == 0) {
-             break;
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
-         veclen--;
-         vd = vfp_advance_sreg(vd, delta_d);
-         vn = vfp_advance_sreg(vn, delta_d);
--        neon_load_reg32(f0, vn);
-+        vfp_load_reg32(f0, vn);
-         if (delta_m) {
-             vm = vfp_advance_sreg(vm, delta_m);
--            neon_load_reg32(f1, vm);
-+            vfp_load_reg32(f1, vm);
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn,
-     fd = tcg_temp_new_i32();
-     fpst = fpstatus_ptr(FPST_FPCR_F16);
--    neon_load_reg32(f0, vn);
--    neon_load_reg32(f1, vm);
-+    vfp_load_reg32(f0, vn);
-+    vfp_load_reg32(f1, vm);
-     if (reads_vd) {
--        neon_load_reg32(fd, vd);
-+        vfp_load_reg32(fd, vd);
-     }
-     fn(fd, f0, f1, fpst);
--    neon_store_reg32(fd, vd);
-+    vfp_store_reg32(fd, vd);
-     tcg_temp_free_i32(f0);
-     tcg_temp_free_i32(f1);
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
-     f0 = tcg_temp_new_i32();
-     fd = tcg_temp_new_i32();
--    neon_load_reg32(f0, vm);
-+    vfp_load_reg32(f0, vm);
-     for (;;) {
-         fn(fd, f0);
--        neon_store_reg32(fd, vd);
-+        vfp_store_reg32(fd, vd);
-         if (veclen == 0) {
-             break;
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
-             /* single source one-many */
-             while (veclen--) {
-                 vd = vfp_advance_sreg(vd, delta_d);
--                neon_store_reg32(fd, vd);
-+                vfp_store_reg32(fd, vd);
-             }
-             break;
-         }
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
-         veclen--;
-         vd = vfp_advance_sreg(vd, delta_d);
-         vm = vfp_advance_sreg(vm, delta_m);
--        neon_load_reg32(f0, vm);
-+        vfp_load_reg32(f0, vm);
-     }
-     tcg_temp_free_i32(f0);
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
-     }
-     f0 = tcg_temp_new_i32();
--    neon_load_reg32(f0, vm);
-+    vfp_load_reg32(f0, vm);
-     fn(f0, f0);
--    neon_store_reg32(f0, vd);
-+    vfp_store_reg32(f0, vd);
-     tcg_temp_free_i32(f0);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
-     vm = tcg_temp_new_i32();
-     vd = tcg_temp_new_i32();
--    neon_load_reg32(vn, a->vn);
--    neon_load_reg32(vm, a->vm);
-+    vfp_load_reg32(vn, a->vn);
-+    vfp_load_reg32(vm, a->vm);
-     if (neg_n) {
-         /* VFNMS, VFMS */
-         gen_helper_vfp_negh(vn, vn);
-     }
--    neon_load_reg32(vd, a->vd);
-+    vfp_load_reg32(vd, a->vd);
-     if (neg_d) {
-         /* VFNMA, VFNMS */
-         gen_helper_vfp_negh(vd, vd);
-     }
-     fpst = fpstatus_ptr(FPST_FPCR_F16);
-     gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst);
--    neon_store_reg32(vd, a->vd);
-+    vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(vn);
-@@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
-     vm = tcg_temp_new_i32();
-     vd = tcg_temp_new_i32();
--    neon_load_reg32(vn, a->vn);
--    neon_load_reg32(vm, a->vm);
-+    vfp_load_reg32(vn, a->vn);
-+    vfp_load_reg32(vm, a->vm);
-     if (neg_n) {
-         /* VFNMS, VFMS */
-         gen_helper_vfp_negs(vn, vn);
-     }
--    neon_load_reg32(vd, a->vd);
-+    vfp_load_reg32(vd, a->vd);
-     if (neg_d) {
-         /* VFNMA, VFNMS */
-         gen_helper_vfp_negs(vd, vd);
-     }
-     fpst = fpstatus_ptr(FPST_FPCR);
-     gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
--    neon_store_reg32(vd, a->vd);
-+    vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(vn);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a)
-     }
-     fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm));
--    neon_store_reg32(fd, a->vd);
-+    vfp_store_reg32(fd, a->vd);
-     tcg_temp_free_i32(fd);
-     return true;
- }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
-     fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
-     for (;;) {
--        neon_store_reg32(fd, vd);
-+        vfp_store_reg32(fd, vd);
-         if (veclen == 0) {
-             break;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a)
-     vd = tcg_temp_new_i32();
-     vm = tcg_temp_new_i32();
--    neon_load_reg32(vd, a->vd);
-+    vfp_load_reg32(vd, a->vd);
-     if (a->z) {
-         tcg_gen_movi_i32(vm, 0);
-     } else {
--        neon_load_reg32(vm, a->vm);
-+        vfp_load_reg32(vm, a->vm);
-     }
-     if (a->e) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
-     vd = tcg_temp_new_i32();
-     vm = tcg_temp_new_i32();
--    neon_load_reg32(vd, a->vd);
-+    vfp_load_reg32(vd, a->vd);
-     if (a->z) {
-         tcg_gen_movi_i32(vm, 0);
-     } else {
--        neon_load_reg32(vm, a->vm);
-+        vfp_load_reg32(vm, a->vm);
-     }
-     if (a->e) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
-     /* The T bit tells us if we want the low or high 16 bits of Vm */
-     tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
-     gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
--    neon_store_reg32(tmp, a->vd);
-+    vfp_store_reg32(tmp, a->vd);
-     tcg_temp_free_i32(ahp_mode);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(tmp);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
-     ahp_mode = get_ahp_flag();
-     tmp = tcg_temp_new_i32();
--    neon_load_reg32(tmp, a->vm);
-+    vfp_load_reg32(tmp, a->vm);
-     gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
-     tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
-     tcg_temp_free_i32(ahp_mode);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a)
-     }
-     tmp = tcg_temp_new_i32();
--    neon_load_reg32(tmp, a->vm);
-+    vfp_load_reg32(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR_F16);
-     gen_helper_rinth(tmp, tmp, fpst);
--    neon_store_reg32(tmp, a->vd);
-+    vfp_store_reg32(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(tmp);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
-     }
-     tmp = tcg_temp_new_i32();
--    neon_load_reg32(tmp, a->vm);
-+    vfp_load_reg32(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     gen_helper_rints(tmp, tmp, fpst);
--    neon_store_reg32(tmp, a->vd);
-+    vfp_store_reg32(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(tmp);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
-     }
-     tmp = tcg_temp_new_i32();
--    neon_load_reg32(tmp, a->vm);
-+    vfp_load_reg32(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR_F16);
-     tcg_rmode = tcg_const_i32(float_round_to_zero);
-     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-     gen_helper_rinth(tmp, tmp, fpst);
-     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
--    neon_store_reg32(tmp, a->vd);
-+    vfp_store_reg32(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(tcg_rmode);
-     tcg_temp_free_i32(tmp);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
-     }
-     tmp = tcg_temp_new_i32();
--    neon_load_reg32(tmp, a->vm);
-+    vfp_load_reg32(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     tcg_rmode = tcg_const_i32(float_round_to_zero);
-     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-     gen_helper_rints(tmp, tmp, fpst);
-     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
--    neon_store_reg32(tmp, a->vd);
-+    vfp_store_reg32(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(tcg_rmode);
-     tcg_temp_free_i32(tmp);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a)
-     }
-     tmp = tcg_temp_new_i32();
--    neon_load_reg32(tmp, a->vm);
-+    vfp_load_reg32(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR_F16);
-     gen_helper_rinth_exact(tmp, tmp, fpst);
--    neon_store_reg32(tmp, a->vd);
-+    vfp_store_reg32(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(tmp);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
-     }
-     tmp = tcg_temp_new_i32();
--    neon_load_reg32(tmp, a->vm);
-+    vfp_load_reg32(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     gen_helper_rints_exact(tmp, tmp, fpst);
--    neon_store_reg32(tmp, a->vd);
-+    vfp_store_reg32(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(tmp);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
-     vm = tcg_temp_new_i32();
-     vd = tcg_temp_new_i64();
--    neon_load_reg32(vm, a->vm);
-+    vfp_load_reg32(vm, a->vm);
-     gen_helper_vfp_fcvtds(vd, vm, cpu_env);
-     neon_store_reg64(vd, a->vd);
-     tcg_temp_free_i32(vm);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
-     vm = tcg_temp_new_i64();
-     neon_load_reg64(vm, a->vm);
-     gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
--    neon_store_reg32(vd, a->vd);
-+    vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_i32(vd);
-     tcg_temp_free_i64(vm);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
-     }
-     vm = tcg_temp_new_i32();
--    neon_load_reg32(vm, a->vm);
-+    vfp_load_reg32(vm, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR_F16);
-     if (a->s) {
-         /* i32 -> f16 */
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
-         /* u32 -> f16 */
-         gen_helper_vfp_uitoh(vm, vm, fpst);
-     }
--    neon_store_reg32(vm, a->vd);
-+    vfp_store_reg32(vm, a->vd);
-     tcg_temp_free_i32(vm);
-     tcg_temp_free_ptr(fpst);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
-     }
-     vm = tcg_temp_new_i32();
--    neon_load_reg32(vm, a->vm);
-+    vfp_load_reg32(vm, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     if (a->s) {
-         /* i32 -> f32 */
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
-         /* u32 -> f32 */
-         gen_helper_vfp_uitos(vm, vm, fpst);
-     }
--    neon_store_reg32(vm, a->vd);
-+    vfp_store_reg32(vm, a->vd);
-     tcg_temp_free_i32(vm);
-     tcg_temp_free_ptr(fpst);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
-     vm = tcg_temp_new_i32();
-     vd = tcg_temp_new_i64();
--    neon_load_reg32(vm, a->vm);
-+    vfp_load_reg32(vm, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     if (a->s) {
-         /* i32 -> f64 */
-@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
-     vd = tcg_temp_new_i32();
-     neon_load_reg64(vm, a->vm);
-     gen_helper_vjcvt(vd, vm, cpu_env);
--    neon_store_reg32(vd, a->vd);
-+    vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_i64(vm);
-     tcg_temp_free_i32(vd);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
-     frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
-     vd = tcg_temp_new_i32();
--    neon_load_reg32(vd, a->vd);
-+    vfp_load_reg32(vd, a->vd);
-     fpst = fpstatus_ptr(FPST_FPCR_F16);
-     shift = tcg_const_i32(frac_bits);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
-         g_assert_not_reached();
-     }
--    neon_store_reg32(vd, a->vd);
-+    vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_i32(vd);
-     tcg_temp_free_i32(shift);
-     tcg_temp_free_ptr(fpst);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
-     frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
-     vd = tcg_temp_new_i32();
--    neon_load_reg32(vd, a->vd);
-+    vfp_load_reg32(vd, a->vd);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     shift = tcg_const_i32(frac_bits);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
-         g_assert_not_reached();
-     }
--    neon_store_reg32(vd, a->vd);
-+    vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_i32(vd);
-     tcg_temp_free_i32(shift);
-     tcg_temp_free_ptr(fpst);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
-     fpst = fpstatus_ptr(FPST_FPCR_F16);
-     vm = tcg_temp_new_i32();
--    neon_load_reg32(vm, a->vm);
-+    vfp_load_reg32(vm, a->vm);
-     if (a->s) {
-         if (a->rz) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
-             gen_helper_vfp_touih(vm, vm, fpst);
-         }
-     }
--    neon_store_reg32(vm, a->vd);
-+    vfp_store_reg32(vm, a->vd);
-     tcg_temp_free_i32(vm);
-     tcg_temp_free_ptr(fpst);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
-     fpst = fpstatus_ptr(FPST_FPCR);
-     vm = tcg_temp_new_i32();
--    neon_load_reg32(vm, a->vm);
-+    vfp_load_reg32(vm, a->vm);
-     if (a->s) {
-         if (a->rz) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
-             gen_helper_vfp_touis(vm, vm, fpst);
-         }
-     }
--    neon_store_reg32(vm, a->vd);
-+    vfp_store_reg32(vm, a->vd);
-     tcg_temp_free_i32(vm);
-     tcg_temp_free_ptr(fpst);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
-             gen_helper_vfp_touid(vd, vm, fpst);
-         }
-     }
--    neon_store_reg32(vd, a->vd);
-+    vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_i32(vd);
-     tcg_temp_free_i64(vm);
-     tcg_temp_free_ptr(fpst);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a)
-     /* Insert low half of Vm into high half of Vd */
-     rm = tcg_temp_new_i32();
-     rd = tcg_temp_new_i32();
--    neon_load_reg32(rm, a->vm);
--    neon_load_reg32(rd, a->vd);
-+    vfp_load_reg32(rm, a->vm);
-+    vfp_load_reg32(rd, a->vd);
-     tcg_gen_deposit_i32(rd, rd, rm, 16, 16);
--    neon_store_reg32(rd, a->vd);
-+    vfp_store_reg32(rd, a->vd);
-     tcg_temp_free_i32(rm);
-     tcg_temp_free_i32(rd);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a)
-     /* Set Vd to high half of Vm */
-     rm = tcg_temp_new_i32();
--    neon_load_reg32(rm, a->vm);
-+    vfp_load_reg32(rm, a->vm);
-     tcg_gen_shri_i32(rm, rm, 16);
--    neon_store_reg32(rm, a->vd);
-+    vfp_store_reg32(rm, a->vd);
-     tcg_temp_free_i32(rm);
-     return true;
- }
---
-.20.1

-[PULL 09/26] target/arm: Rename neon_load_reg64 to vfp_load_reg64
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-The only uses of this function are for loading VFP
-double-precision values, and nothing to do with NEON.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-10-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate.c         |  8 ++--
- target/arm/translate-vfp.c.inc | 84 +++++++++++++++++-----------------
-files changed, 46 insertions(+), 46 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
-     }
- }
--static inline void neon_load_reg64(TCGv_i64 var, int reg)
-+static inline void vfp_load_reg64(TCGv_i64 var, int reg)
- {
--    tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
-+    tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
- }
--static inline void neon_store_reg64(TCGv_i64 var, int reg)
-+static inline void vfp_store_reg64(TCGv_i64 var, int reg)
- {
--    tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
-+    tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
- }
- static inline void vfp_load_reg32(TCGv_i32 var, int reg)
-diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-vfp.c.inc
-+++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
-         tcg_gen_ext_i32_i64(nf, cpu_NF);
-         tcg_gen_ext_i32_i64(vf, cpu_VF);
--        neon_load_reg64(frn, rn);
--        neon_load_reg64(frm, rm);
-+        vfp_load_reg64(frn, rn);
-+        vfp_load_reg64(frm, rm);
-         switch (a->cc) {
-         case 0: /* eq: Z */
-             tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
-@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
-             tcg_temp_free_i64(tmp);
-             break;
-         }
--        neon_store_reg64(dest, rd);
-+        vfp_store_reg64(dest, rd);
-         tcg_temp_free_i64(frn);
-         tcg_temp_free_i64(frm);
-         tcg_temp_free_i64(dest);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
-         TCGv_i64 tcg_res;
-         tcg_op = tcg_temp_new_i64();
-         tcg_res = tcg_temp_new_i64();
--        neon_load_reg64(tcg_op, rm);
-+        vfp_load_reg64(tcg_op, rm);
-         gen_helper_rintd(tcg_res, tcg_op, fpst);
--        neon_store_reg64(tcg_res, rd);
-+        vfp_store_reg64(tcg_res, rd);
-         tcg_temp_free_i64(tcg_op);
-         tcg_temp_free_i64(tcg_res);
-     } else {
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
-         tcg_double = tcg_temp_new_i64();
-         tcg_res = tcg_temp_new_i64();
-         tcg_tmp = tcg_temp_new_i32();
--        neon_load_reg64(tcg_double, rm);
-+        vfp_load_reg64(tcg_double, rm);
-         if (is_signed) {
-             gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
-         } else {
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
-     tmp = tcg_temp_new_i64();
-     if (a->l) {
-         gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
--        neon_store_reg64(tmp, a->vd);
-+        vfp_store_reg64(tmp, a->vd);
-     } else {
--        neon_load_reg64(tmp, a->vd);
-+        vfp_load_reg64(tmp, a->vd);
-         gen_aa32_st64(s, tmp, addr, get_mem_index(s));
-     }
-     tcg_temp_free_i64(tmp);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
-         if (a->l) {
-             /* load */
-             gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
--            neon_store_reg64(tmp, a->vd + i);
-+            vfp_store_reg64(tmp, a->vd + i);
-         } else {
-             /* store */
--            neon_load_reg64(tmp, a->vd + i);
-+            vfp_load_reg64(tmp, a->vd + i);
-             gen_aa32_st64(s, tmp, addr, get_mem_index(s));
-         }
-         tcg_gen_addi_i32(addr, addr, offset);
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
-     fd = tcg_temp_new_i64();
-     fpst = fpstatus_ptr(FPST_FPCR);
--    neon_load_reg64(f0, vn);
--    neon_load_reg64(f1, vm);
-+    vfp_load_reg64(f0, vn);
-+    vfp_load_reg64(f1, vm);
-     for (;;) {
-         if (reads_vd) {
--            neon_load_reg64(fd, vd);
-+            vfp_load_reg64(fd, vd);
-         }
-         fn(fd, f0, f1, fpst);
--        neon_store_reg64(fd, vd);
-+        vfp_store_reg64(fd, vd);
-         if (veclen == 0) {
-             break;
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
-         veclen--;
-         vd = vfp_advance_dreg(vd, delta_d);
-         vn = vfp_advance_dreg(vn, delta_d);
--        neon_load_reg64(f0, vn);
-+        vfp_load_reg64(f0, vn);
-         if (delta_m) {
-             vm = vfp_advance_dreg(vm, delta_m);
--            neon_load_reg64(f1, vm);
-+            vfp_load_reg64(f1, vm);
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
-     f0 = tcg_temp_new_i64();
-     fd = tcg_temp_new_i64();
--    neon_load_reg64(f0, vm);
-+    vfp_load_reg64(f0, vm);
-     for (;;) {
-         fn(fd, f0);
--        neon_store_reg64(fd, vd);
-+        vfp_store_reg64(fd, vd);
-         if (veclen == 0) {
-             break;
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
-             /* single source one-many */
-             while (veclen--) {
-                 vd = vfp_advance_dreg(vd, delta_d);
--                neon_store_reg64(fd, vd);
-+                vfp_store_reg64(fd, vd);
-             }
-             break;
-         }
-@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
-         veclen--;
-         vd = vfp_advance_dreg(vd, delta_d);
-         vd = vfp_advance_dreg(vm, delta_m);
--        neon_load_reg64(f0, vm);
-+        vfp_load_reg64(f0, vm);
-     }
-     tcg_temp_free_i64(f0);
-@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
-     vm = tcg_temp_new_i64();
-     vd = tcg_temp_new_i64();
--    neon_load_reg64(vn, a->vn);
--    neon_load_reg64(vm, a->vm);
-+    vfp_load_reg64(vn, a->vn);
-+    vfp_load_reg64(vm, a->vm);
-     if (neg_n) {
-         /* VFNMS, VFMS */
-         gen_helper_vfp_negd(vn, vn);
-     }
--    neon_load_reg64(vd, a->vd);
-+    vfp_load_reg64(vd, a->vd);
-     if (neg_d) {
-         /* VFNMA, VFNMS */
-         gen_helper_vfp_negd(vd, vd);
-     }
-     fpst = fpstatus_ptr(FPST_FPCR);
-     gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
--    neon_store_reg64(vd, a->vd);
-+    vfp_store_reg64(vd, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i64(vn);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
-     fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
-     for (;;) {
--        neon_store_reg64(fd, vd);
-+        vfp_store_reg64(fd, vd);
-         if (veclen == 0) {
-             break;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
-     vd = tcg_temp_new_i64();
-     vm = tcg_temp_new_i64();
--    neon_load_reg64(vd, a->vd);
-+    vfp_load_reg64(vd, a->vd);
-     if (a->z) {
-         tcg_gen_movi_i64(vm, 0);
-     } else {
--        neon_load_reg64(vm, a->vm);
-+        vfp_load_reg64(vm, a->vm);
-     }
-     if (a->e) {
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
-     tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
-     vd = tcg_temp_new_i64();
-     gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
--    neon_store_reg64(vd, a->vd);
-+    vfp_store_reg64(vd, a->vd);
-     tcg_temp_free_i32(ahp_mode);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i32(tmp);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
-     tmp = tcg_temp_new_i32();
-     vm = tcg_temp_new_i64();
--    neon_load_reg64(vm, a->vm);
-+    vfp_load_reg64(vm, a->vm);
-     gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
-     tcg_temp_free_i64(vm);
-     tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
-     }
-     tmp = tcg_temp_new_i64();
--    neon_load_reg64(tmp, a->vm);
-+    vfp_load_reg64(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     gen_helper_rintd(tmp, tmp, fpst);
--    neon_store_reg64(tmp, a->vd);
-+    vfp_store_reg64(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i64(tmp);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
-     }
-     tmp = tcg_temp_new_i64();
--    neon_load_reg64(tmp, a->vm);
-+    vfp_load_reg64(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     tcg_rmode = tcg_const_i32(float_round_to_zero);
-     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-     gen_helper_rintd(tmp, tmp, fpst);
-     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
--    neon_store_reg64(tmp, a->vd);
-+    vfp_store_reg64(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i64(tmp);
-     tcg_temp_free_i32(tcg_rmode);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
-     }
-     tmp = tcg_temp_new_i64();
--    neon_load_reg64(tmp, a->vm);
-+    vfp_load_reg64(tmp, a->vm);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     gen_helper_rintd_exact(tmp, tmp, fpst);
--    neon_store_reg64(tmp, a->vd);
-+    vfp_store_reg64(tmp, a->vd);
-     tcg_temp_free_ptr(fpst);
-     tcg_temp_free_i64(tmp);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
-     vd = tcg_temp_new_i64();
-     vfp_load_reg32(vm, a->vm);
-     gen_helper_vfp_fcvtds(vd, vm, cpu_env);
--    neon_store_reg64(vd, a->vd);
-+    vfp_store_reg64(vd, a->vd);
-     tcg_temp_free_i32(vm);
-     tcg_temp_free_i64(vd);
-     return true;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
-     vd = tcg_temp_new_i32();
-     vm = tcg_temp_new_i64();
--    neon_load_reg64(vm, a->vm);
-+    vfp_load_reg64(vm, a->vm);
-     gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
-     vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_i32(vd);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
-         /* u32 -> f64 */
-         gen_helper_vfp_uitod(vd, vm, fpst);
-     }
--    neon_store_reg64(vd, a->vd);
-+    vfp_store_reg64(vd, a->vd);
-     tcg_temp_free_i32(vm);
-     tcg_temp_free_i64(vd);
-     tcg_temp_free_ptr(fpst);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
-     vm = tcg_temp_new_i64();
-     vd = tcg_temp_new_i32();
--    neon_load_reg64(vm, a->vm);
-+    vfp_load_reg64(vm, a->vm);
-     gen_helper_vjcvt(vd, vm, cpu_env);
-     vfp_store_reg32(vd, a->vd);
-     tcg_temp_free_i64(vm);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
-     frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
-     vd = tcg_temp_new_i64();
--    neon_load_reg64(vd, a->vd);
-+    vfp_load_reg64(vd, a->vd);
-     fpst = fpstatus_ptr(FPST_FPCR);
-     shift = tcg_const_i32(frac_bits);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
-         g_assert_not_reached();
-     }
--    neon_store_reg64(vd, a->vd);
-+    vfp_store_reg64(vd, a->vd);
-     tcg_temp_free_i64(vd);
-     tcg_temp_free_i32(shift);
-     tcg_temp_free_ptr(fpst);
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
-     fpst = fpstatus_ptr(FPST_FPCR);
-     vm = tcg_temp_new_i64();
-     vd = tcg_temp_new_i32();
--    neon_load_reg64(vm, a->vm);
-+    vfp_load_reg64(vm, a->vm);
-     if (a->s) {
-         if (a->rz) {
---
-.20.1

-[PULL 10/26] target/arm: Simplify do_long_3d and do_2scalar_long
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-In both cases, we can sink the write-back and perform
-the accumulate into the normal destination temps.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-11-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/translate-neon.c.inc | 23 +++++++++--------------
-file changed, 9 insertions(+), 14 deletions(-)
-diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c.inc
-+++ b/target/arm/translate-neon.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
-     if (accfn) {
-         tmp = tcg_temp_new_i64();
-         read_neon_element64(tmp, a->vd, 0, MO_64);
--        accfn(tmp, tmp, rd0);
--        write_neon_element64(tmp, a->vd, 0, MO_64);
-+        accfn(rd0, tmp, rd0);
-         read_neon_element64(tmp, a->vd, 1, MO_64);
--        accfn(tmp, tmp, rd1);
--        write_neon_element64(tmp, a->vd, 1, MO_64);
-+        accfn(rd1, tmp, rd1);
-         tcg_temp_free_i64(tmp);
--    } else {
--        write_neon_element64(rd0, a->vd, 0, MO_64);
--        write_neon_element64(rd1, a->vd, 1, MO_64);
-     }
-+    write_neon_element64(rd0, a->vd, 0, MO_64);
-+    write_neon_element64(rd1, a->vd, 1, MO_64);
-     tcg_temp_free_i64(rd0);
-     tcg_temp_free_i64(rd1);
-@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
-     if (accfn) {
-         TCGv_i64 t64 = tcg_temp_new_i64();
-         read_neon_element64(t64, a->vd, 0, MO_64);
--        accfn(t64, t64, rn0_64);
--        write_neon_element64(t64, a->vd, 0, MO_64);
-+        accfn(rn0_64, t64, rn0_64);
-         read_neon_element64(t64, a->vd, 1, MO_64);
--        accfn(t64, t64, rn1_64);
--        write_neon_element64(t64, a->vd, 1, MO_64);
-+        accfn(rn1_64, t64, rn1_64);
-         tcg_temp_free_i64(t64);
--    } else {
--        write_neon_element64(rn0_64, a->vd, 0, MO_64);
--        write_neon_element64(rn1_64, a->vd, 1, MO_64);
-     }
-+
-+    write_neon_element64(rn0_64, a->vd, 0, MO_64);
-+    write_neon_element64(rn1_64, a->vd, 1, MO_64);
-     tcg_temp_free_i64(rn0_64);
-     tcg_temp_free_i64(rn1_64);
-     return true;
---
-.20.1

-[PULL 14/26] target/arm: fix handling of HCR.FB
+[PULL 6/7] target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()
-From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+From: Ake Koomsin <ake@igel.co.jp>
-HCR should be applied when NS is set, not when it is cleared.
+We need to check HCR_E2H and HCR_TGE to select the right MMU index for
 the correct translation regime.
-Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
+To check for EL2&0 translation regime:
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+- For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE
 - For S1E2* ops, check only HCR_E2H
 Signed-off-by: Ake Koomsin <ake@igel.co.jp>
 Message-id: 20221101064250.12444-1-ake@igel.co.jp
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 5 ++---
+ target/arm/helper.c | 15 +++++++++------
-file changed, 2 insertions(+), 3 deletions(-)
+file changed, 9 insertions(+), 6 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
+     MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
- /*
+     ARMMMUIdx mmu_idx;
-  * Non-IS variants of TLB operations are upgraded to
+     int secure = arm_is_secure_below_el3(env);
-- * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
++    uint64_t hcr_el2 = arm_hcr_el2_eff(env);
-+ * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
++    bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE);
-  * force broadcast of these operations.
-  */
+     switch (ri->opc2 & 6) {
- static bool tlb_force_broadcast(CPUARMState *env)
+     case 0:
- {
+         switch (ri->opc1) {
--    return (env->cp15.hcr_el2 & HCR_FB) &&
+         case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
--        arm_current_el(env) == 1 && arm_is_secure_below_el3(env);
+             if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
-+    return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
+-                mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
- }
++                mmu_idx = regime_e20 ?
++                          ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN;
- static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
+             } else {
 -                mmu_idx = ARMMMUIdx_Stage1_E1;
 +                mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_E1;
              }
              break;
          case 4: /* AT S1E2R, AT S1E2W */
 -            mmu_idx = ARMMMUIdx_E2;
 +            mmu_idx = hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2;
              break;
          case 6: /* AT S1E3R, AT S1E3W */
              mmu_idx = ARMMMUIdx_E3;
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
          }
          break;
      case 2: /* AT S1E0R, AT S1E0W */
 -        mmu_idx = ARMMMUIdx_Stage1_E0;
 +        mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0;
          break;
      case 4: /* AT S12E1R, AT S12E1W */
 -        mmu_idx = ARMMMUIdx_E10_1;
 +        mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1;
          break;
      case 6: /* AT S12E0R, AT S12E0W */
 -        mmu_idx = ARMMMUIdx_E10_0;
 +        mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0;
          break;
      default:
          g_assert_not_reached();
 --
-.20.1
+.25.1

-[PULL 11/26] target/arm: Improve do_prewiden_3d
+[PULL 7/7] target/arm: Two fixes for secure ptw
 From: Richard Henderson <richard.henderson@linaro.org>
-We can use proper widening loads to extend 32-bit inputs,
+Reversed the sense of non-secure in get_phys_addr_lpae,
-and skip the "widenfn" step.
+and failed to initialize attrs.secure for ARMMMUIdx_Phys_S.
+Fixes: 48da29e4 ("target/arm: Add ptw_idx to S1Translate")
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1293
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20201030022618.785675-12-richard.henderson@linaro.org
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c          |  6 +++
+ target/arm/ptw.c | 15 ++++++++-------
- target/arm/translate-neon.c.inc | 66 ++++++++++++++++++---------------
+file changed, 8 insertions(+), 7 deletions(-)
 files changed, 43 insertions(+), 29 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/ptw.c
-+++ b/target/arm/translate.c
++++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
-     long off = neon_element_offset(reg, ele, memop);
+     descaddr |= (address >> (stride * (4 - level))) & indexmask;
+     descaddr &= ~7ULL;
-     switch (memop) {
+     nstable = extract32(tableattrs, 4, 1);
-+    case MO_SL:
+-    if (!nstable) {
-+        tcg_gen_ld32s_i64(dest, cpu_env, off);
++    if (nstable) {
-+        break;
+         /*
-+    case MO_UL:
+          * Stage2_S -> Stage2 or Phys_S -> Phys_NS
-+        tcg_gen_ld32u_i64(dest, cpu_env, off);
+          * Assert that the non-secure idx are even, and relative order.
-+        break;
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
-     case MO_Q:
+     bool is_secure = ptw->in_secure;
-         tcg_gen_ld_i64(dest, cpu_env, off);
+     ARMMMUIdx s1_mmu_idx;
 +    /*
 +     * The page table entries may downgrade secure to non-secure, but
 +     * cannot upgrade an non-secure translation regime's attributes
 +     * to secure.
 +     */
 +    result->f.attrs.secure = is_secure;
 +
      switch (mmu_idx) {
      case ARMMMUIdx_Phys_S:
      case ARMMMUIdx_Phys_NS:
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
          break;
-diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c.inc
-+++ b/target/arm/translate-neon.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
- static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
-                            NeonGenWidenFn *widenfn,
-                            NeonGenTwo64OpFn *opfn,
--                           bool src1_wide)
-+                           int src1_mop, int src2_mop)
- {
-     /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */
-     TCGv_i64 rn0_64, rn1_64, rm_64;
--    TCGv_i32 rm;
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-         return false;
-@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
-         return false;
      }
--    if (!widenfn || !opfn) {
+-    /*
-+    if (!opfn) {
+-     * The page table entries may downgrade secure to non-secure, but
-         /* size == 3 case, which is an entirely different insn group */
+-     * cannot upgrade an non-secure translation regime's attributes
-         return false;
+-     * to secure.
-     }
+-     */
+-    result->f.attrs.secure = is_secure;
--    if ((a->vd & 1) || (src1_wide && (a->vn & 1))) {
+     result->f.attrs.user = regime_is_user(env, mmu_idx);
 +    if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
      rn1_64 = tcg_temp_new_i64();
      rm_64 = tcg_temp_new_i64();
 -    if (src1_wide) {
 -        read_neon_element64(rn0_64, a->vn, 0, MO_64);
 +    if (src1_mop >= 0) {
 +        read_neon_element64(rn0_64, a->vn, 0, src1_mop);
      } else {
          TCGv_i32 tmp = tcg_temp_new_i32();
          read_neon_element32(tmp, a->vn, 0, MO_32);
          widenfn(rn0_64, tmp);
          tcg_temp_free_i32(tmp);
      }
 -    rm = tcg_temp_new_i32();
 -    read_neon_element32(rm, a->vm, 0, MO_32);
 +    if (src2_mop >= 0) {
 +        read_neon_element64(rm_64, a->vm, 0, src2_mop);
 +    } else {
 +        TCGv_i32 tmp = tcg_temp_new_i32();
 +        read_neon_element32(tmp, a->vm, 0, MO_32);
 +        widenfn(rm_64, tmp);
 +        tcg_temp_free_i32(tmp);
 +    }
 -    widenfn(rm_64, rm);
 -    tcg_temp_free_i32(rm);
      opfn(rn0_64, rn0_64, rm_64);
      /*
-      * Load second pass inputs before storing the first pass result, to
-      * avoid incorrect results if a narrow input overlaps with the result.
-      */
--    if (src1_wide) {
--        read_neon_element64(rn1_64, a->vn, 1, MO_64);
-+    if (src1_mop >= 0) {
-+        read_neon_element64(rn1_64, a->vn, 1, src1_mop);
-     } else {
-         TCGv_i32 tmp = tcg_temp_new_i32();
-         read_neon_element32(tmp, a->vn, 1, MO_32);
-         widenfn(rn1_64, tmp);
-         tcg_temp_free_i32(tmp);
-     }
--    rm = tcg_temp_new_i32();
--    read_neon_element32(rm, a->vm, 1, MO_32);
-+    if (src2_mop >= 0) {
-+        read_neon_element64(rm_64, a->vm, 1, src2_mop);
-+    } else {
-+        TCGv_i32 tmp = tcg_temp_new_i32();
-+        read_neon_element32(tmp, a->vm, 1, MO_32);
-+        widenfn(rm_64, tmp);
-+        tcg_temp_free_i32(tmp);
-+    }
-     write_neon_element64(rn0_64, a->vd, 0, MO_64);
--    widenfn(rm_64, rm);
--    tcg_temp_free_i32(rm);
-     opfn(rn1_64, rn1_64, rm_64);
-     write_neon_element64(rn1_64, a->vd, 1, MO_64);
-@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
-     return true;
- }
--#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE)                         \
-+#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN)                        \
-     static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a)        \
-     {                                                                   \
-         static NeonGenWidenFn * const widenfn[] = {                     \
-             gen_helper_neon_widen_##S##8,                               \
-             gen_helper_neon_widen_##S##16,                              \
--            tcg_gen_##EXT##_i32_i64,                                    \
--            NULL,                                                       \
-+            NULL, NULL,                                                 \
-         };                                                              \
-         static NeonGenTwo64OpFn * const addfn[] = {                     \
-             gen_helper_neon_##OP##l_u16,                                \
-@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
-             tcg_gen_##OP##_i64,                                         \
-             NULL,                                                       \
-         };                                                              \
--        return do_prewiden_3d(s, a, widenfn[a->size],                   \
--                              addfn[a->size], SRC1WIDE);                \
-+        int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1;          \
-+        return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size],   \
-+                              SRC1WIDE ? MO_Q : narrow_mop,             \
-+                              narrow_mop);                              \
-     }
--DO_PREWIDEN(VADDL_S, s, ext, add, false)
--DO_PREWIDEN(VADDL_U, u, extu, add, false)
--DO_PREWIDEN(VSUBL_S, s, ext, sub, false)
--DO_PREWIDEN(VSUBL_U, u, extu, sub, false)
--DO_PREWIDEN(VADDW_S, s, ext, add, true)
--DO_PREWIDEN(VADDW_U, u, extu, add, true)
--DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
--DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
-+DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN)
-+DO_PREWIDEN(VADDL_U, u, add, false, 0)
-+DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN)
-+DO_PREWIDEN(VSUBL_U, u, sub, false, 0)
-+DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN)
-+DO_PREWIDEN(VADDW_U, u, add, true, 0)
-+DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN)
-+DO_PREWIDEN(VSUBW_U, u, sub, true, 0)
- static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
-                          NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
 --
-.20.1
+.25.1

-[PULL 12/26] target/arm: Fix float16 pairwise Neon ops on big-endian hosts
+Deleted patch
-In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error
-meant we were using the H4() address swizzler macro rather than the
-H2() which is required for 2-byte data.  This had no effect on
-little-endian hosts but meant we put the result data into the
-destination Dreg in the wrong order on big-endian hosts.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20201028191712.4910-2-peter.maydell@linaro.org
----
- target/arm/vec_helper.c | 8 ++++----
-file changed, 4 insertions(+), 4 deletions(-)
-diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/vec_helper.c
-+++ b/target/arm/vec_helper.c
-@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)
-         r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst);                    \
-         r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst);                    \
-                                                                         \
--        d[H4(0)] = r0;                                                  \
--        d[H4(1)] = r1;                                                  \
--        d[H4(2)] = r2;                                                  \
--        d[H4(3)] = r3;                                                  \
-+        d[H2(0)] = r0;                                                  \
-+        d[H2(1)] = r1;                                                  \
-+        d[H2(2)] = r2;                                                  \
-+        d[H2(3)] = r3;                                                  \
-     }
- DO_NEON_PAIRWISE(neon_padd, add)
---
-.20.1

-[PULL 13/26] target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
+Deleted patch
-The helper functions for performing the udot/sdot operations against
-a scalar were not using an address-swizzling macro when converting
-the index of the scalar element into a pointer into the vm array.
-This had no effect on little-endian hosts but meant we generated
-incorrect results on big-endian hosts.
-For these insns, the index is indexing over group of 4 8-bit values,
-so 32 bits per indexed entity, and H4() is therefore what we want.
-(For Neon the only possible input indexes are 0 and 1.)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20201028191712.4910-3-peter.maydell@linaro.org
----
- target/arm/vec_helper.c | 4 ++--
-file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/vec_helper.c
-+++ b/target/arm/vec_helper.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
-     intptr_t index = simd_data(desc);
-     uint32_t *d = vd;
-     int8_t *n = vn;
--    int8_t *m_indexed = (int8_t *)vm + index * 4;
-+    int8_t *m_indexed = (int8_t *)vm + H4(index) * 4;
-     /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
-      * Otherwise opr_sz is a multiple of 16.
-@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
-     intptr_t index = simd_data(desc);
-     uint32_t *d = vd;
-     uint8_t *n = vn;
--    uint8_t *m_indexed = (uint8_t *)vm + index * 4;
-+    uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4;
-     /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
-      * Otherwise opr_sz is a multiple of 16.
---
-.20.1

-[PULL 16/26] disas/capstone: Fix monitor disassembly of >32 bytes
+Deleted patch
-If we're using the capstone disassembler, disassembly of a run of
-instructions more than 32 bytes long disassembles the wrong data for
-instructions beyond the 32 byte mark:
-(qemu) xp /16x 0x100
-0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000
-0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000
-0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574
-0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000
-(qemu) xp /16i 0x100
-x00000100: 00000005 andeq r0, r0, r5
-x00000104: 54410001 strbpl r0, [r1], #-1
-x00000108: 00000001 andeq r0, r0, r1
-x0000010c: 00001000 andeq r1, r0, r0
-x00000110: 00000000 andeq r0, r0, r0
-x00000114: 00000004 andeq r0, r0, r4
-x00000118: 54410002 strbpl r0, [r1], #-2
-x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
-x00000120: 54410001 strbpl r0, [r1], #-1
-x00000124: 00000001 andeq r0, r0, r1
-x00000128: 00001000 andeq r1, r0, r0
-x0000012c: 00000000 andeq r0, r0, r0
-x00000130: 00000004 andeq r0, r0, r4
-x00000134: 54410002 strbpl r0, [r1], #-2
-x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
-x0000013c: 00000000 andeq r0, r0, r0
-Here the disassembly of 0x120..0x13f is using the data that is in
-x104..0x123.
-This is caused by passing the wrong value to the read_memory_func().
-The intention is that at this point in the loop the 'cap_buf' buffer
-already contains 'csize' bytes of data for the instruction at guest
-addr 'pc', and we want to read in an extra 'tsize' bytes.  Those
-extra bytes are therefore at 'pc + csize', not 'pc'.  On the first
-time through the loop 'csize' happens to be zero, so the initial read
-of 32 bytes into cap_buf is correct and as long as the disassembly
-never needs to read more data we return the correct information.
-Use the correct guest address in the call to read_memory_func().
-Cc: qemu-stable@nongnu.org
-Fixes: https://bugs.launchpad.net/qemu/+bug/1900779
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20201022132445.25039-1-peter.maydell@linaro.org
----
- disas/capstone.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/disas/capstone.c b/disas/capstone.c
-index XXXXXXX..XXXXXXX 100644
---- a/disas/capstone.c
-+++ b/disas/capstone.c
-@@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
-         /* Make certain that we can make progress.  */
-         assert(tsize != 0);
--        info->read_memory_func(pc, cap_buf + csize, tsize, info);
-+        info->read_memory_func(pc + csize, cap_buf + csize, tsize, info);
-         csize += tsize;
-         if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
---
-.20.1

-[PULL 17/26] hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
+Deleted patch
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
-Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
-This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):
-  CID 1432363 (#1 of 1): Unintentional integer overflow:
-  overflow_before_widen:
-    Potentially overflowing expression 1 << scale with type int
-    (32 bits, signed) is evaluated using 32-bit arithmetic, and
-    then used in a context that expects an expression of type
-    hwaddr (64 bits, unsigned).
-Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Acked-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 20201030144617.1535064-1-philmd@redhat.com
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/smmuv3.c | 3 ++-
-file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/smmuv3.c
-+++ b/hw/arm/smmuv3.c
-@@ -XXX,XX +XXX,XX @@
-  */
- #include "qemu/osdep.h"
-+#include "qemu/bitops.h"
- #include "hw/irq.h"
- #include "hw/sysbus.h"
- #include "migration/vmstate.h"
-@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
-         scale = CMD_SCALE(cmd);
-         num = CMD_NUM(cmd);
-         ttl = CMD_TTL(cmd);
--        num_pages = (num + 1) * (1 << (scale));
-+        num_pages = (num + 1) * BIT_ULL(scale);
-     }
-     if (type == SMMU_CMD_TLBI_NH_VA) {
---
-.20.1

-[PULL 19/26] hw/display/omap_lcdc: Fix potential NULL pointer dereference
+Deleted patch
-From: AlexChen <alex.chen@huawei.com>
-In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before
-being check if it is valid, which may lead to NULL pointer dereference.
-So move the assignment to surface after checking that the omap_lcd is valid
-and move surface_bits_per_pixel(surface) to after the surface assignment.
-Reported-by: Euler Robot <euler.robot@huawei.com>
-Signed-off-by: AlexChen <alex.chen@huawei.com>
-Message-id: 5F9CDB8A.9000001@huawei.com
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/display/omap_lcdc.c | 10 +++++++---
-file changed, 7 insertions(+), 3 deletions(-)
-diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/display/omap_lcdc.c
-+++ b/hw/display/omap_lcdc.c
-@@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
- static void omap_update_display(void *opaque)
- {
-     struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
--    DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
-+    DisplaySurface *surface;
-     draw_line_func draw_line;
-     int size, height, first, last;
-     int width, linesize, step, bpp, frame_offset;
-     hwaddr frame_base;
--    if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable ||
--        !surface_bits_per_pixel(surface)) {
-+    if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) {
-+        return;
-+    }
-+
-+    surface = qemu_console_surface(omap_lcd->con);
-+    if (!surface_bits_per_pixel(surface)) {
-         return;
-     }
---
-.20.1

-[PULL 20/26] hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
+Deleted patch
-From: AlexChen <alex.chen@huawei.com>
-In exynos4210_fimd_update(), the pointer s is dereferinced before
-being check if it is valid, which may lead to NULL pointer dereference.
-So move the assignment to global_width after checking that the s is valid.
-Reported-by: Euler Robot <euler.robot@huawei.com>
-Signed-off-by: Alex Chen <alex.chen@huawei.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 5F9F8D88.9030102@huawei.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/display/exynos4210_fimd.c | 4 +++-
-file changed, 3 insertions(+), 1 deletion(-)
-diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/display/exynos4210_fimd.c
-+++ b/hw/display/exynos4210_fimd.c
-@@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque)
-     bool blend = false;
-     uint8_t *host_fb_addr;
-     bool is_dirty = false;
--    const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
-+    int global_width;
-     if (!s || !s->console || !s->enabled ||
-         surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
-         return;
-     }
-+
-+    global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
-     exynos4210_update_resolution(s);
-     surface = qemu_console_surface(s->console);
---
-.20.1

-[PULL 22/26] configure: Test that gio libs from pkg-config work
+Deleted patch
-On some hosts (eg Ubuntu Bionic) pkg-config returns a set of
-libraries for gio-2.0 which don't actually work when compiling
-statically. (Specifically, the returned library string includes
--lmount, but not -lblkid which -lmount depends upon, so linking
-fails due to missing symbols.)
-Check that the libraries work, and don't enable gio if they don't,
-in the same way we do for gnutls.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20200928160402.7961-1-peter.maydell@linaro.org
----
- configure | 10 +++++++++-
-file changed, 9 insertions(+), 1 deletion(-)
-diff --git a/configure b/configure
-index XXXXXXX..XXXXXXX 100755
---- a/configure
-+++ b/configure
-@@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then
- fi
- if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
--    gio=yes
-     gio_cflags=$($pkg_config --cflags gio-2.0)
-     gio_libs=$($pkg_config --libs gio-2.0)
-     gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0)
-     if [ ! -x "$gdbus_codegen" ]; then
-         gdbus_codegen=
-     fi
-+    # Check that the libraries actually work -- Ubuntu 18.04 ships
-+    # with pkg-config --static --libs data for gio-2.0 that is missing
-+    # -lblkid and will give a link error.
-+    write_c_skeleton
-+    if compile_prog "" "gio_libs" ; then
-+        gio=yes
-+    else
-+        gio=no
-+    fi
- else
-     gio=no
- fi
---
-.20.1

-[PULL 23/26] hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
+Deleted patch
-In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt
-into the GICv3CPUState struct's maintenance_irq field.  This will
-only work if the board happens to have already wired up the CPU
-maintenance IRQ before the GIC was realized.  Unfortunately this is
-not the case for the 'virt' board, and so the value that gets copied
-is NULL (since a qemu_irq is really a pointer to an IRQState struct
-under the hood).  The effect is that the CPU interface code never
-actually raises the maintenance interrupt line.
-Instead, since the GICv3CPUState has a pointer to the CPUState, make
-the dereference at the point where we want to raise the interrupt, to
-avoid an implicit requirement on board code to wire things up in a
-particular order.
-Reported-by: Jose Martins <josemartins90@gmail.com>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20201009153904.28529-1-peter.maydell@linaro.org
-Reviewed-by: Luc Michel <luc@lmichel.fr>
----
- include/hw/intc/arm_gicv3_common.h | 1 -
- hw/intc/arm_gicv3_cpuif.c          | 5 ++---
-files changed, 2 insertions(+), 4 deletions(-)
-diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/intc/arm_gicv3_common.h
-+++ b/include/hw/intc/arm_gicv3_common.h
-@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
-     qemu_irq parent_fiq;
-     qemu_irq parent_virq;
-     qemu_irq parent_vfiq;
--    qemu_irq maintenance_irq;
-     /* Redistributor */
-     uint32_t level;                  /* Current IRQ level */
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
-     int irqlevel = 0;
-     int fiqlevel = 0;
-     int maintlevel = 0;
-+    ARMCPU *cpu = ARM_CPU(cs->cpu);
-     idx = hppvi_index(cs);
-     trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx);
-@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
-     qemu_set_irq(cs->parent_vfiq, fiqlevel);
-     qemu_set_irq(cs->parent_virq, irqlevel);
--    qemu_set_irq(cs->maintenance_irq, maintlevel);
-+    qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel);
- }
- static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
-@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
-             && cpu->gic_num_lrs) {
-             int j;
--            cs->maintenance_irq = cpu->gicv3_maintenance_interrupt;
--
-             cs->num_list_regs = cpu->gic_num_lrs;
-             cs->vpribits = cpu->gic_vpribits;
-             cs->vprebits = cpu->gic_vprebits;
---
-.20.1

-[PULL 24/26] scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
+Deleted patch
-The kerneldoc script currently emits Sphinx markup for a macro with
-arguments that uses the c:function directive. This is correct for
-Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow
-documentation of macros with arguments and c:function is not picky
-about the syntax of what it is passed. However, in Sphinx 3 the
-c:macro directive was enhanced to support macros with arguments,
-and c:function was made more picky about what syntax it accepted.
-When kerneldoc is told that it needs to produce output for Sphinx
-or later, make it emit c:function only for functions and c:macro
-for macros with arguments. We assume that anything with a return
-type is a function and anything without is a macro.
-This fixes the Sphinx error:
-/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator
-If declarator-id with parameters (e.g., 'void f(int arg)'):
-  Invalid C declaration: Expected identifier in nested name. [error at 25]
-    DECLARE_INSTANCE_CHECKER ( InstanceType,  OBJ_NAME,  TYPENAME)
-    -------------------------^
-If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'):
-  Error in declarator or parameters
-  Invalid C declaration: Expecting "(" in parameters. [error at 39]
-    DECLARE_INSTANCE_CHECKER ( InstanceType,  OBJ_NAME,  TYPENAME)
-    ---------------------------------------^
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
-Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
-Message-id: 20201030174700.7204-2-peter.maydell@linaro.org
----
- scripts/kernel-doc | 18 +++++++++++++++++-
-file changed, 17 insertions(+), 1 deletion(-)
-diff --git a/scripts/kernel-doc b/scripts/kernel-doc
-index XXXXXXX..XXXXXXX 100755
---- a/scripts/kernel-doc
-+++ b/scripts/kernel-doc
-@@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) {
-     output_highlight_rst($args{'purpose'});
-     $start = "\n\n**Syntax**\n\n  ``";
-     } else {
--    print ".. c:function:: ";
-+        if ((split(/\./, $sphinx_version))[0] >= 3) {
-+            # Sphinx 3 and later distinguish macros and functions and
-+            # complain if you use c:function with something that's not
-+            # syntactically valid as a function declaration.
-+            # We assume that anything with a return type is a function
-+            # and anything without is a macro.
-+            if ($args{'functiontype'} ne "") {
-+                print ".. c:function:: ";
-+            } else {
-+                print ".. c:macro:: ";
-+            }
-+        } else {
-+            # Older Sphinx don't support documenting macros that take
-+            # arguments with c:macro, and don't complain about the use
-+            # of c:function for this.
-+            print ".. c:function:: ";
-+        }
-     }
-     if ($args{'functiontype'} ne "") {
-     $start .= $args{'functiontype'} . " " . $args{'function'} . " (";
---
-.20.1

-[PULL 25/26] qemu-option-trace.rst.inc: Don't use option:: markup
+Deleted patch
-Sphinx 3.2 is pickier than earlier versions about the option:: markup,
-and complains about our usage in qemu-option-trace.rst:
-../../docs/qemu-option-trace.rst.inc:4:Malformed option description
-  '[enable=]PATTERN', should look like "opt", "-opt args", "--opt args",
-  "/opt args" or "+opt args"
-In this file, we're really trying to document the different parts of
-the top-level --trace option, which qemu-nbd.rst and qemu-img.rst
-have already introduced with an option:: markup.  So it's not right
-to use option:: here anyway.  Switch to a different markup
-(definition lists) which gives about the same formatted output.
-(Unlike option::, this markup doesn't produce index entries; but
-at the moment we don't do anything much with indexes anyway, and
-in any case I think it doesn't make much sense to have individual
-index entries for the sub-parts of the --trace option.)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
-Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
-Message-id: 20201030174700.7204-3-peter.maydell@linaro.org
----
- docs/qemu-option-trace.rst.inc | 6 +++---
-file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc
-index XXXXXXX..XXXXXXX 100644
---- a/docs/qemu-option-trace.rst.inc
-+++ b/docs/qemu-option-trace.rst.inc
-@@ -XXX,XX +XXX,XX @@
- Specify tracing options.
--.. option:: [enable=]PATTERN
-+``[enable=]PATTERN``
-   Immediately enable events matching *PATTERN*
-   (either event name or a globbing pattern).  This option is only
-@@ -XXX,XX +XXX,XX @@ Specify tracing options.
-   Use :option:`-trace help` to print a list of names of trace points.
--.. option:: events=FILE
-+``events=FILE``
-   Immediately enable events listed in *FILE*.
-   The file must contain one event name (as listed in the ``trace-events-all``
-@@ -XXX,XX +XXX,XX @@ Specify tracing options.
-   available if QEMU has been compiled with the ``simple``, ``log`` or
-   ``ftrace`` tracing backend.
--.. option:: file=FILE
-+``file=FILE``
-   Log output traces to *FILE*.
-   This option is only available if QEMU has been compiled with
---
-.20.1

-[PULL 26/26] tests/qtest/npcm7xx_rng-test: Disable randomness tests
+Deleted patch
-The randomness tests in the NPCM7xx RNG test fail intermittently
-but fairly frequently. On my machine running the test in a loop:
- while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done
-will fail in less than a minute with an error like:
-ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs:
-assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01)
-(Failures have been observed on all 4 of the randomness tests,
-not just first_byte_runs.)
-It's not clear why these tests are failing like this, but intermittent
-failures make CI and merge testing awkward, so disable running them
-unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when
-running the test suite, until we work out the cause.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20201102152454.8287-1-peter.maydell@linaro.org
-Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
----
- tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++----
-file changed, 10 insertions(+), 4 deletions(-)
-diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
-index XXXXXXX..XXXXXXX 100644
---- a/tests/qtest/npcm7xx_rng-test.c
-+++ b/tests/qtest/npcm7xx_rng-test.c
-@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
-     qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);
-     qtest_add_func("npcm7xx_rng/rosel", test_rosel);
--    qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
--    qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
--    qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
--    qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
-+    /*
-+     * These tests fail intermittently; only run them on explicit
-+     * request until we figure out why.
-+     */
-+    if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) {
-+        qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
-+        qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
-+        qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
-+        qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
-+    }
-     qtest_start("-machine npcm750-evb");
-     ret = g_test_run();
---
-.20.1

Small pile of bug fixes for rc1. I've included my patches to get
our docs building with Sphinx 3, just for convenience...

-- PMM

The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96:

Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102

for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a:

tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000)

----------------------------------------------------------------
target-arm queue:
 * target/arm: Fix Neon emulation bugs on big-endian hosts
 * target/arm: fix handling of HCR.FB
 * target/arm: fix LORID_EL1 access check
 * disas/capstone: Fix monitor disassembly of >32 bytes
 * hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)
 * hw/arm/boot: fix SVE for EL3 direct kernel boot
 * hw/display/omap_lcdc: Fix potential NULL pointer dereference
 * hw/display/exynos4210_fimd: Fix potential NULL pointer dereference
 * target/arm: Get correct MMU index for other-security-state
 * configure: Test that gio libs from pkg-config work
 * hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
 * docs: Fix building with Sphinx 3
 * tests/qtest/npcm7xx_rng-test: Disable randomness tests

----------------------------------------------------------------
AlexChen (2):
      hw/display/omap_lcdc: Fix potential NULL pointer dereference
      hw/display/exynos4210_fimd: Fix potential NULL pointer dereference

Peter Maydell (9):
      target/arm: Fix float16 pairwise Neon ops on big-endian hosts
      target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts
      disas/capstone: Fix monitor disassembly of >32 bytes
      target/arm: Get correct MMU index for other-security-state
      configure: Test that gio libs from pkg-config work
      hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work
      scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments
      qemu-option-trace.rst.inc: Don't use option:: markup
      tests/qtest/npcm7xx_rng-test: Disable randomness tests

Philippe Mathieu-Daudé (1):
      hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)

Richard Henderson (11):
      target/arm: Introduce neon_full_reg_offset
      target/arm: Move neon_element_offset to translate.c
      target/arm: Use neon_element_offset in neon_load/store_reg
      target/arm: Use neon_element_offset in vfp_reg_offset
      target/arm: Add read/write_neon_element32
      target/arm: Expand read/write_neon_element32 to all MemOp
      target/arm: Rename neon_load_reg32 to vfp_load_reg32
      target/arm: Add read/write_neon_element64
      target/arm: Rename neon_load_reg64 to vfp_load_reg64
      target/arm: Simplify do_long_3d and do_2scalar_long
      target/arm: Improve do_prewiden_3d

Rémi Denis-Courmont (3):
      target/arm: fix handling of HCR.FB
      target/arm: fix LORID_EL1 access check
      hw/arm/boot: fix SVE for EL3 direct kernel boot

From: Richard Henderson <richard.henderson@linaro.org>

This function makes it clear that we're talking about the whole
register, and not the 32-bit piece at index 0.  This fixes a bug
when running on a big-endian host.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c          |  8 ++++++
 target/arm/translate-neon.c.inc | 44 ++++++++++++++++-----------------
 target/arm/translate-vfp.c.inc  |  2 +-
 3 files changed, 31 insertions(+), 23 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
     unallocated_encoding(s);
 }
 
+/*
+ * Return the offset of a "full" NEON Dreg.
+ */
+static long neon_full_reg_offset(unsigned reg)
+{
+    return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
+}
+
 static inline long vfp_reg_offset(bool dp, unsigned reg)
 {
     if (dp) {
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size)
         ofs ^= 8 - element_size;
     }
 #endif
-    return neon_reg_offset(reg, 0) + ofs;
+    return neon_full_reg_offset(reg) + ofs;
 }
 
 static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
              * We cannot write 16 bytes at once because the
              * destination is unaligned.
              */
-            tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
+            tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
                                  8, 8, tmp);
-            tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
-                             neon_reg_offset(vd, 0), 8, 8);
+            tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1),
+                             neon_full_reg_offset(vd), 8, 8);
         } else {
-            tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
+            tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),
                                  vec_size, vec_size, tmp);
         }
         tcg_gen_addi_i32(addr, addr, 1 << size);
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
 static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
 {
     int vec_size = a->q ? 16 : 8;
-    int rd_ofs = neon_reg_offset(a->vd, 0);
-    int rn_ofs = neon_reg_offset(a->vn, 0);
-    int rm_ofs = neon_reg_offset(a->vm, 0);
+    int rd_ofs = neon_full_reg_offset(a->vd);
+    int rn_ofs = neon_full_reg_offset(a->vn);
+    int rm_ofs = neon_full_reg_offset(a->vm);
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
 {
     /* Handle a 2-reg-shift insn which can be vectorized. */
     int vec_size = a->q ? 16 : 8;
-    int rd_ofs = neon_reg_offset(a->vd, 0);
-    int rm_ofs = neon_reg_offset(a->vm, 0);
+    int rd_ofs = neon_full_reg_offset(a->vd);
+    int rm_ofs = neon_full_reg_offset(a->vm);
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
 {
     /* FP operations in 2-reg-and-shift group */
     int vec_size = a->q ? 16 : 8;
-    int rd_ofs = neon_reg_offset(a->vd, 0);
-    int rm_ofs = neon_reg_offset(a->vm, 0);
+    int rd_ofs = neon_full_reg_offset(a->vd);
+    int rm_ofs = neon_full_reg_offset(a->vm);
     TCGv_ptr fpst;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
         return true;
     }
 
-    reg_ofs = neon_reg_offset(a->vd, 0);
+    reg_ofs = neon_full_reg_offset(a->vd);
     vec_size = a->q ? 16 : 8;
     imm = asimd_imm_const(a->imm, a->cmode, a->op);
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)
         return true;
     }
 
-    tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0),
-                       neon_reg_offset(a->vn, 0),
-                       neon_reg_offset(a->vm, 0),
+    tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd),
+                       neon_full_reg_offset(a->vn),
+                       neon_full_reg_offset(a->vm),
                        16, 16, 0, fn_gvec);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
 {
     /* Two registers and a scalar, using gvec */
     int vec_size = a->q ? 16 : 8;
-    int rd_ofs = neon_reg_offset(a->vd, 0);
-    int rn_ofs = neon_reg_offset(a->vn, 0);
+    int rd_ofs = neon_full_reg_offset(a->vd);
+    int rn_ofs = neon_full_reg_offset(a->vn);
     int rm_ofs;
     int idx;
     TCGv_ptr fpstatus;
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,
     /* a->vm is M:Vm, which encodes both register and index */
     idx = extract32(a->vm, a->size + 2, 2);
     a->vm = extract32(a->vm, 0, a->size + 2);
-    rm_ofs = neon_reg_offset(a->vm, 0);
+    rm_ofs = neon_full_reg_offset(a->vm);
 
     fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD);
     tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus,
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
         return true;
     }
 
-    tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0),
+    tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd),
                          neon_element_offset(a->vm, a->index, a->size),
                          a->q ? 16 : 8, a->q ? 16 : 8);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
 static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)
 {
     int vec_size = a->q ? 16 : 8;
-    int rd_ofs = neon_reg_offset(a->vd, 0);
-    int rm_ofs = neon_reg_offset(a->vm, 0);
+    int rd_ofs = neon_full_reg_offset(a->vd);
+    int rm_ofs = neon_full_reg_offset(a->vm);
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return false;
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
     }
 
     tmp = load_reg(s, a->rt);
-    tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),
+    tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn),
                          vec_size, vec_size, tmp);
     tcg_temp_free_i32(tmp);
 
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

This will shortly have users outside of translate-neon.c.inc.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c          | 20 ++++++++++++++++++++
 target/arm/translate-neon.c.inc | 19 -------------------
 2 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
     return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
 }
 
+/*
+ * Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
+ * where 0 is the least significant end of the register.
+ */
+static long neon_element_offset(int reg, int element, MemOp size)
+{
+    int element_size = 1 << size;
+    int ofs = element * element_size;
+#ifdef HOST_WORDS_BIGENDIAN
+    /*
+     * Calculate the offset assuming fully little-endian,
+     * then XOR to account for the order of the 8-byte units.
+     */
+    if (element_size < 8) {
+        ofs ^= 8 - element_size;
+    }
+#endif
+    return neon_full_reg_offset(reg) + ofs;
+}
+
 static inline long vfp_reg_offset(bool dp, unsigned reg)
 {
     if (dp) {
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x)
 #include "decode-neon-ls.c.inc"
 #include "decode-neon-shared.c.inc"
 
-/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
- * where 0 is the least significant end of the register.
- */
-static inline long
-neon_element_offset(int reg, int element, MemOp size)
-{
-    int element_size = 1 << size;
-    int ofs = element * element_size;
-#ifdef HOST_WORDS_BIGENDIAN
-    /* Calculate the offset assuming fully little-endian,
-     * then XOR to account for the order of the 8-byte units.
-     */
-    if (element_size < 8) {
-        ofs ^= 8 - element_size;
-    }
-#endif
-    return neon_full_reg_offset(reg) + ofs;
-}
-
 static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)
 {
     long offset = neon_element_offset(reg, ele, mop & MO_SIZE);
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

These are the only users of neon_reg_offset, so remove that.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg)
     }
 }
 
-/* Return the offset of a 32-bit piece of a NEON register.
-   zero is the least significant end of the register.  */
-static inline long
-neon_reg_offset (int reg, int n)
-{
-    int sreg;
-    sreg = reg * 2 + n;
-    return vfp_reg_offset(0, sreg);
-}
-
 static TCGv_i32 neon_load_reg(int reg, int pass)
 {
     TCGv_i32 tmp = tcg_temp_new_i32();
-    tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
+    tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
     return tmp;
 }
 
 static void neon_store_reg(int reg, int pass, TCGv_i32 var)
 {
-    tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
+    tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
     tcg_temp_free_i32(var);
 }
 
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

This seems a bit more readable than using offsetof CPU_DoubleU.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size)
     return neon_full_reg_offset(reg) + ofs;
 }
 
-static inline long vfp_reg_offset(bool dp, unsigned reg)
+/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */
+static long vfp_reg_offset(bool dp, unsigned reg)
 {
     if (dp) {
-        return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);
+        return neon_element_offset(reg, 0, MO_64);
     } else {
-        long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]);
-        if (reg & 1) {
-            ofs += offsetof(CPU_DoubleU, l.upper);
-        } else {
-            ofs += offsetof(CPU_DoubleU, l.lower);
-        }
-        return ofs;
+        return neon_element_offset(reg >> 1, reg & 1, MO_32);
     }
 }
 
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Model these off the aa64 read/write_vec_element functions.
Use it within translate-neon.c.inc.  The new functions do
not allocate or free temps, so this rearranges the calling
code a bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c          |  26 ++++
 target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------
 2 files changed, 183 insertions(+), 99 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
     tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
 }
 
+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
+{
+    long off = neon_element_offset(reg, ele, size);
+
+    switch (size) {
+    case MO_32:
+        tcg_gen_ld_i32(dest, cpu_env, off);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
+{
+    long off = neon_element_offset(reg, ele, size);
+
+    switch (size) {
+    case MO_32:
+        tcg_gen_st_i32(src, cpu_env, off);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
 {
     TCGv_ptr ret = tcg_temp_new_ptr();
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
      * early. Since Q is 0 there are always just two passes, so instead
      * of a complicated loop over each pass we just unroll.
      */
-    tmp = neon_load_reg(a->vn, 0);
-    tmp2 = neon_load_reg(a->vn, 1);
+    tmp = tcg_temp_new_i32();
+    tmp2 = tcg_temp_new_i32();
+    tmp3 = tcg_temp_new_i32();
+
+    read_neon_element32(tmp, a->vn, 0, MO_32);
+    read_neon_element32(tmp2, a->vn, 1, MO_32);
     fn(tmp, tmp, tmp2);
-    tcg_temp_free_i32(tmp2);
 
-    tmp3 = neon_load_reg(a->vm, 0);
-    tmp2 = neon_load_reg(a->vm, 1);
+    read_neon_element32(tmp3, a->vm, 0, MO_32);
+    read_neon_element32(tmp2, a->vm, 1, MO_32);
     fn(tmp3, tmp3, tmp2);
-    tcg_temp_free_i32(tmp2);
 
-    neon_store_reg(a->vd, 0, tmp);
-    neon_store_reg(a->vd, 1, tmp3);
+    write_neon_element32(tmp, a->vd, 0, MO_32);
+    write_neon_element32(tmp3, a->vd, 1, MO_32);
+
+    tcg_temp_free_i32(tmp);
+    tcg_temp_free_i32(tmp2);
+    tcg_temp_free_i32(tmp3);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
      * 2-reg-and-shift operations, size < 3 case, where the
      * helper needs to be passed cpu_env.
      */
-    TCGv_i32 constimm;
+    TCGv_i32 constimm, tmp;
     int pass;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a,
      * by immediate using the variable shift operations.
      */
     constimm = tcg_const_i32(dup_const(a->size, a->shift));
+    tmp = tcg_temp_new_i32();
 
     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+        read_neon_element32(tmp, a->vm, pass, MO_32);
         fn(tmp, cpu_env, tmp, constimm);
-        neon_store_reg(a->vd, pass, tmp);
+        write_neon_element32(tmp, a->vd, pass, MO_32);
     }
+    tcg_temp_free_i32(tmp);
     tcg_temp_free_i32(constimm);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
     constimm = tcg_const_i64(-a->shift);
     rm1 = tcg_temp_new_i64();
     rm2 = tcg_temp_new_i64();
+    rd = tcg_temp_new_i32();
 
     /* Load both inputs first to avoid potential overwrite if rm == rd */
     neon_load_reg64(rm1, a->vm);
     neon_load_reg64(rm2, a->vm + 1);
 
     shiftfn(rm1, rm1, constimm);
-    rd = tcg_temp_new_i32();
     narrowfn(rd, cpu_env, rm1);
-    neon_store_reg(a->vd, 0, rd);
+    write_neon_element32(rd, a->vd, 0, MO_32);
 
     shiftfn(rm2, rm2, constimm);
-    rd = tcg_temp_new_i32();
     narrowfn(rd, cpu_env, rm2);
-    neon_store_reg(a->vd, 1, rd);
+    write_neon_element32(rd, a->vd, 1, MO_32);
 
+    tcg_temp_free_i32(rd);
     tcg_temp_free_i64(rm1);
     tcg_temp_free_i64(rm2);
     tcg_temp_free_i64(constimm);
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
     constimm = tcg_const_i32(imm);
 
     /* Load all inputs first to avoid potential overwrite */
-    rm1 = neon_load_reg(a->vm, 0);
-    rm2 = neon_load_reg(a->vm, 1);
-    rm3 = neon_load_reg(a->vm + 1, 0);
-    rm4 = neon_load_reg(a->vm + 1, 1);
+    rm1 = tcg_temp_new_i32();
+    rm2 = tcg_temp_new_i32();
+    rm3 = tcg_temp_new_i32();
+    rm4 = tcg_temp_new_i32();
+    read_neon_element32(rm1, a->vm, 0, MO_32);
+    read_neon_element32(rm2, a->vm, 1, MO_32);
+    read_neon_element32(rm3, a->vm, 2, MO_32);
+    read_neon_element32(rm4, a->vm, 3, MO_32);
     rtmp = tcg_temp_new_i64();
 
     shiftfn(rm1, rm1, constimm);
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
     tcg_temp_free_i32(rm2);
 
     narrowfn(rm1, cpu_env, rtmp);
-    neon_store_reg(a->vd, 0, rm1);
+    write_neon_element32(rm1, a->vd, 0, MO_32);
+    tcg_temp_free_i32(rm1);
 
     shiftfn(rm3, rm3, constimm);
     shiftfn(rm4, rm4, constimm);
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a,
 
     narrowfn(rm3, cpu_env, rtmp);
     tcg_temp_free_i64(rtmp);
-    neon_store_reg(a->vd, 1, rm3);
+    write_neon_element32(rm3, a->vd, 1, MO_32);
+    tcg_temp_free_i32(rm3);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
         widen_mask = dup_const(a->size + 1, widen_mask);
     }
 
-    rm0 = neon_load_reg(a->vm, 0);
-    rm1 = neon_load_reg(a->vm, 1);
+    rm0 = tcg_temp_new_i32();
+    rm1 = tcg_temp_new_i32();
+    read_neon_element32(rm0, a->vm, 0, MO_32);
+    read_neon_element32(rm1, a->vm, 1, MO_32);
     tmp = tcg_temp_new_i64();
 
     widenfn(tmp, rm0);
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
     if (src1_wide) {
         neon_load_reg64(rn0_64, a->vn);
     } else {
-        TCGv_i32 tmp = neon_load_reg(a->vn, 0);
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        read_neon_element32(tmp, a->vn, 0, MO_32);
         widenfn(rn0_64, tmp);
         tcg_temp_free_i32(tmp);
     }
-    rm = neon_load_reg(a->vm, 0);
+    rm = tcg_temp_new_i32();
+    read_neon_element32(rm, a->vm, 0, MO_32);
 
     widenfn(rm_64, rm);
     tcg_temp_free_i32(rm);
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
     if (src1_wide) {
         neon_load_reg64(rn1_64, a->vn + 1);
     } else {
-        TCGv_i32 tmp = neon_load_reg(a->vn, 1);
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        read_neon_element32(tmp, a->vn, 1, MO_32);
         widenfn(rn1_64, tmp);
         tcg_temp_free_i32(tmp);
     }
-    rm = neon_load_reg(a->vm, 1);
+    rm = tcg_temp_new_i32();
+    read_neon_element32(rm, a->vm, 1, MO_32);
 
     neon_store_reg64(rn0_64, a->vd);
 
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
 
     narrowfn(rd1, rn_64);
 
-    neon_store_reg(a->vd, 0, rd0);
-    neon_store_reg(a->vd, 1, rd1);
+    write_neon_element32(rd0, a->vd, 0, MO_32);
+    write_neon_element32(rd1, a->vd, 1, MO_32);
 
+    tcg_temp_free_i32(rd0);
+    tcg_temp_free_i32(rd1);
     tcg_temp_free_i64(rn_64);
     tcg_temp_free_i64(rm_64);
 
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
     rd0 = tcg_temp_new_i64();
     rd1 = tcg_temp_new_i64();
 
-    rn = neon_load_reg(a->vn, 0);
-    rm = neon_load_reg(a->vm, 0);
+    rn = tcg_temp_new_i32();
+    rm = tcg_temp_new_i32();
+    read_neon_element32(rn, a->vn, 0, MO_32);
+    read_neon_element32(rm, a->vm, 0, MO_32);
     opfn(rd0, rn, rm);
-    tcg_temp_free_i32(rn);
-    tcg_temp_free_i32(rm);
 
-    rn = neon_load_reg(a->vn, 1);
-    rm = neon_load_reg(a->vm, 1);
+    read_neon_element32(rn, a->vn, 1, MO_32);
+    read_neon_element32(rm, a->vm, 1, MO_32);
     opfn(rd1, rn, rm);
     tcg_temp_free_i32(rn);
     tcg_temp_free_i32(rm);
@@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var)
 
 static inline TCGv_i32 neon_get_scalar(int size, int reg)
 {
-    TCGv_i32 tmp;
-    if (size == 1) {
-        tmp = neon_load_reg(reg & 7, reg >> 4);
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    if (size == MO_16) {
+        read_neon_element32(tmp, reg & 7, reg >> 4, MO_32);
         if (reg & 8) {
             gen_neon_dup_high16(tmp);
         } else {
             gen_neon_dup_low16(tmp);
         }
     } else {
-        tmp = neon_load_reg(reg & 15, reg >> 4);
+        read_neon_element32(tmp, reg & 15, reg >> 4, MO_32);
     }
     return tmp;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
      * perform an accumulation operation of that result into the
      * destination.
      */
-    TCGv_i32 scalar;
+    TCGv_i32 scalar, tmp;
     int pass;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a,
     }
 
     scalar = neon_get_scalar(a->size, a->vm);
+    tmp = tcg_temp_new_i32();
 
     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-        TCGv_i32 tmp = neon_load_reg(a->vn, pass);
+        read_neon_element32(tmp, a->vn, pass, MO_32);
         opfn(tmp, tmp, scalar);
         if (accfn) {
-            TCGv_i32 rd = neon_load_reg(a->vd, pass);
+            TCGv_i32 rd = tcg_temp_new_i32();
+            read_neon_element32(rd, a->vd, pass, MO_32);
             accfn(tmp, rd, tmp);
             tcg_temp_free_i32(rd);
         }
-        neon_store_reg(a->vd, pass, tmp);
+        write_neon_element32(tmp, a->vd, pass, MO_32);
     }
+    tcg_temp_free_i32(tmp);
     tcg_temp_free_i32(scalar);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
      * performs a kind of fused op-then-accumulate using a helper
      * function that takes all of rd, rn and the scalar at once.
      */
-    TCGv_i32 scalar;
+    TCGv_i32 scalar, rn, rd;
     int pass;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a,
     }
 
     scalar = neon_get_scalar(a->size, a->vm);
+    rn = tcg_temp_new_i32();
+    rd = tcg_temp_new_i32();
 
     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-        TCGv_i32 rn = neon_load_reg(a->vn, pass);
-        TCGv_i32 rd = neon_load_reg(a->vd, pass);
+        read_neon_element32(rn, a->vn, pass, MO_32);
+        read_neon_element32(rd, a->vd, pass, MO_32);
         opfn(rd, cpu_env, rn, scalar, rd);
-        tcg_temp_free_i32(rn);
-        neon_store_reg(a->vd, pass, rd);
+        write_neon_element32(rd, a->vd, pass, MO_32);
     }
+    tcg_temp_free_i32(rn);
+    tcg_temp_free_i32(rd);
     tcg_temp_free_i32(scalar);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
     scalar = neon_get_scalar(a->size, a->vm);
 
     /* Load all inputs before writing any outputs, in case of overlap */
-    rn = neon_load_reg(a->vn, 0);
+    rn = tcg_temp_new_i32();
+    read_neon_element32(rn, a->vn, 0, MO_32);
     rn0_64 = tcg_temp_new_i64();
     opfn(rn0_64, rn, scalar);
-    tcg_temp_free_i32(rn);
 
-    rn = neon_load_reg(a->vn, 1);
+    read_neon_element32(rn, a->vn, 1, MO_32);
     rn1_64 = tcg_temp_new_i64();
     opfn(rn1_64, rn, scalar);
     tcg_temp_free_i32(rn);
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
         return false;
     }
     n <<= 3;
+    tmp = tcg_temp_new_i32();
     if (a->op) {
-        tmp = neon_load_reg(a->vd, 0);
+        read_neon_element32(tmp, a->vd, 0, MO_32);
     } else {
-        tmp = tcg_temp_new_i32();
         tcg_gen_movi_i32(tmp, 0);
     }
-    tmp2 = neon_load_reg(a->vm, 0);
+    tmp2 = tcg_temp_new_i32();
+    read_neon_element32(tmp2, a->vm, 0, MO_32);
     ptr1 = vfp_reg_ptr(true, a->vn);
     tmp4 = tcg_const_i32(n);
     gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
-    tcg_temp_free_i32(tmp);
+
     if (a->op) {
-        tmp = neon_load_reg(a->vd, 1);
+        read_neon_element32(tmp, a->vd, 1, MO_32);
     } else {
-        tmp = tcg_temp_new_i32();
         tcg_gen_movi_i32(tmp, 0);
     }
-    tmp3 = neon_load_reg(a->vm, 1);
+    tmp3 = tcg_temp_new_i32();
+    read_neon_element32(tmp3, a->vm, 1, MO_32);
     gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
+    tcg_temp_free_i32(tmp);
     tcg_temp_free_i32(tmp4);
     tcg_temp_free_ptr(ptr1);
-    neon_store_reg(a->vd, 0, tmp2);
-    neon_store_reg(a->vd, 1, tmp3);
-    tcg_temp_free_i32(tmp);
+
+    write_neon_element32(tmp2, a->vd, 0, MO_32);
+    write_neon_element32(tmp3, a->vd, 1, MO_32);
+    tcg_temp_free_i32(tmp2);
+    tcg_temp_free_i32(tmp3);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)
 static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
 {
     int pass, half;
+    TCGv_i32 tmp[2];
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
         return true;
     }
 
-    for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
-        TCGv_i32 tmp[2];
+    tmp[0] = tcg_temp_new_i32();
+    tmp[1] = tcg_temp_new_i32();
 
+    for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
         for (half = 0; half < 2; half++) {
-            tmp[half] = neon_load_reg(a->vm, pass * 2 + half);
+            read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32);
             switch (a->size) {
             case 0:
                 tcg_gen_bswap32_i32(tmp[half], tmp[half]);
@@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
                 g_assert_not_reached();
             }
         }
-        neon_store_reg(a->vd, pass * 2, tmp[1]);
-        neon_store_reg(a->vd, pass * 2 + 1, tmp[0]);
+        write_neon_element32(tmp[1], a->vd, pass * 2, MO_32);
+        write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32);
     }
+
+    tcg_temp_free_i32(tmp[0]);
+    tcg_temp_free_i32(tmp[1]);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
         rm0_64 = tcg_temp_new_i64();
         rm1_64 = tcg_temp_new_i64();
         rd_64 = tcg_temp_new_i64();
-        tmp = neon_load_reg(a->vm, pass * 2);
+
+        tmp = tcg_temp_new_i32();
+        read_neon_element32(tmp, a->vm, pass * 2, MO_32);
         widenfn(rm0_64, tmp);
-        tcg_temp_free_i32(tmp);
-        tmp = neon_load_reg(a->vm, pass * 2 + 1);
+        read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32);
         widenfn(rm1_64, tmp);
         tcg_temp_free_i32(tmp);
+
         opfn(rd_64, rm0_64, rm1_64);
         tcg_temp_free_i64(rm0_64);
         tcg_temp_free_i64(rm1_64);
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
     narrowfn(rd0, cpu_env, rm);
     neon_load_reg64(rm, a->vm + 1);
     narrowfn(rd1, cpu_env, rm);
-    neon_store_reg(a->vd, 0, rd0);
-    neon_store_reg(a->vd, 1, rd1);
+    write_neon_element32(rd0, a->vd, 0, MO_32);
+    write_neon_element32(rd1, a->vd, 1, MO_32);
+    tcg_temp_free_i32(rd0);
+    tcg_temp_free_i32(rd1);
     tcg_temp_free_i64(rm);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
     }
 
     rd = tcg_temp_new_i64();
+    rm0 = tcg_temp_new_i32();
+    rm1 = tcg_temp_new_i32();
 
-    rm0 = neon_load_reg(a->vm, 0);
-    rm1 = neon_load_reg(a->vm, 1);
+    read_neon_element32(rm0, a->vm, 0, MO_32);
+    read_neon_element32(rm1, a->vm, 1, MO_32);
 
     widenfn(rd, rm0);
     tcg_gen_shli_i64(rd, rd, 8 << a->size);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a)
 
     fpst = fpstatus_ptr(FPST_STD);
     ahp = get_ahp_flag();
-    tmp = neon_load_reg(a->vm, 0);
+    tmp = tcg_temp_new_i32();
+    read_neon_element32(tmp, a->vm, 0, MO_32);
     gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
-    tmp2 = neon_load_reg(a->vm, 1);
+    tmp2 = tcg_temp_new_i32();
+    read_neon_element32(tmp2, a->vm, 1, MO_32);
     gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
     tcg_gen_shli_i32(tmp2, tmp2, 16);
     tcg_gen_or_i32(tmp2, tmp2, tmp);
-    tcg_temp_free_i32(tmp);
-    tmp = neon_load_reg(a->vm, 2);
+    read_neon_element32(tmp, a->vm, 2, MO_32);
     gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
-    tmp3 = neon_load_reg(a->vm, 3);
-    neon_store_reg(a->vd, 0, tmp2);
+    tmp3 = tcg_temp_new_i32();
+    read_neon_element32(tmp3, a->vm, 3, MO_32);
+    write_neon_element32(tmp2, a->vd, 0, MO_32);
+    tcg_temp_free_i32(tmp2);
     gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
     tcg_gen_shli_i32(tmp3, tmp3, 16);
     tcg_gen_or_i32(tmp3, tmp3, tmp);
-    neon_store_reg(a->vd, 1, tmp3);
+    write_neon_element32(tmp3, a->vd, 1, MO_32);
+    tcg_temp_free_i32(tmp3);
     tcg_temp_free_i32(tmp);
     tcg_temp_free_i32(ahp);
     tcg_temp_free_ptr(fpst);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)
     fpst = fpstatus_ptr(FPST_STD);
     ahp = get_ahp_flag();
     tmp3 = tcg_temp_new_i32();
-    tmp = neon_load_reg(a->vm, 0);
-    tmp2 = neon_load_reg(a->vm, 1);
+    tmp2 = tcg_temp_new_i32();
+    tmp = tcg_temp_new_i32();
+    read_neon_element32(tmp, a->vm, 0, MO_32);
+    read_neon_element32(tmp2, a->vm, 1, MO_32);
     tcg_gen_ext16u_i32(tmp3, tmp);
     gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
-    neon_store_reg(a->vd, 0, tmp3);
+    write_neon_element32(tmp3, a->vd, 0, MO_32);
     tcg_gen_shri_i32(tmp, tmp, 16);
     gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
-    neon_store_reg(a->vd, 1, tmp);
-    tmp3 = tcg_temp_new_i32();
+    write_neon_element32(tmp, a->vd, 1, MO_32);
+    tcg_temp_free_i32(tmp);
     tcg_gen_ext16u_i32(tmp3, tmp2);
     gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
-    neon_store_reg(a->vd, 2, tmp3);
+    write_neon_element32(tmp3, a->vd, 2, MO_32);
+    tcg_temp_free_i32(tmp3);
     tcg_gen_shri_i32(tmp2, tmp2, 16);
     gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
-    neon_store_reg(a->vd, 3, tmp2);
+    write_neon_element32(tmp2, a->vd, 3, MO_32);
+    tcg_temp_free_i32(tmp2);
     tcg_temp_free_i32(ahp);
     tcg_temp_free_ptr(fpst);
 
@@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2)
 
 static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
 {
+    TCGv_i32 tmp;
     int pass;
 
     /* Handle a 2-reg-misc operation by iterating 32 bits at a time */
@@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn)
         return true;
     }
 
+    tmp = tcg_temp_new_i32();
     for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-        TCGv_i32 tmp = neon_load_reg(a->vm, pass);
+        read_neon_element32(tmp, a->vm, pass, MO_32);
         fn(tmp, tmp);
-        neon_store_reg(a->vd, pass, tmp);
+        write_neon_element32(tmp, a->vd, pass, MO_32);
     }
+    tcg_temp_free_i32(tmp);
 
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a)
         return true;
     }
 
-    if (a->size == 2) {
+    tmp = tcg_temp_new_i32();
+    tmp2 = tcg_temp_new_i32();
+    if (a->size == MO_32) {
         for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
-            tmp = neon_load_reg(a->vm, pass);
-            tmp2 = neon_load_reg(a->vd, pass + 1);
-            neon_store_reg(a->vm, pass, tmp2);
-            neon_store_reg(a->vd, pass + 1, tmp);
+            read_neon_element32(tmp, a->vm, pass, MO_32);
+            read_neon_element32(tmp2, a->vd, pass + 1, MO_32);
+            write_neon_element32(tmp2, a->vm, pass, MO_32);
+            write_neon_element32(tmp, a->vd, pass + 1, MO_32);
         }
     } else {
         for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
-            tmp = neon_load_reg(a->vm, pass);
-            tmp2 = neon_load_reg(a->vd, pass);
-            if (a->size == 0) {
+            read_neon_element32(tmp, a->vm, pass, MO_32);
+            read_neon_element32(tmp2, a->vd, pass, MO_32);
+            if (a->size == MO_8) {
                 gen_neon_trn_u8(tmp, tmp2);
             } else {
                 gen_neon_trn_u16(tmp, tmp2);
             }
-            neon_store_reg(a->vm, pass, tmp2);
-            neon_store_reg(a->vd, pass, tmp);
+            write_neon_element32(tmp2, a->vm, pass, MO_32);
+            write_neon_element32(tmp, a->vd, pass, MO_32);
         }
     }
+    tcg_temp_free_i32(tmp);
+    tcg_temp_free_i32(tmp2);
     return true;
 }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

We can then use this to improve VMOV (scalar to gp) and
VMOV (gp to scalar) so that we simply perform the memory
operation that we wanted, rather than inserting or
extracting from a 32-bit quantity.

These were the last uses of neon_load/store_reg, so remove them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c         | 50 +++++++++++++-----------
 target/arm/translate-vfp.c.inc | 71 +++++-----------------------------
 2 files changed, 37 insertions(+), 84 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg)
  * Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
  * where 0 is the least significant end of the register.
  */
-static long neon_element_offset(int reg, int element, MemOp size)
+static long neon_element_offset(int reg, int element, MemOp memop)
 {
-    int element_size = 1 << size;
+    int element_size = 1 << (memop & MO_SIZE);
     int ofs = element * element_size;
 #ifdef HOST_WORDS_BIGENDIAN
     /*
@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
     }
 }
 
-static TCGv_i32 neon_load_reg(int reg, int pass)
-{
-    TCGv_i32 tmp = tcg_temp_new_i32();
-    tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
-    return tmp;
-}
-
-static void neon_store_reg(int reg, int pass, TCGv_i32 var)
-{
-    tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
-    tcg_temp_free_i32(var);
-}
-
 static inline void neon_load_reg64(TCGv_i64 var, int reg)
 {
     tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)
     tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
 }
 
-static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
 {
-    long off = neon_element_offset(reg, ele, size);
+    long off = neon_element_offset(reg, ele, memop);
 
-    switch (size) {
-    case MO_32:
+    switch (memop) {
+    case MO_SB:
+        tcg_gen_ld8s_i32(dest, cpu_env, off);
+        break;
+    case MO_UB:
+        tcg_gen_ld8u_i32(dest, cpu_env, off);
+        break;
+    case MO_SW:
+        tcg_gen_ld16s_i32(dest, cpu_env, off);
+        break;
+    case MO_UW:
+        tcg_gen_ld16u_i32(dest, cpu_env, off);
+        break;
+    case MO_UL:
+    case MO_SL:
         tcg_gen_ld_i32(dest, cpu_env, off);
         break;
     default:
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)
     }
 }
 
-static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)
+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
 {
-    long off = neon_element_offset(reg, ele, size);
+    long off = neon_element_offset(reg, ele, memop);
 
-    switch (size) {
+    switch (memop) {
+    case MO_8:
+        tcg_gen_st8_i32(src, cpu_env, off);
+        break;
+    case MO_16:
+        tcg_gen_st16_i32(src, cpu_env, off);
+        break;
     case MO_32:
         tcg_gen_st_i32(src, cpu_env, off);
         break;
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
 {
     /* VMOV scalar to general purpose register */
     TCGv_i32 tmp;
-    int pass;
-    uint32_t offset;
 
-    /* SIZE == 2 is a VFP instruction; otherwise NEON.  */
-    if (a->size == 2
+    /* SIZE == MO_32 is a VFP instruction; otherwise NEON.  */
+    if (a->size == MO_32
         ? !dc_isar_feature(aa32_fpsp_v2, s)
         : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
         return false;
     }
 
-    offset = a->index << a->size;
-    pass = extract32(offset, 2, 1);
-    offset = extract32(offset, 0, 2) * 8;
-
     if (!vfp_access_check(s)) {
         return true;
     }
 
-    tmp = neon_load_reg(a->vn, pass);
-    switch (a->size) {
-    case 0:
-        if (offset) {
-            tcg_gen_shri_i32(tmp, tmp, offset);
-        }
-        if (a->u) {
-            gen_uxtb(tmp);
-        } else {
-            gen_sxtb(tmp);
-        }
-        break;
-    case 1:
-        if (a->u) {
-            if (offset) {
-                tcg_gen_shri_i32(tmp, tmp, 16);
-            } else {
-                gen_uxth(tmp);
-            }
-        } else {
-            if (offset) {
-                tcg_gen_sari_i32(tmp, tmp, 16);
-            } else {
-                gen_sxth(tmp);
-            }
-        }
-        break;
-    case 2:
-        break;
-    }
+    tmp = tcg_temp_new_i32();
+    read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN));
     store_reg(s, a->rt, tmp);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
 static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
 {
     /* VMOV general purpose register to scalar */
-    TCGv_i32 tmp, tmp2;
-    int pass;
-    uint32_t offset;
+    TCGv_i32 tmp;
 
-    /* SIZE == 2 is a VFP instruction; otherwise NEON.  */
-    if (a->size == 2
+    /* SIZE == MO_32 is a VFP instruction; otherwise NEON.  */
+    if (a->size == MO_32
         ? !dc_isar_feature(aa32_fpsp_v2, s)
         : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
         return false;
     }
 
-    offset = a->index << a->size;
-    pass = extract32(offset, 2, 1);
-    offset = extract32(offset, 0, 2) * 8;
-
     if (!vfp_access_check(s)) {
         return true;
     }
 
     tmp = load_reg(s, a->rt);
-    switch (a->size) {
-    case 0:
-        tmp2 = neon_load_reg(a->vn, pass);
-        tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
-        tcg_temp_free_i32(tmp2);
-        break;
-    case 1:
-        tmp2 = neon_load_reg(a->vn, pass);
-        tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
-        tcg_temp_free_i32(tmp2);
-        break;
-    case 2:
-        break;
-    }
-    neon_store_reg(a->vn, pass, tmp);
+    write_neon_element32(tmp, a->vn, a->index, a->size);
+    tcg_temp_free_i32(tmp);
 
     return true;
 }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The only uses of this function are for loading VFP
single-precision values, and nothing to do with NEON.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c         |   4 +-
 target/arm/translate-vfp.c.inc | 184 ++++++++++++++++-----------------
 2 files changed, 94 insertions(+), 94 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg)
     tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
 }
 
-static inline void neon_load_reg32(TCGv_i32 var, int reg)
+static inline void vfp_load_reg32(TCGv_i32 var, int reg)
 {
     tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg));
 }
 
-static inline void neon_store_reg32(TCGv_i32 var, int reg)
+static inline void vfp_store_reg32(TCGv_i32 var, int reg)
 {
     tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));
 }
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
         frn = tcg_temp_new_i32();
         frm = tcg_temp_new_i32();
         dest = tcg_temp_new_i32();
-        neon_load_reg32(frn, rn);
-        neon_load_reg32(frm, rm);
+        vfp_load_reg32(frn, rn);
+        vfp_load_reg32(frm, rm);
         switch (a->cc) {
         case 0: /* eq: Z */
             tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero,
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
         if (sz == 1) {
             tcg_gen_andi_i32(dest, dest, 0xffff);
         }
-        neon_store_reg32(dest, rd);
+        vfp_store_reg32(dest, rd);
         tcg_temp_free_i32(frn);
         tcg_temp_free_i32(frm);
         tcg_temp_free_i32(dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
         TCGv_i32 tcg_res;
         tcg_op = tcg_temp_new_i32();
         tcg_res = tcg_temp_new_i32();
-        neon_load_reg32(tcg_op, rm);
+        vfp_load_reg32(tcg_op, rm);
         if (sz == 1) {
             gen_helper_rinth(tcg_res, tcg_op, fpst);
         } else {
             gen_helper_rints(tcg_res, tcg_op, fpst);
         }
-        neon_store_reg32(tcg_res, rd);
+        vfp_store_reg32(tcg_res, rd);
         tcg_temp_free_i32(tcg_op);
         tcg_temp_free_i32(tcg_res);
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
             gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst);
         }
         tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res);
-        neon_store_reg32(tcg_tmp, rd);
+        vfp_store_reg32(tcg_tmp, rd);
         tcg_temp_free_i32(tcg_tmp);
         tcg_temp_free_i64(tcg_res);
         tcg_temp_free_i64(tcg_double);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
         TCGv_i32 tcg_single, tcg_res;
         tcg_single = tcg_temp_new_i32();
         tcg_res = tcg_temp_new_i32();
-        neon_load_reg32(tcg_single, rm);
+        vfp_load_reg32(tcg_single, rm);
         if (sz == 1) {
             if (is_signed) {
                 gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
                 gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
             }
         }
-        neon_store_reg32(tcg_res, rd);
+        vfp_store_reg32(tcg_res, rd);
         tcg_temp_free_i32(tcg_res);
         tcg_temp_free_i32(tcg_single);
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
     if (a->l) {
         /* VFP to general purpose register */
         tmp = tcg_temp_new_i32();
-        neon_load_reg32(tmp, a->vn);
+        vfp_load_reg32(tmp, a->vn);
         tcg_gen_andi_i32(tmp, tmp, 0xffff);
         store_reg(s, a->rt, tmp);
     } else {
         /* general purpose register to VFP */
         tmp = load_reg(s, a->rt);
         tcg_gen_andi_i32(tmp, tmp, 0xffff);
-        neon_store_reg32(tmp, a->vn);
+        vfp_store_reg32(tmp, a->vn);
         tcg_temp_free_i32(tmp);
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
     if (a->l) {
         /* VFP to general purpose register */
         tmp = tcg_temp_new_i32();
-        neon_load_reg32(tmp, a->vn);
+        vfp_load_reg32(tmp, a->vn);
         if (a->rt == 15) {
             /* Set the 4 flag bits in the CPSR.  */
             gen_set_nzcv(tmp);
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
     } else {
         /* general purpose register to VFP */
         tmp = load_reg(s, a->rt);
-        neon_store_reg32(tmp, a->vn);
+        vfp_store_reg32(tmp, a->vn);
         tcg_temp_free_i32(tmp);
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
     if (a->op) {
         /* fpreg to gpreg */
         tmp = tcg_temp_new_i32();
-        neon_load_reg32(tmp, a->vm);
+        vfp_load_reg32(tmp, a->vm);
         store_reg(s, a->rt, tmp);
         tmp = tcg_temp_new_i32();
-        neon_load_reg32(tmp, a->vm + 1);
+        vfp_load_reg32(tmp, a->vm + 1);
         store_reg(s, a->rt2, tmp);
     } else {
         /* gpreg to fpreg */
         tmp = load_reg(s, a->rt);
-        neon_store_reg32(tmp, a->vm);
+        vfp_store_reg32(tmp, a->vm);
         tcg_temp_free_i32(tmp);
         tmp = load_reg(s, a->rt2);
-        neon_store_reg32(tmp, a->vm + 1);
+        vfp_store_reg32(tmp, a->vm + 1);
         tcg_temp_free_i32(tmp);
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
     if (a->op) {
         /* fpreg to gpreg */
         tmp = tcg_temp_new_i32();
-        neon_load_reg32(tmp, a->vm * 2);
+        vfp_load_reg32(tmp, a->vm * 2);
         store_reg(s, a->rt, tmp);
         tmp = tcg_temp_new_i32();
-        neon_load_reg32(tmp, a->vm * 2 + 1);
+        vfp_load_reg32(tmp, a->vm * 2 + 1);
         store_reg(s, a->rt2, tmp);
     } else {
         /* gpreg to fpreg */
         tmp = load_reg(s, a->rt);
-        neon_store_reg32(tmp, a->vm * 2);
+        vfp_store_reg32(tmp, a->vm * 2);
         tcg_temp_free_i32(tmp);
         tmp = load_reg(s, a->rt2);
-        neon_store_reg32(tmp, a->vm * 2 + 1);
+        vfp_store_reg32(tmp, a->vm * 2 + 1);
         tcg_temp_free_i32(tmp);
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a)
     tmp = tcg_temp_new_i32();
     if (a->l) {
         gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
-        neon_store_reg32(tmp, a->vd);
+        vfp_store_reg32(tmp, a->vd);
     } else {
-        neon_load_reg32(tmp, a->vd);
+        vfp_load_reg32(tmp, a->vd);
         gen_aa32_st16(s, tmp, addr, get_mem_index(s));
     }
     tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
     tmp = tcg_temp_new_i32();
     if (a->l) {
         gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
-        neon_store_reg32(tmp, a->vd);
+        vfp_store_reg32(tmp, a->vd);
     } else {
-        neon_load_reg32(tmp, a->vd);
+        vfp_load_reg32(tmp, a->vd);
         gen_aa32_st32(s, tmp, addr, get_mem_index(s));
     }
     tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
         if (a->l) {
             /* load */
             gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
-            neon_store_reg32(tmp, a->vd + i);
+            vfp_store_reg32(tmp, a->vd + i);
         } else {
             /* store */
-            neon_load_reg32(tmp, a->vd + i);
+            vfp_load_reg32(tmp, a->vd + i);
             gen_aa32_st32(s, tmp, addr, get_mem_index(s));
         }
         tcg_gen_addi_i32(addr, addr, offset);
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
     fd = tcg_temp_new_i32();
     fpst = fpstatus_ptr(FPST_FPCR);
 
-    neon_load_reg32(f0, vn);
-    neon_load_reg32(f1, vm);
+    vfp_load_reg32(f0, vn);
+    vfp_load_reg32(f1, vm);
 
     for (;;) {
         if (reads_vd) {
-            neon_load_reg32(fd, vd);
+            vfp_load_reg32(fd, vd);
         }
         fn(fd, f0, f1, fpst);
-        neon_store_reg32(fd, vd);
+        vfp_store_reg32(fd, vd);
 
         if (veclen == 0) {
             break;
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
         veclen--;
         vd = vfp_advance_sreg(vd, delta_d);
         vn = vfp_advance_sreg(vn, delta_d);
-        neon_load_reg32(f0, vn);
+        vfp_load_reg32(f0, vn);
         if (delta_m) {
             vm = vfp_advance_sreg(vm, delta_m);
-            neon_load_reg32(f1, vm);
+            vfp_load_reg32(f1, vm);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn,
     fd = tcg_temp_new_i32();
     fpst = fpstatus_ptr(FPST_FPCR_F16);
 
-    neon_load_reg32(f0, vn);
-    neon_load_reg32(f1, vm);
+    vfp_load_reg32(f0, vn);
+    vfp_load_reg32(f1, vm);
 
     if (reads_vd) {
-        neon_load_reg32(fd, vd);
+        vfp_load_reg32(fd, vd);
     }
     fn(fd, f0, f1, fpst);
-    neon_store_reg32(fd, vd);
+    vfp_store_reg32(fd, vd);
 
     tcg_temp_free_i32(f0);
     tcg_temp_free_i32(f1);
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
     f0 = tcg_temp_new_i32();
     fd = tcg_temp_new_i32();
 
-    neon_load_reg32(f0, vm);
+    vfp_load_reg32(f0, vm);
 
     for (;;) {
         fn(fd, f0);
-        neon_store_reg32(fd, vd);
+        vfp_store_reg32(fd, vd);
 
         if (veclen == 0) {
             break;
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
             /* single source one-many */
             while (veclen--) {
                 vd = vfp_advance_sreg(vd, delta_d);
-                neon_store_reg32(fd, vd);
+                vfp_store_reg32(fd, vd);
             }
             break;
         }
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
         veclen--;
         vd = vfp_advance_sreg(vd, delta_d);
         vm = vfp_advance_sreg(vm, delta_m);
-        neon_load_reg32(f0, vm);
+        vfp_load_reg32(f0, vm);
     }
 
     tcg_temp_free_i32(f0);
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
     }
 
     f0 = tcg_temp_new_i32();
-    neon_load_reg32(f0, vm);
+    vfp_load_reg32(f0, vm);
     fn(f0, f0);
-    neon_store_reg32(f0, vd);
+    vfp_store_reg32(f0, vd);
     tcg_temp_free_i32(f0);
 
     return true;
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
     vm = tcg_temp_new_i32();
     vd = tcg_temp_new_i32();
 
-    neon_load_reg32(vn, a->vn);
-    neon_load_reg32(vm, a->vm);
+    vfp_load_reg32(vn, a->vn);
+    vfp_load_reg32(vm, a->vm);
     if (neg_n) {
         /* VFNMS, VFMS */
         gen_helper_vfp_negh(vn, vn);
     }
-    neon_load_reg32(vd, a->vd);
+    vfp_load_reg32(vd, a->vd);
     if (neg_d) {
         /* VFNMA, VFNMS */
         gen_helper_vfp_negh(vd, vd);
     }
     fpst = fpstatus_ptr(FPST_FPCR_F16);
     gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst);
-    neon_store_reg32(vd, a->vd);
+    vfp_store_reg32(vd, a->vd);
 
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(vn);
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
     vm = tcg_temp_new_i32();
     vd = tcg_temp_new_i32();
 
-    neon_load_reg32(vn, a->vn);
-    neon_load_reg32(vm, a->vm);
+    vfp_load_reg32(vn, a->vn);
+    vfp_load_reg32(vm, a->vm);
     if (neg_n) {
         /* VFNMS, VFMS */
         gen_helper_vfp_negs(vn, vn);
     }
-    neon_load_reg32(vd, a->vd);
+    vfp_load_reg32(vd, a->vd);
     if (neg_d) {
         /* VFNMA, VFNMS */
         gen_helper_vfp_negs(vd, vd);
     }
     fpst = fpstatus_ptr(FPST_FPCR);
     gen_helper_vfp_muladds(vd, vn, vm, vd, fpst);
-    neon_store_reg32(vd, a->vd);
+    vfp_store_reg32(vd, a->vd);
 
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(vn);
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a)
     }
 
     fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm));
-    neon_store_reg32(fd, a->vd);
+    vfp_store_reg32(fd, a->vd);
     tcg_temp_free_i32(fd);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
     fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
 
     for (;;) {
-        neon_store_reg32(fd, vd);
+        vfp_store_reg32(fd, vd);
 
         if (veclen == 0) {
             break;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a)
     vd = tcg_temp_new_i32();
     vm = tcg_temp_new_i32();
 
-    neon_load_reg32(vd, a->vd);
+    vfp_load_reg32(vd, a->vd);
     if (a->z) {
         tcg_gen_movi_i32(vm, 0);
     } else {
-        neon_load_reg32(vm, a->vm);
+        vfp_load_reg32(vm, a->vm);
     }
 
     if (a->e) {
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
     vd = tcg_temp_new_i32();
     vm = tcg_temp_new_i32();
 
-    neon_load_reg32(vd, a->vd);
+    vfp_load_reg32(vd, a->vd);
     if (a->z) {
         tcg_gen_movi_i32(vm, 0);
     } else {
-        neon_load_reg32(vm, a->vm);
+        vfp_load_reg32(vm, a->vm);
     }
 
     if (a->e) {
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a)
     /* The T bit tells us if we want the low or high 16 bits of Vm */
     tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
     gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode);
-    neon_store_reg32(tmp, a->vd);
+    vfp_store_reg32(tmp, a->vd);
     tcg_temp_free_i32(ahp_mode);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a)
     ahp_mode = get_ahp_flag();
     tmp = tcg_temp_new_i32();
 
-    neon_load_reg32(tmp, a->vm);
+    vfp_load_reg32(tmp, a->vm);
     gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode);
     tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
     tcg_temp_free_i32(ahp_mode);
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a)
     }
 
     tmp = tcg_temp_new_i32();
-    neon_load_reg32(tmp, a->vm);
+    vfp_load_reg32(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR_F16);
     gen_helper_rinth(tmp, tmp, fpst);
-    neon_store_reg32(tmp, a->vd);
+    vfp_store_reg32(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(tmp);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a)
     }
 
     tmp = tcg_temp_new_i32();
-    neon_load_reg32(tmp, a->vm);
+    vfp_load_reg32(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR);
     gen_helper_rints(tmp, tmp, fpst);
-    neon_store_reg32(tmp, a->vd);
+    vfp_store_reg32(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(tmp);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
     }
 
     tmp = tcg_temp_new_i32();
-    neon_load_reg32(tmp, a->vm);
+    vfp_load_reg32(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR_F16);
     tcg_rmode = tcg_const_i32(float_round_to_zero);
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
     gen_helper_rinth(tmp, tmp, fpst);
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-    neon_store_reg32(tmp, a->vd);
+    vfp_store_reg32(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(tcg_rmode);
     tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
     }
 
     tmp = tcg_temp_new_i32();
-    neon_load_reg32(tmp, a->vm);
+    vfp_load_reg32(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR);
     tcg_rmode = tcg_const_i32(float_round_to_zero);
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
     gen_helper_rints(tmp, tmp, fpst);
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-    neon_store_reg32(tmp, a->vd);
+    vfp_store_reg32(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(tcg_rmode);
     tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a)
     }
 
     tmp = tcg_temp_new_i32();
-    neon_load_reg32(tmp, a->vm);
+    vfp_load_reg32(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR_F16);
     gen_helper_rinth_exact(tmp, tmp, fpst);
-    neon_store_reg32(tmp, a->vd);
+    vfp_store_reg32(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(tmp);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a)
     }
 
     tmp = tcg_temp_new_i32();
-    neon_load_reg32(tmp, a->vm);
+    vfp_load_reg32(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR);
     gen_helper_rints_exact(tmp, tmp, fpst);
-    neon_store_reg32(tmp, a->vd);
+    vfp_store_reg32(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(tmp);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
 
     vm = tcg_temp_new_i32();
     vd = tcg_temp_new_i64();
-    neon_load_reg32(vm, a->vm);
+    vfp_load_reg32(vm, a->vm);
     gen_helper_vfp_fcvtds(vd, vm, cpu_env);
     neon_store_reg64(vd, a->vd);
     tcg_temp_free_i32(vm);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
     vm = tcg_temp_new_i64();
     neon_load_reg64(vm, a->vm);
     gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
-    neon_store_reg32(vd, a->vd);
+    vfp_store_reg32(vd, a->vd);
     tcg_temp_free_i32(vd);
     tcg_temp_free_i64(vm);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
     }
 
     vm = tcg_temp_new_i32();
-    neon_load_reg32(vm, a->vm);
+    vfp_load_reg32(vm, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR_F16);
     if (a->s) {
         /* i32 -> f16 */
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a)
         /* u32 -> f16 */
         gen_helper_vfp_uitoh(vm, vm, fpst);
     }
-    neon_store_reg32(vm, a->vd);
+    vfp_store_reg32(vm, a->vd);
     tcg_temp_free_i32(vm);
     tcg_temp_free_ptr(fpst);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
     }
 
     vm = tcg_temp_new_i32();
-    neon_load_reg32(vm, a->vm);
+    vfp_load_reg32(vm, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR);
     if (a->s) {
         /* i32 -> f32 */
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
         /* u32 -> f32 */
         gen_helper_vfp_uitos(vm, vm, fpst);
     }
-    neon_store_reg32(vm, a->vd);
+    vfp_store_reg32(vm, a->vd);
     tcg_temp_free_i32(vm);
     tcg_temp_free_ptr(fpst);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
 
     vm = tcg_temp_new_i32();
     vd = tcg_temp_new_i64();
-    neon_load_reg32(vm, a->vm);
+    vfp_load_reg32(vm, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR);
     if (a->s) {
         /* i32 -> f64 */
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
     vd = tcg_temp_new_i32();
     neon_load_reg64(vm, a->vm);
     gen_helper_vjcvt(vd, vm, cpu_env);
-    neon_store_reg32(vd, a->vd);
+    vfp_store_reg32(vd, a->vd);
     tcg_temp_free_i64(vm);
     tcg_temp_free_i32(vd);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
     frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
 
     vd = tcg_temp_new_i32();
-    neon_load_reg32(vd, a->vd);
+    vfp_load_reg32(vd, a->vd);
 
     fpst = fpstatus_ptr(FPST_FPCR_F16);
     shift = tcg_const_i32(frac_bits);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a)
         g_assert_not_reached();
     }
 
-    neon_store_reg32(vd, a->vd);
+    vfp_store_reg32(vd, a->vd);
     tcg_temp_free_i32(vd);
     tcg_temp_free_i32(shift);
     tcg_temp_free_ptr(fpst);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
     frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
 
     vd = tcg_temp_new_i32();
-    neon_load_reg32(vd, a->vd);
+    vfp_load_reg32(vd, a->vd);
 
     fpst = fpstatus_ptr(FPST_FPCR);
     shift = tcg_const_i32(frac_bits);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
         g_assert_not_reached();
     }
 
-    neon_store_reg32(vd, a->vd);
+    vfp_store_reg32(vd, a->vd);
     tcg_temp_free_i32(vd);
     tcg_temp_free_i32(shift);
     tcg_temp_free_ptr(fpst);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
 
     fpst = fpstatus_ptr(FPST_FPCR_F16);
     vm = tcg_temp_new_i32();
-    neon_load_reg32(vm, a->vm);
+    vfp_load_reg32(vm, a->vm);
 
     if (a->s) {
         if (a->rz) {
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a)
             gen_helper_vfp_touih(vm, vm, fpst);
         }
     }
-    neon_store_reg32(vm, a->vd);
+    vfp_store_reg32(vm, a->vd);
     tcg_temp_free_i32(vm);
     tcg_temp_free_ptr(fpst);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
 
     fpst = fpstatus_ptr(FPST_FPCR);
     vm = tcg_temp_new_i32();
-    neon_load_reg32(vm, a->vm);
+    vfp_load_reg32(vm, a->vm);
 
     if (a->s) {
         if (a->rz) {
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
             gen_helper_vfp_touis(vm, vm, fpst);
         }
     }
-    neon_store_reg32(vm, a->vd);
+    vfp_store_reg32(vm, a->vd);
     tcg_temp_free_i32(vm);
     tcg_temp_free_ptr(fpst);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
             gen_helper_vfp_touid(vd, vm, fpst);
         }
     }
-    neon_store_reg32(vd, a->vd);
+    vfp_store_reg32(vd, a->vd);
     tcg_temp_free_i32(vd);
     tcg_temp_free_i64(vm);
     tcg_temp_free_ptr(fpst);
@@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a)
     /* Insert low half of Vm into high half of Vd */
     rm = tcg_temp_new_i32();
     rd = tcg_temp_new_i32();
-    neon_load_reg32(rm, a->vm);
-    neon_load_reg32(rd, a->vd);
+    vfp_load_reg32(rm, a->vm);
+    vfp_load_reg32(rd, a->vd);
     tcg_gen_deposit_i32(rd, rd, rm, 16, 16);
-    neon_store_reg32(rd, a->vd);
+    vfp_store_reg32(rd, a->vd);
     tcg_temp_free_i32(rm);
     tcg_temp_free_i32(rd);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a)
 
     /* Set Vd to high half of Vm */
     rm = tcg_temp_new_i32();
-    neon_load_reg32(rm, a->vm);
+    vfp_load_reg32(rm, a->vm);
     tcg_gen_shri_i32(rm, rm, 16);
-    neon_store_reg32(rm, a->vd);
+    vfp_store_reg32(rm, a->vd);
     tcg_temp_free_i32(rm);
     return true;
 }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Replace all uses of neon_load/store_reg64 within translate-neon.c.inc.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c          | 26 +++++++++
 target/arm/translate-neon.c.inc | 94 ++++++++++++++++-----------------
 2 files changed, 73 insertions(+), 47 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop)
     }
 }
 
+static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
+{
+    long off = neon_element_offset(reg, ele, memop);
+
+    switch (memop) {
+    case MO_Q:
+        tcg_gen_ld_i64(dest, cpu_env, off);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
 {
     long off = neon_element_offset(reg, ele, memop);
@@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop)
     }
 }
 
+static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
+{
+    long off = neon_element_offset(reg, ele, memop);
+
+    switch (memop) {
+    case MO_64:
+        tcg_gen_st_i64(src, cpu_env, off);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
 {
     TCGv_ptr ret = tcg_temp_new_ptr();
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a,
     for (pass = 0; pass < a->q + 1; pass++) {
         TCGv_i64 tmp = tcg_temp_new_i64();
 
-        neon_load_reg64(tmp, a->vm + pass);
+        read_neon_element64(tmp, a->vm, pass, MO_64);
         fn(tmp, cpu_env, tmp, constimm);
-        neon_store_reg64(tmp, a->vd + pass);
+        write_neon_element64(tmp, a->vd, pass, MO_64);
         tcg_temp_free_i64(tmp);
     }
     tcg_temp_free_i64(constimm);
@@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a,
     rd = tcg_temp_new_i32();
 
     /* Load both inputs first to avoid potential overwrite if rm == rd */
-    neon_load_reg64(rm1, a->vm);
-    neon_load_reg64(rm2, a->vm + 1);
+    read_neon_element64(rm1, a->vm, 0, MO_64);
+    read_neon_element64(rm2, a->vm, 1, MO_64);
 
     shiftfn(rm1, rm1, constimm);
     narrowfn(rd, cpu_env, rm1);
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
         tcg_gen_shli_i64(tmp, tmp, a->shift);
         tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
     }
-    neon_store_reg64(tmp, a->vd);
+    write_neon_element64(tmp, a->vd, 0, MO_64);
 
     widenfn(tmp, rm1);
     tcg_temp_free_i32(rm1);
@@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a,
         tcg_gen_shli_i64(tmp, tmp, a->shift);
         tcg_gen_andi_i64(tmp, tmp, ~widen_mask);
     }
-    neon_store_reg64(tmp, a->vd + 1);
+    write_neon_element64(tmp, a->vd, 1, MO_64);
     tcg_temp_free_i64(tmp);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
     rm_64 = tcg_temp_new_i64();
 
     if (src1_wide) {
-        neon_load_reg64(rn0_64, a->vn);
+        read_neon_element64(rn0_64, a->vn, 0, MO_64);
     } else {
         TCGv_i32 tmp = tcg_temp_new_i32();
         read_neon_element32(tmp, a->vn, 0, MO_32);
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
      * avoid incorrect results if a narrow input overlaps with the result.
      */
     if (src1_wide) {
-        neon_load_reg64(rn1_64, a->vn + 1);
+        read_neon_element64(rn1_64, a->vn, 1, MO_64);
     } else {
         TCGv_i32 tmp = tcg_temp_new_i32();
         read_neon_element32(tmp, a->vn, 1, MO_32);
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
     rm = tcg_temp_new_i32();
     read_neon_element32(rm, a->vm, 1, MO_32);
 
-    neon_store_reg64(rn0_64, a->vd);
+    write_neon_element64(rn0_64, a->vd, 0, MO_64);
 
     widenfn(rm_64, rm);
     tcg_temp_free_i32(rm);
     opfn(rn1_64, rn1_64, rm_64);
-    neon_store_reg64(rn1_64, a->vd + 1);
+    write_neon_element64(rn1_64, a->vd, 1, MO_64);
 
     tcg_temp_free_i64(rn0_64);
     tcg_temp_free_i64(rn1_64);
@@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
     rd0 = tcg_temp_new_i32();
     rd1 = tcg_temp_new_i32();
 
-    neon_load_reg64(rn_64, a->vn);
-    neon_load_reg64(rm_64, a->vm);
+    read_neon_element64(rn_64, a->vn, 0, MO_64);
+    read_neon_element64(rm_64, a->vm, 0, MO_64);
 
     opfn(rn_64, rn_64, rm_64);
 
     narrowfn(rd0, rn_64);
 
-    neon_load_reg64(rn_64, a->vn + 1);
-    neon_load_reg64(rm_64, a->vm + 1);
+    read_neon_element64(rn_64, a->vn, 1, MO_64);
+    read_neon_element64(rm_64, a->vm, 1, MO_64);
 
     opfn(rn_64, rn_64, rm_64);
 
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
     /* Don't store results until after all loads: they might overlap */
     if (accfn) {
         tmp = tcg_temp_new_i64();
-        neon_load_reg64(tmp, a->vd);
+        read_neon_element64(tmp, a->vd, 0, MO_64);
         accfn(tmp, tmp, rd0);
-        neon_store_reg64(tmp, a->vd);
-        neon_load_reg64(tmp, a->vd + 1);
+        write_neon_element64(tmp, a->vd, 0, MO_64);
+        read_neon_element64(tmp, a->vd, 1, MO_64);
         accfn(tmp, tmp, rd1);
-        neon_store_reg64(tmp, a->vd + 1);
+        write_neon_element64(tmp, a->vd, 1, MO_64);
         tcg_temp_free_i64(tmp);
     } else {
-        neon_store_reg64(rd0, a->vd);
-        neon_store_reg64(rd1, a->vd + 1);
+        write_neon_element64(rd0, a->vd, 0, MO_64);
+        write_neon_element64(rd1, a->vd, 1, MO_64);
     }
 
     tcg_temp_free_i64(rd0);
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
 
     if (accfn) {
         TCGv_i64 t64 = tcg_temp_new_i64();
-        neon_load_reg64(t64, a->vd);
+        read_neon_element64(t64, a->vd, 0, MO_64);
         accfn(t64, t64, rn0_64);
-        neon_store_reg64(t64, a->vd);
-        neon_load_reg64(t64, a->vd + 1);
+        write_neon_element64(t64, a->vd, 0, MO_64);
+        read_neon_element64(t64, a->vd, 1, MO_64);
         accfn(t64, t64, rn1_64);
-        neon_store_reg64(t64, a->vd + 1);
+        write_neon_element64(t64, a->vd, 1, MO_64);
         tcg_temp_free_i64(t64);
     } else {
-        neon_store_reg64(rn0_64, a->vd);
-        neon_store_reg64(rn1_64, a->vd + 1);
+        write_neon_element64(rn0_64, a->vd, 0, MO_64);
+        write_neon_element64(rn1_64, a->vd, 1, MO_64);
     }
     tcg_temp_free_i64(rn0_64);
     tcg_temp_free_i64(rn1_64);
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
         right = tcg_temp_new_i64();
         dest = tcg_temp_new_i64();
 
-        neon_load_reg64(right, a->vn);
-        neon_load_reg64(left, a->vm);
+        read_neon_element64(right, a->vn, 0, MO_64);
+        read_neon_element64(left, a->vm, 0, MO_64);
         tcg_gen_extract2_i64(dest, right, left, a->imm * 8);
-        neon_store_reg64(dest, a->vd);
+        write_neon_element64(dest, a->vd, 0, MO_64);
 
         tcg_temp_free_i64(left);
         tcg_temp_free_i64(right);
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
         destright = tcg_temp_new_i64();
 
         if (a->imm < 8) {
-            neon_load_reg64(right, a->vn);
-            neon_load_reg64(middle, a->vn + 1);
+            read_neon_element64(right, a->vn, 0, MO_64);
+            read_neon_element64(middle, a->vn, 1, MO_64);
             tcg_gen_extract2_i64(destright, right, middle, a->imm * 8);
-            neon_load_reg64(left, a->vm);
+            read_neon_element64(left, a->vm, 0, MO_64);
             tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8);
         } else {
-            neon_load_reg64(right, a->vn + 1);
-            neon_load_reg64(middle, a->vm);
+            read_neon_element64(right, a->vn, 1, MO_64);
+            read_neon_element64(middle, a->vm, 0, MO_64);
             tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8);
-            neon_load_reg64(left, a->vm + 1);
+            read_neon_element64(left, a->vm, 1, MO_64);
             tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8);
         }
 
-        neon_store_reg64(destright, a->vd);
-        neon_store_reg64(destleft, a->vd + 1);
+        write_neon_element64(destright, a->vd, 0, MO_64);
+        write_neon_element64(destleft, a->vd, 1, MO_64);
 
         tcg_temp_free_i64(destright);
         tcg_temp_free_i64(destleft);
@@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a,
 
         if (accfn) {
             TCGv_i64 tmp64 = tcg_temp_new_i64();
-            neon_load_reg64(tmp64, a->vd + pass);
+            read_neon_element64(tmp64, a->vd, pass, MO_64);
             accfn(rd_64, tmp64, rd_64);
             tcg_temp_free_i64(tmp64);
         }
-        neon_store_reg64(rd_64, a->vd + pass);
+        write_neon_element64(rd_64, a->vd, pass, MO_64);
         tcg_temp_free_i64(rd_64);
     }
     return true;
@@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a,
     rd0 = tcg_temp_new_i32();
     rd1 = tcg_temp_new_i32();
 
-    neon_load_reg64(rm, a->vm);
+    read_neon_element64(rm, a->vm, 0, MO_64);
     narrowfn(rd0, cpu_env, rm);
-    neon_load_reg64(rm, a->vm + 1);
+    read_neon_element64(rm, a->vm, 1, MO_64);
     narrowfn(rd1, cpu_env, rm);
     write_neon_element32(rd0, a->vd, 0, MO_32);
     write_neon_element32(rd1, a->vd, 1, MO_32);
@@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a)
 
     widenfn(rd, rm0);
     tcg_gen_shli_i64(rd, rd, 8 << a->size);
-    neon_store_reg64(rd, a->vd);
+    write_neon_element64(rd, a->vd, 0, MO_64);
     widenfn(rd, rm1);
     tcg_gen_shli_i64(rd, rd, 8 << a->size);
-    neon_store_reg64(rd, a->vd + 1);
+    write_neon_element64(rd, a->vd, 1, MO_64);
 
     tcg_temp_free_i64(rd);
     tcg_temp_free_i32(rm0);
@@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
     rm = tcg_temp_new_i64();
     rd = tcg_temp_new_i64();
     for (pass = 0; pass < (a->q ? 2 : 1); pass++) {
-        neon_load_reg64(rm, a->vm + pass);
-        neon_load_reg64(rd, a->vd + pass);
-        neon_store_reg64(rm, a->vd + pass);
-        neon_store_reg64(rd, a->vm + pass);
+        read_neon_element64(rm, a->vm, pass, MO_64);
+        read_neon_element64(rd, a->vd, pass, MO_64);
+        write_neon_element64(rm, a->vd, pass, MO_64);
+        write_neon_element64(rd, a->vm, pass, MO_64);
     }
     tcg_temp_free_i64(rm);
     tcg_temp_free_i64(rd);
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The only uses of this function are for loading VFP
double-precision values, and nothing to do with NEON.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c         |  8 ++--
 target/arm/translate-vfp.c.inc | 84 +++++++++++++++++-----------------
 2 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg)
     }
 }
 
-static inline void neon_load_reg64(TCGv_i64 var, int reg)
+static inline void vfp_load_reg64(TCGv_i64 var, int reg)
 {
-    tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
+    tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg));
 }
 
-static inline void neon_store_reg64(TCGv_i64 var, int reg)
+static inline void vfp_store_reg64(TCGv_i64 var, int reg)
 {
-    tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
+    tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg));
 }
 
 static inline void vfp_load_reg32(TCGv_i32 var, int reg)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
         tcg_gen_ext_i32_i64(nf, cpu_NF);
         tcg_gen_ext_i32_i64(vf, cpu_VF);
 
-        neon_load_reg64(frn, rn);
-        neon_load_reg64(frm, rm);
+        vfp_load_reg64(frn, rn);
+        vfp_load_reg64(frm, rm);
         switch (a->cc) {
         case 0: /* eq: Z */
             tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero,
@@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
             tcg_temp_free_i64(tmp);
             break;
         }
-        neon_store_reg64(dest, rd);
+        vfp_store_reg64(dest, rd);
         tcg_temp_free_i64(frn);
         tcg_temp_free_i64(frm);
         tcg_temp_free_i64(dest);
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
         TCGv_i64 tcg_res;
         tcg_op = tcg_temp_new_i64();
         tcg_res = tcg_temp_new_i64();
-        neon_load_reg64(tcg_op, rm);
+        vfp_load_reg64(tcg_op, rm);
         gen_helper_rintd(tcg_res, tcg_op, fpst);
-        neon_store_reg64(tcg_res, rd);
+        vfp_store_reg64(tcg_res, rd);
         tcg_temp_free_i64(tcg_op);
         tcg_temp_free_i64(tcg_res);
     } else {
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
         tcg_double = tcg_temp_new_i64();
         tcg_res = tcg_temp_new_i64();
         tcg_tmp = tcg_temp_new_i32();
-        neon_load_reg64(tcg_double, rm);
+        vfp_load_reg64(tcg_double, rm);
         if (is_signed) {
             gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst);
         } else {
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
     tmp = tcg_temp_new_i64();
     if (a->l) {
         gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
-        neon_store_reg64(tmp, a->vd);
+        vfp_store_reg64(tmp, a->vd);
     } else {
-        neon_load_reg64(tmp, a->vd);
+        vfp_load_reg64(tmp, a->vd);
         gen_aa32_st64(s, tmp, addr, get_mem_index(s));
     }
     tcg_temp_free_i64(tmp);
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
         if (a->l) {
             /* load */
             gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
-            neon_store_reg64(tmp, a->vd + i);
+            vfp_store_reg64(tmp, a->vd + i);
         } else {
             /* store */
-            neon_load_reg64(tmp, a->vd + i);
+            vfp_load_reg64(tmp, a->vd + i);
             gen_aa32_st64(s, tmp, addr, get_mem_index(s));
         }
         tcg_gen_addi_i32(addr, addr, offset);
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
     fd = tcg_temp_new_i64();
     fpst = fpstatus_ptr(FPST_FPCR);
 
-    neon_load_reg64(f0, vn);
-    neon_load_reg64(f1, vm);
+    vfp_load_reg64(f0, vn);
+    vfp_load_reg64(f1, vm);
 
     for (;;) {
         if (reads_vd) {
-            neon_load_reg64(fd, vd);
+            vfp_load_reg64(fd, vd);
         }
         fn(fd, f0, f1, fpst);
-        neon_store_reg64(fd, vd);
+        vfp_store_reg64(fd, vd);
 
         if (veclen == 0) {
             break;
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
         veclen--;
         vd = vfp_advance_dreg(vd, delta_d);
         vn = vfp_advance_dreg(vn, delta_d);
-        neon_load_reg64(f0, vn);
+        vfp_load_reg64(f0, vn);
         if (delta_m) {
             vm = vfp_advance_dreg(vm, delta_m);
-            neon_load_reg64(f1, vm);
+            vfp_load_reg64(f1, vm);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
     f0 = tcg_temp_new_i64();
     fd = tcg_temp_new_i64();
 
-    neon_load_reg64(f0, vm);
+    vfp_load_reg64(f0, vm);
 
     for (;;) {
         fn(fd, f0);
-        neon_store_reg64(fd, vd);
+        vfp_store_reg64(fd, vd);
 
         if (veclen == 0) {
             break;
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
             /* single source one-many */
             while (veclen--) {
                 vd = vfp_advance_dreg(vd, delta_d);
-                neon_store_reg64(fd, vd);
+                vfp_store_reg64(fd, vd);
             }
             break;
         }
@@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
         veclen--;
         vd = vfp_advance_dreg(vd, delta_d);
         vd = vfp_advance_dreg(vm, delta_m);
-        neon_load_reg64(f0, vm);
+        vfp_load_reg64(f0, vm);
     }
 
     tcg_temp_free_i64(f0);
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
     vm = tcg_temp_new_i64();
     vd = tcg_temp_new_i64();
 
-    neon_load_reg64(vn, a->vn);
-    neon_load_reg64(vm, a->vm);
+    vfp_load_reg64(vn, a->vn);
+    vfp_load_reg64(vm, a->vm);
     if (neg_n) {
         /* VFNMS, VFMS */
         gen_helper_vfp_negd(vn, vn);
     }
-    neon_load_reg64(vd, a->vd);
+    vfp_load_reg64(vd, a->vd);
     if (neg_d) {
         /* VFNMA, VFNMS */
         gen_helper_vfp_negd(vd, vd);
     }
     fpst = fpstatus_ptr(FPST_FPCR);
     gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst);
-    neon_store_reg64(vd, a->vd);
+    vfp_store_reg64(vd, a->vd);
 
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i64(vn);
@@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
     fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
 
     for (;;) {
-        neon_store_reg64(fd, vd);
+        vfp_store_reg64(fd, vd);
 
         if (veclen == 0) {
             break;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
     vd = tcg_temp_new_i64();
     vm = tcg_temp_new_i64();
 
-    neon_load_reg64(vd, a->vd);
+    vfp_load_reg64(vd, a->vd);
     if (a->z) {
         tcg_gen_movi_i64(vm, 0);
     } else {
-        neon_load_reg64(vm, a->vm);
+        vfp_load_reg64(vm, a->vm);
     }
 
     if (a->e) {
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
     tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t));
     vd = tcg_temp_new_i64();
     gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode);
-    neon_store_reg64(vd, a->vd);
+    vfp_store_reg64(vd, a->vd);
     tcg_temp_free_i32(ahp_mode);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i32(tmp);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
     tmp = tcg_temp_new_i32();
     vm = tcg_temp_new_i64();
 
-    neon_load_reg64(vm, a->vm);
+    vfp_load_reg64(vm, a->vm);
     gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode);
     tcg_temp_free_i64(vm);
     tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t));
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
     }
 
     tmp = tcg_temp_new_i64();
-    neon_load_reg64(tmp, a->vm);
+    vfp_load_reg64(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR);
     gen_helper_rintd(tmp, tmp, fpst);
-    neon_store_reg64(tmp, a->vd);
+    vfp_store_reg64(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i64(tmp);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
     }
 
     tmp = tcg_temp_new_i64();
-    neon_load_reg64(tmp, a->vm);
+    vfp_load_reg64(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR);
     tcg_rmode = tcg_const_i32(float_round_to_zero);
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
     gen_helper_rintd(tmp, tmp, fpst);
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
-    neon_store_reg64(tmp, a->vd);
+    vfp_store_reg64(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i64(tmp);
     tcg_temp_free_i32(tcg_rmode);
@@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
     }
 
     tmp = tcg_temp_new_i64();
-    neon_load_reg64(tmp, a->vm);
+    vfp_load_reg64(tmp, a->vm);
     fpst = fpstatus_ptr(FPST_FPCR);
     gen_helper_rintd_exact(tmp, tmp, fpst);
-    neon_store_reg64(tmp, a->vd);
+    vfp_store_reg64(tmp, a->vd);
     tcg_temp_free_ptr(fpst);
     tcg_temp_free_i64(tmp);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
     vd = tcg_temp_new_i64();
     vfp_load_reg32(vm, a->vm);
     gen_helper_vfp_fcvtds(vd, vm, cpu_env);
-    neon_store_reg64(vd, a->vd);
+    vfp_store_reg64(vd, a->vd);
     tcg_temp_free_i32(vm);
     tcg_temp_free_i64(vd);
     return true;
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
 
     vd = tcg_temp_new_i32();
     vm = tcg_temp_new_i64();
-    neon_load_reg64(vm, a->vm);
+    vfp_load_reg64(vm, a->vm);
     gen_helper_vfp_fcvtsd(vd, vm, cpu_env);
     vfp_store_reg32(vd, a->vd);
     tcg_temp_free_i32(vd);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
         /* u32 -> f64 */
         gen_helper_vfp_uitod(vd, vm, fpst);
     }
-    neon_store_reg64(vd, a->vd);
+    vfp_store_reg64(vd, a->vd);
     tcg_temp_free_i32(vm);
     tcg_temp_free_i64(vd);
     tcg_temp_free_ptr(fpst);
@@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
 
     vm = tcg_temp_new_i64();
     vd = tcg_temp_new_i32();
-    neon_load_reg64(vm, a->vm);
+    vfp_load_reg64(vm, a->vm);
     gen_helper_vjcvt(vd, vm, cpu_env);
     vfp_store_reg32(vd, a->vd);
     tcg_temp_free_i64(vm);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
     frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm);
 
     vd = tcg_temp_new_i64();
-    neon_load_reg64(vd, a->vd);
+    vfp_load_reg64(vd, a->vd);
 
     fpst = fpstatus_ptr(FPST_FPCR);
     shift = tcg_const_i32(frac_bits);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
         g_assert_not_reached();
     }
 
-    neon_store_reg64(vd, a->vd);
+    vfp_store_reg64(vd, a->vd);
     tcg_temp_free_i64(vd);
     tcg_temp_free_i32(shift);
     tcg_temp_free_ptr(fpst);
@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
     fpst = fpstatus_ptr(FPST_FPCR);
     vm = tcg_temp_new_i64();
     vd = tcg_temp_new_i32();
-    neon_load_reg64(vm, a->vm);
+    vfp_load_reg64(vm, a->vm);
 
     if (a->s) {
         if (a->rz) {
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

In both cases, we can sink the write-back and perform
the accumulate into the normal destination temps.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-11-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-neon.c.inc | 23 +++++++++--------------
 1 file changed, 9 insertions(+), 14 deletions(-)

diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a,
     if (accfn) {
         tmp = tcg_temp_new_i64();
         read_neon_element64(tmp, a->vd, 0, MO_64);
-        accfn(tmp, tmp, rd0);
-        write_neon_element64(tmp, a->vd, 0, MO_64);
+        accfn(rd0, tmp, rd0);
         read_neon_element64(tmp, a->vd, 1, MO_64);
-        accfn(tmp, tmp, rd1);
-        write_neon_element64(tmp, a->vd, 1, MO_64);
+        accfn(rd1, tmp, rd1);
         tcg_temp_free_i64(tmp);
-    } else {
-        write_neon_element64(rd0, a->vd, 0, MO_64);
-        write_neon_element64(rd1, a->vd, 1, MO_64);
     }
 
+    write_neon_element64(rd0, a->vd, 0, MO_64);
+    write_neon_element64(rd1, a->vd, 1, MO_64);
     tcg_temp_free_i64(rd0);
     tcg_temp_free_i64(rd1);
 
@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a,
     if (accfn) {
         TCGv_i64 t64 = tcg_temp_new_i64();
         read_neon_element64(t64, a->vd, 0, MO_64);
-        accfn(t64, t64, rn0_64);
-        write_neon_element64(t64, a->vd, 0, MO_64);
+        accfn(rn0_64, t64, rn0_64);
         read_neon_element64(t64, a->vd, 1, MO_64);
-        accfn(t64, t64, rn1_64);
-        write_neon_element64(t64, a->vd, 1, MO_64);
+        accfn(rn1_64, t64, rn1_64);
         tcg_temp_free_i64(t64);
-    } else {
-        write_neon_element64(rn0_64, a->vd, 0, MO_64);
-        write_neon_element64(rn1_64, a->vd, 1, MO_64);
     }
+
+    write_neon_element64(rn0_64, a->vd, 0, MO_64);
+    write_neon_element64(rn1_64, a->vd, 1, MO_64);
     tcg_temp_free_i64(rn0_64);
     tcg_temp_free_i64(rn1_64);
     return true;
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

We can use proper widening loads to extend 32-bit inputs,
and skip the "widenfn" step.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c          |  6 +++
 target/arm/translate-neon.c.inc | 66 ++++++++++++++++++---------------
 2 files changed, 43 insertions(+), 29 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop)
     long off = neon_element_offset(reg, ele, memop);
 
     switch (memop) {
+    case MO_SL:
+        tcg_gen_ld32s_i64(dest, cpu_env, off);
+        break;
+    case MO_UL:
+        tcg_gen_ld32u_i64(dest, cpu_env, off);
+        break;
     case MO_Q:
         tcg_gen_ld_i64(dest, cpu_env, off);
         break;
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a)
 static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
                            NeonGenWidenFn *widenfn,
                            NeonGenTwo64OpFn *opfn,
-                           bool src1_wide)
+                           int src1_mop, int src2_mop)
 {
     /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */
     TCGv_i64 rn0_64, rn1_64, rm_64;
-    TCGv_i32 rm;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
         return false;
     }
 
-    if (!widenfn || !opfn) {
+    if (!opfn) {
         /* size == 3 case, which is an entirely different insn group */
         return false;
     }
 
-    if ((a->vd & 1) || (src1_wide && (a->vn & 1))) {
+    if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
     rn1_64 = tcg_temp_new_i64();
     rm_64 = tcg_temp_new_i64();
 
-    if (src1_wide) {
-        read_neon_element64(rn0_64, a->vn, 0, MO_64);
+    if (src1_mop >= 0) {
+        read_neon_element64(rn0_64, a->vn, 0, src1_mop);
     } else {
         TCGv_i32 tmp = tcg_temp_new_i32();
         read_neon_element32(tmp, a->vn, 0, MO_32);
         widenfn(rn0_64, tmp);
         tcg_temp_free_i32(tmp);
     }
-    rm = tcg_temp_new_i32();
-    read_neon_element32(rm, a->vm, 0, MO_32);
+    if (src2_mop >= 0) {
+        read_neon_element64(rm_64, a->vm, 0, src2_mop);
+    } else {
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        read_neon_element32(tmp, a->vm, 0, MO_32);
+        widenfn(rm_64, tmp);
+        tcg_temp_free_i32(tmp);
+    }
 
-    widenfn(rm_64, rm);
-    tcg_temp_free_i32(rm);
     opfn(rn0_64, rn0_64, rm_64);
 
     /*
      * Load second pass inputs before storing the first pass result, to
      * avoid incorrect results if a narrow input overlaps with the result.
      */
-    if (src1_wide) {
-        read_neon_element64(rn1_64, a->vn, 1, MO_64);
+    if (src1_mop >= 0) {
+        read_neon_element64(rn1_64, a->vn, 1, src1_mop);
     } else {
         TCGv_i32 tmp = tcg_temp_new_i32();
         read_neon_element32(tmp, a->vn, 1, MO_32);
         widenfn(rn1_64, tmp);
         tcg_temp_free_i32(tmp);
     }
-    rm = tcg_temp_new_i32();
-    read_neon_element32(rm, a->vm, 1, MO_32);
+    if (src2_mop >= 0) {
+        read_neon_element64(rm_64, a->vm, 1, src2_mop);
+    } else {
+        TCGv_i32 tmp = tcg_temp_new_i32();
+        read_neon_element32(tmp, a->vm, 1, MO_32);
+        widenfn(rm_64, tmp);
+        tcg_temp_free_i32(tmp);
+    }
 
     write_neon_element64(rn0_64, a->vd, 0, MO_64);
 
-    widenfn(rm_64, rm);
-    tcg_temp_free_i32(rm);
     opfn(rn1_64, rn1_64, rm_64);
     write_neon_element64(rn1_64, a->vd, 1, MO_64);
 
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
     return true;
 }
 
-#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE)                         \
+#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN)                        \
     static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a)        \
     {                                                                   \
         static NeonGenWidenFn * const widenfn[] = {                     \
             gen_helper_neon_widen_##S##8,                               \
             gen_helper_neon_widen_##S##16,                              \
-            tcg_gen_##EXT##_i32_i64,                                    \
-            NULL,                                                       \
+            NULL, NULL,                                                 \
         };                                                              \
         static NeonGenTwo64OpFn * const addfn[] = {                     \
             gen_helper_neon_##OP##l_u16,                                \
@@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
             tcg_gen_##OP##_i64,                                         \
             NULL,                                                       \
         };                                                              \
-        return do_prewiden_3d(s, a, widenfn[a->size],                   \
-                              addfn[a->size], SRC1WIDE);                \
+        int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1;          \
+        return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size],   \
+                              SRC1WIDE ? MO_Q : narrow_mop,             \
+                              narrow_mop);                              \
     }
 
-DO_PREWIDEN(VADDL_S, s, ext, add, false)
-DO_PREWIDEN(VADDL_U, u, extu, add, false)
-DO_PREWIDEN(VSUBL_S, s, ext, sub, false)
-DO_PREWIDEN(VSUBL_U, u, extu, sub, false)
-DO_PREWIDEN(VADDW_S, s, ext, add, true)
-DO_PREWIDEN(VADDW_U, u, extu, add, true)
-DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
-DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
+DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN)
+DO_PREWIDEN(VADDL_U, u, add, false, 0)
+DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN)
+DO_PREWIDEN(VSUBL_U, u, sub, false, 0)
+DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN)
+DO_PREWIDEN(VADDW_U, u, add, true, 0)
+DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN)
+DO_PREWIDEN(VSUBW_U, u, sub, true, 0)
 
 static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
                          NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
-- 
2.20.1

In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error
meant we were using the H4() address swizzler macro rather than the
H2() which is required for 2-byte data.  This had no effect on
little-endian hosts but meant we put the result data into the
destination Dreg in the wrong order on big-endian hosts.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201028191712.4910-2-peter.maydell@linaro.org
---
 target/arm/vec_helper.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)
         r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst);                    \
         r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst);                    \
                                                                         \
-        d[H4(0)] = r0;                                                  \
-        d[H4(1)] = r1;                                                  \
-        d[H4(2)] = r2;                                                  \
-        d[H4(3)] = r3;                                                  \
+        d[H2(0)] = r0;                                                  \
+        d[H2(1)] = r1;                                                  \
+        d[H2(2)] = r2;                                                  \
+        d[H2(3)] = r3;                                                  \
     }
 
 DO_NEON_PAIRWISE(neon_padd, add)
-- 
2.20.1

The helper functions for performing the udot/sdot operations against
a scalar were not using an address-swizzling macro when converting
the index of the scalar element into a pointer into the vm array.
This had no effect on little-endian hosts but meant we generated
incorrect results on big-endian hosts.

For these insns, the index is indexing over group of 4 8-bit values,
so 32 bits per indexed entity, and H4() is therefore what we want.
(For Neon the only possible input indexes are 0 and 1.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201028191712.4910-3-peter.maydell@linaro.org
---
 target/arm/vec_helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
     intptr_t index = simd_data(desc);
     uint32_t *d = vd;
     int8_t *n = vn;
-    int8_t *m_indexed = (int8_t *)vm + index * 4;
+    int8_t *m_indexed = (int8_t *)vm + H4(index) * 4;
 
     /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
      * Otherwise opr_sz is a multiple of 16.
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
     intptr_t index = simd_data(desc);
     uint32_t *d = vd;
     uint8_t *n = vn;
-    uint8_t *m_indexed = (uint8_t *)vm + index * 4;
+    uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4;
 
     /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
      * Otherwise opr_sz is a multiple of 16.
-- 
2.20.1

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

HCR should be applied when NS is set, not when it is cleared.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
 /*
  * Non-IS variants of TLB operations are upgraded to
- * IS versions if we are at NS EL1 and HCR_EL2.FB is set to
+ * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
  * force broadcast of these operations.
  */
 static bool tlb_force_broadcast(CPUARMState *env)
 {
-    return (env->cp15.hcr_el2 & HCR_FB) &&
-        arm_current_el(env) == 1 && arm_is_secure_below_el3(env);
+    return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
 }
 
 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.20.1

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

Secure mode is not exempted from checking SCR_EL3.TLOR, and in the
future HCR_EL2.TLOR when S-EL2 is enabled.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 19 +++++--------------
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
 #endif
 
 /* Shared logic between LORID and the rest of the LOR* registers.
- * Secure state has already been delt with.
+ * Secure state exclusion has already been dealt with.
  */
-static CPAccessResult access_lor_ns(CPUARMState *env)
+static CPAccessResult access_lor_ns(CPUARMState *env,
+                                    const ARMCPRegInfo *ri, bool isread)
 {
     int el = arm_current_el(env);
 
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env)
     return CP_ACCESS_OK;
 }
 
-static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,
-                                   bool isread)
-{
-    if (arm_is_secure_below_el3(env)) {
-        /* Access ok in secure mode.  */
-        return CP_ACCESS_OK;
-    }
-    return access_lor_ns(env);
-}
-
 static CPAccessResult access_lor_other(CPUARMState *env,
                                        const ARMCPRegInfo *ri, bool isread)
 {
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env,
         /* Access denied in secure mode.  */
         return CP_ACCESS_TRAP;
     }
-    return access_lor_ns(env);
+    return access_lor_ns(env, ri, isread);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
-      .access = PL1_R, .accessfn = access_lorid,
+      .access = PL1_R, .accessfn = access_lor_ns,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     REGINFO_SENTINEL
 };
-- 
2.20.1

If we're using the capstone disassembler, disassembly of a run of
instructions more than 32 bytes long disassembles the wrong data for
instructions beyond the 32 byte mark:

(qemu) xp /16x 0x100
0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000
0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000
0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574
0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000
(qemu) xp /16i 0x100
0x00000100: 00000005 andeq r0, r0, r5
0x00000104: 54410001 strbpl r0, [r1], #-1
0x00000108: 00000001 andeq r0, r0, r1
0x0000010c: 00001000 andeq r1, r0, r0
0x00000110: 00000000 andeq r0, r0, r0
0x00000114: 00000004 andeq r0, r0, r4
0x00000118: 54410002 strbpl r0, [r1], #-2
0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
0x00000120: 54410001 strbpl r0, [r1], #-1
0x00000124: 00000001 andeq r0, r0, r1
0x00000128: 00001000 andeq r1, r0, r0
0x0000012c: 00000000 andeq r0, r0, r0
0x00000130: 00000004 andeq r0, r0, r4
0x00000134: 54410002 strbpl r0, [r1], #-2
0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c
0x0000013c: 00000000 andeq r0, r0, r0

Here the disassembly of 0x120..0x13f is using the data that is in
0x104..0x123.

This is caused by passing the wrong value to the read_memory_func().
The intention is that at this point in the loop the 'cap_buf' buffer
already contains 'csize' bytes of data for the instruction at guest
addr 'pc', and we want to read in an extra 'tsize' bytes.  Those
extra bytes are therefore at 'pc + csize', not 'pc'.  On the first
time through the loop 'csize' happens to be zero, so the initial read
of 32 bytes into cap_buf is correct and as long as the disassembly
never needs to read more data we return the correct information.

Use the correct guest address in the call to read_memory_func().

Cc: qemu-stable@nongnu.org
Fixes: https://bugs.launchpad.net/qemu/+bug/1900779
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201022132445.25039-1-peter.maydell@linaro.org
---
 disas/capstone.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/disas/capstone.c b/disas/capstone.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/capstone.c
+++ b/disas/capstone.c
@@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count)
 
         /* Make certain that we can make progress.  */
         assert(tsize != 0);
-        info->read_memory_func(pc, cap_buf + csize, tsize, info);
+        info->read_memory_func(pc + csize, cap_buf + csize, tsize, info);
         csize += tsize;
 
         if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) {
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.
This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):

CID 1432363 (#1 of 1): Unintentional integer overflow:

overflow_before_widen:
    Potentially overflowing expression 1 << scale with type int
    (32 bits, signed) is evaluated using 32-bit arithmetic, and
    then used in a context that expects an expression of type
    hwaddr (64 bits, unsigned).

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20201030144617.1535064-1-philmd@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/bitops.h"
 #include "hw/irq.h"
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
         scale = CMD_SCALE(cmd);
         num = CMD_NUM(cmd);
         ttl = CMD_TTL(cmd);
-        num_pages = (num + 1) * (1 << (scale));
+        num_pages = (num + 1) * BIT_ULL(scale);
     }
 
     if (type == SMMU_CMD_TLBI_NH_VA) {
-- 
2.20.1

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so
that SVE will not trap to EL3.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030151541.11976-1-remi@remlab.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     if (cpu_isar_feature(aa64_mte, cpu)) {
                         env->cp15.scr_el3 |= SCR_ATA;
                     }
+                    if (cpu_isar_feature(aa64_sve, cpu)) {
+                        env->cp15.cptr_el[3] |= CPTR_EZ;
+                    }
                     /* AArch64 kernels never boot in secure mode */
                     assert(!info->secure_boot);
                     /* This hook is only supported for AArch32 currently:
-- 
2.20.1

From: AlexChen <alex.chen@huawei.com>

In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before
being check if it is valid, which may lead to NULL pointer dereference.
So move the assignment to surface after checking that the omap_lcd is valid
and move surface_bits_per_pixel(surface) to after the surface assignment.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: AlexChen <alex.chen@huawei.com>
Message-id: 5F9CDB8A.9000001@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/display/omap_lcdc.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/omap_lcdc.c
+++ b/hw/display/omap_lcdc.c
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
 static void omap_update_display(void *opaque)
 {
     struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
-    DisplaySurface *surface = qemu_console_surface(omap_lcd->con);
+    DisplaySurface *surface;
     draw_line_func draw_line;
     int size, height, first, last;
     int width, linesize, step, bpp, frame_offset;
     hwaddr frame_base;
 
-    if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable ||
-        !surface_bits_per_pixel(surface)) {
+    if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) {
+        return;
+    }
+
+    surface = qemu_console_surface(omap_lcd->con);
+    if (!surface_bits_per_pixel(surface)) {
         return;
     }
 
-- 
2.20.1

From: AlexChen <alex.chen@huawei.com>

In exynos4210_fimd_update(), the pointer s is dereferinced before
being check if it is valid, which may lead to NULL pointer dereference.
So move the assignment to global_width after checking that the s is valid.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 5F9F8D88.9030102@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/display/exynos4210_fimd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/display/exynos4210_fimd.c
+++ b/hw/display/exynos4210_fimd.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque)
     bool blend = false;
     uint8_t *host_fb_addr;
     bool is_dirty = false;
-    const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
+    int global_width;
 
     if (!s || !s->console || !s->enabled ||
         surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
         return;
     }
+
+    global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
     exynos4210_update_resolution(s);
     surface = qemu_console_surface(s->console);
 
-- 
2.20.1

In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to
armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el().
This is incorrect when the security state being queried is not the
current one, because arm_current_el() uses the current security state
to determine which of the banked CONTROL.nPRIV bits to look at.
The effect was that if (for instance) Secure state was in privileged
mode but Non-Secure was not then we would return the wrong MMU index.

The only places where we are using this function in a way that could
trigger this bug are for the stack loads during a v8M function-return
and for the instruction fetch of a v8M SG insn.

Fix the bug by expanding out the M-profile version of the
arm_current_el() logic inline so it can use the passed in secstate
rather than env->v7m.secure.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201022164408.13214-1-peter.maydell@linaro.org
---
 target/arm/m_helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
 /* Return the MMU index for a v7M CPU in the specified security state */
 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 {
-    bool priv = arm_current_el(env) != 0;
+    bool priv = arm_v7m_is_handler_mode(env) ||
+        !(env->v7m.control[secstate] & 1);
 
     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
 }
-- 
2.20.1

On some hosts (eg Ubuntu Bionic) pkg-config returns a set of
libraries for gio-2.0 which don't actually work when compiling
statically. (Specifically, the returned library string includes
-lmount, but not -lblkid which -lmount depends upon, so linking
fails due to missing symbols.)

Check that the libraries work, and don't enable gio if they don't,
in the same way we do for gnutls.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200928160402.7961-1-peter.maydell@linaro.org
---
 configure | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/configure b/configure
index XXXXXXX..XXXXXXX 100755
--- a/configure
+++ b/configure
@@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then
 fi
 
 if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then
-    gio=yes
     gio_cflags=$($pkg_config --cflags gio-2.0)
     gio_libs=$($pkg_config --libs gio-2.0)
     gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0)
     if [ ! -x "$gdbus_codegen" ]; then
         gdbus_codegen=
     fi
+    # Check that the libraries actually work -- Ubuntu 18.04 ships
+    # with pkg-config --static --libs data for gio-2.0 that is missing
+    # -lblkid and will give a link error.
+    write_c_skeleton
+    if compile_prog "" "gio_libs" ; then
+        gio=yes
+    else
+        gio=no
+    fi
 else
     gio=no
 fi
-- 
2.20.1

In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt
into the GICv3CPUState struct's maintenance_irq field.  This will
only work if the board happens to have already wired up the CPU
maintenance IRQ before the GIC was realized.  Unfortunately this is
not the case for the 'virt' board, and so the value that gets copied
is NULL (since a qemu_irq is really a pointer to an IRQState struct
under the hood).  The effect is that the CPU interface code never
actually raises the maintenance interrupt line.

Instead, since the GICv3CPUState has a pointer to the CPUState, make
the dereference at the point where we want to raise the interrupt, to
avoid an implicit requirement on board code to wire things up in a
particular order.

Reported-by: Jose Martins <josemartins90@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201009153904.28529-1-peter.maydell@linaro.org
Reviewed-by: Luc Michel <luc@lmichel.fr>
---
 include/hw/intc/arm_gicv3_common.h | 1 -
 hw/intc/arm_gicv3_cpuif.c          | 5 ++---
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -XXX,XX +XXX,XX @@ struct GICv3CPUState {
     qemu_irq parent_fiq;
     qemu_irq parent_virq;
     qemu_irq parent_vfiq;
-    qemu_irq maintenance_irq;
 
     /* Redistributor */
     uint32_t level;                  /* Current IRQ level */
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
     int irqlevel = 0;
     int fiqlevel = 0;
     int maintlevel = 0;
+    ARMCPU *cpu = ARM_CPU(cs->cpu);
 
     idx = hppvi_index(cs);
     trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx);
@@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
 
     qemu_set_irq(cs->parent_vfiq, fiqlevel);
     qemu_set_irq(cs->parent_virq, irqlevel);
-    qemu_set_irq(cs->maintenance_irq, maintlevel);
+    qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel);
 }
 
 static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
@@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s)
             && cpu->gic_num_lrs) {
             int j;
 
-            cs->maintenance_irq = cpu->gicv3_maintenance_interrupt;
-
             cs->num_list_regs = cpu->gic_num_lrs;
             cs->vpribits = cpu->gic_vpribits;
             cs->vprebits = cpu->gic_vprebits;
-- 
2.20.1

The kerneldoc script currently emits Sphinx markup for a macro with
arguments that uses the c:function directive. This is correct for
Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow
documentation of macros with arguments and c:function is not picky
about the syntax of what it is passed. However, in Sphinx 3 the
c:macro directive was enhanced to support macros with arguments,
and c:function was made more picky about what syntax it accepted.

When kerneldoc is told that it needs to produce output for Sphinx
3 or later, make it emit c:function only for functions and c:macro
for macros with arguments. We assume that anything with a return
type is a function and anything without is a macro.

This fixes the Sphinx error:

/home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator
If declarator-id with parameters (e.g., 'void f(int arg)'):
  Invalid C declaration: Expected identifier in nested name. [error at 25]
    DECLARE_INSTANCE_CHECKER ( InstanceType,  OBJ_NAME,  TYPENAME)
    -------------------------^
If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'):
  Error in declarator or parameters
  Invalid C declaration: Expecting "(" in parameters. [error at 39]
    DECLARE_INSTANCE_CHECKER ( InstanceType,  OBJ_NAME,  TYPENAME)
    ---------------------------------------^

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 20201030174700.7204-2-peter.maydell@linaro.org
---
 scripts/kernel-doc | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/scripts/kernel-doc b/scripts/kernel-doc
index XXXXXXX..XXXXXXX 100755
--- a/scripts/kernel-doc
+++ b/scripts/kernel-doc
@@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) {
 	output_highlight_rst($args{'purpose'});
 	$start = "\n\n**Syntax**\n\n  ``";
     } else {
-	print ".. c:function:: ";
+        if ((split(/\./, $sphinx_version))[0] >= 3) {
+            # Sphinx 3 and later distinguish macros and functions and
+            # complain if you use c:function with something that's not
+            # syntactically valid as a function declaration.
+            # We assume that anything with a return type is a function
+            # and anything without is a macro.
+            if ($args{'functiontype'} ne "") {
+                print ".. c:function:: ";
+            } else {
+                print ".. c:macro:: ";
+            }
+        } else {
+            # Older Sphinx don't support documenting macros that take
+            # arguments with c:macro, and don't complain about the use
+            # of c:function for this.
+            print ".. c:function:: ";
+        }
     }
     if ($args{'functiontype'} ne "") {
 	$start .= $args{'functiontype'} . " " . $args{'function'} . " (";
-- 
2.20.1

Sphinx 3.2 is pickier than earlier versions about the option:: markup,
and complains about our usage in qemu-option-trace.rst:

../../docs/qemu-option-trace.rst.inc:4:Malformed option description
  '[enable=]PATTERN', should look like "opt", "-opt args", "--opt args",
  "/opt args" or "+opt args"

In this file, we're really trying to document the different parts of
the top-level --trace option, which qemu-nbd.rst and qemu-img.rst
have already introduced with an option:: markup.  So it's not right
to use option:: here anyway.  Switch to a different markup
(definition lists) which gives about the same formatted output.

(Unlike option::, this markup doesn't produce index entries; but
at the moment we don't do anything much with indexes anyway, and
in any case I think it doesn't make much sense to have individual
index entries for the sub-parts of the --trace option.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 20201030174700.7204-3-peter.maydell@linaro.org
---
 docs/qemu-option-trace.rst.inc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc
index XXXXXXX..XXXXXXX 100644
--- a/docs/qemu-option-trace.rst.inc
+++ b/docs/qemu-option-trace.rst.inc
@@ -XXX,XX +XXX,XX @@
 
 Specify tracing options.
 
-.. option:: [enable=]PATTERN
+``[enable=]PATTERN``
 
   Immediately enable events matching *PATTERN*
   (either event name or a globbing pattern).  This option is only
@@ -XXX,XX +XXX,XX @@ Specify tracing options.
 
   Use :option:`-trace help` to print a list of names of trace points.
 
-.. option:: events=FILE
+``events=FILE``
 
   Immediately enable events listed in *FILE*.
   The file must contain one event name (as listed in the ``trace-events-all``
@@ -XXX,XX +XXX,XX @@ Specify tracing options.
   available if QEMU has been compiled with the ``simple``, ``log`` or
   ``ftrace`` tracing backend.
 
-.. option:: file=FILE
+``file=FILE``
 
   Log output traces to *FILE*.
   This option is only available if QEMU has been compiled with
-- 
2.20.1

The randomness tests in the NPCM7xx RNG test fail intermittently
but fairly frequently. On my machine running the test in a loop:
 while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done

will fail in less than a minute with an error like:
ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs:
assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01)

(Failures have been observed on all 4 of the randomness tests,
not just first_byte_runs.)

It's not clear why these tests are failing like this, but intermittent
failures make CI and merge testing awkward, so disable running them
unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when
running the test suite, until we work out the cause.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20201102152454.8287-1-peter.maydell@linaro.org
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
---
 tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/npcm7xx_rng-test.c
+++ b/tests/qtest/npcm7xx_rng-test.c
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
 
     qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);
     qtest_add_func("npcm7xx_rng/rosel", test_rosel);
-    qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
-    qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
-    qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
-    qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
+    /*
+     * These tests fail intermittently; only run them on explicit
+     * request until we figure out why.
+     */
+    if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) {
+        qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);
+        qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);
+        qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);
+        qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);
+    }
 
     qtest_start("-machine npcm750-evb");
     ret = g_test_run();
-- 
2.20.1

Hi; this pull request has a collection of bug fixes for rc0.
The big one is the trusted firmware boot regression fix.

thanks
-- PMM

The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:

Merge tag 'linux-user-for-7.2-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221104

for you to fetch changes up to cead7fa4c06087c86c67c5ce815cc1ff0bfeac3a:

target/arm: Two fixes for secure ptw (2022-11-04 10:58:58 +0000)

----------------------------------------------------------------
target-arm queue:
 * Fix regression booting Trusted Firmware
 * Honor HCR_E2H and HCR_TGE in ats_write64()
 * Copy the entire vector in DO_ZIP
 * Fix Privileged Access Never (PAN) for aarch32
 * Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB
 * Set SCR_EL3.HXEn when direct booting kernel
 * Set SME and SVE EL3 vector lengths when direct booting kernel

----------------------------------------------------------------
Ake Koomsin (1):
      target/arm: Honor HCR_E2H and HCR_TGE in ats_write64()

Peter Maydell (3):
      hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel
      hw/arm/boot: Set SCR_EL3.HXEn when booting kernel
      target/arm: Make TLBIOS and TLBIRANGE ops trap on HCR_EL2.TTLB

Richard Henderson (2):
      target/arm: Copy the entire vector in DO_ZIP
      target/arm: Two fixes for secure ptw

Timofey Kutergin (1):
      target/arm: Fix Privileged Access Never (PAN) for aarch32

hw/arm/boot.c           |  5 ++++
 target/arm/helper.c     | 64 +++++++++++++++++++++++++++++--------------------
 target/arm/ptw.c        | 50 ++++++++++++++++++++++++++++----------
 target/arm/sve_helper.c |  4 ++--
 4 files changed, 83 insertions(+), 40 deletions(-)

When we direct boot a kernel on a CPU which emulates EL3, we need
to set up the EL3 system registers as the Linux kernel documentation
specifies:
 https://www.kernel.org/doc/Documentation/arm64/booting.rst

For SVE and SME this includes:
    - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
      kernel is executed on.
    - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
      kernel will execute on.

Although we are technically compliant with this, the "same value" we
currently use by default is the reset value of 0.  This will end up
forcing the guest kernel's SVE and SME vector length to be only the
smallest supported length.

Initialize the vector length fields to their maximum possible value,
which is 0xf. If the implementation doesn't actually support that
vector length then the effective vector length will be constrained
down to the maximum supported value at point of use.

This allows the guest to use all the vector lengths the emulated CPU
supports (by programming the _EL2 and _EL1 versions of these
registers.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221027140207.413084-2-peter.maydell@linaro.org
---
 hw/arm/boot.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     }
                     if (cpu_isar_feature(aa64_sve, cpu)) {
                         env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
+                        env->vfp.zcr_el[3] = 0xf;
                     }
                     if (cpu_isar_feature(aa64_sme, cpu)) {
                         env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
                         env->cp15.scr_el3 |= SCR_ENTP2;
+                        env->vfp.smcr_el[3] = 0xf;
                     }
                     /* AArch64 kernels never boot in secure mode */
                     assert(!info->secure_boot);
-- 
2.25.1

When we direct boot a kernel on a CPU which emulates EL3, we need to
set up the EL3 system registers as the Linux kernel documentation
specifies:
     https://www.kernel.org/doc/Documentation/arm64/booting.rst

For CPUs with FEAT_HCX support this includes:
    - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.

but we forgot to do this when implementing FEAT_HCX, which would mean
that a guest trying to access the HCRX_EL2 register would crash.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221027140207.413084-3-peter.maydell@linaro.org
---
 hw/arm/boot.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                         env->cp15.scr_el3 |= SCR_ENTP2;
                         env->vfp.smcr_el[3] = 0xf;
                     }
+                    if (cpu_isar_feature(aa64_hcx, cpu)) {
+                        env->cp15.scr_el3 |= SCR_HXEN;
+                    }
                     /* AArch64 kernels never boot in secure mode */
                     assert(!info->secure_boot);
                     /* This hook is only supported for AArch32 currently:
-- 
2.25.1

The HCR_EL2.TTLB bit is supposed to trap all EL1 execution of TLB
maintenance instructions.  However we have added new TLB insns for
FEAT_TLBIOS and FEAT_TLBIRANGE, and forgot to set their accessfn to
access_ttlb.  Add the missing accessfns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 36 ++++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
 static const ARMCPRegInfo tlbirange_reginfo[] = {
     { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
    { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
    { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1is_write },
     { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1_write },
    { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_rvae1_write },
     { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
 static const ARMCPRegInfo tlbios_reginfo[] = {
     { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vmalle1is_write },
     { .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
-      .access = PL1_W, .type = ARM_CP_NO_RAW,
+      .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
       .writefn = tlbi_aa64_vae1is_write },
     { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
-- 
2.25.1

From: Timofey Kutergin <tkutergin@gmail.com>

When we implemented the PAN support we theoretically wanted
to support it for both AArch32 and AArch64, but in practice
several bugs made it essentially unusable with an AArch32
guest. Fix all those problems:

- Use CPSR.PAN to check for PAN state in aarch32 mode
    - throw permission fault during address translation when PAN is
      enabled and kernel tries to access user acessible page
    - ignore SCTLR_XP bit for armv7 and armv8 (conflicts with SCTLR_SPAN).

Signed-off-by: Timofey Kutergin <tkutergin@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221027112619.2205229-1-tkutergin@gmail.com
[PMM: tweak commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 13 +++++++++++--
 target/arm/ptw.c    | 35 ++++++++++++++++++++++++++++++-----
 2 files changed, 41 insertions(+), 7 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 }
 #endif
 
+static bool arm_pan_enabled(CPUARMState *env)
+{
+    if (is_a64(env)) {
+        return env->pstate & PSTATE_PAN;
+    } else {
+        return env->uncached_cpsr & CPSR_PAN;
+    }
+}
+
 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
 {
     ARMMMUIdx idx;
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
         }
         break;
     case 1:
-        if (env->pstate & PSTATE_PAN) {
+        if (arm_pan_enabled(env)) {
             idx = ARMMMUIdx_E10_1_PAN;
         } else {
             idx = ARMMMUIdx_E10_1;
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
     case 2:
         /* Note that TGE does not apply at EL2.  */
         if (arm_hcr_el2_eff(env) & HCR_E2H) {
-            if (env->pstate & PSTATE_PAN) {
+            if (arm_pan_enabled(env)) {
                 idx = ARMMMUIdx_E20_2_PAN;
             } else {
                 idx = ARMMMUIdx_E20_2;
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
  * @mmu_idx:     MMU index indicating required translation regime
  * @ap:          The 3-bit access permissions (AP[2:0])
  * @domain_prot: The 2-bit domain access permissions
+ * @is_user: TRUE if accessing from PL0
  */
-static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
-                         int ap, int domain_prot)
+static int ap_to_rw_prot_is_user(CPUARMState *env, ARMMMUIdx mmu_idx,
+                         int ap, int domain_prot, bool is_user)
 {
-    bool is_user = regime_is_user(env, mmu_idx);
-
     if (domain_prot == 3) {
         return PAGE_READ | PAGE_WRITE;
     }
@@ -XXX,XX +XXX,XX @@ static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
     }
 }
 
+/*
+ * Translate section/page access permissions to page R/W protection flags
+ * @env:         CPUARMState
+ * @mmu_idx:     MMU index indicating required translation regime
+ * @ap:          The 3-bit access permissions (AP[2:0])
+ * @domain_prot: The 2-bit domain access permissions
+ */
+static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
+                         int ap, int domain_prot)
+{
+   return ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot,
+                                regime_is_user(env, mmu_idx));
+}
+
 /*
  * Translate section/page access permissions to page R/W protection flags.
  * @ap:      The 2-bit simple AP (AP[2:1])
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
     hwaddr phys_addr;
     uint32_t dacr;
     bool ns;
+    int user_prot;
 
     /* Pagetable walk.  */
     /* Lookup l1 descriptor.  */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
                 goto do_fault;
             }
             result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
+            user_prot = simple_ap_to_rw_prot_is_user(ap >> 1, 1);
         } else {
             result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
+            user_prot = ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot, 1);
         }
         if (result->f.prot && !xn) {
             result->f.prot |= PAGE_EXEC;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, S1Translate *ptw,
             fi->type = ARMFault_Permission;
             goto do_fault;
         }
+        if (regime_is_pan(env, mmu_idx) &&
+            !regime_is_user(env, mmu_idx) &&
+            user_prot &&
+            access_type != MMU_INST_FETCH) {
+            /* Privileged Access Never fault */
+            fi->type = ARMFault_Permission;
+            goto do_fault;
+        }
     }
     if (ns) {
         /* The NS bit will (as required by the architecture) have no effect if
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
     if (regime_using_lpae_format(env, mmu_idx)) {
         return get_phys_addr_lpae(env, ptw, address, access_type, false,
                                   result, fi);
-    } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
+    } else if (arm_feature(env, ARM_FEATURE_V7) ||
+               regime_sctlr(env, mmu_idx) & SCTLR_XP) {
         return get_phys_addr_v6(env, ptw, address, access_type, result, fi);
     } else {
         return get_phys_addr_v5(env, ptw, address, access_type, result, fi);
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

With odd_ofs set, we weren't copying enough data.

Fixes: 09eb6d7025d1 ("target/arm: Move sve zip high_ofs into simd_data")
Reported-by: Idan Horowitz <idan.horowitz@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221031054144.3574-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sve_helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc)       \
     /* We produce output faster than we consume input.               \
        Therefore we must be mindful of possible overlap.  */         \
     if (unlikely((vn - vd) < (uintptr_t)oprsz)) {                    \
-        vn = memcpy(&tmp_n, vn, oprsz_2);                            \
+        vn = memcpy(&tmp_n, vn, oprsz);                              \
     }                                                                \
     if (unlikely((vm - vd) < (uintptr_t)oprsz)) {                    \
-        vm = memcpy(&tmp_m, vm, oprsz_2);                            \
+        vm = memcpy(&tmp_m, vm, oprsz);                              \
     }                                                                \
     for (i = 0; i < oprsz_2; i += sizeof(TYPE)) {                    \
         *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + odd_ofs + H(i)); \
-- 
2.25.1

From: Ake Koomsin <ake@igel.co.jp>

We need to check HCR_E2H and HCR_TGE to select the right MMU index for
the correct translation regime.

To check for EL2&0 translation regime:
- For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE
- For S1E2* ops, check only HCR_E2H

Signed-off-by: Ake Koomsin <ake@igel.co.jp>
Message-id: 20221101064250.12444-1-ake@igel.co.jp
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
     MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
     ARMMMUIdx mmu_idx;
     int secure = arm_is_secure_below_el3(env);
+    uint64_t hcr_el2 = arm_hcr_el2_eff(env);
+    bool regime_e20 = (hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE);
 
     switch (ri->opc2 & 6) {
     case 0:
         switch (ri->opc1) {
         case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
             if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
-                mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
+                mmu_idx = regime_e20 ?
+                          ARMMMUIdx_E20_2_PAN : ARMMMUIdx_Stage1_E1_PAN;
             } else {
-                mmu_idx = ARMMMUIdx_Stage1_E1;
+                mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_E1;
             }
             break;
         case 4: /* AT S1E2R, AT S1E2W */
-            mmu_idx = ARMMMUIdx_E2;
+            mmu_idx = hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_E2;
             break;
         case 6: /* AT S1E3R, AT S1E3W */
             mmu_idx = ARMMMUIdx_E3;
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
         }
         break;
     case 2: /* AT S1E0R, AT S1E0W */
-        mmu_idx = ARMMMUIdx_Stage1_E0;
+        mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_Stage1_E0;
         break;
     case 4: /* AT S12E1R, AT S12E1W */
-        mmu_idx = ARMMMUIdx_E10_1;
+        mmu_idx = regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_E10_1;
         break;
     case 6: /* AT S12E0R, AT S12E0W */
-        mmu_idx = ARMMMUIdx_E10_0;
+        mmu_idx = regime_e20 ? ARMMMUIdx_E20_0 : ARMMMUIdx_E10_0;
         break;
     default:
         g_assert_not_reached();
-- 
2.25.1

From: Richard Henderson <richard.henderson@linaro.org>

Reversed the sense of non-secure in get_phys_addr_lpae,
and failed to initialize attrs.secure for ARMMMUIdx_Phys_S.

Fixes: 48da29e4 ("target/arm: Add ptw_idx to S1Translate")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1293
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
     descaddr |= (address >> (stride * (4 - level))) & indexmask;
     descaddr &= ~7ULL;
     nstable = extract32(tableattrs, 4, 1);
-    if (!nstable) {
+    if (nstable) {
         /*
          * Stage2_S -> Stage2 or Phys_S -> Phys_NS
          * Assert that the non-secure idx are even, and relative order.
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
     bool is_secure = ptw->in_secure;
     ARMMMUIdx s1_mmu_idx;
 
+    /*
+     * The page table entries may downgrade secure to non-secure, but
+     * cannot upgrade an non-secure translation regime's attributes
+     * to secure.
+     */
+    result->f.attrs.secure = is_secure;
+
     switch (mmu_idx) {
     case ARMMMUIdx_Phys_S:
     case ARMMMUIdx_Phys_NS:
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
         break;
     }
 
-    /*
-     * The page table entries may downgrade secure to non-secure, but
-     * cannot upgrade an non-secure translation regime's attributes
-     * to secure.
-     */
-    result->f.attrs.secure = is_secure;
     result->f.attrs.user = regime_is_user(env, mmu_idx);
 
     /*
-- 
2.25.1