Small pile of bug fixes for rc1. I've included my patches to get

our docs building with Sphinx 3, just for convenience...

The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96:

Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102

for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a:

tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000)

* target/arm: Fix Neon emulation bugs on big-endian hosts

* target/arm: fix handling of HCR.FB

* target/arm: fix LORID_EL1 access check

* disas/capstone: Fix monitor disassembly of >32 bytes

* hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)

* hw/arm/boot: fix SVE for EL3 direct kernel boot

* hw/display/omap_lcdc: Fix potential NULL pointer dereference

* hw/display/exynos4210_fimd: Fix potential NULL pointer dereference

* target/arm: Get correct MMU index for other-security-state

* configure: Test that gio libs from pkg-config work

* hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work

* docs: Fix building with Sphinx 3

* tests/qtest/npcm7xx_rng-test: Disable randomness tests

AlexChen (2):

hw/display/omap_lcdc: Fix potential NULL pointer dereference

hw/display/exynos4210_fimd: Fix potential NULL pointer dereference

Peter Maydell (9):

target/arm: Fix float16 pairwise Neon ops on big-endian hosts

target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts

disas/capstone: Fix monitor disassembly of >32 bytes

target/arm: Get correct MMU index for other-security-state

configure: Test that gio libs from pkg-config work

hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work

scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments

qemu-option-trace.rst.inc: Don't use option:: markup

tests/qtest/npcm7xx_rng-test: Disable randomness tests

hw/arm/smmuv3: Fix potential integer overflow (CID 1432363)

Richard Henderson (11):

target/arm: Introduce neon_full_reg_offset

target/arm: Move neon_element_offset to translate.c

target/arm: Use neon_element_offset in neon_load/store_reg

target/arm: Use neon_element_offset in vfp_reg_offset

target/arm: Add read/write_neon_element32

target/arm: Expand read/write_neon_element32 to all MemOp

target/arm: Rename neon_load_reg32 to vfp_load_reg32

target/arm: Add read/write_neon_element64

target/arm: Rename neon_load_reg64 to vfp_load_reg64

target/arm: Simplify do_long_3d and do_2scalar_long

target/arm: Improve do_prewiden_3d

Rémi Denis-Courmont (3):

target/arm: fix handling of HCR.FB

target/arm: fix LORID_EL1 access check

hw/arm/boot: fix SVE for EL3 direct kernel boot

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Use the BIT_ULL() macro to ensure we use 64-bit arithmetic.

This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN):

CID 1432363 (#1 of 1): Unintentional integer overflow:

overflow_before_widen:

Potentially overflowing expression 1 << scale with type int

(32 bits, signed) is evaluated using 32-bit arithmetic, and

then used in a context that expects an expression of type

hwaddr (64 bits, unsigned).

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Acked-by: Eric Auger <eric.auger@redhat.com>

Message-id: 20201030144617.1535064-1-philmd@redhat.com

hw/arm/smmuv3.c | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c

--- a/hw/arm/smmuv3.c

+++ b/hw/arm/smmuv3.c

@@ -XXX,XX +XXX,XX @@

*/

#include "qemu/osdep.h"

+#include "qemu/bitops.h"

#include "hw/irq.h"

#include "hw/sysbus.h"

#include "migration/vmstate.h"

@@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)

scale = CMD_SCALE(cmd);

num = CMD_NUM(cmd);

ttl = CMD_TTL(cmd);

- num_pages = (num + 1) * (1 << (scale));

+ num_pages = (num + 1) * BIT_ULL(scale);

}

if (type == SMMU_CMD_TLBI_NH_VA) {

The randomness tests in the NPCM7xx RNG test fail intermittently

but fairly frequently. On my machine running the test in a loop:

while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done

will fail in less than a minute with an error like:

ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs:

assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01)

(Failures have been observed on all 4 of the randomness tests,

not just first_byte_runs.)

It's not clear why these tests are failing like this, but intermittent

failures make CI and merge testing awkward, so disable running them

unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when

running the test suite, until we work out the cause.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Message-id: 20201102152454.8287-1-peter.maydell@linaro.org

Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>

tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++----

1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c

--- a/tests/qtest/npcm7xx_rng-test.c

+++ b/tests/qtest/npcm7xx_rng-test.c

@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)

qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable);

qtest_add_func("npcm7xx_rng/rosel", test_rosel);

- qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);

- qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);

- qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);

- qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);

+ /*

+ * These tests fail intermittently; only run them on explicit

+ * request until we figure out why.

+ */

+ if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) {

+ qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit);

+ qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs);

+ qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit);

+ qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs);

+ }

qtest_start("-machine npcm750-evb");

ret = g_test_run();

From: Richard Henderson <richard.henderson@linaro.org>

These are the only users of neon_reg_offset, so remove that.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20201030022618.785675-4-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/translate.c | 14 ++------------

1 file changed, 2 insertions(+), 12 deletions(-)

@@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg)

}

-/* Return the offset of a 32-bit piece of a NEON register.

- zero is the least significant end of the register. */

-static inline long

-neon_reg_offset (int reg, int n)

-{

- int sreg;

- sreg = reg * 2 + n;

- return vfp_reg_offset(0, sreg);

-}

-

static TCGv_i32 neon_load_reg(int reg, int pass)

{

TCGv_i32 tmp = tcg_temp_new_i32();

- tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));

+ tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));

return tmp;

}

static void neon_store_reg(int reg, int pass, TCGv_i32 var)

{

- tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));

+ tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));

Sphinx 3.2 is pickier than earlier versions about the option:: markup,

and complains about our usage in qemu-option-trace.rst:

../../docs/qemu-option-trace.rst.inc:4:Malformed option description

'[enable=]PATTERN', should look like "opt", "-opt args", "--opt args",

"/opt args" or "+opt args"

In this file, we're really trying to document the different parts of

the top-level --trace option, which qemu-nbd.rst and qemu-img.rst

have already introduced with an option:: markup. So it's not right

to use option:: here anyway. Switch to a different markup

(definition lists) which gives about the same formatted output.

(Unlike option::, this markup doesn't produce index entries; but

at the moment we don't do anything much with indexes anyway, and

in any case I think it doesn't make much sense to have individual

index entries for the sub-parts of the --trace option.)

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>

Tested-by: Stefan Hajnoczi <stefanha@redhat.com>

Message-id: 20201030174700.7204-3-peter.maydell@linaro.org

docs/qemu-option-trace.rst.inc | 6 +++---

1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc

--- a/docs/qemu-option-trace.rst.inc

+++ b/docs/qemu-option-trace.rst.inc

@@ -XXX,XX +XXX,XX @@

Specify tracing options.

-.. option:: [enable=]PATTERN

+``[enable=]PATTERN``

Immediately enable events matching *PATTERN*

(either event name or a globbing pattern). This option is only

@@ -XXX,XX +XXX,XX @@ Specify tracing options.

Use :option:`-trace help` to print a list of names of trace points.

-.. option:: events=FILE

+``events=FILE``

Immediately enable events listed in *FILE*.

The file must contain one event name (as listed in the ``trace-events-all``

@@ -XXX,XX +XXX,XX @@ Specify tracing options.

available if QEMU has been compiled with the ``simple``, ``log`` or

``ftrace`` tracing backend.

-.. option:: file=FILE

+``file=FILE``

Log output traces to *FILE*.

This option is only available if QEMU has been compiled with

In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to

armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el().

This is incorrect when the security state being queried is not the

current one, because arm_current_el() uses the current security state

to determine which of the banked CONTROL.nPRIV bits to look at.

The effect was that if (for instance) Secure state was in privileged

mode but Non-Secure was not then we would return the wrong MMU index.

The only places where we are using this function in a way that could

trigger this bug are for the stack loads during a v8M function-return

and for the instruction fetch of a v8M SG insn.

Fix the bug by expanding out the M-profile version of the

arm_current_el() logic inline so it can use the passed in secstate

rather than env->v7m.secure.

Message-id: 20201022164408.13214-1-peter.maydell@linaro.org

target/arm/m_helper.c | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,

/* Return the MMU index for a v7M CPU in the specified security state */

ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)

{

- bool priv = arm_current_el(env) != 0;

+ bool priv = arm_v7m_is_handler_mode(env) ||

+ !(env->v7m.control[secstate] & 1);

return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);

}

The helper functions for performing the udot/sdot operations against

a scalar were not using an address-swizzling macro when converting

the index of the scalar element into a pointer into the vm array.

This had no effect on little-endian hosts but meant we generated

incorrect results on big-endian hosts.

For these insns, the index is indexing over group of 4 8-bit values,

so 32 bits per indexed entity, and H4() is therefore what we want.

(For Neon the only possible input indexes are 0 and 1.)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20201028191712.4910-3-peter.maydell@linaro.org

target/arm/vec_helper.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c

--- a/target/arm/vec_helper.c

+++ b/target/arm/vec_helper.c

@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)

intptr_t index = simd_data(desc);

uint32_t *d = vd;

int8_t *n = vn;

- int8_t *m_indexed = (int8_t *)vm + index * 4;

+ int8_t *m_indexed = (int8_t *)vm + H4(index) * 4;

/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.

* Otherwise opr_sz is a multiple of 16.

@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)

intptr_t index = simd_data(desc);

uint32_t *d = vd;

uint8_t *n = vn;

- uint8_t *m_indexed = (uint8_t *)vm + index * 4;

+ uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4;

/* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.

* Otherwise opr_sz is a multiple of 16.

In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error

meant we were using the H4() address swizzler macro rather than the

H2() which is required for 2-byte data. This had no effect on

little-endian hosts but meant we put the result data into the

destination Dreg in the wrong order on big-endian hosts.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20201028191712.4910-2-peter.maydell@linaro.org

target/arm/vec_helper.c | 8 ++++----

1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c

--- a/target/arm/vec_helper.c

+++ b/target/arm/vec_helper.c

@@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t)

r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \

r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \

\

- d[H4(0)] = r0; \

- d[H4(1)] = r1; \

- d[H4(2)] = r2; \

- d[H4(3)] = r3; \

+ d[H2(0)] = r0; \

+ d[H2(1)] = r1; \

+ d[H2(2)] = r2; \

+ d[H2(3)] = r3; \

}

DO_NEON_PAIRWISE(neon_padd, add)

From: Richard Henderson <richard.henderson@linaro.org>

This function makes it clear that we're talking about the whole

register, and not the 32-bit piece at index 0. This fixes a bug

when running on a big-endian host.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20201030022618.785675-2-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/translate.c | 8 ++++++

target/arm/translate-neon.c.inc | 44 ++++++++++++++++-----------------

target/arm/translate-vfp.c.inc | 2 +-

3 files changed, 31 insertions(+), 23 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)

unallocated_encoding(s);

+/*

+ * Return the offset of a "full" NEON Dreg.

+ */

+static long neon_full_reg_offset(unsigned reg)

+ return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);

static inline long vfp_reg_offset(bool dp, unsigned reg)

if (dp) {

diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-neon.c.inc

+++ b/target/arm/translate-neon.c.inc

@@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size)

ofs ^= 8 - element_size;

}

#endif

- return neon_reg_offset(reg, 0) + ofs;

+ return neon_full_reg_offset(reg) + ofs;

}

static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop)

@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)

* We cannot write 16 bytes at once because the

* destination is unaligned.

*/

- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),

+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),

8, 8, tmp);

- tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),

- neon_reg_offset(vd, 0), 8, 8);

+ tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1),

+ neon_full_reg_offset(vd), 8, 8);

} else {

- tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),

+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd),

vec_size, vec_size, tmp);

}

tcg_gen_addi_i32(addr, addr, 1 << size);

@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)

static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)

{

int vec_size = a->q ? 16 : 8;

- int rd_ofs = neon_reg_offset(a->vd, 0);

- int rn_ofs = neon_reg_offset(a->vn, 0);

- int rm_ofs = neon_reg_offset(a->vm, 0);

+ int rd_ofs = neon_full_reg_offset(a->vd);

+ int rn_ofs = neon_full_reg_offset(a->vn);

+ int rm_ofs = neon_full_reg_offset(a->vm);

if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {

return false;

@@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)

{

/* Handle a 2-reg-shift insn which can be vectorized. */

int vec_size = a->q ? 16 : 8;

- int rd_ofs = neon_reg_offset(a->vd, 0);

- int rm_ofs = neon_reg_offset(a->vm, 0);

+ int rd_ofs = neon_full_reg_offset(a->vd);

+ int rm_ofs = neon_full_reg_offset(a->vm);

if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {

return false;

@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,

{

/* FP operations in 2-reg-and-shift group */

int vec_size = a->q ? 16 : 8;

- int rd_ofs = neon_reg_offset(a->vd, 0);

- int rm_ofs = neon_reg_offset(a->vm, 0);

+ int rd_ofs = neon_full_reg_offset(a->vd);

+ int rm_ofs = neon_full_reg_offset(a->vm);

TCGv_ptr fpst;

if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {

@@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,

return true;

}

- reg_ofs = neon_reg_offset(a->vd, 0);

+ reg_ofs = neon_full_reg_offset(a->vd);

vec_size = a->q ? 16 : 8;

imm = asimd_imm_const(a->imm, a->cmode, a->op);

@@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a)

return true;

}

- tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0),

- neon_reg_offset(a->vn, 0),

- neon_reg_offset(a->vm, 0),

+ tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd),

+ neon_full_reg_offset(a->vn),

+ neon_full_reg_offset(a->vm),

16, 16, 0, fn_gvec);

return true;

}

@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,

{

/* Two registers and a scalar, using gvec */

int vec_size = a->q ? 16 : 8;

- int rd_ofs = neon_reg_offset(a->vd, 0);

- int rn_ofs = neon_reg_offset(a->vn, 0);

+ int rd_ofs = neon_full_reg_offset(a->vd);

+ int rn_ofs = neon_full_reg_offset(a->vn);

int rm_ofs;

int idx;

TCGv_ptr fpstatus;

@@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a,

/* a->vm is M:Vm, which encodes both register and index */

idx = extract32(a->vm, a->size + 2, 2);

a->vm = extract32(a->vm, 0, a->size + 2);

- rm_ofs = neon_reg_offset(a->vm, 0);

+ rm_ofs = neon_full_reg_offset(a->vm);

fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD);

tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus,

@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a)

return true;

}

- tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0),

+ tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd),

neon_element_offset(a->vm, a->index, a->size),

a->q ? 16 : 8, a->q ? 16 : 8);

return true;

@@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a)

static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn)

{

int vec_size = a->q ? 16 : 8;

- int rd_ofs = neon_reg_offset(a->vd, 0);

- int rm_ofs = neon_reg_offset(a->vm, 0);

+ int rd_ofs = neon_full_reg_offset(a->vd);

+ int rm_ofs = neon_full_reg_offset(a->vm);

if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {

return false;

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-vfp.c.inc

+++ b/target/arm/translate-vfp.c.inc

@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)

}

tmp = load_reg(s, a->rt);

- tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0),

+ tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn),

vec_size, vec_size, tmp);

tcg_temp_free_i32(tmp);

On some hosts (eg Ubuntu Bionic) pkg-config returns a set of

libraries for gio-2.0 which don't actually work when compiling

statically. (Specifically, the returned library string includes

-lmount, but not -lblkid which -lmount depends upon, so linking

fails due to missing symbols.)

Check that the libraries work, and don't enable gio if they don't,

in the same way we do for gnutls.

configure | 10 +++++++++-

1 file changed, 9 insertions(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then

if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then

- gio=yes

gio_cflags=$($pkg_config --cflags gio-2.0)

gio_libs=$($pkg_config --libs gio-2.0)

gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0)

if [ ! -x "$gdbus_codegen" ]; then

gdbus_codegen=

fi

+ # Check that the libraries actually work -- Ubuntu 18.04 ships

+ # with pkg-config --static --libs data for gio-2.0 that is missing

+ # -lblkid and will give a link error.

+ write_c_skeleton

+ if compile_prog "" "gio_libs" ; then

+ gio=yes

+ else

+ gio=no

+ fi

else

gio=no

fi

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

Secure mode is not exempted from checking SCR_EL3.TLOR, and in the

future HCR_EL2.TLOR when S-EL2 is enabled.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

target/arm/helper.c | 19 +++++--------------

1 file changed, 5 insertions(+), 14 deletions(-)

@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)

#endif

/* Shared logic between LORID and the rest of the LOR* registers.

- * Secure state has already been delt with.

+ * Secure state exclusion has already been dealt with.

*/

-static CPAccessResult access_lor_ns(CPUARMState *env)

+static CPAccessResult access_lor_ns(CPUARMState *env,

+ const ARMCPRegInfo *ri, bool isread)

int el = arm_current_el(env);

@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env)

return CP_ACCESS_OK;

}

-static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,

- bool isread)

-{

- if (arm_is_secure_below_el3(env)) {

- /* Access ok in secure mode. */

- return CP_ACCESS_OK;

- }

- return access_lor_ns(env);

-}

-

static CPAccessResult access_lor_other(CPUARMState *env,

const ARMCPRegInfo *ri, bool isread)

{

@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env,

/* Access denied in secure mode. */

return CP_ACCESS_TRAP;

}

- return access_lor_ns(env);

+ return access_lor_ns(env, ri, isread);

}

/*

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = {

.type = ARM_CP_CONST, .resetvalue = 0 },

{ .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,

.opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,

- .access = PL1_R, .accessfn = access_lorid,

+ .access = PL1_R, .accessfn = access_lor_ns,

.type = ARM_CP_CONST, .resetvalue = 0 },

REGINFO_SENTINEL

};

This seems a bit more readable than using offsetof CPU_DoubleU.

target/arm/translate.c | 13 ++++---------

1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size)

return neon_full_reg_offset(reg) + ofs;

-static inline long vfp_reg_offset(bool dp, unsigned reg)

+/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */

+static long vfp_reg_offset(bool dp, unsigned reg)

if (dp) {

- return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]);

+ return neon_element_offset(reg, 0, MO_64);

} else {

- long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]);

- if (reg & 1) {

- ofs += offsetof(CPU_DoubleU, l.upper);

- } else {

- ofs += offsetof(CPU_DoubleU, l.lower);

- }

- return ofs;

+ return neon_element_offset(reg >> 1, reg & 1, MO_32);

Model these off the aa64 read/write_vec_element functions.

Use it within translate-neon.c.inc. The new functions do

not allocate or free temps, so this rearranges the calling

code a bit.

target/arm/translate.c | 26 ++++

target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------

2 files changed, 183 insertions(+), 99 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg)

tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg));

+static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size)

+ long off = neon_element_offset(reg, ele, size);

+ switch (size) {

+ case MO_32:

+ tcg_gen_ld_i32(dest, cpu_env, off);

+ break;

+ default:

+ g_assert_not_reached();

+static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size)