1 | Small pile of bug fixes for rc1. I've included my patches to get | 1 | The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df: |
---|---|---|---|
2 | our docs building with Sphinx 3, just for convenience... | ||
3 | 2 | ||
4 | -- PMM | 3 | Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100) |
5 | |||
6 | The following changes since commit b149dea55cce97cb226683d06af61984a1c11e96: | ||
7 | |||
8 | Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201102' into staging (2020-11-02 10:57:48 +0000) | ||
9 | 4 | ||
10 | are available in the Git repository at: | 5 | are available in the Git repository at: |
11 | 6 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201102 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702 |
13 | 8 | ||
14 | for you to fetch changes up to ffb4fbf90a2f63c9cb33e4bb9f854c79bf04ca4a: | 9 | for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8: |
15 | 10 | ||
16 | tests/qtest/npcm7xx_rng-test: Disable randomness tests (2020-11-02 16:52:18 +0000) | 11 | target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100) |
17 | 12 | ||
18 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
19 | target-arm queue: | 14 | target-arm queue: |
20 | * target/arm: Fix Neon emulation bugs on big-endian hosts | 15 | * more MVE instructions |
21 | * target/arm: fix handling of HCR.FB | 16 | * hw/gpio/gpio_pwr: use shutdown function for reboot |
22 | * target/arm: fix LORID_EL1 access check | 17 | * target/arm: Check NaN mode before silencing NaN |
23 | * disas/capstone: Fix monitor disassembly of >32 bytes | 18 | * tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine |
24 | * hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) | 19 | * hw/arm: Add basic power management to raspi. |
25 | * hw/arm/boot: fix SVE for EL3 direct kernel boot | 20 | * docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc |
26 | * hw/display/omap_lcdc: Fix potential NULL pointer dereference | ||
27 | * hw/display/exynos4210_fimd: Fix potential NULL pointer dereference | ||
28 | * target/arm: Get correct MMU index for other-security-state | ||
29 | * configure: Test that gio libs from pkg-config work | ||
30 | * hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work | ||
31 | * docs: Fix building with Sphinx 3 | ||
32 | * tests/qtest/npcm7xx_rng-test: Disable randomness tests | ||
33 | 21 | ||
34 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
35 | AlexChen (2): | 23 | Joe Komlodi (1): |
36 | hw/display/omap_lcdc: Fix potential NULL pointer dereference | 24 | target/arm: Check NaN mode before silencing NaN |
37 | hw/display/exynos4210_fimd: Fix potential NULL pointer dereference | ||
38 | 25 | ||
39 | Peter Maydell (9): | 26 | Maxim Uvarov (1): |
40 | target/arm: Fix float16 pairwise Neon ops on big-endian hosts | 27 | hw/gpio/gpio_pwr: use shutdown function for reboot |
41 | target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts | 28 | |
42 | disas/capstone: Fix monitor disassembly of >32 bytes | 29 | Nolan Leake (1): |
43 | target/arm: Get correct MMU index for other-security-state | 30 | hw/arm: Add basic power management to raspi. |
44 | configure: Test that gio libs from pkg-config work | 31 | |
45 | hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work | 32 | Patrick Venture (2): |
46 | scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments | 33 | docs/system/arm: Add quanta-q7l1-bmc reference |
47 | qemu-option-trace.rst.inc: Don't use option:: markup | 34 | docs/system/arm: Add quanta-gbs-bmc reference |
48 | tests/qtest/npcm7xx_rng-test: Disable randomness tests | 35 | |
36 | Peter Maydell (18): | ||
37 | target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation | ||
38 | target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH | ||
39 | target/arm: Make asimd_imm_const() public | ||
40 | target/arm: Use asimd_imm_const for A64 decode | ||
41 | target/arm: Use dup_const() instead of bitfield_replicate() | ||
42 | target/arm: Implement MVE logical immediate insns | ||
43 | target/arm: Implement MVE vector shift left by immediate insns | ||
44 | target/arm: Implement MVE vector shift right by immediate insns | ||
45 | target/arm: Implement MVE VSHLL | ||
46 | target/arm: Implement MVE VSRI, VSLI | ||
47 | target/arm: Implement MVE VSHRN, VRSHRN | ||
48 | target/arm: Implement MVE saturating narrowing shifts | ||
49 | target/arm: Implement MVE VSHLC | ||
50 | target/arm: Implement MVE VADDLV | ||
51 | target/arm: Implement MVE long shifts by immediate | ||
52 | target/arm: Implement MVE long shifts by register | ||
53 | target/arm: Implement MVE shifts by immediate | ||
54 | target/arm: Implement MVE shifts by register | ||
49 | 55 | ||
50 | Philippe Mathieu-Daudé (1): | 56 | Philippe Mathieu-Daudé (1): |
51 | hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) | 57 | tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine |
52 | 58 | ||
53 | Richard Henderson (11): | 59 | docs/system/arm/aspeed.rst | 1 + |
54 | target/arm: Introduce neon_full_reg_offset | 60 | docs/system/arm/nuvoton.rst | 5 +- |
55 | target/arm: Move neon_element_offset to translate.c | 61 | include/hw/arm/bcm2835_peripherals.h | 3 +- |
56 | target/arm: Use neon_element_offset in neon_load/store_reg | 62 | include/hw/misc/bcm2835_powermgt.h | 29 ++ |
57 | target/arm: Use neon_element_offset in vfp_reg_offset | 63 | target/arm/helper-mve.h | 108 +++++++ |
58 | target/arm: Add read/write_neon_element32 | 64 | target/arm/translate.h | 41 +++ |
59 | target/arm: Expand read/write_neon_element32 to all MemOp | 65 | target/arm/mve.decode | 177 ++++++++++- |
60 | target/arm: Rename neon_load_reg32 to vfp_load_reg32 | 66 | target/arm/t32.decode | 71 ++++- |
61 | target/arm: Add read/write_neon_element64 | 67 | hw/arm/bcm2835_peripherals.c | 13 +- |
62 | target/arm: Rename neon_load_reg64 to vfp_load_reg64 | 68 | hw/gpio/gpio_pwr.c | 2 +- |
63 | target/arm: Simplify do_long_3d and do_2scalar_long | 69 | hw/misc/bcm2835_powermgt.c | 160 ++++++++++ |
64 | target/arm: Improve do_prewiden_3d | 70 | target/arm/helper-a64.c | 12 +- |
71 | target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++-- | ||
72 | target/arm/translate-a64.c | 86 +----- | ||
73 | target/arm/translate-mve.c | 261 +++++++++++++++- | ||
74 | target/arm/translate-neon.c | 81 ----- | ||
75 | target/arm/translate.c | 327 +++++++++++++++++++- | ||
76 | target/arm/vfp_helper.c | 24 +- | ||
77 | hw/misc/meson.build | 1 + | ||
78 | tests/acceptance/boot_linux_console.py | 43 +++ | ||
79 | 20 files changed, 1760 insertions(+), 209 deletions(-) | ||
80 | create mode 100644 include/hw/misc/bcm2835_powermgt.h | ||
81 | create mode 100644 hw/misc/bcm2835_powermgt.c | ||
65 | 82 | ||
66 | Rémi Denis-Courmont (3): | ||
67 | target/arm: fix handling of HCR.FB | ||
68 | target/arm: fix LORID_EL1 access check | ||
69 | hw/arm/boot: fix SVE for EL3 direct kernel boot | ||
70 | |||
71 | docs/qemu-option-trace.rst.inc | 6 +- | ||
72 | configure | 10 +- | ||
73 | include/hw/intc/arm_gicv3_common.h | 1 - | ||
74 | disas/capstone.c | 2 +- | ||
75 | hw/arm/boot.c | 3 + | ||
76 | hw/arm/smmuv3.c | 3 +- | ||
77 | hw/display/exynos4210_fimd.c | 4 +- | ||
78 | hw/display/omap_lcdc.c | 10 +- | ||
79 | hw/intc/arm_gicv3_cpuif.c | 5 +- | ||
80 | target/arm/helper.c | 24 +- | ||
81 | target/arm/m_helper.c | 3 +- | ||
82 | target/arm/translate.c | 153 +++++++++--- | ||
83 | target/arm/vec_helper.c | 12 +- | ||
84 | tests/qtest/npcm7xx_rng-test.c | 14 +- | ||
85 | scripts/kernel-doc | 18 +- | ||
86 | target/arm/translate-neon.c.inc | 472 ++++++++++++++++++++----------------- | ||
87 | target/arm/translate-vfp.c.inc | 341 +++++++++++---------------- | ||
88 | 17 files changed, 588 insertions(+), 493 deletions(-) | ||
89 | diff view generated by jsdifflib |
1 | From: AlexChen <alex.chen@huawei.com> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | In exynos4210_fimd_update(), the pointer s is dereferinced before | 3 | Adds a line-item reference to the supported quanta-q71l-bmc aspeed |
4 | being check if it is valid, which may lead to NULL pointer dereference. | 4 | entry. |
5 | So move the assignment to global_width after checking that the s is valid. | ||
6 | 5 | ||
7 | Reported-by: Euler Robot <euler.robot@huawei.com> | 6 | Signed-off-by: Patrick Venture <venture@google.com> |
8 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 8 | Message-id: 20210615192848.1065297-2-venture@google.com |
10 | Message-id: 5F9F8D88.9030102@huawei.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 10 | --- |
13 | hw/display/exynos4210_fimd.c | 4 +++- | 11 | docs/system/arm/aspeed.rst | 1 + |
14 | 1 file changed, 3 insertions(+), 1 deletion(-) | 12 | 1 file changed, 1 insertion(+) |
15 | 13 | ||
16 | diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/display/exynos4210_fimd.c | 16 | --- a/docs/system/arm/aspeed.rst |
19 | +++ b/hw/display/exynos4210_fimd.c | 17 | +++ b/docs/system/arm/aspeed.rst |
20 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_fimd_update(void *opaque) | 18 | @@ -XXX,XX +XXX,XX @@ etc. |
21 | bool blend = false; | 19 | AST2400 SoC based machines : |
22 | uint8_t *host_fb_addr; | 20 | |
23 | bool is_dirty = false; | 21 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC |
24 | - const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; | 22 | +- ``quanta-q71l-bmc`` OpenBMC Quanta BMC |
25 | + int global_width; | 23 | |
26 | 24 | AST2500 SoC based machines : | |
27 | if (!s || !s->console || !s->enabled || | ||
28 | surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) { | ||
29 | return; | ||
30 | } | ||
31 | + | ||
32 | + global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; | ||
33 | exynos4210_update_resolution(s); | ||
34 | surface = qemu_console_surface(s->console); | ||
35 | 25 | ||
36 | -- | 26 | -- |
37 | 2.20.1 | 27 | 2.20.1 |
38 | 28 | ||
39 | 29 | diff view generated by jsdifflib |
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so | 3 | Add line item reference to quanta-gbs-bmc machine. |
4 | that SVE will not trap to EL3. | ||
5 | 4 | ||
6 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 5 | Signed-off-by: Patrick Venture <venture@google.com> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
8 | Message-id: 20201030151541.11976-1-remi@remlab.net | 7 | Message-id: 20210615192848.1065297-3-venture@google.com |
8 | [PMM: fixed underline Sphinx warning] | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | hw/arm/boot.c | 3 +++ | 11 | docs/system/arm/nuvoton.rst | 5 +++-- |
12 | 1 file changed, 3 insertions(+) | 12 | 1 file changed, 3 insertions(+), 2 deletions(-) |
13 | 13 | ||
14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/boot.c | 16 | --- a/docs/system/arm/nuvoton.rst |
17 | +++ b/hw/arm/boot.c | 17 | +++ b/docs/system/arm/nuvoton.rst |
18 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) | 18 | @@ -XXX,XX +XXX,XX @@ |
19 | if (cpu_isar_feature(aa64_mte, cpu)) { | 19 | -Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``) |
20 | env->cp15.scr_el3 |= SCR_ATA; | 20 | -===================================================== |
21 | } | 21 | +Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``) |
22 | + if (cpu_isar_feature(aa64_sve, cpu)) { | 22 | +================================================================ |
23 | + env->cp15.cptr_el[3] |= CPTR_EZ; | 23 | |
24 | + } | 24 | The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are |
25 | /* AArch64 kernels never boot in secure mode */ | 25 | designed to be used as Baseboard Management Controllers (BMCs) in various |
26 | assert(!info->secure_boot); | 26 | @@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip : |
27 | /* This hook is only supported for AArch32 currently: | 27 | The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and |
28 | Hyperscale applications. The following machines are based on this chip : | ||
29 | |||
30 | +- ``quanta-gbs-bmc`` Quanta GBS server BMC | ||
31 | - ``quanta-gsj`` Quanta GSJ server BMC | ||
32 | |||
33 | There are also two more SoCs, NPCM710 and NPCM705, which are single-core | ||
28 | -- | 34 | -- |
29 | 2.20.1 | 35 | 2.20.1 |
30 | 36 | ||
31 | 37 | diff view generated by jsdifflib |
1 | From: AlexChen <alex.chen@huawei.com> | 1 | From: Nolan Leake <nolan@sigbus.net> |
---|---|---|---|
2 | 2 | ||
3 | In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before | 3 | This is just enough to make reboot and poweroff work. Works for |
4 | being check if it is valid, which may lead to NULL pointer dereference. | 4 | linux, u-boot, and the arm trusted firmware. Not tested, but should |
5 | So move the assignment to surface after checking that the omap_lcd is valid | 5 | work for plan9, and bare-metal/hobby OSes, since they seem to generally |
6 | and move surface_bits_per_pixel(surface) to after the surface assignment. | 6 | do what linux does for reset. |
7 | 7 | ||
8 | Reported-by: Euler Robot <euler.robot@huawei.com> | 8 | The watchdog timer functionality is not yet implemented. |
9 | Signed-off-by: AlexChen <alex.chen@huawei.com> | 9 | |
10 | Message-id: 5F9CDB8A.9000001@huawei.com | 10 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64 |
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Nolan Leake <nolan@sigbus.net> |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 20210625210209.1870217-1-nolan@sigbus.net | ||
15 | [PMM: tweaked commit title; fixed region size to 0x200; | ||
16 | moved header file to include/] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 18 | --- |
14 | hw/display/omap_lcdc.c | 10 +++++++--- | 19 | include/hw/arm/bcm2835_peripherals.h | 3 +- |
15 | 1 file changed, 7 insertions(+), 3 deletions(-) | 20 | include/hw/misc/bcm2835_powermgt.h | 29 +++++ |
16 | 21 | hw/arm/bcm2835_peripherals.c | 13 ++- | |
17 | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c | 22 | hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++ |
23 | hw/misc/meson.build | 1 + | ||
24 | 5 files changed, 204 insertions(+), 2 deletions(-) | ||
25 | create mode 100644 include/hw/misc/bcm2835_powermgt.h | ||
26 | create mode 100644 hw/misc/bcm2835_powermgt.c | ||
27 | |||
28 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/display/omap_lcdc.c | 30 | --- a/include/hw/arm/bcm2835_peripherals.h |
20 | +++ b/hw/display/omap_lcdc.c | 31 | +++ b/include/hw/arm/bcm2835_peripherals.h |
21 | @@ -XXX,XX +XXX,XX @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s) | 32 | @@ -XXX,XX +XXX,XX @@ |
22 | static void omap_update_display(void *opaque) | 33 | #include "hw/misc/bcm2835_mphi.h" |
23 | { | 34 | #include "hw/misc/bcm2835_thermal.h" |
24 | struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque; | 35 | #include "hw/misc/bcm2835_cprman.h" |
25 | - DisplaySurface *surface = qemu_console_surface(omap_lcd->con); | 36 | +#include "hw/misc/bcm2835_powermgt.h" |
26 | + DisplaySurface *surface; | 37 | #include "hw/sd/sdhci.h" |
27 | draw_line_func draw_line; | 38 | #include "hw/sd/bcm2835_sdhost.h" |
28 | int size, height, first, last; | 39 | #include "hw/gpio/bcm2835_gpio.h" |
29 | int width, linesize, step, bpp, frame_offset; | 40 | @@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState { |
30 | hwaddr frame_base; | 41 | BCM2835MphiState mphi; |
31 | 42 | UnimplementedDeviceState txp; | |
32 | - if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable || | 43 | UnimplementedDeviceState armtmr; |
33 | - !surface_bits_per_pixel(surface)) { | 44 | - UnimplementedDeviceState powermgt; |
34 | + if (!omap_lcd || omap_lcd->plm == 1 || !omap_lcd->enable) { | 45 | + BCM2835PowerMgtState powermgt; |
46 | BCM2835CprmanState cprman; | ||
47 | PL011State uart0; | ||
48 | BCM2835AuxState aux; | ||
49 | diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h | ||
50 | new file mode 100644 | ||
51 | index XXXXXXX..XXXXXXX | ||
52 | --- /dev/null | ||
53 | +++ b/include/hw/misc/bcm2835_powermgt.h | ||
54 | @@ -XXX,XX +XXX,XX @@ | ||
55 | +/* | ||
56 | + * BCM2835 Power Management emulation | ||
57 | + * | ||
58 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> | ||
59 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> | ||
60 | + * | ||
61 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
62 | + * See the COPYING file in the top-level directory. | ||
63 | + */ | ||
64 | + | ||
65 | +#ifndef BCM2835_POWERMGT_H | ||
66 | +#define BCM2835_POWERMGT_H | ||
67 | + | ||
68 | +#include "hw/sysbus.h" | ||
69 | +#include "qom/object.h" | ||
70 | + | ||
71 | +#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt" | ||
72 | +OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT) | ||
73 | + | ||
74 | +struct BCM2835PowerMgtState { | ||
75 | + SysBusDevice busdev; | ||
76 | + MemoryRegion iomem; | ||
77 | + | ||
78 | + uint32_t rstc; | ||
79 | + uint32_t rsts; | ||
80 | + uint32_t wdog; | ||
81 | +}; | ||
82 | + | ||
83 | +#endif | ||
84 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/arm/bcm2835_peripherals.c | ||
87 | +++ b/hw/arm/bcm2835_peripherals.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj) | ||
89 | |||
90 | object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", | ||
91 | OBJECT(&s->gpu_bus_mr)); | ||
92 | + | ||
93 | + /* Power Management */ | ||
94 | + object_initialize_child(obj, "powermgt", &s->powermgt, | ||
95 | + TYPE_BCM2835_POWERMGT); | ||
96 | } | ||
97 | |||
98 | static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
99 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
100 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | ||
101 | INTERRUPT_USB)); | ||
102 | |||
103 | + /* Power Management */ | ||
104 | + if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) { | ||
35 | + return; | 105 | + return; |
36 | + } | 106 | + } |
37 | + | 107 | + |
38 | + surface = qemu_console_surface(omap_lcd->con); | 108 | + memory_region_add_subregion(&s->peri_mr, PM_OFFSET, |
39 | + if (!surface_bits_per_pixel(surface)) { | 109 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0)); |
40 | return; | 110 | + |
41 | } | 111 | create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000); |
42 | 112 | create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); | |
113 | - create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); | ||
114 | create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); | ||
115 | create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); | ||
116 | create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); | ||
117 | diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c | ||
118 | new file mode 100644 | ||
119 | index XXXXXXX..XXXXXXX | ||
120 | --- /dev/null | ||
121 | +++ b/hw/misc/bcm2835_powermgt.c | ||
122 | @@ -XXX,XX +XXX,XX @@ | ||
123 | +/* | ||
124 | + * BCM2835 Power Management emulation | ||
125 | + * | ||
126 | + * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com> | ||
127 | + * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net> | ||
128 | + * | ||
129 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
130 | + * See the COPYING file in the top-level directory. | ||
131 | + */ | ||
132 | + | ||
133 | +#include "qemu/osdep.h" | ||
134 | +#include "qemu/log.h" | ||
135 | +#include "qemu/module.h" | ||
136 | +#include "hw/misc/bcm2835_powermgt.h" | ||
137 | +#include "migration/vmstate.h" | ||
138 | +#include "sysemu/runstate.h" | ||
139 | + | ||
140 | +#define PASSWORD 0x5a000000 | ||
141 | +#define PASSWORD_MASK 0xff000000 | ||
142 | + | ||
143 | +#define R_RSTC 0x1c | ||
144 | +#define V_RSTC_RESET 0x20 | ||
145 | +#define R_RSTS 0x20 | ||
146 | +#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */ | ||
147 | +#define R_WDOG 0x24 | ||
148 | + | ||
149 | +static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset, | ||
150 | + unsigned size) | ||
151 | +{ | ||
152 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | ||
153 | + uint32_t res = 0; | ||
154 | + | ||
155 | + switch (offset) { | ||
156 | + case R_RSTC: | ||
157 | + res = s->rstc; | ||
158 | + break; | ||
159 | + case R_RSTS: | ||
160 | + res = s->rsts; | ||
161 | + break; | ||
162 | + case R_WDOG: | ||
163 | + res = s->wdog; | ||
164 | + break; | ||
165 | + | ||
166 | + default: | ||
167 | + qemu_log_mask(LOG_UNIMP, | ||
168 | + "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx | ||
169 | + "\n", offset); | ||
170 | + res = 0; | ||
171 | + break; | ||
172 | + } | ||
173 | + | ||
174 | + return res; | ||
175 | +} | ||
176 | + | ||
177 | +static void bcm2835_powermgt_write(void *opaque, hwaddr offset, | ||
178 | + uint64_t value, unsigned size) | ||
179 | +{ | ||
180 | + BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque; | ||
181 | + | ||
182 | + if ((value & PASSWORD_MASK) != PASSWORD) { | ||
183 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
184 | + "bcm2835_powermgt_write: Bad password 0x%"PRIx64 | ||
185 | + " at offset 0x%08"HWADDR_PRIx"\n", | ||
186 | + value, offset); | ||
187 | + return; | ||
188 | + } | ||
189 | + | ||
190 | + value = value & ~PASSWORD_MASK; | ||
191 | + | ||
192 | + switch (offset) { | ||
193 | + case R_RSTC: | ||
194 | + s->rstc = value; | ||
195 | + if (value & V_RSTC_RESET) { | ||
196 | + if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) { | ||
197 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); | ||
198 | + } else { | ||
199 | + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); | ||
200 | + } | ||
201 | + } | ||
202 | + break; | ||
203 | + case R_RSTS: | ||
204 | + qemu_log_mask(LOG_UNIMP, | ||
205 | + "bcm2835_powermgt_write: RSTS\n"); | ||
206 | + s->rsts = value; | ||
207 | + break; | ||
208 | + case R_WDOG: | ||
209 | + qemu_log_mask(LOG_UNIMP, | ||
210 | + "bcm2835_powermgt_write: WDOG\n"); | ||
211 | + s->wdog = value; | ||
212 | + break; | ||
213 | + | ||
214 | + default: | ||
215 | + qemu_log_mask(LOG_UNIMP, | ||
216 | + "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx | ||
217 | + "\n", offset); | ||
218 | + break; | ||
219 | + } | ||
220 | +} | ||
221 | + | ||
222 | +static const MemoryRegionOps bcm2835_powermgt_ops = { | ||
223 | + .read = bcm2835_powermgt_read, | ||
224 | + .write = bcm2835_powermgt_write, | ||
225 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
226 | + .impl.min_access_size = 4, | ||
227 | + .impl.max_access_size = 4, | ||
228 | +}; | ||
229 | + | ||
230 | +static const VMStateDescription vmstate_bcm2835_powermgt = { | ||
231 | + .name = TYPE_BCM2835_POWERMGT, | ||
232 | + .version_id = 1, | ||
233 | + .minimum_version_id = 1, | ||
234 | + .fields = (VMStateField[]) { | ||
235 | + VMSTATE_UINT32(rstc, BCM2835PowerMgtState), | ||
236 | + VMSTATE_UINT32(rsts, BCM2835PowerMgtState), | ||
237 | + VMSTATE_UINT32(wdog, BCM2835PowerMgtState), | ||
238 | + VMSTATE_END_OF_LIST() | ||
239 | + } | ||
240 | +}; | ||
241 | + | ||
242 | +static void bcm2835_powermgt_init(Object *obj) | ||
243 | +{ | ||
244 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj); | ||
245 | + | ||
246 | + memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s, | ||
247 | + TYPE_BCM2835_POWERMGT, 0x200); | ||
248 | + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); | ||
249 | +} | ||
250 | + | ||
251 | +static void bcm2835_powermgt_reset(DeviceState *dev) | ||
252 | +{ | ||
253 | + BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev); | ||
254 | + | ||
255 | + /* https://elinux.org/BCM2835_registers#PM */ | ||
256 | + s->rstc = 0x00000102; | ||
257 | + s->rsts = 0x00001000; | ||
258 | + s->wdog = 0x00000000; | ||
259 | +} | ||
260 | + | ||
261 | +static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data) | ||
262 | +{ | ||
263 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
264 | + | ||
265 | + dc->reset = bcm2835_powermgt_reset; | ||
266 | + dc->vmsd = &vmstate_bcm2835_powermgt; | ||
267 | +} | ||
268 | + | ||
269 | +static TypeInfo bcm2835_powermgt_info = { | ||
270 | + .name = TYPE_BCM2835_POWERMGT, | ||
271 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
272 | + .instance_size = sizeof(BCM2835PowerMgtState), | ||
273 | + .class_init = bcm2835_powermgt_class_init, | ||
274 | + .instance_init = bcm2835_powermgt_init, | ||
275 | +}; | ||
276 | + | ||
277 | +static void bcm2835_powermgt_register_types(void) | ||
278 | +{ | ||
279 | + type_register_static(&bcm2835_powermgt_info); | ||
280 | +} | ||
281 | + | ||
282 | +type_init(bcm2835_powermgt_register_types) | ||
283 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
284 | index XXXXXXX..XXXXXXX 100644 | ||
285 | --- a/hw/misc/meson.build | ||
286 | +++ b/hw/misc/meson.build | ||
287 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( | ||
288 | 'bcm2835_rng.c', | ||
289 | 'bcm2835_thermal.c', | ||
290 | 'bcm2835_cprman.c', | ||
291 | + 'bcm2835_powermgt.c', | ||
292 | )) | ||
293 | softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) | ||
294 | softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c')) | ||
43 | -- | 295 | -- |
44 | 2.20.1 | 296 | 2.20.1 |
45 | 297 | ||
46 | 298 | diff view generated by jsdifflib |
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Secure mode is not exempted from checking SCR_EL3.TLOR, and in the | 3 | Add a test booting and quickly shutdown a raspi2 machine, |
4 | future HCR_EL2.TLOR when S-EL2 is enabled. | 4 | to test the power management model: |
5 | 5 | ||
6 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 6 | (1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd: |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | console: [ 0.000000] Booting Linux on physical CPU 0xf00 |
8 | console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019 | ||
9 | console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d | ||
10 | console: [ 0.000000] CPU: div instructions available: patching division code | ||
11 | console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache | ||
12 | console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B | ||
13 | ... | ||
14 | console: Boot successful. | ||
15 | console: cat /proc/cpuinfo | ||
16 | console: / # cat /proc/cpuinfo | ||
17 | ... | ||
18 | console: processor : 3 | ||
19 | console: model name : ARMv7 Processor rev 5 (v7l) | ||
20 | console: BogoMIPS : 125.00 | ||
21 | console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm | ||
22 | console: CPU implementer : 0x41 | ||
23 | console: CPU architecture: 7 | ||
24 | console: CPU variant : 0x0 | ||
25 | console: CPU part : 0xc07 | ||
26 | console: CPU revision : 5 | ||
27 | console: Hardware : BCM2835 | ||
28 | console: Revision : 0000 | ||
29 | console: Serial : 0000000000000000 | ||
30 | console: cat /proc/iomem | ||
31 | console: / # cat /proc/iomem | ||
32 | console: 00000000-3bffffff : System RAM | ||
33 | console: 00008000-00afffff : Kernel code | ||
34 | console: 00c00000-00d468ef : Kernel data | ||
35 | console: 3f006000-3f006fff : dwc_otg | ||
36 | console: 3f007000-3f007eff : /soc/dma@7e007000 | ||
37 | console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880 | ||
38 | console: 3f100000-3f100027 : /soc/watchdog@7e100000 | ||
39 | console: 3f101000-3f102fff : /soc/cprman@7e101000 | ||
40 | console: 3f200000-3f2000b3 : /soc/gpio@7e200000 | ||
41 | PASS (24.59 s) | ||
42 | RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 | ||
43 | JOB TIME : 25.02 s | ||
44 | |||
45 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
46 | Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> | ||
47 | Message-id: 20210531113837.1689775-1-f4bug@amsat.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 48 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 49 | --- |
10 | target/arm/helper.c | 19 +++++-------------- | 50 | tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++ |
11 | 1 file changed, 5 insertions(+), 14 deletions(-) | 51 | 1 file changed, 43 insertions(+) |
12 | 52 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 53 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py |
14 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 55 | --- a/tests/acceptance/boot_linux_console.py |
16 | +++ b/target/arm/helper.c | 56 | +++ b/tests/acceptance/boot_linux_console.py |
17 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) | 57 | @@ -XXX,XX +XXX,XX @@ |
18 | #endif | 58 | from avocado import skip |
19 | 59 | from avocado import skipUnless | |
20 | /* Shared logic between LORID and the rest of the LOR* registers. | 60 | from avocado_qemu import Test |
21 | - * Secure state has already been delt with. | 61 | +from avocado_qemu import exec_command |
22 | + * Secure state exclusion has already been dealt with. | 62 | from avocado_qemu import exec_command_and_wait_for_pattern |
23 | */ | 63 | from avocado_qemu import interrupt_interactive_console_until_pattern |
24 | -static CPAccessResult access_lor_ns(CPUARMState *env) | 64 | from avocado_qemu import wait_for_console_pattern |
25 | +static CPAccessResult access_lor_ns(CPUARMState *env, | 65 | @@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self): |
26 | + const ARMCPRegInfo *ri, bool isread) | 66 | """ |
27 | { | 67 | self.do_test_arm_raspi2(0) |
28 | int el = arm_current_el(env); | 68 | |
29 | 69 | + def test_arm_raspi2_initrd(self): | |
30 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_ns(CPUARMState *env) | 70 | + """ |
31 | return CP_ACCESS_OK; | 71 | + :avocado: tags=arch:arm |
32 | } | 72 | + :avocado: tags=machine:raspi2 |
33 | 73 | + """ | |
34 | -static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, | 74 | + deb_url = ('http://archive.raspberrypi.org/debian/' |
35 | - bool isread) | 75 | + 'pool/main/r/raspberrypi-firmware/' |
36 | -{ | 76 | + 'raspberrypi-kernel_1.20190215-1_armhf.deb') |
37 | - if (arm_is_secure_below_el3(env)) { | 77 | + deb_hash = 'cd284220b32128c5084037553db3c482426f3972' |
38 | - /* Access ok in secure mode. */ | 78 | + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash) |
39 | - return CP_ACCESS_OK; | 79 | + kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img') |
40 | - } | 80 | + dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb') |
41 | - return access_lor_ns(env); | 81 | + |
42 | -} | 82 | + initrd_url = ('https://github.com/groeck/linux-build-test/raw/' |
43 | - | 83 | + '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/' |
44 | static CPAccessResult access_lor_other(CPUARMState *env, | 84 | + 'arm/rootfs-armv7a.cpio.gz') |
45 | const ARMCPRegInfo *ri, bool isread) | 85 | + initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c' |
46 | { | 86 | + initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash) |
47 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env, | 87 | + initrd_path = os.path.join(self.workdir, 'rootfs.cpio') |
48 | /* Access denied in secure mode. */ | 88 | + archive.gzip_uncompress(initrd_path_gz, initrd_path) |
49 | return CP_ACCESS_TRAP; | 89 | + |
50 | } | 90 | + self.vm.set_console() |
51 | - return access_lor_ns(env); | 91 | + kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + |
52 | + return access_lor_ns(env, ri, isread); | 92 | + 'earlycon=pl011,0x3f201000 console=ttyAMA0 ' |
53 | } | 93 | + 'panic=-1 noreboot ' + |
54 | 94 | + 'dwc_otg.fiq_fsm_enable=0') | |
55 | /* | 95 | + self.vm.add_args('-kernel', kernel_path, |
56 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo lor_reginfo[] = { | 96 | + '-dtb', dtb_path, |
57 | .type = ARM_CP_CONST, .resetvalue = 0 }, | 97 | + '-initrd', initrd_path, |
58 | { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, | 98 | + '-append', kernel_command_line, |
59 | .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, | 99 | + '-no-reboot') |
60 | - .access = PL1_R, .accessfn = access_lorid, | 100 | + self.vm.launch() |
61 | + .access = PL1_R, .accessfn = access_lor_ns, | 101 | + self.wait_for_console_pattern('Boot successful.') |
62 | .type = ARM_CP_CONST, .resetvalue = 0 }, | 102 | + |
63 | REGINFO_SENTINEL | 103 | + exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo', |
64 | }; | 104 | + 'BCM2835') |
105 | + exec_command_and_wait_for_pattern(self, 'cat /proc/iomem', | ||
106 | + '/soc/cprman@7e101000') | ||
107 | + exec_command(self, 'halt') | ||
108 | + # Wait for VM to shut down gracefully | ||
109 | + self.vm.wait() | ||
110 | + | ||
111 | def test_arm_exynos4210_initrd(self): | ||
112 | """ | ||
113 | :avocado: tags=arch:arm | ||
65 | -- | 114 | -- |
66 | 2.20.1 | 115 | 2.20.1 |
67 | 116 | ||
68 | 117 | diff view generated by jsdifflib |
1 | From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 1 | From: Joe Komlodi <joe.komlodi@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | HCR should be applied when NS is set, not when it is cleared. | 3 | If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute |
4 | FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will | ||
5 | assert due to fpst->default_nan_mode being set. | ||
4 | 6 | ||
5 | Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 7 | To avoid this, we check to see what NaN mode we're running in before we call |
8 | floatxx_silence_nan(). | ||
9 | |||
10 | Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 15 | --- |
9 | target/arm/helper.c | 5 ++--- | 16 | target/arm/helper-a64.c | 12 +++++++++--- |
10 | 1 file changed, 2 insertions(+), 3 deletions(-) | 17 | target/arm/vfp_helper.c | 24 ++++++++++++++++++------ |
18 | 2 files changed, 27 insertions(+), 9 deletions(-) | ||
11 | 19 | ||
12 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 20 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c |
13 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/helper.c | 22 | --- a/target/arm/helper-a64.c |
15 | +++ b/target/arm/helper.c | 23 | +++ b/target/arm/helper-a64.c |
16 | @@ -XXX,XX +XXX,XX @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | 24 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) |
17 | 25 | float16 nan = a; | |
18 | /* | 26 | if (float16_is_signaling_nan(a, fpst)) { |
19 | * Non-IS variants of TLB operations are upgraded to | 27 | float_raise(float_flag_invalid, fpst); |
20 | - * IS versions if we are at NS EL1 and HCR_EL2.FB is set to | 28 | - nan = float16_silence_nan(a, fpst); |
21 | + * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to | 29 | + if (!fpst->default_nan_mode) { |
22 | * force broadcast of these operations. | 30 | + nan = float16_silence_nan(a, fpst); |
23 | */ | 31 | + } |
24 | static bool tlb_force_broadcast(CPUARMState *env) | 32 | } |
25 | { | 33 | if (fpst->default_nan_mode) { |
26 | - return (env->cp15.hcr_el2 & HCR_FB) && | 34 | nan = float16_default_nan(fpst); |
27 | - arm_current_el(env) == 1 && arm_is_secure_below_el3(env); | 35 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) |
28 | + return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB); | 36 | float32 nan = a; |
29 | } | 37 | if (float32_is_signaling_nan(a, fpst)) { |
30 | 38 | float_raise(float_flag_invalid, fpst); | |
31 | static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, | 39 | - nan = float32_silence_nan(a, fpst); |
40 | + if (!fpst->default_nan_mode) { | ||
41 | + nan = float32_silence_nan(a, fpst); | ||
42 | + } | ||
43 | } | ||
44 | if (fpst->default_nan_mode) { | ||
45 | nan = float32_default_nan(fpst); | ||
46 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) | ||
47 | float64 nan = a; | ||
48 | if (float64_is_signaling_nan(a, fpst)) { | ||
49 | float_raise(float_flag_invalid, fpst); | ||
50 | - nan = float64_silence_nan(a, fpst); | ||
51 | + if (!fpst->default_nan_mode) { | ||
52 | + nan = float64_silence_nan(a, fpst); | ||
53 | + } | ||
54 | } | ||
55 | if (fpst->default_nan_mode) { | ||
56 | nan = float64_default_nan(fpst); | ||
57 | diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/target/arm/vfp_helper.c | ||
60 | +++ b/target/arm/vfp_helper.c | ||
61 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) | ||
62 | float16 nan = f16; | ||
63 | if (float16_is_signaling_nan(f16, fpst)) { | ||
64 | float_raise(float_flag_invalid, fpst); | ||
65 | - nan = float16_silence_nan(f16, fpst); | ||
66 | + if (!fpst->default_nan_mode) { | ||
67 | + nan = float16_silence_nan(f16, fpst); | ||
68 | + } | ||
69 | } | ||
70 | if (fpst->default_nan_mode) { | ||
71 | nan = float16_default_nan(fpst); | ||
72 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) | ||
73 | float32 nan = f32; | ||
74 | if (float32_is_signaling_nan(f32, fpst)) { | ||
75 | float_raise(float_flag_invalid, fpst); | ||
76 | - nan = float32_silence_nan(f32, fpst); | ||
77 | + if (!fpst->default_nan_mode) { | ||
78 | + nan = float32_silence_nan(f32, fpst); | ||
79 | + } | ||
80 | } | ||
81 | if (fpst->default_nan_mode) { | ||
82 | nan = float32_default_nan(fpst); | ||
83 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) | ||
84 | float64 nan = f64; | ||
85 | if (float64_is_signaling_nan(f64, fpst)) { | ||
86 | float_raise(float_flag_invalid, fpst); | ||
87 | - nan = float64_silence_nan(f64, fpst); | ||
88 | + if (!fpst->default_nan_mode) { | ||
89 | + nan = float64_silence_nan(f64, fpst); | ||
90 | + } | ||
91 | } | ||
92 | if (fpst->default_nan_mode) { | ||
93 | nan = float64_default_nan(fpst); | ||
94 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) | ||
95 | float16 nan = f16; | ||
96 | if (float16_is_signaling_nan(f16, s)) { | ||
97 | float_raise(float_flag_invalid, s); | ||
98 | - nan = float16_silence_nan(f16, s); | ||
99 | + if (!s->default_nan_mode) { | ||
100 | + nan = float16_silence_nan(f16, fpstp); | ||
101 | + } | ||
102 | } | ||
103 | if (s->default_nan_mode) { | ||
104 | nan = float16_default_nan(s); | ||
105 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) | ||
106 | float32 nan = f32; | ||
107 | if (float32_is_signaling_nan(f32, s)) { | ||
108 | float_raise(float_flag_invalid, s); | ||
109 | - nan = float32_silence_nan(f32, s); | ||
110 | + if (!s->default_nan_mode) { | ||
111 | + nan = float32_silence_nan(f32, fpstp); | ||
112 | + } | ||
113 | } | ||
114 | if (s->default_nan_mode) { | ||
115 | nan = float32_default_nan(s); | ||
116 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) | ||
117 | float64 nan = f64; | ||
118 | if (float64_is_signaling_nan(f64, s)) { | ||
119 | float_raise(float_flag_invalid, s); | ||
120 | - nan = float64_silence_nan(f64, s); | ||
121 | + if (!s->default_nan_mode) { | ||
122 | + nan = float64_silence_nan(f64, fpstp); | ||
123 | + } | ||
124 | } | ||
125 | if (s->default_nan_mode) { | ||
126 | nan = float64_default_nan(s); | ||
32 | -- | 127 | -- |
33 | 2.20.1 | 128 | 2.20.1 |
34 | 129 | ||
35 | 130 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Maxim Uvarov <maxim.uvarov@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This seems a bit more readable than using offsetof CPU_DoubleU. | 3 | qemu has 2 type of functions: shutdown and reboot. Shutdown |
4 | function has to be used for machine shutdown. Otherwise we cause | ||
5 | a reset with a bogus "cause" value, when we intended a shutdown. | ||
4 | 6 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org> |
6 | Message-id: 20201030022618.785675-5-richard.henderson@linaro.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org | ||
10 | [PMM: tweaked commit message] | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 12 | --- |
10 | target/arm/translate.c | 13 ++++--------- | 13 | hw/gpio/gpio_pwr.c | 2 +- |
11 | 1 file changed, 4 insertions(+), 9 deletions(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 15 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 16 | diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 18 | --- a/hw/gpio/gpio_pwr.c |
16 | +++ b/target/arm/translate.c | 19 | +++ b/hw/gpio/gpio_pwr.c |
17 | @@ -XXX,XX +XXX,XX @@ static long neon_element_offset(int reg, int element, MemOp size) | 20 | @@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level) |
18 | return neon_full_reg_offset(reg) + ofs; | 21 | static void gpio_pwr_shutdown(void *opaque, int n, int level) |
19 | } | ||
20 | |||
21 | -static inline long vfp_reg_offset(bool dp, unsigned reg) | ||
22 | +/* Return the offset of a VFP Dreg (dp = true) or VFP Sreg (dp = false). */ | ||
23 | +static long vfp_reg_offset(bool dp, unsigned reg) | ||
24 | { | 22 | { |
25 | if (dp) { | 23 | if (level) { |
26 | - return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | 24 | - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
27 | + return neon_element_offset(reg, 0, MO_64); | 25 | + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); |
28 | } else { | ||
29 | - long ofs = offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1) & 1]); | ||
30 | - if (reg & 1) { | ||
31 | - ofs += offsetof(CPU_DoubleU, l.upper); | ||
32 | - } else { | ||
33 | - ofs += offsetof(CPU_DoubleU, l.lower); | ||
34 | - } | ||
35 | - return ofs; | ||
36 | + return neon_element_offset(reg >> 1, reg & 1, MO_32); | ||
37 | } | 26 | } |
38 | } | 27 | } |
39 | 28 | ||
40 | -- | 29 | -- |
41 | 2.20.1 | 30 | 2.20.1 |
42 | 31 | ||
43 | 32 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | In do_ldst(), the calculation of the offset needs to be based on the |
---|---|---|---|
2 | size of the memory access, not the size of the elements in the | ||
3 | vector. This meant we were getting it wrong for the widening and | ||
4 | narrowing variants of the various VLDR and VSTR insns. | ||
2 | 5 | ||
3 | We can then use this to improve VMOV (scalar to gp) and | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | VMOV (gp to scalar) so that we simply perform the memory | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | operation that we wanted, rather than inserting or | 8 | Message-id: 20210628135835.6690-2-peter.maydell@linaro.org |
6 | extracting from a 32-bit quantity. | 9 | --- |
10 | target/arm/translate-mve.c | 17 +++++++++-------- | ||
11 | 1 file changed, 9 insertions(+), 8 deletions(-) | ||
7 | 12 | ||
8 | These were the last uses of neon_load/store_reg, so remove them. | 13 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20201030022618.785675-7-richard.henderson@linaro.org | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | target/arm/translate.c | 50 +++++++++++++----------- | ||
16 | target/arm/translate-vfp.c.inc | 71 +++++----------------------------- | ||
17 | 2 files changed, 37 insertions(+), 84 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/translate.c | 15 | --- a/target/arm/translate-mve.c |
22 | +++ b/target/arm/translate.c | 16 | +++ b/target/arm/translate-mve.c |
23 | @@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg) | 17 | @@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s) |
24 | * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
25 | * where 0 is the least significant end of the register. | ||
26 | */ | ||
27 | -static long neon_element_offset(int reg, int element, MemOp size) | ||
28 | +static long neon_element_offset(int reg, int element, MemOp memop) | ||
29 | { | ||
30 | - int element_size = 1 << size; | ||
31 | + int element_size = 1 << (memop & MO_SIZE); | ||
32 | int ofs = element * element_size; | ||
33 | #ifdef HOST_WORDS_BIGENDIAN | ||
34 | /* | ||
35 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) | ||
36 | } | 18 | } |
37 | } | 19 | } |
38 | 20 | ||
39 | -static TCGv_i32 neon_load_reg(int reg, int pass) | 21 | -static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) |
40 | -{ | 22 | +static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, |
41 | - TCGv_i32 tmp = tcg_temp_new_i32(); | 23 | + unsigned msize) |
42 | - tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); | ||
43 | - return tmp; | ||
44 | -} | ||
45 | - | ||
46 | -static void neon_store_reg(int reg, int pass, TCGv_i32 var) | ||
47 | -{ | ||
48 | - tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); | ||
49 | - tcg_temp_free_i32(var); | ||
50 | -} | ||
51 | - | ||
52 | static inline void neon_load_reg64(TCGv_i64 var, int reg) | ||
53 | { | 24 | { |
54 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | 25 | TCGv_i32 addr; |
55 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg) | 26 | uint32_t offset; |
56 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | 27 | @@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) |
57 | } | ||
58 | |||
59 | -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) | ||
60 | +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | ||
61 | { | ||
62 | - long off = neon_element_offset(reg, ele, size); | ||
63 | + long off = neon_element_offset(reg, ele, memop); | ||
64 | |||
65 | - switch (size) { | ||
66 | - case MO_32: | ||
67 | + switch (memop) { | ||
68 | + case MO_SB: | ||
69 | + tcg_gen_ld8s_i32(dest, cpu_env, off); | ||
70 | + break; | ||
71 | + case MO_UB: | ||
72 | + tcg_gen_ld8u_i32(dest, cpu_env, off); | ||
73 | + break; | ||
74 | + case MO_SW: | ||
75 | + tcg_gen_ld16s_i32(dest, cpu_env, off); | ||
76 | + break; | ||
77 | + case MO_UW: | ||
78 | + tcg_gen_ld16u_i32(dest, cpu_env, off); | ||
79 | + break; | ||
80 | + case MO_UL: | ||
81 | + case MO_SL: | ||
82 | tcg_gen_ld_i32(dest, cpu_env, off); | ||
83 | break; | ||
84 | default: | ||
85 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) | ||
86 | } | ||
87 | } | ||
88 | |||
89 | -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size) | ||
90 | +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | ||
91 | { | ||
92 | - long off = neon_element_offset(reg, ele, size); | ||
93 | + long off = neon_element_offset(reg, ele, memop); | ||
94 | |||
95 | - switch (size) { | ||
96 | + switch (memop) { | ||
97 | + case MO_8: | ||
98 | + tcg_gen_st8_i32(src, cpu_env, off); | ||
99 | + break; | ||
100 | + case MO_16: | ||
101 | + tcg_gen_st16_i32(src, cpu_env, off); | ||
102 | + break; | ||
103 | case MO_32: | ||
104 | tcg_gen_st_i32(src, cpu_env, off); | ||
105 | break; | ||
106 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/arm/translate-vfp.c.inc | ||
109 | +++ b/target/arm/translate-vfp.c.inc | ||
110 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
111 | { | ||
112 | /* VMOV scalar to general purpose register */ | ||
113 | TCGv_i32 tmp; | ||
114 | - int pass; | ||
115 | - uint32_t offset; | ||
116 | |||
117 | - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | ||
118 | - if (a->size == 2 | ||
119 | + /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */ | ||
120 | + if (a->size == MO_32 | ||
121 | ? !dc_isar_feature(aa32_fpsp_v2, s) | ||
122 | : !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
123 | return false; | ||
124 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
125 | return false; | ||
126 | } | ||
127 | |||
128 | - offset = a->index << a->size; | ||
129 | - pass = extract32(offset, 2, 1); | ||
130 | - offset = extract32(offset, 0, 2) * 8; | ||
131 | - | ||
132 | if (!vfp_access_check(s)) { | ||
133 | return true; | 28 | return true; |
134 | } | 29 | } |
135 | 30 | ||
136 | - tmp = neon_load_reg(a->vn, pass); | 31 | - offset = a->imm << a->size; |
137 | - switch (a->size) { | 32 | + offset = a->imm << msize; |
138 | - case 0: | 33 | if (!a->a) { |
139 | - if (offset) { | 34 | offset = -offset; |
140 | - tcg_gen_shri_i32(tmp, tmp, offset); | 35 | } |
141 | - } | 36 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) |
142 | - if (a->u) { | 37 | { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, |
143 | - gen_uxtb(tmp); | 38 | { NULL, NULL } |
144 | - } else { | 39 | }; |
145 | - gen_sxtb(tmp); | 40 | - return do_ldst(s, a, ldstfns[a->size][a->l]); |
146 | - } | 41 | + return do_ldst(s, a, ldstfns[a->size][a->l], a->size); |
147 | - break; | 42 | } |
148 | - case 1: | 43 | |
149 | - if (a->u) { | 44 | -#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ |
150 | - if (offset) { | 45 | +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \ |
151 | - tcg_gen_shri_i32(tmp, tmp, 16); | 46 | static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ |
152 | - } else { | 47 | { \ |
153 | - gen_uxth(tmp); | 48 | static MVEGenLdStFn * const ldstfns[2][2] = { \ |
154 | - } | 49 | { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ |
155 | - } else { | 50 | { NULL, gen_helper_mve_##ULD }, \ |
156 | - if (offset) { | 51 | }; \ |
157 | - tcg_gen_sari_i32(tmp, tmp, 16); | 52 | - return do_ldst(s, a, ldstfns[a->u][a->l]); \ |
158 | - } else { | 53 | + return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \ |
159 | - gen_sxth(tmp); | 54 | } |
160 | - } | 55 | |
161 | - } | 56 | -DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) |
162 | - break; | 57 | -DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) |
163 | - case 2: | 58 | -DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) |
164 | - break; | 59 | +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8) |
165 | - } | 60 | +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8) |
166 | + tmp = tcg_temp_new_i32(); | 61 | +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16) |
167 | + read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN)); | 62 | |
168 | store_reg(s, a->rt, tmp); | 63 | static bool trans_VDUP(DisasContext *s, arg_VDUP *a) |
169 | |||
170 | return true; | ||
171 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
172 | static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
173 | { | 64 | { |
174 | /* VMOV general purpose register to scalar */ | ||
175 | - TCGv_i32 tmp, tmp2; | ||
176 | - int pass; | ||
177 | - uint32_t offset; | ||
178 | + TCGv_i32 tmp; | ||
179 | |||
180 | - /* SIZE == 2 is a VFP instruction; otherwise NEON. */ | ||
181 | - if (a->size == 2 | ||
182 | + /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */ | ||
183 | + if (a->size == MO_32 | ||
184 | ? !dc_isar_feature(aa32_fpsp_v2, s) | ||
185 | : !arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
186 | return false; | ||
187 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
188 | return false; | ||
189 | } | ||
190 | |||
191 | - offset = a->index << a->size; | ||
192 | - pass = extract32(offset, 2, 1); | ||
193 | - offset = extract32(offset, 0, 2) * 8; | ||
194 | - | ||
195 | if (!vfp_access_check(s)) { | ||
196 | return true; | ||
197 | } | ||
198 | |||
199 | tmp = load_reg(s, a->rt); | ||
200 | - switch (a->size) { | ||
201 | - case 0: | ||
202 | - tmp2 = neon_load_reg(a->vn, pass); | ||
203 | - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); | ||
204 | - tcg_temp_free_i32(tmp2); | ||
205 | - break; | ||
206 | - case 1: | ||
207 | - tmp2 = neon_load_reg(a->vn, pass); | ||
208 | - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); | ||
209 | - tcg_temp_free_i32(tmp2); | ||
210 | - break; | ||
211 | - case 2: | ||
212 | - break; | ||
213 | - } | ||
214 | - neon_store_reg(a->vn, pass, tmp); | ||
215 | + write_neon_element32(tmp, a->vn, a->index, a->size); | ||
216 | + tcg_temp_free_i32(tmp); | ||
217 | |||
218 | return true; | ||
219 | } | ||
220 | -- | 65 | -- |
221 | 2.20.1 | 66 | 2.20.1 |
222 | 67 | ||
223 | 68 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH |
---|---|---|---|
2 | insns had some bugs: | ||
3 | * the 32x32 multiply of elements was being done as 32x32->32, | ||
4 | not 32x32->64 | ||
5 | * we were incorrectly maintaining the accumulator in its full | ||
6 | 72-bit form across all 4 beats of the insn; in the pseudocode | ||
7 | it is squashed back into the 64 bits of the RdaHi:RdaLo | ||
8 | registers after each beat | ||
2 | 9 | ||
3 | Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. | 10 | In particular, fixing the second of these allows us to recast |
4 | This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): | 11 | the implementation to avoid 128-bit arithmetic entirely. |
5 | 12 | ||
6 | CID 1432363 (#1 of 1): Unintentional integer overflow: | 13 | Since the element size here is always 4, we can also drop the |
14 | parameterization of ESIZE to make the code a little more readable. | ||
7 | 15 | ||
8 | overflow_before_widen: | 16 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Potentially overflowing expression 1 << scale with type int | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | (32 bits, signed) is evaluated using 32-bit arithmetic, and | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | then used in a context that expects an expression of type | 19 | Message-id: 20210628135835.6690-3-peter.maydell@linaro.org |
12 | hwaddr (64 bits, unsigned). | 20 | --- |
21 | target/arm/mve_helper.c | 38 +++++++++++++++++++++----------------- | ||
22 | 1 file changed, 21 insertions(+), 17 deletions(-) | ||
13 | 23 | ||
14 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 24 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
15 | Acked-by: Eric Auger <eric.auger@redhat.com> | ||
16 | Message-id: 20201030144617.1535064-1-philmd@redhat.com | ||
17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | hw/arm/smmuv3.c | 3 ++- | ||
21 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
22 | |||
23 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/hw/arm/smmuv3.c | 26 | --- a/target/arm/mve_helper.c |
26 | +++ b/hw/arm/smmuv3.c | 27 | +++ b/target/arm/mve_helper.c |
27 | @@ -XXX,XX +XXX,XX @@ | 28 | @@ -XXX,XX +XXX,XX @@ |
28 | */ | 29 | */ |
29 | 30 | ||
30 | #include "qemu/osdep.h" | 31 | #include "qemu/osdep.h" |
31 | +#include "qemu/bitops.h" | 32 | -#include "qemu/int128.h" |
32 | #include "hw/irq.h" | 33 | #include "cpu.h" |
33 | #include "hw/sysbus.h" | 34 | #include "internals.h" |
34 | #include "migration/vmstate.h" | 35 | #include "vec_internal.h" |
35 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) | 36 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) |
36 | scale = CMD_SCALE(cmd); | 37 | DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) |
37 | num = CMD_NUM(cmd); | 38 | |
38 | ttl = CMD_TTL(cmd); | 39 | /* |
39 | - num_pages = (num + 1) * (1 << (scale)); | 40 | - * Rounding multiply add long dual accumulate high: we must keep |
40 | + num_pages = (num + 1) * BIT_ULL(scale); | 41 | - * a 72-bit internal accumulator value and return the top 64 bits. |
42 | + * Rounding multiply add long dual accumulate high. In the pseudocode | ||
43 | + * this is implemented with a 72-bit internal accumulator value of which | ||
44 | + * the top 64 bits are returned. We optimize this to avoid having to | ||
45 | + * use 128-bit arithmetic -- we can do this because the 74-bit accumulator | ||
46 | + * is squashed back into 64-bits after each beat. | ||
47 | */ | ||
48 | -#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \ | ||
49 | +#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \ | ||
50 | uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ | ||
51 | void *vm, uint64_t a) \ | ||
52 | { \ | ||
53 | uint16_t mask = mve_element_mask(env); \ | ||
54 | unsigned e; \ | ||
55 | TYPE *n = vn, *m = vm; \ | ||
56 | - Int128 acc = int128_lshift(TO128(a), 8); \ | ||
57 | - for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
58 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
59 | if (mask & 1) { \ | ||
60 | + LTYPE mul; \ | ||
61 | if (e & 1) { \ | ||
62 | - acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \ | ||
63 | - m[H##ESIZE(e)])); \ | ||
64 | + mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \ | ||
65 | + if (SUB) { \ | ||
66 | + mul = -mul; \ | ||
67 | + } \ | ||
68 | } else { \ | ||
69 | - acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \ | ||
70 | - m[H##ESIZE(e)])); \ | ||
71 | + mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \ | ||
72 | } \ | ||
73 | - acc = int128_add(acc, int128_make64(1 << 7)); \ | ||
74 | + mul = (mul >> 8) + ((mul >> 7) & 1); \ | ||
75 | + a += mul; \ | ||
76 | } \ | ||
77 | } \ | ||
78 | mve_advance_vpt(env); \ | ||
79 | - return int128_getlo(int128_rshift(acc, 8)); \ | ||
80 | + return a; \ | ||
41 | } | 81 | } |
42 | 82 | ||
43 | if (type == SMMU_CMD_TLBI_NH_VA) { | 83 | -DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64) |
84 | -DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64) | ||
85 | +DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false) | ||
86 | +DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false) | ||
87 | |||
88 | -DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64) | ||
89 | +DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false) | ||
90 | |||
91 | -DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64) | ||
92 | -DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64) | ||
93 | +DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true) | ||
94 | +DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true) | ||
95 | |||
96 | /* Vector add across vector */ | ||
97 | #define DO_VADDV(OP, ESIZE, TYPE) \ | ||
44 | -- | 98 | -- |
45 | 2.20.1 | 99 | 2.20.1 |
46 | 100 | ||
47 | 101 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The function asimd_imm_const() in translate-neon.c is an |
---|---|---|---|
2 | implementation of the pseudocode AdvSIMDExpandImm(), which we will | ||
3 | also want for MVE. Move the implementation to translate.c, with a | ||
4 | prototype in translate.h. | ||
2 | 5 | ||
3 | This will shortly have users outside of translate-neon.c.inc. | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210628135835.6690-4-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/translate.h | 16 ++++++++++ | ||
11 | target/arm/translate-neon.c | 63 ------------------------------------- | ||
12 | target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++ | ||
13 | 3 files changed, 73 insertions(+), 63 deletions(-) | ||
4 | 14 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 15 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
6 | Message-id: 20201030022618.785675-3-richard.henderson@linaro.org | 16 | index XXXXXXX..XXXXXXX 100644 |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | --- a/target/arm/translate.h |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | +++ b/target/arm/translate.h |
9 | --- | 19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) |
10 | target/arm/translate.c | 20 ++++++++++++++++++++ | 20 | return opc | s->be_data; |
11 | target/arm/translate-neon.c.inc | 19 ------------------- | 21 | } |
12 | 2 files changed, 20 insertions(+), 19 deletions(-) | 22 | |
13 | 23 | +/** | |
24 | + * asimd_imm_const: Expand an encoded SIMD constant value | ||
25 | + * | ||
26 | + * Expand a SIMD constant value. This is essentially the pseudocode | ||
27 | + * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for | ||
28 | + * VMVN and VBIC (when cmode < 14 && op == 1). | ||
29 | + * | ||
30 | + * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; | ||
31 | + * callers must catch this. | ||
32 | + * | ||
33 | + * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but | ||
34 | + * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; | ||
35 | + * we produce an immediate constant value of 0 in these cases. | ||
36 | + */ | ||
37 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); | ||
38 | + | ||
39 | #endif /* TARGET_ARM_TRANSLATE_H */ | ||
40 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/translate-neon.c | ||
43 | +++ b/target/arm/translate-neon.c | ||
44 | @@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh) | ||
45 | DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs) | ||
46 | DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu) | ||
47 | |||
48 | -static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
49 | -{ | ||
50 | - /* | ||
51 | - * Expand the encoded constant. | ||
52 | - * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. | ||
53 | - * We choose to not special-case this and will behave as if a | ||
54 | - * valid constant encoding of 0 had been given. | ||
55 | - * cmode = 15 op = 1 must UNDEF; we assume decode has handled that. | ||
56 | - */ | ||
57 | - switch (cmode) { | ||
58 | - case 0: case 1: | ||
59 | - /* no-op */ | ||
60 | - break; | ||
61 | - case 2: case 3: | ||
62 | - imm <<= 8; | ||
63 | - break; | ||
64 | - case 4: case 5: | ||
65 | - imm <<= 16; | ||
66 | - break; | ||
67 | - case 6: case 7: | ||
68 | - imm <<= 24; | ||
69 | - break; | ||
70 | - case 8: case 9: | ||
71 | - imm |= imm << 16; | ||
72 | - break; | ||
73 | - case 10: case 11: | ||
74 | - imm = (imm << 8) | (imm << 24); | ||
75 | - break; | ||
76 | - case 12: | ||
77 | - imm = (imm << 8) | 0xff; | ||
78 | - break; | ||
79 | - case 13: | ||
80 | - imm = (imm << 16) | 0xffff; | ||
81 | - break; | ||
82 | - case 14: | ||
83 | - if (op) { | ||
84 | - /* | ||
85 | - * This is the only case where the top and bottom 32 bits | ||
86 | - * of the encoded constant differ. | ||
87 | - */ | ||
88 | - uint64_t imm64 = 0; | ||
89 | - int n; | ||
90 | - | ||
91 | - for (n = 0; n < 8; n++) { | ||
92 | - if (imm & (1 << n)) { | ||
93 | - imm64 |= (0xffULL << (n * 8)); | ||
94 | - } | ||
95 | - } | ||
96 | - return imm64; | ||
97 | - } | ||
98 | - imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
99 | - break; | ||
100 | - case 15: | ||
101 | - imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
102 | - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
103 | - break; | ||
104 | - } | ||
105 | - if (op) { | ||
106 | - imm = ~imm; | ||
107 | - } | ||
108 | - return dup_const(MO_32, imm); | ||
109 | -} | ||
110 | - | ||
111 | static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
112 | GVecGen2iFn *fn) | ||
113 | { | ||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 114 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
15 | index XXXXXXX..XXXXXXX 100644 | 115 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate.c | 116 | --- a/target/arm/translate.c |
17 | +++ b/target/arm/translate.c | 117 | +++ b/target/arm/translate.c |
18 | @@ -XXX,XX +XXX,XX @@ static long neon_full_reg_offset(unsigned reg) | 118 | @@ -XXX,XX +XXX,XX @@ void arm_translate_init(void) |
19 | return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | 119 | a64_translate_init(); |
20 | } | 120 | } |
21 | 121 | ||
22 | +/* | 122 | +uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) |
23 | + * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
24 | + * where 0 is the least significant end of the register. | ||
25 | + */ | ||
26 | +static long neon_element_offset(int reg, int element, MemOp size) | ||
27 | +{ | 123 | +{ |
28 | + int element_size = 1 << size; | 124 | + /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */ |
29 | + int ofs = element * element_size; | 125 | + switch (cmode) { |
30 | +#ifdef HOST_WORDS_BIGENDIAN | 126 | + case 0: case 1: |
31 | + /* | 127 | + /* no-op */ |
32 | + * Calculate the offset assuming fully little-endian, | 128 | + break; |
33 | + * then XOR to account for the order of the 8-byte units. | 129 | + case 2: case 3: |
34 | + */ | 130 | + imm <<= 8; |
35 | + if (element_size < 8) { | 131 | + break; |
36 | + ofs ^= 8 - element_size; | 132 | + case 4: case 5: |
133 | + imm <<= 16; | ||
134 | + break; | ||
135 | + case 6: case 7: | ||
136 | + imm <<= 24; | ||
137 | + break; | ||
138 | + case 8: case 9: | ||
139 | + imm |= imm << 16; | ||
140 | + break; | ||
141 | + case 10: case 11: | ||
142 | + imm = (imm << 8) | (imm << 24); | ||
143 | + break; | ||
144 | + case 12: | ||
145 | + imm = (imm << 8) | 0xff; | ||
146 | + break; | ||
147 | + case 13: | ||
148 | + imm = (imm << 16) | 0xffff; | ||
149 | + break; | ||
150 | + case 14: | ||
151 | + if (op) { | ||
152 | + /* | ||
153 | + * This is the only case where the top and bottom 32 bits | ||
154 | + * of the encoded constant differ. | ||
155 | + */ | ||
156 | + uint64_t imm64 = 0; | ||
157 | + int n; | ||
158 | + | ||
159 | + for (n = 0; n < 8; n++) { | ||
160 | + if (imm & (1 << n)) { | ||
161 | + imm64 |= (0xffULL << (n * 8)); | ||
162 | + } | ||
163 | + } | ||
164 | + return imm64; | ||
165 | + } | ||
166 | + imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
167 | + break; | ||
168 | + case 15: | ||
169 | + imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
170 | + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
171 | + break; | ||
37 | + } | 172 | + } |
38 | +#endif | 173 | + if (op) { |
39 | + return neon_full_reg_offset(reg) + ofs; | 174 | + imm = ~imm; |
175 | + } | ||
176 | + return dup_const(MO_32, imm); | ||
40 | +} | 177 | +} |
41 | + | 178 | + |
42 | static inline long vfp_reg_offset(bool dp, unsigned reg) | 179 | /* Generate a label used for skipping this instruction */ |
180 | void arm_gen_condlabel(DisasContext *s) | ||
43 | { | 181 | { |
44 | if (dp) { | ||
45 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate-neon.c.inc | ||
48 | +++ b/target/arm/translate-neon.c.inc | ||
49 | @@ -XXX,XX +XXX,XX @@ static inline int neon_3same_fp_size(DisasContext *s, int x) | ||
50 | #include "decode-neon-ls.c.inc" | ||
51 | #include "decode-neon-shared.c.inc" | ||
52 | |||
53 | -/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
54 | - * where 0 is the least significant end of the register. | ||
55 | - */ | ||
56 | -static inline long | ||
57 | -neon_element_offset(int reg, int element, MemOp size) | ||
58 | -{ | ||
59 | - int element_size = 1 << size; | ||
60 | - int ofs = element * element_size; | ||
61 | -#ifdef HOST_WORDS_BIGENDIAN | ||
62 | - /* Calculate the offset assuming fully little-endian, | ||
63 | - * then XOR to account for the order of the 8-byte units. | ||
64 | - */ | ||
65 | - if (element_size < 8) { | ||
66 | - ofs ^= 8 - element_size; | ||
67 | - } | ||
68 | -#endif | ||
69 | - return neon_full_reg_offset(reg) + ofs; | ||
70 | -} | ||
71 | - | ||
72 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | ||
73 | { | ||
74 | long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | ||
75 | -- | 182 | -- |
76 | 2.20.1 | 183 | 2.20.1 |
77 | 184 | ||
78 | 185 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The A64 AdvSIMD modified-immediate grouping uses almost the same |
---|---|---|---|
2 | constant encoding that A32 Neon does; reuse asimd_imm_const() (to | ||
3 | which we add the AArch64-specific case for cmode 15 op 1) instead of | ||
4 | reimplementing it all. | ||
2 | 5 | ||
3 | The only uses of this function are for loading VFP | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | double-precision values, and nothing to do with NEON. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20210628135835.6690-5-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/translate.h | 3 +- | ||
11 | target/arm/translate-a64.c | 86 ++++---------------------------------- | ||
12 | target/arm/translate.c | 17 +++++++- | ||
13 | 3 files changed, 24 insertions(+), 82 deletions(-) | ||
5 | 14 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 15 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
7 | Message-id: 20201030022618.785675-10-richard.henderson@linaro.org | 16 | index XXXXXXX..XXXXXXX 100644 |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | --- a/target/arm/translate.h |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | +++ b/target/arm/translate.h |
10 | --- | 19 | @@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc) |
11 | target/arm/translate.c | 8 ++-- | 20 | * VMVN and VBIC (when cmode < 14 && op == 1). |
12 | target/arm/translate-vfp.c.inc | 84 +++++++++++++++++----------------- | 21 | * |
13 | 2 files changed, 46 insertions(+), 46 deletions(-) | 22 | * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; |
14 | 23 | - * callers must catch this. | |
24 | + * callers must catch this; we return the 64-bit constant value defined | ||
25 | + * for AArch64. | ||
26 | * | ||
27 | * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but | ||
28 | * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; | ||
29 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate-a64.c | ||
32 | +++ b/target/arm/translate-a64.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | ||
34 | { | ||
35 | int rd = extract32(insn, 0, 5); | ||
36 | int cmode = extract32(insn, 12, 4); | ||
37 | - int cmode_3_1 = extract32(cmode, 1, 3); | ||
38 | - int cmode_0 = extract32(cmode, 0, 1); | ||
39 | int o2 = extract32(insn, 11, 1); | ||
40 | uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); | ||
41 | bool is_neg = extract32(insn, 29, 1); | ||
42 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) | ||
43 | return; | ||
44 | } | ||
45 | |||
46 | - /* See AdvSIMDExpandImm() in ARM ARM */ | ||
47 | - switch (cmode_3_1) { | ||
48 | - case 0: /* Replicate(Zeros(24):imm8, 2) */ | ||
49 | - case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ | ||
50 | - case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ | ||
51 | - case 3: /* Replicate(imm8:Zeros(24), 2) */ | ||
52 | - { | ||
53 | - int shift = cmode_3_1 * 8; | ||
54 | - imm = bitfield_replicate(abcdefgh << shift, 32); | ||
55 | - break; | ||
56 | - } | ||
57 | - case 4: /* Replicate(Zeros(8):imm8, 4) */ | ||
58 | - case 5: /* Replicate(imm8:Zeros(8), 4) */ | ||
59 | - { | ||
60 | - int shift = (cmode_3_1 & 0x1) * 8; | ||
61 | - imm = bitfield_replicate(abcdefgh << shift, 16); | ||
62 | - break; | ||
63 | - } | ||
64 | - case 6: | ||
65 | - if (cmode_0) { | ||
66 | - /* Replicate(Zeros(8):imm8:Ones(16), 2) */ | ||
67 | - imm = (abcdefgh << 16) | 0xffff; | ||
68 | - } else { | ||
69 | - /* Replicate(Zeros(16):imm8:Ones(8), 2) */ | ||
70 | - imm = (abcdefgh << 8) | 0xff; | ||
71 | - } | ||
72 | - imm = bitfield_replicate(imm, 32); | ||
73 | - break; | ||
74 | - case 7: | ||
75 | - if (!cmode_0 && !is_neg) { | ||
76 | - imm = bitfield_replicate(abcdefgh, 8); | ||
77 | - } else if (!cmode_0 && is_neg) { | ||
78 | - int i; | ||
79 | - imm = 0; | ||
80 | - for (i = 0; i < 8; i++) { | ||
81 | - if ((abcdefgh) & (1 << i)) { | ||
82 | - imm |= 0xffULL << (i * 8); | ||
83 | - } | ||
84 | - } | ||
85 | - } else if (cmode_0) { | ||
86 | - if (is_neg) { | ||
87 | - imm = (abcdefgh & 0x3f) << 48; | ||
88 | - if (abcdefgh & 0x80) { | ||
89 | - imm |= 0x8000000000000000ULL; | ||
90 | - } | ||
91 | - if (abcdefgh & 0x40) { | ||
92 | - imm |= 0x3fc0000000000000ULL; | ||
93 | - } else { | ||
94 | - imm |= 0x4000000000000000ULL; | ||
95 | - } | ||
96 | - } else { | ||
97 | - if (o2) { | ||
98 | - /* FMOV (vector, immediate) - half-precision */ | ||
99 | - imm = vfp_expand_imm(MO_16, abcdefgh); | ||
100 | - /* now duplicate across the lanes */ | ||
101 | - imm = bitfield_replicate(imm, 16); | ||
102 | - } else { | ||
103 | - imm = (abcdefgh & 0x3f) << 19; | ||
104 | - if (abcdefgh & 0x80) { | ||
105 | - imm |= 0x80000000; | ||
106 | - } | ||
107 | - if (abcdefgh & 0x40) { | ||
108 | - imm |= 0x3e000000; | ||
109 | - } else { | ||
110 | - imm |= 0x40000000; | ||
111 | - } | ||
112 | - imm |= (imm << 32); | ||
113 | - } | ||
114 | - } | ||
115 | - } | ||
116 | - break; | ||
117 | - default: | ||
118 | - g_assert_not_reached(); | ||
119 | - } | ||
120 | - | ||
121 | - if (cmode_3_1 != 7 && is_neg) { | ||
122 | - imm = ~imm; | ||
123 | + if (cmode == 15 && o2 && !is_neg) { | ||
124 | + /* FMOV (vector, immediate) - half-precision */ | ||
125 | + imm = vfp_expand_imm(MO_16, abcdefgh); | ||
126 | + /* now duplicate across the lanes */ | ||
127 | + imm = bitfield_replicate(imm, 16); | ||
128 | + } else { | ||
129 | + imm = asimd_imm_const(abcdefgh, cmode, is_neg); | ||
130 | } | ||
131 | |||
132 | if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) { | ||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 133 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
16 | index XXXXXXX..XXXXXXX 100644 | 134 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate.c | 135 | --- a/target/arm/translate.c |
18 | +++ b/target/arm/translate.c | 136 | +++ b/target/arm/translate.c |
19 | @@ -XXX,XX +XXX,XX @@ static long vfp_reg_offset(bool dp, unsigned reg) | 137 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) |
20 | } | 138 | case 14: |
21 | } | 139 | if (op) { |
22 | 140 | /* | |
23 | -static inline void neon_load_reg64(TCGv_i64 var, int reg) | 141 | - * This is the only case where the top and bottom 32 bits |
24 | +static inline void vfp_load_reg64(TCGv_i64 var, int reg) | 142 | - * of the encoded constant differ. |
25 | { | 143 | + * This and cmode == 15 op == 1 are the only cases where |
26 | - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | 144 | + * the top and bottom 32 bits of the encoded constant differ. |
27 | + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); | 145 | */ |
28 | } | 146 | uint64_t imm64 = 0; |
29 | 147 | int n; | |
30 | -static inline void neon_store_reg64(TCGv_i64 var, int reg) | 148 | @@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) |
31 | +static inline void vfp_store_reg64(TCGv_i64 var, int reg) | 149 | imm |= (imm << 8) | (imm << 16) | (imm << 24); |
32 | { | 150 | break; |
33 | - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); | 151 | case 15: |
34 | + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); | 152 | + if (op) { |
35 | } | 153 | + /* Reserved encoding for AArch32; valid for AArch64 */ |
36 | 154 | + uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; | |
37 | static inline void vfp_load_reg32(TCGv_i32 var, int reg) | 155 | + if (imm & 0x80) { |
38 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | 156 | + imm64 |= 0x8000000000000000ULL; |
39 | index XXXXXXX..XXXXXXX 100644 | 157 | + } |
40 | --- a/target/arm/translate-vfp.c.inc | 158 | + if (imm & 0x40) { |
41 | +++ b/target/arm/translate-vfp.c.inc | 159 | + imm64 |= 0x3fc0000000000000ULL; |
42 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | 160 | + } else { |
43 | tcg_gen_ext_i32_i64(nf, cpu_NF); | 161 | + imm64 |= 0x4000000000000000ULL; |
44 | tcg_gen_ext_i32_i64(vf, cpu_VF); | 162 | + } |
45 | 163 | + return imm64; | |
46 | - neon_load_reg64(frn, rn); | 164 | + } |
47 | - neon_load_reg64(frm, rm); | 165 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) |
48 | + vfp_load_reg64(frn, rn); | 166 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); |
49 | + vfp_load_reg64(frm, rm); | 167 | break; |
50 | switch (a->cc) { | ||
51 | case 0: /* eq: Z */ | ||
52 | tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, | ||
53 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
54 | tcg_temp_free_i64(tmp); | ||
55 | break; | ||
56 | } | ||
57 | - neon_store_reg64(dest, rd); | ||
58 | + vfp_store_reg64(dest, rd); | ||
59 | tcg_temp_free_i64(frn); | ||
60 | tcg_temp_free_i64(frm); | ||
61 | tcg_temp_free_i64(dest); | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
63 | TCGv_i64 tcg_res; | ||
64 | tcg_op = tcg_temp_new_i64(); | ||
65 | tcg_res = tcg_temp_new_i64(); | ||
66 | - neon_load_reg64(tcg_op, rm); | ||
67 | + vfp_load_reg64(tcg_op, rm); | ||
68 | gen_helper_rintd(tcg_res, tcg_op, fpst); | ||
69 | - neon_store_reg64(tcg_res, rd); | ||
70 | + vfp_store_reg64(tcg_res, rd); | ||
71 | tcg_temp_free_i64(tcg_op); | ||
72 | tcg_temp_free_i64(tcg_res); | ||
73 | } else { | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
75 | tcg_double = tcg_temp_new_i64(); | ||
76 | tcg_res = tcg_temp_new_i64(); | ||
77 | tcg_tmp = tcg_temp_new_i32(); | ||
78 | - neon_load_reg64(tcg_double, rm); | ||
79 | + vfp_load_reg64(tcg_double, rm); | ||
80 | if (is_signed) { | ||
81 | gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); | ||
82 | } else { | ||
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) | ||
84 | tmp = tcg_temp_new_i64(); | ||
85 | if (a->l) { | ||
86 | gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); | ||
87 | - neon_store_reg64(tmp, a->vd); | ||
88 | + vfp_store_reg64(tmp, a->vd); | ||
89 | } else { | ||
90 | - neon_load_reg64(tmp, a->vd); | ||
91 | + vfp_load_reg64(tmp, a->vd); | ||
92 | gen_aa32_st64(s, tmp, addr, get_mem_index(s)); | ||
93 | } | ||
94 | tcg_temp_free_i64(tmp); | ||
95 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) | ||
96 | if (a->l) { | ||
97 | /* load */ | ||
98 | gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); | ||
99 | - neon_store_reg64(tmp, a->vd + i); | ||
100 | + vfp_store_reg64(tmp, a->vd + i); | ||
101 | } else { | ||
102 | /* store */ | ||
103 | - neon_load_reg64(tmp, a->vd + i); | ||
104 | + vfp_load_reg64(tmp, a->vd + i); | ||
105 | gen_aa32_st64(s, tmp, addr, get_mem_index(s)); | ||
106 | } | ||
107 | tcg_gen_addi_i32(addr, addr, offset); | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
109 | fd = tcg_temp_new_i64(); | ||
110 | fpst = fpstatus_ptr(FPST_FPCR); | ||
111 | |||
112 | - neon_load_reg64(f0, vn); | ||
113 | - neon_load_reg64(f1, vm); | ||
114 | + vfp_load_reg64(f0, vn); | ||
115 | + vfp_load_reg64(f1, vm); | ||
116 | |||
117 | for (;;) { | ||
118 | if (reads_vd) { | ||
119 | - neon_load_reg64(fd, vd); | ||
120 | + vfp_load_reg64(fd, vd); | ||
121 | } | ||
122 | fn(fd, f0, f1, fpst); | ||
123 | - neon_store_reg64(fd, vd); | ||
124 | + vfp_store_reg64(fd, vd); | ||
125 | |||
126 | if (veclen == 0) { | ||
127 | break; | ||
128 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
129 | veclen--; | ||
130 | vd = vfp_advance_dreg(vd, delta_d); | ||
131 | vn = vfp_advance_dreg(vn, delta_d); | ||
132 | - neon_load_reg64(f0, vn); | ||
133 | + vfp_load_reg64(f0, vn); | ||
134 | if (delta_m) { | ||
135 | vm = vfp_advance_dreg(vm, delta_m); | ||
136 | - neon_load_reg64(f1, vm); | ||
137 | + vfp_load_reg64(f1, vm); | ||
138 | } | ||
139 | } | ||
140 | |||
141 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
142 | f0 = tcg_temp_new_i64(); | ||
143 | fd = tcg_temp_new_i64(); | ||
144 | |||
145 | - neon_load_reg64(f0, vm); | ||
146 | + vfp_load_reg64(f0, vm); | ||
147 | |||
148 | for (;;) { | ||
149 | fn(fd, f0); | ||
150 | - neon_store_reg64(fd, vd); | ||
151 | + vfp_store_reg64(fd, vd); | ||
152 | |||
153 | if (veclen == 0) { | ||
154 | break; | ||
155 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
156 | /* single source one-many */ | ||
157 | while (veclen--) { | ||
158 | vd = vfp_advance_dreg(vd, delta_d); | ||
159 | - neon_store_reg64(fd, vd); | ||
160 | + vfp_store_reg64(fd, vd); | ||
161 | } | ||
162 | break; | ||
163 | } | ||
164 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
165 | veclen--; | ||
166 | vd = vfp_advance_dreg(vd, delta_d); | ||
167 | vd = vfp_advance_dreg(vm, delta_m); | ||
168 | - neon_load_reg64(f0, vm); | ||
169 | + vfp_load_reg64(f0, vm); | ||
170 | } | ||
171 | |||
172 | tcg_temp_free_i64(f0); | ||
173 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) | ||
174 | vm = tcg_temp_new_i64(); | ||
175 | vd = tcg_temp_new_i64(); | ||
176 | |||
177 | - neon_load_reg64(vn, a->vn); | ||
178 | - neon_load_reg64(vm, a->vm); | ||
179 | + vfp_load_reg64(vn, a->vn); | ||
180 | + vfp_load_reg64(vm, a->vm); | ||
181 | if (neg_n) { | ||
182 | /* VFNMS, VFMS */ | ||
183 | gen_helper_vfp_negd(vn, vn); | ||
184 | } | ||
185 | - neon_load_reg64(vd, a->vd); | ||
186 | + vfp_load_reg64(vd, a->vd); | ||
187 | if (neg_d) { | ||
188 | /* VFNMA, VFNMS */ | ||
189 | gen_helper_vfp_negd(vd, vd); | ||
190 | } | ||
191 | fpst = fpstatus_ptr(FPST_FPCR); | ||
192 | gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); | ||
193 | - neon_store_reg64(vd, a->vd); | ||
194 | + vfp_store_reg64(vd, a->vd); | ||
195 | |||
196 | tcg_temp_free_ptr(fpst); | ||
197 | tcg_temp_free_i64(vn); | ||
198 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
199 | fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); | ||
200 | |||
201 | for (;;) { | ||
202 | - neon_store_reg64(fd, vd); | ||
203 | + vfp_store_reg64(fd, vd); | ||
204 | |||
205 | if (veclen == 0) { | ||
206 | break; | ||
207 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) | ||
208 | vd = tcg_temp_new_i64(); | ||
209 | vm = tcg_temp_new_i64(); | ||
210 | |||
211 | - neon_load_reg64(vd, a->vd); | ||
212 | + vfp_load_reg64(vd, a->vd); | ||
213 | if (a->z) { | ||
214 | tcg_gen_movi_i64(vm, 0); | ||
215 | } else { | ||
216 | - neon_load_reg64(vm, a->vm); | ||
217 | + vfp_load_reg64(vm, a->vm); | ||
218 | } | ||
219 | |||
220 | if (a->e) { | ||
221 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) | ||
222 | tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); | ||
223 | vd = tcg_temp_new_i64(); | ||
224 | gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); | ||
225 | - neon_store_reg64(vd, a->vd); | ||
226 | + vfp_store_reg64(vd, a->vd); | ||
227 | tcg_temp_free_i32(ahp_mode); | ||
228 | tcg_temp_free_ptr(fpst); | ||
229 | tcg_temp_free_i32(tmp); | ||
230 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) | ||
231 | tmp = tcg_temp_new_i32(); | ||
232 | vm = tcg_temp_new_i64(); | ||
233 | |||
234 | - neon_load_reg64(vm, a->vm); | ||
235 | + vfp_load_reg64(vm, a->vm); | ||
236 | gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); | ||
237 | tcg_temp_free_i64(vm); | ||
238 | tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); | ||
239 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) | ||
240 | } | ||
241 | |||
242 | tmp = tcg_temp_new_i64(); | ||
243 | - neon_load_reg64(tmp, a->vm); | ||
244 | + vfp_load_reg64(tmp, a->vm); | ||
245 | fpst = fpstatus_ptr(FPST_FPCR); | ||
246 | gen_helper_rintd(tmp, tmp, fpst); | ||
247 | - neon_store_reg64(tmp, a->vd); | ||
248 | + vfp_store_reg64(tmp, a->vd); | ||
249 | tcg_temp_free_ptr(fpst); | ||
250 | tcg_temp_free_i64(tmp); | ||
251 | return true; | ||
252 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) | ||
253 | } | ||
254 | |||
255 | tmp = tcg_temp_new_i64(); | ||
256 | - neon_load_reg64(tmp, a->vm); | ||
257 | + vfp_load_reg64(tmp, a->vm); | ||
258 | fpst = fpstatus_ptr(FPST_FPCR); | ||
259 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
260 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
261 | gen_helper_rintd(tmp, tmp, fpst); | ||
262 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
263 | - neon_store_reg64(tmp, a->vd); | ||
264 | + vfp_store_reg64(tmp, a->vd); | ||
265 | tcg_temp_free_ptr(fpst); | ||
266 | tcg_temp_free_i64(tmp); | ||
267 | tcg_temp_free_i32(tcg_rmode); | ||
268 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) | ||
269 | } | ||
270 | |||
271 | tmp = tcg_temp_new_i64(); | ||
272 | - neon_load_reg64(tmp, a->vm); | ||
273 | + vfp_load_reg64(tmp, a->vm); | ||
274 | fpst = fpstatus_ptr(FPST_FPCR); | ||
275 | gen_helper_rintd_exact(tmp, tmp, fpst); | ||
276 | - neon_store_reg64(tmp, a->vd); | ||
277 | + vfp_store_reg64(tmp, a->vd); | ||
278 | tcg_temp_free_ptr(fpst); | ||
279 | tcg_temp_free_i64(tmp); | ||
280 | return true; | ||
281 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
282 | vd = tcg_temp_new_i64(); | ||
283 | vfp_load_reg32(vm, a->vm); | ||
284 | gen_helper_vfp_fcvtds(vd, vm, cpu_env); | ||
285 | - neon_store_reg64(vd, a->vd); | ||
286 | + vfp_store_reg64(vd, a->vd); | ||
287 | tcg_temp_free_i32(vm); | ||
288 | tcg_temp_free_i64(vd); | ||
289 | return true; | ||
290 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
291 | |||
292 | vd = tcg_temp_new_i32(); | ||
293 | vm = tcg_temp_new_i64(); | ||
294 | - neon_load_reg64(vm, a->vm); | ||
295 | + vfp_load_reg64(vm, a->vm); | ||
296 | gen_helper_vfp_fcvtsd(vd, vm, cpu_env); | ||
297 | vfp_store_reg32(vd, a->vd); | ||
298 | tcg_temp_free_i32(vd); | ||
299 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
300 | /* u32 -> f64 */ | ||
301 | gen_helper_vfp_uitod(vd, vm, fpst); | ||
302 | } | ||
303 | - neon_store_reg64(vd, a->vd); | ||
304 | + vfp_store_reg64(vd, a->vd); | ||
305 | tcg_temp_free_i32(vm); | ||
306 | tcg_temp_free_i64(vd); | ||
307 | tcg_temp_free_ptr(fpst); | ||
308 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
309 | |||
310 | vm = tcg_temp_new_i64(); | ||
311 | vd = tcg_temp_new_i32(); | ||
312 | - neon_load_reg64(vm, a->vm); | ||
313 | + vfp_load_reg64(vm, a->vm); | ||
314 | gen_helper_vjcvt(vd, vm, cpu_env); | ||
315 | vfp_store_reg32(vd, a->vd); | ||
316 | tcg_temp_free_i64(vm); | ||
317 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
318 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
319 | |||
320 | vd = tcg_temp_new_i64(); | ||
321 | - neon_load_reg64(vd, a->vd); | ||
322 | + vfp_load_reg64(vd, a->vd); | ||
323 | |||
324 | fpst = fpstatus_ptr(FPST_FPCR); | ||
325 | shift = tcg_const_i32(frac_bits); | ||
326 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
327 | g_assert_not_reached(); | ||
328 | } | ||
329 | |||
330 | - neon_store_reg64(vd, a->vd); | ||
331 | + vfp_store_reg64(vd, a->vd); | ||
332 | tcg_temp_free_i64(vd); | ||
333 | tcg_temp_free_i32(shift); | ||
334 | tcg_temp_free_ptr(fpst); | ||
335 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
336 | fpst = fpstatus_ptr(FPST_FPCR); | ||
337 | vm = tcg_temp_new_i64(); | ||
338 | vd = tcg_temp_new_i32(); | ||
339 | - neon_load_reg64(vm, a->vm); | ||
340 | + vfp_load_reg64(vm, a->vm); | ||
341 | |||
342 | if (a->s) { | ||
343 | if (a->rz) { | ||
344 | -- | 168 | -- |
345 | 2.20.1 | 169 | 2.20.1 |
346 | 170 | ||
347 | 171 | diff view generated by jsdifflib |
1 | The randomness tests in the NPCM7xx RNG test fail intermittently | 1 | Use dup_const() instead of bitfield_replicate() in |
---|---|---|---|
2 | but fairly frequently. On my machine running the test in a loop: | 2 | disas_simd_mod_imm(). |
3 | while QTEST_QEMU_BINARY=./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-test; do true; done | ||
4 | 3 | ||
5 | will fail in less than a minute with an error like: | 4 | (We can't replace the other use of bitfield_replicate() in this file, |
6 | ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs: | 5 | in logic_imm_decode_wmask(), because that location needs to handle 2 |
7 | assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): (0.00286205989 > 0.01) | 6 | and 4 bit elements, which dup_const() cannot.) |
8 | |||
9 | (Failures have been observed on all 4 of the randomness tests, | ||
10 | not just first_byte_runs.) | ||
11 | |||
12 | It's not clear why these tests are failing like this, but intermittent | ||
13 | failures make CI and merge testing awkward, so disable running them | ||
14 | unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when | ||
15 | running the test suite, until we work out the cause. | ||
16 | 7 | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
19 | Message-id: 20201102152454.8287-1-peter.maydell@linaro.org | 10 | Message-id: 20210628135835.6690-6-peter.maydell@linaro.org |
20 | Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
21 | --- | 11 | --- |
22 | tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++---- | 12 | target/arm/translate-a64.c | 2 +- |
23 | 1 file changed, 10 insertions(+), 4 deletions(-) | 13 | 1 file changed, 1 insertion(+), 1 deletion(-) |
24 | 14 | ||
25 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c | 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
26 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/tests/qtest/npcm7xx_rng-test.c | 17 | --- a/target/arm/translate-a64.c |
28 | +++ b/tests/qtest/npcm7xx_rng-test.c | 18 | +++ b/target/arm/translate-a64.c |
29 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | 19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) |
30 | 20 | /* FMOV (vector, immediate) - half-precision */ | |
31 | qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable); | 21 | imm = vfp_expand_imm(MO_16, abcdefgh); |
32 | qtest_add_func("npcm7xx_rng/rosel", test_rosel); | 22 | /* now duplicate across the lanes */ |
33 | - qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit); | 23 | - imm = bitfield_replicate(imm, 16); |
34 | - qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); | 24 | + imm = dup_const(MO_16, imm); |
35 | - qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit); | 25 | } else { |
36 | - qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); | 26 | imm = asimd_imm_const(abcdefgh, cmode, is_neg); |
37 | + /* | 27 | } |
38 | + * These tests fail intermittently; only run them on explicit | ||
39 | + * request until we figure out why. | ||
40 | + */ | ||
41 | + if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) { | ||
42 | + qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monobit); | ||
43 | + qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); | ||
44 | + qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monobit); | ||
45 | + qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); | ||
46 | + } | ||
47 | |||
48 | qtest_start("-machine npcm750-evb"); | ||
49 | ret = g_test_run(); | ||
50 | -- | 28 | -- |
51 | 2.20.1 | 29 | 2.20.1 |
52 | 30 | ||
53 | 31 | diff view generated by jsdifflib |
1 | Sphinx 3.2 is pickier than earlier versions about the option:: markup, | 1 | Implement the MVE logical-immediate insns (VMOV, VMVN, |
---|---|---|---|
2 | and complains about our usage in qemu-option-trace.rst: | 2 | VORR and VBIC). These have essentially the same encoding |
3 | 3 | as their Neon equivalents, and we implement the decode | |
4 | ../../docs/qemu-option-trace.rst.inc:4:Malformed option description | 4 | in the same way. |
5 | '[enable=]PATTERN', should look like "opt", "-opt args", "--opt args", | ||
6 | "/opt args" or "+opt args" | ||
7 | |||
8 | In this file, we're really trying to document the different parts of | ||
9 | the top-level --trace option, which qemu-nbd.rst and qemu-img.rst | ||
10 | have already introduced with an option:: markup. So it's not right | ||
11 | to use option:: here anyway. Switch to a different markup | ||
12 | (definition lists) which gives about the same formatted output. | ||
13 | |||
14 | (Unlike option::, this markup doesn't produce index entries; but | ||
15 | at the moment we don't do anything much with indexes anyway, and | ||
16 | in any case I think it doesn't make much sense to have individual | ||
17 | index entries for the sub-parts of the --trace option.) | ||
18 | 5 | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
20 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
21 | Tested-by: Stefan Hajnoczi <stefanha@redhat.com> | 8 | Message-id: 20210628135835.6690-7-peter.maydell@linaro.org |
22 | Message-id: 20201030174700.7204-3-peter.maydell@linaro.org | ||
23 | --- | 9 | --- |
24 | docs/qemu-option-trace.rst.inc | 6 +++--- | 10 | target/arm/helper-mve.h | 4 +++ |
25 | 1 file changed, 3 insertions(+), 3 deletions(-) | 11 | target/arm/mve.decode | 17 +++++++++++++ |
12 | target/arm/mve_helper.c | 24 ++++++++++++++++++ | ||
13 | target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++ | ||
14 | 4 files changed, 95 insertions(+) | ||
26 | 15 | ||
27 | diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
28 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/docs/qemu-option-trace.rst.inc | 18 | --- a/target/arm/helper-mve.h |
30 | +++ b/docs/qemu-option-trace.rst.inc | 19 | +++ b/target/arm/helper-mve.h |
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
21 | DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
22 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
23 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
24 | + | ||
25 | +DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
26 | +DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
27 | +DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/mve.decode | ||
31 | +++ b/target/arm/mve.decode | ||
31 | @@ -XXX,XX +XXX,XX @@ | 32 | @@ -XXX,XX +XXX,XX @@ |
32 | 33 | # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit | |
33 | Specify tracing options. | 34 | %size_28 28:1 !function=plus_1 |
34 | 35 | ||
35 | -.. option:: [enable=]PATTERN | 36 | +# 1imm format immediate |
36 | +``[enable=]PATTERN`` | 37 | +%imm_28_16_0 28:1 16:3 0:4 |
37 | 38 | + | |
38 | Immediately enable events matching *PATTERN* | 39 | &vldr_vstr rn qd imm p a w size l u |
39 | (either event name or a globbing pattern). This option is only | 40 | &1op qd qm size |
40 | @@ -XXX,XX +XXX,XX @@ Specify tracing options. | 41 | &2op qd qm qn size |
41 | 42 | &2scalar qd qn rm size | |
42 | Use :option:`-trace help` to print a list of names of trace points. | 43 | +&1imm qd imm cmode op |
43 | 44 | ||
44 | -.. option:: events=FILE | 45 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 |
45 | +``events=FILE`` | 46 | # Note that both Rn and Qd are 3 bits only (no D bit) |
46 | 47 | @@ -XXX,XX +XXX,XX @@ | |
47 | Immediately enable events listed in *FILE*. | 48 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 |
48 | The file must contain one event name (as listed in the ``trace-events-all`` | 49 | @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \ |
49 | @@ -XXX,XX +XXX,XX @@ Specify tracing options. | 50 | size=%size_28 |
50 | available if QEMU has been compiled with the ``simple``, ``log`` or | 51 | +@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0 |
51 | ``ftrace`` tracing backend. | 52 | |
52 | 53 | # The _rev suffix indicates that Vn and Vm are reversed. This is | |
53 | -.. option:: file=FILE | 54 | # the case for shifts. In the Arm ARM these insns are documented |
54 | +``file=FILE`` | 55 | @@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd |
55 | 56 | # Predicate operations | |
56 | Log output traces to *FILE*. | 57 | %mask_22_13 22:1 13:3 |
57 | This option is only available if QEMU has been compiled with | 58 | VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 |
59 | + | ||
60 | +# Logical immediate operations (1 reg and modified-immediate) | ||
61 | + | ||
62 | +# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but | ||
63 | +# not in a way we can conveniently represent in decodetree without | ||
64 | +# a lot of repetition: | ||
65 | +# VORR: op=0, (cmode & 1) && cmode < 12 | ||
66 | +# VBIC: op=1, (cmode & 1) && cmode < 12 | ||
67 | +# VMOV: everything else | ||
68 | +# So we have a single decode line and check the cmode/op in the | ||
69 | +# trans function. | ||
70 | +Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
71 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/arm/mve_helper.c | ||
74 | +++ b/target/arm/mve_helper.c | ||
75 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG) | ||
76 | DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) | ||
77 | DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) | ||
78 | |||
79 | +/* | ||
80 | + * 1 operand immediates: Vda is destination and possibly also one source. | ||
81 | + * All these insns work at 64-bit widths. | ||
82 | + */ | ||
83 | +#define DO_1OP_IMM(OP, FN) \ | ||
84 | + void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \ | ||
85 | + { \ | ||
86 | + uint64_t *da = vda; \ | ||
87 | + uint16_t mask = mve_element_mask(env); \ | ||
88 | + unsigned e; \ | ||
89 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ | ||
90 | + mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \ | ||
91 | + } \ | ||
92 | + mve_advance_vpt(env); \ | ||
93 | + } | ||
94 | + | ||
95 | +#define DO_MOVI(N, I) (I) | ||
96 | +#define DO_ANDI(N, I) ((N) & (I)) | ||
97 | +#define DO_ORRI(N, I) ((N) | (I)) | ||
98 | + | ||
99 | +DO_1OP_IMM(vmovi, DO_MOVI) | ||
100 | +DO_1OP_IMM(vandi, DO_ANDI) | ||
101 | +DO_1OP_IMM(vorri, DO_ORRI) | ||
102 | + | ||
103 | #define DO_2OP(OP, ESIZE, TYPE, FN) \ | ||
104 | void HELPER(glue(mve_, OP))(CPUARMState *env, \ | ||
105 | void *vd, void *vn, void *vm) \ | ||
106 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/arm/translate-mve.c | ||
109 | +++ b/target/arm/translate-mve.c | ||
110 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
111 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
112 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
113 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
114 | +typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
115 | |||
116 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ | ||
117 | static inline long mve_qreg_offset(unsigned reg) | ||
118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) | ||
119 | mve_update_eci(s); | ||
120 | return true; | ||
121 | } | ||
122 | + | ||
123 | +static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) | ||
124 | +{ | ||
125 | + TCGv_ptr qd; | ||
126 | + uint64_t imm; | ||
127 | + | ||
128 | + if (!dc_isar_feature(aa32_mve, s) || | ||
129 | + !mve_check_qreg_bank(s, a->qd) || | ||
130 | + !fn) { | ||
131 | + return false; | ||
132 | + } | ||
133 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
134 | + return true; | ||
135 | + } | ||
136 | + | ||
137 | + imm = asimd_imm_const(a->imm, a->cmode, a->op); | ||
138 | + | ||
139 | + qd = mve_qreg_ptr(a->qd); | ||
140 | + fn(cpu_env, qd, tcg_constant_i64(imm)); | ||
141 | + tcg_temp_free_ptr(qd); | ||
142 | + mve_update_eci(s); | ||
143 | + return true; | ||
144 | +} | ||
145 | + | ||
146 | +static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
147 | +{ | ||
148 | + /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ | ||
149 | + MVEGenOneOpImmFn *fn; | ||
150 | + | ||
151 | + if ((a->cmode & 1) && a->cmode < 12) { | ||
152 | + if (a->op) { | ||
153 | + /* | ||
154 | + * For op=1, the immediate will be inverted by asimd_imm_const(), | ||
155 | + * so the VBIC becomes a logical AND operation. | ||
156 | + */ | ||
157 | + fn = gen_helper_mve_vandi; | ||
158 | + } else { | ||
159 | + fn = gen_helper_mve_vorri; | ||
160 | + } | ||
161 | + } else { | ||
162 | + /* There is one unallocated cmode/op combination in this space */ | ||
163 | + if (a->cmode == 15 && a->op == 1) { | ||
164 | + return false; | ||
165 | + } | ||
166 | + /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */ | ||
167 | + fn = gen_helper_mve_vmovi; | ||
168 | + } | ||
169 | + return do_1imm(s, a, fn); | ||
170 | +} | ||
58 | -- | 171 | -- |
59 | 2.20.1 | 172 | 2.20.1 |
60 | 173 | ||
61 | 174 | diff view generated by jsdifflib |
1 | The kerneldoc script currently emits Sphinx markup for a macro with | 1 | Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL |
---|---|---|---|
2 | arguments that uses the c:function directive. This is correct for | 2 | and VQSHLU. |
3 | Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow | 3 | |
4 | documentation of macros with arguments and c:function is not picky | 4 | The size-and-immediate encoding here is the same as Neon, and we |
5 | about the syntax of what it is passed. However, in Sphinx 3 the | 5 | handle it the same way neon-dp.decode does. |
6 | c:macro directive was enhanced to support macros with arguments, | ||
7 | and c:function was made more picky about what syntax it accepted. | ||
8 | |||
9 | When kerneldoc is told that it needs to produce output for Sphinx | ||
10 | 3 or later, make it emit c:function only for functions and c:macro | ||
11 | for macros with arguments. We assume that anything with a return | ||
12 | type is a function and anything without is a macro. | ||
13 | |||
14 | This fixes the Sphinx error: | ||
15 | |||
16 | /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:155:Error in declarator | ||
17 | If declarator-id with parameters (e.g., 'void f(int arg)'): | ||
18 | Invalid C declaration: Expected identifier in nested name. [error at 25] | ||
19 | DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) | ||
20 | -------------------------^ | ||
21 | If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'): | ||
22 | Error in declarator or parameters | ||
23 | Invalid C declaration: Expecting "(" in parameters. [error at 39] | ||
24 | DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) | ||
25 | ---------------------------------------^ | ||
26 | 6 | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
28 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
29 | Tested-by: Stefan Hajnoczi <stefanha@redhat.com> | 9 | Message-id: 20210628135835.6690-8-peter.maydell@linaro.org |
30 | Message-id: 20201030174700.7204-2-peter.maydell@linaro.org | ||
31 | --- | 10 | --- |
32 | scripts/kernel-doc | 18 +++++++++++++++++- | 11 | target/arm/helper-mve.h | 16 +++++++++++ |
33 | 1 file changed, 17 insertions(+), 1 deletion(-) | 12 | target/arm/mve.decode | 23 +++++++++++++++ |
34 | 13 | target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++ | |
35 | diff --git a/scripts/kernel-doc b/scripts/kernel-doc | 14 | target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++ |
36 | index XXXXXXX..XXXXXXX 100755 | 15 | 4 files changed, 147 insertions(+) |
37 | --- a/scripts/kernel-doc | 16 | |
38 | +++ b/scripts/kernel-doc | 17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
39 | @@ -XXX,XX +XXX,XX @@ sub output_function_rst(%) { | 18 | index XXXXXXX..XXXXXXX 100644 |
40 | output_highlight_rst($args{'purpose'}); | 19 | --- a/target/arm/helper-mve.h |
41 | $start = "\n\n**Syntax**\n\n ``"; | 20 | +++ b/target/arm/helper-mve.h |
42 | } else { | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
43 | - print ".. c:function:: "; | 22 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) |
44 | + if ((split(/\./, $sphinx_version))[0] >= 3) { | 23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) |
45 | + # Sphinx 3 and later distinguish macros and functions and | 24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) |
46 | + # complain if you use c:function with something that's not | 25 | + |
47 | + # syntactically valid as a function declaration. | 26 | +DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
48 | + # We assume that anything with a return type is a function | 27 | +DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
49 | + # and anything without is a macro. | 28 | +DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
50 | + if ($args{'functiontype'} ne "") { | 29 | + |
51 | + print ".. c:function:: "; | 30 | +DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
52 | + } else { | 31 | +DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
53 | + print ".. c:macro:: "; | 32 | +DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
54 | + } | 33 | + |
55 | + } else { | 34 | +DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
56 | + # Older Sphinx don't support documenting macros that take | 35 | +DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
57 | + # arguments with c:macro, and don't complain about the use | 36 | +DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
58 | + # of c:function for this. | 37 | + |
59 | + print ".. c:function:: "; | 38 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
60 | + } | 39 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
40 | +DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/mve.decode | ||
44 | +++ b/target/arm/mve.decode | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | &2op qd qm qn size | ||
47 | &2scalar qd qn rm size | ||
48 | &1imm qd imm cmode op | ||
49 | +&2shift qd qm shift size | ||
50 | |||
51 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
52 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
55 | @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
56 | |||
57 | +@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 | ||
58 | +@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 | ||
59 | +@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 | ||
60 | + | ||
61 | # Vector loads and stores | ||
62 | |||
63 | # Widening loads and narrowing stores: | ||
64 | @@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
65 | # So we have a single decode line and check the cmode/op in the | ||
66 | # trans function. | ||
67 | Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm | ||
68 | + | ||
69 | +# Shifts by immediate | ||
70 | + | ||
71 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
72 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
73 | +VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
74 | + | ||
75 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
76 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
77 | +VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
78 | + | ||
79 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b | ||
80 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h | ||
81 | +VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
82 | + | ||
83 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
84 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
85 | +VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
86 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/target/arm/mve_helper.c | ||
89 | +++ b/target/arm/mve_helper.c | ||
90 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) | ||
91 | WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) | ||
92 | #define DO_UQRSHL_OP(N, M, satp) \ | ||
93 | WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) | ||
94 | +#define DO_SUQSHL_OP(N, M, satp) \ | ||
95 | + WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp) | ||
96 | |||
97 | DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) | ||
98 | DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) | ||
99 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t) | ||
100 | DO_VADDV(vaddvub, 1, uint8_t) | ||
101 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
102 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
103 | + | ||
104 | +/* Shifts by immediate */ | ||
105 | +#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
106 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
107 | + void *vm, uint32_t shift) \ | ||
108 | + { \ | ||
109 | + TYPE *d = vd, *m = vm; \ | ||
110 | + uint16_t mask = mve_element_mask(env); \ | ||
111 | + unsigned e; \ | ||
112 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
113 | + mergemask(&d[H##ESIZE(e)], \ | ||
114 | + FN(m[H##ESIZE(e)], shift), mask); \ | ||
115 | + } \ | ||
116 | + mve_advance_vpt(env); \ | ||
117 | + } | ||
118 | + | ||
119 | +#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \ | ||
120 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
121 | + void *vm, uint32_t shift) \ | ||
122 | + { \ | ||
123 | + TYPE *d = vd, *m = vm; \ | ||
124 | + uint16_t mask = mve_element_mask(env); \ | ||
125 | + unsigned e; \ | ||
126 | + bool qc = false; \ | ||
127 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
128 | + bool sat = false; \ | ||
129 | + mergemask(&d[H##ESIZE(e)], \ | ||
130 | + FN(m[H##ESIZE(e)], shift, &sat), mask); \ | ||
131 | + qc |= sat & mask & 1; \ | ||
132 | + } \ | ||
133 | + if (qc) { \ | ||
134 | + env->vfp.qc[0] = qc; \ | ||
135 | + } \ | ||
136 | + mve_advance_vpt(env); \ | ||
137 | + } | ||
138 | + | ||
139 | +/* provide unsigned 2-op shift helpers for all sizes */ | ||
140 | +#define DO_2SHIFT_U(OP, FN) \ | ||
141 | + DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
142 | + DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
143 | + DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
144 | + | ||
145 | +#define DO_2SHIFT_SAT_U(OP, FN) \ | ||
146 | + DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
147 | + DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \ | ||
148 | + DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN) | ||
149 | +#define DO_2SHIFT_SAT_S(OP, FN) \ | ||
150 | + DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \ | ||
151 | + DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \ | ||
152 | + DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
153 | + | ||
154 | +DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
155 | +DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
156 | +DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
157 | +DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
158 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
159 | index XXXXXXX..XXXXXXX 100644 | ||
160 | --- a/target/arm/translate-mve.c | ||
161 | +++ b/target/arm/translate-mve.c | ||
162 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
163 | typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
164 | typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
165 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
166 | +typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
167 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
168 | typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
169 | typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
170 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a) | ||
61 | } | 171 | } |
62 | if ($args{'functiontype'} ne "") { | 172 | return do_1imm(s, a, fn); |
63 | $start .= $args{'functiontype'} . " " . $args{'function'} . " ("; | 173 | } |
174 | + | ||
175 | +static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn, | ||
176 | + bool negateshift) | ||
177 | +{ | ||
178 | + TCGv_ptr qd, qm; | ||
179 | + int shift = a->shift; | ||
180 | + | ||
181 | + if (!dc_isar_feature(aa32_mve, s) || | ||
182 | + !mve_check_qreg_bank(s, a->qd | a->qm) || | ||
183 | + !fn) { | ||
184 | + return false; | ||
185 | + } | ||
186 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
187 | + return true; | ||
188 | + } | ||
189 | + | ||
190 | + /* | ||
191 | + * When we handle a right shift insn using a left-shift helper | ||
192 | + * which permits a negative shift count to indicate a right-shift, | ||
193 | + * we must negate the shift count. | ||
194 | + */ | ||
195 | + if (negateshift) { | ||
196 | + shift = -shift; | ||
197 | + } | ||
198 | + | ||
199 | + qd = mve_qreg_ptr(a->qd); | ||
200 | + qm = mve_qreg_ptr(a->qm); | ||
201 | + fn(cpu_env, qd, qm, tcg_constant_i32(shift)); | ||
202 | + tcg_temp_free_ptr(qd); | ||
203 | + tcg_temp_free_ptr(qm); | ||
204 | + mve_update_eci(s); | ||
205 | + return true; | ||
206 | +} | ||
207 | + | ||
208 | +#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \ | ||
209 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
210 | + { \ | ||
211 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
212 | + gen_helper_mve_##FN##b, \ | ||
213 | + gen_helper_mve_##FN##h, \ | ||
214 | + gen_helper_mve_##FN##w, \ | ||
215 | + NULL, \ | ||
216 | + }; \ | ||
217 | + return do_2shift(s, a, fns[a->size], NEGATESHIFT); \ | ||
218 | + } | ||
219 | + | ||
220 | +DO_2SHIFT(VSHLI, vshli_u, false) | ||
221 | +DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
222 | +DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
223 | +DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
64 | -- | 224 | -- |
65 | 2.20.1 | 225 | 2.20.1 |
66 | 226 | ||
67 | 227 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE vector shift right by immediate insns VSHRI and |
---|---|---|---|
2 | VRSHRI. As with Neon, we implement these by using helper functions | ||
3 | which perform left shifts but allow negative shift counts to indicate | ||
4 | right shifts. | ||
2 | 5 | ||
3 | This function makes it clear that we're talking about the whole | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | register, and not the 32-bit piece at index 0. This fixes a bug | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | when running on a big-endian host. | 8 | Message-id: 20210628135835.6690-9-peter.maydell@linaro.org |
9 | --- | ||
10 | target/arm/helper-mve.h | 12 ++++++++++++ | ||
11 | target/arm/translate.h | 20 ++++++++++++++++++++ | ||
12 | target/arm/mve.decode | 28 ++++++++++++++++++++++++++++ | ||
13 | target/arm/mve_helper.c | 7 +++++++ | ||
14 | target/arm/translate-mve.c | 5 +++++ | ||
15 | target/arm/translate-neon.c | 18 ------------------ | ||
16 | 6 files changed, 72 insertions(+), 18 deletions(-) | ||
6 | 17 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
8 | Message-id: 20201030022618.785675-2-richard.henderson@linaro.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | target/arm/translate.c | 8 ++++++ | ||
13 | target/arm/translate-neon.c.inc | 44 ++++++++++++++++----------------- | ||
14 | target/arm/translate-vfp.c.inc | 2 +- | ||
15 | 3 files changed, 31 insertions(+), 23 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/translate.c | 20 | --- a/target/arm/helper-mve.h |
20 | +++ b/target/arm/translate.c | 21 | +++ b/target/arm/helper-mve.h |
21 | @@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm) | 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) |
22 | unallocated_encoding(s); | 23 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) |
24 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
25 | |||
26 | +DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
29 | + | ||
30 | DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
34 | DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
35 | DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
36 | DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
37 | + | ||
38 | +DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | +DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | + | ||
42 | +DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
43 | +DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
44 | +DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
45 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/translate.h | ||
48 | +++ b/target/arm/translate.h | ||
49 | @@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x) | ||
50 | return x * 2 + 1; | ||
23 | } | 51 | } |
24 | 52 | ||
25 | +/* | 53 | +static inline int rsub_64(DisasContext *s, int x) |
26 | + * Return the offset of a "full" NEON Dreg. | ||
27 | + */ | ||
28 | +static long neon_full_reg_offset(unsigned reg) | ||
29 | +{ | 54 | +{ |
30 | + return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); | 55 | + return 64 - x; |
31 | +} | 56 | +} |
32 | + | 57 | + |
33 | static inline long vfp_reg_offset(bool dp, unsigned reg) | 58 | +static inline int rsub_32(DisasContext *s, int x) |
59 | +{ | ||
60 | + return 32 - x; | ||
61 | +} | ||
62 | + | ||
63 | +static inline int rsub_16(DisasContext *s, int x) | ||
64 | +{ | ||
65 | + return 16 - x; | ||
66 | +} | ||
67 | + | ||
68 | +static inline int rsub_8(DisasContext *s, int x) | ||
69 | +{ | ||
70 | + return 8 - x; | ||
71 | +} | ||
72 | + | ||
73 | static inline int arm_dc_feature(DisasContext *dc, int feature) | ||
34 | { | 74 | { |
35 | if (dp) { | 75 | return (dc->features & (1ULL << feature)) != 0; |
36 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | 76 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
37 | index XXXXXXX..XXXXXXX 100644 | 77 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/target/arm/translate-neon.c.inc | 78 | --- a/target/arm/mve.decode |
39 | +++ b/target/arm/translate-neon.c.inc | 79 | +++ b/target/arm/mve.decode |
40 | @@ -XXX,XX +XXX,XX @@ neon_element_offset(int reg, int element, MemOp size) | 80 | @@ -XXX,XX +XXX,XX @@ |
41 | ofs ^= 8 - element_size; | 81 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
42 | } | 82 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 |
43 | #endif | 83 | |
44 | - return neon_reg_offset(reg, 0) + ofs; | 84 | +# Right shifts are encoded as N - shift, where N is the element size in bits. |
45 | + return neon_full_reg_offset(reg) + ofs; | 85 | +%rshift_i5 16:5 !function=rsub_32 |
86 | +%rshift_i4 16:4 !function=rsub_16 | ||
87 | +%rshift_i3 16:3 !function=rsub_8 | ||
88 | + | ||
89 | +@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
90 | + size=0 shift=%rshift_i3 | ||
91 | +@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
92 | + size=1 shift=%rshift_i4 | ||
93 | +@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \ | ||
94 | + size=2 shift=%rshift_i5 | ||
95 | + | ||
96 | # Vector loads and stores | ||
97 | |||
98 | # Widening loads and narrowing stores: | ||
99 | @@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w | ||
100 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b | ||
101 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h | ||
102 | VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w | ||
103 | + | ||
104 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
105 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
106 | +VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
107 | + | ||
108 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b | ||
109 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h | ||
110 | +VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w | ||
111 | + | ||
112 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
113 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
114 | +VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
115 | + | ||
116 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
117 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
118 | +VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
119 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
120 | index XXXXXXX..XXXXXXX 100644 | ||
121 | --- a/target/arm/mve_helper.c | ||
122 | +++ b/target/arm/mve_helper.c | ||
123 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
124 | DO_2SHIFT(OP##b, 1, uint8_t, FN) \ | ||
125 | DO_2SHIFT(OP##h, 2, uint16_t, FN) \ | ||
126 | DO_2SHIFT(OP##w, 4, uint32_t, FN) | ||
127 | +#define DO_2SHIFT_S(OP, FN) \ | ||
128 | + DO_2SHIFT(OP##b, 1, int8_t, FN) \ | ||
129 | + DO_2SHIFT(OP##h, 2, int16_t, FN) \ | ||
130 | + DO_2SHIFT(OP##w, 4, int32_t, FN) | ||
131 | |||
132 | #define DO_2SHIFT_SAT_U(OP, FN) \ | ||
133 | DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \ | ||
134 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t) | ||
135 | DO_2SHIFT_SAT(OP##w, 4, int32_t, FN) | ||
136 | |||
137 | DO_2SHIFT_U(vshli_u, DO_VSHLU) | ||
138 | +DO_2SHIFT_S(vshli_s, DO_VSHLS) | ||
139 | DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP) | ||
140 | DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
141 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
142 | +DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
143 | +DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
144 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
145 | index XXXXXXX..XXXXXXX 100644 | ||
146 | --- a/target/arm/translate-mve.c | ||
147 | +++ b/target/arm/translate-mve.c | ||
148 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false) | ||
149 | DO_2SHIFT(VQSHLI_S, vqshli_s, false) | ||
150 | DO_2SHIFT(VQSHLI_U, vqshli_u, false) | ||
151 | DO_2SHIFT(VQSHLUI, vqshlui_s, false) | ||
152 | +/* These right shifts use a left-shift helper with negated shift count */ | ||
153 | +DO_2SHIFT(VSHRI_S, vshli_s, true) | ||
154 | +DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
155 | +DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
156 | +DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
157 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
158 | index XXXXXXX..XXXXXXX 100644 | ||
159 | --- a/target/arm/translate-neon.c | ||
160 | +++ b/target/arm/translate-neon.c | ||
161 | @@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x) | ||
162 | return x + 1; | ||
46 | } | 163 | } |
47 | 164 | ||
48 | static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | 165 | -static inline int rsub_64(DisasContext *s, int x) |
49 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) | 166 | -{ |
50 | * We cannot write 16 bytes at once because the | 167 | - return 64 - x; |
51 | * destination is unaligned. | 168 | -} |
52 | */ | 169 | - |
53 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | 170 | -static inline int rsub_32(DisasContext *s, int x) |
54 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), | 171 | -{ |
55 | 8, 8, tmp); | 172 | - return 32 - x; |
56 | - tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), | 173 | -} |
57 | - neon_reg_offset(vd, 0), 8, 8); | 174 | -static inline int rsub_16(DisasContext *s, int x) |
58 | + tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1), | 175 | -{ |
59 | + neon_full_reg_offset(vd), 8, 8); | 176 | - return 16 - x; |
60 | } else { | 177 | -} |
61 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | 178 | -static inline int rsub_8(DisasContext *s, int x) |
62 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), | 179 | -{ |
63 | vec_size, vec_size, tmp); | 180 | - return 8 - x; |
64 | } | 181 | -} |
65 | tcg_gen_addi_i32(addr, addr, 1 << size); | 182 | - |
66 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) | 183 | static inline int neon_3same_fp_size(DisasContext *s, int x) |
67 | static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) | ||
68 | { | 184 | { |
69 | int vec_size = a->q ? 16 : 8; | 185 | /* Convert 0==fp32, 1==fp16 into a MO_* value */ |
70 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
71 | - int rn_ofs = neon_reg_offset(a->vn, 0); | ||
72 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
73 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
74 | + int rn_ofs = neon_full_reg_offset(a->vn); | ||
75 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
76 | |||
77 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
78 | return false; | ||
79 | @@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) | ||
80 | { | ||
81 | /* Handle a 2-reg-shift insn which can be vectorized. */ | ||
82 | int vec_size = a->q ? 16 : 8; | ||
83 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
84 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
85 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
86 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
87 | |||
88 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
89 | return false; | ||
90 | @@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, | ||
91 | { | ||
92 | /* FP operations in 2-reg-and-shift group */ | ||
93 | int vec_size = a->q ? 16 : 8; | ||
94 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
95 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
96 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
97 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
98 | TCGv_ptr fpst; | ||
99 | |||
100 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
102 | return true; | ||
103 | } | ||
104 | |||
105 | - reg_ofs = neon_reg_offset(a->vd, 0); | ||
106 | + reg_ofs = neon_full_reg_offset(a->vd); | ||
107 | vec_size = a->q ? 16 : 8; | ||
108 | imm = asimd_imm_const(a->imm, a->cmode, a->op); | ||
109 | |||
110 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3diff *a) | ||
111 | return true; | ||
112 | } | ||
113 | |||
114 | - tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), | ||
115 | - neon_reg_offset(a->vn, 0), | ||
116 | - neon_reg_offset(a->vm, 0), | ||
117 | + tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd), | ||
118 | + neon_full_reg_offset(a->vn), | ||
119 | + neon_full_reg_offset(a->vm), | ||
120 | 16, 16, 0, fn_gvec); | ||
121 | return true; | ||
122 | } | ||
123 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, | ||
124 | { | ||
125 | /* Two registers and a scalar, using gvec */ | ||
126 | int vec_size = a->q ? 16 : 8; | ||
127 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
128 | - int rn_ofs = neon_reg_offset(a->vn, 0); | ||
129 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
130 | + int rn_ofs = neon_full_reg_offset(a->vn); | ||
131 | int rm_ofs; | ||
132 | int idx; | ||
133 | TCGv_ptr fpstatus; | ||
134 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2scalar *a, | ||
135 | /* a->vm is M:Vm, which encodes both register and index */ | ||
136 | idx = extract32(a->vm, a->size + 2, 2); | ||
137 | a->vm = extract32(a->vm, 0, a->size + 2); | ||
138 | - rm_ofs = neon_reg_offset(a->vm, 0); | ||
139 | + rm_ofs = neon_full_reg_offset(a->vm); | ||
140 | |||
141 | fpstatus = fpstatus_ptr(a->size == 1 ? FPST_STD_F16 : FPST_STD); | ||
142 | tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus, | ||
143 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
144 | return true; | ||
145 | } | ||
146 | |||
147 | - tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), | ||
148 | + tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd), | ||
149 | neon_element_offset(a->vm, a->index, a->size), | ||
150 | a->q ? 16 : 8, a->q ? 16 : 8); | ||
151 | return true; | ||
152 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
153 | static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) | ||
154 | { | ||
155 | int vec_size = a->q ? 16 : 8; | ||
156 | - int rd_ofs = neon_reg_offset(a->vd, 0); | ||
157 | - int rm_ofs = neon_reg_offset(a->vm, 0); | ||
158 | + int rd_ofs = neon_full_reg_offset(a->vd); | ||
159 | + int rm_ofs = neon_full_reg_offset(a->vm); | ||
160 | |||
161 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
162 | return false; | ||
163 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/target/arm/translate-vfp.c.inc | ||
166 | +++ b/target/arm/translate-vfp.c.inc | ||
167 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
168 | } | ||
169 | |||
170 | tmp = load_reg(s, a->rt); | ||
171 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), | ||
172 | + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn), | ||
173 | vec_size, vec_size, tmp); | ||
174 | tcg_temp_free_i32(tmp); | ||
175 | |||
176 | -- | 186 | -- |
177 | 2.20.1 | 187 | 2.20.1 |
178 | 188 | ||
179 | 189 | diff view generated by jsdifflib |
1 | On some hosts (eg Ubuntu Bionic) pkg-config returns a set of | 1 | Implement the MVE VHLL (vector shift left long) insn. This has two |
---|---|---|---|
2 | libraries for gio-2.0 which don't actually work when compiling | 2 | encodings: the T1 encoding is the usual shift-by-immediate format, |
3 | statically. (Specifically, the returned library string includes | 3 | and the T2 encoding is a special case where the shift count is always |
4 | -lmount, but not -lblkid which -lmount depends upon, so linking | 4 | equal to the element size. |
5 | fails due to missing symbols.) | ||
6 | |||
7 | Check that the libraries work, and don't enable gio if they don't, | ||
8 | in the same way we do for gnutls. | ||
9 | 5 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 8 | Message-id: 20210628135835.6690-10-peter.maydell@linaro.org |
13 | Message-id: 20200928160402.7961-1-peter.maydell@linaro.org | ||
14 | --- | 9 | --- |
15 | configure | 10 +++++++++- | 10 | target/arm/helper-mve.h | 9 +++++++ |
16 | 1 file changed, 9 insertions(+), 1 deletion(-) | 11 | target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++--- |
12 | target/arm/mve_helper.c | 32 +++++++++++++++++++++++ | ||
13 | target/arm/translate-mve.c | 15 +++++++++++ | ||
14 | 4 files changed, 105 insertions(+), 4 deletions(-) | ||
17 | 15 | ||
18 | diff --git a/configure b/configure | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
19 | index XXXXXXX..XXXXXXX 100755 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/configure | 18 | --- a/target/arm/helper-mve.h |
21 | +++ b/configure | 19 | +++ b/target/arm/helper-mve.h |
22 | @@ -XXX,XX +XXX,XX @@ if test "$static" = yes && test "$mingw32" = yes; then | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | fi | 21 | DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | 22 | DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
25 | if $pkg_config --atleast-version=$glib_req_ver gio-2.0; then | 23 | DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | - gio=yes | 24 | + |
27 | gio_cflags=$($pkg_config --cflags gio-2.0) | 25 | +DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | gio_libs=$($pkg_config --libs gio-2.0) | 26 | +DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
29 | gdbus_codegen=$($pkg_config --variable=gdbus_codegen gio-2.0) | 27 | +DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | if [ ! -x "$gdbus_codegen" ]; then | 28 | +DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | gdbus_codegen= | 29 | +DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | fi | 30 | +DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | + # Check that the libraries actually work -- Ubuntu 18.04 ships | 31 | +DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | + # with pkg-config --static --libs data for gio-2.0 that is missing | 32 | +DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
35 | + # -lblkid and will give a link error. | 33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
36 | + write_c_skeleton | 34 | index XXXXXXX..XXXXXXX 100644 |
37 | + if compile_prog "" "gio_libs" ; then | 35 | --- a/target/arm/mve.decode |
38 | + gio=yes | 36 | +++ b/target/arm/mve.decode |
39 | + else | 37 | @@ -XXX,XX +XXX,XX @@ |
40 | + gio=no | 38 | @2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
41 | + fi | 39 | @2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2 |
42 | else | 40 | |
43 | gio=no | 41 | +@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0 |
44 | fi | 42 | +@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1 |
43 | +# VSHLL encoding T2 where shift == esize | ||
44 | +@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \ | ||
45 | + qd=%qd qm=%qm size=0 shift=8 | ||
46 | +@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \ | ||
47 | + qd=%qd qm=%qm size=1 shift=16 | ||
48 | + | ||
49 | # Right shifts are encoded as N - shift, where N is the element size in bits. | ||
50 | %rshift_i5 16:5 !function=rsub_32 | ||
51 | %rshift_i4 16:4 !function=rsub_16 | ||
52 | @@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
53 | VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
54 | VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op | ||
55 | |||
56 | -VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
57 | -VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
58 | +# The VSHLL T2 encoding is not a @2op pattern, but is here because it | ||
59 | +# overlaps what would be size=0b11 VMULH/VRMULH | ||
60 | +{ | ||
61 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
62 | + VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
63 | |||
64 | -VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
65 | -VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
66 | + VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
67 | +} | ||
68 | + | ||
69 | +{ | ||
70 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
71 | + VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
72 | + | ||
73 | + VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
74 | +} | ||
75 | + | ||
76 | +{ | ||
77 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
78 | + VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
79 | + | ||
80 | + VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
81 | +} | ||
82 | + | ||
83 | +{ | ||
84 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b | ||
85 | + VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h | ||
86 | + | ||
87 | + VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op | ||
88 | +} | ||
89 | |||
90 | VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
91 | VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
92 | @@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
93 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b | ||
94 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h | ||
95 | VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w | ||
96 | + | ||
97 | +# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file | ||
98 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b | ||
99 | +VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h | ||
100 | + | ||
101 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b | ||
102 | +VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h | ||
103 | + | ||
104 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | ||
105 | +VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
106 | + | ||
107 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | ||
108 | +VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
109 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/target/arm/mve_helper.c | ||
112 | +++ b/target/arm/mve_helper.c | ||
113 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP) | ||
114 | DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
115 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
116 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
117 | + | ||
118 | +/* | ||
119 | + * Long shifts taking half-sized inputs from top or bottom of the input | ||
120 | + * vector and producing a double-width result. ESIZE, TYPE are for | ||
121 | + * the input, and LESIZE, LTYPE for the output. | ||
122 | + * Unlike the normal shift helpers, we do not handle negative shift counts, | ||
123 | + * because the long shift is strictly left-only. | ||
124 | + */ | ||
125 | +#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \ | ||
126 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
127 | + void *vm, uint32_t shift) \ | ||
128 | + { \ | ||
129 | + LTYPE *d = vd; \ | ||
130 | + TYPE *m = vm; \ | ||
131 | + uint16_t mask = mve_element_mask(env); \ | ||
132 | + unsigned le; \ | ||
133 | + assert(shift <= 16); \ | ||
134 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
135 | + LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \ | ||
136 | + mergemask(&d[H##LESIZE(le)], r, mask); \ | ||
137 | + } \ | ||
138 | + mve_advance_vpt(env); \ | ||
139 | + } | ||
140 | + | ||
141 | +#define DO_VSHLL_ALL(OP, TOP) \ | ||
142 | + DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \ | ||
143 | + DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \ | ||
144 | + DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \ | ||
145 | + DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \ | ||
146 | + | ||
147 | +DO_VSHLL_ALL(vshllb, false) | ||
148 | +DO_VSHLL_ALL(vshllt, true) | ||
149 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
150 | index XXXXXXX..XXXXXXX 100644 | ||
151 | --- a/target/arm/translate-mve.c | ||
152 | +++ b/target/arm/translate-mve.c | ||
153 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true) | ||
154 | DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
155 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
156 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
157 | + | ||
158 | +#define DO_VSHLL(INSN, FN) \ | ||
159 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
160 | + { \ | ||
161 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
162 | + gen_helper_mve_##FN##b, \ | ||
163 | + gen_helper_mve_##FN##h, \ | ||
164 | + }; \ | ||
165 | + return do_2shift(s, a, fns[a->size], false); \ | ||
166 | + } | ||
167 | + | ||
168 | +DO_VSHLL(VSHLL_BS, vshllbs) | ||
169 | +DO_VSHLL(VSHLL_BU, vshllbu) | ||
170 | +DO_VSHLL(VSHLL_TS, vshllts) | ||
171 | +DO_VSHLL(VSHLL_TU, vshlltu) | ||
45 | -- | 172 | -- |
46 | 2.20.1 | 173 | 2.20.1 |
47 | 174 | ||
48 | 175 | diff view generated by jsdifflib |
1 | In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to | 1 | Implement the MVE VSRI and VSLI insns, which perform a |
---|---|---|---|
2 | armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el(). | 2 | shift-and-insert operation. |
3 | This is incorrect when the security state being queried is not the | ||
4 | current one, because arm_current_el() uses the current security state | ||
5 | to determine which of the banked CONTROL.nPRIV bits to look at. | ||
6 | The effect was that if (for instance) Secure state was in privileged | ||
7 | mode but Non-Secure was not then we would return the wrong MMU index. | ||
8 | |||
9 | The only places where we are using this function in a way that could | ||
10 | trigger this bug are for the stack loads during a v8M function-return | ||
11 | and for the instruction fetch of a v8M SG insn. | ||
12 | |||
13 | Fix the bug by expanding out the M-profile version of the | ||
14 | arm_current_el() logic inline so it can use the passed in secstate | ||
15 | rather than env->v7m.secure. | ||
16 | 3 | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
19 | Message-id: 20201022164408.13214-1-peter.maydell@linaro.org | 6 | Message-id: 20210628135835.6690-11-peter.maydell@linaro.org |
20 | --- | 7 | --- |
21 | target/arm/m_helper.c | 3 ++- | 8 | target/arm/helper-mve.h | 8 ++++++++ |
22 | 1 file changed, 2 insertions(+), 1 deletion(-) | 9 | target/arm/mve.decode | 9 ++++++++ |
10 | target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-mve.c | 3 +++ | ||
12 | 4 files changed, 62 insertions(+) | ||
23 | 13 | ||
24 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
25 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/m_helper.c | 16 | --- a/target/arm/helper-mve.h |
27 | +++ b/target/arm/m_helper.c | 17 | +++ b/target/arm/helper-mve.h |
28 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
29 | /* Return the MMU index for a v7M CPU in the specified security state */ | 19 | DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 20 | DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | { | 21 | DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | - bool priv = arm_current_el(env) != 0; | 22 | + |
33 | + bool priv = arm_v7m_is_handler_mode(env) || | 23 | +DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | + !(env->v7m.control[secstate] & 1); | 24 | +DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
35 | 25 | +DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
36 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); | 26 | + |
37 | } | 27 | +DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | +DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
30 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/mve.decode | ||
33 | +++ b/target/arm/mve.decode | ||
34 | @@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
35 | |||
36 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b | ||
37 | VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h | ||
38 | + | ||
39 | +# Shift-and-insert | ||
40 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b | ||
41 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h | ||
42 | +VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | ||
43 | + | ||
44 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
45 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
46 | +VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
47 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/mve_helper.c | ||
50 | +++ b/target/arm/mve_helper.c | ||
51 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP) | ||
52 | DO_2SHIFT_U(vrshli_u, DO_VRSHLU) | ||
53 | DO_2SHIFT_S(vrshli_s, DO_VRSHLS) | ||
54 | |||
55 | +/* Shift-and-insert; we always work with 64 bits at a time */ | ||
56 | +#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \ | ||
57 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
58 | + void *vm, uint32_t shift) \ | ||
59 | + { \ | ||
60 | + uint64_t *d = vd, *m = vm; \ | ||
61 | + uint16_t mask; \ | ||
62 | + uint64_t shiftmask; \ | ||
63 | + unsigned e; \ | ||
64 | + if (shift == 0 || shift == ESIZE * 8) { \ | ||
65 | + /* \ | ||
66 | + * Only VSLI can shift by 0; only VSRI can shift by <dt>. \ | ||
67 | + * The generic logic would give the right answer for 0 but \ | ||
68 | + * fails for <dt>. \ | ||
69 | + */ \ | ||
70 | + goto done; \ | ||
71 | + } \ | ||
72 | + assert(shift < ESIZE * 8); \ | ||
73 | + mask = mve_element_mask(env); \ | ||
74 | + /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \ | ||
75 | + shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \ | ||
76 | + for (e = 0; e < 16 / 8; e++, mask >>= 8) { \ | ||
77 | + uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \ | ||
78 | + (d[H8(e)] & ~shiftmask); \ | ||
79 | + mergemask(&d[H8(e)], r, mask); \ | ||
80 | + } \ | ||
81 | +done: \ | ||
82 | + mve_advance_vpt(env); \ | ||
83 | + } | ||
84 | + | ||
85 | +#define DO_SHL(N, SHIFT) ((N) << (SHIFT)) | ||
86 | +#define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) | ||
87 | +#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) | ||
88 | +#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) | ||
89 | + | ||
90 | +DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK) | ||
91 | +DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK) | ||
92 | +DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK) | ||
93 | +DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK) | ||
94 | +DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK) | ||
95 | +DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | ||
96 | + | ||
97 | /* | ||
98 | * Long shifts taking half-sized inputs from top or bottom of the input | ||
99 | * vector and producing a double-width result. ESIZE, TYPE are for | ||
100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/target/arm/translate-mve.c | ||
103 | +++ b/target/arm/translate-mve.c | ||
104 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true) | ||
105 | DO_2SHIFT(VRSHRI_S, vrshli_s, true) | ||
106 | DO_2SHIFT(VRSHRI_U, vrshli_u, true) | ||
107 | |||
108 | +DO_2SHIFT(VSRI, vsri, false) | ||
109 | +DO_2SHIFT(VSLI, vsli, false) | ||
110 | + | ||
111 | #define DO_VSHLL(INSN, FN) \ | ||
112 | static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
113 | { \ | ||
38 | -- | 114 | -- |
39 | 2.20.1 | 115 | 2.20.1 |
40 | 116 | ||
41 | 117 | diff view generated by jsdifflib |
1 | The helper functions for performing the udot/sdot operations against | 1 | Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN. |
---|---|---|---|
2 | a scalar were not using an address-swizzling macro when converting | ||
3 | the index of the scalar element into a pointer into the vm array. | ||
4 | This had no effect on little-endian hosts but meant we generated | ||
5 | incorrect results on big-endian hosts. | ||
6 | 2 | ||
7 | For these insns, the index is indexing over group of 4 8-bit values, | 3 | do_urshr() is borrowed from sve_helper.c. |
8 | so 32 bits per indexed entity, and H4() is therefore what we want. | ||
9 | (For Neon the only possible input indexes are 0 and 1.) | ||
10 | 4 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Message-id: 20210628135835.6690-12-peter.maydell@linaro.org |
14 | Message-id: 20201028191712.4910-3-peter.maydell@linaro.org | ||
15 | --- | 8 | --- |
16 | target/arm/vec_helper.c | 4 ++-- | 9 | target/arm/helper-mve.h | 10 ++++++++++ |
17 | 1 file changed, 2 insertions(+), 2 deletions(-) | 10 | target/arm/mve.decode | 11 +++++++++++ |
11 | target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++ | ||
12 | target/arm/translate-mve.c | 15 ++++++++++++++ | ||
13 | 4 files changed, 76 insertions(+) | ||
18 | 14 | ||
19 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
20 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/vec_helper.c | 17 | --- a/target/arm/helper-mve.h |
22 | +++ b/target/arm/vec_helper.c | 18 | +++ b/target/arm/helper-mve.h |
23 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | intptr_t index = simd_data(desc); | 20 | DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | uint32_t *d = vd; | 21 | DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | int8_t *n = vn; | 22 | DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | - int8_t *m_indexed = (int8_t *)vm + index * 4; | 23 | + |
28 | + int8_t *m_indexed = (int8_t *)vm + H4(index) * 4; | 24 | +DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
29 | 25 | +DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
30 | /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. | 26 | +DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | * Otherwise opr_sz is a multiple of 16. | 27 | +DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc) | 28 | + |
33 | intptr_t index = simd_data(desc); | 29 | +DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | uint32_t *d = vd; | 30 | +DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
35 | uint8_t *n = vn; | 31 | +DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
36 | - uint8_t *m_indexed = (uint8_t *)vm + index * 4; | 32 | +DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
37 | + uint8_t *m_indexed = (uint8_t *)vm + H4(index) * 4; | 33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
38 | 34 | index XXXXXXX..XXXXXXX 100644 | |
39 | /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd. | 35 | --- a/target/arm/mve.decode |
40 | * Otherwise opr_sz is a multiple of 16. | 36 | +++ b/target/arm/mve.decode |
37 | @@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w | ||
38 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b | ||
39 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h | ||
40 | VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w | ||
41 | + | ||
42 | +# Narrowing shifts (which only support b and h sizes) | ||
43 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
44 | +VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
45 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
46 | +VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
47 | + | ||
48 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
49 | +VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
50 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
51 | +VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/mve_helper.c | ||
55 | +++ b/target/arm/mve_helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK) | ||
57 | |||
58 | DO_VSHLL_ALL(vshllb, false) | ||
59 | DO_VSHLL_ALL(vshllt, true) | ||
60 | + | ||
61 | +/* | ||
62 | + * Narrowing right shifts, taking a double sized input, shifting it | ||
63 | + * and putting the result in either the top or bottom half of the output. | ||
64 | + * ESIZE, TYPE are the output, and LESIZE, LTYPE the input. | ||
65 | + */ | ||
66 | +#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ | ||
67 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
68 | + void *vm, uint32_t shift) \ | ||
69 | + { \ | ||
70 | + LTYPE *m = vm; \ | ||
71 | + TYPE *d = vd; \ | ||
72 | + uint16_t mask = mve_element_mask(env); \ | ||
73 | + unsigned le; \ | ||
74 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
75 | + TYPE r = FN(m[H##LESIZE(le)], shift); \ | ||
76 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ | ||
77 | + } \ | ||
78 | + mve_advance_vpt(env); \ | ||
79 | + } | ||
80 | + | ||
81 | +#define DO_VSHRN_ALL(OP, FN) \ | ||
82 | + DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \ | ||
83 | + DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \ | ||
84 | + DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \ | ||
85 | + DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN) | ||
86 | + | ||
87 | +static inline uint64_t do_urshr(uint64_t x, unsigned sh) | ||
88 | +{ | ||
89 | + if (likely(sh < 64)) { | ||
90 | + return (x >> sh) + ((x >> (sh - 1)) & 1); | ||
91 | + } else if (sh == 64) { | ||
92 | + return x >> 63; | ||
93 | + } else { | ||
94 | + return 0; | ||
95 | + } | ||
96 | +} | ||
97 | + | ||
98 | +DO_VSHRN_ALL(vshrn, DO_SHR) | ||
99 | +DO_VSHRN_ALL(vrshrn, do_urshr) | ||
100 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
101 | index XXXXXXX..XXXXXXX 100644 | ||
102 | --- a/target/arm/translate-mve.c | ||
103 | +++ b/target/arm/translate-mve.c | ||
104 | @@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs) | ||
105 | DO_VSHLL(VSHLL_BU, vshllbu) | ||
106 | DO_VSHLL(VSHLL_TS, vshllts) | ||
107 | DO_VSHLL(VSHLL_TU, vshlltu) | ||
108 | + | ||
109 | +#define DO_2SHIFT_N(INSN, FN) \ | ||
110 | + static bool trans_##INSN(DisasContext *s, arg_2shift *a) \ | ||
111 | + { \ | ||
112 | + static MVEGenTwoOpShiftFn * const fns[] = { \ | ||
113 | + gen_helper_mve_##FN##b, \ | ||
114 | + gen_helper_mve_##FN##h, \ | ||
115 | + }; \ | ||
116 | + return do_2shift(s, a, fns[a->size], false); \ | ||
117 | + } | ||
118 | + | ||
119 | +DO_2SHIFT_N(VSHRNB, vshrnb) | ||
120 | +DO_2SHIFT_N(VSHRNT, vshrnt) | ||
121 | +DO_2SHIFT_N(VRSHRNB, vrshrnb) | ||
122 | +DO_2SHIFT_N(VRSHRNT, vrshrnt) | ||
41 | -- | 123 | -- |
42 | 2.20.1 | 124 | 2.20.1 |
43 | 125 | ||
44 | 126 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE saturating shift-right-and-narrow insns |
---|---|---|---|
2 | 2 | VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN. | |
3 | Replace all uses of neon_load/store_reg64 within translate-neon.c.inc. | 3 | |
4 | 4 | do_srshr() is borrowed from sve_helper.c. | |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | |
6 | Message-id: 20201030022618.785675-9-richard.henderson@linaro.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210628135835.6690-13-peter.maydell@linaro.org | ||
9 | --- | 9 | --- |
10 | target/arm/translate.c | 26 +++++++++ | 10 | target/arm/helper-mve.h | 30 +++++++++++ |
11 | target/arm/translate-neon.c.inc | 94 ++++++++++++++++----------------- | 11 | target/arm/mve.decode | 28 ++++++++++ |
12 | 2 files changed, 73 insertions(+), 47 deletions(-) | 12 | target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++ |
13 | 13 | target/arm/translate-mve.c | 12 +++++ | |
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 14 | 4 files changed, 174 insertions(+) |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | |
16 | --- a/target/arm/translate.c | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
17 | +++ b/target/arm/translate.c | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop) | 18 | --- a/target/arm/helper-mve.h |
19 | +++ b/target/arm/helper-mve.h | ||
20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
21 | DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
22 | DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
23 | DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
24 | + | ||
25 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
26 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
29 | + | ||
30 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | +DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
34 | + | ||
35 | +DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
36 | +DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
37 | +DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
38 | +DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | + | ||
40 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
42 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
43 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
44 | + | ||
45 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
46 | +DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
47 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
48 | +DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
49 | + | ||
50 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
51 | +DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
52 | +DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
53 | +DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
54 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/arm/mve.decode | ||
57 | +++ b/target/arm/mve.decode | ||
58 | @@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b | ||
59 | VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h | ||
60 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b | ||
61 | VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h | ||
62 | + | ||
63 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b | ||
64 | +VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h | ||
65 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b | ||
66 | +VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h | ||
67 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b | ||
68 | +VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h | ||
69 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b | ||
70 | +VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h | ||
71 | + | ||
72 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
73 | +VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
74 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
75 | +VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
76 | + | ||
77 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b | ||
78 | +VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h | ||
79 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b | ||
80 | +VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h | ||
81 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b | ||
82 | +VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h | ||
83 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b | ||
84 | +VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h | ||
85 | + | ||
86 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b | ||
87 | +VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h | ||
88 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b | ||
89 | +VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | ||
90 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/target/arm/mve_helper.c | ||
93 | +++ b/target/arm/mve_helper.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh) | ||
19 | } | 95 | } |
20 | } | 96 | } |
21 | 97 | ||
22 | +static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | 98 | +static inline int64_t do_srshr(int64_t x, unsigned sh) |
23 | +{ | 99 | +{ |
24 | + long off = neon_element_offset(reg, ele, memop); | 100 | + if (likely(sh < 64)) { |
25 | + | 101 | + return (x >> sh) + ((x >> (sh - 1)) & 1); |
26 | + switch (memop) { | 102 | + } else { |
27 | + case MO_Q: | 103 | + /* Rounding the sign bit always produces 0. */ |
28 | + tcg_gen_ld_i64(dest, cpu_env, off); | 104 | + return 0; |
29 | + break; | ||
30 | + default: | ||
31 | + g_assert_not_reached(); | ||
32 | + } | 105 | + } |
33 | +} | 106 | +} |
34 | + | 107 | + |
35 | static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | 108 | DO_VSHRN_ALL(vshrn, DO_SHR) |
36 | { | 109 | DO_VSHRN_ALL(vrshrn, do_urshr) |
37 | long off = neon_element_offset(reg, ele, memop); | 110 | + |
38 | @@ -XXX,XX +XXX,XX @@ static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop) | 111 | +static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max, |
39 | } | 112 | + bool *satp) |
40 | } | ||
41 | |||
42 | +static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) | ||
43 | +{ | 113 | +{ |
44 | + long off = neon_element_offset(reg, ele, memop); | 114 | + if (val > max) { |
45 | + | 115 | + *satp = true; |
46 | + switch (memop) { | 116 | + return max; |
47 | + case MO_64: | 117 | + } else if (val < min) { |
48 | + tcg_gen_st_i64(src, cpu_env, off); | 118 | + *satp = true; |
49 | + break; | 119 | + return min; |
50 | + default: | 120 | + } else { |
51 | + g_assert_not_reached(); | 121 | + return val; |
52 | + } | 122 | + } |
53 | +} | 123 | +} |
54 | + | 124 | + |
55 | static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | 125 | +/* Saturating narrowing right shifts */ |
56 | { | 126 | +#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ |
57 | TCGv_ptr ret = tcg_temp_new_ptr(); | 127 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ |
58 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | 128 | + void *vm, uint32_t shift) \ |
59 | index XXXXXXX..XXXXXXX 100644 | 129 | + { \ |
60 | --- a/target/arm/translate-neon.c.inc | 130 | + LTYPE *m = vm; \ |
61 | +++ b/target/arm/translate-neon.c.inc | 131 | + TYPE *d = vd; \ |
62 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, | 132 | + uint16_t mask = mve_element_mask(env); \ |
63 | for (pass = 0; pass < a->q + 1; pass++) { | 133 | + bool qc = false; \ |
64 | TCGv_i64 tmp = tcg_temp_new_i64(); | 134 | + unsigned le; \ |
65 | 135 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | |
66 | - neon_load_reg64(tmp, a->vm + pass); | 136 | + bool sat = false; \ |
67 | + read_neon_element64(tmp, a->vm, pass, MO_64); | 137 | + TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \ |
68 | fn(tmp, cpu_env, tmp, constimm); | 138 | + mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \ |
69 | - neon_store_reg64(tmp, a->vd + pass); | 139 | + qc |= sat && (mask & 1 << (TOP * ESIZE)); \ |
70 | + write_neon_element64(tmp, a->vd, pass, MO_64); | 140 | + } \ |
71 | tcg_temp_free_i64(tmp); | 141 | + if (qc) { \ |
72 | } | 142 | + env->vfp.qc[0] = qc; \ |
73 | tcg_temp_free_i64(constimm); | 143 | + } \ |
74 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, | 144 | + mve_advance_vpt(env); \ |
75 | rd = tcg_temp_new_i32(); | 145 | + } |
76 | 146 | + | |
77 | /* Load both inputs first to avoid potential overwrite if rm == rd */ | 147 | +#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \ |
78 | - neon_load_reg64(rm1, a->vm); | 148 | + DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \ |
79 | - neon_load_reg64(rm2, a->vm + 1); | 149 | + DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN) |
80 | + read_neon_element64(rm1, a->vm, 0, MO_64); | 150 | + |
81 | + read_neon_element64(rm2, a->vm, 1, MO_64); | 151 | +#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \ |
82 | 152 | + DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \ | |
83 | shiftfn(rm1, rm1, constimm); | 153 | + DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN) |
84 | narrowfn(rd, cpu_env, rm1); | 154 | + |
85 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | 155 | +#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \ |
86 | tcg_gen_shli_i64(tmp, tmp, a->shift); | 156 | + DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \ |
87 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | 157 | + DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN) |
88 | } | 158 | + |
89 | - neon_store_reg64(tmp, a->vd); | 159 | +#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \ |
90 | + write_neon_element64(tmp, a->vd, 0, MO_64); | 160 | + DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \ |
91 | 161 | + DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN) | |
92 | widenfn(tmp, rm1); | 162 | + |
93 | tcg_temp_free_i32(rm1); | 163 | +#define DO_SHRN_SB(N, M, SATP) \ |
94 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | 164 | + do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP) |
95 | tcg_gen_shli_i64(tmp, tmp, a->shift); | 165 | +#define DO_SHRN_UB(N, M, SATP) \ |
96 | tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | 166 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP) |
97 | } | 167 | +#define DO_SHRUN_B(N, M, SATP) \ |
98 | - neon_store_reg64(tmp, a->vd + 1); | 168 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP) |
99 | + write_neon_element64(tmp, a->vd, 1, MO_64); | 169 | + |
100 | tcg_temp_free_i64(tmp); | 170 | +#define DO_SHRN_SH(N, M, SATP) \ |
101 | return true; | 171 | + do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP) |
102 | } | 172 | +#define DO_SHRN_UH(N, M, SATP) \ |
103 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | 173 | + do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP) |
104 | rm_64 = tcg_temp_new_i64(); | 174 | +#define DO_SHRUN_H(N, M, SATP) \ |
105 | 175 | + do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP) | |
106 | if (src1_wide) { | 176 | + |
107 | - neon_load_reg64(rn0_64, a->vn); | 177 | +#define DO_RSHRN_SB(N, M, SATP) \ |
108 | + read_neon_element64(rn0_64, a->vn, 0, MO_64); | 178 | + do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP) |
109 | } else { | 179 | +#define DO_RSHRN_UB(N, M, SATP) \ |
110 | TCGv_i32 tmp = tcg_temp_new_i32(); | 180 | + do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP) |
111 | read_neon_element32(tmp, a->vn, 0, MO_32); | 181 | +#define DO_RSHRUN_B(N, M, SATP) \ |
112 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | 182 | + do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP) |
113 | * avoid incorrect results if a narrow input overlaps with the result. | 183 | + |
114 | */ | 184 | +#define DO_RSHRN_SH(N, M, SATP) \ |
115 | if (src1_wide) { | 185 | + do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP) |
116 | - neon_load_reg64(rn1_64, a->vn + 1); | 186 | +#define DO_RSHRN_UH(N, M, SATP) \ |
117 | + read_neon_element64(rn1_64, a->vn, 1, MO_64); | 187 | + do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP) |
118 | } else { | 188 | +#define DO_RSHRUN_H(N, M, SATP) \ |
119 | TCGv_i32 tmp = tcg_temp_new_i32(); | 189 | + do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP) |
120 | read_neon_element32(tmp, a->vn, 1, MO_32); | 190 | + |
121 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | 191 | +DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB) |
122 | rm = tcg_temp_new_i32(); | 192 | +DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH) |
123 | read_neon_element32(rm, a->vm, 1, MO_32); | 193 | +DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB) |
124 | 194 | +DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH) | |
125 | - neon_store_reg64(rn0_64, a->vd); | 195 | +DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B) |
126 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | 196 | +DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H) |
127 | 197 | + | |
128 | widenfn(rm_64, rm); | 198 | +DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB) |
129 | tcg_temp_free_i32(rm); | 199 | +DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH) |
130 | opfn(rn1_64, rn1_64, rm_64); | 200 | +DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) |
131 | - neon_store_reg64(rn1_64, a->vd + 1); | 201 | +DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) |
132 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | 202 | +DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) |
133 | 203 | +DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) | |
134 | tcg_temp_free_i64(rn0_64); | 204 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
135 | tcg_temp_free_i64(rn1_64); | 205 | index XXXXXXX..XXXXXXX 100644 |
136 | @@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | 206 | --- a/target/arm/translate-mve.c |
137 | rd0 = tcg_temp_new_i32(); | 207 | +++ b/target/arm/translate-mve.c |
138 | rd1 = tcg_temp_new_i32(); | 208 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb) |
139 | 209 | DO_2SHIFT_N(VSHRNT, vshrnt) | |
140 | - neon_load_reg64(rn_64, a->vn); | 210 | DO_2SHIFT_N(VRSHRNB, vrshrnb) |
141 | - neon_load_reg64(rm_64, a->vm); | 211 | DO_2SHIFT_N(VRSHRNT, vrshrnt) |
142 | + read_neon_element64(rn_64, a->vn, 0, MO_64); | 212 | +DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s) |
143 | + read_neon_element64(rm_64, a->vm, 0, MO_64); | 213 | +DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s) |
144 | 214 | +DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u) | |
145 | opfn(rn_64, rn_64, rm_64); | 215 | +DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u) |
146 | 216 | +DO_2SHIFT_N(VQSHRUNB, vqshrunb) | |
147 | narrowfn(rd0, rn_64); | 217 | +DO_2SHIFT_N(VQSHRUNT, vqshrunt) |
148 | 218 | +DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s) | |
149 | - neon_load_reg64(rn_64, a->vn + 1); | 219 | +DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s) |
150 | - neon_load_reg64(rm_64, a->vm + 1); | 220 | +DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) |
151 | + read_neon_element64(rn_64, a->vn, 1, MO_64); | 221 | +DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) |
152 | + read_neon_element64(rm_64, a->vm, 1, MO_64); | 222 | +DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) |
153 | 223 | +DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | |
154 | opfn(rn_64, rn_64, rm_64); | ||
155 | |||
156 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
157 | /* Don't store results until after all loads: they might overlap */ | ||
158 | if (accfn) { | ||
159 | tmp = tcg_temp_new_i64(); | ||
160 | - neon_load_reg64(tmp, a->vd); | ||
161 | + read_neon_element64(tmp, a->vd, 0, MO_64); | ||
162 | accfn(tmp, tmp, rd0); | ||
163 | - neon_store_reg64(tmp, a->vd); | ||
164 | - neon_load_reg64(tmp, a->vd + 1); | ||
165 | + write_neon_element64(tmp, a->vd, 0, MO_64); | ||
166 | + read_neon_element64(tmp, a->vd, 1, MO_64); | ||
167 | accfn(tmp, tmp, rd1); | ||
168 | - neon_store_reg64(tmp, a->vd + 1); | ||
169 | + write_neon_element64(tmp, a->vd, 1, MO_64); | ||
170 | tcg_temp_free_i64(tmp); | ||
171 | } else { | ||
172 | - neon_store_reg64(rd0, a->vd); | ||
173 | - neon_store_reg64(rd1, a->vd + 1); | ||
174 | + write_neon_element64(rd0, a->vd, 0, MO_64); | ||
175 | + write_neon_element64(rd1, a->vd, 1, MO_64); | ||
176 | } | ||
177 | |||
178 | tcg_temp_free_i64(rd0); | ||
179 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
180 | |||
181 | if (accfn) { | ||
182 | TCGv_i64 t64 = tcg_temp_new_i64(); | ||
183 | - neon_load_reg64(t64, a->vd); | ||
184 | + read_neon_element64(t64, a->vd, 0, MO_64); | ||
185 | accfn(t64, t64, rn0_64); | ||
186 | - neon_store_reg64(t64, a->vd); | ||
187 | - neon_load_reg64(t64, a->vd + 1); | ||
188 | + write_neon_element64(t64, a->vd, 0, MO_64); | ||
189 | + read_neon_element64(t64, a->vd, 1, MO_64); | ||
190 | accfn(t64, t64, rn1_64); | ||
191 | - neon_store_reg64(t64, a->vd + 1); | ||
192 | + write_neon_element64(t64, a->vd, 1, MO_64); | ||
193 | tcg_temp_free_i64(t64); | ||
194 | } else { | ||
195 | - neon_store_reg64(rn0_64, a->vd); | ||
196 | - neon_store_reg64(rn1_64, a->vd + 1); | ||
197 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
198 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
199 | } | ||
200 | tcg_temp_free_i64(rn0_64); | ||
201 | tcg_temp_free_i64(rn1_64); | ||
202 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
203 | right = tcg_temp_new_i64(); | ||
204 | dest = tcg_temp_new_i64(); | ||
205 | |||
206 | - neon_load_reg64(right, a->vn); | ||
207 | - neon_load_reg64(left, a->vm); | ||
208 | + read_neon_element64(right, a->vn, 0, MO_64); | ||
209 | + read_neon_element64(left, a->vm, 0, MO_64); | ||
210 | tcg_gen_extract2_i64(dest, right, left, a->imm * 8); | ||
211 | - neon_store_reg64(dest, a->vd); | ||
212 | + write_neon_element64(dest, a->vd, 0, MO_64); | ||
213 | |||
214 | tcg_temp_free_i64(left); | ||
215 | tcg_temp_free_i64(right); | ||
216 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
217 | destright = tcg_temp_new_i64(); | ||
218 | |||
219 | if (a->imm < 8) { | ||
220 | - neon_load_reg64(right, a->vn); | ||
221 | - neon_load_reg64(middle, a->vn + 1); | ||
222 | + read_neon_element64(right, a->vn, 0, MO_64); | ||
223 | + read_neon_element64(middle, a->vn, 1, MO_64); | ||
224 | tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); | ||
225 | - neon_load_reg64(left, a->vm); | ||
226 | + read_neon_element64(left, a->vm, 0, MO_64); | ||
227 | tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); | ||
228 | } else { | ||
229 | - neon_load_reg64(right, a->vn + 1); | ||
230 | - neon_load_reg64(middle, a->vm); | ||
231 | + read_neon_element64(right, a->vn, 1, MO_64); | ||
232 | + read_neon_element64(middle, a->vm, 0, MO_64); | ||
233 | tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * 8); | ||
234 | - neon_load_reg64(left, a->vm + 1); | ||
235 | + read_neon_element64(left, a->vm, 1, MO_64); | ||
236 | tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); | ||
237 | } | ||
238 | |||
239 | - neon_store_reg64(destright, a->vd); | ||
240 | - neon_store_reg64(destleft, a->vd + 1); | ||
241 | + write_neon_element64(destright, a->vd, 0, MO_64); | ||
242 | + write_neon_element64(destleft, a->vd, 1, MO_64); | ||
243 | |||
244 | tcg_temp_free_i64(destright); | ||
245 | tcg_temp_free_i64(destleft); | ||
246 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
247 | |||
248 | if (accfn) { | ||
249 | TCGv_i64 tmp64 = tcg_temp_new_i64(); | ||
250 | - neon_load_reg64(tmp64, a->vd + pass); | ||
251 | + read_neon_element64(tmp64, a->vd, pass, MO_64); | ||
252 | accfn(rd_64, tmp64, rd_64); | ||
253 | tcg_temp_free_i64(tmp64); | ||
254 | } | ||
255 | - neon_store_reg64(rd_64, a->vd + pass); | ||
256 | + write_neon_element64(rd_64, a->vd, pass, MO_64); | ||
257 | tcg_temp_free_i64(rd_64); | ||
258 | } | ||
259 | return true; | ||
260 | @@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
261 | rd0 = tcg_temp_new_i32(); | ||
262 | rd1 = tcg_temp_new_i32(); | ||
263 | |||
264 | - neon_load_reg64(rm, a->vm); | ||
265 | + read_neon_element64(rm, a->vm, 0, MO_64); | ||
266 | narrowfn(rd0, cpu_env, rm); | ||
267 | - neon_load_reg64(rm, a->vm + 1); | ||
268 | + read_neon_element64(rm, a->vm, 1, MO_64); | ||
269 | narrowfn(rd1, cpu_env, rm); | ||
270 | write_neon_element32(rd0, a->vd, 0, MO_32); | ||
271 | write_neon_element32(rd1, a->vd, 1, MO_32); | ||
272 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
273 | |||
274 | widenfn(rd, rm0); | ||
275 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
276 | - neon_store_reg64(rd, a->vd); | ||
277 | + write_neon_element64(rd, a->vd, 0, MO_64); | ||
278 | widenfn(rd, rm1); | ||
279 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
280 | - neon_store_reg64(rd, a->vd + 1); | ||
281 | + write_neon_element64(rd, a->vd, 1, MO_64); | ||
282 | |||
283 | tcg_temp_free_i64(rd); | ||
284 | tcg_temp_free_i32(rm0); | ||
285 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a) | ||
286 | rm = tcg_temp_new_i64(); | ||
287 | rd = tcg_temp_new_i64(); | ||
288 | for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
289 | - neon_load_reg64(rm, a->vm + pass); | ||
290 | - neon_load_reg64(rd, a->vd + pass); | ||
291 | - neon_store_reg64(rm, a->vd + pass); | ||
292 | - neon_store_reg64(rd, a->vm + pass); | ||
293 | + read_neon_element64(rm, a->vm, pass, MO_64); | ||
294 | + read_neon_element64(rd, a->vd, pass, MO_64); | ||
295 | + write_neon_element64(rm, a->vd, pass, MO_64); | ||
296 | + write_neon_element64(rd, a->vm, pass, MO_64); | ||
297 | } | ||
298 | tcg_temp_free_i64(rm); | ||
299 | tcg_temp_free_i64(rd); | ||
300 | -- | 224 | -- |
301 | 2.20.1 | 225 | 2.20.1 |
302 | 226 | ||
303 | 227 | diff view generated by jsdifflib |
1 | In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error | 1 | Implement the MVE VSHLC insn, which performs a shift left of the |
---|---|---|---|
2 | meant we were using the H4() address swizzler macro rather than the | 2 | entire vector with carry in bits provided from a general purpose |
3 | H2() which is required for 2-byte data. This had no effect on | 3 | register and carry out bits written back to that register. |
4 | little-endian hosts but meant we put the result data into the | ||
5 | destination Dreg in the wrong order on big-endian hosts. | ||
6 | 4 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Message-id: 20210628135835.6690-14-peter.maydell@linaro.org |
10 | Message-id: 20201028191712.4910-2-peter.maydell@linaro.org | ||
11 | --- | 8 | --- |
12 | target/arm/vec_helper.c | 8 ++++---- | 9 | target/arm/helper-mve.h | 2 ++ |
13 | 1 file changed, 4 insertions(+), 4 deletions(-) | 10 | target/arm/mve.decode | 2 ++ |
11 | target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++ | ||
12 | target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++ | ||
13 | 4 files changed, 72 insertions(+) | ||
14 | 14 | ||
15 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/vec_helper.c | 17 | --- a/target/arm/helper-mve.h |
18 | +++ b/target/arm/vec_helper.c | 18 | +++ b/target/arm/helper-mve.h |
19 | @@ -XXX,XX +XXX,XX @@ DO_ABA(gvec_uaba_d, uint64_t) | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
20 | r2 = float16_##OP(m[H2(0)], m[H2(1)], fpst); \ | 20 | DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
21 | r3 = float16_##OP(m[H2(2)], m[H2(3)], fpst); \ | 21 | DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | \ | 22 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | - d[H4(0)] = r0; \ | 23 | + |
24 | - d[H4(1)] = r1; \ | 24 | +DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) |
25 | - d[H4(2)] = r2; \ | 25 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
26 | - d[H4(3)] = r3; \ | 26 | index XXXXXXX..XXXXXXX 100644 |
27 | + d[H2(0)] = r0; \ | 27 | --- a/target/arm/mve.decode |
28 | + d[H2(1)] = r1; \ | 28 | +++ b/target/arm/mve.decode |
29 | + d[H2(2)] = r2; \ | 29 | @@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b |
30 | + d[H2(3)] = r3; \ | 30 | VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h |
31 | } | 31 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b |
32 | 32 | VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h | |
33 | DO_NEON_PAIRWISE(neon_padd, add) | 33 | + |
34 | +VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd | ||
35 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/mve_helper.c | ||
38 | +++ b/target/arm/mve_helper.c | ||
39 | @@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB) | ||
40 | DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH) | ||
41 | DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B) | ||
42 | DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H) | ||
43 | + | ||
44 | +uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
45 | + uint32_t shift) | ||
46 | +{ | ||
47 | + uint32_t *d = vd; | ||
48 | + uint16_t mask = mve_element_mask(env); | ||
49 | + unsigned e; | ||
50 | + uint32_t r; | ||
51 | + | ||
52 | + /* | ||
53 | + * For each 32-bit element, we shift it left, bringing in the | ||
54 | + * low 'shift' bits of rdm at the bottom. Bits shifted out at | ||
55 | + * the top become the new rdm, if the predicate mask permits. | ||
56 | + * The final rdm value is returned to update the register. | ||
57 | + * shift == 0 here means "shift by 32 bits". | ||
58 | + */ | ||
59 | + if (shift == 0) { | ||
60 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
61 | + r = rdm; | ||
62 | + if (mask & 1) { | ||
63 | + rdm = d[H4(e)]; | ||
64 | + } | ||
65 | + mergemask(&d[H4(e)], r, mask); | ||
66 | + } | ||
67 | + } else { | ||
68 | + uint32_t shiftmask = MAKE_64BIT_MASK(0, shift); | ||
69 | + | ||
70 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
71 | + r = (d[H4(e)] << shift) | (rdm & shiftmask); | ||
72 | + if (mask & 1) { | ||
73 | + rdm = d[H4(e)] >> (32 - shift); | ||
74 | + } | ||
75 | + mergemask(&d[H4(e)], r, mask); | ||
76 | + } | ||
77 | + } | ||
78 | + mve_advance_vpt(env); | ||
79 | + return rdm; | ||
80 | +} | ||
81 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/target/arm/translate-mve.c | ||
84 | +++ b/target/arm/translate-mve.c | ||
85 | @@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u) | ||
86 | DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u) | ||
87 | DO_2SHIFT_N(VQRSHRUNB, vqrshrunb) | ||
88 | DO_2SHIFT_N(VQRSHRUNT, vqrshrunt) | ||
89 | + | ||
90 | +static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) | ||
91 | +{ | ||
92 | + /* | ||
93 | + * Whole Vector Left Shift with Carry. The carry is taken | ||
94 | + * from a general purpose register and written back there. | ||
95 | + * An imm of 0 means "shift by 32". | ||
96 | + */ | ||
97 | + TCGv_ptr qd; | ||
98 | + TCGv_i32 rdm; | ||
99 | + | ||
100 | + if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) { | ||
101 | + return false; | ||
102 | + } | ||
103 | + if (a->rdm == 13 || a->rdm == 15) { | ||
104 | + /* CONSTRAINED UNPREDICTABLE: we UNDEF */ | ||
105 | + return false; | ||
106 | + } | ||
107 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
108 | + return true; | ||
109 | + } | ||
110 | + | ||
111 | + qd = mve_qreg_ptr(a->qd); | ||
112 | + rdm = load_reg(s, a->rdm); | ||
113 | + gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); | ||
114 | + store_reg(s, a->rdm, rdm); | ||
115 | + tcg_temp_free_ptr(qd); | ||
116 | + mve_update_eci(s); | ||
117 | + return true; | ||
118 | +} | ||
34 | -- | 119 | -- |
35 | 2.20.1 | 120 | 2.20.1 |
36 | 121 | ||
37 | 122 | diff view generated by jsdifflib |
1 | In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt | 1 | Implement the MVE VADDLV insn; this is similar to VADDV, except |
---|---|---|---|
2 | into the GICv3CPUState struct's maintenance_irq field. This will | 2 | that it accumulates 32-bit elements into a 64-bit accumulator |
3 | only work if the board happens to have already wired up the CPU | 3 | stored in a pair of general-purpose registers. |
4 | maintenance IRQ before the GIC was realized. Unfortunately this is | ||
5 | not the case for the 'virt' board, and so the value that gets copied | ||
6 | is NULL (since a qemu_irq is really a pointer to an IRQState struct | ||
7 | under the hood). The effect is that the CPU interface code never | ||
8 | actually raises the maintenance interrupt line. | ||
9 | 4 | ||
10 | Instead, since the GICv3CPUState has a pointer to the CPUState, make | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | the dereference at the point where we want to raise the interrupt, to | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | avoid an implicit requirement on board code to wire things up in a | 7 | Message-id: 20210628135835.6690-15-peter.maydell@linaro.org |
13 | particular order. | 8 | --- |
9 | target/arm/helper-mve.h | 3 ++ | ||
10 | target/arm/mve.decode | 6 +++- | ||
11 | target/arm/mve_helper.c | 19 ++++++++++++ | ||
12 | target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++ | ||
13 | 4 files changed, 90 insertions(+), 1 deletion(-) | ||
14 | 14 | ||
15 | Reported-by: Jose Martins <josemartins90@gmail.com> | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Message-id: 20201009153904.28529-1-peter.maydell@linaro.org | ||
18 | Reviewed-by: Luc Michel <luc@lmichel.fr> | ||
19 | --- | ||
20 | include/hw/intc/arm_gicv3_common.h | 1 - | ||
21 | hw/intc/arm_gicv3_cpuif.c | 5 ++--- | ||
22 | 2 files changed, 2 insertions(+), 4 deletions(-) | ||
23 | |||
24 | diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/include/hw/intc/arm_gicv3_common.h | 17 | --- a/target/arm/helper-mve.h |
27 | +++ b/include/hw/intc/arm_gicv3_common.h | 18 | +++ b/target/arm/helper-mve.h |
28 | @@ -XXX,XX +XXX,XX @@ struct GICv3CPUState { | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) |
29 | qemu_irq parent_fiq; | 20 | DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
30 | qemu_irq parent_virq; | 21 | DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
31 | qemu_irq parent_vfiq; | 22 | |
32 | - qemu_irq maintenance_irq; | 23 | +DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64) |
33 | 24 | +DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64) | |
34 | /* Redistributor */ | 25 | + |
35 | uint32_t level; /* Current IRQ level */ | 26 | DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64) |
36 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | 27 | DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64) |
28 | DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64) | ||
29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
37 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
38 | --- a/hw/intc/arm_gicv3_cpuif.c | 31 | --- a/target/arm/mve.decode |
39 | +++ b/hw/intc/arm_gicv3_cpuif.c | 32 | +++ b/target/arm/mve.decode |
40 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) | 33 | @@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar |
41 | int irqlevel = 0; | 34 | VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar |
42 | int fiqlevel = 0; | 35 | |
43 | int maintlevel = 0; | 36 | # Vector add across vector |
44 | + ARMCPU *cpu = ARM_CPU(cs->cpu); | 37 | -VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo |
45 | 38 | +{ | |
46 | idx = hppvi_index(cs); | 39 | + VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo |
47 | trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); | 40 | + VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \ |
48 | @@ -XXX,XX +XXX,XX @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) | 41 | + rdahi=%rdahi rdalo=%rdalo |
49 | 42 | +} | |
50 | qemu_set_irq(cs->parent_vfiq, fiqlevel); | 43 | |
51 | qemu_set_irq(cs->parent_virq, irqlevel); | 44 | # Predicate operations |
52 | - qemu_set_irq(cs->maintenance_irq, maintlevel); | 45 | %mask_22_13 22:1 13:3 |
53 | + qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); | 46 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/mve_helper.c | ||
49 | +++ b/target/arm/mve_helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t) | ||
51 | DO_VADDV(vaddvuh, 2, uint16_t) | ||
52 | DO_VADDV(vaddvuw, 4, uint32_t) | ||
53 | |||
54 | +#define DO_VADDLV(OP, TYPE, LTYPE) \ | ||
55 | + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ | ||
56 | + uint64_t ra) \ | ||
57 | + { \ | ||
58 | + uint16_t mask = mve_element_mask(env); \ | ||
59 | + unsigned e; \ | ||
60 | + TYPE *m = vm; \ | ||
61 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { \ | ||
62 | + if (mask & 1) { \ | ||
63 | + ra += (LTYPE)m[H4(e)]; \ | ||
64 | + } \ | ||
65 | + } \ | ||
66 | + mve_advance_vpt(env); \ | ||
67 | + return ra; \ | ||
68 | + } \ | ||
69 | + | ||
70 | +DO_VADDLV(vaddlv_s, int32_t, int64_t) | ||
71 | +DO_VADDLV(vaddlv_u, uint32_t, uint64_t) | ||
72 | + | ||
73 | /* Shifts by immediate */ | ||
74 | #define DO_2SHIFT(OP, ESIZE, TYPE, FN) \ | ||
75 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ | ||
76 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/arm/translate-mve.c | ||
79 | +++ b/target/arm/translate-mve.c | ||
80 | @@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) | ||
81 | return true; | ||
54 | } | 82 | } |
55 | 83 | ||
56 | static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | 84 | +static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a) |
57 | @@ -XXX,XX +XXX,XX @@ void gicv3_init_cpuif(GICv3State *s) | 85 | +{ |
58 | && cpu->gic_num_lrs) { | 86 | + /* |
59 | int j; | 87 | + * Vector Add Long Across Vector: accumulate the 32-bit |
60 | 88 | + * elements of the vector into a 64-bit result stored in | |
61 | - cs->maintenance_irq = cpu->gicv3_maintenance_interrupt; | 89 | + * a pair of general-purpose registers. |
62 | - | 90 | + * No need to check Qm's bank: it is only 3 bits in decode. |
63 | cs->num_list_regs = cpu->gic_num_lrs; | 91 | + */ |
64 | cs->vpribits = cpu->gic_vpribits; | 92 | + TCGv_ptr qm; |
65 | cs->vprebits = cpu->gic_vprebits; | 93 | + TCGv_i64 rda; |
94 | + TCGv_i32 rdalo, rdahi; | ||
95 | + | ||
96 | + if (!dc_isar_feature(aa32_mve, s)) { | ||
97 | + return false; | ||
98 | + } | ||
99 | + /* | ||
100 | + * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related | ||
101 | + * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. | ||
102 | + */ | ||
103 | + if (a->rdahi == 13 || a->rdahi == 15) { | ||
104 | + return false; | ||
105 | + } | ||
106 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
107 | + return true; | ||
108 | + } | ||
109 | + | ||
110 | + /* | ||
111 | + * This insn is subject to beat-wise execution. Partial execution | ||
112 | + * of an A=0 (no-accumulate) insn which does not execute the first | ||
113 | + * beat must start with the current value of RdaHi:RdaLo, not zero. | ||
114 | + */ | ||
115 | + if (a->a || mve_skip_first_beat(s)) { | ||
116 | + /* Accumulate input from RdaHi:RdaLo */ | ||
117 | + rda = tcg_temp_new_i64(); | ||
118 | + rdalo = load_reg(s, a->rdalo); | ||
119 | + rdahi = load_reg(s, a->rdahi); | ||
120 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); | ||
121 | + tcg_temp_free_i32(rdalo); | ||
122 | + tcg_temp_free_i32(rdahi); | ||
123 | + } else { | ||
124 | + /* Accumulate starting at zero */ | ||
125 | + rda = tcg_const_i64(0); | ||
126 | + } | ||
127 | + | ||
128 | + qm = mve_qreg_ptr(a->qm); | ||
129 | + if (a->u) { | ||
130 | + gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda); | ||
131 | + } else { | ||
132 | + gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda); | ||
133 | + } | ||
134 | + tcg_temp_free_ptr(qm); | ||
135 | + | ||
136 | + rdalo = tcg_temp_new_i32(); | ||
137 | + rdahi = tcg_temp_new_i32(); | ||
138 | + tcg_gen_extrl_i64_i32(rdalo, rda); | ||
139 | + tcg_gen_extrh_i64_i32(rdahi, rda); | ||
140 | + store_reg(s, a->rdalo, rdalo); | ||
141 | + store_reg(s, a->rdahi, rdahi); | ||
142 | + tcg_temp_free_i64(rda); | ||
143 | + mve_update_eci(s); | ||
144 | + return true; | ||
145 | +} | ||
146 | + | ||
147 | static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn) | ||
148 | { | ||
149 | TCGv_ptr qd; | ||
66 | -- | 150 | -- |
67 | 2.20.1 | 151 | 2.20.1 |
68 | 152 | ||
69 | 153 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The MVE extension to v8.1M includes some new shift instructions which |
---|---|---|---|
2 | 2 | sit entirely within the non-coprocessor part of the encoding space | |
3 | We can use proper widening loads to extend 32-bit inputs, | 3 | and which operate only on general-purpose registers. They take up |
4 | and skip the "widenfn" step. | 4 | the space which was previously UNPREDICTABLE MOVS and ORRS encodings |
5 | 5 | with Rm == 13 or 15. | |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | |
7 | Message-id: 20201030022618.785675-12-richard.henderson@linaro.org | 7 | Implement the long shifts by immediate, which perform shifts on a |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | pair of general-purpose registers treated as a 64-bit quantity, with |
9 | an immediate shift count between 1 and 32. | ||
10 | |||
11 | Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for | ||
12 | the Rm==13,15 case, we need to explicitly emit code to UNDEF for the | ||
13 | cases where v8.1M now requires that. (Trying to change MOVS and ORRS | ||
14 | is too difficult, because the functions that generate the code are | ||
15 | shared between a dozen different kinds of arithmetic or logical | ||
16 | instruction for all A32, T16 and T32 encodings, and for some insns | ||
17 | and some encodings Rm==13,15 are valid.) | ||
18 | |||
19 | We make the helper functions we need for UQSHLL and SQSHLL take | ||
20 | a 32-bit value which the helper casts to int8_t because we'll need | ||
21 | these helpers also for the shift-by-register insns, where the shift | ||
22 | count might be < 0 or > 32. | ||
23 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
26 | Message-id: 20210628135835.6690-16-peter.maydell@linaro.org | ||
10 | --- | 27 | --- |
11 | target/arm/translate.c | 6 +++ | 28 | target/arm/helper-mve.h | 3 ++ |
12 | target/arm/translate-neon.c.inc | 66 ++++++++++++++++++--------------- | 29 | target/arm/translate.h | 1 + |
13 | 2 files changed, 43 insertions(+), 29 deletions(-) | 30 | target/arm/t32.decode | 28 +++++++++++++ |
14 | 31 | target/arm/mve_helper.c | 10 +++++ | |
32 | target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++ | ||
33 | 5 files changed, 132 insertions(+) | ||
34 | |||
35 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/helper-mve.h | ||
38 | +++ b/target/arm/helper-mve.h | ||
39 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | |||
42 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | ||
43 | + | ||
44 | +DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
45 | +DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
46 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/translate.h | ||
49 | +++ b/target/arm/translate.h | ||
50 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); | ||
51 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
52 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
53 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
54 | +typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
55 | |||
56 | /** | ||
57 | * arm_tbflags_from_tb: | ||
58 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/t32.decode | ||
61 | +++ b/target/arm/t32.decode | ||
62 | @@ -XXX,XX +XXX,XX @@ | ||
63 | &mcr !extern cp opc1 crn crm opc2 rt | ||
64 | &mcrr !extern cp opc1 crm rt rt2 | ||
65 | |||
66 | +&mve_shl_ri rdalo rdahi shim | ||
67 | + | ||
68 | +# rdahi: bits [3:1] from insn, bit 0 is 1 | ||
69 | +# rdalo: bits [3:1] from insn, bit 0 is 0 | ||
70 | +%rdahi_9 9:3 !function=times_2_plus_1 | ||
71 | +%rdalo_17 17:3 !function=times_2 | ||
72 | + | ||
73 | # Data-processing (register) | ||
74 | |||
75 | %imm5_12_6 12:3 6:2 | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | @S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ | ||
78 | &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 | ||
79 | |||
80 | +@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ | ||
81 | + &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
82 | + | ||
83 | { | ||
84 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
85 | AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi | ||
86 | } | ||
87 | BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
88 | { | ||
89 | + # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS | ||
90 | + # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE | ||
91 | + # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that | ||
92 | + # they explicitly call unallocated_encoding() for cases that must UNDEF | ||
93 | + # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting | ||
94 | + # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
95 | + # handling them as r13 and r15 accesses with the same semantics as A32). | ||
96 | + [ | ||
97 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
98 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
99 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
100 | + | ||
101 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
102 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
103 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
104 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
105 | + ] | ||
106 | + | ||
107 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | ||
108 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | ||
109 | } | ||
110 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/target/arm/mve_helper.c | ||
113 | +++ b/target/arm/mve_helper.c | ||
114 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
115 | mve_advance_vpt(env); | ||
116 | return rdm; | ||
117 | } | ||
118 | + | ||
119 | +uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
120 | +{ | ||
121 | + return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
122 | +} | ||
123 | + | ||
124 | +uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
125 | +{ | ||
126 | + return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
127 | +} | ||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 128 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
16 | index XXXXXXX..XXXXXXX 100644 | 129 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate.c | 130 | --- a/target/arm/translate.c |
18 | +++ b/target/arm/translate.c | 131 | +++ b/target/arm/translate.c |
19 | @@ -XXX,XX +XXX,XX @@ static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop) | 132 | @@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a) |
20 | long off = neon_element_offset(reg, ele, memop); | ||
21 | |||
22 | switch (memop) { | ||
23 | + case MO_SL: | ||
24 | + tcg_gen_ld32s_i64(dest, cpu_env, off); | ||
25 | + break; | ||
26 | + case MO_UL: | ||
27 | + tcg_gen_ld32u_i64(dest, cpu_env, off); | ||
28 | + break; | ||
29 | case MO_Q: | ||
30 | tcg_gen_ld_i64(dest, cpu_env, off); | ||
31 | break; | ||
32 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/translate-neon.c.inc | ||
35 | +++ b/target/arm/translate-neon.c.inc | ||
36 | @@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) | ||
37 | static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
38 | NeonGenWidenFn *widenfn, | ||
39 | NeonGenTwo64OpFn *opfn, | ||
40 | - bool src1_wide) | ||
41 | + int src1_mop, int src2_mop) | ||
42 | { | ||
43 | /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW) */ | ||
44 | TCGv_i64 rn0_64, rn1_64, rm_64; | ||
45 | - TCGv_i32 rm; | ||
46 | |||
47 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
48 | return false; | ||
49 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
50 | return false; | ||
51 | } | ||
52 | |||
53 | - if (!widenfn || !opfn) { | ||
54 | + if (!opfn) { | ||
55 | /* size == 3 case, which is an entirely different insn group */ | ||
56 | return false; | ||
57 | } | ||
58 | |||
59 | - if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { | ||
60 | + if ((a->vd & 1) || (src1_mop == MO_Q && (a->vn & 1))) { | ||
61 | return false; | ||
62 | } | ||
63 | |||
64 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
65 | rn1_64 = tcg_temp_new_i64(); | ||
66 | rm_64 = tcg_temp_new_i64(); | ||
67 | |||
68 | - if (src1_wide) { | ||
69 | - read_neon_element64(rn0_64, a->vn, 0, MO_64); | ||
70 | + if (src1_mop >= 0) { | ||
71 | + read_neon_element64(rn0_64, a->vn, 0, src1_mop); | ||
72 | } else { | ||
73 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
74 | read_neon_element32(tmp, a->vn, 0, MO_32); | ||
75 | widenfn(rn0_64, tmp); | ||
76 | tcg_temp_free_i32(tmp); | ||
77 | } | ||
78 | - rm = tcg_temp_new_i32(); | ||
79 | - read_neon_element32(rm, a->vm, 0, MO_32); | ||
80 | + if (src2_mop >= 0) { | ||
81 | + read_neon_element64(rm_64, a->vm, 0, src2_mop); | ||
82 | + } else { | ||
83 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
84 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
85 | + widenfn(rm_64, tmp); | ||
86 | + tcg_temp_free_i32(tmp); | ||
87 | + } | ||
88 | |||
89 | - widenfn(rm_64, rm); | ||
90 | - tcg_temp_free_i32(rm); | ||
91 | opfn(rn0_64, rn0_64, rm_64); | ||
92 | |||
93 | /* | ||
94 | * Load second pass inputs before storing the first pass result, to | ||
95 | * avoid incorrect results if a narrow input overlaps with the result. | ||
96 | */ | ||
97 | - if (src1_wide) { | ||
98 | - read_neon_element64(rn1_64, a->vn, 1, MO_64); | ||
99 | + if (src1_mop >= 0) { | ||
100 | + read_neon_element64(rn1_64, a->vn, 1, src1_mop); | ||
101 | } else { | ||
102 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
103 | read_neon_element32(tmp, a->vn, 1, MO_32); | ||
104 | widenfn(rn1_64, tmp); | ||
105 | tcg_temp_free_i32(tmp); | ||
106 | } | ||
107 | - rm = tcg_temp_new_i32(); | ||
108 | - read_neon_element32(rm, a->vm, 1, MO_32); | ||
109 | + if (src2_mop >= 0) { | ||
110 | + read_neon_element64(rm_64, a->vm, 1, src2_mop); | ||
111 | + } else { | ||
112 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
113 | + read_neon_element32(tmp, a->vm, 1, MO_32); | ||
114 | + widenfn(rm_64, tmp); | ||
115 | + tcg_temp_free_i32(tmp); | ||
116 | + } | ||
117 | |||
118 | write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
119 | |||
120 | - widenfn(rm_64, rm); | ||
121 | - tcg_temp_free_i32(rm); | ||
122 | opfn(rn1_64, rn1_64, rm_64); | ||
123 | write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
124 | |||
125 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
126 | return true; | 133 | return true; |
127 | } | 134 | } |
128 | 135 | ||
129 | -#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ | 136 | +/* |
130 | +#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \ | 137 | + * v8.1M MVE wide-shifts |
131 | static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ | 138 | + */ |
132 | { \ | 139 | +static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a, |
133 | static NeonGenWidenFn * const widenfn[] = { \ | 140 | + WideShiftImmFn *fn) |
134 | gen_helper_neon_widen_##S##8, \ | 141 | +{ |
135 | gen_helper_neon_widen_##S##16, \ | 142 | + TCGv_i64 rda; |
136 | - tcg_gen_##EXT##_i32_i64, \ | 143 | + TCGv_i32 rdalo, rdahi; |
137 | - NULL, \ | 144 | + |
138 | + NULL, NULL, \ | 145 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
139 | }; \ | 146 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
140 | static NeonGenTwo64OpFn * const addfn[] = { \ | 147 | + return false; |
141 | gen_helper_neon_##OP##l_u16, \ | 148 | + } |
142 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | 149 | + if (a->rdahi == 15) { |
143 | tcg_gen_##OP##_i64, \ | 150 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ |
144 | NULL, \ | 151 | + return false; |
145 | }; \ | 152 | + } |
146 | - return do_prewiden_3d(s, a, widenfn[a->size], \ | 153 | + if (!dc_isar_feature(aa32_mve, s) || |
147 | - addfn[a->size], SRC1WIDE); \ | 154 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
148 | + int narrow_mop = a->size == MO_32 ? MO_32 | SIGN : -1; \ | 155 | + a->rdahi == 13) { |
149 | + return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \ | 156 | + /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */ |
150 | + SRC1WIDE ? MO_Q : narrow_mop, \ | 157 | + unallocated_encoding(s); |
151 | + narrow_mop); \ | 158 | + return true; |
152 | } | 159 | + } |
153 | 160 | + | |
154 | -DO_PREWIDEN(VADDL_S, s, ext, add, false) | 161 | + if (a->shim == 0) { |
155 | -DO_PREWIDEN(VADDL_U, u, extu, add, false) | 162 | + a->shim = 32; |
156 | -DO_PREWIDEN(VSUBL_S, s, ext, sub, false) | 163 | + } |
157 | -DO_PREWIDEN(VSUBL_U, u, extu, sub, false) | 164 | + |
158 | -DO_PREWIDEN(VADDW_S, s, ext, add, true) | 165 | + rda = tcg_temp_new_i64(); |
159 | -DO_PREWIDEN(VADDW_U, u, extu, add, true) | 166 | + rdalo = load_reg(s, a->rdalo); |
160 | -DO_PREWIDEN(VSUBW_S, s, ext, sub, true) | 167 | + rdahi = load_reg(s, a->rdahi); |
161 | -DO_PREWIDEN(VSUBW_U, u, extu, sub, true) | 168 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); |
162 | +DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN) | 169 | + |
163 | +DO_PREWIDEN(VADDL_U, u, add, false, 0) | 170 | + fn(rda, rda, a->shim); |
164 | +DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN) | 171 | + |
165 | +DO_PREWIDEN(VSUBL_U, u, sub, false, 0) | 172 | + tcg_gen_extrl_i64_i32(rdalo, rda); |
166 | +DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN) | 173 | + tcg_gen_extrh_i64_i32(rdahi, rda); |
167 | +DO_PREWIDEN(VADDW_U, u, add, true, 0) | 174 | + store_reg(s, a->rdalo, rdalo); |
168 | +DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN) | 175 | + store_reg(s, a->rdahi, rdahi); |
169 | +DO_PREWIDEN(VSUBW_U, u, sub, true, 0) | 176 | + tcg_temp_free_i64(rda); |
170 | 177 | + | |
171 | static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | 178 | + return true; |
172 | NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) | 179 | +} |
180 | + | ||
181 | +static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
182 | +{ | ||
183 | + return do_mve_shl_ri(s, a, tcg_gen_sari_i64); | ||
184 | +} | ||
185 | + | ||
186 | +static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
187 | +{ | ||
188 | + return do_mve_shl_ri(s, a, tcg_gen_shli_i64); | ||
189 | +} | ||
190 | + | ||
191 | +static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
192 | +{ | ||
193 | + return do_mve_shl_ri(s, a, tcg_gen_shri_i64); | ||
194 | +} | ||
195 | + | ||
196 | +static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
197 | +{ | ||
198 | + gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
199 | +} | ||
200 | + | ||
201 | +static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
202 | +{ | ||
203 | + return do_mve_shl_ri(s, a, gen_mve_sqshll); | ||
204 | +} | ||
205 | + | ||
206 | +static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) | ||
207 | +{ | ||
208 | + gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift)); | ||
209 | +} | ||
210 | + | ||
211 | +static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
212 | +{ | ||
213 | + return do_mve_shl_ri(s, a, gen_mve_uqshll); | ||
214 | +} | ||
215 | + | ||
216 | +static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
217 | +{ | ||
218 | + return do_mve_shl_ri(s, a, gen_srshr64_i64); | ||
219 | +} | ||
220 | + | ||
221 | +static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) | ||
222 | +{ | ||
223 | + return do_mve_shl_ri(s, a, gen_urshr64_i64); | ||
224 | +} | ||
225 | + | ||
226 | /* | ||
227 | * Multiply and multiply accumulate | ||
228 | */ | ||
173 | -- | 229 | -- |
174 | 2.20.1 | 230 | 2.20.1 |
175 | 231 | ||
176 | 232 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE long shifts by register, which perform shifts on a |
---|---|---|---|
2 | 2 | pair of general-purpose registers treated as a 64-bit quantity, with | |
3 | The only uses of this function are for loading VFP | 3 | the shift count in another general-purpose register, which might be |
4 | single-precision values, and nothing to do with NEON. | 4 | either positive or negative. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Like the long-shifts-by-immediate, these encodings sit in the space |
7 | Message-id: 20201030022618.785675-8-richard.henderson@linaro.org | 7 | that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15. |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and |
9 | also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases), | ||
10 | we have to move the CSEL pattern into the same decodetree group. | ||
11 | |||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
14 | Message-id: 20210628135835.6690-17-peter.maydell@linaro.org | ||
10 | --- | 15 | --- |
11 | target/arm/translate.c | 4 +- | 16 | target/arm/helper-mve.h | 6 +++ |
12 | target/arm/translate-vfp.c.inc | 184 ++++++++++++++++----------------- | 17 | target/arm/translate.h | 1 + |
13 | 2 files changed, 94 insertions(+), 94 deletions(-) | 18 | target/arm/t32.decode | 16 +++++-- |
14 | 19 | target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++ | |
20 | target/arm/translate.c | 69 ++++++++++++++++++++++++++++++ | ||
21 | 5 files changed, 182 insertions(+), 3 deletions(-) | ||
22 | |||
23 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/arm/helper-mve.h | ||
26 | +++ b/target/arm/helper-mve.h | ||
27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | |||
29 | DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32) | ||
30 | |||
31 | +DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
32 | +DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
33 | DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
34 | DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
35 | +DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
36 | +DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
37 | +DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
38 | +DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
39 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/translate.h | ||
42 | +++ b/target/arm/translate.h | ||
43 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
44 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
45 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
46 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
47 | +typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
48 | |||
49 | /** | ||
50 | * arm_tbflags_from_tb: | ||
51 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/t32.decode | ||
54 | +++ b/target/arm/t32.decode | ||
55 | @@ -XXX,XX +XXX,XX @@ | ||
56 | &mcrr !extern cp opc1 crm rt rt2 | ||
57 | |||
58 | &mve_shl_ri rdalo rdahi shim | ||
59 | +&mve_shl_rr rdalo rdahi rm | ||
60 | |||
61 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
62 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
63 | @@ -XXX,XX +XXX,XX @@ | ||
64 | |||
65 | @mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \ | ||
66 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
67 | +@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ | ||
68 | + &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
69 | |||
70 | { | ||
71 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
72 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
73 | URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
74 | SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
75 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
76 | + | ||
77 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
78 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
79 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
80 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
81 | + UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr | ||
82 | + SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr | ||
83 | ] | ||
84 | |||
85 | MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi | ||
86 | ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi | ||
87 | + | ||
88 | + # v8.1M CSEL and friends | ||
89 | + CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 | ||
90 | } | ||
91 | { | ||
92 | MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi | ||
93 | @@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi | ||
94 | } | ||
95 | RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi | ||
96 | |||
97 | -# v8.1M CSEL and friends | ||
98 | -CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4 | ||
99 | - | ||
100 | # Data-processing (register-shifted register) | ||
101 | |||
102 | MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ | ||
103 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/target/arm/mve_helper.c | ||
106 | +++ b/target/arm/mve_helper.c | ||
107 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm, | ||
108 | return rdm; | ||
109 | } | ||
110 | |||
111 | +uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
112 | +{ | ||
113 | + return do_sqrshl_d(n, -(int8_t)shift, false, NULL); | ||
114 | +} | ||
115 | + | ||
116 | +uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
117 | +{ | ||
118 | + return do_uqrshl_d(n, (int8_t)shift, false, NULL); | ||
119 | +} | ||
120 | + | ||
121 | uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
122 | { | ||
123 | return do_sqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
124 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
125 | { | ||
126 | return do_uqrshl_d(n, (int8_t)shift, false, &env->QF); | ||
127 | } | ||
128 | + | ||
129 | +uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
130 | +{ | ||
131 | + return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF); | ||
132 | +} | ||
133 | + | ||
134 | +uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
135 | +{ | ||
136 | + return do_uqrshl_d(n, (int8_t)shift, true, &env->QF); | ||
137 | +} | ||
138 | + | ||
139 | +/* Operate on 64-bit values, but saturate at 48 bits */ | ||
140 | +static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift, | ||
141 | + bool round, uint32_t *sat) | ||
142 | +{ | ||
143 | + if (shift <= -48) { | ||
144 | + /* Rounding the sign bit always produces 0. */ | ||
145 | + if (round) { | ||
146 | + return 0; | ||
147 | + } | ||
148 | + return src >> 63; | ||
149 | + } else if (shift < 0) { | ||
150 | + if (round) { | ||
151 | + src >>= -shift - 1; | ||
152 | + return (src >> 1) + (src & 1); | ||
153 | + } | ||
154 | + return src >> -shift; | ||
155 | + } else if (shift < 48) { | ||
156 | + int64_t val = src << shift; | ||
157 | + int64_t extval = sextract64(val, 0, 48); | ||
158 | + if (!sat || val == extval) { | ||
159 | + return extval; | ||
160 | + } | ||
161 | + } else if (!sat || src == 0) { | ||
162 | + return 0; | ||
163 | + } | ||
164 | + | ||
165 | + *sat = 1; | ||
166 | + return (1ULL << 47) - (src >= 0); | ||
167 | +} | ||
168 | + | ||
169 | +/* Operate on 64-bit values, but saturate at 48 bits */ | ||
170 | +static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift, | ||
171 | + bool round, uint32_t *sat) | ||
172 | +{ | ||
173 | + uint64_t val, extval; | ||
174 | + | ||
175 | + if (shift <= -(48 + round)) { | ||
176 | + return 0; | ||
177 | + } else if (shift < 0) { | ||
178 | + if (round) { | ||
179 | + val = src >> (-shift - 1); | ||
180 | + val = (val >> 1) + (val & 1); | ||
181 | + } else { | ||
182 | + val = src >> -shift; | ||
183 | + } | ||
184 | + extval = extract64(val, 0, 48); | ||
185 | + if (!sat || val == extval) { | ||
186 | + return extval; | ||
187 | + } | ||
188 | + } else if (shift < 48) { | ||
189 | + uint64_t val = src << shift; | ||
190 | + uint64_t extval = extract64(val, 0, 48); | ||
191 | + if (!sat || val == extval) { | ||
192 | + return extval; | ||
193 | + } | ||
194 | + } else if (!sat || src == 0) { | ||
195 | + return 0; | ||
196 | + } | ||
197 | + | ||
198 | + *sat = 1; | ||
199 | + return MAKE_64BIT_MASK(0, 48); | ||
200 | +} | ||
201 | + | ||
202 | +uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
203 | +{ | ||
204 | + return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF); | ||
205 | +} | ||
206 | + | ||
207 | +uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
208 | +{ | ||
209 | + return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
210 | +} | ||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 211 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
16 | index XXXXXXX..XXXXXXX 100644 | 212 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate.c | 213 | --- a/target/arm/translate.c |
18 | +++ b/target/arm/translate.c | 214 | +++ b/target/arm/translate.c |
19 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg64(TCGv_i64 var, int reg) | 215 | @@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a) |
20 | tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); | 216 | return do_mve_shl_ri(s, a, gen_urshr64_i64); |
21 | } | 217 | } |
22 | 218 | ||
23 | -static inline void neon_load_reg32(TCGv_i32 var, int reg) | 219 | +static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn) |
24 | +static inline void vfp_load_reg32(TCGv_i32 var, int reg) | 220 | +{ |
25 | { | 221 | + TCGv_i64 rda; |
26 | tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); | 222 | + TCGv_i32 rdalo, rdahi; |
27 | } | 223 | + |
28 | 224 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | |
29 | -static inline void neon_store_reg32(TCGv_i32 var, int reg) | 225 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
30 | +static inline void vfp_store_reg32(TCGv_i32 var, int reg) | 226 | + return false; |
31 | { | 227 | + } |
32 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | 228 | + if (a->rdahi == 15) { |
33 | } | 229 | + /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */ |
34 | diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc | 230 | + return false; |
35 | index XXXXXXX..XXXXXXX 100644 | 231 | + } |
36 | --- a/target/arm/translate-vfp.c.inc | 232 | + if (!dc_isar_feature(aa32_mve, s) || |
37 | +++ b/target/arm/translate-vfp.c.inc | 233 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | 234 | + a->rdahi == 13 || a->rm == 13 || a->rm == 15 || |
39 | frn = tcg_temp_new_i32(); | 235 | + a->rm == a->rdahi || a->rm == a->rdalo) { |
40 | frm = tcg_temp_new_i32(); | 236 | + /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */ |
41 | dest = tcg_temp_new_i32(); | 237 | + unallocated_encoding(s); |
42 | - neon_load_reg32(frn, rn); | 238 | + return true; |
43 | - neon_load_reg32(frm, rm); | 239 | + } |
44 | + vfp_load_reg32(frn, rn); | 240 | + |
45 | + vfp_load_reg32(frm, rm); | 241 | + rda = tcg_temp_new_i64(); |
46 | switch (a->cc) { | 242 | + rdalo = load_reg(s, a->rdalo); |
47 | case 0: /* eq: Z */ | 243 | + rdahi = load_reg(s, a->rdahi); |
48 | tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, | 244 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); |
49 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | 245 | + |
50 | if (sz == 1) { | 246 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ |
51 | tcg_gen_andi_i32(dest, dest, 0xffff); | 247 | + fn(rda, cpu_env, rda, cpu_R[a->rm]); |
52 | } | 248 | + |
53 | - neon_store_reg32(dest, rd); | 249 | + tcg_gen_extrl_i64_i32(rdalo, rda); |
54 | + vfp_store_reg32(dest, rd); | 250 | + tcg_gen_extrh_i64_i32(rdahi, rda); |
55 | tcg_temp_free_i32(frn); | 251 | + store_reg(s, a->rdalo, rdalo); |
56 | tcg_temp_free_i32(frm); | 252 | + store_reg(s, a->rdahi, rdahi); |
57 | tcg_temp_free_i32(dest); | 253 | + tcg_temp_free_i64(rda); |
58 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | 254 | + |
59 | TCGv_i32 tcg_res; | 255 | + return true; |
60 | tcg_op = tcg_temp_new_i32(); | 256 | +} |
61 | tcg_res = tcg_temp_new_i32(); | 257 | + |
62 | - neon_load_reg32(tcg_op, rm); | 258 | +static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a) |
63 | + vfp_load_reg32(tcg_op, rm); | 259 | +{ |
64 | if (sz == 1) { | 260 | + return do_mve_shl_rr(s, a, gen_helper_mve_ushll); |
65 | gen_helper_rinth(tcg_res, tcg_op, fpst); | 261 | +} |
66 | } else { | 262 | + |
67 | gen_helper_rints(tcg_res, tcg_op, fpst); | 263 | +static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a) |
68 | } | 264 | +{ |
69 | - neon_store_reg32(tcg_res, rd); | 265 | + return do_mve_shl_rr(s, a, gen_helper_mve_sshrl); |
70 | + vfp_store_reg32(tcg_res, rd); | 266 | +} |
71 | tcg_temp_free_i32(tcg_op); | 267 | + |
72 | tcg_temp_free_i32(tcg_res); | 268 | +static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a) |
73 | } | 269 | +{ |
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | 270 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll); |
75 | gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); | 271 | +} |
76 | } | 272 | + |
77 | tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); | 273 | +static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a) |
78 | - neon_store_reg32(tcg_tmp, rd); | 274 | +{ |
79 | + vfp_store_reg32(tcg_tmp, rd); | 275 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl); |
80 | tcg_temp_free_i32(tcg_tmp); | 276 | +} |
81 | tcg_temp_free_i64(tcg_res); | 277 | + |
82 | tcg_temp_free_i64(tcg_double); | 278 | +static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a) |
83 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | 279 | +{ |
84 | TCGv_i32 tcg_single, tcg_res; | 280 | + return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48); |
85 | tcg_single = tcg_temp_new_i32(); | 281 | +} |
86 | tcg_res = tcg_temp_new_i32(); | 282 | + |
87 | - neon_load_reg32(tcg_single, rm); | 283 | +static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) |
88 | + vfp_load_reg32(tcg_single, rm); | 284 | +{ |
89 | if (sz == 1) { | 285 | + return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); |
90 | if (is_signed) { | 286 | +} |
91 | gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst); | 287 | + |
92 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | 288 | /* |
93 | gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); | 289 | * Multiply and multiply accumulate |
94 | } | 290 | */ |
95 | } | ||
96 | - neon_store_reg32(tcg_res, rd); | ||
97 | + vfp_store_reg32(tcg_res, rd); | ||
98 | tcg_temp_free_i32(tcg_res); | ||
99 | tcg_temp_free_i32(tcg_single); | ||
100 | } | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) | ||
102 | if (a->l) { | ||
103 | /* VFP to general purpose register */ | ||
104 | tmp = tcg_temp_new_i32(); | ||
105 | - neon_load_reg32(tmp, a->vn); | ||
106 | + vfp_load_reg32(tmp, a->vn); | ||
107 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | ||
108 | store_reg(s, a->rt, tmp); | ||
109 | } else { | ||
110 | /* general purpose register to VFP */ | ||
111 | tmp = load_reg(s, a->rt); | ||
112 | tcg_gen_andi_i32(tmp, tmp, 0xffff); | ||
113 | - neon_store_reg32(tmp, a->vn); | ||
114 | + vfp_store_reg32(tmp, a->vn); | ||
115 | tcg_temp_free_i32(tmp); | ||
116 | } | ||
117 | |||
118 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) | ||
119 | if (a->l) { | ||
120 | /* VFP to general purpose register */ | ||
121 | tmp = tcg_temp_new_i32(); | ||
122 | - neon_load_reg32(tmp, a->vn); | ||
123 | + vfp_load_reg32(tmp, a->vn); | ||
124 | if (a->rt == 15) { | ||
125 | /* Set the 4 flag bits in the CPSR. */ | ||
126 | gen_set_nzcv(tmp); | ||
127 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a) | ||
128 | } else { | ||
129 | /* general purpose register to VFP */ | ||
130 | tmp = load_reg(s, a->rt); | ||
131 | - neon_store_reg32(tmp, a->vn); | ||
132 | + vfp_store_reg32(tmp, a->vn); | ||
133 | tcg_temp_free_i32(tmp); | ||
134 | } | ||
135 | |||
136 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) | ||
137 | if (a->op) { | ||
138 | /* fpreg to gpreg */ | ||
139 | tmp = tcg_temp_new_i32(); | ||
140 | - neon_load_reg32(tmp, a->vm); | ||
141 | + vfp_load_reg32(tmp, a->vm); | ||
142 | store_reg(s, a->rt, tmp); | ||
143 | tmp = tcg_temp_new_i32(); | ||
144 | - neon_load_reg32(tmp, a->vm + 1); | ||
145 | + vfp_load_reg32(tmp, a->vm + 1); | ||
146 | store_reg(s, a->rt2, tmp); | ||
147 | } else { | ||
148 | /* gpreg to fpreg */ | ||
149 | tmp = load_reg(s, a->rt); | ||
150 | - neon_store_reg32(tmp, a->vm); | ||
151 | + vfp_store_reg32(tmp, a->vm); | ||
152 | tcg_temp_free_i32(tmp); | ||
153 | tmp = load_reg(s, a->rt2); | ||
154 | - neon_store_reg32(tmp, a->vm + 1); | ||
155 | + vfp_store_reg32(tmp, a->vm + 1); | ||
156 | tcg_temp_free_i32(tmp); | ||
157 | } | ||
158 | |||
159 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) | ||
160 | if (a->op) { | ||
161 | /* fpreg to gpreg */ | ||
162 | tmp = tcg_temp_new_i32(); | ||
163 | - neon_load_reg32(tmp, a->vm * 2); | ||
164 | + vfp_load_reg32(tmp, a->vm * 2); | ||
165 | store_reg(s, a->rt, tmp); | ||
166 | tmp = tcg_temp_new_i32(); | ||
167 | - neon_load_reg32(tmp, a->vm * 2 + 1); | ||
168 | + vfp_load_reg32(tmp, a->vm * 2 + 1); | ||
169 | store_reg(s, a->rt2, tmp); | ||
170 | } else { | ||
171 | /* gpreg to fpreg */ | ||
172 | tmp = load_reg(s, a->rt); | ||
173 | - neon_store_reg32(tmp, a->vm * 2); | ||
174 | + vfp_store_reg32(tmp, a->vm * 2); | ||
175 | tcg_temp_free_i32(tmp); | ||
176 | tmp = load_reg(s, a->rt2); | ||
177 | - neon_store_reg32(tmp, a->vm * 2 + 1); | ||
178 | + vfp_store_reg32(tmp, a->vm * 2 + 1); | ||
179 | tcg_temp_free_i32(tmp); | ||
180 | } | ||
181 | |||
182 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
183 | tmp = tcg_temp_new_i32(); | ||
184 | if (a->l) { | ||
185 | gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); | ||
186 | - neon_store_reg32(tmp, a->vd); | ||
187 | + vfp_store_reg32(tmp, a->vd); | ||
188 | } else { | ||
189 | - neon_load_reg32(tmp, a->vd); | ||
190 | + vfp_load_reg32(tmp, a->vd); | ||
191 | gen_aa32_st16(s, tmp, addr, get_mem_index(s)); | ||
192 | } | ||
193 | tcg_temp_free_i32(tmp); | ||
194 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) | ||
195 | tmp = tcg_temp_new_i32(); | ||
196 | if (a->l) { | ||
197 | gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
198 | - neon_store_reg32(tmp, a->vd); | ||
199 | + vfp_store_reg32(tmp, a->vd); | ||
200 | } else { | ||
201 | - neon_load_reg32(tmp, a->vd); | ||
202 | + vfp_load_reg32(tmp, a->vd); | ||
203 | gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
204 | } | ||
205 | tcg_temp_free_i32(tmp); | ||
206 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) | ||
207 | if (a->l) { | ||
208 | /* load */ | ||
209 | gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); | ||
210 | - neon_store_reg32(tmp, a->vd + i); | ||
211 | + vfp_store_reg32(tmp, a->vd + i); | ||
212 | } else { | ||
213 | /* store */ | ||
214 | - neon_load_reg32(tmp, a->vd + i); | ||
215 | + vfp_load_reg32(tmp, a->vd + i); | ||
216 | gen_aa32_st32(s, tmp, addr, get_mem_index(s)); | ||
217 | } | ||
218 | tcg_gen_addi_i32(addr, addr, offset); | ||
219 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
220 | fd = tcg_temp_new_i32(); | ||
221 | fpst = fpstatus_ptr(FPST_FPCR); | ||
222 | |||
223 | - neon_load_reg32(f0, vn); | ||
224 | - neon_load_reg32(f1, vm); | ||
225 | + vfp_load_reg32(f0, vn); | ||
226 | + vfp_load_reg32(f1, vm); | ||
227 | |||
228 | for (;;) { | ||
229 | if (reads_vd) { | ||
230 | - neon_load_reg32(fd, vd); | ||
231 | + vfp_load_reg32(fd, vd); | ||
232 | } | ||
233 | fn(fd, f0, f1, fpst); | ||
234 | - neon_store_reg32(fd, vd); | ||
235 | + vfp_store_reg32(fd, vd); | ||
236 | |||
237 | if (veclen == 0) { | ||
238 | break; | ||
239 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
240 | veclen--; | ||
241 | vd = vfp_advance_sreg(vd, delta_d); | ||
242 | vn = vfp_advance_sreg(vn, delta_d); | ||
243 | - neon_load_reg32(f0, vn); | ||
244 | + vfp_load_reg32(f0, vn); | ||
245 | if (delta_m) { | ||
246 | vm = vfp_advance_sreg(vm, delta_m); | ||
247 | - neon_load_reg32(f1, vm); | ||
248 | + vfp_load_reg32(f1, vm); | ||
249 | } | ||
250 | } | ||
251 | |||
252 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3OpSPFn *fn, | ||
253 | fd = tcg_temp_new_i32(); | ||
254 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
255 | |||
256 | - neon_load_reg32(f0, vn); | ||
257 | - neon_load_reg32(f1, vm); | ||
258 | + vfp_load_reg32(f0, vn); | ||
259 | + vfp_load_reg32(f1, vm); | ||
260 | |||
261 | if (reads_vd) { | ||
262 | - neon_load_reg32(fd, vd); | ||
263 | + vfp_load_reg32(fd, vd); | ||
264 | } | ||
265 | fn(fd, f0, f1, fpst); | ||
266 | - neon_store_reg32(fd, vd); | ||
267 | + vfp_store_reg32(fd, vd); | ||
268 | |||
269 | tcg_temp_free_i32(f0); | ||
270 | tcg_temp_free_i32(f1); | ||
271 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
272 | f0 = tcg_temp_new_i32(); | ||
273 | fd = tcg_temp_new_i32(); | ||
274 | |||
275 | - neon_load_reg32(f0, vm); | ||
276 | + vfp_load_reg32(f0, vm); | ||
277 | |||
278 | for (;;) { | ||
279 | fn(fd, f0); | ||
280 | - neon_store_reg32(fd, vd); | ||
281 | + vfp_store_reg32(fd, vd); | ||
282 | |||
283 | if (veclen == 0) { | ||
284 | break; | ||
285 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
286 | /* single source one-many */ | ||
287 | while (veclen--) { | ||
288 | vd = vfp_advance_sreg(vd, delta_d); | ||
289 | - neon_store_reg32(fd, vd); | ||
290 | + vfp_store_reg32(fd, vd); | ||
291 | } | ||
292 | break; | ||
293 | } | ||
294 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
295 | veclen--; | ||
296 | vd = vfp_advance_sreg(vd, delta_d); | ||
297 | vm = vfp_advance_sreg(vm, delta_m); | ||
298 | - neon_load_reg32(f0, vm); | ||
299 | + vfp_load_reg32(f0, vm); | ||
300 | } | ||
301 | |||
302 | tcg_temp_free_i32(f0); | ||
303 | @@ -XXX,XX +XXX,XX @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm) | ||
304 | } | ||
305 | |||
306 | f0 = tcg_temp_new_i32(); | ||
307 | - neon_load_reg32(f0, vm); | ||
308 | + vfp_load_reg32(f0, vm); | ||
309 | fn(f0, f0); | ||
310 | - neon_store_reg32(f0, vd); | ||
311 | + vfp_store_reg32(f0, vd); | ||
312 | tcg_temp_free_i32(f0); | ||
313 | |||
314 | return true; | ||
315 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | ||
316 | vm = tcg_temp_new_i32(); | ||
317 | vd = tcg_temp_new_i32(); | ||
318 | |||
319 | - neon_load_reg32(vn, a->vn); | ||
320 | - neon_load_reg32(vm, a->vm); | ||
321 | + vfp_load_reg32(vn, a->vn); | ||
322 | + vfp_load_reg32(vm, a->vm); | ||
323 | if (neg_n) { | ||
324 | /* VFNMS, VFMS */ | ||
325 | gen_helper_vfp_negh(vn, vn); | ||
326 | } | ||
327 | - neon_load_reg32(vd, a->vd); | ||
328 | + vfp_load_reg32(vd, a->vd); | ||
329 | if (neg_d) { | ||
330 | /* VFNMA, VFNMS */ | ||
331 | gen_helper_vfp_negh(vd, vd); | ||
332 | } | ||
333 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
334 | gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst); | ||
335 | - neon_store_reg32(vd, a->vd); | ||
336 | + vfp_store_reg32(vd, a->vd); | ||
337 | |||
338 | tcg_temp_free_ptr(fpst); | ||
339 | tcg_temp_free_i32(vn); | ||
340 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d) | ||
341 | vm = tcg_temp_new_i32(); | ||
342 | vd = tcg_temp_new_i32(); | ||
343 | |||
344 | - neon_load_reg32(vn, a->vn); | ||
345 | - neon_load_reg32(vm, a->vm); | ||
346 | + vfp_load_reg32(vn, a->vn); | ||
347 | + vfp_load_reg32(vm, a->vm); | ||
348 | if (neg_n) { | ||
349 | /* VFNMS, VFMS */ | ||
350 | gen_helper_vfp_negs(vn, vn); | ||
351 | } | ||
352 | - neon_load_reg32(vd, a->vd); | ||
353 | + vfp_load_reg32(vd, a->vd); | ||
354 | if (neg_d) { | ||
355 | /* VFNMA, VFNMS */ | ||
356 | gen_helper_vfp_negs(vd, vd); | ||
357 | } | ||
358 | fpst = fpstatus_ptr(FPST_FPCR); | ||
359 | gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); | ||
360 | - neon_store_reg32(vd, a->vd); | ||
361 | + vfp_store_reg32(vd, a->vd); | ||
362 | |||
363 | tcg_temp_free_ptr(fpst); | ||
364 | tcg_temp_free_i32(vn); | ||
365 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
366 | } | ||
367 | |||
368 | fd = tcg_const_i32(vfp_expand_imm(MO_16, a->imm)); | ||
369 | - neon_store_reg32(fd, a->vd); | ||
370 | + vfp_store_reg32(fd, a->vd); | ||
371 | tcg_temp_free_i32(fd); | ||
372 | return true; | ||
373 | } | ||
374 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) | ||
375 | fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); | ||
376 | |||
377 | for (;;) { | ||
378 | - neon_store_reg32(fd, vd); | ||
379 | + vfp_store_reg32(fd, vd); | ||
380 | |||
381 | if (veclen == 0) { | ||
382 | break; | ||
383 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_sp *a) | ||
384 | vd = tcg_temp_new_i32(); | ||
385 | vm = tcg_temp_new_i32(); | ||
386 | |||
387 | - neon_load_reg32(vd, a->vd); | ||
388 | + vfp_load_reg32(vd, a->vd); | ||
389 | if (a->z) { | ||
390 | tcg_gen_movi_i32(vm, 0); | ||
391 | } else { | ||
392 | - neon_load_reg32(vm, a->vm); | ||
393 | + vfp_load_reg32(vm, a->vm); | ||
394 | } | ||
395 | |||
396 | if (a->e) { | ||
397 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a) | ||
398 | vd = tcg_temp_new_i32(); | ||
399 | vm = tcg_temp_new_i32(); | ||
400 | |||
401 | - neon_load_reg32(vd, a->vd); | ||
402 | + vfp_load_reg32(vd, a->vd); | ||
403 | if (a->z) { | ||
404 | tcg_gen_movi_i32(vm, 0); | ||
405 | } else { | ||
406 | - neon_load_reg32(vm, a->vm); | ||
407 | + vfp_load_reg32(vm, a->vm); | ||
408 | } | ||
409 | |||
410 | if (a->e) { | ||
411 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_VCVT_f32_f16 *a) | ||
412 | /* The T bit tells us if we want the low or high 16 bits of Vm */ | ||
413 | tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); | ||
414 | gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); | ||
415 | - neon_store_reg32(tmp, a->vd); | ||
416 | + vfp_store_reg32(tmp, a->vd); | ||
417 | tcg_temp_free_i32(ahp_mode); | ||
418 | tcg_temp_free_ptr(fpst); | ||
419 | tcg_temp_free_i32(tmp); | ||
420 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_VCVT_f16_f32 *a) | ||
421 | ahp_mode = get_ahp_flag(); | ||
422 | tmp = tcg_temp_new_i32(); | ||
423 | |||
424 | - neon_load_reg32(tmp, a->vm); | ||
425 | + vfp_load_reg32(tmp, a->vm); | ||
426 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); | ||
427 | tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); | ||
428 | tcg_temp_free_i32(ahp_mode); | ||
429 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VRINTR_sp *a) | ||
430 | } | ||
431 | |||
432 | tmp = tcg_temp_new_i32(); | ||
433 | - neon_load_reg32(tmp, a->vm); | ||
434 | + vfp_load_reg32(tmp, a->vm); | ||
435 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
436 | gen_helper_rinth(tmp, tmp, fpst); | ||
437 | - neon_store_reg32(tmp, a->vd); | ||
438 | + vfp_store_reg32(tmp, a->vd); | ||
439 | tcg_temp_free_ptr(fpst); | ||
440 | tcg_temp_free_i32(tmp); | ||
441 | return true; | ||
442 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VRINTR_sp *a) | ||
443 | } | ||
444 | |||
445 | tmp = tcg_temp_new_i32(); | ||
446 | - neon_load_reg32(tmp, a->vm); | ||
447 | + vfp_load_reg32(tmp, a->vm); | ||
448 | fpst = fpstatus_ptr(FPST_FPCR); | ||
449 | gen_helper_rints(tmp, tmp, fpst); | ||
450 | - neon_store_reg32(tmp, a->vd); | ||
451 | + vfp_store_reg32(tmp, a->vd); | ||
452 | tcg_temp_free_ptr(fpst); | ||
453 | tcg_temp_free_i32(tmp); | ||
454 | return true; | ||
455 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a) | ||
456 | } | ||
457 | |||
458 | tmp = tcg_temp_new_i32(); | ||
459 | - neon_load_reg32(tmp, a->vm); | ||
460 | + vfp_load_reg32(tmp, a->vm); | ||
461 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
462 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
463 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
464 | gen_helper_rinth(tmp, tmp, fpst); | ||
465 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
466 | - neon_store_reg32(tmp, a->vd); | ||
467 | + vfp_store_reg32(tmp, a->vd); | ||
468 | tcg_temp_free_ptr(fpst); | ||
469 | tcg_temp_free_i32(tcg_rmode); | ||
470 | tcg_temp_free_i32(tmp); | ||
471 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a) | ||
472 | } | ||
473 | |||
474 | tmp = tcg_temp_new_i32(); | ||
475 | - neon_load_reg32(tmp, a->vm); | ||
476 | + vfp_load_reg32(tmp, a->vm); | ||
477 | fpst = fpstatus_ptr(FPST_FPCR); | ||
478 | tcg_rmode = tcg_const_i32(float_round_to_zero); | ||
479 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
480 | gen_helper_rints(tmp, tmp, fpst); | ||
481 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
482 | - neon_store_reg32(tmp, a->vd); | ||
483 | + vfp_store_reg32(tmp, a->vd); | ||
484 | tcg_temp_free_ptr(fpst); | ||
485 | tcg_temp_free_i32(tcg_rmode); | ||
486 | tcg_temp_free_i32(tmp); | ||
487 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VRINTX_sp *a) | ||
488 | } | ||
489 | |||
490 | tmp = tcg_temp_new_i32(); | ||
491 | - neon_load_reg32(tmp, a->vm); | ||
492 | + vfp_load_reg32(tmp, a->vm); | ||
493 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
494 | gen_helper_rinth_exact(tmp, tmp, fpst); | ||
495 | - neon_store_reg32(tmp, a->vd); | ||
496 | + vfp_store_reg32(tmp, a->vd); | ||
497 | tcg_temp_free_ptr(fpst); | ||
498 | tcg_temp_free_i32(tmp); | ||
499 | return true; | ||
500 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VRINTX_sp *a) | ||
501 | } | ||
502 | |||
503 | tmp = tcg_temp_new_i32(); | ||
504 | - neon_load_reg32(tmp, a->vm); | ||
505 | + vfp_load_reg32(tmp, a->vm); | ||
506 | fpst = fpstatus_ptr(FPST_FPCR); | ||
507 | gen_helper_rints_exact(tmp, tmp, fpst); | ||
508 | - neon_store_reg32(tmp, a->vd); | ||
509 | + vfp_store_reg32(tmp, a->vd); | ||
510 | tcg_temp_free_ptr(fpst); | ||
511 | tcg_temp_free_i32(tmp); | ||
512 | return true; | ||
513 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
514 | |||
515 | vm = tcg_temp_new_i32(); | ||
516 | vd = tcg_temp_new_i64(); | ||
517 | - neon_load_reg32(vm, a->vm); | ||
518 | + vfp_load_reg32(vm, a->vm); | ||
519 | gen_helper_vfp_fcvtds(vd, vm, cpu_env); | ||
520 | neon_store_reg64(vd, a->vd); | ||
521 | tcg_temp_free_i32(vm); | ||
522 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
523 | vm = tcg_temp_new_i64(); | ||
524 | neon_load_reg64(vm, a->vm); | ||
525 | gen_helper_vfp_fcvtsd(vd, vm, cpu_env); | ||
526 | - neon_store_reg32(vd, a->vd); | ||
527 | + vfp_store_reg32(vd, a->vd); | ||
528 | tcg_temp_free_i32(vd); | ||
529 | tcg_temp_free_i64(vm); | ||
530 | return true; | ||
531 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) | ||
532 | } | ||
533 | |||
534 | vm = tcg_temp_new_i32(); | ||
535 | - neon_load_reg32(vm, a->vm); | ||
536 | + vfp_load_reg32(vm, a->vm); | ||
537 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
538 | if (a->s) { | ||
539 | /* i32 -> f16 */ | ||
540 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VCVT_int_sp *a) | ||
541 | /* u32 -> f16 */ | ||
542 | gen_helper_vfp_uitoh(vm, vm, fpst); | ||
543 | } | ||
544 | - neon_store_reg32(vm, a->vd); | ||
545 | + vfp_store_reg32(vm, a->vd); | ||
546 | tcg_temp_free_i32(vm); | ||
547 | tcg_temp_free_ptr(fpst); | ||
548 | return true; | ||
549 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
550 | } | ||
551 | |||
552 | vm = tcg_temp_new_i32(); | ||
553 | - neon_load_reg32(vm, a->vm); | ||
554 | + vfp_load_reg32(vm, a->vm); | ||
555 | fpst = fpstatus_ptr(FPST_FPCR); | ||
556 | if (a->s) { | ||
557 | /* i32 -> f32 */ | ||
558 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a) | ||
559 | /* u32 -> f32 */ | ||
560 | gen_helper_vfp_uitos(vm, vm, fpst); | ||
561 | } | ||
562 | - neon_store_reg32(vm, a->vd); | ||
563 | + vfp_store_reg32(vm, a->vd); | ||
564 | tcg_temp_free_i32(vm); | ||
565 | tcg_temp_free_ptr(fpst); | ||
566 | return true; | ||
567 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
568 | |||
569 | vm = tcg_temp_new_i32(); | ||
570 | vd = tcg_temp_new_i64(); | ||
571 | - neon_load_reg32(vm, a->vm); | ||
572 | + vfp_load_reg32(vm, a->vm); | ||
573 | fpst = fpstatus_ptr(FPST_FPCR); | ||
574 | if (a->s) { | ||
575 | /* i32 -> f64 */ | ||
576 | @@ -XXX,XX +XXX,XX @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
577 | vd = tcg_temp_new_i32(); | ||
578 | neon_load_reg64(vm, a->vm); | ||
579 | gen_helper_vjcvt(vd, vm, cpu_env); | ||
580 | - neon_store_reg32(vd, a->vd); | ||
581 | + vfp_store_reg32(vd, a->vd); | ||
582 | tcg_temp_free_i64(vm); | ||
583 | tcg_temp_free_i32(vd); | ||
584 | return true; | ||
585 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
586 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
587 | |||
588 | vd = tcg_temp_new_i32(); | ||
589 | - neon_load_reg32(vd, a->vd); | ||
590 | + vfp_load_reg32(vd, a->vd); | ||
591 | |||
592 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
593 | shift = tcg_const_i32(frac_bits); | ||
594 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
595 | g_assert_not_reached(); | ||
596 | } | ||
597 | |||
598 | - neon_store_reg32(vd, a->vd); | ||
599 | + vfp_store_reg32(vd, a->vd); | ||
600 | tcg_temp_free_i32(vd); | ||
601 | tcg_temp_free_i32(shift); | ||
602 | tcg_temp_free_ptr(fpst); | ||
603 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
604 | frac_bits = (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); | ||
605 | |||
606 | vd = tcg_temp_new_i32(); | ||
607 | - neon_load_reg32(vd, a->vd); | ||
608 | + vfp_load_reg32(vd, a->vd); | ||
609 | |||
610 | fpst = fpstatus_ptr(FPST_FPCR); | ||
611 | shift = tcg_const_i32(frac_bits); | ||
612 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a) | ||
613 | g_assert_not_reached(); | ||
614 | } | ||
615 | |||
616 | - neon_store_reg32(vd, a->vd); | ||
617 | + vfp_store_reg32(vd, a->vd); | ||
618 | tcg_temp_free_i32(vd); | ||
619 | tcg_temp_free_i32(shift); | ||
620 | tcg_temp_free_ptr(fpst); | ||
621 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
622 | |||
623 | fpst = fpstatus_ptr(FPST_FPCR_F16); | ||
624 | vm = tcg_temp_new_i32(); | ||
625 | - neon_load_reg32(vm, a->vm); | ||
626 | + vfp_load_reg32(vm, a->vm); | ||
627 | |||
628 | if (a->s) { | ||
629 | if (a->rz) { | ||
630 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
631 | gen_helper_vfp_touih(vm, vm, fpst); | ||
632 | } | ||
633 | } | ||
634 | - neon_store_reg32(vm, a->vd); | ||
635 | + vfp_store_reg32(vm, a->vd); | ||
636 | tcg_temp_free_i32(vm); | ||
637 | tcg_temp_free_ptr(fpst); | ||
638 | return true; | ||
639 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
640 | |||
641 | fpst = fpstatus_ptr(FPST_FPCR); | ||
642 | vm = tcg_temp_new_i32(); | ||
643 | - neon_load_reg32(vm, a->vm); | ||
644 | + vfp_load_reg32(vm, a->vm); | ||
645 | |||
646 | if (a->s) { | ||
647 | if (a->rz) { | ||
648 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a) | ||
649 | gen_helper_vfp_touis(vm, vm, fpst); | ||
650 | } | ||
651 | } | ||
652 | - neon_store_reg32(vm, a->vd); | ||
653 | + vfp_store_reg32(vm, a->vd); | ||
654 | tcg_temp_free_i32(vm); | ||
655 | tcg_temp_free_ptr(fpst); | ||
656 | return true; | ||
657 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
658 | gen_helper_vfp_touid(vd, vm, fpst); | ||
659 | } | ||
660 | } | ||
661 | - neon_store_reg32(vd, a->vd); | ||
662 | + vfp_store_reg32(vd, a->vd); | ||
663 | tcg_temp_free_i32(vd); | ||
664 | tcg_temp_free_i64(vm); | ||
665 | tcg_temp_free_ptr(fpst); | ||
666 | @@ -XXX,XX +XXX,XX @@ static bool trans_VINS(DisasContext *s, arg_VINS *a) | ||
667 | /* Insert low half of Vm into high half of Vd */ | ||
668 | rm = tcg_temp_new_i32(); | ||
669 | rd = tcg_temp_new_i32(); | ||
670 | - neon_load_reg32(rm, a->vm); | ||
671 | - neon_load_reg32(rd, a->vd); | ||
672 | + vfp_load_reg32(rm, a->vm); | ||
673 | + vfp_load_reg32(rd, a->vd); | ||
674 | tcg_gen_deposit_i32(rd, rd, rm, 16, 16); | ||
675 | - neon_store_reg32(rd, a->vd); | ||
676 | + vfp_store_reg32(rd, a->vd); | ||
677 | tcg_temp_free_i32(rm); | ||
678 | tcg_temp_free_i32(rd); | ||
679 | return true; | ||
680 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a) | ||
681 | |||
682 | /* Set Vd to high half of Vm */ | ||
683 | rm = tcg_temp_new_i32(); | ||
684 | - neon_load_reg32(rm, a->vm); | ||
685 | + vfp_load_reg32(rm, a->vm); | ||
686 | tcg_gen_shri_i32(rm, rm, 16); | ||
687 | - neon_store_reg32(rm, a->vd); | ||
688 | + vfp_store_reg32(rm, a->vd); | ||
689 | tcg_temp_free_i32(rm); | ||
690 | return true; | ||
691 | } | ||
692 | -- | 291 | -- |
693 | 2.20.1 | 292 | 2.20.1 |
694 | 293 | ||
695 | 294 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE shifts by immediate, which perform shifts |
---|---|---|---|
2 | 2 | on a single general-purpose register. | |
3 | These are the only users of neon_reg_offset, so remove that. | 3 | |
4 | 4 | These patterns overlap with the long-shift-by-immediates, | |
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 5 | so we have to rearrange the grouping a little here. |
6 | Message-id: 20201030022618.785675-4-richard.henderson@linaro.org | 6 | |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210628135835.6690-18-peter.maydell@linaro.org | ||
9 | --- | 10 | --- |
10 | target/arm/translate.c | 14 ++------------ | 11 | target/arm/helper-mve.h | 3 ++ |
11 | 1 file changed, 2 insertions(+), 12 deletions(-) | 12 | target/arm/translate.h | 1 + |
12 | 13 | target/arm/t32.decode | 31 ++++++++++++++----- | |
14 | target/arm/mve_helper.c | 10 ++++++ | ||
15 | target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++-- | ||
16 | 5 files changed, 104 insertions(+), 9 deletions(-) | ||
17 | |||
18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/target/arm/helper-mve.h | ||
21 | +++ b/target/arm/helper-mve.h | ||
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
23 | DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
24 | DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
25 | DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) | ||
26 | + | ||
27 | +DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
28 | +DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
29 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate.h | ||
32 | +++ b/target/arm/translate.h | ||
33 | @@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
34 | typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
35 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
36 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
37 | +typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | ||
38 | |||
39 | /** | ||
40 | * arm_tbflags_from_tb: | ||
41 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/t32.decode | ||
44 | +++ b/target/arm/t32.decode | ||
45 | @@ -XXX,XX +XXX,XX @@ | ||
46 | |||
47 | &mve_shl_ri rdalo rdahi shim | ||
48 | &mve_shl_rr rdalo rdahi rm | ||
49 | +&mve_sh_ri rda shim | ||
50 | |||
51 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
52 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
55 | @mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \ | ||
56 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
57 | +@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ | ||
58 | + &mve_sh_ri shim=%imm5_12_6 | ||
59 | |||
60 | { | ||
61 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
62 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
63 | # the rest fall through (where ORR_rrri and MOV_rxri will end up | ||
64 | # handling them as r13 and r15 accesses with the same semantics as A32). | ||
65 | [ | ||
66 | - LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
67 | - LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
68 | - ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
69 | + { | ||
70 | + UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri | ||
71 | + LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
72 | + UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
73 | + } | ||
74 | |||
75 | - UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri | ||
76 | - URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
77 | - SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
78 | - SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
79 | + { | ||
80 | + URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri | ||
81 | + LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
82 | + URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri | ||
83 | + } | ||
84 | + | ||
85 | + { | ||
86 | + SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri | ||
87 | + ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
88 | + SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri | ||
89 | + } | ||
90 | + | ||
91 | + { | ||
92 | + SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri | ||
93 | + SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
94 | + } | ||
95 | |||
96 | LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
97 | ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
98 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
99 | index XXXXXXX..XXXXXXX 100644 | ||
100 | --- a/target/arm/mve_helper.c | ||
101 | +++ b/target/arm/mve_helper.c | ||
102 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift) | ||
103 | { | ||
104 | return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF); | ||
105 | } | ||
106 | + | ||
107 | +uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
108 | +{ | ||
109 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
110 | +} | ||
111 | + | ||
112 | +uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
113 | +{ | ||
114 | + return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
115 | +} | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 116 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
14 | index XXXXXXX..XXXXXXX 100644 | 117 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 118 | --- a/target/arm/translate.c |
16 | +++ b/target/arm/translate.c | 119 | +++ b/target/arm/translate.c |
17 | @@ -XXX,XX +XXX,XX @@ static inline long vfp_reg_offset(bool dp, unsigned reg) | 120 | @@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) |
18 | } | 121 | |
122 | static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) | ||
123 | { | ||
124 | - TCGv_i32 t = tcg_temp_new_i32(); | ||
125 | + TCGv_i32 t; | ||
126 | |||
127 | + /* Handle shift by the input size for the benefit of trans_SRSHR_ri */ | ||
128 | + if (sh == 32) { | ||
129 | + tcg_gen_movi_i32(d, 0); | ||
130 | + return; | ||
131 | + } | ||
132 | + t = tcg_temp_new_i32(); | ||
133 | tcg_gen_extract_i32(t, a, sh - 1, 1); | ||
134 | tcg_gen_sari_i32(d, a, sh); | ||
135 | tcg_gen_add_i32(d, d, t); | ||
136 | @@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh) | ||
137 | |||
138 | static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh) | ||
139 | { | ||
140 | - TCGv_i32 t = tcg_temp_new_i32(); | ||
141 | + TCGv_i32 t; | ||
142 | |||
143 | + /* Handle shift by the input size for the benefit of trans_URSHR_ri */ | ||
144 | + if (sh == 32) { | ||
145 | + tcg_gen_extract_i32(d, a, sh - 1, 1); | ||
146 | + return; | ||
147 | + } | ||
148 | + t = tcg_temp_new_i32(); | ||
149 | tcg_gen_extract_i32(t, a, sh - 1, 1); | ||
150 | tcg_gen_shri_i32(d, a, sh); | ||
151 | tcg_gen_add_i32(d, d, t); | ||
152 | @@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a) | ||
153 | return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48); | ||
19 | } | 154 | } |
20 | 155 | ||
21 | -/* Return the offset of a 32-bit piece of a NEON register. | 156 | +static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn) |
22 | - zero is the least significant end of the register. */ | 157 | +{ |
23 | -static inline long | 158 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
24 | -neon_reg_offset (int reg, int n) | 159 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ |
25 | -{ | 160 | + return false; |
26 | - int sreg; | 161 | + } |
27 | - sreg = reg * 2 + n; | 162 | + if (!dc_isar_feature(aa32_mve, s) || |
28 | - return vfp_reg_offset(0, sreg); | 163 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || |
29 | -} | 164 | + a->rda == 13 || a->rda == 15) { |
30 | - | 165 | + /* These rda cases are UNPREDICTABLE; we choose to UNDEF */ |
31 | static TCGv_i32 neon_load_reg(int reg, int pass) | 166 | + unallocated_encoding(s); |
32 | { | 167 | + return true; |
33 | TCGv_i32 tmp = tcg_temp_new_i32(); | 168 | + } |
34 | - tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); | 169 | + |
35 | + tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); | 170 | + if (a->shim == 0) { |
36 | return tmp; | 171 | + a->shim = 32; |
37 | } | 172 | + } |
38 | 173 | + fn(cpu_R[a->rda], cpu_R[a->rda], a->shim); | |
39 | static void neon_store_reg(int reg, int pass, TCGv_i32 var) | 174 | + |
40 | { | 175 | + return true; |
41 | - tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); | 176 | +} |
42 | + tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); | 177 | + |
43 | tcg_temp_free_i32(var); | 178 | +static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a) |
44 | } | 179 | +{ |
45 | 180 | + return do_mve_sh_ri(s, a, gen_urshr32_i32); | |
181 | +} | ||
182 | + | ||
183 | +static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
184 | +{ | ||
185 | + return do_mve_sh_ri(s, a, gen_srshr32_i32); | ||
186 | +} | ||
187 | + | ||
188 | +static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) | ||
189 | +{ | ||
190 | + gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift)); | ||
191 | +} | ||
192 | + | ||
193 | +static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
194 | +{ | ||
195 | + return do_mve_sh_ri(s, a, gen_mve_sqshl); | ||
196 | +} | ||
197 | + | ||
198 | +static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) | ||
199 | +{ | ||
200 | + gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift)); | ||
201 | +} | ||
202 | + | ||
203 | +static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) | ||
204 | +{ | ||
205 | + return do_mve_sh_ri(s, a, gen_mve_uqshl); | ||
206 | +} | ||
207 | + | ||
208 | /* | ||
209 | * Multiply and multiply accumulate | ||
210 | */ | ||
46 | -- | 211 | -- |
47 | 2.20.1 | 212 | 2.20.1 |
48 | 213 | ||
49 | 214 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Implement the MVE shifts by register, which perform |
---|---|---|---|
2 | shifts on a single general-purpose register. | ||
2 | 3 | ||
3 | Model these off the aa64 read/write_vec_element functions. | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Use it within translate-neon.c.inc. The new functions do | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | not allocate or free temps, so this rearranges the calling | 6 | Message-id: 20210628135835.6690-19-peter.maydell@linaro.org |
6 | code a bit. | 7 | --- |
8 | target/arm/helper-mve.h | 2 ++ | ||
9 | target/arm/translate.h | 1 + | ||
10 | target/arm/t32.decode | 18 ++++++++++++++---- | ||
11 | target/arm/mve_helper.c | 10 ++++++++++ | ||
12 | target/arm/translate.c | 30 ++++++++++++++++++++++++++++++ | ||
13 | 5 files changed, 57 insertions(+), 4 deletions(-) | ||
7 | 14 | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
9 | Message-id: 20201030022618.785675-6-richard.henderson@linaro.org | 16 | index XXXXXXX..XXXXXXX 100644 |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | --- a/target/arm/helper-mve.h |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | +++ b/target/arm/helper-mve.h |
12 | --- | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32) |
13 | target/arm/translate.c | 26 ++++ | 20 | |
14 | target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------ | 21 | DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) |
15 | 2 files changed, 183 insertions(+), 99 deletions(-) | 22 | DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32) |
16 | 23 | +DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32) | |
24 | +DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32) | ||
25 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/translate.h | ||
28 | +++ b/target/arm/translate.h | ||
29 | @@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
30 | typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); | ||
31 | typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
32 | typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); | ||
33 | +typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | ||
34 | |||
35 | /** | ||
36 | * arm_tbflags_from_tb: | ||
37 | diff --git a/target/arm/t32.decode b/target/arm/t32.decode | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/t32.decode | ||
40 | +++ b/target/arm/t32.decode | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | &mve_shl_ri rdalo rdahi shim | ||
43 | &mve_shl_rr rdalo rdahi rm | ||
44 | &mve_sh_ri rda shim | ||
45 | +&mve_sh_rr rda rm | ||
46 | |||
47 | # rdahi: bits [3:1] from insn, bit 0 is 1 | ||
48 | # rdalo: bits [3:1] from insn, bit 0 is 0 | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9 | ||
51 | @mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \ | ||
52 | &mve_sh_ri shim=%imm5_12_6 | ||
53 | +@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr | ||
54 | |||
55 | { | ||
56 | TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi | ||
57 | @@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi | ||
58 | SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri | ||
59 | } | ||
60 | |||
61 | - LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
62 | - ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
63 | - UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
64 | - SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
65 | + { | ||
66 | + UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr | ||
67 | + LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr | ||
68 | + UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr | ||
69 | + } | ||
70 | + | ||
71 | + { | ||
72 | + SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr | ||
73 | + ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr | ||
74 | + SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr | ||
75 | + } | ||
76 | + | ||
77 | UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr | ||
78 | SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr | ||
79 | ] | ||
80 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/arm/mve_helper.c | ||
83 | +++ b/target/arm/mve_helper.c | ||
84 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
85 | { | ||
86 | return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF); | ||
87 | } | ||
88 | + | ||
89 | +uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
90 | +{ | ||
91 | + return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF); | ||
92 | +} | ||
93 | + | ||
94 | +uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift) | ||
95 | +{ | ||
96 | + return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF); | ||
97 | +} | ||
17 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 98 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
18 | index XXXXXXX..XXXXXXX 100644 | 99 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/translate.c | 100 | --- a/target/arm/translate.c |
20 | +++ b/target/arm/translate.c | 101 | +++ b/target/arm/translate.c |
21 | @@ -XXX,XX +XXX,XX @@ static inline void neon_store_reg32(TCGv_i32 var, int reg) | 102 | @@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) |
22 | tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); | 103 | return do_mve_sh_ri(s, a, gen_mve_uqshl); |
23 | } | 104 | } |
24 | 105 | ||
25 | +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp size) | 106 | +static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn) |
26 | +{ | 107 | +{ |
27 | + long off = neon_element_offset(reg, ele, size); | 108 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { |
109 | + /* Decode falls through to ORR/MOV UNPREDICTABLE handling */ | ||
110 | + return false; | ||
111 | + } | ||
112 | + if (!dc_isar_feature(aa32_mve, s) || | ||
113 | + !arm_dc_feature(s, ARM_FEATURE_M_MAIN) || | ||
114 | + a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 || | ||
115 | + a->rm == a->rda) { | ||
116 | + /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */ | ||
117 | + unallocated_encoding(s); | ||
118 | + return true; | ||
119 | + } | ||
28 | + | 120 | + |
29 | + switch (size) { | 121 | + /* The helper takes care of the sign-extension of the low 8 bits of Rm */ |
30 | + case MO_32: | 122 | + fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]); |
31 | + tcg_gen_ld_i32(dest, cpu_env, off); | 123 | + return true; |
32 | + break; | ||
33 | + default: | ||
34 | + g_assert_not_reached(); | ||
35 | + } | ||
36 | +} | 124 | +} |
37 | + | 125 | + |
38 | +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp size) | 126 | +static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a) |
39 | +{ | 127 | +{ |
40 | + long off = neon_element_offset(reg, ele, size); | 128 | + return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr); |
41 | + | ||
42 | + switch (size) { | ||
43 | + case MO_32: | ||
44 | + tcg_gen_st_i32(src, cpu_env, off); | ||
45 | + break; | ||
46 | + default: | ||
47 | + g_assert_not_reached(); | ||
48 | + } | ||
49 | +} | 129 | +} |
50 | + | 130 | + |
51 | static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | 131 | +static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a) |
52 | { | 132 | +{ |
53 | TCGv_ptr ret = tcg_temp_new_ptr(); | 133 | + return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl); |
54 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | 134 | +} |
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/arm/translate-neon.c.inc | ||
57 | +++ b/target/arm/translate-neon.c.inc | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn) | ||
59 | * early. Since Q is 0 there are always just two passes, so instead | ||
60 | * of a complicated loop over each pass we just unroll. | ||
61 | */ | ||
62 | - tmp = neon_load_reg(a->vn, 0); | ||
63 | - tmp2 = neon_load_reg(a->vn, 1); | ||
64 | + tmp = tcg_temp_new_i32(); | ||
65 | + tmp2 = tcg_temp_new_i32(); | ||
66 | + tmp3 = tcg_temp_new_i32(); | ||
67 | + | 135 | + |
68 | + read_neon_element32(tmp, a->vn, 0, MO_32); | 136 | /* |
69 | + read_neon_element32(tmp2, a->vn, 1, MO_32); | 137 | * Multiply and multiply accumulate |
70 | fn(tmp, tmp, tmp2); | 138 | */ |
71 | - tcg_temp_free_i32(tmp2); | ||
72 | |||
73 | - tmp3 = neon_load_reg(a->vm, 0); | ||
74 | - tmp2 = neon_load_reg(a->vm, 1); | ||
75 | + read_neon_element32(tmp3, a->vm, 0, MO_32); | ||
76 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
77 | fn(tmp3, tmp3, tmp2); | ||
78 | - tcg_temp_free_i32(tmp2); | ||
79 | |||
80 | - neon_store_reg(a->vd, 0, tmp); | ||
81 | - neon_store_reg(a->vd, 1, tmp3); | ||
82 | + write_neon_element32(tmp, a->vd, 0, MO_32); | ||
83 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
84 | + | ||
85 | + tcg_temp_free_i32(tmp); | ||
86 | + tcg_temp_free_i32(tmp2); | ||
87 | + tcg_temp_free_i32(tmp3); | ||
88 | return true; | ||
89 | } | ||
90 | |||
91 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, | ||
92 | * 2-reg-and-shift operations, size < 3 case, where the | ||
93 | * helper needs to be passed cpu_env. | ||
94 | */ | ||
95 | - TCGv_i32 constimm; | ||
96 | + TCGv_i32 constimm, tmp; | ||
97 | int pass; | ||
98 | |||
99 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
100 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, | ||
101 | * by immediate using the variable shift operations. | ||
102 | */ | ||
103 | constimm = tcg_const_i32(dup_const(a->size, a->shift)); | ||
104 | + tmp = tcg_temp_new_i32(); | ||
105 | |||
106 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
107 | - TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
108 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
109 | fn(tmp, cpu_env, tmp, constimm); | ||
110 | - neon_store_reg(a->vd, pass, tmp); | ||
111 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
112 | } | ||
113 | + tcg_temp_free_i32(tmp); | ||
114 | tcg_temp_free_i32(constimm); | ||
115 | return true; | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, | ||
118 | constimm = tcg_const_i64(-a->shift); | ||
119 | rm1 = tcg_temp_new_i64(); | ||
120 | rm2 = tcg_temp_new_i64(); | ||
121 | + rd = tcg_temp_new_i32(); | ||
122 | |||
123 | /* Load both inputs first to avoid potential overwrite if rm == rd */ | ||
124 | neon_load_reg64(rm1, a->vm); | ||
125 | neon_load_reg64(rm2, a->vm + 1); | ||
126 | |||
127 | shiftfn(rm1, rm1, constimm); | ||
128 | - rd = tcg_temp_new_i32(); | ||
129 | narrowfn(rd, cpu_env, rm1); | ||
130 | - neon_store_reg(a->vd, 0, rd); | ||
131 | + write_neon_element32(rd, a->vd, 0, MO_32); | ||
132 | |||
133 | shiftfn(rm2, rm2, constimm); | ||
134 | - rd = tcg_temp_new_i32(); | ||
135 | narrowfn(rd, cpu_env, rm2); | ||
136 | - neon_store_reg(a->vd, 1, rd); | ||
137 | + write_neon_element32(rd, a->vd, 1, MO_32); | ||
138 | |||
139 | + tcg_temp_free_i32(rd); | ||
140 | tcg_temp_free_i64(rm1); | ||
141 | tcg_temp_free_i64(rm2); | ||
142 | tcg_temp_free_i64(constimm); | ||
143 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
144 | constimm = tcg_const_i32(imm); | ||
145 | |||
146 | /* Load all inputs first to avoid potential overwrite */ | ||
147 | - rm1 = neon_load_reg(a->vm, 0); | ||
148 | - rm2 = neon_load_reg(a->vm, 1); | ||
149 | - rm3 = neon_load_reg(a->vm + 1, 0); | ||
150 | - rm4 = neon_load_reg(a->vm + 1, 1); | ||
151 | + rm1 = tcg_temp_new_i32(); | ||
152 | + rm2 = tcg_temp_new_i32(); | ||
153 | + rm3 = tcg_temp_new_i32(); | ||
154 | + rm4 = tcg_temp_new_i32(); | ||
155 | + read_neon_element32(rm1, a->vm, 0, MO_32); | ||
156 | + read_neon_element32(rm2, a->vm, 1, MO_32); | ||
157 | + read_neon_element32(rm3, a->vm, 2, MO_32); | ||
158 | + read_neon_element32(rm4, a->vm, 3, MO_32); | ||
159 | rtmp = tcg_temp_new_i64(); | ||
160 | |||
161 | shiftfn(rm1, rm1, constimm); | ||
162 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
163 | tcg_temp_free_i32(rm2); | ||
164 | |||
165 | narrowfn(rm1, cpu_env, rtmp); | ||
166 | - neon_store_reg(a->vd, 0, rm1); | ||
167 | + write_neon_element32(rm1, a->vd, 0, MO_32); | ||
168 | + tcg_temp_free_i32(rm1); | ||
169 | |||
170 | shiftfn(rm3, rm3, constimm); | ||
171 | shiftfn(rm4, rm4, constimm); | ||
172 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
173 | |||
174 | narrowfn(rm3, cpu_env, rtmp); | ||
175 | tcg_temp_free_i64(rtmp); | ||
176 | - neon_store_reg(a->vd, 1, rm3); | ||
177 | + write_neon_element32(rm3, a->vd, 1, MO_32); | ||
178 | + tcg_temp_free_i32(rm3); | ||
179 | return true; | ||
180 | } | ||
181 | |||
182 | @@ -XXX,XX +XXX,XX @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, | ||
183 | widen_mask = dup_const(a->size + 1, widen_mask); | ||
184 | } | ||
185 | |||
186 | - rm0 = neon_load_reg(a->vm, 0); | ||
187 | - rm1 = neon_load_reg(a->vm, 1); | ||
188 | + rm0 = tcg_temp_new_i32(); | ||
189 | + rm1 = tcg_temp_new_i32(); | ||
190 | + read_neon_element32(rm0, a->vm, 0, MO_32); | ||
191 | + read_neon_element32(rm1, a->vm, 1, MO_32); | ||
192 | tmp = tcg_temp_new_i64(); | ||
193 | |||
194 | widenfn(tmp, rm0); | ||
195 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
196 | if (src1_wide) { | ||
197 | neon_load_reg64(rn0_64, a->vn); | ||
198 | } else { | ||
199 | - TCGv_i32 tmp = neon_load_reg(a->vn, 0); | ||
200 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
201 | + read_neon_element32(tmp, a->vn, 0, MO_32); | ||
202 | widenfn(rn0_64, tmp); | ||
203 | tcg_temp_free_i32(tmp); | ||
204 | } | ||
205 | - rm = neon_load_reg(a->vm, 0); | ||
206 | + rm = tcg_temp_new_i32(); | ||
207 | + read_neon_element32(rm, a->vm, 0, MO_32); | ||
208 | |||
209 | widenfn(rm_64, rm); | ||
210 | tcg_temp_free_i32(rm); | ||
211 | @@ -XXX,XX +XXX,XX @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, | ||
212 | if (src1_wide) { | ||
213 | neon_load_reg64(rn1_64, a->vn + 1); | ||
214 | } else { | ||
215 | - TCGv_i32 tmp = neon_load_reg(a->vn, 1); | ||
216 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
217 | + read_neon_element32(tmp, a->vn, 1, MO_32); | ||
218 | widenfn(rn1_64, tmp); | ||
219 | tcg_temp_free_i32(tmp); | ||
220 | } | ||
221 | - rm = neon_load_reg(a->vm, 1); | ||
222 | + rm = tcg_temp_new_i32(); | ||
223 | + read_neon_element32(rm, a->vm, 1, MO_32); | ||
224 | |||
225 | neon_store_reg64(rn0_64, a->vd); | ||
226 | |||
227 | @@ -XXX,XX +XXX,XX @@ static bool do_narrow_3d(DisasContext *s, arg_3diff *a, | ||
228 | |||
229 | narrowfn(rd1, rn_64); | ||
230 | |||
231 | - neon_store_reg(a->vd, 0, rd0); | ||
232 | - neon_store_reg(a->vd, 1, rd1); | ||
233 | + write_neon_element32(rd0, a->vd, 0, MO_32); | ||
234 | + write_neon_element32(rd1, a->vd, 1, MO_32); | ||
235 | |||
236 | + tcg_temp_free_i32(rd0); | ||
237 | + tcg_temp_free_i32(rd1); | ||
238 | tcg_temp_free_i64(rn_64); | ||
239 | tcg_temp_free_i64(rm_64); | ||
240 | |||
241 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
242 | rd0 = tcg_temp_new_i64(); | ||
243 | rd1 = tcg_temp_new_i64(); | ||
244 | |||
245 | - rn = neon_load_reg(a->vn, 0); | ||
246 | - rm = neon_load_reg(a->vm, 0); | ||
247 | + rn = tcg_temp_new_i32(); | ||
248 | + rm = tcg_temp_new_i32(); | ||
249 | + read_neon_element32(rn, a->vn, 0, MO_32); | ||
250 | + read_neon_element32(rm, a->vm, 0, MO_32); | ||
251 | opfn(rd0, rn, rm); | ||
252 | - tcg_temp_free_i32(rn); | ||
253 | - tcg_temp_free_i32(rm); | ||
254 | |||
255 | - rn = neon_load_reg(a->vn, 1); | ||
256 | - rm = neon_load_reg(a->vm, 1); | ||
257 | + read_neon_element32(rn, a->vn, 1, MO_32); | ||
258 | + read_neon_element32(rm, a->vm, 1, MO_32); | ||
259 | opfn(rd1, rn, rm); | ||
260 | tcg_temp_free_i32(rn); | ||
261 | tcg_temp_free_i32(rm); | ||
262 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_dup_high16(TCGv_i32 var) | ||
263 | |||
264 | static inline TCGv_i32 neon_get_scalar(int size, int reg) | ||
265 | { | ||
266 | - TCGv_i32 tmp; | ||
267 | - if (size == 1) { | ||
268 | - tmp = neon_load_reg(reg & 7, reg >> 4); | ||
269 | + TCGv_i32 tmp = tcg_temp_new_i32(); | ||
270 | + if (size == MO_16) { | ||
271 | + read_neon_element32(tmp, reg & 7, reg >> 4, MO_32); | ||
272 | if (reg & 8) { | ||
273 | gen_neon_dup_high16(tmp); | ||
274 | } else { | ||
275 | gen_neon_dup_low16(tmp); | ||
276 | } | ||
277 | } else { | ||
278 | - tmp = neon_load_reg(reg & 15, reg >> 4); | ||
279 | + read_neon_element32(tmp, reg & 15, reg >> 4, MO_32); | ||
280 | } | ||
281 | return tmp; | ||
282 | } | ||
283 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
284 | * perform an accumulation operation of that result into the | ||
285 | * destination. | ||
286 | */ | ||
287 | - TCGv_i32 scalar; | ||
288 | + TCGv_i32 scalar, tmp; | ||
289 | int pass; | ||
290 | |||
291 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
292 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar(DisasContext *s, arg_2scalar *a, | ||
293 | } | ||
294 | |||
295 | scalar = neon_get_scalar(a->size, a->vm); | ||
296 | + tmp = tcg_temp_new_i32(); | ||
297 | |||
298 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
299 | - TCGv_i32 tmp = neon_load_reg(a->vn, pass); | ||
300 | + read_neon_element32(tmp, a->vn, pass, MO_32); | ||
301 | opfn(tmp, tmp, scalar); | ||
302 | if (accfn) { | ||
303 | - TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
304 | + TCGv_i32 rd = tcg_temp_new_i32(); | ||
305 | + read_neon_element32(rd, a->vd, pass, MO_32); | ||
306 | accfn(tmp, rd, tmp); | ||
307 | tcg_temp_free_i32(rd); | ||
308 | } | ||
309 | - neon_store_reg(a->vd, pass, tmp); | ||
310 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
311 | } | ||
312 | + tcg_temp_free_i32(tmp); | ||
313 | tcg_temp_free_i32(scalar); | ||
314 | return true; | ||
315 | } | ||
316 | @@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | ||
317 | * performs a kind of fused op-then-accumulate using a helper | ||
318 | * function that takes all of rd, rn and the scalar at once. | ||
319 | */ | ||
320 | - TCGv_i32 scalar; | ||
321 | + TCGv_i32 scalar, rn, rd; | ||
322 | int pass; | ||
323 | |||
324 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
325 | @@ -XXX,XX +XXX,XX @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2scalar *a, | ||
326 | } | ||
327 | |||
328 | scalar = neon_get_scalar(a->size, a->vm); | ||
329 | + rn = tcg_temp_new_i32(); | ||
330 | + rd = tcg_temp_new_i32(); | ||
331 | |||
332 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
333 | - TCGv_i32 rn = neon_load_reg(a->vn, pass); | ||
334 | - TCGv_i32 rd = neon_load_reg(a->vd, pass); | ||
335 | + read_neon_element32(rn, a->vn, pass, MO_32); | ||
336 | + read_neon_element32(rd, a->vd, pass, MO_32); | ||
337 | opfn(rd, cpu_env, rn, scalar, rd); | ||
338 | - tcg_temp_free_i32(rn); | ||
339 | - neon_store_reg(a->vd, pass, rd); | ||
340 | + write_neon_element32(rd, a->vd, pass, MO_32); | ||
341 | } | ||
342 | + tcg_temp_free_i32(rn); | ||
343 | + tcg_temp_free_i32(rd); | ||
344 | tcg_temp_free_i32(scalar); | ||
345 | |||
346 | return true; | ||
347 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
348 | scalar = neon_get_scalar(a->size, a->vm); | ||
349 | |||
350 | /* Load all inputs before writing any outputs, in case of overlap */ | ||
351 | - rn = neon_load_reg(a->vn, 0); | ||
352 | + rn = tcg_temp_new_i32(); | ||
353 | + read_neon_element32(rn, a->vn, 0, MO_32); | ||
354 | rn0_64 = tcg_temp_new_i64(); | ||
355 | opfn(rn0_64, rn, scalar); | ||
356 | - tcg_temp_free_i32(rn); | ||
357 | |||
358 | - rn = neon_load_reg(a->vn, 1); | ||
359 | + read_neon_element32(rn, a->vn, 1, MO_32); | ||
360 | rn1_64 = tcg_temp_new_i64(); | ||
361 | opfn(rn1_64, rn, scalar); | ||
362 | tcg_temp_free_i32(rn); | ||
363 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
364 | return false; | ||
365 | } | ||
366 | n <<= 3; | ||
367 | + tmp = tcg_temp_new_i32(); | ||
368 | if (a->op) { | ||
369 | - tmp = neon_load_reg(a->vd, 0); | ||
370 | + read_neon_element32(tmp, a->vd, 0, MO_32); | ||
371 | } else { | ||
372 | - tmp = tcg_temp_new_i32(); | ||
373 | tcg_gen_movi_i32(tmp, 0); | ||
374 | } | ||
375 | - tmp2 = neon_load_reg(a->vm, 0); | ||
376 | + tmp2 = tcg_temp_new_i32(); | ||
377 | + read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
378 | ptr1 = vfp_reg_ptr(true, a->vn); | ||
379 | tmp4 = tcg_const_i32(n); | ||
380 | gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
381 | - tcg_temp_free_i32(tmp); | ||
382 | + | ||
383 | if (a->op) { | ||
384 | - tmp = neon_load_reg(a->vd, 1); | ||
385 | + read_neon_element32(tmp, a->vd, 1, MO_32); | ||
386 | } else { | ||
387 | - tmp = tcg_temp_new_i32(); | ||
388 | tcg_gen_movi_i32(tmp, 0); | ||
389 | } | ||
390 | - tmp3 = neon_load_reg(a->vm, 1); | ||
391 | + tmp3 = tcg_temp_new_i32(); | ||
392 | + read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
393 | gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
394 | + tcg_temp_free_i32(tmp); | ||
395 | tcg_temp_free_i32(tmp4); | ||
396 | tcg_temp_free_ptr(ptr1); | ||
397 | - neon_store_reg(a->vd, 0, tmp2); | ||
398 | - neon_store_reg(a->vd, 1, tmp3); | ||
399 | - tcg_temp_free_i32(tmp); | ||
400 | + | ||
401 | + write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
402 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
403 | + tcg_temp_free_i32(tmp2); | ||
404 | + tcg_temp_free_i32(tmp3); | ||
405 | return true; | ||
406 | } | ||
407 | |||
408 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
409 | static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
410 | { | ||
411 | int pass, half; | ||
412 | + TCGv_i32 tmp[2]; | ||
413 | |||
414 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
415 | return false; | ||
416 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
417 | return true; | ||
418 | } | ||
419 | |||
420 | - for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
421 | - TCGv_i32 tmp[2]; | ||
422 | + tmp[0] = tcg_temp_new_i32(); | ||
423 | + tmp[1] = tcg_temp_new_i32(); | ||
424 | |||
425 | + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
426 | for (half = 0; half < 2; half++) { | ||
427 | - tmp[half] = neon_load_reg(a->vm, pass * 2 + half); | ||
428 | + read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32); | ||
429 | switch (a->size) { | ||
430 | case 0: | ||
431 | tcg_gen_bswap32_i32(tmp[half], tmp[half]); | ||
432 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
433 | g_assert_not_reached(); | ||
434 | } | ||
435 | } | ||
436 | - neon_store_reg(a->vd, pass * 2, tmp[1]); | ||
437 | - neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); | ||
438 | + write_neon_element32(tmp[1], a->vd, pass * 2, MO_32); | ||
439 | + write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32); | ||
440 | } | ||
441 | + | ||
442 | + tcg_temp_free_i32(tmp[0]); | ||
443 | + tcg_temp_free_i32(tmp[1]); | ||
444 | return true; | ||
445 | } | ||
446 | |||
447 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
448 | rm0_64 = tcg_temp_new_i64(); | ||
449 | rm1_64 = tcg_temp_new_i64(); | ||
450 | rd_64 = tcg_temp_new_i64(); | ||
451 | - tmp = neon_load_reg(a->vm, pass * 2); | ||
452 | + | ||
453 | + tmp = tcg_temp_new_i32(); | ||
454 | + read_neon_element32(tmp, a->vm, pass * 2, MO_32); | ||
455 | widenfn(rm0_64, tmp); | ||
456 | - tcg_temp_free_i32(tmp); | ||
457 | - tmp = neon_load_reg(a->vm, pass * 2 + 1); | ||
458 | + read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32); | ||
459 | widenfn(rm1_64, tmp); | ||
460 | tcg_temp_free_i32(tmp); | ||
461 | + | ||
462 | opfn(rd_64, rm0_64, rm1_64); | ||
463 | tcg_temp_free_i64(rm0_64); | ||
464 | tcg_temp_free_i64(rm1_64); | ||
465 | @@ -XXX,XX +XXX,XX @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
466 | narrowfn(rd0, cpu_env, rm); | ||
467 | neon_load_reg64(rm, a->vm + 1); | ||
468 | narrowfn(rd1, cpu_env, rm); | ||
469 | - neon_store_reg(a->vd, 0, rd0); | ||
470 | - neon_store_reg(a->vd, 1, rd1); | ||
471 | + write_neon_element32(rd0, a->vd, 0, MO_32); | ||
472 | + write_neon_element32(rd1, a->vd, 1, MO_32); | ||
473 | + tcg_temp_free_i32(rd0); | ||
474 | + tcg_temp_free_i32(rd1); | ||
475 | tcg_temp_free_i64(rm); | ||
476 | return true; | ||
477 | } | ||
478 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
479 | } | ||
480 | |||
481 | rd = tcg_temp_new_i64(); | ||
482 | + rm0 = tcg_temp_new_i32(); | ||
483 | + rm1 = tcg_temp_new_i32(); | ||
484 | |||
485 | - rm0 = neon_load_reg(a->vm, 0); | ||
486 | - rm1 = neon_load_reg(a->vm, 1); | ||
487 | + read_neon_element32(rm0, a->vm, 0, MO_32); | ||
488 | + read_neon_element32(rm1, a->vm, 1, MO_32); | ||
489 | |||
490 | widenfn(rd, rm0); | ||
491 | tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
492 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) | ||
493 | |||
494 | fpst = fpstatus_ptr(FPST_STD); | ||
495 | ahp = get_ahp_flag(); | ||
496 | - tmp = neon_load_reg(a->vm, 0); | ||
497 | + tmp = tcg_temp_new_i32(); | ||
498 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
499 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
500 | - tmp2 = neon_load_reg(a->vm, 1); | ||
501 | + tmp2 = tcg_temp_new_i32(); | ||
502 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
503 | gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); | ||
504 | tcg_gen_shli_i32(tmp2, tmp2, 16); | ||
505 | tcg_gen_or_i32(tmp2, tmp2, tmp); | ||
506 | - tcg_temp_free_i32(tmp); | ||
507 | - tmp = neon_load_reg(a->vm, 2); | ||
508 | + read_neon_element32(tmp, a->vm, 2, MO_32); | ||
509 | gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
510 | - tmp3 = neon_load_reg(a->vm, 3); | ||
511 | - neon_store_reg(a->vd, 0, tmp2); | ||
512 | + tmp3 = tcg_temp_new_i32(); | ||
513 | + read_neon_element32(tmp3, a->vm, 3, MO_32); | ||
514 | + write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
515 | + tcg_temp_free_i32(tmp2); | ||
516 | gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); | ||
517 | tcg_gen_shli_i32(tmp3, tmp3, 16); | ||
518 | tcg_gen_or_i32(tmp3, tmp3, tmp); | ||
519 | - neon_store_reg(a->vd, 1, tmp3); | ||
520 | + write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
521 | + tcg_temp_free_i32(tmp3); | ||
522 | tcg_temp_free_i32(tmp); | ||
523 | tcg_temp_free_i32(ahp); | ||
524 | tcg_temp_free_ptr(fpst); | ||
525 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
526 | fpst = fpstatus_ptr(FPST_STD); | ||
527 | ahp = get_ahp_flag(); | ||
528 | tmp3 = tcg_temp_new_i32(); | ||
529 | - tmp = neon_load_reg(a->vm, 0); | ||
530 | - tmp2 = neon_load_reg(a->vm, 1); | ||
531 | + tmp2 = tcg_temp_new_i32(); | ||
532 | + tmp = tcg_temp_new_i32(); | ||
533 | + read_neon_element32(tmp, a->vm, 0, MO_32); | ||
534 | + read_neon_element32(tmp2, a->vm, 1, MO_32); | ||
535 | tcg_gen_ext16u_i32(tmp3, tmp); | ||
536 | gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
537 | - neon_store_reg(a->vd, 0, tmp3); | ||
538 | + write_neon_element32(tmp3, a->vd, 0, MO_32); | ||
539 | tcg_gen_shri_i32(tmp, tmp, 16); | ||
540 | gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); | ||
541 | - neon_store_reg(a->vd, 1, tmp); | ||
542 | - tmp3 = tcg_temp_new_i32(); | ||
543 | + write_neon_element32(tmp, a->vd, 1, MO_32); | ||
544 | + tcg_temp_free_i32(tmp); | ||
545 | tcg_gen_ext16u_i32(tmp3, tmp2); | ||
546 | gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
547 | - neon_store_reg(a->vd, 2, tmp3); | ||
548 | + write_neon_element32(tmp3, a->vd, 2, MO_32); | ||
549 | + tcg_temp_free_i32(tmp3); | ||
550 | tcg_gen_shri_i32(tmp2, tmp2, 16); | ||
551 | gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); | ||
552 | - neon_store_reg(a->vd, 3, tmp2); | ||
553 | + write_neon_element32(tmp2, a->vd, 3, MO_32); | ||
554 | + tcg_temp_free_i32(tmp2); | ||
555 | tcg_temp_free_i32(ahp); | ||
556 | tcg_temp_free_ptr(fpst); | ||
557 | |||
558 | @@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) | ||
559 | |||
560 | static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
561 | { | ||
562 | + TCGv_i32 tmp; | ||
563 | int pass; | ||
564 | |||
565 | /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ | ||
566 | @@ -XXX,XX +XXX,XX @@ static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
567 | return true; | ||
568 | } | ||
569 | |||
570 | + tmp = tcg_temp_new_i32(); | ||
571 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
572 | - TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
573 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
574 | fn(tmp, tmp); | ||
575 | - neon_store_reg(a->vd, pass, tmp); | ||
576 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
577 | } | ||
578 | + tcg_temp_free_i32(tmp); | ||
579 | |||
580 | return true; | ||
581 | } | ||
582 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTRN(DisasContext *s, arg_2misc *a) | ||
583 | return true; | ||
584 | } | ||
585 | |||
586 | - if (a->size == 2) { | ||
587 | + tmp = tcg_temp_new_i32(); | ||
588 | + tmp2 = tcg_temp_new_i32(); | ||
589 | + if (a->size == MO_32) { | ||
590 | for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) { | ||
591 | - tmp = neon_load_reg(a->vm, pass); | ||
592 | - tmp2 = neon_load_reg(a->vd, pass + 1); | ||
593 | - neon_store_reg(a->vm, pass, tmp2); | ||
594 | - neon_store_reg(a->vd, pass + 1, tmp); | ||
595 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
596 | + read_neon_element32(tmp2, a->vd, pass + 1, MO_32); | ||
597 | + write_neon_element32(tmp2, a->vm, pass, MO_32); | ||
598 | + write_neon_element32(tmp, a->vd, pass + 1, MO_32); | ||
599 | } | ||
600 | } else { | ||
601 | for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
602 | - tmp = neon_load_reg(a->vm, pass); | ||
603 | - tmp2 = neon_load_reg(a->vd, pass); | ||
604 | - if (a->size == 0) { | ||
605 | + read_neon_element32(tmp, a->vm, pass, MO_32); | ||
606 | + read_neon_element32(tmp2, a->vd, pass, MO_32); | ||
607 | + if (a->size == MO_8) { | ||
608 | gen_neon_trn_u8(tmp, tmp2); | ||
609 | } else { | ||
610 | gen_neon_trn_u16(tmp, tmp2); | ||
611 | } | ||
612 | - neon_store_reg(a->vm, pass, tmp2); | ||
613 | - neon_store_reg(a->vd, pass, tmp); | ||
614 | + write_neon_element32(tmp2, a->vm, pass, MO_32); | ||
615 | + write_neon_element32(tmp, a->vd, pass, MO_32); | ||
616 | } | ||
617 | } | ||
618 | + tcg_temp_free_i32(tmp); | ||
619 | + tcg_temp_free_i32(tmp2); | ||
620 | return true; | ||
621 | } | ||
622 | -- | 139 | -- |
623 | 2.20.1 | 140 | 2.20.1 |
624 | 141 | ||
625 | 142 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | In both cases, we can sink the write-back and perform | ||
4 | the accumulate into the normal destination temps. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201030022618.785675-11-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate-neon.c.inc | 23 +++++++++-------------- | ||
12 | 1 file changed, 9 insertions(+), 14 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate-neon.c.inc | ||
17 | +++ b/target/arm/translate-neon.c.inc | ||
18 | @@ -XXX,XX +XXX,XX @@ static bool do_long_3d(DisasContext *s, arg_3diff *a, | ||
19 | if (accfn) { | ||
20 | tmp = tcg_temp_new_i64(); | ||
21 | read_neon_element64(tmp, a->vd, 0, MO_64); | ||
22 | - accfn(tmp, tmp, rd0); | ||
23 | - write_neon_element64(tmp, a->vd, 0, MO_64); | ||
24 | + accfn(rd0, tmp, rd0); | ||
25 | read_neon_element64(tmp, a->vd, 1, MO_64); | ||
26 | - accfn(tmp, tmp, rd1); | ||
27 | - write_neon_element64(tmp, a->vd, 1, MO_64); | ||
28 | + accfn(rd1, tmp, rd1); | ||
29 | tcg_temp_free_i64(tmp); | ||
30 | - } else { | ||
31 | - write_neon_element64(rd0, a->vd, 0, MO_64); | ||
32 | - write_neon_element64(rd1, a->vd, 1, MO_64); | ||
33 | } | ||
34 | |||
35 | + write_neon_element64(rd0, a->vd, 0, MO_64); | ||
36 | + write_neon_element64(rd1, a->vd, 1, MO_64); | ||
37 | tcg_temp_free_i64(rd0); | ||
38 | tcg_temp_free_i64(rd1); | ||
39 | |||
40 | @@ -XXX,XX +XXX,XX @@ static bool do_2scalar_long(DisasContext *s, arg_2scalar *a, | ||
41 | if (accfn) { | ||
42 | TCGv_i64 t64 = tcg_temp_new_i64(); | ||
43 | read_neon_element64(t64, a->vd, 0, MO_64); | ||
44 | - accfn(t64, t64, rn0_64); | ||
45 | - write_neon_element64(t64, a->vd, 0, MO_64); | ||
46 | + accfn(rn0_64, t64, rn0_64); | ||
47 | read_neon_element64(t64, a->vd, 1, MO_64); | ||
48 | - accfn(t64, t64, rn1_64); | ||
49 | - write_neon_element64(t64, a->vd, 1, MO_64); | ||
50 | + accfn(rn1_64, t64, rn1_64); | ||
51 | tcg_temp_free_i64(t64); | ||
52 | - } else { | ||
53 | - write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
54 | - write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
55 | } | ||
56 | + | ||
57 | + write_neon_element64(rn0_64, a->vd, 0, MO_64); | ||
58 | + write_neon_element64(rn1_64, a->vd, 1, MO_64); | ||
59 | tcg_temp_free_i64(rn0_64); | ||
60 | tcg_temp_free_i64(rn1_64); | ||
61 | return true; | ||
62 | -- | ||
63 | 2.20.1 | ||
64 | |||
65 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | If we're using the capstone disassembler, disassembly of a run of | ||
2 | instructions more than 32 bytes long disassembles the wrong data for | ||
3 | instructions beyond the 32 byte mark: | ||
4 | 1 | ||
5 | (qemu) xp /16x 0x100 | ||
6 | 0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000 | ||
7 | 0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000 | ||
8 | 0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574 | ||
9 | 0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000 | ||
10 | (qemu) xp /16i 0x100 | ||
11 | 0x00000100: 00000005 andeq r0, r0, r5 | ||
12 | 0x00000104: 54410001 strbpl r0, [r1], #-1 | ||
13 | 0x00000108: 00000001 andeq r0, r0, r1 | ||
14 | 0x0000010c: 00001000 andeq r1, r0, r0 | ||
15 | 0x00000110: 00000000 andeq r0, r0, r0 | ||
16 | 0x00000114: 00000004 andeq r0, r0, r4 | ||
17 | 0x00000118: 54410002 strbpl r0, [r1], #-2 | ||
18 | 0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c | ||
19 | 0x00000120: 54410001 strbpl r0, [r1], #-1 | ||
20 | 0x00000124: 00000001 andeq r0, r0, r1 | ||
21 | 0x00000128: 00001000 andeq r1, r0, r0 | ||
22 | 0x0000012c: 00000000 andeq r0, r0, r0 | ||
23 | 0x00000130: 00000004 andeq r0, r0, r4 | ||
24 | 0x00000134: 54410002 strbpl r0, [r1], #-2 | ||
25 | 0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c | ||
26 | 0x0000013c: 00000000 andeq r0, r0, r0 | ||
27 | |||
28 | Here the disassembly of 0x120..0x13f is using the data that is in | ||
29 | 0x104..0x123. | ||
30 | |||
31 | This is caused by passing the wrong value to the read_memory_func(). | ||
32 | The intention is that at this point in the loop the 'cap_buf' buffer | ||
33 | already contains 'csize' bytes of data for the instruction at guest | ||
34 | addr 'pc', and we want to read in an extra 'tsize' bytes. Those | ||
35 | extra bytes are therefore at 'pc + csize', not 'pc'. On the first | ||
36 | time through the loop 'csize' happens to be zero, so the initial read | ||
37 | of 32 bytes into cap_buf is correct and as long as the disassembly | ||
38 | never needs to read more data we return the correct information. | ||
39 | |||
40 | Use the correct guest address in the call to read_memory_func(). | ||
41 | |||
42 | Cc: qemu-stable@nongnu.org | ||
43 | Fixes: https://bugs.launchpad.net/qemu/+bug/1900779 | ||
44 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
45 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
46 | Message-id: 20201022132445.25039-1-peter.maydell@linaro.org | ||
47 | --- | ||
48 | disas/capstone.c | 2 +- | ||
49 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
50 | |||
51 | diff --git a/disas/capstone.c b/disas/capstone.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/disas/capstone.c | ||
54 | +++ b/disas/capstone.c | ||
55 | @@ -XXX,XX +XXX,XX @@ bool cap_disas_monitor(disassemble_info *info, uint64_t pc, int count) | ||
56 | |||
57 | /* Make certain that we can make progress. */ | ||
58 | assert(tsize != 0); | ||
59 | - info->read_memory_func(pc, cap_buf + csize, tsize, info); | ||
60 | + info->read_memory_func(pc + csize, cap_buf + csize, tsize, info); | ||
61 | csize += tsize; | ||
62 | |||
63 | if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) { | ||
64 | -- | ||
65 | 2.20.1 | ||
66 | |||
67 | diff view generated by jsdifflib |