1
The following changes since commit 4a74626970ab4ea475263d155b10fb75c9af0b33:
1
Note that I've extended the expiration date of my gpg key
2
and have uploaded it to keyserver.ubuntu.com.
2
3
3
Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/tracing-pull-request' into staging (2020-10-27 11:28:46 +0000)
4
5
r~
6
7
8
The following changes since commit 99c44988d5ba1866a411450c877ed818b1b70081:
9
10
Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210910' into staging (2021-09-11 14:00:39 +0100)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20201027
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210912
8
15
9
for you to fetch changes up to 1d705e8a5bbfe36294081baa45ab68a9ad987f33:
16
for you to fetch changes up to 267a3ec3e2a8fb3e06a9d46d09fcfc57dfefd118:
10
17
11
accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile() (2020-10-27 09:48:07 -0700)
18
tcg/arm: Fix tcg_out_vec_op function signature (2021-09-12 05:07:36 -0700)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
Optimize across branches.
21
Fix translation race condition for user-only.
15
Add logging for cpu_io_recompile.
22
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
23
Fix tcg/arm tcg_out_vec_op signature.
24
Fix tcg/ppc (32bit) build with clang.
25
Remove dupluate TCG_KICK_PERIOD definition.
26
Remove unused tcg_global_reg_new.
27
Use __builtin_bswap*.
16
28
17
----------------------------------------------------------------
29
----------------------------------------------------------------
18
Peter Maydell (1):
30
Bin Meng (1):
19
accel/tcg: Add CPU_LOG_EXEC tracing for cpu_io_recompile()
31
tcg: Remove tcg_global_reg_new defines
20
32
21
Richard Henderson (2):
33
Ilya Leoshkevich (2):
22
tcg: Do not kill globals at conditional branches
34
accel/tcg: Add DisasContextBase argument to translator_ld*
23
tcg/optimize: Flush data at labels not TCG_OPF_BB_END
35
accel/tcg: Clear PAGE_WRITE before translation
24
36
25
include/tcg/tcg-opc.h | 7 +++---
37
Jose R. Ziviani (1):
26
include/tcg/tcg.h | 4 +++-
38
tcg/arm: Fix tcg_out_vec_op function signature
27
accel/tcg/translate-all.c | 4 ++++
28
tcg/optimize.c | 35 +++++++++++++++---------------
29
tcg/tcg.c | 55 +++++++++++++++++++++++++++++++++++++++++++++--
30
5 files changed, 82 insertions(+), 23 deletions(-)
31
39
40
Luc Michel (1):
41
accel/tcg: remove redundant TCG_KICK_PERIOD define
42
43
Richard Henderson (4):
44
tcg/i386: Split P_VEXW from P_REXW
45
include/qemu: Use builtins for bswap
46
tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
47
tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
48
49
meson.build | 6 ----
50
include/exec/translate-all.h | 1 +
51
include/exec/translator.h | 44 +++++++++++++----------
52
include/qemu/bswap.h | 53 ++-------------------------
53
include/tcg/tcg-op.h | 2 --
54
target/arm/arm_ldst.h | 12 +++----
55
accel/tcg/tcg-accel-ops-rr.c | 2 --
56
accel/tcg/translate-all.c | 59 ++++++++++++++++++-------------
57
accel/tcg/translator.c | 39 ++++++++++++++++++++
58
target/alpha/translate.c | 2 +-
59
target/arm/translate-a64.c | 2 +-
60
target/arm/translate.c | 9 ++---
61
target/hexagon/translate.c | 3 +-
62
target/hppa/translate.c | 5 +--
63
target/i386/tcg/translate.c | 10 +++---
64
target/m68k/translate.c | 2 +-
65
target/mips/tcg/translate.c | 8 ++---
66
target/openrisc/translate.c | 2 +-
67
target/ppc/translate.c | 5 +--
68
target/riscv/translate.c | 5 +--
69
target/s390x/tcg/translate.c | 16 +++++----
70
target/sh4/translate.c | 4 +--
71
target/sparc/translate.c | 2 +-
72
target/xtensa/translate.c | 5 +--
73
target/mips/tcg/micromips_translate.c.inc | 2 +-
74
target/mips/tcg/mips16e_translate.c.inc | 4 +--
75
target/mips/tcg/nanomips_translate.c.inc | 4 +--
76
tcg/arm/tcg-target.c.inc | 3 +-
77
tcg/i386/tcg-target.c.inc | 13 +++----
78
tcg/ppc/tcg-target.c.inc | 25 ++++++++++---
79
30 files changed, 185 insertions(+), 164 deletions(-)
80
diff view generated by jsdifflib
New patch
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
2
3
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
4
[rth: Split out of a larger patch.]
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
include/exec/translator.h | 9 +++++----
8
target/arm/arm_ldst.h | 12 ++++++------
9
target/alpha/translate.c | 2 +-
10
target/arm/translate-a64.c | 2 +-
11
target/arm/translate.c | 9 +++++----
12
target/hexagon/translate.c | 3 ++-
13
target/hppa/translate.c | 2 +-
14
target/i386/tcg/translate.c | 10 +++++-----
15
target/m68k/translate.c | 2 +-
16
target/mips/tcg/translate.c | 8 ++++----
17
target/openrisc/translate.c | 2 +-
18
target/ppc/translate.c | 5 +++--
19
target/riscv/translate.c | 5 +++--
20
target/s390x/tcg/translate.c | 16 +++++++++-------
21
target/sh4/translate.c | 4 ++--
22
target/sparc/translate.c | 2 +-
23
target/xtensa/translate.c | 5 +++--
24
target/mips/tcg/micromips_translate.c.inc | 2 +-
25
target/mips/tcg/mips16e_translate.c.inc | 4 ++--
26
target/mips/tcg/nanomips_translate.c.inc | 4 ++--
27
20 files changed, 58 insertions(+), 50 deletions(-)
28
29
diff --git a/include/exec/translator.h b/include/exec/translator.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/exec/translator.h
32
+++ b/include/exec/translator.h
33
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
34
35
#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
36
static inline type \
37
- fullname ## _swap(CPUArchState *env, abi_ptr pc, bool do_swap) \
38
+ fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
39
+ abi_ptr pc, bool do_swap) \
40
{ \
41
type ret = load_fn(env, pc); \
42
if (do_swap) { \
43
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
44
plugin_insn_append(&ret, sizeof(ret)); \
45
return ret; \
46
} \
47
- \
48
- static inline type fullname(CPUArchState *env, abi_ptr pc) \
49
+ static inline type fullname(CPUArchState *env, \
50
+ DisasContextBase *dcbase, abi_ptr pc) \
51
{ \
52
- return fullname ## _swap(env, pc, false); \
53
+ return fullname ## _swap(env, dcbase, pc, false); \
54
}
55
56
GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
57
diff --git a/target/arm/arm_ldst.h b/target/arm/arm_ldst.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/arm_ldst.h
60
+++ b/target/arm/arm_ldst.h
61
@@ -XXX,XX +XXX,XX @@
62
#include "qemu/bswap.h"
63
64
/* Load an instruction and return it in the standard little-endian order */
65
-static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr,
66
- bool sctlr_b)
67
+static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,
68
+ target_ulong addr, bool sctlr_b)
69
{
70
- return translator_ldl_swap(env, addr, bswap_code(sctlr_b));
71
+ return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));
72
}
73
74
/* Ditto, for a halfword (Thumb) instruction */
75
-static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
76
- bool sctlr_b)
77
+static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,
78
+ target_ulong addr, bool sctlr_b)
79
{
80
#ifndef CONFIG_USER_ONLY
81
/* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped
82
@@ -XXX,XX +XXX,XX @@ static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr,
83
addr ^= 2;
84
}
85
#endif
86
- return translator_lduw_swap(env, addr, bswap_code(sctlr_b));
87
+ return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));
88
}
89
90
#endif
91
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/target/alpha/translate.c
94
+++ b/target/alpha/translate.c
95
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
96
{
97
DisasContext *ctx = container_of(dcbase, DisasContext, base);
98
CPUAlphaState *env = cpu->env_ptr;
99
- uint32_t insn = translator_ldl(env, ctx->base.pc_next);
100
+ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
101
102
ctx->base.pc_next += 4;
103
ctx->base.is_jmp = translate_one(ctx, insn);
104
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/target/arm/translate-a64.c
107
+++ b/target/arm/translate-a64.c
108
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
109
uint32_t insn;
110
111
s->pc_curr = s->base.pc_next;
112
- insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
113
+ insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
114
s->insn = insn;
115
s->base.pc_next += 4;
116
117
diff --git a/target/arm/translate.c b/target/arm/translate.c
118
index XXXXXXX..XXXXXXX 100644
119
--- a/target/arm/translate.c
120
+++ b/target/arm/translate.c
121
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
122
* boundary, so we cross the page if the first 16 bits indicate
123
* that this is a 32 bit insn.
124
*/
125
- uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
126
+ uint16_t insn = arm_lduw_code(env, &s->base, s->base.pc_next, s->sctlr_b);
127
128
return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
129
}
130
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
131
}
132
133
dc->pc_curr = dc->base.pc_next;
134
- insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
135
+ insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
136
dc->insn = insn;
137
dc->base.pc_next += 4;
138
disas_arm_insn(dc, insn);
139
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
140
}
141
142
dc->pc_curr = dc->base.pc_next;
143
- insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
144
+ insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
145
is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
146
dc->base.pc_next += 2;
147
if (!is_16bit) {
148
- uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
149
+ uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
150
+ dc->sctlr_b);
151
152
insn = insn << 16 | insn2;
153
dc->base.pc_next += 2;
154
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
155
index XXXXXXX..XXXXXXX 100644
156
--- a/target/hexagon/translate.c
157
+++ b/target/hexagon/translate.c
158
@@ -XXX,XX +XXX,XX @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
159
memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
160
for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
161
words[nwords] =
162
- translator_ldl(env, ctx->base.pc_next + nwords * sizeof(uint32_t));
163
+ translator_ldl(env, &ctx->base,
164
+ ctx->base.pc_next + nwords * sizeof(uint32_t));
165
found_end = is_packet_end(words[nwords]);
166
}
167
if (!found_end) {
168
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/hppa/translate.c
171
+++ b/target/hppa/translate.c
172
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
173
{
174
/* Always fetch the insn, even if nullified, so that we check
175
the page permissions for execute. */
176
- uint32_t insn = translator_ldl(env, ctx->base.pc_next);
177
+ uint32_t insn = translator_ldl(env, &ctx->base, ctx->base.pc_next);
178
179
/* Set up the IA queue for the next insn.
180
This will be overwritten by a branch. */
181
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
182
index XXXXXXX..XXXXXXX 100644
183
--- a/target/i386/tcg/translate.c
184
+++ b/target/i386/tcg/translate.c
185
@@ -XXX,XX +XXX,XX @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes)
186
187
static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s)
188
{
189
- return translator_ldub(env, advance_pc(env, s, 1));
190
+ return translator_ldub(env, &s->base, advance_pc(env, s, 1));
191
}
192
193
static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s)
194
{
195
- return translator_ldsw(env, advance_pc(env, s, 2));
196
+ return translator_ldsw(env, &s->base, advance_pc(env, s, 2));
197
}
198
199
static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s)
200
{
201
- return translator_lduw(env, advance_pc(env, s, 2));
202
+ return translator_lduw(env, &s->base, advance_pc(env, s, 2));
203
}
204
205
static inline uint32_t x86_ldl_code(CPUX86State *env, DisasContext *s)
206
{
207
- return translator_ldl(env, advance_pc(env, s, 4));
208
+ return translator_ldl(env, &s->base, advance_pc(env, s, 4));
209
}
210
211
#ifdef TARGET_X86_64
212
static inline uint64_t x86_ldq_code(CPUX86State *env, DisasContext *s)
213
{
214
- return translator_ldq(env, advance_pc(env, s, 8));
215
+ return translator_ldq(env, &s->base, advance_pc(env, s, 8));
216
}
217
#endif
218
219
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
220
index XXXXXXX..XXXXXXX 100644
221
--- a/target/m68k/translate.c
222
+++ b/target/m68k/translate.c
223
@@ -XXX,XX +XXX,XX @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
224
static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
225
{
226
uint16_t im;
227
- im = translator_lduw(env, s->pc);
228
+ im = translator_lduw(env, &s->base, s->pc);
229
s->pc += 2;
230
return im;
231
}
232
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/target/mips/tcg/translate.c
235
+++ b/target/mips/tcg/translate.c
236
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
237
238
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
239
if (ctx->insn_flags & ISA_NANOMIPS32) {
240
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
241
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
242
insn_bytes = decode_isa_nanomips(env, ctx);
243
} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
244
- ctx->opcode = translator_ldl(env, ctx->base.pc_next);
245
+ ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
246
insn_bytes = 4;
247
decode_opc(env, ctx);
248
} else if (ctx->insn_flags & ASE_MICROMIPS) {
249
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
250
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
251
insn_bytes = decode_isa_micromips(env, ctx);
252
} else if (ctx->insn_flags & ASE_MIPS16) {
253
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
254
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
255
insn_bytes = decode_ase_mips16e(env, ctx);
256
} else {
257
gen_reserved_instruction(ctx);
258
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
259
index XXXXXXX..XXXXXXX 100644
260
--- a/target/openrisc/translate.c
261
+++ b/target/openrisc/translate.c
262
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
263
{
264
DisasContext *dc = container_of(dcbase, DisasContext, base);
265
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
266
- uint32_t insn = translator_ldl(&cpu->env, dc->base.pc_next);
267
+ uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next);
268
269
if (!decode(dc, insn)) {
270
gen_illegal_exception(dc);
271
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
272
index XXXXXXX..XXXXXXX 100644
273
--- a/target/ppc/translate.c
274
+++ b/target/ppc/translate.c
275
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
276
ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
277
278
ctx->cia = pc = ctx->base.pc_next;
279
- insn = translator_ldl_swap(env, pc, need_byteswap(ctx));
280
+ insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx));
281
ctx->base.pc_next = pc += 4;
282
283
if (!is_prefix_insn(ctx, insn)) {
284
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
285
gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN);
286
ok = true;
287
} else {
288
- uint32_t insn2 = translator_ldl_swap(env, pc, need_byteswap(ctx));
289
+ uint32_t insn2 = translator_ldl_swap(env, dcbase, pc,
290
+ need_byteswap(ctx));
291
ctx->base.pc_next = pc += 4;
292
ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn));
293
}
294
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
295
index XXXXXXX..XXXXXXX 100644
296
--- a/target/riscv/translate.c
297
+++ b/target/riscv/translate.c
298
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
299
} else {
300
uint32_t opcode32 = opcode;
301
opcode32 = deposit32(opcode32, 16, 16,
302
- translator_lduw(env, ctx->base.pc_next + 2));
303
+ translator_lduw(env, &ctx->base,
304
+ ctx->base.pc_next + 2));
305
ctx->pc_succ_insn = ctx->base.pc_next + 4;
306
if (!decode_insn32(ctx, opcode32)) {
307
gen_exception_illegal(ctx);
308
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
309
{
310
DisasContext *ctx = container_of(dcbase, DisasContext, base);
311
CPURISCVState *env = cpu->env_ptr;
312
- uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
313
+ uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
314
315
decode_opc(env, ctx, opcode16);
316
ctx->base.pc_next = ctx->pc_succ_insn;
317
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
318
index XXXXXXX..XXXXXXX 100644
319
--- a/target/s390x/tcg/translate.c
320
+++ b/target/s390x/tcg/translate.c
321
@@ -XXX,XX +XXX,XX @@ static void update_cc_op(DisasContext *s)
322
}
323
}
324
325
-static inline uint64_t ld_code2(CPUS390XState *env, uint64_t pc)
326
+static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s,
327
+ uint64_t pc)
328
{
329
- return (uint64_t)cpu_lduw_code(env, pc);
330
+ return (uint64_t)translator_lduw(env, &s->base, pc);
331
}
332
333
-static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
334
+static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s,
335
+ uint64_t pc)
336
{
337
- return (uint64_t)(uint32_t)cpu_ldl_code(env, pc);
338
+ return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc);
339
}
340
341
static int get_mem_index(DisasContext *s)
342
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
343
ilen = s->ex_value & 0xf;
344
op = insn >> 56;
345
} else {
346
- insn = ld_code2(env, pc);
347
+ insn = ld_code2(env, s, pc);
348
op = (insn >> 8) & 0xff;
349
ilen = get_ilen(op);
350
switch (ilen) {
351
@@ -XXX,XX +XXX,XX @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
352
insn = insn << 48;
353
break;
354
case 4:
355
- insn = ld_code4(env, pc) << 32;
356
+ insn = ld_code4(env, s, pc) << 32;
357
break;
358
case 6:
359
- insn = (insn << 48) | (ld_code4(env, pc + 2) << 16);
360
+ insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16);
361
break;
362
default:
363
g_assert_not_reached();
364
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
365
index XXXXXXX..XXXXXXX 100644
366
--- a/target/sh4/translate.c
367
+++ b/target/sh4/translate.c
368
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
369
370
/* Read all of the insns for the region. */
371
for (i = 0; i < max_insns; ++i) {
372
- insns[i] = translator_lduw(env, pc + i * 2);
373
+ insns[i] = translator_lduw(env, &ctx->base, pc + i * 2);
374
}
375
376
ld_adr = ld_dst = ld_mop = -1;
377
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
378
}
379
#endif
380
381
- ctx->opcode = translator_lduw(env, ctx->base.pc_next);
382
+ ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
383
decode_opc(ctx);
384
ctx->base.pc_next += 2;
385
}
386
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
387
index XXXXXXX..XXXXXXX 100644
388
--- a/target/sparc/translate.c
389
+++ b/target/sparc/translate.c
390
@@ -XXX,XX +XXX,XX @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
391
CPUSPARCState *env = cs->env_ptr;
392
unsigned int insn;
393
394
- insn = translator_ldl(env, dc->pc);
395
+ insn = translator_ldl(env, &dc->base, dc->pc);
396
dc->base.pc_next += 4;
397
disas_sparc_insn(dc, insn);
398
399
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
400
index XXXXXXX..XXXXXXX 100644
401
--- a/target/xtensa/translate.c
402
+++ b/target/xtensa/translate.c
403
@@ -XXX,XX +XXX,XX @@ static int arg_copy_compare(const void *a, const void *b)
404
static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
405
{
406
xtensa_isa isa = dc->config->isa;
407
- unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, dc->pc)};
408
+ unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base,
409
+ dc->pc)};
410
unsigned len = xtensa_op0_insn_len(dc, b[0]);
411
xtensa_format fmt;
412
int slot, slots;
413
@@ -XXX,XX +XXX,XX @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
414
415
dc->base.pc_next = dc->pc + len;
416
for (i = 1; i < len; ++i) {
417
- b[i] = translator_ldub(env, dc->pc + i);
418
+ b[i] = translator_ldub(env, &dc->base, dc->pc + i);
419
}
420
xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
421
fmt = xtensa_format_decode(isa, dc->insnbuf);
422
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
423
index XXXXXXX..XXXXXXX 100644
424
--- a/target/mips/tcg/micromips_translate.c.inc
425
+++ b/target/mips/tcg/micromips_translate.c.inc
426
@@ -XXX,XX +XXX,XX @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
427
uint32_t op, minor, minor2, mips32_op;
428
uint32_t cond, fmt, cc;
429
430
- insn = translator_lduw(env, ctx->base.pc_next + 2);
431
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
432
ctx->opcode = (ctx->opcode << 16) | insn;
433
434
rt = (ctx->opcode >> 21) & 0x1f;
435
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
436
index XXXXXXX..XXXXXXX 100644
437
--- a/target/mips/tcg/mips16e_translate.c.inc
438
+++ b/target/mips/tcg/mips16e_translate.c.inc
439
@@ -XXX,XX +XXX,XX @@ static void decode_i64_mips16(DisasContext *ctx,
440
441
static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
442
{
443
- int extend = translator_lduw(env, ctx->base.pc_next + 2);
444
+ int extend = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
445
int op, rx, ry, funct, sa;
446
int16_t imm, offset;
447
448
@@ -XXX,XX +XXX,XX @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
449
/* No delay slot, so just process as a normal instruction */
450
break;
451
case M16_OPC_JAL:
452
- offset = translator_lduw(env, ctx->base.pc_next + 2);
453
+ offset = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
454
offset = (((ctx->opcode & 0x1f) << 21)
455
| ((ctx->opcode >> 5) & 0x1f) << 16
456
| offset) << 2;
457
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
458
index XXXXXXX..XXXXXXX 100644
459
--- a/target/mips/tcg/nanomips_translate.c.inc
460
+++ b/target/mips/tcg/nanomips_translate.c.inc
461
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
462
int offset;
463
int imm;
464
465
- insn = translator_lduw(env, ctx->base.pc_next + 2);
466
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 2);
467
ctx->opcode = (ctx->opcode << 16) | insn;
468
469
rt = extract32(ctx->opcode, 21, 5);
470
@@ -XXX,XX +XXX,XX @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
471
break;
472
case NM_P48I:
473
{
474
- insn = translator_lduw(env, ctx->base.pc_next + 4);
475
+ insn = translator_lduw(env, &ctx->base, ctx->base.pc_next + 4);
476
target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
477
switch (extract32(ctx->opcode, 16, 5)) {
478
case NM_LI48:
479
--
480
2.25.1
481
482
diff view generated by jsdifflib
1
We can easily register allocate the entire extended basic block
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
(in this case, the set of blocks connected by fallthru), simply
2
3
by not discarding the register state at the branch.
3
translate_insn() implementations fetch instruction bytes piecemeal,
4
4
which can cause qemu-user to generate inconsistent translations if
5
This does not help blocks starting with a label, as they are
5
another thread modifies them concurrently [1].
6
reached via a taken branch, and that would require saving the
6
7
complete register state at the branch.
7
Fix by making pages containing translated instruction non-writable
8
8
right before loading instruction bytes from them.
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
10
[1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html
11
12
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
13
Message-Id: <20210805204835.158918-1-iii@linux.ibm.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
15
---
12
include/tcg/tcg-opc.h | 7 +++---
16
include/exec/translate-all.h | 1 +
13
include/tcg/tcg.h | 4 +++-
17
include/exec/translator.h | 39 ++++++++++++++----------
14
tcg/tcg.c | 55 +++++++++++++++++++++++++++++++++++++++++--
18
accel/tcg/translate-all.c | 59 +++++++++++++++++++++---------------
15
3 files changed, 60 insertions(+), 6 deletions(-)
19
accel/tcg/translator.c | 39 ++++++++++++++++++++++++
16
20
4 files changed, 97 insertions(+), 41 deletions(-)
17
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
21
18
index XXXXXXX..XXXXXXX 100644
22
diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h
19
--- a/include/tcg/tcg-opc.h
23
index XXXXXXX..XXXXXXX 100644
20
+++ b/include/tcg/tcg-opc.h
24
--- a/include/exec/translate-all.h
21
@@ -XXX,XX +XXX,XX @@ DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
25
+++ b/include/exec/translate-all.h
22
DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
26
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end);
23
DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
27
void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
24
28
25
-DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
29
#ifdef CONFIG_USER_ONLY
26
+DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
30
+void page_protect(tb_page_addr_t page_addr);
27
31
int page_unprotect(target_ulong address, uintptr_t pc);
28
DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
32
#endif
29
DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
33
30
@@ -XXX,XX +XXX,XX @@ DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
34
diff --git a/include/exec/translator.h b/include/exec/translator.h
31
DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
35
index XXXXXXX..XXXXXXX 100644
32
DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
36
--- a/include/exec/translator.h
33
DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
37
+++ b/include/exec/translator.h
34
-DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
38
@@ -XXX,XX +XXX,XX @@
35
+DEF(brcond2_i32, 0, 4, 2,
39
#include "exec/exec-all.h"
36
+ TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32))
40
#include "exec/cpu_ldst.h"
37
DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
41
#include "exec/plugin-gen.h"
38
42
+#include "exec/translate-all.h"
39
DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
43
#include "tcg/tcg.h"
40
@@ -XXX,XX +XXX,XX @@ DEF(extrh_i64_i32, 1, 1, 0,
44
41
IMPL(TCG_TARGET_HAS_extrh_i64_i32)
45
42
| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
46
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContextBase {
43
47
int num_insns;
44
-DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
48
int max_insns;
45
+DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64)
49
bool singlestep_enabled;
46
DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
50
+#ifdef CONFIG_USER_ONLY
47
DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
51
+ /*
48
DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
52
+ * Guest address of the last byte of the last protected page.
49
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
53
+ *
50
index XXXXXXX..XXXXXXX 100644
54
+ * Pages containing the translated instructions are made non-writable in
51
--- a/include/tcg/tcg.h
55
+ * order to achieve consistency in case another thread is modifying the
52
+++ b/include/tcg/tcg.h
56
+ * code while translate_insn() fetches the instruction bytes piecemeal.
53
@@ -XXX,XX +XXX,XX @@ typedef struct TCGArgConstraint {
57
+ * Such writer threads are blocked on mmap_lock() in page_unprotect().
54
58
+ */
55
#define TCG_MAX_OP_ARGS 16
59
+ target_ulong page_protect_end;
56
60
+#endif
57
-/* Bits for TCGOpDef->flags, 8 bits available. */
61
} DisasContextBase;
58
+/* Bits for TCGOpDef->flags, 8 bits available, all used. */
62
59
enum {
63
/**
60
/* Instruction exits the translation block. */
64
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
61
TCG_OPF_BB_EXIT = 0x01,
65
*/
62
@@ -XXX,XX +XXX,XX @@ enum {
66
63
TCG_OPF_NOT_PRESENT = 0x20,
67
#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
64
/* Instruction operands are vectors. */
68
- static inline type \
65
TCG_OPF_VECTOR = 0x40,
69
- fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
66
+ /* Instruction is a conditional branch. */
70
- abi_ptr pc, bool do_swap) \
67
+ TCG_OPF_COND_BRANCH = 0x80
71
- { \
68
};
72
- type ret = load_fn(env, pc); \
69
73
- if (do_swap) { \
70
typedef struct TCGOpDef {
74
- ret = swap_fn(ret); \
71
diff --git a/tcg/tcg.c b/tcg/tcg.c
75
- } \
72
index XXXXXXX..XXXXXXX 100644
76
- plugin_insn_append(&ret, sizeof(ret)); \
73
--- a/tcg/tcg.c
77
- return ret; \
74
+++ b/tcg/tcg.c
78
- } \
75
@@ -XXX,XX +XXX,XX @@ static void la_global_sync(TCGContext *s, int ng)
79
+ type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
80
+ abi_ptr pc, bool do_swap); \
81
static inline type fullname(CPUArchState *env, \
82
DisasContextBase *dcbase, abi_ptr pc) \
83
{ \
84
return fullname ## _swap(env, dcbase, pc, false); \
76
}
85
}
86
87
-GEN_TRANSLATOR_LD(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)
88
-GEN_TRANSLATOR_LD(translator_ldsw, int16_t, cpu_ldsw_code, bswap16)
89
-GEN_TRANSLATOR_LD(translator_lduw, uint16_t, cpu_lduw_code, bswap16)
90
-GEN_TRANSLATOR_LD(translator_ldl, uint32_t, cpu_ldl_code, bswap32)
91
-GEN_TRANSLATOR_LD(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
92
+#define FOR_EACH_TRANSLATOR_LD(F) \
93
+ F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \
94
+ F(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) \
95
+ F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \
96
+ F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \
97
+ F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
98
+
99
+FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
100
+
101
#undef GEN_TRANSLATOR_LD
102
103
#endif /* EXEC__TRANSLATOR_H */
104
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
105
index XXXXXXX..XXXXXXX 100644
106
--- a/accel/tcg/translate-all.c
107
+++ b/accel/tcg/translate-all.c
108
@@ -XXX,XX +XXX,XX @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb,
109
invalidate_page_bitmap(p);
110
111
#if defined(CONFIG_USER_ONLY)
112
- if (p->flags & PAGE_WRITE) {
113
- target_ulong addr;
114
- PageDesc *p2;
115
- int prot;
116
-
117
- /* force the host page as non writable (writes will have a
118
- page fault + mprotect overhead) */
119
- page_addr &= qemu_host_page_mask;
120
- prot = 0;
121
- for (addr = page_addr; addr < page_addr + qemu_host_page_size;
122
- addr += TARGET_PAGE_SIZE) {
123
-
124
- p2 = page_find(addr >> TARGET_PAGE_BITS);
125
- if (!p2) {
126
- continue;
127
- }
128
- prot |= p2->flags;
129
- p2->flags &= ~PAGE_WRITE;
130
- }
131
- mprotect(g2h_untagged(page_addr), qemu_host_page_size,
132
- (prot & PAGE_BITS) & ~PAGE_WRITE);
133
- if (DEBUG_TB_INVALIDATE_GATE) {
134
- printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr);
135
- }
136
- }
137
+ /* translator_loop() must have made all TB pages non-writable */
138
+ assert(!(p->flags & PAGE_WRITE));
139
#else
140
/* if some code is already present, then the pages are already
141
protected. So we handle the case where only the first TB is
142
@@ -XXX,XX +XXX,XX @@ int page_check_range(target_ulong start, target_ulong len, int flags)
143
return 0;
77
}
144
}
78
145
79
+/*
146
+void page_protect(tb_page_addr_t page_addr)
80
+ * liveness analysis: conditional branch: all temps are dead,
81
+ * globals and local temps should be synced.
82
+ */
83
+static void la_bb_sync(TCGContext *s, int ng, int nt)
84
+{
147
+{
85
+ la_global_sync(s, ng);
148
+ target_ulong addr;
86
+
149
+ PageDesc *p;
87
+ for (int i = ng; i < nt; ++i) {
150
+ int prot;
88
+ if (s->temps[i].temp_local) {
151
+
89
+ int state = s->temps[i].state;
152
+ p = page_find(page_addr >> TARGET_PAGE_BITS);
90
+ s->temps[i].state = state | TS_MEM;
153
+ if (p && (p->flags & PAGE_WRITE)) {
91
+ if (state != TS_DEAD) {
154
+ /*
155
+ * Force the host page as non writable (writes will have a page fault +
156
+ * mprotect overhead).
157
+ */
158
+ page_addr &= qemu_host_page_mask;
159
+ prot = 0;
160
+ for (addr = page_addr; addr < page_addr + qemu_host_page_size;
161
+ addr += TARGET_PAGE_SIZE) {
162
+
163
+ p = page_find(addr >> TARGET_PAGE_BITS);
164
+ if (!p) {
92
+ continue;
165
+ continue;
93
+ }
166
+ }
94
+ } else {
167
+ prot |= p->flags;
95
+ s->temps[i].state = TS_DEAD;
168
+ p->flags &= ~PAGE_WRITE;
96
+ }
169
+ }
97
+ la_reset_pref(&s->temps[i]);
170
+ mprotect(g2h_untagged(page_addr), qemu_host_page_size,
98
+ }
171
+ (prot & PAGE_BITS) & ~PAGE_WRITE);
99
+}
172
+ if (DEBUG_TB_INVALIDATE_GATE) {
100
+
173
+ printf("protecting code page: 0x" TB_PAGE_ADDR_FMT "\n", page_addr);
101
/* liveness analysis: sync globals back to memory and kill. */
102
static void la_global_kill(TCGContext *s, int ng)
103
{
104
@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
105
/* If end of basic block, update. */
106
if (def->flags & TCG_OPF_BB_EXIT) {
107
la_func_end(s, nb_globals, nb_temps);
108
+ } else if (def->flags & TCG_OPF_COND_BRANCH) {
109
+ la_bb_sync(s, nb_globals, nb_temps);
110
} else if (def->flags & TCG_OPF_BB_END) {
111
la_bb_end(s, nb_globals, nb_temps);
112
} else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
113
@@ -XXX,XX +XXX,XX @@ static bool liveness_pass_2(TCGContext *s)
114
nb_oargs = def->nb_oargs;
115
116
/* Set flags similar to how calls require. */
117
- if (def->flags & TCG_OPF_BB_END) {
118
+ if (def->flags & TCG_OPF_COND_BRANCH) {
119
+ /* Like reading globals: sync_globals */
120
+ call_flags = TCG_CALL_NO_WRITE_GLOBALS;
121
+ } else if (def->flags & TCG_OPF_BB_END) {
122
/* Like writing globals: save_globals */
123
call_flags = 0;
124
} else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
125
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
126
save_globals(s, allocated_regs);
127
}
128
129
+/*
130
+ * At a conditional branch, we assume all temporaries are dead and
131
+ * all globals and local temps are synced to their location.
132
+ */
133
+static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs)
134
+{
135
+ sync_globals(s, allocated_regs);
136
+
137
+ for (int i = s->nb_globals; i < s->nb_temps; i++) {
138
+ TCGTemp *ts = &s->temps[i];
139
+ /*
140
+ * The liveness analysis already ensures that temps are dead.
141
+ * Keep tcg_debug_asserts for safety.
142
+ */
143
+ if (ts->temp_local) {
144
+ tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent);
145
+ } else {
146
+ tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD);
147
+ }
174
+ }
148
+ }
175
+ }
149
+}
176
+}
150
+
177
+
151
/*
178
/* called from signal handler: invalidate the code and unprotect the
152
* Specialized code generation for INDEX_op_movi_*.
179
* page. Return 0 if the fault was not handled, 1 if it was handled,
153
*/
180
* and 2 if it was handled but the caller must cause the TB to be
154
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
181
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
155
}
182
index XXXXXXX..XXXXXXX 100644
183
--- a/accel/tcg/translator.c
184
+++ b/accel/tcg/translator.c
185
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
186
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
187
}
188
189
+static inline void translator_page_protect(DisasContextBase *dcbase,
190
+ target_ulong pc)
191
+{
192
+#ifdef CONFIG_USER_ONLY
193
+ dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK;
194
+ page_protect(pc);
195
+#endif
196
+}
197
+
198
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
199
CPUState *cpu, TranslationBlock *tb, int max_insns)
200
{
201
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
202
db->num_insns = 0;
203
db->max_insns = max_insns;
204
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
205
+ translator_page_protect(db, db->pc_next);
206
207
ops->init_disas_context(db, cpu);
208
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
209
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
156
}
210
}
157
211
#endif
158
- if (def->flags & TCG_OPF_BB_END) {
212
}
159
+ if (def->flags & TCG_OPF_COND_BRANCH) {
213
+
160
+ tcg_reg_alloc_cbranch(s, i_allocated_regs);
214
+static inline void translator_maybe_page_protect(DisasContextBase *dcbase,
161
+ } else if (def->flags & TCG_OPF_BB_END) {
215
+ target_ulong pc, size_t len)
162
tcg_reg_alloc_bb_end(s, i_allocated_regs);
216
+{
163
} else {
217
+#ifdef CONFIG_USER_ONLY
164
if (def->flags & TCG_OPF_CALL_CLOBBER) {
218
+ target_ulong end = pc + len - 1;
219
+
220
+ if (end > dcbase->page_protect_end) {
221
+ translator_page_protect(dcbase, end);
222
+ }
223
+#endif
224
+}
225
+
226
+#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
227
+ type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
228
+ abi_ptr pc, bool do_swap) \
229
+ { \
230
+ translator_maybe_page_protect(dcbase, pc, sizeof(type)); \
231
+ type ret = load_fn(env, pc); \
232
+ if (do_swap) { \
233
+ ret = swap_fn(ret); \
234
+ } \
235
+ plugin_insn_append(&ret, sizeof(ret)); \
236
+ return ret; \
237
+ }
238
+
239
+FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
240
+
241
+#undef GEN_TRANSLATOR_LD
165
--
242
--
166
2.25.1
243
2.25.1
167
244
168
245
diff view generated by jsdifflib
1
From: Peter Maydell <peter.maydell@linaro.org>
1
We need to be able to represent VEX.W on a 32-bit host, where REX.W
2
will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ.
2
3
3
When using -icount, it's useful for the CPU_LOG_EXEC logging
4
Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes")
4
to include information about when cpu_io_recompile() was
5
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
5
called, because it alerts the reader of the log that the
6
tracing of a previous TB execution may not actually
7
correspond to an actually executed instruction. For instance
8
if you're using -icount and also -singlestep then a guest
9
instruction that makes an IO access appears in two
10
"Trace" lines, once in a TB that triggers the cpu_io_recompile()
11
and then again in the TB that actually executes.
12
13
(This is a similar reason to why the "Stopped execution of
14
TB chain before..." logging in cpu_tb_exec() is helpful
15
when trying to track execution flow in the logs.)
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Message-Id: <20201013122658.4620-1-peter.maydell@linaro.org>
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
---
7
---
21
accel/tcg/translate-all.c | 4 ++++
8
tcg/i386/tcg-target.c.inc | 13 +++++++------
22
1 file changed, 4 insertions(+)
9
1 file changed, 7 insertions(+), 6 deletions(-)
23
10
24
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
11
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
25
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
26
--- a/accel/tcg/translate-all.c
13
--- a/tcg/i386/tcg-target.c.inc
27
+++ b/accel/tcg/translate-all.c
14
+++ b/tcg/i386/tcg-target.c.inc
28
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
15
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
29
tb_destroy(tb);
16
#define P_EXT        0x100        /* 0x0f opcode prefix */
17
#define P_EXT38 0x200 /* 0x0f 0x38 opcode prefix */
18
#define P_DATA16 0x400 /* 0x66 opcode prefix */
19
+#define P_VEXW 0x1000 /* Set VEX.W = 1 */
20
#if TCG_TARGET_REG_BITS == 64
21
-# define P_REXW 0x1000 /* Set REX.W = 1 */
22
+# define P_REXW P_VEXW /* Set REX.W = 1; match VEXW */
23
# define P_REXB_R 0x2000 /* REG field as byte register */
24
# define P_REXB_RM 0x4000 /* R/M field as byte register */
25
# define P_GS 0x8000 /* gs segment override */
26
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
27
#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
28
#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
29
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
30
-#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW)
31
+#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
32
#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
33
#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
34
-#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_REXW)
35
+#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
36
#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16)
37
#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
38
-#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_REXW)
39
+#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
40
#define OPC_VZEROUPPER (0x77 | P_EXT)
41
#define OPC_XCHG_ax_r32    (0x90)
42
43
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
44
45
/* Use the two byte form if possible, which cannot encode
46
VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */
47
- if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT
48
+ if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_VEXW)) == P_EXT
49
&& ((rm | index) & 8) == 0) {
50
/* Two byte VEX prefix. */
51
tcg_out8(s, 0xc5);
52
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
53
tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
54
tcg_out8(s, tmp);
55
56
- tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
57
+ tmp = (opc & P_VEXW ? 0x80 : 0); /* VEX.W */
30
}
58
}
31
59
32
+ qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
60
tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */
33
+ "cpu_io_recompile: rewound execution of TB to "
34
+ TARGET_FMT_lx "\n", tb->pc);
35
+
36
/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
37
* the first in the TB) then we end up generating a whole new TB and
38
* repeating the fault, which is horribly inefficient.
39
--
61
--
40
2.25.1
62
2.25.1
41
63
42
64
diff view generated by jsdifflib
New patch
1
From: Luc Michel <lmichel@kalray.eu>
1
2
3
The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h.
4
Remove it from tcg-accel-ops-rr.c.
5
6
Signed-off-by: Luc Michel <lmichel@kalray.eu>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20210811141229.12470-1-lmichel@kalray.eu>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
accel/tcg/tcg-accel-ops-rr.c | 2 --
13
1 file changed, 2 deletions(-)
14
15
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/accel/tcg/tcg-accel-ops-rr.c
18
+++ b/accel/tcg/tcg-accel-ops-rr.c
19
@@ -XXX,XX +XXX,XX @@ void rr_kick_vcpu_thread(CPUState *unused)
20
static QEMUTimer *rr_kick_vcpu_timer;
21
static CPUState *rr_current_cpu;
22
23
-#define TCG_KICK_PERIOD (NANOSECONDS_PER_SECOND / 10)
24
-
25
static inline int64_t rr_next_kick_time(void)
26
{
27
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + TCG_KICK_PERIOD;
28
--
29
2.25.1
30
31
diff view generated by jsdifflib
New patch
1
From: Bin Meng <bmeng.cn@gmail.com>
1
2
3
Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"),
4
these tcg_global_reg_new_ macros are not used anywhere.
5
6
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
include/tcg/tcg-op.h | 2 --
12
target/hppa/translate.c | 3 ---
13
2 files changed, 5 deletions(-)
14
15
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/tcg/tcg-op.h
18
+++ b/include/tcg/tcg-op.h
19
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_plugin_cb_end(void)
20
21
#if TARGET_LONG_BITS == 32
22
#define tcg_temp_new() tcg_temp_new_i32()
23
-#define tcg_global_reg_new tcg_global_reg_new_i32
24
#define tcg_global_mem_new tcg_global_mem_new_i32
25
#define tcg_temp_local_new() tcg_temp_local_new_i32()
26
#define tcg_temp_free tcg_temp_free_i32
27
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_plugin_cb_end(void)
28
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
29
#else
30
#define tcg_temp_new() tcg_temp_new_i64()
31
-#define tcg_global_reg_new tcg_global_reg_new_i64
32
#define tcg_global_mem_new tcg_global_mem_new_i64
33
#define tcg_temp_local_new() tcg_temp_local_new_i64()
34
#define tcg_temp_free tcg_temp_free_i64
35
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/hppa/translate.c
38
+++ b/target/hppa/translate.c
39
@@ -XXX,XX +XXX,XX @@
40
41
#undef TCGv
42
#undef tcg_temp_new
43
-#undef tcg_global_reg_new
44
#undef tcg_global_mem_new
45
#undef tcg_temp_local_new
46
#undef tcg_temp_free
47
@@ -XXX,XX +XXX,XX @@
48
#define TCGv_reg TCGv_i64
49
50
#define tcg_temp_new tcg_temp_new_i64
51
-#define tcg_global_reg_new tcg_global_reg_new_i64
52
#define tcg_global_mem_new tcg_global_mem_new_i64
53
#define tcg_temp_local_new tcg_temp_local_new_i64
54
#define tcg_temp_free tcg_temp_free_i64
55
@@ -XXX,XX +XXX,XX @@
56
#else
57
#define TCGv_reg TCGv_i32
58
#define tcg_temp_new tcg_temp_new_i32
59
-#define tcg_global_reg_new tcg_global_reg_new_i32
60
#define tcg_global_mem_new tcg_global_mem_new_i32
61
#define tcg_temp_local_new tcg_temp_local_new_i32
62
#define tcg_temp_free tcg_temp_free_i32
63
--
64
2.25.1
65
66
diff view generated by jsdifflib
New patch
1
All supported compilers have builtins for this.
2
Drop all of the complicated system detection stuff.
1
3
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Message-Id: <20210708181743.750220-1-richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
meson.build | 6 -----
9
include/qemu/bswap.h | 53 +++-----------------------------------------
10
2 files changed, 3 insertions(+), 56 deletions(-)
11
12
diff --git a/meson.build b/meson.build
13
index XXXXXXX..XXXXXXX 100644
14
--- a/meson.build
15
+++ b/meson.build
16
@@ -XXX,XX +XXX,XX @@ config_host_data.set('HAVE_STRCHRNUL', cc.has_function('strchrnul'))
17
config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', prefix: '#include <stdlib.h>'))
18
19
# has_header_symbol
20
-config_host_data.set('CONFIG_BYTESWAP_H',
21
- cc.has_header_symbol('byteswap.h', 'bswap_32'))
22
config_host_data.set('CONFIG_EPOLL_CREATE1',
23
cc.has_header_symbol('sys/epoll.h', 'epoll_create1'))
24
config_host_data.set('CONFIG_HAS_ENVIRON',
25
@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_INOTIFY',
26
cc.has_header_symbol('sys/inotify.h', 'inotify_init'))
27
config_host_data.set('CONFIG_INOTIFY1',
28
cc.has_header_symbol('sys/inotify.h', 'inotify_init1'))
29
-config_host_data.set('CONFIG_MACHINE_BSWAP_H',
30
- cc.has_header_symbol('machine/bswap.h', 'bswap32',
31
- prefix: '''#include <sys/endian.h>
32
- #include <sys/types.h>'''))
33
config_host_data.set('CONFIG_PRCTL_PR_SET_TIMERSLACK',
34
cc.has_header_symbol('sys/prctl.h', 'PR_SET_TIMERSLACK'))
35
config_host_data.set('CONFIG_RTNETLINK',
36
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/qemu/bswap.h
39
+++ b/include/qemu/bswap.h
40
@@ -XXX,XX +XXX,XX @@
41
#ifndef BSWAP_H
42
#define BSWAP_H
43
44
-#ifdef CONFIG_MACHINE_BSWAP_H
45
-# include <sys/endian.h>
46
-# include <machine/bswap.h>
47
-#elif defined(__FreeBSD__)
48
-# include <sys/endian.h>
49
-#elif defined(__HAIKU__)
50
-# include <endian.h>
51
-#elif defined(CONFIG_BYTESWAP_H)
52
-# include <byteswap.h>
53
-#define BSWAP_FROM_BYTESWAP
54
-# else
55
-#define BSWAP_FROM_FALLBACKS
56
-#endif /* ! CONFIG_MACHINE_BSWAP_H */
57
-
58
#ifdef __cplusplus
59
extern "C" {
60
#endif
61
62
#include "fpu/softfloat-types.h"
63
64
-#ifdef BSWAP_FROM_BYTESWAP
65
static inline uint16_t bswap16(uint16_t x)
66
{
67
- return bswap_16(x);
68
+ return __builtin_bswap16(x);
69
}
70
71
static inline uint32_t bswap32(uint32_t x)
72
{
73
- return bswap_32(x);
74
+ return __builtin_bswap32(x);
75
}
76
77
static inline uint64_t bswap64(uint64_t x)
78
{
79
- return bswap_64(x);
80
+ return __builtin_bswap64(x);
81
}
82
-#endif
83
-
84
-#ifdef BSWAP_FROM_FALLBACKS
85
-static inline uint16_t bswap16(uint16_t x)
86
-{
87
- return (((x & 0x00ff) << 8) |
88
- ((x & 0xff00) >> 8));
89
-}
90
-
91
-static inline uint32_t bswap32(uint32_t x)
92
-{
93
- return (((x & 0x000000ffU) << 24) |
94
- ((x & 0x0000ff00U) << 8) |
95
- ((x & 0x00ff0000U) >> 8) |
96
- ((x & 0xff000000U) >> 24));
97
-}
98
-
99
-static inline uint64_t bswap64(uint64_t x)
100
-{
101
- return (((x & 0x00000000000000ffULL) << 56) |
102
- ((x & 0x000000000000ff00ULL) << 40) |
103
- ((x & 0x0000000000ff0000ULL) << 24) |
104
- ((x & 0x00000000ff000000ULL) << 8) |
105
- ((x & 0x000000ff00000000ULL) >> 8) |
106
- ((x & 0x0000ff0000000000ULL) >> 24) |
107
- ((x & 0x00ff000000000000ULL) >> 40) |
108
- ((x & 0xff00000000000000ULL) >> 56));
109
-}
110
-#endif
111
-
112
-#undef BSWAP_FROM_BYTESWAP
113
-#undef BSWAP_FROM_FALLBACKS
114
115
static inline void bswap16s(uint16_t *s)
116
{
117
--
118
2.25.1
119
120
diff view generated by jsdifflib
New patch
1
If __APPLE__, ensure that _CALL_DARWIN is set, then remove
2
our local TCG_TARGET_CALL_DARWIN.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/ppc/tcg-target.c.inc | 8 ++++----
7
1 file changed, 4 insertions(+), 4 deletions(-)
8
9
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/ppc/tcg-target.c.inc
12
+++ b/tcg/ppc/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@
14
#include "elf.h"
15
#include "../tcg-pool.c.inc"
16
17
-#if defined _CALL_DARWIN || defined __APPLE__
18
-#define TCG_TARGET_CALL_DARWIN
19
+#if !defined _CALL_DARWIN && defined __APPLE__
20
+#define _CALL_DARWIN 1
21
#endif
22
#ifdef _CALL_SYSV
23
# define TCG_TARGET_CALL_ALIGN_ARGS 1
24
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[] = {
25
};
26
27
static const int tcg_target_callee_save_regs[] = {
28
-#ifdef TCG_TARGET_CALL_DARWIN
29
+#ifdef _CALL_DARWIN
30
TCG_REG_R11,
31
#endif
32
TCG_REG_R14,
33
@@ -XXX,XX +XXX,XX @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
34
# define LINK_AREA_SIZE (6 * SZR)
35
# define LR_OFFSET (1 * SZR)
36
# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
37
-#elif defined(TCG_TARGET_CALL_DARWIN)
38
+#elif defined(_CALL_DARWIN)
39
# define LINK_AREA_SIZE (6 * SZR)
40
# define LR_OFFSET (2 * SZR)
41
#elif TCG_TARGET_REG_BITS == 64
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
New patch
1
Clang only sets _CALL_ELF for ppc64, and nothing at all to specify
2
the ABI for ppc32. Make a good guess based on other symbols.
1
3
4
Reported-by: Brad Smith <brad@comstyle.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/ppc/tcg-target.c.inc | 21 ++++++++++++++++++---
8
1 file changed, 18 insertions(+), 3 deletions(-)
9
10
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/ppc/tcg-target.c.inc
13
+++ b/tcg/ppc/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@
15
#include "elf.h"
16
#include "../tcg-pool.c.inc"
17
18
-#if !defined _CALL_DARWIN && defined __APPLE__
19
-#define _CALL_DARWIN 1
20
-#endif
21
+/*
22
+ * Standardize on the _CALL_FOO symbols used by GCC:
23
+ * Apple XCode does not define _CALL_DARWIN.
24
+ * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit).
25
+ */
26
+#if !defined(_CALL_SYSV) && \
27
+ !defined(_CALL_DARWIN) && \
28
+ !defined(_CALL_AIX) && \
29
+ !defined(_CALL_ELF)
30
+# if defined(__APPLE__)
31
+# define _CALL_DARWIN
32
+# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32
33
+# define _CALL_SYSV
34
+# else
35
+# error "Unknown ABI"
36
+# endif
37
+#endif
38
+
39
#ifdef _CALL_SYSV
40
# define TCG_TARGET_CALL_ALIGN_ARGS 1
41
#endif
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
1
We can easily propagate temp values through the entire extended
1
From: "Jose R. Ziviani" <jziviani@suse.de>
2
basic block (in this case, the set of blocks connected by fallthru),
3
simply by not discarding the register state at the branch.
4
2
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op
4
for arm is missing. It causes a build error on armv6 and armv7:
5
6
tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *'
7
{aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=]
8
const TCGArg *args, const int *const_args)
9
~~~~~~~~~~~~~~^~~~
10
../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]'
11
{aka 'const unsigned int[16]'}
12
const TCGArg args[TCG_MAX_OP_ARGS],
13
~~~~~~~~~~~~~~^~~~
14
15
Signed-off-by: Jose R. Ziviani <jziviani@suse.de>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-Id: <20210908185338.7927-1-jziviani@suse.de>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
19
---
8
tcg/optimize.c | 35 ++++++++++++++++++-----------------
20
tcg/arm/tcg-target.c.inc | 3 ++-
9
1 file changed, 18 insertions(+), 17 deletions(-)
21
1 file changed, 2 insertions(+), 1 deletion(-)
10
22
11
diff --git a/tcg/optimize.c b/tcg/optimize.c
23
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
12
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/optimize.c
25
--- a/tcg/arm/tcg-target.c.inc
14
+++ b/tcg/optimize.c
26
+++ b/tcg/arm/tcg-target.c.inc
15
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
27
@@ -XXX,XX +XXX,XX @@ static const ARMInsn vec_cmp0_insn[16] = {
16
}
28
17
}
29
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
18
}
30
unsigned vecl, unsigned vece,
19
- goto do_reset_output;
31
- const TCGArg *args, const int *const_args)
20
+ /* fall through */
32
+ const TCGArg args[TCG_MAX_OP_ARGS],
21
33
+ const int const_args[TCG_MAX_OP_ARGS])
22
default:
34
{
23
do_default:
35
TCGType type = vecl + TCG_TYPE_V64;
24
- /* Default case: we know nothing about operation (or were unable
36
unsigned q = vecl;
25
- to compute the operation result) so no propagation is done.
26
- We trash everything if the operation is the end of a basic
27
- block, otherwise we only trash the output args. "mask" is
28
- the non-zero bits mask for the first output arg. */
29
- if (def->flags & TCG_OPF_BB_END) {
30
- bitmap_zero(temps_used.l, nb_temps);
31
- } else {
32
- do_reset_output:
33
- for (i = 0; i < nb_oargs; i++) {
34
- reset_temp(op->args[i]);
35
- /* Save the corresponding known-zero bits mask for the
36
- first output argument (only one supported so far). */
37
- if (i == 0) {
38
- arg_info(op->args[i])->mask = mask;
39
- }
40
+ /*
41
+ * Default case: we know nothing about operation (or were unable
42
+ * to compute the operation result) so no propagation is done.
43
+ */
44
+ for (i = 0; i < nb_oargs; i++) {
45
+ reset_temp(op->args[i]);
46
+ /*
47
+ * Save the corresponding known-zero bits mask for the
48
+ * first output argument (only one supported so far).
49
+ */
50
+ if (i == 0) {
51
+ arg_info(op->args[i])->mask = mask;
52
}
53
}
54
break;
55
+
56
+ case INDEX_op_set_label:
57
+ /* Trash everything at the start of a new extended bb. */
58
+ bitmap_zero(temps_used.l, nb_temps);
59
+ break;
60
}
61
62
/* Eliminate duplicate and redundant fence instructions. */
63
--
37
--
64
2.25.1
38
2.25.1
65
39
66
40
diff view generated by jsdifflib