[v6] RISC-V Pointer Masking implementation

[PATCH v6 0/6] RISC-V Pointer Masking implementation

Alexey Baturo posted 6 patches 3 years, 6 months ago

Diff against v1 v2 v3 v4 v5 v7 v8 v8 v8 v9 v10 v11 v14 v15 v16 v17
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git fetch https://github.com/patchew-project/qemu tags/patchew/20201022080440.10069-1-space.monkey.delivers@gmail.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>

There is a newer version of this series

target/riscv/cpu.c                      |  30 +++
target/riscv/cpu.h                      |  33 +++
target/riscv/cpu_bits.h                 |  66 ++++++
target/riscv/csr.c                      | 271 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc |   3 +
target/riscv/insn_trans/trans_rvd.c.inc |   2 +
target/riscv/insn_trans/trans_rvf.c.inc |   2 +
target/riscv/insn_trans/trans_rvi.c.inc |   2 +
target/riscv/translate.c                |  44 ++++
9 files changed, 453 insertions(+)

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[PATCH v6 0/6] RISC-V Pointer Masking implementation

Posted by Alexey Baturo 3 years, 6 months ago

Hi,

Added missing sign-off on the first patch.

Thanks

Alexey Baturo (5):
  [RISCV_PM] Add J-extension into RISC-V
  [RISCV_PM] Support CSRs required for RISC-V PM extension except for
    ones in hypervisor mode
  [RISCV_PM] Print new PM CSRs in QEMU logs
  [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
    instructions
  [RISCV_PM] Allow experimental J-ext to be turned on

Anatoly Parshintsev (1):
  [RISCV_PM] Implement address masking functions required for RISC-V
    Pointer Masking extension

 target/riscv/cpu.c                      |  30 +++
 target/riscv/cpu.h                      |  33 +++
 target/riscv/cpu_bits.h                 |  66 ++++++
 target/riscv/csr.c                      | 271 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rva.c.inc |   3 +
 target/riscv/insn_trans/trans_rvd.c.inc |   2 +
 target/riscv/insn_trans/trans_rvf.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc |   2 +
 target/riscv/translate.c                |  44 ++++
 9 files changed, 453 insertions(+)

-- 
2.20.1

Re: [PATCH v6 0/6] RISC-V Pointer Masking implementation

Posted by Alistair Francis 3 years, 6 months ago

On Thu, Oct 22, 2020 at 1:04 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> Hi,
>
> Added missing sign-off on the first patch.
>
> Thanks
>
> Alexey Baturo (5):
>   [RISCV_PM] Add J-extension into RISC-V
>   [RISCV_PM] Support CSRs required for RISC-V PM extension except for
>     ones in hypervisor mode
>   [RISCV_PM] Print new PM CSRs in QEMU logs
>   [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
>     instructions
>   [RISCV_PM] Allow experimental J-ext to be turned on
>
> Anatoly Parshintsev (1):
>   [RISCV_PM] Implement address masking functions required for RISC-V
>     Pointer Masking extension

Thanks for the patches!

I don't know a lot about the J-extension, so it will take me some time
to read into it before I can review this.

Maybe you can convince Richard to review it for you :P

Alistair

>
>  target/riscv/cpu.c                      |  30 +++
>  target/riscv/cpu.h                      |  33 +++
>  target/riscv/cpu_bits.h                 |  66 ++++++
>  target/riscv/csr.c                      | 271 ++++++++++++++++++++++++
>  target/riscv/insn_trans/trans_rva.c.inc |   3 +
>  target/riscv/insn_trans/trans_rvd.c.inc |   2 +
>  target/riscv/insn_trans/trans_rvf.c.inc |   2 +
>  target/riscv/insn_trans/trans_rvi.c.inc |   2 +
>  target/riscv/translate.c                |  44 ++++
>  9 files changed, 453 insertions(+)
>
> --
> 2.20.1
>
>

Re: [PATCH v6 0/6] RISC-V Pointer Masking implementation

Posted by Richard Henderson 3 years, 6 months ago

On 10/23/20 5:25 PM, Alistair Francis wrote:
> On Thu, Oct 22, 2020 at 1:04 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>>
>> Hi,
>>
>> Added missing sign-off on the first patch.
>>
>> Thanks
>>
>> Alexey Baturo (5):
>>   [RISCV_PM] Add J-extension into RISC-V
>>   [RISCV_PM] Support CSRs required for RISC-V PM extension except for
>>     ones in hypervisor mode
>>   [RISCV_PM] Print new PM CSRs in QEMU logs
>>   [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
>>     instructions
>>   [RISCV_PM] Allow experimental J-ext to be turned on
>>
>> Anatoly Parshintsev (1):
>>   [RISCV_PM] Implement address masking functions required for RISC-V
>>     Pointer Masking extension
> 
> Thanks for the patches!
> 
> I don't know a lot about the J-extension, so it will take me some time
> to read into it before I can review this.
> 
> Maybe you can convince Richard to review it for you :P

Richard did review v3.  Alexey seems to have misplaced or not added the r-b
tags.  Although I missed that it misses the mask for the special hypervisor
load/store insns?


r~