Series comparison

 [PULL v2 00/29] target-arm queue
-v2: dropped linux-user bti series.
+v2: drop pvpanic-pci patches.
-The following changes since commit 4c41341af76cfc85b5a6c0f87de4838672ab9f89:
+The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
-  Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging (2020-10-20 11:20:36 +0100)
+  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201020-1
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
-for you to fetch changes up to 8128c8e8cc9489a8387c74075974f86dc0222e7f:
+for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
-  target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension (2020-10-20 16:12:01 +0100)
+  docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * Fix AArch32 SMLAD incorrect setting of Q bit
+ * Implement IMPDEF pauth algorithm
- * AArch32 VCVT fixed-point to float is always round-to-nearest
+ * Support ARMv8.4-SEL2
- * strongarm: Fix 'time to transmit a char' unit comment
+ * Fix bug where we were truncating predicate vector lengths in SVE insns
- * Restrict APEI tables generation to the 'virt' machine
+ * npcm7xx_adc-test: Fix memleak in adc_qom_set
- * bcm2835: minor code cleanups
+ * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
- * bcm2835: connect all IRQs from SYS_timer device
+ * docs: Build and install all the docs in a single manual
  * correctly flush TLBs when TBI is enabled
  * tests/qtest: Add npcm7xx timer test
  * loads-stores.rst: add footnote that clarifies GETPC usage
  * Fix reported EL for mte_check_fail
  * Ignore HCR_EL2.ATA when {E2H,TGE} != 11
  * microbit_i2c: Fix coredump when dump-vmstate
  * nseries: Fix loading kernel image on n8x0 machines
  * Implement v8.1M low-overhead-loops
 ----------------------------------------------------------------
-Emanuele Giuseppe Esposito (1):
+Gan Qixin (1):
-      loads-stores.rst: add footnote that clarifies GETPC usage
+      npcm7xx_adc-test: Fix memleak in adc_qom_set
-Havard Skinnemoen (1):
+Peter Maydell (1):
-      tests/qtest: Add npcm7xx timer test
+      docs: Build and install all the docs in a single manual
-Peng Liang (1):
+Philippe Mathieu-Daudé (1):
-      microbit_i2c: Fix coredump when dump-vmstate
+      target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
-Peter Maydell (12):
+Richard Henderson (7):
-      target/arm: Fix SMLAD incorrect setting of Q bit
+      target/arm: Implement an IMPDEF pauth algorithm
-      target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
+      target/arm: Add cpu properties to control pauth
-      decodetree: Fix codegen for non-overlapping group inside overlapping group
+      target/arm: Use object_property_add_bool for "sve" property
-      target/arm: Implement v8.1M NOCP handling
+      target/arm: Introduce PREDDESC field definitions
-      target/arm: Implement v8.1M conditional-select insns
+      target/arm: Update PFIRST, PNEXT for pred_desc
-      target/arm: Make the t32 insn[25:23]=111 group non-overlapping
+      target/arm: Update ZIP, UZP, TRN for pred_desc
-      target/arm: Don't allow BLX imm for M-profile
+      target/arm: Update REV, PUNPK for pred_desc
       target/arm: Implement v8.1M branch-future insns (as NOPs)
       target/arm: Implement v8.1M low-overhead-loop instructions
       target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
       target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
       target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
-Philippe Mathieu-Daudé (9):
+Rémi Denis-Courmont (19):
-      hw/arm/strongarm: Fix 'time to transmit a char' unit comment
+      target/arm: remove redundant tests
-      hw/arm: Restrict APEI tables generation to the 'virt' machine
+      target/arm: add arm_is_el2_enabled() helper
-      hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
+      target/arm: use arm_is_el2_enabled() where applicable
-      hw/timer/bcm2835: Rename variable holding CTRL_STATUS register
+      target/arm: use arm_hcr_el2_eff() where applicable
-      hw/timer/bcm2835: Support the timer COMPARE registers
+      target/arm: factor MDCR_EL2 common handling
-      hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
+      target/arm: Define isar_feature function to test for presence of SEL2
-      hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
+      target/arm: add 64-bit S-EL2 to EL exception table
-      hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
+      target/arm: add MMU stage 1 for Secure EL2
-      hw/arm/nseries: Fix loading kernel image on n8x0 machines
+      target/arm: add ARMv8.4-SEL2 system registers
       target/arm: handle VMID change in secure state
       target/arm: do S1_ptw_translate() before address space lookup
       target/arm: translate NS bit in page-walks
       target/arm: generalize 2-stage page-walk condition
       target/arm: secure stage 2 translation regime
       target/arm: set HPFAR_EL2.NS on secure stage 2 faults
       target/arm: revector to run-time pick target EL
       target/arm: Implement SCR_EL2.EEL2
       target/arm: enable Secure EL2 in max CPU
       target/arm: refactor vae1_tlbmask()
-Richard Henderson (5):
+ docs/conf.py                     |  46 ++++-
-      accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
+ docs/devel/conf.py               |  15 --
-      target/arm: Use tlb_flush_page_bits_by_mmuidx*
+ docs/index.html.in               |  17 --
-      target/arm: Remove redundant mmu_idx lookup
+ docs/interop/conf.py             |  28 ---
-      target/arm: Fix reported EL for mte_check_fail
+ docs/meson.build                 |  64 +++---
-      target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
+ docs/specs/conf.py               |  16 --
  docs/system/arm/cpu-features.rst |  21 ++
  docs/system/conf.py              |  28 ---
  docs/tools/conf.py               |  37 ----
  docs/user/conf.py                |  15 --
  include/qemu/xxhash.h            |  98 +++++++++
  target/arm/cpu-param.h           |   2 +-
  target/arm/cpu.h                 | 107 ++++++++--
  target/arm/internals.h           |  45 +++++
  target/arm/cpu.c                 |  23 ++-
  target/arm/cpu64.c               |  65 ++++--
  target/arm/helper-a64.c          |   8 +-
  target/arm/helper.c              | 414 ++++++++++++++++++++++++++-------------
  target/arm/m_helper.c            |   2 +-
  target/arm/monitor.c             |   1 +
  target/arm/op_helper.c           |   4 +-
  target/arm/pauth_helper.c        |  27 ++-
  target/arm/sve_helper.c          |  33 ++--
  target/arm/tlb_helper.c          |   3 +
  target/arm/translate-a64.c       |   4 +
  target/arm/translate-sve.c       |  31 ++-
  target/arm/translate.c           |  36 +++-
  tests/qtest/arm-cpu-features.c   |  13 ++
  tests/qtest/npcm7xx_adc-test.c   |   1 +
  .gitlab-ci.yml                   |   4 +-
 files changed, 770 insertions(+), 438 deletions(-)
  delete mode 100644 docs/devel/conf.py
  delete mode 100644 docs/index.html.in
  delete mode 100644 docs/interop/conf.py
  delete mode 100644 docs/specs/conf.py
  delete mode 100644 docs/system/conf.py
  delete mode 100644 docs/tools/conf.py
  delete mode 100644 docs/user/conf.py
- docs/devel/loads-stores.rst             |   8 +-
- default-configs/devices/arm-softmmu.mak |   1 -
- include/exec/exec-all.h                 |  36 ++
- include/hw/timer/bcm2835_systmr.h       |  17 +-
- target/arm/cpu.h                        |   8 +
- target/arm/helper.h                     |  13 +
- target/arm/internals.h                  |   9 +-
- target/arm/m-nocp.decode                |  10 +-
- target/arm/t32.decode                   |  50 ++-
- accel/tcg/cputlb.c                      | 275 +++++++++++++++-
- hw/arm/bcm2835_peripherals.c            |  13 +-
- hw/arm/nseries.c                        |   1 +
- hw/arm/strongarm.c                      |   2 +-
- hw/i2c/microbit_i2c.c                   |   1 +
- hw/intc/bcm2835_ic.c                    |   4 +-
- hw/intc/bcm2836_control.c               |   8 +-
- hw/timer/bcm2835_systmr.c               |  57 ++--
- target/arm/cpu.c                        |  38 ++-
- target/arm/helper.c                     |  55 +++-
- target/arm/mte_helper.c                 |  13 +-
- target/arm/translate.c                  | 239 +++++++++++++-
- target/arm/vfp_helper.c                 |  76 +++--
- tests/qtest/npcm7xx_timer-test.c        | 562 ++++++++++++++++++++++++++++++++
- hw/arm/Kconfig                          |   1 +
- hw/intc/trace-events                    |   4 +
- hw/timer/trace-events                   |   6 +-
- scripts/decodetree.py                   |   2 +-
- target/arm/translate-vfp.c.inc          |  41 ++-
- tests/qtest/meson.build                 |   1 +
-files changed, 1404 insertions(+), 147 deletions(-)
- create mode 100644 tests/qtest/npcm7xx_timer-test.c

v2: dropped linux-user bti series.

The following changes since commit 4c41341af76cfc85b5a6c0f87de4838672ab9f89:

Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging (2020-10-20 11:20:36 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201020-1

for you to fetch changes up to 8128c8e8cc9489a8387c74075974f86dc0222e7f:

target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension (2020-10-20 16:12:01 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix AArch32 SMLAD incorrect setting of Q bit
 * AArch32 VCVT fixed-point to float is always round-to-nearest
 * strongarm: Fix 'time to transmit a char' unit comment
 * Restrict APEI tables generation to the 'virt' machine
 * bcm2835: minor code cleanups
 * bcm2835: connect all IRQs from SYS_timer device
 * correctly flush TLBs when TBI is enabled
 * tests/qtest: Add npcm7xx timer test
 * loads-stores.rst: add footnote that clarifies GETPC usage
 * Fix reported EL for mte_check_fail
 * Ignore HCR_EL2.ATA when {E2H,TGE} != 11
 * microbit_i2c: Fix coredump when dump-vmstate
 * nseries: Fix loading kernel image on n8x0 machines
 * Implement v8.1M low-overhead-loops

----------------------------------------------------------------
Emanuele Giuseppe Esposito (1):
      loads-stores.rst: add footnote that clarifies GETPC usage

Havard Skinnemoen (1):
      tests/qtest: Add npcm7xx timer test

Peng Liang (1):
      microbit_i2c: Fix coredump when dump-vmstate

Peter Maydell (12):
      target/arm: Fix SMLAD incorrect setting of Q bit
      target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
      decodetree: Fix codegen for non-overlapping group inside overlapping group
      target/arm: Implement v8.1M NOCP handling
      target/arm: Implement v8.1M conditional-select insns
      target/arm: Make the t32 insn[25:23]=111 group non-overlapping
      target/arm: Don't allow BLX imm for M-profile
      target/arm: Implement v8.1M branch-future insns (as NOPs)
      target/arm: Implement v8.1M low-overhead-loop instructions
      target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
      target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
      target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension

Philippe Mathieu-Daudé (9):
      hw/arm/strongarm: Fix 'time to transmit a char' unit comment
      hw/arm: Restrict APEI tables generation to the 'virt' machine
      hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
      hw/timer/bcm2835: Rename variable holding CTRL_STATUS register
      hw/timer/bcm2835: Support the timer COMPARE registers
      hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
      hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
      hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
      hw/arm/nseries: Fix loading kernel image on n8x0 machines

Richard Henderson (5):
      accel/tcg: Add tlb_flush_page_bits_by_mmuidx*
      target/arm: Use tlb_flush_page_bits_by_mmuidx*
      target/arm: Remove redundant mmu_idx lookup
      target/arm: Fix reported EL for mte_check_fail
      target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11

v2: drop pvpanic-pci patches.

The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1

for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:

docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)

----------------------------------------------------------------
target-arm queue:
 * Implement IMPDEF pauth algorithm
 * Support ARMv8.4-SEL2
 * Fix bug where we were truncating predicate vector lengths in SVE insns
 * npcm7xx_adc-test: Fix memleak in adc_qom_set
 * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
 * docs: Build and install all the docs in a single manual

----------------------------------------------------------------
Gan Qixin (1):
      npcm7xx_adc-test: Fix memleak in adc_qom_set

Peter Maydell (1):
      docs: Build and install all the docs in a single manual

Philippe Mathieu-Daudé (1):
      target/arm/m_helper: Silence GCC 10 maybe-uninitialized error

Richard Henderson (7):
      target/arm: Implement an IMPDEF pauth algorithm
      target/arm: Add cpu properties to control pauth
      target/arm: Use object_property_add_bool for "sve" property
      target/arm: Introduce PREDDESC field definitions
      target/arm: Update PFIRST, PNEXT for pred_desc
      target/arm: Update ZIP, UZP, TRN for pred_desc
      target/arm: Update REV, PUNPK for pred_desc

Rémi Denis-Courmont (19):
      target/arm: remove redundant tests
      target/arm: add arm_is_el2_enabled() helper
      target/arm: use arm_is_el2_enabled() where applicable
      target/arm: use arm_hcr_el2_eff() where applicable
      target/arm: factor MDCR_EL2 common handling
      target/arm: Define isar_feature function to test for presence of SEL2
      target/arm: add 64-bit S-EL2 to EL exception table
      target/arm: add MMU stage 1 for Secure EL2
      target/arm: add ARMv8.4-SEL2 system registers
      target/arm: handle VMID change in secure state
      target/arm: do S1_ptw_translate() before address space lookup
      target/arm: translate NS bit in page-walks
      target/arm: generalize 2-stage page-walk condition
      target/arm: secure stage 2 translation regime
      target/arm: set HPFAR_EL2.NS on secure stage 2 faults
      target/arm: revector to run-time pick target EL
      target/arm: Implement SCR_EL2.EEL2
      target/arm: enable Secure EL2 in max CPU
      target/arm: refactor vae1_tlbmask()