[PATCH v3 0/5] RISC-V Pointer Masking implementation

Alexey Baturo posted 5 patches 3 days ago
Test checkpatch failed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20201016221138.10371-1-space.monkey.delivers@gmail.com
Maintainers: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Alistair Francis <Alistair.Francis@wdc.com>
target/riscv/cpu.c                      |  24 +++
target/riscv/cpu.h                      |  32 +++
target/riscv/cpu_bits.h                 |  66 ++++++
target/riscv/csr.c                      | 264 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc |   3 +
target/riscv/insn_trans/trans_rvd.c.inc |   2 +
target/riscv/insn_trans/trans_rvf.c.inc |   2 +
target/riscv/insn_trans/trans_rvi.c.inc |   2 +
target/riscv/translate.c                |  44 ++++
9 files changed, 439 insertions(+)

[PATCH v3 0/5] RISC-V Pointer Masking implementation

Posted by Alexey Baturo 3 days ago
Hi folks,

This is third iteration of patches to support Pointer Masking for RISC-V.
Most of suggestions have been addressed, however some of them not:
- applying mask for return value while reading PM CSR has been kept to mask higher priv level bits
- check_pm_current_disabled is not placed into CSR predicate, since the spec expects to read zero from PM CSR if no PM extenstion is present

Thanks

Alexey Baturo (4):
  [RISCV_PM] Add J-extension into RISC-V
  [RISCV_PM] Support CSRs required for RISC-V PM extension except for
    ones in hypervisor mode
  [RISCV_PM] Print new PM CSRs in QEMU logs
  [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
    instructions

Anatoly Parshintsev (1):
  [RISCV_PM] Implement address masking functions required for RISC-V
    Pointer Masking extension

 target/riscv/cpu.c                      |  24 +++
 target/riscv/cpu.h                      |  32 +++
 target/riscv/cpu_bits.h                 |  66 ++++++
 target/riscv/csr.c                      | 264 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rva.c.inc |   3 +
 target/riscv/insn_trans/trans_rvd.c.inc |   2 +
 target/riscv/insn_trans/trans_rvf.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc |   2 +
 target/riscv/translate.c                |  44 ++++
 9 files changed, 439 insertions(+)

-- 
2.20.1


Re: [PATCH v3 0/5] RISC-V Pointer Masking implementation

Posted by no-reply@patchew.org 3 days ago
Patchew URL: https://patchew.org/QEMU/20201016221138.10371-1-space.monkey.delivers@gmail.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20201016221138.10371-1-space.monkey.delivers@gmail.com
Subject: [PATCH v3 0/5] RISC-V Pointer Masking implementation

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20201016210754.818257-1-richard.henderson@linaro.org -> patchew/20201016210754.818257-1-richard.henderson@linaro.org
 * [new tag]         patchew/20201016221138.10371-1-space.monkey.delivers@gmail.com -> patchew/20201016221138.10371-1-space.monkey.delivers@gmail.com
Switched to a new branch 'test'
fb26b62 Implement address masking functions required for RISC-V Pointer Masking extension
1135d53 Support pointer masking for RISC-V for i/c/f/d/a types of instructions
760b894 Print new PM CSRs in QEMU logs
c4c4e27 Support CSRs required for RISC-V PM extension except for ones in hypervisor mode
5981961 Add J-extension into RISC-V

=== OUTPUT BEGIN ===
1/5 Checking commit 5981961fdb00 (Add J-extension into RISC-V)
2/5 Checking commit c4c4e27fe937 (Support CSRs required for RISC-V PM extension except for ones in hypervisor mode)
WARNING: Block comments use a leading /* on a separate line
#31: FILE: target/riscv/cpu.h:230:
+    /* CSRs for PM

ERROR: trailing whitespace
#146: FILE: target/riscv/csr.c:1258:
+/* Functions to access Pointer Masking feature registers $

WARNING: Block comments use a leading /* on a separate line
#146: FILE: target/riscv/csr.c:1258:
+/* Functions to access Pointer Masking feature registers 

ERROR: line over 90 characters
#153: FILE: target/riscv/csr.c:1265:
+    /* If priv lvls differ that means we're accessing csr from higher priv lvl, so allow */

WARNING: line over 80 characters
#172: FILE: target/riscv/csr.c:1284:
+    /* We're in same priv lvl, so we allow to modify csr only if pm_current==1 */

ERROR: line over 90 characters
#194: FILE: target/riscv/csr.c:1306:
+                      "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", val, wpri_val);

ERROR: line over 90 characters
#220: FILE: target/riscv/csr.c:1332:
+                      "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", val, wpri_val);

ERROR: line over 90 characters
#249: FILE: target/riscv/csr.c:1361:
+                      "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n", val, wpri_val);

total: 5 errors, 3 warnings, 382 lines checked

Patch 2/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/5 Checking commit 760b8944af78 (Print new PM CSRs in QEMU logs)
WARNING: line over 80 characters
#22: FILE: target/riscv/cpu.c:262:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", env->upmbase);

WARNING: line over 80 characters
#23: FILE: target/riscv/cpu.c:263:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", env->upmmask);

WARNING: line over 80 characters
#26: FILE: target/riscv/cpu.c:266:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", env->spmbase);

WARNING: line over 80 characters
#27: FILE: target/riscv/cpu.c:267:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", env->spmmask);

WARNING: line over 80 characters
#30: FILE: target/riscv/cpu.c:270:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", env->mpmbase);

WARNING: line over 80 characters
#31: FILE: target/riscv/cpu.c:271:
+            qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", env->mpmmask);

total: 0 errors, 6 warnings, 25 lines checked

Patch 3/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/5 Checking commit 1135d53a1565 (Support pointer masking for RISC-V for i/c/f/d/a types of instructions)
5/5 Checking commit fb26b62914a4 (Implement address masking functions required for RISC-V Pointer Masking extension)
WARNING: line over 80 characters
#110: FILE: target/riscv/translate.c:966:
+    pm_mask[PRV_U] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask),

WARNING: line over 80 characters
#112: FILE: target/riscv/translate.c:968:
+    pm_base[PRV_U] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase),

WARNING: line over 80 characters
#114: FILE: target/riscv/translate.c:970:
+    pm_mask[PRV_S] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask),

WARNING: line over 80 characters
#116: FILE: target/riscv/translate.c:972:
+    pm_base[PRV_S] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase),

WARNING: line over 80 characters
#118: FILE: target/riscv/translate.c:974:
+    pm_mask[PRV_M] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask),

WARNING: line over 80 characters
#120: FILE: target/riscv/translate.c:976:
+    pm_base[PRV_M] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase),

total: 0 errors, 6 warnings, 98 lines checked

Patch 5/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20201016221138.10371-1-space.monkey.delivers@gmail.com/testing.checkpatch/?type=message.
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