[v6] Enable CET support for guest

[Qemu-devel][PATCH v6 0/6] Enable CET support for guest

Yang Weijiang posted 6 patches 3 years, 6 months ago

Diff against v5 v7 v8
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git fetch https://github.com/patchew-project/qemu tags/patchew/20201013051935.6052-1-weijiang.yang@intel.com

Maintainers: Eduardo Habkost <ehabkost@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <rth@twiddle.net>, Marcelo Tosatti <mtosatti@redhat.com>

There is a newer version of this series

target/i386/cpu.c        | 132 +++++++++++++++++++++++---------
target/i386/cpu.h        |  57 +++++++++++++-
target/i386/fpu_helper.c |   2 +-
target/i386/kvm.c        |  73 ++++++++++++++++++
target/i386/machine.c    | 161 +++++++++++++++++++++++++++++++++++++++
target/i386/translate.c  |   2 +-
6 files changed, 384 insertions(+), 43 deletions(-)

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[Qemu-devel][PATCH v6 0/6] Enable CET support for guest

Posted by Yang Weijiang 3 years, 6 months ago

Control-flow Enforcement Technology (CET) provides protection against
Return/Jump-Oriented Programming (ROP/JOP). It includes two sub-features:
Shadow Stack(SHSTK) and Indirect Branch Tracking(IBT).
This patchset is for guest CET enabling. It enclosed patches for
XSS feature report and CET CPUID enumeration, XSAVE support and MSR
access interface etc.

Related patch series:
CET KVM patches v14:
https://github.com/sean-jc/linux/releases/tag/kvm-cet-v14-rc1

Intel 64 and IA-32 Architectures Software Developer's Manual:
https://software.intel.com/en-us/download/intel-64-and-ia-32-
architectures-sdm-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4

CET Shadow Stack patches v14:
https://lkml.kernel.org/r/20201012153850.26996-1-yu-cheng.yu@intel.com/

[3] Indirect Branch Tracking patches v14.
https://lkml.kernel.org/r/20201012154530.28382-1-yu-cheng.yu@intel.com/

v6:
  - Cleaned up XSAVE related naming for adding XSS features.
  - Refactored patches based on new QEMU code base.
v5:
  - Checked CET states before access related MSRs.
  - Added new MSR MSR_KVM_GUEST_SSP for live-migration.
  - Refactored patches to make them more structured.

v4:
  - Added MSR read/write interface for PL1_SSP/PL2_SSP.
  - Removed CET structures from X86XSaveArea.
  - Cleared ebx in return of CPUID.(EAX=d, ECX=1).
 
v3:
  - Add CET MSR save/restore support for live-migration.
 
v2:
  - In CPUID.(EAX=d, ECX=1), set return ECX[n] = 0 if bit n corresponds
    to a bit in MSR_IA32_XSS.
  - In CPUID.(EAX=d, ECX=n), set return ECX = 1 if bit n corresponds
    to a bit in MSR_IA32_XSS.
  - Skip Supervisor mode xsave component when calculate User mode
    xave component size in xsave_area_size() and x86_cpu_reset().

Yang Weijiang (6):
  x86/cpu: Rename XSAVE related feature words.
  x86/cpuid: Enable XSS feature enumeration for CPUID
  x86/cpu: Enable CET components support for XSAVE
  x86/cpu: Add user-space MSR access interface for CET
  x86/cpu: Add CET state support for guest migration
  x86/cpu: Advise CET bits in CPU/MSR feature words

 target/i386/cpu.c        | 132 +++++++++++++++++++++++---------
 target/i386/cpu.h        |  57 +++++++++++++-
 target/i386/fpu_helper.c |   2 +-
 target/i386/kvm.c        |  73 ++++++++++++++++++
 target/i386/machine.c    | 161 +++++++++++++++++++++++++++++++++++++++
 target/i386/translate.c  |   2 +-
 6 files changed, 384 insertions(+), 43 deletions(-)

-- 
2.26.2