[PULL 00/12] target-arm queue
[PULL 00/32] target-arm queue
1
The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:
1
target-arm queue: the big stuff here is the final part of
2
rth's patches for Cortex-A76 and Neoverse-N1 support;
3
also present are Gavin's NUMA series and a few other things.
2
4
3
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)
5
thanks
6
-- PMM
7
8
The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
9
10
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging (2022-05-08 17:03:26 -0500)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201008
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220509
8
15
9
for you to fetch changes up to ba118c26e16a97e6ff6de8184057d3420ce16a23:
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for you to fetch changes up to ae9141d4a3265553503bf07d3574b40f84615a34:
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17
11
target/arm: Make '-cpu max' have a 48-bit PA (2020-10-08 15:24:32 +0100)
18
hw/acpi/aml-build: Use existing CPU topology to build PPTT table (2022-05-09 11:47:55 +0100)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
target-arm queue:
21
target-arm queue:
15
* hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
22
* MAINTAINERS/.mailmap: update email for Leif Lindholm
16
* hw/arm/fsl-imx25: Fix a typo
23
* hw/arm: add version information to sbsa-ref machine DT
17
* hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
24
* Enable new features for -cpu max:
18
* hw/arm/sbsa-ref : allocate IRQs for SMMUv3
25
FEAT_Debugv8p2, FEAT_Debugv8p4, FEAT_RAS (minimal version only),
19
* hw/char/bcm2835_aux: Allow less than 32-bit accesses
26
FEAT_IESB, FEAT_CSV2, FEAT_CSV2_2, FEAT_CSV3, FEAT_DGH
20
* hw/arm/virt: Implement kvm-steal-time
27
* Emulate Cortex-A76
21
* target/arm: Make '-cpu max' have a 48-bit PA
28
* Emulate Neoverse-N1
29
* Fix the virt board default NUMA topology
22
30
23
----------------------------------------------------------------
31
----------------------------------------------------------------
24
Andrew Jones (6):
32
Gavin Shan (6):
25
linux headers: sync to 5.9-rc7
33
qapi/machine.json: Add cluster-id
26
target/arm/kvm: Make uncalled stubs explicitly unreachable
34
qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
27
hw/arm/virt: Move post cpu realize check into its own function
35
hw/arm/virt: Consider SMP configuration in CPU topology
28
hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
36
qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
29
tests/qtest: Restore aarch64 arm-cpu-features test
37
hw/arm/virt: Fix CPU's default NUMA node ID
30
hw/arm/virt: Implement kvm-steal-time
38
hw/acpi/aml-build: Use existing CPU topology to build PPTT table
31
39
32
Graeme Gregory (2):
40
Leif Lindholm (2):
33
hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
41
MAINTAINERS/.mailmap: update email for Leif Lindholm
34
hw/arm/sbsa-ref : allocate IRQs for SMMUv3
42
hw/arm: add versioning to sbsa-ref machine DT
35
43
36
Peter Maydell (1):
44
Richard Henderson (24):
37
target/arm: Make '-cpu max' have a 48-bit PA
45
target/arm: Handle cpreg registration for missing EL
46
target/arm: Drop EL3 no EL2 fallbacks
47
target/arm: Merge zcr reginfo
48
target/arm: Adjust definition of CONTEXTIDR_EL2
49
target/arm: Move cortex impdef sysregs to cpu_tcg.c
50
target/arm: Update qemu-system-arm -cpu max to cortex-a57
51
target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
52
target/arm: Split out aa32_max_features
53
target/arm: Annotate arm_max_initfn with FEAT identifiers
54
target/arm: Use field names for manipulating EL2 and EL3 modes
55
target/arm: Enable FEAT_Debugv8p2 for -cpu max
56
target/arm: Enable FEAT_Debugv8p4 for -cpu max
57
target/arm: Add minimal RAS registers
58
target/arm: Enable SCR and HCR bits for RAS
59
target/arm: Implement virtual SError exceptions
60
target/arm: Implement ESB instruction
61
target/arm: Enable FEAT_RAS for -cpu max
62
target/arm: Enable FEAT_IESB for -cpu max
63
target/arm: Enable FEAT_CSV2 for -cpu max
64
target/arm: Enable FEAT_CSV2_2 for -cpu max
65
target/arm: Enable FEAT_CSV3 for -cpu max
66
target/arm: Enable FEAT_DGH for -cpu max
67
target/arm: Define cortex-a76
68
target/arm: Define neoverse-n1
38
69
39
Philippe Mathieu-Daudé (3):
70
docs/system/arm/emulation.rst | 10 +
40
hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
71
docs/system/arm/virt.rst | 2 +
41
hw/arm/fsl-imx25: Fix a typo
72
qapi/machine.json | 6 +-
42
hw/char/bcm2835_aux: Allow less than 32-bit accesses
73
target/arm/cpregs.h | 11 +
43
74
target/arm/cpu.h | 23 ++
44
docs/system/arm/cpu-features.rst | 11 ++++
75
target/arm/helper.h | 1 +
45
include/hw/arm/fsl-imx25.h | 2 +-
76
target/arm/internals.h | 16 ++
46
include/hw/arm/virt.h | 5 ++
77
target/arm/syndrome.h | 5 +
47
linux-headers/linux/kvm.h | 6 ++-
78
target/arm/a32.decode | 16 +-
48
target/arm/cpu.h | 4 ++
79
target/arm/t32.decode | 18 +-
49
target/arm/kvm_arm.h | 94 ++++++++++++++++++++++++++-------
80
hw/acpi/aml-build.c | 111 ++++----
50
hw/arm/sbsa-ref.c | 3 +-
81
hw/arm/sbsa-ref.c | 16 ++
51
hw/arm/virt.c | 110 ++++++++++++++++++++++++++++-----------
82
hw/arm/virt.c | 21 +-
52
hw/char/bcm2835_aux.c | 4 +-
83
hw/core/machine-hmp-cmds.c | 4 +
53
hw/ssi/npcm7xx_fiu.c | 12 ++---
84
hw/core/machine.c | 16 ++
54
target/arm/cpu.c | 8 +++
85
target/arm/cpu.c | 66 ++++-
55
target/arm/cpu64.c | 4 ++
86
target/arm/cpu64.c | 353 ++++++++++++++-----------
56
target/arm/kvm.c | 16 ++++++
87
target/arm/cpu_tcg.c | 227 +++++++++++-----
57
target/arm/kvm64.c | 64 +++++++++++++++++++++--
88
target/arm/helper.c | 600 +++++++++++++++++++++++++-----------------
58
target/arm/monitor.c | 2 +-
89
target/arm/op_helper.c | 43 +++
59
tests/qtest/arm-cpu-features.c | 25 +++++++--
90
target/arm/translate-a64.c | 18 ++
60
hw/ssi/trace-events | 2 +-
91
target/arm/translate.c | 23 ++
61
tests/qtest/meson.build | 3 +-
92
tests/qtest/numa-test.c | 19 +-
62
18 files changed, 303 insertions(+), 72 deletions(-)
93
.mailmap | 3 +-
63
94
MAINTAINERS | 2 +-
95
25 files changed, 1068 insertions(+), 562 deletions(-)
diff view generated by jsdifflib
[PULL 06/12] linux headers: sync to 5.9-rc7
[PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm
1
From: Andrew Jones <drjones@redhat.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
Update against Linux 5.9-rc7.
3
NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
4
separate infrastructure for a transitional period. We've now switched
5
over to contributing as Qualcomm Innovation Center (quicinc), so update
6
my email address to reflect this.
4
7
5
Cc: Paolo Bonzini <pbonzini@redhat.com>
8
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
6
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com
7
Message-id: 20201001061718.101915-2-drjones@redhat.com
10
Cc: Leif Lindholm <leif@nuviainc.com>
11
Cc: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
[Fixed commit message typo]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
15
---
10
linux-headers/linux/kvm.h | 6 ++++--
16
.mailmap | 3 ++-
11
1 file changed, 4 insertions(+), 2 deletions(-)
17
MAINTAINERS | 2 +-
18
2 files changed, 3 insertions(+), 2 deletions(-)
12
19
13
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
20
diff --git a/.mailmap b/.mailmap
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/linux-headers/linux/kvm.h
22
--- a/.mailmap
16
+++ b/linux-headers/linux/kvm.h
23
+++ b/.mailmap
17
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
24
@@ -XXX,XX +XXX,XX @@ Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
18
#define KVM_VM_PPC_HV 1
25
Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
19
#define KVM_VM_PPC_PR 2
26
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
20
27
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
21
-/* on MIPS, 0 forces trap & emulate, 1 forces VZ ASE */
28
-Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
22
-#define KVM_VM_MIPS_TE        0
29
+Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
23
+/* on MIPS, 0 indicates auto, 1 forces VZ ASE, 2 forces trap & emulate */
30
+Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
24
+#define KVM_VM_MIPS_AUTO    0
31
Radoslaw Biernacki <rad@semihalf.com> <radoslaw.biernacki@linaro.org>
25
#define KVM_VM_MIPS_VZ        1
32
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
26
+#define KVM_VM_MIPS_TE        2
33
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
27
34
diff --git a/MAINTAINERS b/MAINTAINERS
28
#define KVM_S390_SIE_PAGE_OFFSET 1
35
index XXXXXXX..XXXXXXX 100644
29
36
--- a/MAINTAINERS
30
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
37
+++ b/MAINTAINERS
31
#define KVM_CAP_LAST_CPU 184
38
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
32
#define KVM_CAP_SMALLER_MAXPHYADDR 185
39
SBSA-REF
33
#define KVM_CAP_S390_DIAG318 186
40
M: Radoslaw Biernacki <rad@semihalf.com>
34
+#define KVM_CAP_STEAL_TIME 187
41
M: Peter Maydell <peter.maydell@linaro.org>
35
42
-R: Leif Lindholm <leif@nuviainc.com>
36
#ifdef KVM_CAP_IRQ_ROUTING
43
+R: Leif Lindholm <quic_llindhol@quicinc.com>
37
44
L: qemu-arm@nongnu.org
45
S: Maintained
46
F: hw/arm/sbsa-ref.c
38
--
47
--
39
2.20.1
48
2.25.1
40
49
41
50
diff view generated by jsdifflib
New patch
[PULL 02/32] target/arm: Handle cpreg registration for missing EL
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
More gracefully handle cpregs when EL2 and/or EL3 are missing.
4
If the reg is entirely inaccessible, do not register it at all.
5
If the reg is for EL2, and EL3 is present but EL2 is not,
6
either discard, squash to res0, const, or keep unchanged.
7
8
Per rule RJFFP, mark the 4 aarch32 hypervisor access registers
9
with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address
10
translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF.
11
Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ.
12
13
This will simplify cpreg registration for conditional arm features.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20220506180242.216785-2-richard.henderson@linaro.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/cpregs.h | 11 +++
21
target/arm/helper.c | 178 ++++++++++++++++++++++++++++++--------------
22
2 files changed, 133 insertions(+), 56 deletions(-)
23
24
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpregs.h
27
+++ b/target/arm/cpregs.h
28
@@ -XXX,XX +XXX,XX @@ enum {
29
ARM_CP_SVE = 1 << 14,
30
/* Flag: Do not expose in gdb sysreg xml. */
31
ARM_CP_NO_GDB = 1 << 15,
32
+ /*
33
+ * Flags: If EL3 but not EL2...
34
+ * - UNDEF: discard the cpreg,
35
+ * - KEEP: retain the cpreg as is,
36
+ * - C_NZ: set const on the cpreg, but retain resetvalue,
37
+ * - else: set const on the cpreg, zero resetvalue, aka RES0.
38
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
39
+ */
40
+ ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16,
41
+ ARM_CP_EL3_NO_EL2_KEEP = 1 << 17,
42
+ ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18,
43
};
44
45
/*
46
diff --git a/target/arm/helper.c b/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/helper.c
49
+++ b/target/arm/helper.c
50
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
51
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
52
{ .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
53
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
54
- .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
55
+ .access = PL2_RW,
56
+ .type = ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP,
57
.fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
58
{ .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
59
.opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
60
- .access = PL2_RW, .resetvalue = 0,
61
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
62
.writefn = dacr_write, .raw_writefn = raw_write,
63
.fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
64
{ .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
65
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
66
- .access = PL2_RW, .resetvalue = 0,
67
+ .access = PL2_RW, .resetvalue = 0, .type = ARM_CP_EL3_NO_EL2_KEEP,
68
.fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
69
{ .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
70
.type = ARM_CP_ALIAS,
71
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
72
.writefn = tlbimva_hyp_is_write },
73
{ .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
74
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
75
- .type = ARM_CP_NO_RAW, .access = PL2_W,
76
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
77
.writefn = tlbi_aa64_alle2_write },
78
{ .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
79
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
80
- .type = ARM_CP_NO_RAW, .access = PL2_W,
81
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
82
.writefn = tlbi_aa64_vae2_write },
83
{ .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
84
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
85
- .access = PL2_W, .type = ARM_CP_NO_RAW,
86
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
87
.writefn = tlbi_aa64_vae2_write },
88
{ .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
89
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
90
- .access = PL2_W, .type = ARM_CP_NO_RAW,
91
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
92
.writefn = tlbi_aa64_alle2is_write },
93
{ .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
94
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
95
- .type = ARM_CP_NO_RAW, .access = PL2_W,
96
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
97
.writefn = tlbi_aa64_vae2is_write },
98
{ .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
99
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
100
- .access = PL2_W, .type = ARM_CP_NO_RAW,
101
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
102
.writefn = tlbi_aa64_vae2is_write },
103
#ifndef CONFIG_USER_ONLY
104
/* Unlike the other EL2-related AT operations, these must
105
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
106
{ .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
107
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
108
.access = PL2_W, .accessfn = at_s1e2_access,
109
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
110
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
111
+ .writefn = ats_write64 },
112
{ .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
113
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
114
.access = PL2_W, .accessfn = at_s1e2_access,
115
- .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn = ats_write64 },
116
+ .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
117
+ .writefn = ats_write64 },
118
/* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
119
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
120
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
121
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
122
{ .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
123
.opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
124
.access = PL2_RW, .accessfn = access_tda,
125
- .type = ARM_CP_NOP },
126
+ .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
127
/* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
128
* Channel but Linux may try to access this register. The 32-bit
129
* alias is DBGDCCINT.
130
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
131
.access = PL2_W, .type = ARM_CP_NOP },
132
{ .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64,
133
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1,
134
- .access = PL2_W, .type = ARM_CP_NO_RAW,
135
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
136
.writefn = tlbi_aa64_rvae2is_write },
137
{ .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64,
138
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5,
139
- .access = PL2_W, .type = ARM_CP_NO_RAW,
140
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
141
.writefn = tlbi_aa64_rvae2is_write },
142
{ .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64,
143
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2,
144
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
145
.access = PL2_W, .type = ARM_CP_NOP },
146
{ .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64,
147
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1,
148
- .access = PL2_W, .type = ARM_CP_NO_RAW,
149
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
150
.writefn = tlbi_aa64_rvae2is_write },
151
{ .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64,
152
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5,
153
- .access = PL2_W, .type = ARM_CP_NO_RAW,
154
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
155
.writefn = tlbi_aa64_rvae2is_write },
156
{ .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64,
157
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1,
158
- .access = PL2_W, .type = ARM_CP_NO_RAW,
159
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
160
.writefn = tlbi_aa64_rvae2_write },
161
{ .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64,
162
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5,
163
- .access = PL2_W, .type = ARM_CP_NO_RAW,
164
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
165
.writefn = tlbi_aa64_rvae2_write },
166
{ .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64,
167
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1,
168
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
169
.writefn = tlbi_aa64_vae1is_write },
170
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
171
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
172
- .access = PL2_W, .type = ARM_CP_NO_RAW,
173
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
174
.writefn = tlbi_aa64_alle2is_write },
175
{ .name = "TLBI_VAE2OS", .state = ARM_CP_STATE_AA64,
176
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 1,
177
- .access = PL2_W, .type = ARM_CP_NO_RAW,
178
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
179
.writefn = tlbi_aa64_vae2is_write },
180
{ .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64,
181
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4,
182
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbios_reginfo[] = {
183
.writefn = tlbi_aa64_alle1is_write },
184
{ .name = "TLBI_VALE2OS", .state = ARM_CP_STATE_AA64,
185
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 5,
186
- .access = PL2_W, .type = ARM_CP_NO_RAW,
187
+ .access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
188
.writefn = tlbi_aa64_vae2is_write },
189
{ .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64,
190
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6,
191
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
192
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
193
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
194
.access = PL2_RW, .accessfn = access_el3_aa32ns,
195
- .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
196
+ .resetvalue = cpu->midr,
197
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
198
.fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
199
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
200
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
201
.access = PL2_RW, .resetvalue = cpu->midr,
202
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
203
.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
204
{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
205
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
206
.access = PL2_RW, .accessfn = access_el3_aa32ns,
207
- .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
208
+ .resetvalue = vmpidr_def,
209
+ .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ,
210
.fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
211
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
212
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
213
- .access = PL2_RW,
214
- .resetvalue = vmpidr_def,
215
+ .access = PL2_RW, .resetvalue = vmpidr_def,
216
+ .type = ARM_CP_EL3_NO_EL2_C_NZ,
217
.fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
218
};
219
define_arm_cp_regs(cpu, vpidr_regs);
220
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
221
int crm, int opc1, int opc2,
222
const char *name)
223
{
224
+ CPUARMState *env = &cpu->env;
225
uint32_t key;
226
ARMCPRegInfo *r2;
227
bool is64 = r->type & ARM_CP_64BIT;
228
bool ns = secstate & ARM_CP_SECSTATE_NS;
229
int cp = r->cp;
230
- bool isbanked;
231
size_t name_len;
232
+ bool make_const;
233
234
switch (state) {
235
case ARM_CP_STATE_AA32:
236
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
237
}
238
}
239
240
+ /*
241
+ * Eliminate registers that are not present because the EL is missing.
242
+ * Doing this here makes it easier to put all registers for a given
243
+ * feature into the same ARMCPRegInfo array and define them all at once.
244
+ */
245
+ make_const = false;
246
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
247
+ /*
248
+ * An EL2 register without EL2 but with EL3 is (usually) RES0.
249
+ * See rule RJFFP in section D1.1.3 of DDI0487H.a.
250
+ */
251
+ int min_el = ctz32(r->access) / 2;
252
+ if (min_el == 2 && !arm_feature(env, ARM_FEATURE_EL2)) {
253
+ if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) {
254
+ return;
255
+ }
256
+ make_const = !(r->type & ARM_CP_EL3_NO_EL2_KEEP);
257
+ }
258
+ } else {
259
+ CPAccessRights max_el = (arm_feature(env, ARM_FEATURE_EL2)
260
+ ? PL2_RW : PL1_RW);
261
+ if ((r->access & max_el) == 0) {
262
+ return;
263
+ }
264
+ }
265
+
266
/* Combine cpreg and name into one allocation. */
267
name_len = strlen(name) + 1;
268
r2 = g_malloc(sizeof(*r2) + name_len);
269
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
270
r2->opaque = opaque;
271
}
272
273
- isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
274
- if (isbanked) {
275
+ if (make_const) {
276
+ /* This should not have been a very special register to begin. */
277
+ int old_special = r2->type & ARM_CP_SPECIAL_MASK;
278
+ assert(old_special == 0 || old_special == ARM_CP_NOP);
279
/*
280
- * Register is banked (using both entries in array).
281
- * Overwriting fieldoffset as the array is only used to define
282
- * banked registers but later only fieldoffset is used.
283
+ * Set the special function to CONST, retaining the other flags.
284
+ * This is important for e.g. ARM_CP_SVE so that we still
285
+ * take the SVE trap if CPTR_EL3.EZ == 0.
286
*/
287
- r2->fieldoffset = r->bank_fieldoffsets[ns];
288
- }
289
+ r2->type = (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST;
290
+ /*
291
+ * Usually, these registers become RES0, but there are a few
292
+ * special cases like VPIDR_EL2 which have a constant non-zero
293
+ * value with writes ignored.
294
+ */
295
+ if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) {
296
+ r2->resetvalue = 0;
297
+ }
298
+ /*
299
+ * ARM_CP_CONST has precedence, so removing the callbacks and
300
+ * offsets are not strictly necessary, but it is potentially
301
+ * less confusing to debug later.
302
+ */
303
+ r2->readfn = NULL;
304
+ r2->writefn = NULL;
305
+ r2->raw_readfn = NULL;
306
+ r2->raw_writefn = NULL;
307
+ r2->resetfn = NULL;
308
+ r2->fieldoffset = 0;
309
+ r2->bank_fieldoffsets[0] = 0;
310
+ r2->bank_fieldoffsets[1] = 0;
311
+ } else {
312
+ bool isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
313
314
- if (state == ARM_CP_STATE_AA32) {
315
if (isbanked) {
316
/*
317
- * If the register is banked then we don't need to migrate or
318
- * reset the 32-bit instance in certain cases:
319
- *
320
- * 1) If the register has both 32-bit and 64-bit instances then we
321
- * can count on the 64-bit instance taking care of the
322
- * non-secure bank.
323
- * 2) If ARMv8 is enabled then we can count on a 64-bit version
324
- * taking care of the secure bank. This requires that separate
325
- * 32 and 64-bit definitions are provided.
326
+ * Register is banked (using both entries in array).
327
+ * Overwriting fieldoffset as the array is only used to define
328
+ * banked registers but later only fieldoffset is used.
329
*/
330
- if ((r->state == ARM_CP_STATE_BOTH && ns) ||
331
- (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
332
+ r2->fieldoffset = r->bank_fieldoffsets[ns];
333
+ }
334
+ if (state == ARM_CP_STATE_AA32) {
335
+ if (isbanked) {
336
+ /*
337
+ * If the register is banked then we don't need to migrate or
338
+ * reset the 32-bit instance in certain cases:
339
+ *
340
+ * 1) If the register has both 32-bit and 64-bit instances
341
+ * then we can count on the 64-bit instance taking care
342
+ * of the non-secure bank.
343
+ * 2) If ARMv8 is enabled then we can count on a 64-bit
344
+ * version taking care of the secure bank. This requires
345
+ * that separate 32 and 64-bit definitions are provided.
346
+ */
347
+ if ((r->state == ARM_CP_STATE_BOTH && ns) ||
348
+ (arm_feature(env, ARM_FEATURE_V8) && !ns)) {
349
+ r2->type |= ARM_CP_ALIAS;
350
+ }
351
+ } else if ((secstate != r->secure) && !ns) {
352
+ /*
353
+ * The register is not banked so we only want to allow
354
+ * migration of the non-secure instance.
355
+ */
356
r2->type |= ARM_CP_ALIAS;
357
}
358
- } else if ((secstate != r->secure) && !ns) {
359
- /*
360
- * The register is not banked so we only want to allow migration
361
- * of the non-secure instance.
362
- */
363
- r2->type |= ARM_CP_ALIAS;
364
- }
365
366
- if (HOST_BIG_ENDIAN &&
367
- r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
368
- r2->fieldoffset += sizeof(uint32_t);
369
+ if (HOST_BIG_ENDIAN &&
370
+ r->state == ARM_CP_STATE_BOTH && r2->fieldoffset) {
371
+ r2->fieldoffset += sizeof(uint32_t);
372
+ }
373
}
374
}
375
376
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
377
* multiple times. Special registers (ie NOP/WFI) are
378
* never migratable and not even raw-accessible.
379
*/
380
- if (r->type & ARM_CP_SPECIAL_MASK) {
381
+ if (r2->type & ARM_CP_SPECIAL_MASK) {
382
r2->type |= ARM_CP_NO_RAW;
383
}
384
if (((r->crm == CP_ANY) && crm != 0) ||
385
--
386
2.25.1
diff view generated by jsdifflib
New patch
[PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
4
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
5
while registering for v8.
6
7
This is a behavior change for v7 cpus with Security Extensions and
8
without Virtualization Extensions, in that the virtualization cpregs
9
are now correctly not present. This would be a migration compatibility
10
break, except that we have an existing bug in which migration of 32-bit
11
cpus with Security Extensions enabled does not work.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.c | 158 ++++----------------------------------------
19
1 file changed, 13 insertions(+), 145 deletions(-)
20
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
24
+++ b/target/arm/helper.c
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
26
.fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
27
};
28
29
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
30
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
31
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH,
32
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
33
- .access = PL2_RW,
34
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
35
- { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
36
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
37
- .access = PL2_RW,
38
- .type = ARM_CP_CONST, .resetvalue = 0 },
39
- { .name = "HACR_EL2", .state = ARM_CP_STATE_BOTH,
40
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 7,
41
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
42
- { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH,
43
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
44
- .access = PL2_RW,
45
- .type = ARM_CP_CONST, .resetvalue = 0 },
46
- { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
47
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
48
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
49
- { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
50
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
51
- .access = PL2_RW, .type = ARM_CP_CONST,
52
- .resetvalue = 0 },
53
- { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
54
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
55
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
56
- { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
57
- .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
58
- .access = PL2_RW, .type = ARM_CP_CONST,
59
- .resetvalue = 0 },
60
- { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32,
61
- .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
62
- .access = PL2_RW, .type = ARM_CP_CONST,
63
- .resetvalue = 0 },
64
- { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
65
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
66
- .access = PL2_RW, .type = ARM_CP_CONST,
67
- .resetvalue = 0 },
68
- { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
69
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
70
- .access = PL2_RW, .type = ARM_CP_CONST,
71
- .resetvalue = 0 },
72
- { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
73
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
74
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
75
- { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
76
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
77
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
78
- .type = ARM_CP_CONST, .resetvalue = 0 },
79
- { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
80
- .cp = 15, .opc1 = 6, .crm = 2,
81
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
82
- .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
83
- { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
84
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
85
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
86
- { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
87
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
88
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
89
- { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
90
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
91
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
92
- { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
93
- .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
94
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
95
- { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
96
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
97
- .resetvalue = 0 },
98
- { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
99
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
100
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
101
- { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
102
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
103
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
104
- { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
105
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
106
- .resetvalue = 0 },
107
- { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
108
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
109
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
110
- { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
111
- .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
112
- .resetvalue = 0 },
113
- { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
114
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
115
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
116
- { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
117
- .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
118
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
119
- { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
120
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
121
- .access = PL2_RW, .accessfn = access_tda,
122
- .type = ARM_CP_CONST, .resetvalue = 0 },
123
- { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
124
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
125
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
126
- .type = ARM_CP_CONST, .resetvalue = 0 },
127
- { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
128
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
129
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
130
- { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH,
131
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
132
- .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
133
- { .name = "HIFAR", .state = ARM_CP_STATE_AA32,
134
- .type = ARM_CP_CONST,
135
- .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2,
136
- .access = PL2_RW, .resetvalue = 0 },
137
-};
138
-
139
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
140
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
141
- { .name = "HCR2", .state = ARM_CP_STATE_AA32,
142
- .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4,
143
- .access = PL2_RW,
144
- .type = ARM_CP_CONST, .resetvalue = 0 },
145
-};
146
-
147
static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
148
{
149
ARMCPU *cpu = env_archcpu(env);
150
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
151
define_arm_cp_regs(cpu, v8_idregs);
152
define_arm_cp_regs(cpu, v8_cp_reginfo);
153
}
154
- if (arm_feature(env, ARM_FEATURE_EL2)) {
155
+
156
+ /*
157
+ * Register the base EL2 cpregs.
158
+ * Pre v8, these registers are implemented only as part of the
159
+ * Virtualization Extensions (EL2 present). Beginning with v8,
160
+ * if EL2 is missing but EL3 is enabled, mostly these become
161
+ * RES0 from EL3, with some specific exceptions.
162
+ */
163
+ if (arm_feature(env, ARM_FEATURE_EL2)
164
+ || (arm_feature(env, ARM_FEATURE_EL3)
165
+ && arm_feature(env, ARM_FEATURE_V8))) {
166
uint64_t vmpidr_def = mpidr_read_val(env);
167
ARMCPRegInfo vpidr_regs[] = {
168
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
169
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
170
};
171
define_one_arm_cp_reg(cpu, &rvbar);
172
}
173
- } else {
174
- /* If EL2 is missing but higher ELs are enabled, we need to
175
- * register the no_el2 reginfos.
176
- */
177
- if (arm_feature(env, ARM_FEATURE_EL3)) {
178
- /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
179
- * of MIDR_EL1 and MPIDR_EL1.
180
- */
181
- ARMCPRegInfo vpidr_regs[] = {
182
- { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
183
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
184
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
185
- .type = ARM_CP_CONST, .resetvalue = cpu->midr,
186
- .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
187
- { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
188
- .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
189
- .access = PL2_RW, .accessfn = access_el3_aa32ns,
190
- .type = ARM_CP_NO_RAW,
191
- .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
192
- };
193
- define_arm_cp_regs(cpu, vpidr_regs);
194
- define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
195
- if (arm_feature(env, ARM_FEATURE_V8)) {
196
- define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
197
- }
198
- }
199
}
200
+
201
+ /* Register the base EL3 cpregs. */
202
if (arm_feature(env, ARM_FEATURE_EL3)) {
203
define_arm_cp_regs(cpu, el3_cp_reginfo);
204
ARMCPRegInfo el3_regs[] = {
205
--
206
2.25.1
diff view generated by jsdifflib
New patch
[PULL 04/32] target/arm: Merge zcr reginfo
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
4
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
5
while registering.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.c | 55 ++++++++++++++-------------------------------
13
1 file changed, 17 insertions(+), 38 deletions(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
}
21
}
22
23
-static const ARMCPRegInfo zcr_el1_reginfo = {
24
- .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
25
- .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
26
- .access = PL1_RW, .type = ARM_CP_SVE,
27
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
28
- .writefn = zcr_write, .raw_writefn = raw_write
29
-};
30
-
31
-static const ARMCPRegInfo zcr_el2_reginfo = {
32
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
33
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
34
- .access = PL2_RW, .type = ARM_CP_SVE,
35
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
36
- .writefn = zcr_write, .raw_writefn = raw_write
37
-};
38
-
39
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
40
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
41
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
42
- .access = PL2_RW, .type = ARM_CP_SVE,
43
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
44
-};
45
-
46
-static const ARMCPRegInfo zcr_el3_reginfo = {
47
- .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
48
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
49
- .access = PL3_RW, .type = ARM_CP_SVE,
50
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
51
- .writefn = zcr_write, .raw_writefn = raw_write
52
+static const ARMCPRegInfo zcr_reginfo[] = {
53
+ { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
54
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
55
+ .access = PL1_RW, .type = ARM_CP_SVE,
56
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
57
+ .writefn = zcr_write, .raw_writefn = raw_write },
58
+ { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
59
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
60
+ .access = PL2_RW, .type = ARM_CP_SVE,
61
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
62
+ .writefn = zcr_write, .raw_writefn = raw_write },
63
+ { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
64
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
65
+ .access = PL3_RW, .type = ARM_CP_SVE,
66
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
67
+ .writefn = zcr_write, .raw_writefn = raw_write },
68
};
69
70
void hw_watchpoint_update(ARMCPU *cpu, int n)
71
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
72
}
73
74
if (cpu_isar_feature(aa64_sve, cpu)) {
75
- define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
76
- if (arm_feature(env, ARM_FEATURE_EL2)) {
77
- define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
78
- } else {
79
- define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
80
- }
81
- if (arm_feature(env, ARM_FEATURE_EL3)) {
82
- define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
83
- }
84
+ define_arm_cp_regs(cpu, zcr_reginfo);
85
}
86
87
#ifdef TARGET_AARCH64
88
--
89
2.25.1
diff view generated by jsdifflib
New patch
[PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This register is present for either VHE or Debugv8p2.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 15 +++++++++++----
11
1 file changed, 11 insertions(+), 4 deletions(-)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
16
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo jazelle_regs[] = {
18
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
19
};
20
21
+static const ARMCPRegInfo contextidr_el2 = {
22
+ .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
23
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
24
+ .access = PL2_RW,
25
+ .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2])
26
+};
27
+
28
static const ARMCPRegInfo vhe_reginfo[] = {
29
- { .name = "CONTEXTIDR_EL2", .state = ARM_CP_STATE_AA64,
30
- .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
31
- .access = PL2_RW,
32
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
33
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
34
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
35
.access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
36
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
37
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
38
}
39
40
+ if (cpu_isar_feature(aa64_vh, cpu) ||
41
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
42
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
43
+ }
44
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
45
define_arm_cp_regs(cpu, vhe_reginfo);
46
}
47
--
48
2.25.1
diff view generated by jsdifflib
[PULL 01/12] hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
[PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fix integer handling issues handling issue reported by Coverity:
3
Previously we were defining some of these in user-only mode,
4
4
but none of them are accessible from user-only, therefore
5
hw/ssi/npcm7xx_fiu.c: 162 in npcm7xx_fiu_flash_read()
5
define them only in system mode.
6
>>> CID 1432730: Integer handling issues (NEGATIVE_RETURNS)
6
7
>>> "npcm7xx_fiu_cs_index(fiu, f)" is passed to a parameter that cannot be negative.
7
This will shortly be used from cpu_tcg.c also.
8
162 npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f));
8
9
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
hw/ssi/npcm7xx_fiu.c: 221 in npcm7xx_fiu_flash_write()
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
218 cs_id = npcm7xx_fiu_cs_index(fiu, f);
11
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
12
219 trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
13
220 size, v);
14
>>> CID 1432729: Integer handling issues (NEGATIVE_RETURNS)
15
>>> "cs_id" is passed to a parameter that cannot be negative.
16
221 npcm7xx_fiu_select(fiu, cs_id);
17
18
Since the index of the flash can not be negative, return an
19
unsigned type.
20
21
Reported-by: Coverity (CID 1432729 & 1432730: NEGATIVE_RETURNS)
22
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
24
Message-id: 20200919132435.310527-1-f4bug@amsat.org
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
13
---
27
hw/ssi/npcm7xx_fiu.c | 12 ++++++------
14
target/arm/internals.h | 6 ++++
28
hw/ssi/trace-events | 2 +-
15
target/arm/cpu64.c | 64 +++---------------------------------------
29
2 files changed, 7 insertions(+), 7 deletions(-)
16
target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++
30
17
3 files changed, 69 insertions(+), 60 deletions(-)
31
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
32
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/ssi/npcm7xx_fiu.c
21
--- a/target/arm/internals.h
34
+++ b/hw/ssi/npcm7xx_fiu.c
22
+++ b/target/arm/internals.h
35
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxFIURegister {
23
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
36
* Returns the index of flash in the fiu->flash array. This corresponds to the
24
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
37
* chip select ID of the flash.
25
#endif
38
*/
26
39
-static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
27
+#ifdef CONFIG_USER_ONLY
40
+static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu,
28
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
41
+ NPCM7xxFIUFlash *flash)
29
+#else
30
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
31
+#endif
32
+
33
#endif
34
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/cpu64.c
37
+++ b/target/arm/cpu64.c
38
@@ -XXX,XX +XXX,XX @@
39
#include "hvf_arm.h"
40
#include "qapi/visitor.h"
41
#include "hw/qdev-properties.h"
42
-#include "cpregs.h"
43
+#include "internals.h"
44
45
46
-#ifndef CONFIG_USER_ONLY
47
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
48
-{
49
- ARMCPU *cpu = env_archcpu(env);
50
-
51
- /* Number of cores is in [25:24]; otherwise we RAZ */
52
- return (cpu->core_count - 1) << 24;
53
-}
54
-#endif
55
-
56
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
57
-#ifndef CONFIG_USER_ONLY
58
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
59
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
60
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
61
- .writefn = arm_cp_write_ignore },
62
- { .name = "L2CTLR",
63
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
64
- .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
65
- .writefn = arm_cp_write_ignore },
66
-#endif
67
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
68
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
69
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
70
- { .name = "L2ECTLR",
71
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
72
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
73
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
74
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
75
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
76
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
77
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
78
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
- { .name = "CPUACTLR",
80
- .cp = 15, .opc1 = 0, .crm = 15,
81
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
82
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
83
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
84
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
85
- { .name = "CPUECTLR",
86
- .cp = 15, .opc1 = 1, .crm = 15,
87
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
88
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
89
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
90
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
91
- { .name = "CPUMERRSR",
92
- .cp = 15, .opc1 = 2, .crm = 15,
93
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
94
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
95
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
96
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
97
- { .name = "L2MERRSR",
98
- .cp = 15, .opc1 = 3, .crm = 15,
99
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
100
-};
101
-
102
static void aarch64_a57_initfn(Object *obj)
42
{
103
{
43
int index = flash - fiu->flash;
104
ARMCPU *cpu = ARM_CPU(obj);
44
105
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
45
@@ -XXX,XX +XXX,XX @@ static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
106
cpu->gic_num_lrs = 4;
107
cpu->gic_vpribits = 5;
108
cpu->gic_vprebits = 5;
109
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
110
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
46
}
111
}
47
112
48
/* Assert the chip select specified in the UMA Control/Status Register. */
113
static void aarch64_a53_initfn(Object *obj)
49
-static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id)
114
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
50
+static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id)
115
cpu->gic_num_lrs = 4;
51
{
116
cpu->gic_vpribits = 5;
52
trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id);
117
cpu->gic_vprebits = 5;
53
118
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
54
if (cs_id < s->cs_count) {
119
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
55
qemu_irq_lower(s->cs_lines[cs_id]);
56
+ s->active_cs = cs_id;
57
} else {
58
qemu_log_mask(LOG_GUEST_ERROR,
59
"%s: UMA to CS%d; this module has only %d chip selects",
60
DEVICE(s)->canonical_path, cs_id, s->cs_count);
61
- cs_id = -1;
62
+ s->active_cs = -1;
63
}
64
-
65
- s->active_cs = cs_id;
66
}
120
}
67
121
68
/* Deassert the currently active chip select. */
122
static void aarch64_a72_initfn(Object *obj)
69
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
123
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
70
NPCM7xxFIUFlash *f = opaque;
124
cpu->gic_num_lrs = 4;
71
NPCM7xxFIUState *fiu = f->fiu;
125
cpu->gic_vpribits = 5;
72
uint32_t dwr_cfg;
126
cpu->gic_vprebits = 5;
73
- int cs_id;
127
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
74
+ unsigned cs_id;
128
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
75
int i;
129
}
76
130
77
if (fiu->active_cs != -1) {
131
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
78
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
132
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
79
index XXXXXXX..XXXXXXX 100644
133
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/ssi/trace-events
134
--- a/target/arm/cpu_tcg.c
81
+++ b/hw/ssi/trace-events
135
+++ b/target/arm/cpu_tcg.c
82
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d"
136
@@ -XXX,XX +XXX,XX @@
83
npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
137
#endif
84
npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
138
#include "cpregs.h"
85
npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
139
86
-npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
140
+#ifndef CONFIG_USER_ONLY
87
+npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
141
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
142
+{
143
+ ARMCPU *cpu = env_archcpu(env);
144
+
145
+ /* Number of cores is in [25:24]; otherwise we RAZ */
146
+ return (cpu->core_count - 1) << 24;
147
+}
148
+
149
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
150
+ { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
151
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
152
+ .access = PL1_RW, .readfn = l2ctlr_read,
153
+ .writefn = arm_cp_write_ignore },
154
+ { .name = "L2CTLR",
155
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
156
+ .access = PL1_RW, .readfn = l2ctlr_read,
157
+ .writefn = arm_cp_write_ignore },
158
+ { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
159
+ .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
160
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
161
+ { .name = "L2ECTLR",
162
+ .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
163
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
164
+ { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
165
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
166
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
167
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
168
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
169
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
170
+ { .name = "CPUACTLR",
171
+ .cp = 15, .opc1 = 0, .crm = 15,
172
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
173
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
174
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
175
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
176
+ { .name = "CPUECTLR",
177
+ .cp = 15, .opc1 = 1, .crm = 15,
178
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
179
+ { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
180
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
181
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
182
+ { .name = "CPUMERRSR",
183
+ .cp = 15, .opc1 = 2, .crm = 15,
184
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
185
+ { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
186
+ .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
187
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
188
+ { .name = "L2MERRSR",
189
+ .cp = 15, .opc1 = 3, .crm = 15,
190
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
191
+};
192
+
193
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
194
+{
195
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
196
+}
197
+#endif /* !CONFIG_USER_ONLY */
198
+
199
/* CPU models. These are not needed for the AArch64 linux-user build. */
200
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
201
88
--
202
--
89
2.20.1
203
2.25.1
90
91
diff view generated by jsdifflib
New patch
[PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Instead of starting with cortex-a15 and adding v8 features to
4
a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
5
This fixes the long-standing to-do where we only enabled v8
6
features for user-only.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++-----------------
14
1 file changed, 92 insertions(+), 59 deletions(-)
15
16
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu_tcg.c
19
+++ b/target/arm/cpu_tcg.c
20
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
21
static void arm_max_initfn(Object *obj)
22
{
23
ARMCPU *cpu = ARM_CPU(obj);
24
+ uint32_t t;
25
26
- cortex_a15_initfn(obj);
27
+ /* aarch64_a57_initfn, advertising none of the aarch64 features */
28
+ cpu->dtb_compatible = "arm,cortex-a57";
29
+ set_feature(&cpu->env, ARM_FEATURE_V8);
30
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
31
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
32
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
33
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
34
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
35
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
36
+ cpu->midr = 0x411fd070;
37
+ cpu->revidr = 0x00000000;
38
+ cpu->reset_fpsid = 0x41034070;
39
+ cpu->isar.mvfr0 = 0x10110222;
40
+ cpu->isar.mvfr1 = 0x12111111;
41
+ cpu->isar.mvfr2 = 0x00000043;
42
+ cpu->ctr = 0x8444c004;
43
+ cpu->reset_sctlr = 0x00c50838;
44
+ cpu->isar.id_pfr0 = 0x00000131;
45
+ cpu->isar.id_pfr1 = 0x00011011;
46
+ cpu->isar.id_dfr0 = 0x03010066;
47
+ cpu->id_afr0 = 0x00000000;
48
+ cpu->isar.id_mmfr0 = 0x10101105;
49
+ cpu->isar.id_mmfr1 = 0x40000000;
50
+ cpu->isar.id_mmfr2 = 0x01260000;
51
+ cpu->isar.id_mmfr3 = 0x02102211;
52
+ cpu->isar.id_isar0 = 0x02101110;
53
+ cpu->isar.id_isar1 = 0x13112111;
54
+ cpu->isar.id_isar2 = 0x21232042;
55
+ cpu->isar.id_isar3 = 0x01112131;
56
+ cpu->isar.id_isar4 = 0x00011142;
57
+ cpu->isar.id_isar5 = 0x00011121;
58
+ cpu->isar.id_isar6 = 0;
59
+ cpu->isar.dbgdidr = 0x3516d000;
60
+ cpu->clidr = 0x0a200023;
61
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
62
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
63
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
64
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
65
66
- /* old-style VFP short-vector support */
67
- cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
68
+ /* Add additional features supported by QEMU */
69
+ t = cpu->isar.id_isar5;
70
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
71
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
72
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
73
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
74
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
75
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
76
+ cpu->isar.id_isar5 = t;
77
+
78
+ t = cpu->isar.id_isar6;
79
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
80
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
81
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
82
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
83
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
84
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
85
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
86
+ cpu->isar.id_isar6 = t;
87
+
88
+ t = cpu->isar.mvfr1;
89
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
90
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
91
+ cpu->isar.mvfr1 = t;
92
+
93
+ t = cpu->isar.mvfr2;
94
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
95
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
96
+ cpu->isar.mvfr2 = t;
97
+
98
+ t = cpu->isar.id_mmfr3;
99
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
100
+ cpu->isar.id_mmfr3 = t;
101
+
102
+ t = cpu->isar.id_mmfr4;
103
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
104
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
105
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
106
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
107
+ cpu->isar.id_mmfr4 = t;
108
+
109
+ t = cpu->isar.id_pfr0;
110
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
111
+ cpu->isar.id_pfr0 = t;
112
+
113
+ t = cpu->isar.id_pfr2;
114
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
115
+ cpu->isar.id_pfr2 = t;
116
117
#ifdef CONFIG_USER_ONLY
118
/*
119
- * We don't set these in system emulation mode for the moment,
120
- * since we don't correctly set (all of) the ID registers to
121
- * advertise them.
122
+ * Break with true ARMv8 and add back old-style VFP short-vector support.
123
+ * Only do this for user-mode, where -cpu max is the default, so that
124
+ * older v6 and v7 programs are more likely to work without adjustment.
125
*/
126
- set_feature(&cpu->env, ARM_FEATURE_V8);
127
- {
128
- uint32_t t;
129
-
130
- t = cpu->isar.id_isar5;
131
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
132
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
133
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
134
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
135
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
136
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
137
- cpu->isar.id_isar5 = t;
138
-
139
- t = cpu->isar.id_isar6;
140
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
141
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
142
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
143
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
144
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
145
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
146
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
147
- cpu->isar.id_isar6 = t;
148
-
149
- t = cpu->isar.mvfr1;
150
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
151
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
152
- cpu->isar.mvfr1 = t;
153
-
154
- t = cpu->isar.mvfr2;
155
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
156
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
157
- cpu->isar.mvfr2 = t;
158
-
159
- t = cpu->isar.id_mmfr3;
160
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
161
- cpu->isar.id_mmfr3 = t;
162
-
163
- t = cpu->isar.id_mmfr4;
164
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
165
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
166
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
167
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
168
- cpu->isar.id_mmfr4 = t;
169
-
170
- t = cpu->isar.id_pfr0;
171
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
172
- cpu->isar.id_pfr0 = t;
173
-
174
- t = cpu->isar.id_pfr2;
175
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
176
- cpu->isar.id_pfr2 = t;
177
- }
178
-#endif /* CONFIG_USER_ONLY */
179
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
180
+#endif
181
}
182
#endif /* !TARGET_AARCH64 */
183
184
--
185
2.25.1
diff view generated by jsdifflib
New patch
[PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We set this for qemu-system-aarch64, but failed to do so
4
for the strictly 32-bit emulation.
5
6
Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/cpu_tcg.c | 4 ++++
13
1 file changed, 4 insertions(+)
14
15
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu_tcg.c
18
+++ b/target/arm/cpu_tcg.c
19
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
20
t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
21
cpu->isar.id_pfr2 = t;
22
23
+ t = cpu->isar.id_dfr0;
24
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
25
+ cpu->isar.id_dfr0 = t;
26
+
27
#ifdef CONFIG_USER_ONLY
28
/*
29
* Break with true ARMv8 and add back old-style VFP short-vector support.
30
--
31
2.25.1
diff view generated by jsdifflib
New patch
[PULL 09/32] target/arm: Split out aa32_max_features
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Share the code to set AArch32 max features so that we no
4
longer have code drift between qemu{-system,}-{arm,aarch64}.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 2 +
12
target/arm/cpu64.c | 50 +-----------------
13
target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++-------------------
14
3 files changed, 65 insertions(+), 101 deletions(-)
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
19
+++ b/target/arm/internals.h
20
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
21
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
22
#endif
23
24
+void aa32_max_features(ARMCPU *cpu);
25
+
26
#endif
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu64.c
30
+++ b/target/arm/cpu64.c
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
32
{
33
ARMCPU *cpu = ARM_CPU(obj);
34
uint64_t t;
35
- uint32_t u;
36
37
if (kvm_enabled() || hvf_enabled()) {
38
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
40
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
41
cpu->isar.id_aa64zfr0 = t;
42
43
- /* Replicate the same data to the 32-bit id registers. */
44
- u = cpu->isar.id_isar5;
45
- u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
46
- u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
47
- u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
48
- u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
49
- u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
50
- u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
51
- cpu->isar.id_isar5 = u;
52
-
53
- u = cpu->isar.id_isar6;
54
- u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
55
- u = FIELD_DP32(u, ID_ISAR6, DP, 1);
56
- u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
57
- u = FIELD_DP32(u, ID_ISAR6, SB, 1);
58
- u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
59
- u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
60
- u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
61
- cpu->isar.id_isar6 = u;
62
-
63
- u = cpu->isar.id_pfr0;
64
- u = FIELD_DP32(u, ID_PFR0, DIT, 1);
65
- cpu->isar.id_pfr0 = u;
66
-
67
- u = cpu->isar.id_pfr2;
68
- u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
69
- cpu->isar.id_pfr2 = u;
70
-
71
- u = cpu->isar.id_mmfr3;
72
- u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
73
- cpu->isar.id_mmfr3 = u;
74
-
75
- u = cpu->isar.id_mmfr4;
76
- u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
77
- u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
78
- u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
79
- u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
80
- cpu->isar.id_mmfr4 = u;
81
-
82
t = cpu->isar.id_aa64dfr0;
83
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
84
cpu->isar.id_aa64dfr0 = t;
85
86
- u = cpu->isar.id_dfr0;
87
- u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
88
- cpu->isar.id_dfr0 = u;
89
-
90
- u = cpu->isar.mvfr1;
91
- u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
92
- u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
93
- cpu->isar.mvfr1 = u;
94
+ /* Replicate the same data to the 32-bit id registers. */
95
+ aa32_max_features(cpu);
96
97
#ifdef CONFIG_USER_ONLY
98
/*
99
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/cpu_tcg.c
102
+++ b/target/arm/cpu_tcg.c
103
@@ -XXX,XX +XXX,XX @@
104
#endif
105
#include "cpregs.h"
106
107
+
108
+/* Share AArch32 -cpu max features with AArch64. */
109
+void aa32_max_features(ARMCPU *cpu)
110
+{
111
+ uint32_t t;
112
+
113
+ /* Add additional features supported by QEMU */
114
+ t = cpu->isar.id_isar5;
115
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
116
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
117
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
118
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
119
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
120
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
121
+ cpu->isar.id_isar5 = t;
122
+
123
+ t = cpu->isar.id_isar6;
124
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
125
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
126
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
127
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
128
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
129
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
130
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
131
+ cpu->isar.id_isar6 = t;
132
+
133
+ t = cpu->isar.mvfr1;
134
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
135
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
136
+ cpu->isar.mvfr1 = t;
137
+
138
+ t = cpu->isar.mvfr2;
139
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
140
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
141
+ cpu->isar.mvfr2 = t;
142
+
143
+ t = cpu->isar.id_mmfr3;
144
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
145
+ cpu->isar.id_mmfr3 = t;
146
+
147
+ t = cpu->isar.id_mmfr4;
148
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
149
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
150
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
151
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
152
+ cpu->isar.id_mmfr4 = t;
153
+
154
+ t = cpu->isar.id_pfr0;
155
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
156
+ cpu->isar.id_pfr0 = t;
157
+
158
+ t = cpu->isar.id_pfr2;
159
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
160
+ cpu->isar.id_pfr2 = t;
161
+
162
+ t = cpu->isar.id_dfr0;
163
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
164
+ cpu->isar.id_dfr0 = t;
165
+}
166
+
167
#ifndef CONFIG_USER_ONLY
168
static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
169
{
170
@@ -XXX,XX +XXX,XX @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
171
static void arm_max_initfn(Object *obj)
172
{
173
ARMCPU *cpu = ARM_CPU(obj);
174
- uint32_t t;
175
176
/* aarch64_a57_initfn, advertising none of the aarch64 features */
177
cpu->dtb_compatible = "arm,cortex-a57";
178
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
179
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
180
define_cortex_a72_a57_a53_cp_reginfo(cpu);
181
182
- /* Add additional features supported by QEMU */
183
- t = cpu->isar.id_isar5;
184
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
185
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
186
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
187
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
188
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
189
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
190
- cpu->isar.id_isar5 = t;
191
-
192
- t = cpu->isar.id_isar6;
193
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
194
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
195
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
196
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
197
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
198
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
199
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
200
- cpu->isar.id_isar6 = t;
201
-
202
- t = cpu->isar.mvfr1;
203
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
204
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
205
- cpu->isar.mvfr1 = t;
206
-
207
- t = cpu->isar.mvfr2;
208
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
- cpu->isar.mvfr2 = t;
211
-
212
- t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
- cpu->isar.id_mmfr3 = t;
215
-
216
- t = cpu->isar.id_mmfr4;
217
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
218
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
219
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
220
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
221
- cpu->isar.id_mmfr4 = t;
222
-
223
- t = cpu->isar.id_pfr0;
224
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
225
- cpu->isar.id_pfr0 = t;
226
-
227
- t = cpu->isar.id_pfr2;
228
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
229
- cpu->isar.id_pfr2 = t;
230
-
231
- t = cpu->isar.id_dfr0;
232
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
233
- cpu->isar.id_dfr0 = t;
234
+ aa32_max_features(cpu);
235
236
#ifdef CONFIG_USER_ONLY
237
/*
238
--
239
2.25.1
diff view generated by jsdifflib
[PULL 12/12] target/arm: Make '-cpu max' have a 48-bit PA
[PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers
1
QEMU supports a 48-bit physical address range, but we don't currently
1
From: Richard Henderson <richard.henderson@linaro.org>
2
expose it in the '-cpu max' ID registers (you get the same range as
3
Cortex-A57, which is 44 bits).
4
2
5
Set the ID_AA64MMFR0.PARange field to indicate 48 bits.
3
Update the legacy feature names to the current names.
4
Provide feature names for id changes that were not marked.
5
Sort the field updates into increasing bitfield order.
6
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-10-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201001160116.18095-1-peter.maydell@linaro.org
10
---
11
---
11
target/arm/cpu64.c | 4 ++++
12
target/arm/cpu64.c | 100 +++++++++++++++++++++----------------------
12
1 file changed, 4 insertions(+)
13
target/arm/cpu_tcg.c | 48 ++++++++++-----------
14
2 files changed, 74 insertions(+), 74 deletions(-)
13
15
14
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu64.c
18
--- a/target/arm/cpu64.c
17
+++ b/target/arm/cpu64.c
19
+++ b/target/arm/cpu64.c
18
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
19
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
21
cpu->midr = t;
20
cpu->isar.id_aa64pfr1 = t;
22
21
23
t = cpu->isar.id_aa64isar0;
22
+ t = cpu->isar.id_aa64mmfr0;
24
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
23
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
25
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
24
+ cpu->isar.id_aa64mmfr0 = t;
26
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
25
+
27
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
26
t = cpu->isar.id_aa64mmfr1;
28
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
27
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
29
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
28
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
30
t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
31
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
32
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
33
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
34
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
35
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
36
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
37
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
38
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
39
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
40
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
41
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
42
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
43
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
44
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
45
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
46
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
47
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
48
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
49
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
50
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
51
cpu->isar.id_aa64isar0 = t;
52
53
t = cpu->isar.id_aa64isar1;
54
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
55
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
56
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
57
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
58
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
59
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
60
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
61
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
62
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
63
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
64
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
65
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
66
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
67
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
68
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
69
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
70
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
71
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
72
cpu->isar.id_aa64isar1 = t;
73
74
t = cpu->isar.id_aa64pfr0;
75
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
76
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
77
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
78
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
79
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
80
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
81
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
82
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
83
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
84
cpu->isar.id_aa64pfr0 = t;
85
86
t = cpu->isar.id_aa64pfr1;
87
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
88
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
89
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
90
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
91
/*
92
* Begin with full support for MTE. This will be downgraded to MTE=0
93
* during realize if the board provides no tag memory, much like
94
* we do for EL2 with the virtualization=on property.
95
*/
96
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
97
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
98
cpu->isar.id_aa64pfr1 = t;
99
100
t = cpu->isar.id_aa64mmfr0;
101
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
102
cpu->isar.id_aa64mmfr0 = t;
103
104
t = cpu->isar.id_aa64mmfr1;
105
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
106
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
107
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
108
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
109
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
110
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
111
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
112
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
113
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
114
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
115
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
116
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
117
cpu->isar.id_aa64mmfr1 = t;
118
119
t = cpu->isar.id_aa64mmfr2;
120
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
121
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
122
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
123
- t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
124
- t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
125
- t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
126
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
127
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
128
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
129
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
130
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
131
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
132
cpu->isar.id_aa64mmfr2 = t;
133
134
t = cpu->isar.id_aa64zfr0;
135
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
136
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
137
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
138
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
139
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
140
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
141
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
142
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
143
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
144
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
145
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
146
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
147
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
148
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
149
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
150
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
151
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
152
cpu->isar.id_aa64zfr0 = t;
153
154
t = cpu->isar.id_aa64dfr0;
155
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
156
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
157
cpu->isar.id_aa64dfr0 = t;
158
159
/* Replicate the same data to the 32-bit id registers. */
160
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
161
index XXXXXXX..XXXXXXX 100644
162
--- a/target/arm/cpu_tcg.c
163
+++ b/target/arm/cpu_tcg.c
164
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
165
166
/* Add additional features supported by QEMU */
167
t = cpu->isar.id_isar5;
168
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
169
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
170
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
171
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
172
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
173
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
174
t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
175
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
176
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
177
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
178
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
179
cpu->isar.id_isar5 = t;
180
181
t = cpu->isar.id_isar6;
182
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
183
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
184
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
185
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
186
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
187
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
188
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
189
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
190
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
191
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
192
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
193
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
194
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
195
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
196
cpu->isar.id_isar6 = t;
197
198
t = cpu->isar.mvfr1;
199
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
200
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
201
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
202
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
203
cpu->isar.mvfr1 = t;
204
205
t = cpu->isar.mvfr2;
206
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
207
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
208
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
209
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
210
cpu->isar.mvfr2 = t;
211
212
t = cpu->isar.id_mmfr3;
213
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
214
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
215
cpu->isar.id_mmfr3 = t;
216
217
t = cpu->isar.id_mmfr4;
218
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
219
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
220
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
221
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
222
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
223
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
224
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
225
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/
226
cpu->isar.id_mmfr4 = t;
227
228
t = cpu->isar.id_pfr0;
229
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
230
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
231
cpu->isar.id_pfr0 = t;
232
233
t = cpu->isar.id_pfr2;
234
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
235
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
236
cpu->isar.id_pfr2 = t;
237
238
t = cpu->isar.id_dfr0;
239
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
240
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
241
cpu->isar.id_dfr0 = t;
242
}
243
29
--
244
--
30
2.20.1
245
2.25.1
31
32
diff view generated by jsdifflib
New patch
[PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
4
during arm_cpu_realizefn.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-11-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.c | 22 +++++++++++++---------
12
1 file changed, 13 insertions(+), 9 deletions(-)
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
19
*/
20
unset_feature(env, ARM_FEATURE_EL3);
21
22
- /* Disable the security extension feature bits in the processor feature
23
- * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
24
+ /*
25
+ * Disable the security extension feature bits in the processor
26
+ * feature registers as well.
27
*/
28
- cpu->isar.id_pfr1 &= ~0xf0;
29
- cpu->isar.id_aa64pfr0 &= ~0xf000;
30
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
31
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
32
+ ID_AA64PFR0, EL3, 0);
33
}
34
35
if (!cpu->has_el2) {
36
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
37
}
38
39
if (!arm_feature(env, ARM_FEATURE_EL2)) {
40
- /* Disable the hypervisor feature bits in the processor feature
41
- * registers if we don't have EL2. These are id_pfr1[15:12] and
42
- * id_aa64pfr0_el1[11:8].
43
+ /*
44
+ * Disable the hypervisor feature bits in the processor feature
45
+ * registers if we don't have EL2.
46
*/
47
- cpu->isar.id_aa64pfr0 &= ~0xf00;
48
- cpu->isar.id_pfr1 &= ~0xf000;
49
+ cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
50
+ ID_AA64PFR0, EL2, 0);
51
+ cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
52
+ ID_PFR1, VIRTUALIZATION, 0);
53
}
54
55
#ifndef CONFIG_USER_ONLY
56
--
57
2.25.1
diff view generated by jsdifflib
New patch
[PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The only portion of FEAT_Debugv8p2 that is relevant to QEMU
4
is CONTEXTIDR_EL2, which is also conditionally implemented
5
with FEAT_VHE. The rest of the debug extension concerns the
6
External debug interface, which is outside the scope of QEMU.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/system/arm/emulation.rst | 1 +
14
target/arm/cpu.c | 1 +
15
target/arm/cpu64.c | 1 +
16
target/arm/cpu_tcg.c | 2 ++
17
4 files changed, 5 insertions(+)
18
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
22
+++ b/docs/system/arm/emulation.rst
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
24
- FEAT_BTI (Branch Target Identification)
25
- FEAT_DIT (Data Independent Timing instructions)
26
- FEAT_DPB (DC CVAP instruction)
27
+- FEAT_Debugv8p2 (Debug changes for v8.2)
28
- FEAT_DotProd (Advanced SIMD dot product instructions)
29
- FEAT_FCMA (Floating-point complex number instructions)
30
- FEAT_FHM (Floating-point half-precision multiplication instructions)
31
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu.c
34
+++ b/target/arm/cpu.c
35
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
36
* feature registers as well.
37
*/
38
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
39
+ cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
40
cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
41
ID_AA64PFR0, EL3, 0);
42
}
43
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/cpu64.c
46
+++ b/target/arm/cpu64.c
47
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
48
cpu->isar.id_aa64zfr0 = t;
49
50
t = cpu->isar.id_aa64dfr0;
51
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
52
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
53
cpu->isar.id_aa64dfr0 = t;
54
55
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/cpu_tcg.c
58
+++ b/target/arm/cpu_tcg.c
59
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
60
cpu->isar.id_pfr2 = t;
61
62
t = cpu->isar.id_dfr0;
63
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
64
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
65
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
66
cpu->isar.id_dfr0 = t;
67
}
68
--
69
2.25.1
diff view generated by jsdifflib
New patch
[PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This extension concerns changes to the External Debug interface,
4
with Secure and Non-secure access to the debug registers, and all
5
of it is outside the scope of QEMU. Indicating support for this
6
is mandatory with FEAT_SEL2, which we do implement.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220506180242.216785-13-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/system/arm/emulation.rst | 1 +
14
target/arm/cpu64.c | 2 +-
15
target/arm/cpu_tcg.c | 4 ++--
16
3 files changed, 4 insertions(+), 3 deletions(-)
17
18
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
19
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/emulation.rst
21
+++ b/docs/system/arm/emulation.rst
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
23
- FEAT_DIT (Data Independent Timing instructions)
24
- FEAT_DPB (DC CVAP instruction)
25
- FEAT_Debugv8p2 (Debug changes for v8.2)
26
+- FEAT_Debugv8p4 (Debug changes for v8.4)
27
- FEAT_DotProd (Advanced SIMD dot product instructions)
28
- FEAT_FCMA (Floating-point complex number instructions)
29
- FEAT_FHM (Floating-point half-precision multiplication instructions)
30
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu64.c
33
+++ b/target/arm/cpu64.c
34
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
35
cpu->isar.id_aa64zfr0 = t;
36
37
t = cpu->isar.id_aa64dfr0;
38
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */
39
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
40
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */
41
cpu->isar.id_aa64dfr0 = t;
42
43
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/cpu_tcg.c
46
+++ b/target/arm/cpu_tcg.c
47
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
48
cpu->isar.id_pfr2 = t;
49
50
t = cpu->isar.id_dfr0;
51
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */
52
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */
53
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
54
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
55
t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */
56
cpu->isar.id_dfr0 = t;
57
}
58
--
59
2.25.1
diff view generated by jsdifflib
[PULL 07/12] target/arm/kvm: Make uncalled stubs explicitly unreachable
[PULL 14/32] target/arm: Add minimal RAS registers
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When we compile without KVM support !defined(CONFIG_KVM) we generate
3
Add only the system registers required to implement zero error
4
stubs for functions that the linker will still encounter. Sometimes
4
records. This means that all values for ERRSELR are out of range,
5
these stubs can be executed safely and are placed in paths where they
5
which means that it and all of the indexed error record registers
6
get executed with or without KVM. Other functions should never be
6
need not be implemented.
7
called without KVM. Those functions should be guarded by kvm_enabled(),
8
but should also be robust to refactoring mistakes. Putting a
9
g_assert_not_reached() in the function should help. Additionally,
10
the g_assert_not_reached() calls may actually help the linker remove
11
some code.
12
7
13
We remove the stubs for kvm_arm_get/put_virtual_time(), as they aren't
8
Add the EL2 registers required for injecting virtual SError.
14
necessary at all - the only caller is in kvm.c
15
9
16
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Andrew Jones <drjones@redhat.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
Message-id: 20201001061718.101915-3-drjones@redhat.com
12
Message-id: 20220506180242.216785-14-richard.henderson@linaro.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
14
---
21
target/arm/kvm_arm.h | 51 +++++++++++++++++++++++++++-----------------
15
target/arm/cpu.h | 5 +++
22
1 file changed, 32 insertions(+), 19 deletions(-)
16
target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++
17
2 files changed, 89 insertions(+)
23
18
24
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/kvm_arm.h
21
--- a/target/arm/cpu.h
27
+++ b/target/arm/kvm_arm.h
22
+++ b/target/arm/cpu.h
28
@@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
23
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
29
24
uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
30
#else
25
uint64_t gcr_el1;
31
26
uint64_t rgsr_el1;
32
-static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
27
+
33
-{
28
+ /* Minimal RAS registers */
34
- /*
29
+ uint64_t disr_el1;
35
- * This should never actually be called in the "not KVM" case,
30
+ uint64_t vdisr_el2;
36
- * but set up the fields to indicate an error anyway.
31
+ uint64_t vsesr_el2;
37
- */
32
} cp15;
38
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
33
39
- cpu->host_cpu_probe_failed = true;
34
struct {
40
-}
35
diff --git a/target/arm/helper.c b/target/arm/helper.c
41
-
36
index XXXXXXX..XXXXXXX 100644
42
-static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
37
--- a/target/arm/helper.c
43
-
38
+++ b/target/arm/helper.c
39
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
40
.access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
41
};
42
44
+/*
43
+/*
45
+ * It's safe to call these functions without KVM support.
44
+ * Check for traps to RAS registers, which are controlled
46
+ * They should either do nothing or return "not supported".
45
+ * by HCR_EL2.TERR and SCR_EL3.TERR.
47
+ */
46
+ */
48
static inline bool kvm_arm_aarch32_supported(void)
47
+static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri,
49
{
48
+ bool isread)
50
return false;
51
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void)
52
return false;
53
}
54
55
+/*
56
+ * These functions should never actually be called without KVM support.
57
+ */
58
+static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
59
+{
49
+{
60
+ g_assert_not_reached();
50
+ int el = arm_current_el(env);
51
+
52
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) {
53
+ return CP_ACCESS_TRAP_EL2;
54
+ }
55
+ if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) {
56
+ return CP_ACCESS_TRAP_EL3;
57
+ }
58
+ return CP_ACCESS_OK;
61
+}
59
+}
62
+
60
+
63
+static inline void kvm_arm_add_vcpu_properties(Object *obj)
61
+static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri)
64
+{
62
+{
65
+ g_assert_not_reached();
63
+ int el = arm_current_el(env);
64
+
65
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
66
+ return env->cp15.vdisr_el2;
67
+ }
68
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
69
+ return 0; /* RAZ/WI */
70
+ }
71
+ return env->cp15.disr_el1;
66
+}
72
+}
67
+
73
+
68
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
74
+static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
69
{
70
- return -ENOENT;
71
+ g_assert_not_reached();
72
}
73
74
static inline int kvm_arm_vgic_probe(void)
75
{
76
- return 0;
77
+ g_assert_not_reached();
78
}
79
80
-static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
81
-static inline void kvm_arm_pmu_init(CPUState *cs) {}
82
+static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
83
+{
75
+{
84
+ g_assert_not_reached();
76
+ int el = arm_current_el(env);
85
+}
77
+
86
78
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) {
87
-static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
79
+ env->cp15.vdisr_el2 = val;
88
+static inline void kvm_arm_pmu_init(CPUState *cs)
80
+ return;
89
+{
81
+ }
90
+ g_assert_not_reached();
82
+ if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) {
83
+ return; /* RAZ/WI */
84
+ }
85
+ env->cp15.disr_el1 = val;
91
+}
86
+}
92
+
87
+
93
+static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
88
+/*
94
+{
89
+ * Minimal RAS implementation with no Error Records.
95
+ g_assert_not_reached();
90
+ * Which means that all of the Error Record registers:
96
+}
91
+ * ERXADDR_EL1
97
92
+ * ERXCTLR_EL1
98
-static inline void kvm_arm_get_virtual_time(CPUState *cs) {}
93
+ * ERXFR_EL1
99
-static inline void kvm_arm_put_virtual_time(CPUState *cs) {}
94
+ * ERXMISC0_EL1
100
#endif
95
+ * ERXMISC1_EL1
101
96
+ * ERXMISC2_EL1
102
static inline const char *gic_class_name(void)
97
+ * ERXMISC3_EL1
98
+ * ERXPFGCDN_EL1 (RASv1p1)
99
+ * ERXPFGCTL_EL1 (RASv1p1)
100
+ * ERXPFGF_EL1 (RASv1p1)
101
+ * ERXSTATUS_EL1
102
+ * and
103
+ * ERRSELR_EL1
104
+ * may generate UNDEFINED, which is the effect we get by not
105
+ * listing them at all.
106
+ */
107
+static const ARMCPRegInfo minimal_ras_reginfo[] = {
108
+ { .name = "DISR_EL1", .state = ARM_CP_STATE_BOTH,
109
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 1,
110
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.disr_el1),
111
+ .readfn = disr_read, .writefn = disr_write, .raw_writefn = raw_write },
112
+ { .name = "ERRIDR_EL1", .state = ARM_CP_STATE_BOTH,
113
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 0,
114
+ .access = PL1_R, .accessfn = access_terr,
115
+ .type = ARM_CP_CONST, .resetvalue = 0 },
116
+ { .name = "VDISR_EL2", .state = ARM_CP_STATE_BOTH,
117
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 1, .opc2 = 1,
118
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vdisr_el2) },
119
+ { .name = "VSESR_EL2", .state = ARM_CP_STATE_BOTH,
120
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 3,
121
+ .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
122
+};
123
+
124
/* Return the exception level to which exceptions should be taken
125
* via SVEAccessTrap. If an exception should be routed through
126
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
127
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
128
if (cpu_isar_feature(aa64_ssbs, cpu)) {
129
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
130
}
131
+ if (cpu_isar_feature(any_ras, cpu)) {
132
+ define_arm_cp_regs(cpu, minimal_ras_reginfo);
133
+ }
134
135
if (cpu_isar_feature(aa64_vh, cpu) ||
136
cpu_isar_feature(aa64_debugv8p2, cpu)) {
103
--
137
--
104
2.20.1
138
2.25.1
105
106
diff view generated by jsdifflib
New patch
[PULL 15/32] target/arm: Enable SCR and HCR bits for RAS
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Enable writes to the TERR and TEA bits when RAS is enabled.
4
These bits are otherwise RES0.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-15-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
19
}
20
valid_mask &= ~SCR_NET;
21
22
+ if (cpu_isar_feature(aa64_ras, cpu)) {
23
+ valid_mask |= SCR_TERR;
24
+ }
25
if (cpu_isar_feature(aa64_lor, cpu)) {
26
valid_mask |= SCR_TLOR;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
29
}
30
} else {
31
valid_mask &= ~(SCR_RW | SCR_ST);
32
+ if (cpu_isar_feature(aa32_ras, cpu)) {
33
+ valid_mask |= SCR_TERR;
34
+ }
35
}
36
37
if (!arm_feature(env, ARM_FEATURE_EL2)) {
38
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
39
if (cpu_isar_feature(aa64_vh, cpu)) {
40
valid_mask |= HCR_E2H;
41
}
42
+ if (cpu_isar_feature(aa64_ras, cpu)) {
43
+ valid_mask |= HCR_TERR | HCR_TEA;
44
+ }
45
if (cpu_isar_feature(aa64_lor, cpu)) {
46
valid_mask |= HCR_TLOR;
47
}
48
--
49
2.25.1
diff view generated by jsdifflib
[PULL 11/12] hw/arm/virt: Implement kvm-steal-time
[PULL 16/32] target/arm: Implement virtual SError exceptions
1
From: Andrew Jones <drjones@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We add the kvm-steal-time CPU property and implement it for machvirt.
3
Virtual SError exceptions are raised by setting HCR_EL2.VSE,
4
A tiny bit of refactoring was also done to allow pmu and pvtime to
4
and are routed to EL1 just like other virtual exceptions.
5
use the same vcpu device helper functions.
6
5
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201001061718.101915-7-drjones@redhat.com
8
Message-id: 20220506180242.216785-16-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
docs/system/arm/cpu-features.rst | 11 ++++++
11
target/arm/cpu.h | 2 ++
13
include/hw/arm/virt.h | 5 +++
12
target/arm/internals.h | 8 ++++++++
14
target/arm/cpu.h | 4 ++
13
target/arm/syndrome.h | 5 +++++
15
target/arm/kvm_arm.h | 43 +++++++++++++++++++++
14
target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++-
16
hw/arm/virt.c | 43 +++++++++++++++++++--
15
target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++-
17
target/arm/cpu.c | 8 ++++
16
5 files changed, 91 insertions(+), 2 deletions(-)
18
target/arm/kvm.c | 16 ++++++++
19
target/arm/kvm64.c | 64 +++++++++++++++++++++++++++++---
20
target/arm/monitor.c | 2 +-
21
tests/qtest/arm-cpu-features.c | 25 +++++++++++--
22
10 files changed, 208 insertions(+), 13 deletions(-)
23
17
24
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
25
index XXXXXXX..XXXXXXX 100644
26
--- a/docs/system/arm/cpu-features.rst
27
+++ b/docs/system/arm/cpu-features.rst
28
@@ -XXX,XX +XXX,XX @@ the list of KVM VCPU features and their descriptions.
29
adjustment, also restoring the legacy (pre-5.0)
30
behavior.
31
32
+ kvm-steal-time Since v5.2, kvm-steal-time is enabled by
33
+ default when KVM is enabled, the feature is
34
+ supported, and the guest is 64-bit.
35
+
36
+ When kvm-steal-time is enabled a 64-bit guest
37
+ can account for time its CPUs were not running
38
+ due to the host not scheduling the corresponding
39
+ VCPU threads. The accounting statistics may
40
+ influence the guest scheduler behavior and/or be
41
+ exposed to the guest userspace.
42
+
43
SVE CPU Properties
44
==================
45
46
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/include/hw/arm/virt.h
49
+++ b/include/hw/arm/virt.h
50
@@ -XXX,XX +XXX,XX @@
51
52
#define PPI(irq) ((irq) + 16)
53
54
+/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
55
+#define PVTIME_SIZE_PER_CPU 64
56
+
57
enum {
58
VIRT_FLASH,
59
VIRT_MEM,
60
@@ -XXX,XX +XXX,XX @@ enum {
61
VIRT_PCDIMM_ACPI,
62
VIRT_ACPI_GED,
63
VIRT_NVDIMM_ACPI,
64
+ VIRT_PVTIME,
65
VIRT_LOWMEMMAP_LAST,
66
};
67
68
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
69
bool no_highmem_ecam;
70
bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
71
bool kvm_no_adjvtime;
72
+ bool no_kvm_steal_time;
73
bool acpi_expose_flash;
74
};
75
76
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
77
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/cpu.h
20
--- a/target/arm/cpu.h
79
+++ b/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
80
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@
81
#include "hw/registerfields.h"
23
#define EXCP_LSERR 21 /* v8M LSERR SecureFault */
82
#include "cpu-qom.h"
24
#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
83
#include "exec/cpu-defs.h"
25
#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
84
+#include "qapi/qapi-types-common.h"
26
+#define EXCP_VSERR 24
85
27
/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
86
/* ARM processors have a weak memory model */
28
87
#define TCG_GUEST_DEFAULT_MO (0)
29
#define ARMV7M_EXCP_RESET 1
88
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
30
@@ -XXX,XX +XXX,XX @@ enum {
89
bool kvm_vtime_dirty;
31
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
90
uint64_t kvm_vtime;
32
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
91
33
#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
92
+ /* KVM steal time */
34
+#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
93
+ OnOffAuto kvm_steal_time;
35
94
+
36
/* The usual mapping for an AArch64 system register to its AArch32
95
/* Uniprocessor system with MP extensions */
37
* counterpart is for the 32 bit world to have access to the lower
96
bool mp_is_up;
38
diff --git a/target/arm/internals.h b/target/arm/internals.h
97
39
index XXXXXXX..XXXXXXX 100644
98
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
40
--- a/target/arm/internals.h
99
index XXXXXXX..XXXXXXX 100644
41
+++ b/target/arm/internals.h
100
--- a/target/arm/kvm_arm.h
42
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
101
+++ b/target/arm/kvm_arm.h
102
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
103
*/
43
*/
104
void kvm_arm_add_vcpu_properties(Object *obj);
44
void arm_cpu_update_vfiq(ARMCPU *cpu);
105
45
106
+/**
46
+/**
107
+ * kvm_arm_steal_time_finalize:
47
+ * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit
108
+ * @cpu: ARMCPU for which to finalize kvm-steal-time
109
+ * @errp: Pointer to Error* for error propagation
110
+ *
48
+ *
111
+ * Validate the kvm-steal-time property selection and set its default
49
+ * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request,
112
+ * based on KVM support and guest configuration.
50
+ * following a change to the HCR_EL2.VSE bit.
113
+ */
51
+ */
114
+void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp);
52
+void arm_cpu_update_vserr(ARMCPU *cpu);
115
+
116
+/**
117
+ * kvm_arm_steal_time_supported:
118
+ *
119
+ * Returns: true if KVM can enable steal time reporting
120
+ * and false otherwise.
121
+ */
122
+bool kvm_arm_steal_time_supported(void);
123
+
53
+
124
/**
54
/**
125
* kvm_arm_aarch32_supported:
55
* arm_mmu_idx_el:
126
*
56
* @env: The cpu environment
127
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void);
57
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
128
58
index XXXXXXX..XXXXXXX 100644
129
void kvm_arm_pmu_set_irq(CPUState *cs, int irq);
59
--- a/target/arm/syndrome.h
130
void kvm_arm_pmu_init(CPUState *cs);
60
+++ b/target/arm/syndrome.h
131
+
61
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pcalignment(void)
132
+/**
62
return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
133
+ * kvm_arm_pvtime_init:
63
}
134
+ * @cs: CPUState
64
135
+ * @ipa: Per-vcpu guest physical base address of the pvtime structures
65
+static inline uint32_t syn_serror(uint32_t extra)
136
+ *
137
+ * Initializes PVTIME for the VCPU, setting the PVTIME IPA to @ipa.
138
+ */
139
+void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa);
140
+
141
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
142
143
#else
144
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void)
145
return false;
146
}
147
148
+static inline bool kvm_arm_steal_time_supported(void)
149
+{
66
+{
150
+ return false;
67
+ return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra;
151
+}
68
+}
152
+
69
+
153
/*
70
#endif /* TARGET_ARM_SYNDROME_H */
154
* These functions should never actually be called without KVM support.
155
*/
156
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_init(CPUState *cs)
157
g_assert_not_reached();
158
}
159
160
+static inline void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
161
+{
162
+ g_assert_not_reached();
163
+}
164
+
165
+static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
166
+{
167
+ g_assert_not_reached();
168
+}
169
+
170
static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
171
{
172
g_assert_not_reached();
173
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
174
index XXXXXXX..XXXXXXX 100644
175
--- a/hw/arm/virt.c
176
+++ b/hw/arm/virt.c
177
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
178
[VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
179
[VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
180
[VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
181
+ [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
182
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
183
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
184
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
185
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
186
* virt_cpu_post_init() must be called after the CPUs have
187
* been realized and the GIC has been created.
188
*/
189
-static void virt_cpu_post_init(VirtMachineState *vms)
190
+static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
191
+ MemoryRegion *sysmem)
192
{
193
- bool aarch64, pmu;
194
+ bool aarch64, pmu, steal_time;
195
CPUState *cpu;
196
197
aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
198
pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
199
+ steal_time = object_property_get_bool(OBJECT(first_cpu),
200
+ "kvm-steal-time", NULL);
201
202
if (kvm_enabled()) {
203
+ hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
204
+ hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
205
+
206
+ if (steal_time) {
207
+ MemoryRegion *pvtime = g_new(MemoryRegion, 1);
208
+ hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
209
+
210
+ /* The memory region size must be a multiple of host page size. */
211
+ pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
212
+
213
+ if (pvtime_size > pvtime_reg_size) {
214
+ error_report("pvtime requires a %ld byte memory region for "
215
+ "%d CPUs, but only %ld has been reserved",
216
+ pvtime_size, max_cpus, pvtime_reg_size);
217
+ exit(1);
218
+ }
219
+
220
+ memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
221
+ memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
222
+ }
223
+
224
CPU_FOREACH(cpu) {
225
if (pmu) {
226
assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
227
@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms)
228
}
229
kvm_arm_pmu_init(cpu);
230
}
231
+ if (steal_time) {
232
+ kvm_arm_pvtime_init(cpu, pvtime_reg_base +
233
+ cpu->cpu_index * PVTIME_SIZE_PER_CPU);
234
+ }
235
}
236
} else {
237
if (aarch64 && vms->highmem) {
238
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
239
object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
240
}
241
242
+ if (vmc->no_kvm_steal_time &&
243
+ object_property_find(cpuobj, "kvm-steal-time")) {
244
+ object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
245
+ }
246
+
247
if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
248
object_property_set_bool(cpuobj, "pmu", false, NULL);
249
}
250
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
251
252
create_gic(vms);
253
254
- virt_cpu_post_init(vms);
255
+ virt_cpu_post_init(vms, possible_cpus->len, sysmem);
256
257
fdt_add_pmu_nodes(vms);
258
259
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 2)
260
261
static void virt_machine_5_1_options(MachineClass *mc)
262
{
263
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
264
+
265
virt_machine_5_2_options(mc);
266
compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
267
+ vmc->no_kvm_steal_time = true;
268
}
269
DEFINE_VIRT_MACHINE(5, 1)
270
271
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
71
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
272
index XXXXXXX..XXXXXXX 100644
72
index XXXXXXX..XXXXXXX 100644
273
--- a/target/arm/cpu.c
73
--- a/target/arm/cpu.c
274
+++ b/target/arm/cpu.c
74
+++ b/target/arm/cpu.c
275
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
75
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_has_work(CPUState *cs)
276
return;
76
return (cpu->power_state != PSCI_OFF)
77
&& cs->interrupt_request &
78
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
79
- | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
80
+ | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
81
| CPU_INTERRUPT_EXITTB);
82
}
83
84
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
85
return false;
277
}
86
}
278
}
87
return !(env->daif & PSTATE_I);
279
+
88
+ case EXCP_VSERR:
280
+ if (kvm_enabled()) {
89
+ if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
281
+ kvm_arm_steal_time_finalize(cpu, &local_err);
90
+ /* VIRQs are only taken when hypervized. */
282
+ if (local_err != NULL) {
91
+ return false;
283
+ error_propagate(errp, local_err);
92
+ }
284
+ return;
93
+ return !(env->daif & PSTATE_A);
94
default:
95
g_assert_not_reached();
96
}
97
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
98
goto found;
99
}
100
}
101
+ if (interrupt_request & CPU_INTERRUPT_VSERR) {
102
+ excp_idx = EXCP_VSERR;
103
+ target_el = 1;
104
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
105
+ cur_el, secure, hcr_el2)) {
106
+ /* Taking a virtual abort clears HCR_EL2.VSE */
107
+ env->cp15.hcr_el2 &= ~HCR_VSE;
108
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
109
+ goto found;
285
+ }
110
+ }
286
+ }
111
+ }
287
}
112
return false;
288
113
289
static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
114
found:
290
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
115
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu)
291
index XXXXXXX..XXXXXXX 100644
116
}
292
--- a/target/arm/kvm.c
117
}
293
+++ b/target/arm/kvm.c
118
294
@@ -XXX,XX +XXX,XX @@ static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp)
119
+void arm_cpu_update_vserr(ARMCPU *cpu)
295
ARM_CPU(obj)->kvm_adjvtime = !value;
296
}
297
298
+static bool kvm_steal_time_get(Object *obj, Error **errp)
299
+{
120
+{
300
+ return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF;
121
+ /*
301
+}
122
+ * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
302
+
123
+ */
303
+static void kvm_steal_time_set(Object *obj, bool value, Error **errp)
124
+ CPUARMState *env = &cpu->env;
304
+{
125
+ CPUState *cs = CPU(cpu);
305
+ ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
126
+
306
+}
127
+ bool new_state = env->cp15.hcr_el2 & HCR_VSE;
307
+
128
+
308
/* KVM VCPU properties should be prefixed with "kvm-". */
129
+ if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
309
void kvm_arm_add_vcpu_properties(Object *obj)
130
+ if (new_state) {
310
{
131
+ cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
311
@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj)
132
+ } else {
312
"the virtual counter. VM stopped time "
133
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
313
"will be counted.");
134
+ }
314
}
315
+
316
+ cpu->kvm_steal_time = ON_OFF_AUTO_AUTO;
317
+ object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get,
318
+ kvm_steal_time_set);
319
+ object_property_set_description(obj, "kvm-steal-time",
320
+ "Set off to disable KVM steal time.");
321
}
322
323
bool kvm_arm_pmu_supported(void)
324
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
325
index XXXXXXX..XXXXXXX 100644
326
--- a/target/arm/kvm64.c
327
+++ b/target/arm/kvm64.c
328
@@ -XXX,XX +XXX,XX @@
329
#include <linux/kvm.h>
330
331
#include "qemu-common.h"
332
+#include "qapi/error.h"
333
#include "cpu.h"
334
#include "qemu/timer.h"
335
#include "qemu/error-report.h"
336
@@ -XXX,XX +XXX,XX @@ static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
337
return NULL;
338
}
339
340
-static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr)
341
+static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr,
342
+ const char *name)
343
{
344
int err;
345
346
err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);
347
if (err != 0) {
348
- error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err));
349
+ error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err));
350
return false;
351
}
352
353
err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr);
354
if (err != 0) {
355
- error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err));
356
+ error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err));
357
return false;
358
}
359
360
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
361
if (!ARM_CPU(cs)->has_pmu) {
362
return;
363
}
364
- if (!kvm_arm_pmu_set_attr(cs, &attr)) {
365
+ if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
366
error_report("failed to init PMU");
367
abort();
368
}
369
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
370
if (!ARM_CPU(cs)->has_pmu) {
371
return;
372
}
373
- if (!kvm_arm_pmu_set_attr(cs, &attr)) {
374
+ if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
375
error_report("failed to set irq for PMU");
376
abort();
377
}
378
}
379
380
+void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
381
+{
382
+ struct kvm_device_attr attr = {
383
+ .group = KVM_ARM_VCPU_PVTIME_CTRL,
384
+ .attr = KVM_ARM_VCPU_PVTIME_IPA,
385
+ .addr = (uint64_t)&ipa,
386
+ };
387
+
388
+ if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) {
389
+ return;
390
+ }
391
+ if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) {
392
+ error_report("failed to init PVTIME IPA");
393
+ abort();
394
+ }
135
+ }
395
+}
136
+}
396
+
137
+
397
static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
138
#ifndef CONFIG_USER_ONLY
139
static void arm_cpu_set_irq(void *opaque, int irq, int level)
398
{
140
{
399
uint64_t ret;
141
diff --git a/target/arm/helper.c b/target/arm/helper.c
400
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
142
index XXXXXXX..XXXXXXX 100644
401
return true;
143
--- a/target/arm/helper.c
402
}
144
+++ b/target/arm/helper.c
403
145
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
404
+void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
146
}
405
+{
147
}
406
+ bool has_steal_time = kvm_arm_steal_time_supported();
148
407
+
149
- /* External aborts are not possible in QEMU so A bit is always clear */
408
+ if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) {
150
+ if (hcr_el2 & HCR_AMO) {
409
+ if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
151
+ if (cs->interrupt_request & CPU_INTERRUPT_VSERR) {
410
+ cpu->kvm_steal_time = ON_OFF_AUTO_OFF;
152
+ ret |= CPSR_A;
411
+ } else {
153
+ }
412
+ cpu->kvm_steal_time = ON_OFF_AUTO_ON;
154
+ }
413
+ }
155
+
414
+ } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) {
156
return ret;
415
+ if (!has_steal_time) {
157
}
416
+ error_setg(errp, "'kvm-steal-time' cannot be enabled "
158
417
+ "on this host");
159
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
418
+ return;
160
g_assert(qemu_mutex_iothread_locked());
419
+ } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
161
arm_cpu_update_virq(cpu);
162
arm_cpu_update_vfiq(cpu);
163
+ arm_cpu_update_vserr(cpu);
164
}
165
166
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
167
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs)
168
[EXCP_LSERR] = "v8M LSERR UsageFault",
169
[EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault",
170
[EXCP_DIVBYZERO] = "v7M DIVBYZERO UsageFault",
171
+ [EXCP_VSERR] = "Virtual SERR",
172
};
173
174
if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
175
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
176
mask = CPSR_A | CPSR_I | CPSR_F;
177
offset = 4;
178
break;
179
+ case EXCP_VSERR:
180
+ {
420
+ /*
181
+ /*
421
+ * DEN0057A chapter 2 says "This specification only covers
182
+ * Note that this is reported as a data abort, but the DFAR
422
+ * systems in which the Execution state of the hypervisor
183
+ * has an UNKNOWN value. Construct the SError syndrome from
423
+ * as well as EL1 of virtual machines is AArch64.". And,
184
+ * AET and ExT fields.
424
+ * to ensure that, the smc/hvc calls are only specified as
425
+ * smc64/hvc64.
426
+ */
185
+ */
427
+ error_setg(errp, "'kvm-steal-time' cannot be enabled "
186
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal, };
428
+ "for AArch32 guests");
187
+
429
+ return;
188
+ if (extended_addresses_enabled(env)) {
430
+ }
189
+ env->exception.fsr = arm_fi_to_lfsc(&fi);
431
+ }
190
+ } else {
432
+}
191
+ env->exception.fsr = arm_fi_to_sfsc(&fi);
433
+
192
+ }
434
bool kvm_arm_aarch32_supported(void)
193
+ env->exception.fsr |= env->cp15.vsesr_el2 & 0xd000;
435
{
194
+ A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
436
return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT);
195
+ qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n",
437
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(void)
196
+ env->exception.fsr);
438
return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
197
+
439
}
198
+ new_mode = ARM_CPU_MODE_ABT;
440
199
+ addr = 0x10;
441
+bool kvm_arm_steal_time_supported(void)
200
+ mask = CPSR_A | CPSR_I;
442
+{
201
+ offset = 8;
443
+ return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME);
202
+ }
444
+}
203
+ break;
445
+
204
case EXCP_SMC:
446
QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
205
new_mode = ARM_CPU_MODE_MON;
447
206
addr = 0x08;
448
void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
207
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
449
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
208
case EXCP_VFIQ:
450
index XXXXXXX..XXXXXXX 100644
209
addr += 0x100;
451
--- a/target/arm/monitor.c
210
break;
452
+++ b/target/arm/monitor.c
211
+ case EXCP_VSERR:
453
@@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = {
212
+ addr += 0x180;
454
"sve128", "sve256", "sve384", "sve512",
213
+ /* Construct the SError syndrome from IDS and ISS fields. */
455
"sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
214
+ env->exception.syndrome = syn_serror(env->cp15.vsesr_el2 & 0x1ffffff);
456
"sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
215
+ env->cp15.esr_el[new_el] = env->exception.syndrome;
457
- "kvm-no-adjvtime",
216
+ break;
458
+ "kvm-no-adjvtime", "kvm-steal-time",
217
default:
459
NULL
218
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
460
};
219
}
461
462
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
463
index XXXXXXX..XXXXXXX 100644
464
--- a/tests/qtest/arm-cpu-features.c
465
+++ b/tests/qtest/arm-cpu-features.c
466
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
467
assert_set_feature(qts, "max", "pmu", true);
468
469
assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
470
+ assert_has_not_feature(qts, "max", "kvm-steal-time");
471
472
if (g_str_equal(qtest_get_arch(), "aarch64")) {
473
assert_has_feature_enabled(qts, "max", "aarch64");
474
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
475
assert_set_feature(qts, "host", "kvm-no-adjvtime", false);
476
477
if (g_str_equal(qtest_get_arch(), "aarch64")) {
478
+ bool kvm_supports_steal_time;
479
bool kvm_supports_sve;
480
char max_name[8], name[8];
481
uint32_t max_vq, vq;
482
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
483
QDict *resp;
484
char *error;
485
486
+ assert_error(qts, "cortex-a15",
487
+ "We cannot guarantee the CPU type 'cortex-a15' works "
488
+ "with KVM on this host", NULL);
489
+
490
assert_has_feature_enabled(qts, "host", "aarch64");
491
492
/* Enabling and disabling pmu should always work. */
493
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
494
assert_set_feature(qts, "host", "pmu", false);
495
assert_set_feature(qts, "host", "pmu", true);
496
497
- assert_error(qts, "cortex-a15",
498
- "We cannot guarantee the CPU type 'cortex-a15' works "
499
- "with KVM on this host", NULL);
500
-
501
+ /*
502
+ * Some features would be enabled by default, but they're disabled
503
+ * because this instance of KVM doesn't support them. Test that the
504
+ * features are present, and, when enabled, issue further tests.
505
+ */
506
+ assert_has_feature(qts, "host", "kvm-steal-time");
507
assert_has_feature(qts, "host", "sve");
508
+
509
resp = do_query_no_props(qts, "host");
510
+ kvm_supports_steal_time = resp_get_feature(resp, "kvm-steal-time");
511
kvm_supports_sve = resp_get_feature(resp, "sve");
512
vls = resp_get_sve_vls(resp);
513
qobject_unref(resp);
514
515
+ if (kvm_supports_steal_time) {
516
+ /* If we have steal-time then we should be able to toggle it. */
517
+ assert_set_feature(qts, "host", "kvm-steal-time", false);
518
+ assert_set_feature(qts, "host", "kvm-steal-time", true);
519
+ }
520
+
521
if (kvm_supports_sve) {
522
g_assert(vls != 0);
523
max_vq = 64 - __builtin_clzll(vls);
524
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
525
assert_has_not_feature(qts, "host", "aarch64");
526
assert_has_not_feature(qts, "host", "pmu");
527
assert_has_not_feature(qts, "host", "sve");
528
+ assert_has_not_feature(qts, "host", "kvm-steal-time");
529
}
530
531
qtest_quit(qts);
532
--
220
--
533
2.20.1
221
2.25.1
534
535
diff view generated by jsdifflib
New patch
[PULL 17/32] target/arm: Implement ESB instruction
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Check for and defer any pending virtual SError.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220506180242.216785-17-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.h | 1 +
11
target/arm/a32.decode | 16 ++++++++------
12
target/arm/t32.decode | 18 ++++++++--------
13
target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-a64.c | 17 +++++++++++++++
15
target/arm/translate.c | 23 ++++++++++++++++++++
16
6 files changed, 103 insertions(+), 15 deletions(-)
17
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
21
+++ b/target/arm/helper.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(wfe, void, env)
23
DEF_HELPER_1(yield, void, env)
24
DEF_HELPER_1(pre_hvc, void, env)
25
DEF_HELPER_2(pre_smc, void, env, i32)
26
+DEF_HELPER_1(vesb, void, env)
27
28
DEF_HELPER_3(cpsr_write, void, env, i32, i32)
29
DEF_HELPER_2(cpsr_write_eret, void, env, i32)
30
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/a32.decode
33
+++ b/target/arm/a32.decode
34
@@ -XXX,XX +XXX,XX @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn
35
36
{
37
{
38
- YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
39
- WFE ---- 0011 0010 0000 1111 ---- 0000 0010
40
- WFI ---- 0011 0010 0000 1111 ---- 0000 0011
41
+ [
42
+ YIELD ---- 0011 0010 0000 1111 ---- 0000 0001
43
+ WFE ---- 0011 0010 0000 1111 ---- 0000 0010
44
+ WFI ---- 0011 0010 0000 1111 ---- 0000 0011
45
46
- # TODO: Implement SEV, SEVL; may help SMP performance.
47
- # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
48
- # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
49
+ # TODO: Implement SEV, SEVL; may help SMP performance.
50
+ # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
51
+ # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
52
+
53
+ ESB ---- 0011 0010 0000 1111 ---- 0001 0000
54
+ ]
55
56
# The canonical nop ends in 00000000, but the whole of the
57
# rest of the space executes as nop if otherwise unsupported.
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
63
[
64
# Hints, and CPS
65
{
66
- YIELD 1111 0011 1010 1111 1000 0000 0000 0001
67
- WFE 1111 0011 1010 1111 1000 0000 0000 0010
68
- WFI 1111 0011 1010 1111 1000 0000 0000 0011
69
+ [
70
+ YIELD 1111 0011 1010 1111 1000 0000 0000 0001
71
+ WFE 1111 0011 1010 1111 1000 0000 0000 0010
72
+ WFI 1111 0011 1010 1111 1000 0000 0000 0011
73
74
- # TODO: Implement SEV, SEVL; may help SMP performance.
75
- # SEV 1111 0011 1010 1111 1000 0000 0000 0100
76
- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
77
+ # TODO: Implement SEV, SEVL; may help SMP performance.
78
+ # SEV 1111 0011 1010 1111 1000 0000 0000 0100
79
+ # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
80
81
- # For M-profile minimal-RAS ESB can be a NOP, which is the
82
- # default behaviour since it is in the hint space.
83
- # ESB 1111 0011 1010 1111 1000 0000 0001 0000
84
+ ESB 1111 0011 1010 1111 1000 0000 0001 0000
85
+ ]
86
87
# The canonical nop ends in 0000 0000, but the whole rest
88
# of the space is "reserved hint, behaves as nop".
89
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
90
index XXXXXXX..XXXXXXX 100644
91
--- a/target/arm/op_helper.c
92
+++ b/target/arm/op_helper.c
93
@@ -XXX,XX +XXX,XX @@ void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
94
access_type, mmu_idx, ra);
95
}
96
}
97
+
98
+/*
99
+ * This function corresponds to AArch64.vESBOperation().
100
+ * Note that the AArch32 version is not functionally different.
101
+ */
102
+void HELPER(vesb)(CPUARMState *env)
103
+{
104
+ /*
105
+ * The EL2Enabled() check is done inside arm_hcr_el2_eff,
106
+ * and will return HCR_EL2.VSE == 0, so nothing happens.
107
+ */
108
+ uint64_t hcr = arm_hcr_el2_eff(env);
109
+ bool enabled = !(hcr & HCR_TGE) && (hcr & HCR_AMO);
110
+ bool pending = enabled && (hcr & HCR_VSE);
111
+ bool masked = (env->daif & PSTATE_A);
112
+
113
+ /* If VSE pending and masked, defer the exception. */
114
+ if (pending && masked) {
115
+ uint32_t syndrome;
116
+
117
+ if (arm_el_is_aa64(env, 1)) {
118
+ /* Copy across IDS and ISS from VSESR. */
119
+ syndrome = env->cp15.vsesr_el2 & 0x1ffffff;
120
+ } else {
121
+ ARMMMUFaultInfo fi = { .type = ARMFault_AsyncExternal };
122
+
123
+ if (extended_addresses_enabled(env)) {
124
+ syndrome = arm_fi_to_lfsc(&fi);
125
+ } else {
126
+ syndrome = arm_fi_to_sfsc(&fi);
127
+ }
128
+ /* Copy across AET and ExT from VSESR. */
129
+ syndrome |= env->cp15.vsesr_el2 & 0xd000;
130
+ }
131
+
132
+ /* Set VDISR_EL2.A along with the syndrome. */
133
+ env->cp15.vdisr_el2 = syndrome | (1u << 31);
134
+
135
+ /* Clear pending virtual SError */
136
+ env->cp15.hcr_el2 &= ~HCR_VSE;
137
+ cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR);
138
+ }
139
+}
140
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
141
index XXXXXXX..XXXXXXX 100644
142
--- a/target/arm/translate-a64.c
143
+++ b/target/arm/translate-a64.c
144
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
145
gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
146
}
147
break;
148
+ case 0b10000: /* ESB */
149
+ /* Without RAS, we must implement this as NOP. */
150
+ if (dc_isar_feature(aa64_ras, s)) {
151
+ /*
152
+ * QEMU does not have a source of physical SErrors,
153
+ * so we are only concerned with virtual SErrors.
154
+ * The pseudocode in the ARM for this case is
155
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
156
+ * AArch64.vESBOperation();
157
+ * Most of the condition can be evaluated at translation time.
158
+ * Test for EL2 present, and defer test for SEL2 to runtime.
159
+ */
160
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
161
+ gen_helper_vesb(cpu_env);
162
+ }
163
+ }
164
+ break;
165
case 0b11000: /* PACIAZ */
166
if (s->pauth_active) {
167
gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
168
diff --git a/target/arm/translate.c b/target/arm/translate.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/arm/translate.c
171
+++ b/target/arm/translate.c
172
@@ -XXX,XX +XXX,XX @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)
173
return true;
174
}
175
176
+static bool trans_ESB(DisasContext *s, arg_ESB *a)
177
+{
178
+ /*
179
+ * For M-profile, minimal-RAS ESB can be a NOP.
180
+ * Without RAS, we must implement this as NOP.
181
+ */
182
+ if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s)) {
183
+ /*
184
+ * QEMU does not have a source of physical SErrors,
185
+ * so we are only concerned with virtual SErrors.
186
+ * The pseudocode in the ARM for this case is
187
+ * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
188
+ * AArch32.vESBOperation();
189
+ * Most of the condition can be evaluated at translation time.
190
+ * Test for EL2 present, and defer test for SEL2 to runtime.
191
+ */
192
+ if (s->current_el <= 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) {
193
+ gen_helper_vesb(cpu_env);
194
+ }
195
+ }
196
+ return true;
197
+}
198
+
199
static bool trans_NOP(DisasContext *s, arg_NOP *a)
200
{
201
return true;
202
--
203
2.25.1
diff view generated by jsdifflib
New patch
[PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220506180242.216785-18-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
docs/system/arm/emulation.rst | 1 +
9
target/arm/cpu64.c | 1 +
10
target/arm/cpu_tcg.c | 1 +
11
3 files changed, 3 insertions(+)
12
13
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
index XXXXXXX..XXXXXXX 100644
15
--- a/docs/system/arm/emulation.rst
16
+++ b/docs/system/arm/emulation.rst
17
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
- FEAT_PMULL (PMULL, PMULL2 instructions)
19
- FEAT_PMUv3p1 (PMU Extensions v3.1)
20
- FEAT_PMUv3p4 (PMU Extensions v3.4)
21
+- FEAT_RAS (Reliability, availability, and serviceability)
22
- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)
23
- FEAT_RNG (Random number generator)
24
- FEAT_SB (Speculation Barrier)
25
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/cpu64.c
28
+++ b/target/arm/cpu64.c
29
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
30
t = cpu->isar.id_aa64pfr0;
31
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
32
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
33
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */
34
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
35
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
36
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
37
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu_tcg.c
40
+++ b/target/arm/cpu_tcg.c
41
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
42
43
t = cpu->isar.id_pfr0;
44
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
45
+ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
46
cpu->isar.id_pfr0 = t;
47
48
t = cpu->isar.id_pfr2;
49
--
50
2.25.1
diff view generated by jsdifflib
New patch
[PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This feature is AArch64 only, and applies to physical SErrors,
4
which QEMU does not implement, thus the feature is a nop.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-19-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/emulation.rst | 1 +
12
target/arm/cpu64.c | 1 +
13
2 files changed, 2 insertions(+)
14
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
18
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
21
- FEAT_HPDS (Hierarchical permission disables)
22
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
23
+- FEAT_IESB (Implicit error synchronization event)
24
- FEAT_JSCVT (JavaScript conversion instructions)
25
- FEAT_LOR (Limited ordering regions)
26
- FEAT_LPA (Large Physical Address space)
27
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/cpu64.c
30
+++ b/target/arm/cpu64.c
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
32
t = cpu->isar.id_aa64mmfr2;
33
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
34
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
35
+ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
36
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
37
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
38
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
39
--
40
2.25.1
diff view generated by jsdifflib
New patch
[PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This extension concerns branch speculation, which TCG does
4
not implement. Thus we can trivially enable this feature.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/emulation.rst | 1 +
12
target/arm/cpu64.c | 1 +
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
15
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
19
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
- FEAT_BBM at level 2 (Translation table break-before-make levels)
22
- FEAT_BF16 (AArch64 BFloat16 instructions)
23
- FEAT_BTI (Branch Target Identification)
24
+- FEAT_CSV2 (Cache speculation variant 2)
25
- FEAT_DIT (Data Independent Timing instructions)
26
- FEAT_DPB (DC CVAP instruction)
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu64.c
31
+++ b/target/arm/cpu64.c
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
33
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
34
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
35
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
37
cpu->isar.id_aa64pfr0 = t;
38
39
t = cpu->isar.id_aa64pfr1;
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu_tcg.c
43
+++ b/target/arm/cpu_tcg.c
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
45
cpu->isar.id_mmfr4 = t;
46
47
t = cpu->isar.id_pfr0;
48
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
49
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
50
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
51
cpu->isar.id_pfr0 = t;
52
--
53
2.25.1
diff view generated by jsdifflib
New patch
[PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
There is no branch prediction in TCG, therefore there is no
4
need to actually include the context number into the predictor.
5
Therefore all we need to do is add the state for SCXTNUM_ELx.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-21-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 3 ++
13
target/arm/cpu.h | 16 +++++++++
14
target/arm/cpu.c | 5 +++
15
target/arm/cpu64.c | 3 +-
16
target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++-
17
5 files changed, 86 insertions(+), 2 deletions(-)
18
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
21
--- a/docs/system/arm/emulation.rst
22
+++ b/docs/system/arm/emulation.rst
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
24
- FEAT_BF16 (AArch64 BFloat16 instructions)
25
- FEAT_BTI (Branch Target Identification)
26
- FEAT_CSV2 (Cache speculation variant 2)
27
+- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
28
+- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
29
+- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
30
- FEAT_DIT (Data Independent Timing instructions)
31
- FEAT_DPB (DC CVAP instruction)
32
- FEAT_Debugv8p2 (Debug changes for v8.2)
33
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/cpu.h
36
+++ b/target/arm/cpu.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
38
ARMPACKey apdb;
39
ARMPACKey apga;
40
} keys;
41
+
42
+ uint64_t scxtnum_el[4];
43
#endif
44
45
#if defined(CONFIG_USER_ONLY)
46
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
47
#define SCTLR_WXN (1U << 19)
48
#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
49
#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
50
+#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
51
#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
52
#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
53
#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
54
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
55
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
56
}
57
58
+static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
59
+{
60
+ int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
61
+ if (key >= 2) {
62
+ return true; /* FEAT_CSV2_2 */
63
+ }
64
+ if (key == 1) {
65
+ key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
66
+ return key >= 2; /* FEAT_CSV2_1p2 */
67
+ }
68
+ return false;
69
+}
70
+
71
static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
72
{
73
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
74
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/cpu.c
77
+++ b/target/arm/cpu.c
78
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
79
*/
80
env->cp15.gcr_el1 = 0x1ffff;
81
}
82
+ /*
83
+ * Disable access to SCXTNUM_EL0 from CSV2_1p2.
84
+ * This is not yet exposed from the Linux kernel in any way.
85
+ */
86
+ env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
87
#else
88
/* Reset into the highest available EL */
89
if (arm_feature(env, ARM_FEATURE_EL3)) {
90
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/cpu64.c
93
+++ b/target/arm/cpu64.c
94
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
95
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
96
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
97
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
98
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
99
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
100
cpu->isar.id_aa64pfr0 = t;
101
102
t = cpu->isar.id_aa64pfr1;
103
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
104
* we do for EL2 with the virtualization=on property.
105
*/
106
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
107
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
108
cpu->isar.id_aa64pfr1 = t;
109
110
t = cpu->isar.id_aa64mmfr0;
111
diff --git a/target/arm/helper.c b/target/arm/helper.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/target/arm/helper.c
114
+++ b/target/arm/helper.c
115
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
116
if (cpu_isar_feature(aa64_mte, cpu)) {
117
valid_mask |= SCR_ATA;
118
}
119
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
120
+ valid_mask |= SCR_ENSCXT;
121
+ }
122
} else {
123
valid_mask &= ~(SCR_RW | SCR_ST);
124
if (cpu_isar_feature(aa32_ras, cpu)) {
125
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
126
if (cpu_isar_feature(aa64_mte, cpu)) {
127
valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5;
128
}
129
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
130
+ valid_mask |= HCR_ENSCXT;
131
+ }
132
}
133
134
/* Clear RES0 bits. */
135
@@ -XXX,XX +XXX,XX @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
136
{ K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
137
"TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
138
139
+ { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
140
+ "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
141
+ isar_feature_aa64_scxtnum },
142
+
143
/* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
144
/* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
145
};
146
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = {
147
},
148
};
149
150
-#endif
151
+static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri,
152
+ bool isread)
153
+{
154
+ uint64_t hcr = arm_hcr_el2_eff(env);
155
+ int el = arm_current_el(env);
156
+
157
+ if (el == 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) {
158
+ if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) {
159
+ if (hcr & HCR_TGE) {
160
+ return CP_ACCESS_TRAP_EL2;
161
+ }
162
+ return CP_ACCESS_TRAP;
163
+ }
164
+ } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) {
165
+ return CP_ACCESS_TRAP_EL2;
166
+ }
167
+ if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) {
168
+ return CP_ACCESS_TRAP_EL2;
169
+ }
170
+ if (el < 3
171
+ && arm_feature(env, ARM_FEATURE_EL3)
172
+ && !(env->cp15.scr_el3 & SCR_ENSCXT)) {
173
+ return CP_ACCESS_TRAP_EL3;
174
+ }
175
+ return CP_ACCESS_OK;
176
+}
177
+
178
+static const ARMCPRegInfo scxtnum_reginfo[] = {
179
+ { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64,
180
+ .opc0 = 3, .opc1 = 3, .crn = 13, .crm = 0, .opc2 = 7,
181
+ .access = PL0_RW, .accessfn = access_scxtnum,
182
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) },
183
+ { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64,
184
+ .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 7,
185
+ .access = PL1_RW, .accessfn = access_scxtnum,
186
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) },
187
+ { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64,
188
+ .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 7,
189
+ .access = PL2_RW, .accessfn = access_scxtnum,
190
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) },
191
+ { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64,
192
+ .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 7,
193
+ .access = PL3_RW,
194
+ .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) },
195
+};
196
+#endif /* TARGET_AARCH64 */
197
198
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
199
bool isread)
200
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
201
define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
202
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
203
}
204
+
205
+ if (cpu_isar_feature(aa64_scxtnum, cpu)) {
206
+ define_arm_cp_regs(cpu, scxtnum_reginfo);
207
+ }
208
#endif
209
210
if (cpu_isar_feature(any_predinv, cpu)) {
211
--
212
2.25.1
diff view generated by jsdifflib
New patch
[PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This extension concerns cache speculation, which TCG does
4
not implement. Thus we can trivially enable this feature.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220506180242.216785-22-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/emulation.rst | 1 +
12
target/arm/cpu64.c | 1 +
13
target/arm/cpu_tcg.c | 1 +
14
3 files changed, 3 insertions(+)
15
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
19
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
24
+- FEAT_CSV3 (Cache speculation variant 3)
25
- FEAT_DIT (Data Independent Timing instructions)
26
- FEAT_DPB (DC CVAP instruction)
27
- FEAT_Debugv8p2 (Debug changes for v8.2)
28
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu64.c
31
+++ b/target/arm/cpu64.c
32
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
33
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
34
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
35
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
36
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
37
cpu->isar.id_aa64pfr0 = t;
38
39
t = cpu->isar.id_aa64pfr1;
40
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu_tcg.c
43
+++ b/target/arm/cpu_tcg.c
44
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
45
cpu->isar.id_pfr0 = t;
46
47
t = cpu->isar.id_pfr2;
48
+ t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
49
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
50
cpu->isar.id_pfr2 = t;
51
52
--
53
2.25.1
diff view generated by jsdifflib
New patch
[PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This extension concerns not merging memory access, which TCG does
4
not implement. Thus we can trivially enable this feature.
5
Add a comment to handle_hint for the DGH instruction, but no code.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220506180242.216785-23-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 1 +
13
target/arm/cpu64.c | 1 +
14
target/arm/translate-a64.c | 1 +
15
3 files changed, 3 insertions(+)
16
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
18
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/arm/emulation.rst
20
+++ b/docs/system/arm/emulation.rst
21
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
22
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
23
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
24
- FEAT_CSV3 (Cache speculation variant 3)
25
+- FEAT_DGH (Data gathering hint)
26
- FEAT_DIT (Data Independent Timing instructions)
27
- FEAT_DPB (DC CVAP instruction)
28
- FEAT_Debugv8p2 (Debug changes for v8.2)
29
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/cpu64.c
32
+++ b/target/arm/cpu64.c
33
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
34
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
35
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
36
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
37
+ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
38
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
39
cpu->isar.id_aa64isar1 = t;
40
41
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/translate-a64.c
44
+++ b/target/arm/translate-a64.c
45
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
46
break;
47
case 0b00100: /* SEV */
48
case 0b00101: /* SEVL */
49
+ case 0b00110: /* DGH */
50
/* we treat all as NOP at least for now */
51
break;
52
case 0b00111: /* XPACLRI */
53
--
54
2.25.1
diff view generated by jsdifflib
[PULL 04/12] hw/arm/sbsa-ref : allocate IRQs for SMMUv3
[PULL 24/32] target/arm: Define cortex-a76
1
From: Graeme Gregory <graeme@nuviainc.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Original commit did not allocate IRQs for the SMMUv3 in the irqmap
3
Enable the a76 for virt and sbsa board use.
4
effectively using irq 0->3 (shared with other devices). Assuming
5
original intent was to allocate unique IRQs then add an allocation
6
to the irqmap.
7
4
8
Fixes: e9fdf453240 ("hw/arm: Add arm SBSA reference machine, devices part")
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
7
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Message-id: 20201007100732.4103790-3-graeme@nuviainc.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
9
---
15
hw/arm/sbsa-ref.c | 1 +
10
docs/system/arm/virt.rst | 1 +
16
1 file changed, 1 insertion(+)
11
hw/arm/sbsa-ref.c | 1 +
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
17
15
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/virt.rst
19
+++ b/docs/system/arm/virt.rst
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
21
- ``cortex-a53`` (64-bit)
22
- ``cortex-a57`` (64-bit)
23
- ``cortex-a72`` (64-bit)
24
+- ``cortex-a76`` (64-bit)
25
- ``a64fx`` (64-bit)
26
- ``host`` (with KVM only)
27
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
18
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
19
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/sbsa-ref.c
30
--- a/hw/arm/sbsa-ref.c
21
+++ b/hw/arm/sbsa-ref.c
31
+++ b/hw/arm/sbsa-ref.c
22
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
32
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
23
[SBSA_SECURE_UART_MM] = 9,
33
static const char * const valid_cpus[] = {
24
[SBSA_AHCI] = 10,
34
ARM_CPU_TYPE_NAME("cortex-a57"),
25
[SBSA_EHCI] = 11,
35
ARM_CPU_TYPE_NAME("cortex-a72"),
26
+ [SBSA_SMMU] = 12, /* ... to 15 */
36
+ ARM_CPU_TYPE_NAME("cortex-a76"),
37
ARM_CPU_TYPE_NAME("max"),
27
};
38
};
28
39
29
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a53"),
46
ARM_CPU_TYPE_NAME("cortex-a57"),
47
ARM_CPU_TYPE_NAME("cortex-a72"),
48
+ ARM_CPU_TYPE_NAME("cortex-a76"),
49
ARM_CPU_TYPE_NAME("a64fx"),
50
ARM_CPU_TYPE_NAME("host"),
51
ARM_CPU_TYPE_NAME("max"),
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
57
define_cortex_a72_a57_a53_cp_reginfo(cpu);
58
}
59
60
+static void aarch64_a76_initfn(Object *obj)
61
+{
62
+ ARMCPU *cpu = ARM_CPU(obj);
63
+
64
+ cpu->dtb_compatible = "arm,cortex-a76";
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
73
+
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
75
+ cpu->clidr = 0x82000023;
76
+ cpu->ctr = 0x8444C004;
77
+ cpu->dcz_blocksize = 4;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0b1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.18 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
110
+
111
+ /* From B2.93 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
123
+}
124
+
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
126
{
127
/*
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
129
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
130
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
131
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
132
+ { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
133
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
134
{ .name = "max", .initfn = aarch64_max_initfn },
135
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
30
--
136
--
31
2.20.1
137
2.25.1
32
33
diff view generated by jsdifflib
[PULL 03/12] hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
[PULL 25/32] target/arm: Define neoverse-n1
1
From: Graeme Gregory <graeme@nuviainc.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
SMMUv3 has an error in a previous patch where an i was transposed to a 1
3
Enable the n1 for virt and sbsa board use.
4
meaning interrupts would not have been correctly assigned to the SMMUv3
5
instance.
6
4
7
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state")
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20220506180242.216785-25-richard.henderson@linaro.org
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 20201007100732.4103790-2-graeme@nuviainc.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
hw/arm/sbsa-ref.c | 2 +-
10
docs/system/arm/virt.rst | 1 +
15
1 file changed, 1 insertion(+), 1 deletion(-)
11
hw/arm/sbsa-ref.c | 1 +
12
hw/arm/virt.c | 1 +
13
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
14
4 files changed, 69 insertions(+)
16
15
16
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/virt.rst
19
+++ b/docs/system/arm/virt.rst
20
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
21
- ``cortex-a76`` (64-bit)
22
- ``a64fx`` (64-bit)
23
- ``host`` (with KVM only)
24
+- ``neoverse-n1`` (64-bit)
25
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
26
27
Note that the default is ``cortex-a15``, so for an AArch64 guest you must
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
28
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
18
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/sbsa-ref.c
30
--- a/hw/arm/sbsa-ref.c
20
+++ b/hw/arm/sbsa-ref.c
31
+++ b/hw/arm/sbsa-ref.c
21
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
32
@@ -XXX,XX +XXX,XX @@ static const char * const valid_cpus[] = {
22
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
33
ARM_CPU_TYPE_NAME("cortex-a57"),
23
for (i = 0; i < NUM_SMMU_IRQS; i++) {
34
ARM_CPU_TYPE_NAME("cortex-a72"),
24
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
35
ARM_CPU_TYPE_NAME("cortex-a76"),
25
- qdev_get_gpio_in(sms->gic, irq + 1));
36
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
26
+ qdev_get_gpio_in(sms->gic, irq + i));
37
ARM_CPU_TYPE_NAME("max"),
27
}
38
};
39
40
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/virt.c
43
+++ b/hw/arm/virt.c
44
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
45
ARM_CPU_TYPE_NAME("cortex-a72"),
46
ARM_CPU_TYPE_NAME("cortex-a76"),
47
ARM_CPU_TYPE_NAME("a64fx"),
48
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
49
ARM_CPU_TYPE_NAME("host"),
50
ARM_CPU_TYPE_NAME("max"),
51
};
52
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu64.c
55
+++ b/target/arm/cpu64.c
56
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
57
cpu->isar.mvfr2 = 0x00000043;
28
}
58
}
29
59
60
+static void aarch64_neoverse_n1_initfn(Object *obj)
61
+{
62
+ ARMCPU *cpu = ARM_CPU(obj);
63
+
64
+ cpu->dtb_compatible = "arm,neoverse-n1";
65
+ set_feature(&cpu->env, ARM_FEATURE_V8);
66
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
67
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
68
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
69
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
70
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
71
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
72
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
73
+
74
+ /* Ordered by B2.4 AArch64 registers by functional group */
75
+ cpu->clidr = 0x82000023;
76
+ cpu->ctr = 0x8444c004;
77
+ cpu->dcz_blocksize = 4;
78
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
79
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
80
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
81
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
82
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
83
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
84
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
85
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
86
+ cpu->id_afr0 = 0x00000000;
87
+ cpu->isar.id_dfr0 = 0x04010088;
88
+ cpu->isar.id_isar0 = 0x02101110;
89
+ cpu->isar.id_isar1 = 0x13112111;
90
+ cpu->isar.id_isar2 = 0x21232042;
91
+ cpu->isar.id_isar3 = 0x01112131;
92
+ cpu->isar.id_isar4 = 0x00010142;
93
+ cpu->isar.id_isar5 = 0x01011121;
94
+ cpu->isar.id_isar6 = 0x00000010;
95
+ cpu->isar.id_mmfr0 = 0x10201105;
96
+ cpu->isar.id_mmfr1 = 0x40000000;
97
+ cpu->isar.id_mmfr2 = 0x01260000;
98
+ cpu->isar.id_mmfr3 = 0x02122211;
99
+ cpu->isar.id_mmfr4 = 0x00021110;
100
+ cpu->isar.id_pfr0 = 0x10010131;
101
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
102
+ cpu->isar.id_pfr2 = 0x00000011;
103
+ cpu->midr = 0x414fd0c1; /* r4p1 */
104
+ cpu->revidr = 0;
105
+
106
+ /* From B2.23 CCSIDR_EL1 */
107
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
108
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
109
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
110
+
111
+ /* From B2.98 SCTLR_EL3 */
112
+ cpu->reset_sctlr = 0x30c50838;
113
+
114
+ /* From B4.23 ICH_VTR_EL2 */
115
+ cpu->gic_num_lrs = 4;
116
+ cpu->gic_vpribits = 5;
117
+ cpu->gic_vprebits = 5;
118
+
119
+ /* From B5.1 AdvSIMD AArch64 register summary */
120
+ cpu->isar.mvfr0 = 0x10110222;
121
+ cpu->isar.mvfr1 = 0x13211111;
122
+ cpu->isar.mvfr2 = 0x00000043;
123
+}
124
+
125
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
126
{
127
/*
128
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
129
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
130
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
131
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
132
+ { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
133
{ .name = "max", .initfn = aarch64_max_initfn },
134
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
135
{ .name = "host", .initfn = aarch64_host_initfn },
30
--
136
--
31
2.20.1
137
2.25.1
32
33
diff view generated by jsdifflib
[PULL 02/12] hw/arm/fsl-imx25: Fix a typo
[PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
The sbsa-ref machine is continuously evolving. Some of the changes we
4
Message-id: 20201002080935.1660005-1-f4bug@amsat.org
4
want to make in the near future, to align with real components (e.g.
5
the GIC-700), will break compatibility for existing firmware.
6
7
Introduce two new properties to the DT generated on machine generation:
8
- machine-version-major
9
To be incremented when a platform change makes the machine
10
incompatible with existing firmware.
11
- machine-version-minor
12
To be incremented when functionality is added to the machine
13
without causing incompatibility with existing firmware.
14
to be reset to 0 when machine-version-major is incremented.
15
16
This versioning scheme is *neither*:
17
- A QEMU versioned machine type; a given version of QEMU will emulate
18
a given version of the platform.
19
- A reflection of level of SBSA (now SystemReady SR) support provided.
20
21
The version will increment on guest-visible functional changes only,
22
akin to a revision ID register found on a physical platform.
23
24
These properties are both introduced with the value 0.
25
(Hence, a machine where the DT is lacking these nodes is equivalent
26
to version 0.0.)
27
28
Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
29
Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com
30
Cc: Peter Maydell <peter.maydell@linaro.org>
31
Cc: Radoslaw Biernacki <rad@semihalf.com>
32
Cc: Cédric Le Goater <clg@kaod.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
35
---
8
include/hw/arm/fsl-imx25.h | 2 +-
36
hw/arm/sbsa-ref.c | 14 ++++++++++++++
9
1 file changed, 1 insertion(+), 1 deletion(-)
37
1 file changed, 14 insertions(+)
10
38
11
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
39
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
12
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/arm/fsl-imx25.h
41
--- a/hw/arm/sbsa-ref.c
14
+++ b/include/hw/arm/fsl-imx25.h
42
+++ b/hw/arm/sbsa-ref.c
15
@@ -XXX,XX +XXX,XX @@ struct FslIMX25State {
43
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SBSAMachineState *sms)
16
* 0xBB00_0000 0xBB00_0FFF 4 Kbytes NAND flash main area buffer
44
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
17
* 0xBB00_1000 0xBB00_11FF 512 B NAND flash spare area buffer
45
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
18
* 0xBB00_1200 0xBB00_1DFF 3 Kbytes Reserved
46
19
- * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control regisers
47
+ /*
20
+ * 0xBB00_1E00 0xBB00_1FFF 512 B NAND flash control registers
48
+ * This versioning scheme is for informing platform fw only. It is neither:
21
* 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
49
+ * - A QEMU versioned machine type; a given version of QEMU will emulate
22
* 0xC000_0000 0xFFFF_FFFF 1024 Mbytes Reserved
50
+ * a given version of the platform.
23
*/
51
+ * - A reflection of level of SBSA (now SystemReady SR) support provided.
52
+ *
53
+ * machine-version-major: updated when changes breaking fw compatibility
54
+ * are introduced.
55
+ * machine-version-minor: updated when features are added that don't break
56
+ * fw compatibility.
57
+ */
58
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0);
59
+ qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0);
60
+
61
if (ms->numa_state->have_numa_distance) {
62
int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
63
uint32_t *matrix = g_malloc0(size);
24
--
64
--
25
2.20.1
65
2.25.1
26
66
27
67
diff view generated by jsdifflib
New patch
[PULL 27/32] qapi/machine.json: Add cluster-id
1
From: Gavin Shan <gshan@redhat.com>
1
2
3
This adds cluster-id in CPU instance properties, which will be used
4
by arm/virt machine. Besides, the cluster-id is also verified or
5
dumped in various spots:
6
7
* hw/core/machine.c::machine_set_cpu_numa_node() to associate
8
CPU with its NUMA node.
9
10
* hw/core/machine.c::machine_numa_finish_cpu_init() to record
11
CPU slots with no NUMA mapping set.
12
13
* hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump
14
cluster-id.
15
16
Signed-off-by: Gavin Shan <gshan@redhat.com>
17
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
18
Acked-by: Igor Mammedov <imammedo@redhat.com>
19
Message-id: 20220503140304.855514-2-gshan@redhat.com
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
qapi/machine.json | 6 ++++--
23
hw/core/machine-hmp-cmds.c | 4 ++++
24
hw/core/machine.c | 16 ++++++++++++++++
25
3 files changed, 24 insertions(+), 2 deletions(-)
26
27
diff --git a/qapi/machine.json b/qapi/machine.json
28
index XXXXXXX..XXXXXXX 100644
29
--- a/qapi/machine.json
30
+++ b/qapi/machine.json
31
@@ -XXX,XX +XXX,XX @@
32
# @node-id: NUMA node ID the CPU belongs to
33
# @socket-id: socket number within node/board the CPU belongs to
34
# @die-id: die number within socket the CPU belongs to (since 4.1)
35
-# @core-id: core number within die the CPU belongs to
36
+# @cluster-id: cluster number within die the CPU belongs to (since 7.1)
37
+# @core-id: core number within cluster the CPU belongs to
38
# @thread-id: thread number within core the CPU belongs to
39
#
40
-# Note: currently there are 5 properties that could be present
41
+# Note: currently there are 6 properties that could be present
42
# but management should be prepared to pass through other
43
# properties with device_add command to allow for future
44
# interface extension. This also requires the filed names to be kept in
45
@@ -XXX,XX +XXX,XX @@
46
'data': { '*node-id': 'int',
47
'*socket-id': 'int',
48
'*die-id': 'int',
49
+ '*cluster-id': 'int',
50
'*core-id': 'int',
51
'*thread-id': 'int'
52
}
53
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/core/machine-hmp-cmds.c
56
+++ b/hw/core/machine-hmp-cmds.c
57
@@ -XXX,XX +XXX,XX @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
58
if (c->has_die_id) {
59
monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
60
}
61
+ if (c->has_cluster_id) {
62
+ monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n",
63
+ c->cluster_id);
64
+ }
65
if (c->has_core_id) {
66
monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
67
}
68
diff --git a/hw/core/machine.c b/hw/core/machine.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/core/machine.c
71
+++ b/hw/core/machine.c
72
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
73
return;
74
}
75
76
+ if (props->has_cluster_id && !slot->props.has_cluster_id) {
77
+ error_setg(errp, "cluster-id is not supported");
78
+ return;
79
+ }
80
+
81
if (props->has_socket_id && !slot->props.has_socket_id) {
82
error_setg(errp, "socket-id is not supported");
83
return;
84
@@ -XXX,XX +XXX,XX @@ void machine_set_cpu_numa_node(MachineState *machine,
85
continue;
86
}
87
88
+ if (props->has_cluster_id &&
89
+ props->cluster_id != slot->props.cluster_id) {
90
+ continue;
91
+ }
92
+
93
if (props->has_die_id && props->die_id != slot->props.die_id) {
94
continue;
95
}
96
@@ -XXX,XX +XXX,XX @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
97
}
98
g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
99
}
100
+ if (cpu->props.has_cluster_id) {
101
+ if (s->len) {
102
+ g_string_append_printf(s, ", ");
103
+ }
104
+ g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id);
105
+ }
106
if (cpu->props.has_core_id) {
107
if (s->len) {
108
g_string_append_printf(s, ", ");
109
--
110
2.25.1
diff view generated by jsdifflib
[PULL 10/12] tests/qtest: Restore aarch64 arm-cpu-features test
[PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu()
1
From: Andrew Jones <drjones@redhat.com>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
arm-cpu-features got dropped from the AArch64 tests during the meson
3
The CPU topology isn't enabled on arm/virt machine yet, but we're
4
conversion shuffle.
4
going to do it in next patch. After the CPU topology is enabled by
5
next patch, "thread-id=1" becomes invalid because the CPU core is
6
preferred on arm/virt machine. It means these two CPUs have 0/1
7
as their core IDs, but their thread IDs are all 0. It will trigger
8
test failure as the following message indicates:
5
9
6
Signed-off-by: Andrew Jones <drjones@redhat.com>
10
[14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR
7
Message-id: 20201001061718.101915-6-drjones@redhat.com
11
1.48s killed by signal 6 SIGABRT
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
>>> G_TEST_DBUS_DAEMON=/home/gavin/sandbox/qemu.main/tests/dbus-vmstate-daemon.sh \
13
QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon \
14
QTEST_QEMU_BINARY=./qemu-system-aarch64 \
15
QTEST_QEMU_IMG=./qemu-img MALLOC_PERTURB_=83 \
16
/home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k
17
――――――――――――――――――――――――――――――――――――――――――――――
18
stderr:
19
qemu-system-aarch64: -numa cpu,node-id=0,thread-id=1: no match found
20
21
This fixes the issue by providing comprehensive SMP configurations
22
in aarch64_numa_cpu(). The SMP configurations aren't used before
23
the CPU topology is enabled in next patch.
24
25
Signed-off-by: Gavin Shan <gshan@redhat.com>
26
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
27
Message-id: 20220503140304.855514-3-gshan@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
29
---
11
tests/qtest/meson.build | 3 ++-
30
tests/qtest/numa-test.c | 3 ++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
31
1 file changed, 2 insertions(+), 1 deletion(-)
13
32
14
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
33
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
15
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/qtest/meson.build
35
--- a/tests/qtest/numa-test.c
17
+++ b/tests/qtest/meson.build
36
+++ b/tests/qtest/numa-test.c
18
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
37
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
19
(cpu != 'arm' ? ['bios-tables-test'] : []) + \
38
QTestState *qts;
20
(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \
39
g_autofree char *cli = NULL;
21
(config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \
40
22
- ['numa-test',
41
- cli = make_cli(data, "-machine smp.cpus=2 "
23
+ ['arm-cpu-features',
42
+ cli = make_cli(data, "-machine "
24
+ 'numa-test',
43
+ "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
25
'boot-serial-test',
44
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
26
'migration-test']
45
"-numa cpu,node-id=1,thread-id=0 "
27
46
"-numa cpu,node-id=0,thread-id=1");
28
--
47
--
29
2.20.1
48
2.25.1
30
49
31
50
diff view generated by jsdifflib
[PULL 09/12] hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
[PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology
1
From: Andrew Jones <drjones@redhat.com>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
Move the KVM PMU setup part of fdt_add_pmu_nodes() to
3
Currently, the SMP configuration isn't considered when the CPU
4
virt_cpu_post_init(), which is a more appropriate location. Now
4
topology is populated. In this case, it's impossible to provide
5
fdt_add_pmu_nodes() is also named more appropriately, because it
5
the default CPU-to-NUMA mapping or association based on the socket
6
no longer does anything but fdt node creation.
6
ID of the given CPU.
7
7
8
No functional change intended.
8
This takes account of SMP configuration when the CPU topology
9
is populated. The die ID for the given CPU isn't assigned since
10
it's not supported on arm/virt machine. Besides, the used SMP
11
configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted
12
to avoid testing failure
9
13
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Gavin Shan <gshan@redhat.com>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
15
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
12
Signed-off-by: Andrew Jones <drjones@redhat.com>
16
Acked-by: Igor Mammedov <imammedo@redhat.com>
13
Message-id: 20201001061718.101915-5-drjones@redhat.com
17
Message-id: 20220503140304.855514-4-gshan@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
19
---
16
hw/arm/virt.c | 34 ++++++++++++++++++----------------
20
hw/arm/virt.c | 15 ++++++++++++++-
17
1 file changed, 18 insertions(+), 16 deletions(-)
21
1 file changed, 14 insertions(+), 1 deletion(-)
18
22
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
23
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
25
--- a/hw/arm/virt.c
22
+++ b/hw/arm/virt.c
26
+++ b/hw/arm/virt.c
23
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
27
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
24
28
int n;
25
static void fdt_add_pmu_nodes(const VirtMachineState *vms)
29
unsigned int max_cpus = ms->smp.max_cpus;
26
{
30
VirtMachineState *vms = VIRT_MACHINE(ms);
27
- CPUState *cpu;
31
+ MachineClass *mc = MACHINE_GET_CLASS(vms);
28
- ARMCPU *armcpu;
32
29
+ ARMCPU *armcpu = ARM_CPU(first_cpu);
33
if (ms->possible_cpus) {
30
uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
34
assert(ms->possible_cpus->len == max_cpus);
31
35
@@ -XXX,XX +XXX,XX @@ static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
32
- CPU_FOREACH(cpu) {
36
ms->possible_cpus->cpus[n].type = ms->cpu_type;
33
- armcpu = ARM_CPU(cpu);
37
ms->possible_cpus->cpus[n].arch_id =
34
- if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
38
virt_cpu_mp_affinity(vms, n);
35
- return;
39
+
36
- }
40
+ assert(!mc->smp_props.dies_supported);
37
- if (kvm_enabled()) {
41
+ ms->possible_cpus->cpus[n].props.has_socket_id = true;
38
- if (kvm_irqchip_in_kernel()) {
42
+ ms->possible_cpus->cpus[n].props.socket_id =
39
- kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
43
+ n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
40
- }
44
+ ms->possible_cpus->cpus[n].props.has_cluster_id = true;
41
- kvm_arm_pmu_init(cpu);
45
+ ms->possible_cpus->cpus[n].props.cluster_id =
42
- }
46
+ (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
43
+ if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
47
+ ms->possible_cpus->cpus[n].props.has_core_id = true;
44
+ assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
48
+ ms->possible_cpus->cpus[n].props.core_id =
45
+ return;
49
+ (n / ms->smp.threads) % ms->smp.cores;
50
ms->possible_cpus->cpus[n].props.has_thread_id = true;
51
- ms->possible_cpus->cpus[n].props.thread_id = n;
52
+ ms->possible_cpus->cpus[n].props.thread_id =
53
+ n % ms->smp.threads;
46
}
54
}
47
55
return ms->possible_cpus;
48
if (vms->gic_version == VIRT_GIC_VERSION_2) {
56
}
49
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
50
(1 << vms->smp_cpus) - 1);
51
}
52
53
- armcpu = ARM_CPU(qemu_get_cpu(0));
54
qemu_fdt_add_subnode(vms->fdt, "/pmu");
55
if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
56
const char compat[] = "arm,armv8-pmuv3";
57
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
58
*/
59
static void virt_cpu_post_init(VirtMachineState *vms)
60
{
61
- bool aarch64;
62
+ bool aarch64, pmu;
63
+ CPUState *cpu;
64
65
aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
66
+ pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
67
68
- if (!kvm_enabled()) {
69
+ if (kvm_enabled()) {
70
+ CPU_FOREACH(cpu) {
71
+ if (pmu) {
72
+ assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
73
+ if (kvm_irqchip_in_kernel()) {
74
+ kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
75
+ }
76
+ kvm_arm_pmu_init(cpu);
77
+ }
78
+ }
79
+ } else {
80
if (aarch64 && vms->highmem) {
81
int requested_pa_size = 64 - clz64(vms->highest_gpa);
82
int pamax = arm_pamax(ARM_CPU(first_cpu));
83
--
57
--
84
2.20.1
58
2.25.1
85
86
diff view generated by jsdifflib
New patch
[PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu()
1
From: Gavin Shan <gshan@redhat.com>
1
2
3
In aarch64_numa_cpu(), the CPU and NUMA association is something
4
like below. Two threads in the same core/cluster/socket are
5
associated with two individual NUMA nodes, which is unreal as
6
Igor Mammedov mentioned. We don't expect the association to break
7
NUMA-to-socket boundary, which matches with the real world.
8
9
NUMA-node socket cluster core thread
10
------------------------------------------
11
0 0 0 0 0
12
1 0 0 0 1
13
14
This corrects the topology for CPUs and their association with
15
NUMA nodes. After this patch is applied, the CPU and NUMA
16
association becomes something like below, which looks real.
17
Besides, socket/cluster/core/thread IDs are all checked when
18
the NUMA node IDs are verified. It helps to check if the CPU
19
topology is properly populated or not.
20
21
NUMA-node socket cluster core thread
22
------------------------------------------
23
0 1 0 0 0
24
1 0 0 0 0
25
26
Suggested-by: Igor Mammedov <imammedo@redhat.com>
27
Signed-off-by: Gavin Shan <gshan@redhat.com>
28
Acked-by: Igor Mammedov <imammedo@redhat.com>
29
Message-id: 20220503140304.855514-5-gshan@redhat.com
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
32
tests/qtest/numa-test.c | 18 ++++++++++++------
33
1 file changed, 12 insertions(+), 6 deletions(-)
34
35
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/tests/qtest/numa-test.c
38
+++ b/tests/qtest/numa-test.c
39
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
40
g_autofree char *cli = NULL;
41
42
cli = make_cli(data, "-machine "
43
- "smp.cpus=2,smp.sockets=1,smp.clusters=1,smp.cores=1,smp.threads=2 "
44
+ "smp.cpus=2,smp.sockets=2,smp.clusters=1,smp.cores=1,smp.threads=1 "
45
"-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 "
46
- "-numa cpu,node-id=1,thread-id=0 "
47
- "-numa cpu,node-id=0,thread-id=1");
48
+ "-numa cpu,node-id=0,socket-id=1,cluster-id=0,core-id=0,thread-id=0 "
49
+ "-numa cpu,node-id=1,socket-id=0,cluster-id=0,core-id=0,thread-id=0");
50
qts = qtest_init(cli);
51
cpus = get_cpus(qts, &resp);
52
g_assert(cpus);
53
54
while ((e = qlist_pop(cpus))) {
55
QDict *cpu, *props;
56
- int64_t thread, node;
57
+ int64_t socket, cluster, core, thread, node;
58
59
cpu = qobject_to(QDict, e);
60
g_assert(qdict_haskey(cpu, "props"));
61
@@ -XXX,XX +XXX,XX @@ static void aarch64_numa_cpu(const void *data)
62
63
g_assert(qdict_haskey(props, "node-id"));
64
node = qdict_get_int(props, "node-id");
65
+ g_assert(qdict_haskey(props, "socket-id"));
66
+ socket = qdict_get_int(props, "socket-id");
67
+ g_assert(qdict_haskey(props, "cluster-id"));
68
+ cluster = qdict_get_int(props, "cluster-id");
69
+ g_assert(qdict_haskey(props, "core-id"));
70
+ core = qdict_get_int(props, "core-id");
71
g_assert(qdict_haskey(props, "thread-id"));
72
thread = qdict_get_int(props, "thread-id");
73
74
- if (thread == 0) {
75
+ if (socket == 0 && cluster == 0 && core == 0 && thread == 0) {
76
g_assert_cmpint(node, ==, 1);
77
- } else if (thread == 1) {
78
+ } else if (socket == 1 && cluster == 0 && core == 0 && thread == 0) {
79
g_assert_cmpint(node, ==, 0);
80
} else {
81
g_assert(false);
82
--
83
2.25.1
diff view generated by jsdifflib
[PULL 08/12] hw/arm/virt: Move post cpu realize check into its own function
[PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID
1
From: Andrew Jones <drjones@redhat.com>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
We'll add more to this new function in coming patches so we also
3
When CPU-to-NUMA association isn't explicitly provided by users,
4
state the gic must be created and call it below create_gic().
4
the default one is given by mc->get_default_cpu_node_id(). However,
5
the CPU topology isn't fully considered in the default association
6
and this causes CPU topology broken warnings on booting Linux guest.
5
7
6
No functional change intended.
8
For example, the following warning messages are observed when the
9
Linux guest is booted with the following command lines.
7
10
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
/home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
-accel kvm -machine virt,gic-version=host \
10
Signed-off-by: Andrew Jones <drjones@redhat.com>
13
-cpu host \
11
Message-id: 20201001061718.101915-4-drjones@redhat.com
14
-smp 6,sockets=2,cores=3,threads=1 \
15
-m 1024M,slots=16,maxmem=64G \
16
-object memory-backend-ram,id=mem0,size=128M \
17
-object memory-backend-ram,id=mem1,size=128M \
18
-object memory-backend-ram,id=mem2,size=128M \
19
-object memory-backend-ram,id=mem3,size=128M \
20
-object memory-backend-ram,id=mem4,size=128M \
21
-object memory-backend-ram,id=mem4,size=384M \
22
-numa node,nodeid=0,memdev=mem0 \
23
-numa node,nodeid=1,memdev=mem1 \
24
-numa node,nodeid=2,memdev=mem2 \
25
-numa node,nodeid=3,memdev=mem3 \
26
-numa node,nodeid=4,memdev=mem4 \
27
-numa node,nodeid=5,memdev=mem5
28
:
29
alternatives: patching kernel code
30
BUG: arch topology borken
31
the CLS domain not a subset of the MC domain
32
<the above error log repeats>
33
BUG: arch topology borken
34
the DIE domain not a subset of the NODE domain
35
36
With current implementation of mc->get_default_cpu_node_id(),
37
CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately.
38
That's incorrect because CPU#0/1/2 should be associated with same
39
NUMA node because they're seated in same socket.
40
41
This fixes the issue by considering the socket ID when the default
42
CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids().
43
With this applied, no more CPU topology broken warnings are seen
44
from the Linux guest. The 6 CPUs are associated with NODE#0/1, but
45
there are no CPUs associated with NODE#2/3/4/5.
46
47
Signed-off-by: Gavin Shan <gshan@redhat.com>
48
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
49
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
50
Message-id: 20220503140304.855514-6-gshan@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
51
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
52
---
14
hw/arm/virt.c | 43 +++++++++++++++++++++++++++----------------
53
hw/arm/virt.c | 4 +++-
15
1 file changed, 27 insertions(+), 16 deletions(-)
54
1 file changed, 3 insertions(+), 1 deletion(-)
16
55
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
56
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
57
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
58
--- a/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
59
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
60
@@ -XXX,XX +XXX,XX @@ virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
22
}
61
62
static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
63
{
64
- return idx % ms->numa_state->num_nodes;
65
+ int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
66
+
67
+ return socket_id % ms->numa_state->num_nodes;
23
}
68
}
24
69
25
+/*
70
static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
26
+ * virt_cpu_post_init() must be called after the CPUs have
27
+ * been realized and the GIC has been created.
28
+ */
29
+static void virt_cpu_post_init(VirtMachineState *vms)
30
+{
31
+ bool aarch64;
32
+
33
+ aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
34
+
35
+ if (!kvm_enabled()) {
36
+ if (aarch64 && vms->highmem) {
37
+ int requested_pa_size = 64 - clz64(vms->highest_gpa);
38
+ int pamax = arm_pamax(ARM_CPU(first_cpu));
39
+
40
+ if (pamax < requested_pa_size) {
41
+ error_report("VCPU supports less PA bits (%d) than "
42
+ "requested by the memory map (%d)",
43
+ pamax, requested_pa_size);
44
+ exit(1);
45
+ }
46
+ }
47
+ }
48
+}
49
+
50
static void machvirt_init(MachineState *machine)
51
{
52
VirtMachineState *vms = VIRT_MACHINE(machine);
53
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
54
fdt_add_timer_nodes(vms);
55
fdt_add_cpu_nodes(vms);
56
57
- if (!kvm_enabled()) {
58
- ARMCPU *cpu = ARM_CPU(first_cpu);
59
- bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
60
-
61
- if (aarch64 && vms->highmem) {
62
- int requested_pa_size, pamax = arm_pamax(cpu);
63
-
64
- requested_pa_size = 64 - clz64(vms->highest_gpa);
65
- if (pamax < requested_pa_size) {
66
- error_report("VCPU supports less PA bits (%d) than requested "
67
- "by the memory map (%d)", pamax, requested_pa_size);
68
- exit(1);
69
- }
70
- }
71
- }
72
-
73
memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
74
machine->ram);
75
if (machine->device_memory) {
76
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
77
78
create_gic(vms);
79
80
+ virt_cpu_post_init(vms);
81
+
82
fdt_add_pmu_nodes(vms);
83
84
create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
85
--
71
--
86
2.20.1
72
2.25.1
87
88
diff view generated by jsdifflib
[PULL 05/12] hw/char/bcm2835_aux: Allow less than 32-bit accesses
[PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
The "BCM2835 ARM Peripherals" datasheet [*] chapter 2
3
When the PPTT table is built, the CPU topology is re-calculated, but
4
("Auxiliaries: UART1 & SPI1, SPI2"), list the register
4
it's unecessary because the CPU topology has been populated in
5
sizes as 3/8/16/32 bits. We assume this means this
5
virt_possible_cpu_arch_ids() on arm/virt machine.
6
peripheral allows 8-bit accesses.
7
6
8
This was not an issue until commit 5d971f9e67 which reverted
7
This reworks build_pptt() to avoid by reusing the existing IDs in
9
("memory: accept mismatching sizes in memory_region_access_valid").
8
ms->possible_cpus. Currently, the only user of build_pptt() is
9
arm/virt machine.
10
10
11
The model is implemented as 32-bit accesses (see commit 97398d900c,
11
Signed-off-by: Gavin Shan <gshan@redhat.com>
12
all registers are 32-bit) so replace MemoryRegionOps.valid as
12
Tested-by: Yanan Wang <wangyanan55@huawei.com>
13
MemoryRegionOps.impl, and re-introduce MemoryRegionOps.valid
13
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
14
with a 8/32-bit range.
14
Acked-by: Igor Mammedov <imammedo@redhat.com>
15
15
Acked-by: Michael S. Tsirkin <mst@redhat.com>
16
[*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
16
Message-id: 20220503140304.855514-7-gshan@redhat.com
17
18
Fixes: 97398d900c ("bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block")
19
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20201002181032.1899463-1-f4bug@amsat.org
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
18
---
24
hw/char/bcm2835_aux.c | 4 +++-
19
hw/acpi/aml-build.c | 111 +++++++++++++++++++-------------------------
25
1 file changed, 3 insertions(+), 1 deletion(-)
20
1 file changed, 48 insertions(+), 63 deletions(-)
26
21
27
diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c
22
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
28
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/char/bcm2835_aux.c
24
--- a/hw/acpi/aml-build.c
30
+++ b/hw/char/bcm2835_aux.c
25
+++ b/hw/acpi/aml-build.c
31
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bcm2835_aux_ops = {
26
@@ -XXX,XX +XXX,XX @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,
32
.read = bcm2835_aux_read,
27
const char *oem_id, const char *oem_table_id)
33
.write = bcm2835_aux_write,
28
{
34
.endianness = DEVICE_NATIVE_ENDIAN,
29
MachineClass *mc = MACHINE_GET_CLASS(ms);
35
- .valid.min_access_size = 4,
30
- GQueue *list = g_queue_new();
36
+ .impl.min_access_size = 4,
31
- guint pptt_start = table_data->len;
37
+ .impl.max_access_size = 4,
32
- guint parent_offset;
38
+ .valid.min_access_size = 1,
33
- guint length, i;
39
.valid.max_access_size = 4,
34
- int uid = 0;
40
};
35
- int socket;
36
+ CPUArchIdList *cpus = ms->possible_cpus;
37
+ int64_t socket_id = -1, cluster_id = -1, core_id = -1;
38
+ uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;
39
+ uint32_t pptt_start = table_data->len;
40
+ int n;
41
AcpiTable table = { .sig = "PPTT", .rev = 2,
42
.oem_id = oem_id, .oem_table_id = oem_table_id };
43
44
acpi_table_begin(&table, table_data);
45
46
- for (socket = 0; socket < ms->smp.sockets; socket++) {
47
- g_queue_push_tail(list,
48
- GUINT_TO_POINTER(table_data->len - pptt_start));
49
- build_processor_hierarchy_node(
50
- table_data,
51
- /*
52
- * Physical package - represents the boundary
53
- * of a physical package
54
- */
55
- (1 << 0),
56
- 0, socket, NULL, 0);
57
- }
58
-
59
- if (mc->smp_props.clusters_supported) {
60
- length = g_queue_get_length(list);
61
- for (i = 0; i < length; i++) {
62
- int cluster;
63
-
64
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
65
- for (cluster = 0; cluster < ms->smp.clusters; cluster++) {
66
- g_queue_push_tail(list,
67
- GUINT_TO_POINTER(table_data->len - pptt_start));
68
- build_processor_hierarchy_node(
69
- table_data,
70
- (0 << 0), /* not a physical package */
71
- parent_offset, cluster, NULL, 0);
72
- }
73
+ /*
74
+ * This works with the assumption that cpus[n].props.*_id has been
75
+ * sorted from top to down levels in mc->possible_cpu_arch_ids().
76
+ * Otherwise, the unexpected and duplicated containers will be
77
+ * created.
78
+ */
79
+ for (n = 0; n < cpus->len; n++) {
80
+ if (cpus->cpus[n].props.socket_id != socket_id) {
81
+ assert(cpus->cpus[n].props.socket_id > socket_id);
82
+ socket_id = cpus->cpus[n].props.socket_id;
83
+ cluster_id = -1;
84
+ core_id = -1;
85
+ socket_offset = table_data->len - pptt_start;
86
+ build_processor_hierarchy_node(table_data,
87
+ (1 << 0), /* Physical package */
88
+ 0, socket_id, NULL, 0);
89
}
90
- }
91
92
- length = g_queue_get_length(list);
93
- for (i = 0; i < length; i++) {
94
- int core;
95
-
96
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
97
- for (core = 0; core < ms->smp.cores; core++) {
98
- if (ms->smp.threads > 1) {
99
- g_queue_push_tail(list,
100
- GUINT_TO_POINTER(table_data->len - pptt_start));
101
- build_processor_hierarchy_node(
102
- table_data,
103
- (0 << 0), /* not a physical package */
104
- parent_offset, core, NULL, 0);
105
- } else {
106
- build_processor_hierarchy_node(
107
- table_data,
108
- (1 << 1) | /* ACPI Processor ID valid */
109
- (1 << 3), /* Node is a Leaf */
110
- parent_offset, uid++, NULL, 0);
111
+ if (mc->smp_props.clusters_supported) {
112
+ if (cpus->cpus[n].props.cluster_id != cluster_id) {
113
+ assert(cpus->cpus[n].props.cluster_id > cluster_id);
114
+ cluster_id = cpus->cpus[n].props.cluster_id;
115
+ core_id = -1;
116
+ cluster_offset = table_data->len - pptt_start;
117
+ build_processor_hierarchy_node(table_data,
118
+ (0 << 0), /* Not a physical package */
119
+ socket_offset, cluster_id, NULL, 0);
120
}
121
+ } else {
122
+ cluster_offset = socket_offset;
123
}
124
- }
125
126
- length = g_queue_get_length(list);
127
- for (i = 0; i < length; i++) {
128
- int thread;
129
+ if (ms->smp.threads == 1) {
130
+ build_processor_hierarchy_node(table_data,
131
+ (1 << 1) | /* ACPI Processor ID valid */
132
+ (1 << 3), /* Node is a Leaf */
133
+ cluster_offset, n, NULL, 0);
134
+ } else {
135
+ if (cpus->cpus[n].props.core_id != core_id) {
136
+ assert(cpus->cpus[n].props.core_id > core_id);
137
+ core_id = cpus->cpus[n].props.core_id;
138
+ core_offset = table_data->len - pptt_start;
139
+ build_processor_hierarchy_node(table_data,
140
+ (0 << 0), /* Not a physical package */
141
+ cluster_offset, core_id, NULL, 0);
142
+ }
143
144
- parent_offset = GPOINTER_TO_UINT(g_queue_pop_head(list));
145
- for (thread = 0; thread < ms->smp.threads; thread++) {
146
- build_processor_hierarchy_node(
147
- table_data,
148
+ build_processor_hierarchy_node(table_data,
149
(1 << 1) | /* ACPI Processor ID valid */
150
(1 << 2) | /* Processor is a Thread */
151
(1 << 3), /* Node is a Leaf */
152
- parent_offset, uid++, NULL, 0);
153
+ core_offset, n, NULL, 0);
154
}
155
}
156
157
- g_queue_free(list);
158
acpi_table_end(linker, &table);
159
}
41
160
42
--
161
--
43
2.20.1
162
2.25.1
44
45
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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