The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)

https://github.com/rth7680/qemu.git tags/pull-tcg-20201008

for you to fetch changes up to 62475e9d007d83db4d0a6ccebcda8914f392e9c9:

accel/tcg: Fix computing of is_write for MIPS (2020-10-08 05:57:32 -0500)

Extend maximum gvec vector size

Fix i386 avx2 dupi

Fix mips host user-only write detection

Misc cleanups.

Kele Huang (1):

accel/tcg: Fix computing of is_write for MIPS

Richard Henderson (10):

tcg: Adjust simd_desc size encoding

tcg: Drop union from TCGArgConstraint

tcg: Move sorted_args into TCGArgConstraint.sort_index

tcg: Remove TCG_CT_REG

tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields

tcg: Remove TCGOpDef.used

tcg/i386: Fix dupi for avx2 32-bit hosts

tcg: Fix generation of dupi_vec for 32-bit host

tcg/optimize: Fold dup2_vec

tcg: Remove TCG_TARGET_HAS_cmp_vec

include/tcg/tcg-gvec-desc.h | 38 ++++++++++++------

include/tcg/tcg.h | 22 ++++------

tcg/aarch64/tcg-target.h | 1 -

tcg/i386/tcg-target.h | 1 -

tcg/ppc/tcg-target.h | 1 -

accel/tcg/user-exec.c | 43 ++++++++++++++++++--

tcg/optimize.c | 15 +++++++

tcg/tcg-op-gvec.c | 35 ++++++++++++----

tcg/tcg-op-vec.c | 12 ++++--

tcg/tcg.c | 96 +++++++++++++++++++-------------------------

tcg/aarch64/tcg-target.c.inc | 17 ++++----

tcg/arm/tcg-target.c.inc | 29 ++++++-------

tcg/i386/tcg-target.c.inc | 39 +++++++-----------

tcg/mips/tcg-target.c.inc | 21 +++++-----

tcg/ppc/tcg-target.c.inc | 29 ++++++-------

tcg/riscv/tcg-target.c.inc | 16 ++++----

tcg/s390/tcg-target.c.inc | 22 +++++-----

tcg/sparc/tcg-target.c.inc | 21 ++++------

tcg/tci/tcg-target.c.inc | 3 +-

19 files changed, 244 insertions(+), 217 deletions(-)

The cmp_vec opcode is mandatory; this symbol is unused.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

tcg/aarch64/tcg-target.h | 1 -

tcg/i386/tcg-target.h | 1 -

tcg/ppc/tcg-target.h | 1 -

3 files changed, 3 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h

--- a/tcg/aarch64/tcg-target.h

+++ b/tcg/aarch64/tcg-target.h

@@ -XXX,XX +XXX,XX @@ typedef enum {

#define TCG_TARGET_HAS_shi_vec 1

#define TCG_TARGET_HAS_shs_vec 0

#define TCG_TARGET_HAS_shv_vec 1

-#define TCG_TARGET_HAS_cmp_vec 1

#define TCG_TARGET_HAS_mul_vec 1

#define TCG_TARGET_HAS_sat_vec 1

#define TCG_TARGET_HAS_minmax_vec 1

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h

index XXXXXXX..XXXXXXX 100644

--- a/tcg/i386/tcg-target.h

+++ b/tcg/i386/tcg-target.h

@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;

#define TCG_TARGET_HAS_shi_vec 1

#define TCG_TARGET_HAS_shs_vec 1

#define TCG_TARGET_HAS_shv_vec have_avx2

-#define TCG_TARGET_HAS_cmp_vec 1

#define TCG_TARGET_HAS_mul_vec 1

#define TCG_TARGET_HAS_sat_vec 1

#define TCG_TARGET_HAS_minmax_vec 1

diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h

index XXXXXXX..XXXXXXX 100644

--- a/tcg/ppc/tcg-target.h

+++ b/tcg/ppc/tcg-target.h

@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;

#define TCG_TARGET_HAS_shi_vec 0

#define TCG_TARGET_HAS_shs_vec 0

#define TCG_TARGET_HAS_shv_vec 1

-#define TCG_TARGET_HAS_cmp_vec 1

#define TCG_TARGET_HAS_mul_vec 1

#define TCG_TARGET_HAS_sat_vec 1

#define TCG_TARGET_HAS_minmax_vec 1

2.25.1

From: Kele Huang <kele.hwang@gmail.com>

Detect all MIPS store instructions in cpu_signal_handler for all available

MIPS versions, and set is_write if encountering such store instructions.

This fixed the error while dealing with self-modified code for MIPS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Kele Huang <kele.hwang@gmail.com>

Signed-off-by: Xu Zou <iwatchnima@gmail.com>

Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>

[rth: Use uintptr_t for pc to fix n32 build error.]

accel/tcg/user-exec.c | 43 +++++++++++++++++++++++++++++++++++++++----

1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c

--- a/accel/tcg/user-exec.c

+++ b/accel/tcg/user-exec.c

@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,

#elif defined(__mips__)

+#if defined(__misp16) || defined(__mips_micromips)

+#error "Unsupported encoding"

+#endif

+

int cpu_signal_handler(int host_signum, void *pinfo,

void *puc)

{

siginfo_t *info = pinfo;

ucontext_t *uc = puc;

- greg_t pc = uc->uc_mcontext.pc;

- int is_write;

+ uintptr_t pc = uc->uc_mcontext.pc;

+ uint32_t insn = *(uint32_t *)pc;

+ int is_write = 0;

+

+ /* Detect all store instructions at program counter. */

+ switch((insn >> 26) & 077) {

+ case 050: /* SB */

+ case 051: /* SH */

+ case 052: /* SWL */

+ case 053: /* SW */

+ case 054: /* SDL */

+ case 055: /* SDR */

+ case 056: /* SWR */

+ case 070: /* SC */

+ case 071: /* SWC1 */

+ case 074: /* SCD */

+ case 075: /* SDC1 */

+ case 077: /* SD */

+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6

+ case 072: /* SWC2 */

+ case 076: /* SDC2 */

+#endif

+ is_write = 1;

+ break;

+ case 023: /* COP1X */

+ /* Required in all versions of MIPS64 since

+ MIPS64r1 and subsequent versions of MIPS32r2. */

+ switch (insn & 077) {

+ case 010: /* SWXC1 */

+ case 011: /* SDXC1 */

+ case 015: /* SUXC1 */

+ is_write = 1;

+ }

+ break;

- /* XXX: compute is_write */

- is_write = 0;

return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);

}

2.25.1

The definition of INDEX_op_dupi_vec is that it operates on

units of tcg_target_ulong -- in this case 32 bits. It does

not work to use this for a uint64_t value that happens to be

small enough to fit in tcg_target_ulong.

Fixes: d2fd745fe8b

Fixes: db432672dc5

Cc: qemu-stable@nongnu.org

tcg/tcg-op-vec.c | 12 ++++++++----

1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c

--- a/tcg/tcg-op-vec.c

+++ b/tcg/tcg-op-vec.c

@@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)

void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)

- if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {

- do_dupi_vec(r, MO_32, a);

- } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {

+ if (TCG_TARGET_REG_BITS == 64) {

do_dupi_vec(r, MO_64, a);

+ } else if (a == dup_const(MO_32, a)) {

+ do_dupi_vec(r, MO_32, a);

} else {

TCGv_i64 c = tcg_const_i64(a);

tcg_gen_dup_i64_vec(MO_64, r, c);

@@ -XXX,XX +XXX,XX @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)

void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)

{

- do_dupi_vec(r, MO_REG, dup_const(vece, a));

+ if (vece == MO_64) {

+ tcg_gen_dup64i_vec(r, a);

+ } else {

+ do_dupi_vec(r, MO_REG, dup_const(vece, a));

void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)

2.25.1

This uses an existing hole in the TCGArgConstraint structure

and will be convenient for keeping the data in one place.

include/tcg/tcg.h | 2 +-

tcg/tcg.c | 35 +++++++++++++++++------------------

2 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h

--- a/include/tcg/tcg.h

+++ b/include/tcg/tcg.h

@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);

typedef struct TCGArgConstraint {

uint16_t ct;

uint8_t alias_index;

+ uint8_t sort_index;

TCGRegSet regs;

} TCGArgConstraint;

@@ -XXX,XX +XXX,XX @@ typedef struct TCGOpDef {

uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;

uint8_t flags;

TCGArgConstraint *args_ct;

- int *sorted_args;

#if defined(CONFIG_DEBUG_TCG)

int used;

#endif

diff --git a/tcg/tcg.c b/tcg/tcg.c

index XXXXXXX..XXXXXXX 100644

--- a/tcg/tcg.c

+++ b/tcg/tcg.c

@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)

int op, total_args, n, i;

TCGOpDef *def;

TCGArgConstraint *args_ct;

- int *sorted_args;

TCGTemp *ts;

memset(s, 0, sizeof(*s));

@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)

args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);

- sorted_args = g_malloc(sizeof(int) * total_args);

for(op = 0; op < NB_OPS; op++) {

def = &tcg_op_defs[op];

def->args_ct = args_ct;

- def->sorted_args = sorted_args;

n = def->nb_iargs + def->nb_oargs;

- sorted_args += n;

args_ct += n;

}

@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)

/* sort from highest priority to lowest */

static void sort_constraints(TCGOpDef *def, int start, int n)

{

- int i, j, p1, p2, tmp;

+ int i, j;

+ TCGArgConstraint *a = def->args_ct;

- for(i = 0; i < n; i++)

- def->sorted_args[start + i] = start + i;

- if (n <= 1)

+ for (i = 0; i < n; i++) {

+ a[start + i].sort_index = start + i;

+ }

+ if (n <= 1) {

return;

- for(i = 0; i < n - 1; i++) {

- for(j = i + 1; j < n; j++) {

- p1 = get_constraint_priority(def, def->sorted_args[start + i]);

- p2 = get_constraint_priority(def, def->sorted_args[start + j]);

+ }

+ for (i = 0; i < n - 1; i++) {

+ for (j = i + 1; j < n; j++) {

+ int p1 = get_constraint_priority(def, a[start + i].sort_index);

+ int p2 = get_constraint_priority(def, a[start + j].sort_index);

if (p1 < p2) {

- tmp = def->sorted_args[start + i];

- def->sorted_args[start + i] = def->sorted_args[start + j];

- def->sorted_args[start + j] = tmp;

+ int tmp = a[start + i].sort_index;

+ a[start + i].sort_index = a[start + j].sort_index;

+ a[start + j].sort_index = tmp;

}

}

}

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

for (k = 0; k < nb_iargs; k++) {

TCGRegSet i_preferred_regs, o_preferred_regs;

- i = def->sorted_args[nb_oargs + k];

+ i = def->args_ct[nb_oargs + k].sort_index;

arg = op->args[i];

arg_ct = &def->args_ct[i];

ts = arg_temp(arg);

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

int k2, i2;

reg = ts->reg;

for (k2 = 0 ; k2 < k ; k2++) {

- i2 = def->sorted_args[nb_oargs + k2];

+ i2 = def->args_ct[nb_oargs + k2].sort_index;

if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&

reg == new_args[i2]) {

goto allocate_in_reg;

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

/* satisfy the output constraints */

for(k = 0; k < nb_oargs; k++) {

- i = def->sorted_args[k];

+ i = def->args_ct[k].sort_index;

arg = op->args[i];

arg_ct = &def->args_ct[i];

ts = arg_temp(arg);

2.25.1

The union is unused; let "regs" appear in the main structure

without the "u.regs" wrapping.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

include/tcg/tcg.h | 4 +---

tcg/tcg.c | 22 +++++++++++-----------

tcg/aarch64/tcg-target.c.inc | 14 +++++++-------

tcg/arm/tcg-target.c.inc | 26 +++++++++++++-------------

tcg/i386/tcg-target.c.inc | 26 +++++++++++++-------------

tcg/mips/tcg-target.c.inc | 18 +++++++++---------

tcg/ppc/tcg-target.c.inc | 24 ++++++++++++------------

tcg/riscv/tcg-target.c.inc | 14 +++++++-------

tcg/s390/tcg-target.c.inc | 18 +++++++++---------

tcg/sparc/tcg-target.c.inc | 16 ++++++++--------

tcg/tci/tcg-target.c.inc | 2 +-

11 files changed, 91 insertions(+), 93 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h

--- a/include/tcg/tcg.h

+++ b/include/tcg/tcg.h

@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);

typedef struct TCGArgConstraint {

uint16_t ct;

uint8_t alias_index;

- union {

- TCGRegSet regs;

- } u;

+ TCGRegSet regs;

} TCGArgConstraint;

#define TCG_MAX_OP_ARGS 16

diff --git a/tcg/tcg.c b/tcg/tcg.c

index XXXXXXX..XXXXXXX 100644

--- a/tcg/tcg.c

+++ b/tcg/tcg.c

@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)

return 0;

n = 0;

for(i = 0; i < TCG_TARGET_NB_REGS; i++) {

- if (tcg_regset_test_reg(arg_ct->u.regs, i))

+ if (tcg_regset_test_reg(arg_ct->regs, i))

n++;

}

}

@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)

/* Incomplete TCGTargetOpDef entry. */

tcg_debug_assert(ct_str != NULL);

- def->args_ct[i].u.regs = 0;

+ def->args_ct[i].regs = 0;

def->args_ct[i].ct = 0;

while (*ct_str != '\0') {

switch(*ct_str) {

@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)

pset = la_temp_pref(ts);

set = *pset;

- set &= ct->u.regs;

+ set &= ct->regs;

if (ct->ct & TCG_CT_IALIAS) {

set &= op->output_pref[ct->alias_index];

}

/* If the combination is not possible, restart. */

if (set == 0) {

- set = ct->u.regs;

+ set = ct->regs;

}

*pset = set;

}

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)

return;

}

- dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;

- dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;

+ dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;

+ dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;

/* Allocate the output register now. */

if (ots->val_type != TEMP_VAL_REG) {

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

}

}

- temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);

+ temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);

reg = ts->reg;

- if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {

+ if (tcg_regset_test_reg(arg_ct->regs, reg)) {

/* nothing to do : the constraint is satisfied */

} else {

allocate_in_reg:

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

and move the temporary register into it */

temp_load(s, ts, tcg_target_available_regs[ts->type],

i_allocated_regs, 0);

- reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,

+ reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,

o_preferred_regs, ts->indirect_base);

if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {

/*

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

&& !const_args[arg_ct->alias_index]) {

reg = new_args[arg_ct->alias_index];

} else if (arg_ct->ct & TCG_CT_NEWREG) {

- reg = tcg_reg_alloc(s, arg_ct->u.regs,

+ reg = tcg_reg_alloc(s, arg_ct->regs,

i_allocated_regs | o_allocated_regs,

op->output_pref[k], ts->indirect_base);

} else {

- reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,

+ reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,

op->output_pref[k], ts->indirect_base);

}

tcg_regset_set_reg(o_allocated_regs, reg);

diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/tcg/aarch64/tcg-target.c.inc

+++ b/tcg/aarch64/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

switch (*ct_str++) {

case 'r': /* general registers */

ct->ct |= TCG_CT_REG;

- ct->u.regs |= 0xffffffffu;

+ ct->regs |= 0xffffffffu;

break;

case 'w': /* advsimd registers */

ct->ct |= TCG_CT_REG;

- ct->u.regs |= 0xffffffff00000000ull;

+ ct->regs |= 0xffffffff00000000ull;

break;

case 'l': /* qemu_ld / qemu_st address, data_reg */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffffu;

+ ct->regs = 0xffffffffu;

#ifdef CONFIG_SOFTMMU

/* x0 and x1 will be overwritten when reading the tlb entry,

and x2, and x3 for helper args, better to avoid using them. */

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_X0);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_X1);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_X2);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_X3);

#endif

break;

case 'A': /* Valid for arithmetic immediate (positive or negative). */

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/tcg/arm/tcg-target.c.inc

+++ b/tcg/arm/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

case 'r':

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffff;

+ ct->regs = 0xffff;

break;

/* qemu_ld address */

case 'l':

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffff;

+ ct->regs = 0xffff;

#ifdef CONFIG_SOFTMMU

/* r0-r2,lr will be overwritten when reading the tlb entry,

so don't use these. */

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R0);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R1);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R14);

#endif

break;

/* qemu_st address & data */

case 's':

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffff;

+ ct->regs = 0xffff;

/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)

and r0-r1 doing the byte swapping, so don't use these. */

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R0);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R1);

#if defined(CONFIG_SOFTMMU)

/* Avoid clashes with registers being used for helper args */

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);

#if TARGET_LONG_BITS == 64

/* Avoid clashes with registers being used for helper args */

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);

#endif

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R14);

#endif

break;

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/tcg/i386/tcg-target.c.inc

+++ b/tcg/i386/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

switch(*ct_str++) {

case 'a':

ct->ct |= TCG_CT_REG;

- tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);

+ tcg_regset_set_reg(ct->regs, TCG_REG_EAX);

break;

case 'b':

ct->ct |= TCG_CT_REG;

- tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);

+ tcg_regset_set_reg(ct->regs, TCG_REG_EBX);

break;

case 'c':

ct->ct |= TCG_CT_REG;

- tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);

+ tcg_regset_set_reg(ct->regs, TCG_REG_ECX);

break;

case 'd':

ct->ct |= TCG_CT_REG;

- tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);

+ tcg_regset_set_reg(ct->regs, TCG_REG_EDX);

break;

case 'S':

ct->ct |= TCG_CT_REG;

- tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);

+ tcg_regset_set_reg(ct->regs, TCG_REG_ESI);

break;

case 'D':

ct->ct |= TCG_CT_REG;

- tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);

+ tcg_regset_set_reg(ct->regs, TCG_REG_EDI);

break;

case 'q':

/* A register that can be used as a byte operand. */

ct->ct |= TCG_CT_REG;

- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;

+ ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;

break;

case 'Q':

/* A register with an addressable second byte (e.g. %ah). */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xf;

+ ct->regs = 0xf;

break;

case 'r':

/* A general register. */

ct->ct |= TCG_CT_REG;

- ct->u.regs |= ALL_GENERAL_REGS;

+ ct->regs |= ALL_GENERAL_REGS;

break;

case 'W':

/* With TZCNT/LZCNT, we can have operand-size as an input. */

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

case 'x':

/* A vector register. */

ct->ct |= TCG_CT_REG;

- ct->u.regs |= ALL_VECTOR_REGS;

+ ct->regs |= ALL_VECTOR_REGS;

break;

/* qemu_ld/st address constraint */

case 'L':

ct->ct |= TCG_CT_REG;

- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);

+ ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;

+ tcg_regset_reset_reg(ct->regs, TCG_REG_L0);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_L1);

break;

case 'e':

diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/tcg/mips/tcg-target.c.inc

+++ b/tcg/mips/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

switch(*ct_str++) {

case 'r':

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

+ ct->regs = 0xffffffff;

break;

case 'L': /* qemu_ld input arg constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);

+ ct->regs = 0xffffffff;

+ tcg_regset_reset_reg(ct->regs, TCG_REG_A0);

#if defined(CONFIG_SOFTMMU)

if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_A2);

break;

case 'S': /* qemu_st constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);

+ ct->regs = 0xffffffff;

+ tcg_regset_reset_reg(ct->regs, TCG_REG_A0);

#if defined(CONFIG_SOFTMMU)

if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_A2);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_A3);

} else {

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_A1);

}

#endif

break;

diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc

--- a/tcg/ppc/tcg-target.c.inc

+++ b/tcg/ppc/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

switch (*ct_str++) {

case 'A': case 'B': case 'C': case 'D':

ct->ct |= TCG_CT_REG;

- tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');

+ tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');

break;

case 'r':

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

+ ct->regs = 0xffffffff;

break;

case 'v':

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff00000000ull;

+ ct->regs = 0xffffffff00000000ull;

break;

case 'L': /* qemu_ld constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

+ ct->regs = 0xffffffff;

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);

#ifdef CONFIG_SOFTMMU

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R5);

#endif

break;

case 'S': /* qemu_st constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

+ ct->regs = 0xffffffff;

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);

#ifdef CONFIG_SOFTMMU

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R5);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R6);

#endif

break;

case 'I':

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/tcg/riscv/tcg-target.c.inc

+++ b/tcg/riscv/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

switch (*ct_str++) {

case 'r':

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

+ ct->regs = 0xffffffff;

break;

case 'L':

/* qemu_ld/qemu_st constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

+ ct->regs = 0xffffffff;

/* qemu_ld/qemu_st uses TCG_REG_TMP0 */

#if defined(CONFIG_SOFTMMU)

- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);

- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);

- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);

- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);

- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);

+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);

+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);

+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);

+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);

+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);

#endif

break;

case 'I':

diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/tcg/s390/tcg-target.c.inc

+++ b/tcg/s390/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

switch (*ct_str++) {

case 'r': /* all registers */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffff;

+ ct->regs = 0xffff;

break;

case 'L': /* qemu_ld/st constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffff;

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);

+ ct->regs = 0xffff;

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);

break;

case 'a': /* force R2 for division */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0;

- tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);

+ ct->regs = 0;

+ tcg_regset_set_reg(ct->regs, TCG_REG_R2);

break;

case 'b': /* force R3 for division */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0;

- tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);

+ ct->regs = 0;

+ tcg_regset_set_reg(ct->regs, TCG_REG_R3);

break;

case 'A':

ct->ct |= TCG_CT_CONST_S33;

diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/tcg/sparc/tcg-target.c.inc

+++ b/tcg/sparc/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

switch (*ct_str++) {

case 'r':

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

+ ct->regs = 0xffffffff;

break;

case 'R':

ct->ct |= TCG_CT_REG;

- ct->u.regs = ALL_64;

+ ct->regs = ALL_64;

break;

case 'A': /* qemu_ld/st address constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;

+ ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;

reserve_helpers:

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);

- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_O0);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_O1);

+ tcg_regset_reset_reg(ct->regs, TCG_REG_O2);

break;

case 's': /* qemu_st data 32-bit constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = 0xffffffff;

+ ct->regs = 0xffffffff;

goto reserve_helpers;

case 'S': /* qemu_st data 64-bit constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = ALL_64;

+ ct->regs = ALL_64;

goto reserve_helpers;

case 'I':

ct->ct |= TCG_CT_CONST_S11;

diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/tcg/tci/tcg-target.c.inc

+++ b/tcg/tci/tcg-target.c.inc

@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,

case 'L': /* qemu_ld constraint */

case 'S': /* qemu_st constraint */

ct->ct |= TCG_CT_REG;

- ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;

+ ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;

break;

default:

return NULL;

2.25.1

With larger vector sizes, it turns out oprsz == maxsz, and we only

need to represent mismatch for oprsz <= 32. We do, however, need

to represent larger oprsz and do so without reducing SIMD_DATA_BITS.

Reduce the size of the oprsz field and increase the maxsz field.

Steal the oprsz value of 24 to indicate equality with maxsz.

Tested-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++-------------

tcg/tcg-op-gvec.c | 35 ++++++++++++++++++++++++++--------

2 files changed, 52 insertions(+), 21 deletions(-)

diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h

--- a/include/tcg/tcg-gvec-desc.h

+++ b/include/tcg/tcg-gvec-desc.h

@@ -XXX,XX +XXX,XX @@

#ifndef TCG_TCG_GVEC_DESC_H

#define TCG_TCG_GVEC_DESC_H

-/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */

-#define SIMD_OPRSZ_SHIFT 0

-#define SIMD_OPRSZ_BITS 5

+/*

+ * This configuration allows MAXSZ to represent 2048 bytes, and

+ * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.

+ *

+ * Encode this with:

+ * 0, 1, 3 -> 8, 16, 32

+ * 2 -> maxsz

+ *

+ * This steals the input that would otherwise map to 24 to match maxsz.

+ */

+#define SIMD_MAXSZ_SHIFT 0

+#define SIMD_MAXSZ_BITS 8

-#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)

-#define SIMD_MAXSZ_BITS 5

+#define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)

+#define SIMD_OPRSZ_BITS 2

-#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)

+#define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)

#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)

/* Create a descriptor from components. */

uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);

-/* Extract the operation size from a descriptor. */

-static inline intptr_t simd_oprsz(uint32_t desc)

-{

- return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;

-}

/* Extract the max vector size from a descriptor. */

static inline intptr_t simd_maxsz(uint32_t desc)

{

- return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;

+ return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;

+}

+/* Extract the operation size from a descriptor. */

+static inline intptr_t simd_oprsz(uint32_t desc)

+{

+ uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);

+ intptr_t o = f * 8 + 8;

+ intptr_t m = simd_maxsz(desc);

+ return f == 2 ? m : o;

/* Extract the operation-specific data from a descriptor. */

diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c

--- a/tcg/tcg-op-gvec.c

+++ b/tcg/tcg-op-gvec.c

@@ -XXX,XX +XXX,XX @@ static const TCGOpcode vecop_list_empty[1] = { 0 };

of the operand offsets so that we can check them all at once. */

static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)

{

- uint32_t opr_align = oprsz >= 16 ? 15 : 7;

- uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;

- tcg_debug_assert(oprsz > 0);

- tcg_debug_assert(oprsz <= maxsz);

- tcg_debug_assert((oprsz & opr_align) == 0);

+ uint32_t max_align;

+

+ switch (oprsz) {

+ case 8:

+ case 16:

+ case 32:

+ tcg_debug_assert(oprsz <= maxsz);

+ break;

+ default:

+ tcg_debug_assert(oprsz == maxsz);

+ break;

+ }

+ tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));

+

+ max_align = maxsz >= 16 ? 15 : 7;

tcg_debug_assert((maxsz & max_align) == 0);

tcg_debug_assert((ofs & max_align) == 0);

}

@@ -XXX,XX +XXX,XX @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)

{

uint32_t desc = 0;

- assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));

- assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));

- assert(data == sextract32(data, 0, SIMD_DATA_BITS));

+ check_size_align(oprsz, maxsz, 0);

+ tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));

oprsz = (oprsz / 8) - 1;

maxsz = (maxsz / 8) - 1;

+

+ /*

+ * We have just asserted in check_size_align that either

+ * oprsz is {8,16,32} or matches maxsz. Encode the final

+ * case with '2', as that would otherwise map to 24.

+ */

+ if (oprsz == maxsz) {

+ oprsz = 2;

+ }

+

desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);

desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);

desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);

2.25.1