[PULL 00/11] tcg patch queue
[PULL 00/28] tcg patch queue
1
The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:
1
The following changes since commit e3acc2c1961cbe22ca474cd5da4163b7bbf7cea3:
2
2
3
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)
3
tests/docker/dockerfiles: Bump fedora-i386-cross to fedora 34 (2021-10-05 16:40:39 -0700)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20201008
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211006
8
8
9
for you to fetch changes up to 62475e9d007d83db4d0a6ccebcda8914f392e9c9:
9
for you to fetch changes up to ea3f2af8f1b87d7bced9b75ef2e788b66ec49961:
10
10
11
accel/tcg: Fix computing of is_write for MIPS (2020-10-08 05:57:32 -0500)
11
tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec (2021-10-05 16:53:17 -0700)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Extend maximum gvec vector size
14
More fixes for fedora-i386-cross
15
Fix i386 avx2 dupi
15
Add dup_const_tl
16
Fix mips host user-only write detection
16
Expand MemOp MO_SIZE
17
Misc cleanups.
17
Move MemOpIdx out of tcg.h
18
Vector support for tcg/s390x
18
19
19
----------------------------------------------------------------
20
----------------------------------------------------------------
20
Kele Huang (1):
21
Philipp Tomsich (1):
21
accel/tcg: Fix computing of is_write for MIPS
22
tcg: add dup_const_tl wrapper
22
23
23
Richard Henderson (10):
24
Richard Henderson (27):
24
tcg: Adjust simd_desc size encoding
25
tests/docker: Remove fedora-i386-cross from DOCKER_PARTIAL_IMAGES
25
tcg: Drop union from TCGArgConstraint
26
tests/docker: Fix fedora-i386-cross cross-compilation
26
tcg: Move sorted_args into TCGArgConstraint.sort_index
27
accel/tcg: Drop signness in tracing in cputlb.c
27
tcg: Remove TCG_CT_REG
28
tcg: Expand MO_SIZE to 3 bits
28
tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
29
tcg: Rename TCGMemOpIdx to MemOpIdx
29
tcg: Remove TCGOpDef.used
30
tcg: Split out MemOpIdx to exec/memopidx.h
30
tcg/i386: Fix dupi for avx2 32-bit hosts
31
trace/mem: Pass MemOpIdx to trace_mem_get_info
31
tcg: Fix generation of dupi_vec for 32-bit host
32
accel/tcg: Pass MemOpIdx to atomic_trace_*_post
32
tcg/optimize: Fold dup2_vec
33
plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb
33
tcg: Remove TCG_TARGET_HAS_cmp_vec
34
trace: Split guest_mem_before
35
hw/core/cpu: Re-sort the non-pointers to the end of CPUClass
36
tcg: Expand usadd/ussub with umin/umax
37
tcg/s390x: Rename from tcg/s390
38
tcg/s390x: Change FACILITY representation
39
tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg
40
tcg/s390x: Add host vector framework
41
tcg/s390x: Implement tcg_out_ld/st for vector types
42
tcg/s390x: Implement tcg_out_mov for vector types
43
tcg/s390x: Implement tcg_out_dup*_vec
44
tcg/s390x: Implement minimal vector operations
45
tcg/s390x: Implement andc, orc, abs, neg, not vector operations
46
tcg/s390x: Implement TCG_TARGET_HAS_mul_vec
47
tcg/s390x: Implement vector shift operations
48
tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec
49
tcg/s390x: Implement TCG_TARGET_HAS_sat_vec
50
tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec
51
tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec
34
52
35
include/tcg/tcg-gvec-desc.h | 38 ++++++++++++------
53
meson.build | 2 -
36
include/tcg/tcg.h | 22 ++++------
54
accel/tcg/atomic_template.h | 73 +-
37
tcg/aarch64/tcg-target.h | 1 -
55
include/exec/memop.h | 14 +-
38
tcg/i386/tcg-target.h | 1 -
56
include/exec/memopidx.h | 55 ++
39
tcg/ppc/tcg-target.h | 1 -
57
include/hw/core/cpu.h | 11 +-
40
accel/tcg/user-exec.c | 43 ++++++++++++++++++--
58
include/qemu/plugin.h | 26 +-
41
tcg/optimize.c | 15 +++++++
59
include/tcg/tcg.h | 117 ++-
42
tcg/tcg-op-gvec.c | 35 ++++++++++++----
60
tcg/{s390 => s390x}/tcg-target-con-set.h | 7 +
43
tcg/tcg-op-vec.c | 12 ++++--
61
tcg/{s390 => s390x}/tcg-target-con-str.h | 1 +
44
tcg/tcg.c | 96 +++++++++++++++++++-------------------------
62
tcg/{s390 => s390x}/tcg-target.h | 91 ++-
45
tcg/aarch64/tcg-target.c.inc | 17 ++++----
63
tcg/s390x/tcg-target.opc.h | 15 +
46
tcg/arm/tcg-target.c.inc | 29 ++++++-------
64
trace/mem.h | 63 --
47
tcg/i386/tcg-target.c.inc | 39 +++++++-----------
65
accel/tcg/cputlb.c | 103 ++-
48
tcg/mips/tcg-target.c.inc | 21 +++++-----
66
accel/tcg/plugin-gen.c | 5 +-
49
tcg/ppc/tcg-target.c.inc | 29 ++++++-------
67
accel/tcg/user-exec.c | 133 ++-
50
tcg/riscv/tcg-target.c.inc | 16 ++++----
68
plugins/api.c | 19 +-
51
tcg/s390/tcg-target.c.inc | 22 +++++-----
69
plugins/core.c | 10 +-
52
tcg/sparc/tcg-target.c.inc | 21 ++++------
70
target/arm/helper-a64.c | 16 +-
53
tcg/tci/tcg-target.c.inc | 3 +-
71
target/arm/m_helper.c | 2 +-
54
19 files changed, 244 insertions(+), 217 deletions(-)
72
target/arm/translate-a64.c | 2 +-
73
target/i386/tcg/mem_helper.c | 4 +-
74
target/m68k/op_helper.c | 2 +-
75
target/mips/tcg/msa_helper.c | 6 +-
76
target/s390x/tcg/mem_helper.c | 20 +-
77
target/sparc/ldst_helper.c | 2 +-
78
tcg/optimize.c | 2 +-
79
tcg/tcg-op-vec.c | 37 +-
80
tcg/tcg-op.c | 60 +-
81
tcg/tcg.c | 2 +-
82
tcg/tci.c | 14 +-
83
accel/tcg/atomic_common.c.inc | 43 +-
84
target/s390x/tcg/translate_vx.c.inc | 2 +-
85
tcg/aarch64/tcg-target.c.inc | 18 +-
86
tcg/arm/tcg-target.c.inc | 14 +-
87
tcg/i386/tcg-target.c.inc | 14 +-
88
tcg/mips/tcg-target.c.inc | 16 +-
89
tcg/ppc/tcg-target.c.inc | 18 +-
90
tcg/riscv/tcg-target.c.inc | 20 +-
91
tcg/{s390 => s390x}/tcg-target.c.inc | 949 ++++++++++++++++++++--
92
tcg/sparc/tcg-target.c.inc | 20 +-
93
tcg/tcg-ldst.c.inc | 2 +-
94
tests/docker/Makefile.include | 2 +-
95
tests/docker/dockerfiles/fedora-i386-cross.docker | 5 +-
96
trace-events | 18 +-
97
44 files changed, 1445 insertions(+), 610 deletions(-)
98
create mode 100644 include/exec/memopidx.h
99
rename tcg/{s390 => s390x}/tcg-target-con-set.h (86%)
100
rename tcg/{s390 => s390x}/tcg-target-con-str.h (96%)
101
rename tcg/{s390 => s390x}/tcg-target.h (66%)
102
create mode 100644 tcg/s390x/tcg-target.opc.h
103
delete mode 100644 trace/mem.h
104
rename tcg/{s390 => s390x}/tcg-target.c.inc (73%)
55
105
diff view generated by jsdifflib
New patch
[PULL 01/28] tests/docker: Remove fedora-i386-cross from DOCKER_PARTIAL_IMAGES
1
The image was upgraded to a full image in ee381b7fe146.
2
This makes it possible to use docker-test@image syntax
3
with this container.
1
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
7
Message-Id: <20210930163636.721311-2-richard.henderson@linaro.org>
8
---
9
tests/docker/Makefile.include | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/docker/Makefile.include
15
+++ b/tests/docker/Makefile.include
16
@@ -XXX,XX +XXX,XX @@ DOCKER_PARTIAL_IMAGES += debian-riscv64-cross
17
DOCKER_PARTIAL_IMAGES += debian-sh4-cross debian-sparc64-cross
18
DOCKER_PARTIAL_IMAGES += debian-tricore-cross
19
DOCKER_PARTIAL_IMAGES += debian-xtensa-cross
20
-DOCKER_PARTIAL_IMAGES += fedora-i386-cross fedora-cris-cross
21
+DOCKER_PARTIAL_IMAGES += fedora-cris-cross
22
23
# Rules for building linux-user powered images
24
#
25
--
26
2.25.1
27
28
diff view generated by jsdifflib
New patch
[PULL 02/28] tests/docker: Fix fedora-i386-cross cross-compilation
1
By using PKG_CONFIG_PATH instead of PKG_CONFIG_LIBDIR,
2
we were still including the 64-bit packages. Install
3
pcre-devel.i686 to fill a missing glib2 dependency.
1
4
5
By using --extra-cflags instead of --cpu, we incorrectly
6
use the wrong probing during meson.
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard W.M. Jones <rjones@redhat.com>
10
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
11
Message-Id: <20210930163636.721311-3-richard.henderson@linaro.org>
12
---
13
tests/docker/dockerfiles/fedora-i386-cross.docker | 5 +++--
14
1 file changed, 3 insertions(+), 2 deletions(-)
15
16
diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker
17
index XXXXXXX..XXXXXXX 100644
18
--- a/tests/docker/dockerfiles/fedora-i386-cross.docker
19
+++ b/tests/docker/dockerfiles/fedora-i386-cross.docker
20
@@ -XXX,XX +XXX,XX @@ ENV PACKAGES \
21
glibc-static.i686 \
22
gnutls-devel.i686 \
23
nettle-devel.i686 \
24
+ pcre-devel.i686 \
25
perl-Test-Harness \
26
pixman-devel.i686 \
27
sysprof-capture-devel.i686 \
28
zlib-devel.i686
29
30
-ENV QEMU_CONFIGURE_OPTS --extra-cflags=-m32 --disable-vhost-user
31
-ENV PKG_CONFIG_PATH /usr/lib/pkgconfig
32
+ENV QEMU_CONFIGURE_OPTS --cpu=i386 --disable-vhost-user
33
+ENV PKG_CONFIG_LIBDIR /usr/lib/pkgconfig
34
35
RUN dnf update -y && dnf install -y $PACKAGES
36
RUN rpm -q $PACKAGES | sort > /packages.txt
37
--
38
2.25.1
39
40
diff view generated by jsdifflib
[PULL 05/11] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
[PULL 03/28] tcg: add dup_const_tl wrapper
1
These are easier to set and test when they have their own fields.
1
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
2
Reduce the size of alias_index and sort_index to 4 bits, which is
3
sufficient for TCG_MAX_OP_ARGS. This leaves only the bits indicating
4
constants within the ct field.
5
2
6
Move all initialization to allocation time, rather than init
3
dup_const always generates a uint64_t, which may exceed the size of a
7
individual fields in process_op_defs.
4
target_long (generating warnings with recent-enough compilers).
8
5
6
To ensure that we can use dup_const both for 64bit and 32bit targets,
7
this adds dup_const_tl, which either maps back to dup_const (for 64bit
8
targets) or provides a similar implementation using 32bit constants.
9
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
12
Message-Id: <20211003214243.3813425-1-philipp.tomsich@vrull.eu>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
14
---
11
include/tcg/tcg.h | 14 +++++++-------
15
include/tcg/tcg.h | 12 ++++++++++++
12
tcg/tcg.c | 28 ++++++++++++----------------
16
1 file changed, 12 insertions(+)
13
2 files changed, 19 insertions(+), 23 deletions(-)
14
17
15
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
18
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/include/tcg/tcg.h
20
--- a/include/tcg/tcg.h
18
+++ b/include/tcg/tcg.h
21
+++ b/include/tcg/tcg.h
19
@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void);
22
@@ -XXX,XX +XXX,XX @@ uint64_t dup_const(unsigned vece, uint64_t c);
20
void tcg_dump_info(void);
23
: (qemu_build_not_reached_always(), 0)) \
21
void tcg_dump_op_count(void);
24
: dup_const(VECE, C))
22
25
23
-#define TCG_CT_ALIAS 0x80
26
+#if TARGET_LONG_BITS == 64
24
-#define TCG_CT_IALIAS 0x40
27
+# define dup_const_tl dup_const
25
-#define TCG_CT_NEWREG 0x20 /* output requires a new register */
28
+#else
26
-#define TCG_CT_CONST 0x02 /* any constant of register size */
29
+# define dup_const_tl(VECE, C) \
27
+#define TCG_CT_CONST 1 /* any constant of register size */
30
+ (__builtin_constant_p(VECE) \
28
31
+ ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \
29
typedef struct TCGArgConstraint {
32
+ : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \
30
- uint16_t ct;
33
+ : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \
31
- uint8_t alias_index;
34
+ : (qemu_build_not_reached_always(), 0)) \
32
- uint8_t sort_index;
35
+ : (target_long)dup_const(VECE, C))
33
+ unsigned ct : 16;
36
+#endif
34
+ unsigned alias_index : 4;
37
+
35
+ unsigned sort_index : 4;
38
/*
36
+ bool oalias : 1;
39
* Memory helpers that will be used by TCG generated code.
37
+ bool ialias : 1;
40
*/
38
+ bool newreg : 1;
39
TCGRegSet regs;
40
} TCGArgConstraint;
41
42
diff --git a/tcg/tcg.c b/tcg/tcg.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/tcg/tcg.c
45
+++ b/tcg/tcg.c
46
@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
47
total_args += n;
48
}
49
50
- args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
51
+ args_ct = g_new0(TCGArgConstraint, total_args);
52
53
for(op = 0; op < NB_OPS; op++) {
54
def = &tcg_op_defs[op];
55
@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
56
const TCGArgConstraint *arg_ct = &def->args_ct[k];
57
int n;
58
59
- if (arg_ct->ct & TCG_CT_ALIAS) {
60
+ if (arg_ct->oalias) {
61
/* an alias is equivalent to a single register */
62
n = 1;
63
} else {
64
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
65
/* Incomplete TCGTargetOpDef entry. */
66
tcg_debug_assert(ct_str != NULL);
67
68
- def->args_ct[i].regs = 0;
69
- def->args_ct[i].ct = 0;
70
while (*ct_str != '\0') {
71
switch(*ct_str) {
72
case '0' ... '9':
73
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
74
tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
75
tcg_debug_assert(oarg < def->nb_oargs);
76
tcg_debug_assert(def->args_ct[oarg].regs != 0);
77
- /* TCG_CT_ALIAS is for the output arguments.
78
- The input is tagged with TCG_CT_IALIAS. */
79
def->args_ct[i] = def->args_ct[oarg];
80
- def->args_ct[oarg].ct |= TCG_CT_ALIAS;
81
+ /* The output sets oalias. */
82
+ def->args_ct[oarg].oalias = true;
83
def->args_ct[oarg].alias_index = i;
84
- def->args_ct[i].ct |= TCG_CT_IALIAS;
85
+ /* The input sets ialias. */
86
+ def->args_ct[i].ialias = true;
87
def->args_ct[i].alias_index = oarg;
88
}
89
ct_str++;
90
break;
91
case '&':
92
- def->args_ct[i].ct |= TCG_CT_NEWREG;
93
+ def->args_ct[i].newreg = true;
94
ct_str++;
95
break;
96
case 'i':
97
@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
98
set = *pset;
99
100
set &= ct->regs;
101
- if (ct->ct & TCG_CT_IALIAS) {
102
+ if (ct->ialias) {
103
set &= op->output_pref[ct->alias_index];
104
}
105
/* If the combination is not possible, restart. */
106
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
107
}
108
109
i_preferred_regs = o_preferred_regs = 0;
110
- if (arg_ct->ct & TCG_CT_IALIAS) {
111
+ if (arg_ct->ialias) {
112
o_preferred_regs = op->output_pref[arg_ct->alias_index];
113
if (ts->fixed_reg) {
114
/* if fixed register, we must allocate a new register
115
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
116
reg = ts->reg;
117
for (k2 = 0 ; k2 < k ; k2++) {
118
i2 = def->args_ct[nb_oargs + k2].sort_index;
119
- if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
120
- reg == new_args[i2]) {
121
+ if (def->args_ct[i2].ialias && reg == new_args[i2]) {
122
goto allocate_in_reg;
123
}
124
}
125
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
126
/* ENV should not be modified. */
127
tcg_debug_assert(!ts->fixed_reg);
128
129
- if ((arg_ct->ct & TCG_CT_ALIAS)
130
- && !const_args[arg_ct->alias_index]) {
131
+ if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
132
reg = new_args[arg_ct->alias_index];
133
- } else if (arg_ct->ct & TCG_CT_NEWREG) {
134
+ } else if (arg_ct->newreg) {
135
reg = tcg_reg_alloc(s, arg_ct->regs,
136
i_allocated_regs | o_allocated_regs,
137
op->output_pref[k], ts->indirect_base);
138
--
41
--
139
2.25.1
42
2.25.1
140
43
141
44
diff view generated by jsdifflib
New patch
[PULL 04/28] accel/tcg: Drop signness in tracing in cputlb.c
1
We are already inconsistent about whether or not
2
MO_SIGN is set in trace_mem_get_info. Dropping it
3
entirely allows some simplification.
1
4
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
accel/tcg/cputlb.c | 10 +++-------
9
accel/tcg/user-exec.c | 45 ++++++-------------------------------------
10
2 files changed, 9 insertions(+), 46 deletions(-)
11
12
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/accel/tcg/cputlb.c
15
+++ b/accel/tcg/cputlb.c
16
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
17
meminfo = trace_mem_get_info(op, mmu_idx, false);
18
trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
19
20
- op &= ~MO_SIGN;
21
oi = make_memop_idx(op, mmu_idx);
22
ret = full_load(env, addr, oi, retaddr);
23
24
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
25
int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
26
int mmu_idx, uintptr_t ra)
27
{
28
- return (int8_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_SB,
29
- full_ldub_mmu);
30
+ return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra);
31
}
32
33
uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
34
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
35
int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
36
int mmu_idx, uintptr_t ra)
37
{
38
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_BESW,
39
- full_be_lduw_mmu);
40
+ return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
41
}
42
43
uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
44
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
45
int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
46
int mmu_idx, uintptr_t ra)
47
{
48
- return (int16_t)cpu_load_helper(env, addr, mmu_idx, ra, MO_LESW,
49
- full_le_lduw_mmu);
50
+ return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra);
51
}
52
53
uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
54
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/accel/tcg/user-exec.c
57
+++ b/accel/tcg/user-exec.c
58
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
59
60
int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
61
{
62
- int ret;
63
- uint16_t meminfo = trace_mem_get_info(MO_SB, MMU_USER_IDX, false);
64
-
65
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
66
- ret = ldsb_p(g2h(env_cpu(env), ptr));
67
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
68
- return ret;
69
+ return (int8_t)cpu_ldub_data(env, ptr);
70
}
71
72
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
73
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
74
75
int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
76
{
77
- int ret;
78
- uint16_t meminfo = trace_mem_get_info(MO_BESW, MMU_USER_IDX, false);
79
-
80
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
81
- ret = ldsw_be_p(g2h(env_cpu(env), ptr));
82
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
83
- return ret;
84
+ return (int16_t)cpu_lduw_be_data(env, ptr);
85
}
86
87
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
88
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
89
90
int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
91
{
92
- int ret;
93
- uint16_t meminfo = trace_mem_get_info(MO_LESW, MMU_USER_IDX, false);
94
-
95
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
96
- ret = ldsw_le_p(g2h(env_cpu(env), ptr));
97
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
98
- return ret;
99
+ return (int16_t)cpu_lduw_le_data(env, ptr);
100
}
101
102
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
103
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
104
105
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
106
{
107
- int ret;
108
-
109
- set_helper_retaddr(retaddr);
110
- ret = cpu_ldsb_data(env, ptr);
111
- clear_helper_retaddr();
112
- return ret;
113
+ return (int8_t)cpu_ldub_data_ra(env, ptr, retaddr);
114
}
115
116
uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
117
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
118
119
int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
120
{
121
- int ret;
122
-
123
- set_helper_retaddr(retaddr);
124
- ret = cpu_ldsw_be_data(env, ptr);
125
- clear_helper_retaddr();
126
- return ret;
127
+ return (int16_t)cpu_lduw_be_data_ra(env, ptr, retaddr);
128
}
129
130
uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
131
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
132
133
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
134
{
135
- int ret;
136
-
137
- set_helper_retaddr(retaddr);
138
- ret = cpu_ldsw_le_data(env, ptr);
139
- clear_helper_retaddr();
140
- return ret;
141
+ return (int16_t)cpu_lduw_le_data_ra(env, ptr, retaddr);
142
}
143
144
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
145
--
146
2.25.1
147
148
diff view generated by jsdifflib
[PULL 02/11] tcg: Drop union from TCGArgConstraint
[PULL 05/28] tcg: Expand MO_SIZE to 3 bits
1
The union is unused; let "regs" appear in the main structure
1
We have lacked expressive support for memory sizes larger
2
without the "u.regs" wrapping.
2
than 64-bits for a while. Fixing that requires adjustment
3
to several points where we used this for array indexing,
4
and two places that develop -Wswitch warnings after the change.
3
5
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
9
---
7
include/tcg/tcg.h | 4 +---
10
include/exec/memop.h | 14 +++++++++-----
8
tcg/tcg.c | 22 +++++++++++-----------
11
target/arm/translate-a64.c | 2 +-
9
tcg/aarch64/tcg-target.c.inc | 14 +++++++-------
12
tcg/tcg-op.c | 13 ++++++++-----
10
tcg/arm/tcg-target.c.inc | 26 +++++++++++++-------------
13
target/s390x/tcg/translate_vx.c.inc | 2 +-
11
tcg/i386/tcg-target.c.inc | 26 +++++++++++++-------------
14
tcg/aarch64/tcg-target.c.inc | 4 ++--
12
tcg/mips/tcg-target.c.inc | 18 +++++++++---------
15
tcg/arm/tcg-target.c.inc | 4 ++--
13
tcg/ppc/tcg-target.c.inc | 24 ++++++++++++------------
16
tcg/i386/tcg-target.c.inc | 4 ++--
14
tcg/riscv/tcg-target.c.inc | 14 +++++++-------
17
tcg/mips/tcg-target.c.inc | 4 ++--
15
tcg/s390/tcg-target.c.inc | 18 +++++++++---------
18
tcg/ppc/tcg-target.c.inc | 8 ++++----
16
tcg/sparc/tcg-target.c.inc | 16 ++++++++--------
19
tcg/riscv/tcg-target.c.inc | 4 ++--
17
tcg/tci/tcg-target.c.inc | 2 +-
20
tcg/s390/tcg-target.c.inc | 4 ++--
18
11 files changed, 91 insertions(+), 93 deletions(-)
21
tcg/sparc/tcg-target.c.inc | 16 ++++++++--------
22
12 files changed, 43 insertions(+), 36 deletions(-)
19
23
20
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
24
diff --git a/include/exec/memop.h b/include/exec/memop.h
21
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
22
--- a/include/tcg/tcg.h
26
--- a/include/exec/memop.h
23
+++ b/include/tcg/tcg.h
27
+++ b/include/exec/memop.h
24
@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
28
@@ -XXX,XX +XXX,XX @@ typedef enum MemOp {
25
typedef struct TCGArgConstraint {
29
MO_16 = 1,
26
uint16_t ct;
30
MO_32 = 2,
27
uint8_t alias_index;
31
MO_64 = 3,
28
- union {
32
- MO_SIZE = 3, /* Mask for the above. */
29
- TCGRegSet regs;
33
+ MO_128 = 4,
30
- } u;
34
+ MO_256 = 5,
31
+ TCGRegSet regs;
35
+ MO_512 = 6,
32
} TCGArgConstraint;
36
+ MO_1024 = 7,
33
37
+ MO_SIZE = 0x07, /* Mask for the above. */
34
#define TCG_MAX_OP_ARGS 16
38
35
diff --git a/tcg/tcg.c b/tcg/tcg.c
39
- MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */
36
index XXXXXXX..XXXXXXX 100644
40
+ MO_SIGN = 0x08, /* Sign-extended, otherwise zero-extended. */
37
--- a/tcg/tcg.c
41
38
+++ b/tcg/tcg.c
42
- MO_BSWAP = 8, /* Host reverse endian. */
39
@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
43
+ MO_BSWAP = 0x10, /* Host reverse endian. */
40
return 0;
44
#ifdef HOST_WORDS_BIGENDIAN
41
n = 0;
45
MO_LE = MO_BSWAP,
42
for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
46
MO_BE = 0,
43
- if (tcg_regset_test_reg(arg_ct->u.regs, i))
47
@@ -XXX,XX +XXX,XX @@ typedef enum MemOp {
44
+ if (tcg_regset_test_reg(arg_ct->regs, i))
48
* - an alignment to a specified size, which may be more or less than
45
n++;
49
* the access size (MO_ALIGN_x where 'x' is a size in bytes);
50
*/
51
- MO_ASHIFT = 4,
52
- MO_AMASK = 7 << MO_ASHIFT,
53
+ MO_ASHIFT = 5,
54
+ MO_AMASK = 0x7 << MO_ASHIFT,
55
#ifdef NEED_CPU_H
56
#ifdef TARGET_ALIGNED_ONLY
57
MO_ALIGN = 0,
58
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/translate-a64.c
61
+++ b/target/arm/translate-a64.c
62
@@ -XXX,XX +XXX,XX @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
63
int element, MemOp memop)
64
{
65
int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
66
- switch (memop) {
67
+ switch ((unsigned)memop) {
68
case MO_8:
69
tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
70
break;
71
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/tcg/tcg-op.c
74
+++ b/tcg/tcg-op.c
75
@@ -XXX,XX +XXX,XX @@ static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
46
}
76
}
77
break;
78
case MO_64:
79
- if (!is64) {
80
- tcg_abort();
81
+ if (is64) {
82
+ op &= ~MO_SIGN;
83
+ break;
84
}
85
- break;
86
+ /* fall through */
87
+ default:
88
+ g_assert_not_reached();
47
}
89
}
48
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
90
if (st) {
49
/* Incomplete TCGTargetOpDef entry. */
91
op &= ~MO_SIGN;
50
tcg_debug_assert(ct_str != NULL);
92
@@ -XXX,XX +XXX,XX @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv,
51
93
# define WITH_ATOMIC64(X)
52
- def->args_ct[i].u.regs = 0;
94
#endif
53
+ def->args_ct[i].regs = 0;
95
54
def->args_ct[i].ct = 0;
96
-static void * const table_cmpxchg[16] = {
55
while (*ct_str != '\0') {
97
+static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] = {
56
switch(*ct_str) {
98
[MO_8] = gen_helper_atomic_cmpxchgb,
57
@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
99
[MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,
58
pset = la_temp_pref(ts);
100
[MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,
59
set = *pset;
101
@@ -XXX,XX +XXX,XX @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
60
102
}
61
- set &= ct->u.regs;
103
62
+ set &= ct->regs;
104
#define GEN_ATOMIC_HELPER(NAME, OP, NEW) \
63
if (ct->ct & TCG_CT_IALIAS) {
105
-static void * const table_##NAME[16] = { \
64
set &= op->output_pref[ct->alias_index];
106
+static void * const table_##NAME[(MO_SIZE | MO_BSWAP) + 1] = { \
65
}
107
[MO_8] = gen_helper_atomic_##NAME##b, \
66
/* If the combination is not possible, restart. */
108
[MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \
67
if (set == 0) {
109
[MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \
68
- set = ct->u.regs;
110
diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/translate_vx.c.inc
69
+ set = ct->regs;
111
index XXXXXXX..XXXXXXX 100644
70
}
112
--- a/target/s390x/tcg/translate_vx.c.inc
71
*pset = set;
113
+++ b/target/s390x/tcg/translate_vx.c.inc
72
}
114
@@ -XXX,XX +XXX,XX @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr,
73
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
115
{
74
return;
116
const int offs = vec_reg_offset(reg, enr, memop & MO_SIZE);
75
}
117
76
118
- switch (memop) {
77
- dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
119
+ switch ((unsigned)memop) {
78
- dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
120
case ES_8:
79
+ dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
121
tcg_gen_ld8u_i64(dst, cpu_env, offs);
80
+ dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
122
break;
81
82
/* Allocate the output register now. */
83
if (ots->val_type != TEMP_VAL_REG) {
84
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
85
}
86
}
87
88
- temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);
89
+ temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
90
reg = ts->reg;
91
92
- if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
93
+ if (tcg_regset_test_reg(arg_ct->regs, reg)) {
94
/* nothing to do : the constraint is satisfied */
95
} else {
96
allocate_in_reg:
97
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
98
and move the temporary register into it */
99
temp_load(s, ts, tcg_target_available_regs[ts->type],
100
i_allocated_regs, 0);
101
- reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
102
+ reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
103
o_preferred_regs, ts->indirect_base);
104
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
105
/*
106
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
107
&& !const_args[arg_ct->alias_index]) {
108
reg = new_args[arg_ct->alias_index];
109
} else if (arg_ct->ct & TCG_CT_NEWREG) {
110
- reg = tcg_reg_alloc(s, arg_ct->u.regs,
111
+ reg = tcg_reg_alloc(s, arg_ct->regs,
112
i_allocated_regs | o_allocated_regs,
113
op->output_pref[k], ts->indirect_base);
114
} else {
115
- reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
116
+ reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
117
op->output_pref[k], ts->indirect_base);
118
}
119
tcg_regset_set_reg(o_allocated_regs, reg);
120
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
123
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
121
index XXXXXXX..XXXXXXX 100644
124
index XXXXXXX..XXXXXXX 100644
122
--- a/tcg/aarch64/tcg-target.c.inc
125
--- a/tcg/aarch64/tcg-target.c.inc
123
+++ b/tcg/aarch64/tcg-target.c.inc
126
+++ b/tcg/aarch64/tcg-target.c.inc
124
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
127
@@ -XXX,XX +XXX,XX @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
125
switch (*ct_str++) {
128
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
126
case 'r': /* general registers */
129
* TCGMemOpIdx oi, uintptr_t ra)
127
ct->ct |= TCG_CT_REG;
130
*/
128
- ct->u.regs |= 0xffffffffu;
131
-static void * const qemu_ld_helpers[4] = {
129
+ ct->regs |= 0xffffffffu;
132
+static void * const qemu_ld_helpers[MO_SIZE + 1] = {
130
break;
133
[MO_8] = helper_ret_ldub_mmu,
131
case 'w': /* advsimd registers */
134
#ifdef HOST_WORDS_BIGENDIAN
132
ct->ct |= TCG_CT_REG;
135
[MO_16] = helper_be_lduw_mmu,
133
- ct->u.regs |= 0xffffffff00000000ull;
136
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[4] = {
134
+ ct->regs |= 0xffffffff00000000ull;
137
* uintxx_t val, TCGMemOpIdx oi,
135
break;
138
* uintptr_t ra)
136
case 'l': /* qemu_ld / qemu_st address, data_reg */
139
*/
137
ct->ct |= TCG_CT_REG;
140
-static void * const qemu_st_helpers[4] = {
138
- ct->u.regs = 0xffffffffu;
141
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
139
+ ct->regs = 0xffffffffu;
142
[MO_8] = helper_ret_stb_mmu,
140
#ifdef CONFIG_SOFTMMU
143
#ifdef HOST_WORDS_BIGENDIAN
141
/* x0 and x1 will be overwritten when reading the tlb entry,
144
[MO_16] = helper_be_stw_mmu,
142
and x2, and x3 for helper args, better to avoid using them. */
143
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
144
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
145
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
146
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
147
+ tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
148
+ tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
149
+ tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
150
+ tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
151
#endif
152
break;
153
case 'A': /* Valid for arithmetic immediate (positive or negative). */
154
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
145
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
155
index XXXXXXX..XXXXXXX 100644
146
index XXXXXXX..XXXXXXX 100644
156
--- a/tcg/arm/tcg-target.c.inc
147
--- a/tcg/arm/tcg-target.c.inc
157
+++ b/tcg/arm/tcg-target.c.inc
148
+++ b/tcg/arm/tcg-target.c.inc
158
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
149
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
159
150
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
160
case 'r':
151
* int mmu_idx, uintptr_t ra)
161
ct->ct |= TCG_CT_REG;
152
*/
162
- ct->u.regs = 0xffff;
153
-static void * const qemu_ld_helpers[8] = {
163
+ ct->regs = 0xffff;
154
+static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
164
break;
155
[MO_UB] = helper_ret_ldub_mmu,
165
156
[MO_SB] = helper_ret_ldsb_mmu,
166
/* qemu_ld address */
157
#ifdef HOST_WORDS_BIGENDIAN
167
case 'l':
158
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[8] = {
168
ct->ct |= TCG_CT_REG;
159
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
169
- ct->u.regs = 0xffff;
160
* uintxx_t val, int mmu_idx, uintptr_t ra)
170
+ ct->regs = 0xffff;
161
*/
171
#ifdef CONFIG_SOFTMMU
162
-static void * const qemu_st_helpers[4] = {
172
/* r0-r2,lr will be overwritten when reading the tlb entry,
163
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
173
so don't use these. */
164
[MO_8] = helper_ret_stb_mmu,
174
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
165
#ifdef HOST_WORDS_BIGENDIAN
175
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
166
[MO_16] = helper_be_stw_mmu,
176
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
177
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
178
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
179
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
180
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
181
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
182
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
183
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
184
#endif
185
break;
186
187
/* qemu_st address & data */
188
case 's':
189
ct->ct |= TCG_CT_REG;
190
- ct->u.regs = 0xffff;
191
+ ct->regs = 0xffff;
192
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
193
and r0-r1 doing the byte swapping, so don't use these. */
194
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
195
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
196
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
197
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
198
#if defined(CONFIG_SOFTMMU)
199
/* Avoid clashes with registers being used for helper args */
200
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
201
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
202
#if TARGET_LONG_BITS == 64
203
/* Avoid clashes with registers being used for helper args */
204
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
205
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
206
#endif
207
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
208
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
209
#endif
210
break;
211
212
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
167
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
213
index XXXXXXX..XXXXXXX 100644
168
index XXXXXXX..XXXXXXX 100644
214
--- a/tcg/i386/tcg-target.c.inc
169
--- a/tcg/i386/tcg-target.c.inc
215
+++ b/tcg/i386/tcg-target.c.inc
170
+++ b/tcg/i386/tcg-target.c.inc
216
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
171
@@ -XXX,XX +XXX,XX @@ static void tcg_out_nopn(TCGContext *s, int n)
217
switch(*ct_str++) {
172
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
218
case 'a':
173
* int mmu_idx, uintptr_t ra)
219
ct->ct |= TCG_CT_REG;
174
*/
220
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
175
-static void * const qemu_ld_helpers[16] = {
221
+ tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
176
+static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
222
break;
177
[MO_UB] = helper_ret_ldub_mmu,
223
case 'b':
178
[MO_LEUW] = helper_le_lduw_mmu,
224
ct->ct |= TCG_CT_REG;
179
[MO_LEUL] = helper_le_ldul_mmu,
225
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
180
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[16] = {
226
+ tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
181
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
227
break;
182
* uintxx_t val, int mmu_idx, uintptr_t ra)
228
case 'c':
183
*/
229
ct->ct |= TCG_CT_REG;
184
-static void * const qemu_st_helpers[16] = {
230
- tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
185
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
231
+ tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
186
[MO_UB] = helper_ret_stb_mmu,
232
break;
187
[MO_LEUW] = helper_le_stw_mmu,
233
case 'd':
188
[MO_LEUL] = helper_le_stl_mmu,
234
ct->ct |= TCG_CT_REG;
235
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
236
+ tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
237
break;
238
case 'S':
239
ct->ct |= TCG_CT_REG;
240
- tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
241
+ tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
242
break;
243
case 'D':
244
ct->ct |= TCG_CT_REG;
245
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
246
+ tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
247
break;
248
case 'q':
249
/* A register that can be used as a byte operand. */
250
ct->ct |= TCG_CT_REG;
251
- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
252
+ ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
253
break;
254
case 'Q':
255
/* A register with an addressable second byte (e.g. %ah). */
256
ct->ct |= TCG_CT_REG;
257
- ct->u.regs = 0xf;
258
+ ct->regs = 0xf;
259
break;
260
case 'r':
261
/* A general register. */
262
ct->ct |= TCG_CT_REG;
263
- ct->u.regs |= ALL_GENERAL_REGS;
264
+ ct->regs |= ALL_GENERAL_REGS;
265
break;
266
case 'W':
267
/* With TZCNT/LZCNT, we can have operand-size as an input. */
268
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
269
case 'x':
270
/* A vector register. */
271
ct->ct |= TCG_CT_REG;
272
- ct->u.regs |= ALL_VECTOR_REGS;
273
+ ct->regs |= ALL_VECTOR_REGS;
274
break;
275
276
/* qemu_ld/st address constraint */
277
case 'L':
278
ct->ct |= TCG_CT_REG;
279
- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
280
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
281
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
282
+ ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
283
+ tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
284
+ tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
285
break;
286
287
case 'e':
288
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
189
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
289
index XXXXXXX..XXXXXXX 100644
190
index XXXXXXX..XXXXXXX 100644
290
--- a/tcg/mips/tcg-target.c.inc
191
--- a/tcg/mips/tcg-target.c.inc
291
+++ b/tcg/mips/tcg-target.c.inc
192
+++ b/tcg/mips/tcg-target.c.inc
292
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
193
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg)
293
switch(*ct_str++) {
294
case 'r':
295
ct->ct |= TCG_CT_REG;
296
- ct->u.regs = 0xffffffff;
297
+ ct->regs = 0xffffffff;
298
break;
299
case 'L': /* qemu_ld input arg constraint */
300
ct->ct |= TCG_CT_REG;
301
- ct->u.regs = 0xffffffff;
302
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
303
+ ct->regs = 0xffffffff;
304
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
305
#if defined(CONFIG_SOFTMMU)
194
#if defined(CONFIG_SOFTMMU)
306
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
195
#include "../tcg-ldst.c.inc"
307
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
196
308
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
197
-static void * const qemu_ld_helpers[16] = {
309
}
198
+static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
199
[MO_UB] = helper_ret_ldub_mmu,
200
[MO_SB] = helper_ret_ldsb_mmu,
201
[MO_LEUW] = helper_le_lduw_mmu,
202
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[16] = {
310
#endif
203
#endif
311
break;
204
};
312
case 'S': /* qemu_st constraint */
205
313
ct->ct |= TCG_CT_REG;
206
-static void * const qemu_st_helpers[16] = {
314
- ct->u.regs = 0xffffffff;
207
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
315
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
208
[MO_UB] = helper_ret_stb_mmu,
316
+ ct->regs = 0xffffffff;
209
[MO_LEUW] = helper_le_stw_mmu,
317
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
210
[MO_LEUL] = helper_le_stl_mmu,
318
#if defined(CONFIG_SOFTMMU)
319
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
320
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
321
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
322
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
323
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
324
} else {
325
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
326
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
327
}
328
#endif
329
break;
330
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
211
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
331
index XXXXXXX..XXXXXXX 100644
212
index XXXXXXX..XXXXXXX 100644
332
--- a/tcg/ppc/tcg-target.c.inc
213
--- a/tcg/ppc/tcg-target.c.inc
333
+++ b/tcg/ppc/tcg-target.c.inc
214
+++ b/tcg/ppc/tcg-target.c.inc
334
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
215
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
335
switch (*ct_str++) {
336
case 'A': case 'B': case 'C': case 'D':
337
ct->ct |= TCG_CT_REG;
338
- tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
339
+ tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
340
break;
341
case 'r':
342
ct->ct |= TCG_CT_REG;
343
- ct->u.regs = 0xffffffff;
344
+ ct->regs = 0xffffffff;
345
break;
346
case 'v':
347
ct->ct |= TCG_CT_REG;
348
- ct->u.regs = 0xffffffff00000000ull;
349
+ ct->regs = 0xffffffff00000000ull;
350
break;
351
case 'L': /* qemu_ld constraint */
352
ct->ct |= TCG_CT_REG;
353
- ct->u.regs = 0xffffffff;
354
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
355
+ ct->regs = 0xffffffff;
356
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
357
#ifdef CONFIG_SOFTMMU
358
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
359
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
360
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
361
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
362
#endif
216
#endif
363
break;
217
}
364
case 'S': /* qemu_st constraint */
218
365
ct->ct |= TCG_CT_REG;
219
-static const uint32_t qemu_ldx_opc[16] = {
366
- ct->u.regs = 0xffffffff;
220
+static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = {
367
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
221
[MO_UB] = LBZX,
368
+ ct->regs = 0xffffffff;
222
[MO_UW] = LHZX,
369
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
223
[MO_UL] = LWZX,
370
#ifdef CONFIG_SOFTMMU
224
@@ -XXX,XX +XXX,XX @@ static const uint32_t qemu_ldx_opc[16] = {
371
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
225
[MO_BSWAP | MO_Q] = LDBRX,
372
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
226
};
373
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
227
374
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
228
-static const uint32_t qemu_stx_opc[16] = {
375
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
229
+static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = {
376
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
230
[MO_UB] = STBX,
377
#endif
231
[MO_UW] = STHX,
378
break;
232
[MO_UL] = STWX,
379
case 'I':
233
@@ -XXX,XX +XXX,XX @@ static const uint32_t qemu_exts_opc[4] = {
234
/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
235
* int mmu_idx, uintptr_t ra)
236
*/
237
-static void * const qemu_ld_helpers[16] = {
238
+static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
239
[MO_UB] = helper_ret_ldub_mmu,
240
[MO_LEUW] = helper_le_lduw_mmu,
241
[MO_LEUL] = helper_le_ldul_mmu,
242
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[16] = {
243
/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
244
* uintxx_t val, int mmu_idx, uintptr_t ra)
245
*/
246
-static void * const qemu_st_helpers[16] = {
247
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
248
[MO_UB] = helper_ret_stb_mmu,
249
[MO_LEUW] = helper_le_stw_mmu,
250
[MO_LEUL] = helper_le_stl_mmu,
380
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
251
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
381
index XXXXXXX..XXXXXXX 100644
252
index XXXXXXX..XXXXXXX 100644
382
--- a/tcg/riscv/tcg-target.c.inc
253
--- a/tcg/riscv/tcg-target.c.inc
383
+++ b/tcg/riscv/tcg-target.c.inc
254
+++ b/tcg/riscv/tcg-target.c.inc
384
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
255
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
385
switch (*ct_str++) {
256
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
386
case 'r':
257
* TCGMemOpIdx oi, uintptr_t ra)
387
ct->ct |= TCG_CT_REG;
258
*/
388
- ct->u.regs = 0xffffffff;
259
-static void * const qemu_ld_helpers[8] = {
389
+ ct->regs = 0xffffffff;
260
+static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
390
break;
261
[MO_UB] = helper_ret_ldub_mmu,
391
case 'L':
262
[MO_SB] = helper_ret_ldsb_mmu,
392
/* qemu_ld/qemu_st constraint */
263
#ifdef HOST_WORDS_BIGENDIAN
393
ct->ct |= TCG_CT_REG;
264
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[8] = {
394
- ct->u.regs = 0xffffffff;
265
* uintxx_t val, TCGMemOpIdx oi,
395
+ ct->regs = 0xffffffff;
266
* uintptr_t ra)
396
/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
267
*/
397
#if defined(CONFIG_SOFTMMU)
268
-static void * const qemu_st_helpers[4] = {
398
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
269
+static void * const qemu_st_helpers[MO_SIZE + 1] = {
399
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
270
[MO_8] = helper_ret_stb_mmu,
400
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
271
#ifdef HOST_WORDS_BIGENDIAN
401
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
272
[MO_16] = helper_be_stw_mmu,
402
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
403
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
404
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
405
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
406
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
407
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
408
#endif
409
break;
410
case 'I':
411
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
273
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
412
index XXXXXXX..XXXXXXX 100644
274
index XXXXXXX..XXXXXXX 100644
413
--- a/tcg/s390/tcg-target.c.inc
275
--- a/tcg/s390/tcg-target.c.inc
414
+++ b/tcg/s390/tcg-target.c.inc
276
+++ b/tcg/s390/tcg-target.c.inc
415
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
277
@@ -XXX,XX +XXX,XX @@ static const uint8_t tcg_cond_to_ltr_cond[] = {
416
switch (*ct_str++) {
278
};
417
case 'r': /* all registers */
279
418
ct->ct |= TCG_CT_REG;
280
#ifdef CONFIG_SOFTMMU
419
- ct->u.regs = 0xffff;
281
-static void * const qemu_ld_helpers[16] = {
420
+ ct->regs = 0xffff;
282
+static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = {
421
break;
283
[MO_UB] = helper_ret_ldub_mmu,
422
case 'L': /* qemu_ld/st constraint */
284
[MO_SB] = helper_ret_ldsb_mmu,
423
ct->ct |= TCG_CT_REG;
285
[MO_LEUW] = helper_le_lduw_mmu,
424
- ct->u.regs = 0xffff;
286
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[16] = {
425
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
287
[MO_BEQ] = helper_be_ldq_mmu,
426
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
288
};
427
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
289
428
+ ct->regs = 0xffff;
290
-static void * const qemu_st_helpers[16] = {
429
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
291
+static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
430
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
292
[MO_UB] = helper_ret_stb_mmu,
431
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
293
[MO_LEUW] = helper_le_stw_mmu,
432
break;
294
[MO_LEUL] = helper_le_stl_mmu,
433
case 'a': /* force R2 for division */
434
ct->ct |= TCG_CT_REG;
435
- ct->u.regs = 0;
436
- tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
437
+ ct->regs = 0;
438
+ tcg_regset_set_reg(ct->regs, TCG_REG_R2);
439
break;
440
case 'b': /* force R3 for division */
441
ct->ct |= TCG_CT_REG;
442
- ct->u.regs = 0;
443
- tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
444
+ ct->regs = 0;
445
+ tcg_regset_set_reg(ct->regs, TCG_REG_R3);
446
break;
447
case 'A':
448
ct->ct |= TCG_CT_CONST_S33;
449
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
295
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
450
index XXXXXXX..XXXXXXX 100644
296
index XXXXXXX..XXXXXXX 100644
451
--- a/tcg/sparc/tcg-target.c.inc
297
--- a/tcg/sparc/tcg-target.c.inc
452
+++ b/tcg/sparc/tcg-target.c.inc
298
+++ b/tcg/sparc/tcg-target.c.inc
453
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
299
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
454
switch (*ct_str++) {
300
}
455
case 'r':
301
456
ct->ct |= TCG_CT_REG;
302
#ifdef CONFIG_SOFTMMU
457
- ct->u.regs = 0xffffffff;
303
-static const tcg_insn_unit *qemu_ld_trampoline[16];
458
+ ct->regs = 0xffffffff;
304
-static const tcg_insn_unit *qemu_st_trampoline[16];
459
break;
305
+static const tcg_insn_unit *qemu_ld_trampoline[(MO_SSIZE | MO_BSWAP) + 1];
460
case 'R':
306
+static const tcg_insn_unit *qemu_st_trampoline[(MO_SIZE | MO_BSWAP) + 1];
461
ct->ct |= TCG_CT_REG;
307
462
- ct->u.regs = ALL_64;
308
static void emit_extend(TCGContext *s, TCGReg r, int op)
463
+ ct->regs = ALL_64;
309
{
464
break;
310
@@ -XXX,XX +XXX,XX @@ static void emit_extend(TCGContext *s, TCGReg r, int op)
465
case 'A': /* qemu_ld/st address constraint */
311
466
ct->ct |= TCG_CT_REG;
312
static void build_trampolines(TCGContext *s)
467
- ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
313
{
468
+ ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
314
- static void * const qemu_ld_helpers[16] = {
469
reserve_helpers:
315
+ static void * const qemu_ld_helpers[] = {
470
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
316
[MO_UB] = helper_ret_ldub_mmu,
471
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
317
[MO_SB] = helper_ret_ldsb_mmu,
472
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
318
[MO_LEUW] = helper_le_lduw_mmu,
473
+ tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
319
@@ -XXX,XX +XXX,XX @@ static void build_trampolines(TCGContext *s)
474
+ tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
320
[MO_BEUL] = helper_be_ldul_mmu,
475
+ tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
321
[MO_BEQ] = helper_be_ldq_mmu,
476
break;
322
};
477
case 's': /* qemu_st data 32-bit constraint */
323
- static void * const qemu_st_helpers[16] = {
478
ct->ct |= TCG_CT_REG;
324
+ static void * const qemu_st_helpers[] = {
479
- ct->u.regs = 0xffffffff;
325
[MO_UB] = helper_ret_stb_mmu,
480
+ ct->regs = 0xffffffff;
326
[MO_LEUW] = helper_le_stw_mmu,
481
goto reserve_helpers;
327
[MO_LEUL] = helper_le_stl_mmu,
482
case 'S': /* qemu_st data 64-bit constraint */
328
@@ -XXX,XX +XXX,XX @@ static void build_trampolines(TCGContext *s)
483
ct->ct |= TCG_CT_REG;
329
int i;
484
- ct->u.regs = ALL_64;
330
TCGReg ra;
485
+ ct->regs = ALL_64;
331
486
goto reserve_helpers;
332
- for (i = 0; i < 16; ++i) {
487
case 'I':
333
+ for (i = 0; i < ARRAY_SIZE(qemu_ld_helpers); ++i) {
488
ct->ct |= TCG_CT_CONST_S11;
334
if (qemu_ld_helpers[i] == NULL) {
489
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
335
continue;
490
index XXXXXXX..XXXXXXX 100644
336
}
491
--- a/tcg/tci/tcg-target.c.inc
337
@@ -XXX,XX +XXX,XX @@ static void build_trampolines(TCGContext *s)
492
+++ b/tcg/tci/tcg-target.c.inc
338
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);
493
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
339
}
494
case 'L': /* qemu_ld constraint */
340
495
case 'S': /* qemu_st constraint */
341
- for (i = 0; i < 16; ++i) {
496
ct->ct |= TCG_CT_REG;
342
+ for (i = 0; i < ARRAY_SIZE(qemu_st_helpers); ++i) {
497
- ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
343
if (qemu_st_helpers[i] == NULL) {
498
+ ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
344
continue;
499
break;
345
}
500
default:
346
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index,
501
return NULL;
347
}
348
#endif /* CONFIG_SOFTMMU */
349
350
-static const int qemu_ld_opc[16] = {
351
+static const int qemu_ld_opc[(MO_SSIZE | MO_BSWAP) + 1] = {
352
[MO_UB] = LDUB,
353
[MO_SB] = LDSB,
354
355
@@ -XXX,XX +XXX,XX @@ static const int qemu_ld_opc[16] = {
356
[MO_LEQ] = LDX_LE,
357
};
358
359
-static const int qemu_st_opc[16] = {
360
+static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = {
361
[MO_UB] = STB,
362
363
[MO_BEUW] = STH,
502
--
364
--
503
2.25.1
365
2.25.1
504
366
505
367
diff view generated by jsdifflib
[PULL 04/11] tcg: Remove TCG_CT_REG
[PULL 06/28] tcg: Rename TCGMemOpIdx to MemOpIdx
1
This wasn't actually used for anything, really. All variable
1
We're about to move this out of tcg.h, so rename it
2
operands must accept registers, and which are indicated by the
2
as we did when moving MemOp.
3
set in TCGArgConstraint.regs.
4
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
---
7
include/tcg/tcg.h | 1 -
8
accel/tcg/atomic_template.h | 24 +++++------
8
tcg/tcg.c | 15 ++++-----------
9
include/tcg/tcg.h | 74 ++++++++++++++++-----------------
9
tcg/aarch64/tcg-target.c.inc | 3 ---
10
accel/tcg/cputlb.c | 78 +++++++++++++++++------------------
10
tcg/arm/tcg-target.c.inc | 3 ---
11
accel/tcg/user-exec.c | 2 +-
11
tcg/i386/tcg-target.c.inc | 11 -----------
12
target/arm/helper-a64.c | 16 +++----
12
tcg/mips/tcg-target.c.inc | 3 ---
13
target/arm/m_helper.c | 2 +-
13
tcg/ppc/tcg-target.c.inc | 5 -----
14
target/i386/tcg/mem_helper.c | 4 +-
14
tcg/riscv/tcg-target.c.inc | 2 --
15
target/m68k/op_helper.c | 2 +-
15
tcg/s390/tcg-target.c.inc | 4 ----
16
target/mips/tcg/msa_helper.c | 6 +--
16
tcg/sparc/tcg-target.c.inc | 5 -----
17
target/s390x/tcg/mem_helper.c | 20 ++++-----
17
tcg/tci/tcg-target.c.inc | 1 -
18
target/sparc/ldst_helper.c | 2 +-
18
11 files changed, 4 insertions(+), 49 deletions(-)
19
tcg/optimize.c | 2 +-
20
tcg/tcg-op.c | 12 +++---
21
tcg/tcg.c | 2 +-
22
tcg/tci.c | 14 +++----
23
accel/tcg/atomic_common.c.inc | 6 +--
24
tcg/aarch64/tcg-target.c.inc | 14 +++----
25
tcg/arm/tcg-target.c.inc | 10 ++---
26
tcg/i386/tcg-target.c.inc | 10 ++---
27
tcg/mips/tcg-target.c.inc | 12 +++---
28
tcg/ppc/tcg-target.c.inc | 10 ++---
29
tcg/riscv/tcg-target.c.inc | 16 +++----
30
tcg/s390/tcg-target.c.inc | 10 ++---
31
tcg/sparc/tcg-target.c.inc | 4 +-
32
tcg/tcg-ldst.c.inc | 2 +-
33
25 files changed, 177 insertions(+), 177 deletions(-)
19
34
35
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/accel/tcg/atomic_template.h
38
+++ b/accel/tcg/atomic_template.h
39
@@ -XXX,XX +XXX,XX @@
40
41
ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
42
ABI_TYPE cmpv, ABI_TYPE newv,
43
- TCGMemOpIdx oi, uintptr_t retaddr)
44
+ MemOpIdx oi, uintptr_t retaddr)
45
{
46
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
47
PAGE_READ | PAGE_WRITE, retaddr);
48
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
49
#if DATA_SIZE >= 16
50
#if HAVE_ATOMIC128
51
ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
52
- TCGMemOpIdx oi, uintptr_t retaddr)
53
+ MemOpIdx oi, uintptr_t retaddr)
54
{
55
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
56
PAGE_READ, retaddr);
57
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
58
}
59
60
void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
61
- TCGMemOpIdx oi, uintptr_t retaddr)
62
+ MemOpIdx oi, uintptr_t retaddr)
63
{
64
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
65
PAGE_WRITE, retaddr);
66
@@ -XXX,XX +XXX,XX @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
67
#endif
68
#else
69
ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
70
- TCGMemOpIdx oi, uintptr_t retaddr)
71
+ MemOpIdx oi, uintptr_t retaddr)
72
{
73
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
74
PAGE_READ | PAGE_WRITE, retaddr);
75
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
76
77
#define GEN_ATOMIC_HELPER(X) \
78
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
79
- ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \
80
+ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
81
{ \
82
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
83
PAGE_READ | PAGE_WRITE, retaddr); \
84
@@ -XXX,XX +XXX,XX @@ GEN_ATOMIC_HELPER(xor_fetch)
85
*/
86
#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
87
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
88
- ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \
89
+ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
90
{ \
91
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
92
PAGE_READ | PAGE_WRITE, retaddr); \
93
@@ -XXX,XX +XXX,XX @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new)
94
95
ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
96
ABI_TYPE cmpv, ABI_TYPE newv,
97
- TCGMemOpIdx oi, uintptr_t retaddr)
98
+ MemOpIdx oi, uintptr_t retaddr)
99
{
100
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
101
PAGE_READ | PAGE_WRITE, retaddr);
102
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
103
#if DATA_SIZE >= 16
104
#if HAVE_ATOMIC128
105
ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
106
- TCGMemOpIdx oi, uintptr_t retaddr)
107
+ MemOpIdx oi, uintptr_t retaddr)
108
{
109
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
110
PAGE_READ, retaddr);
111
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
112
}
113
114
void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
115
- TCGMemOpIdx oi, uintptr_t retaddr)
116
+ MemOpIdx oi, uintptr_t retaddr)
117
{
118
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
119
PAGE_WRITE, retaddr);
120
@@ -XXX,XX +XXX,XX @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
121
#endif
122
#else
123
ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
124
- TCGMemOpIdx oi, uintptr_t retaddr)
125
+ MemOpIdx oi, uintptr_t retaddr)
126
{
127
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
128
PAGE_READ | PAGE_WRITE, retaddr);
129
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
130
131
#define GEN_ATOMIC_HELPER(X) \
132
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
133
- ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \
134
+ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
135
{ \
136
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
137
PAGE_READ | PAGE_WRITE, retaddr); \
138
@@ -XXX,XX +XXX,XX @@ GEN_ATOMIC_HELPER(xor_fetch)
139
*/
140
#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
141
ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
142
- ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \
143
+ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
144
{ \
145
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
146
PAGE_READ | PAGE_WRITE, retaddr); \
20
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
147
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
21
index XXXXXXX..XXXXXXX 100644
148
index XXXXXXX..XXXXXXX 100644
22
--- a/include/tcg/tcg.h
149
--- a/include/tcg/tcg.h
23
+++ b/include/tcg/tcg.h
150
+++ b/include/tcg/tcg.h
24
@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
151
@@ -XXX,XX +XXX,XX @@ static inline size_t tcg_current_code_size(TCGContext *s)
25
#define TCG_CT_ALIAS 0x80
152
}
26
#define TCG_CT_IALIAS 0x40
153
27
#define TCG_CT_NEWREG 0x20 /* output requires a new register */
154
/* Combine the MemOp and mmu_idx parameters into a single value. */
28
-#define TCG_CT_REG 0x01
155
-typedef uint32_t TCGMemOpIdx;
29
#define TCG_CT_CONST 0x02 /* any constant of register size */
156
+typedef uint32_t MemOpIdx;
30
157
31
typedef struct TCGArgConstraint {
158
/**
159
* make_memop_idx
160
@@ -XXX,XX +XXX,XX @@ typedef uint32_t TCGMemOpIdx;
161
*
162
* Encode these values into a single parameter.
163
*/
164
-static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
165
+static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx)
166
{
167
tcg_debug_assert(idx <= 15);
168
return (op << 4) | idx;
169
@@ -XXX,XX +XXX,XX @@ static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx)
170
*
171
* Extract the memory operation from the combined value.
172
*/
173
-static inline MemOp get_memop(TCGMemOpIdx oi)
174
+static inline MemOp get_memop(MemOpIdx oi)
175
{
176
return oi >> 4;
177
}
178
@@ -XXX,XX +XXX,XX @@ static inline MemOp get_memop(TCGMemOpIdx oi)
179
*
180
* Extract the mmu index from the combined value.
181
*/
182
-static inline unsigned get_mmuidx(TCGMemOpIdx oi)
183
+static inline unsigned get_mmuidx(MemOpIdx oi)
184
{
185
return oi & 15;
186
}
187
@@ -XXX,XX +XXX,XX @@ uint64_t dup_const(unsigned vece, uint64_t c);
188
#ifdef CONFIG_SOFTMMU
189
/* Value zero-extended to tcg register size. */
190
tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
191
- TCGMemOpIdx oi, uintptr_t retaddr);
192
+ MemOpIdx oi, uintptr_t retaddr);
193
tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
194
- TCGMemOpIdx oi, uintptr_t retaddr);
195
+ MemOpIdx oi, uintptr_t retaddr);
196
tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
197
- TCGMemOpIdx oi, uintptr_t retaddr);
198
+ MemOpIdx oi, uintptr_t retaddr);
199
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
200
- TCGMemOpIdx oi, uintptr_t retaddr);
201
+ MemOpIdx oi, uintptr_t retaddr);
202
tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
203
- TCGMemOpIdx oi, uintptr_t retaddr);
204
+ MemOpIdx oi, uintptr_t retaddr);
205
tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
206
- TCGMemOpIdx oi, uintptr_t retaddr);
207
+ MemOpIdx oi, uintptr_t retaddr);
208
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
209
- TCGMemOpIdx oi, uintptr_t retaddr);
210
+ MemOpIdx oi, uintptr_t retaddr);
211
212
/* Value sign-extended to tcg register size. */
213
tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
214
- TCGMemOpIdx oi, uintptr_t retaddr);
215
+ MemOpIdx oi, uintptr_t retaddr);
216
tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
217
- TCGMemOpIdx oi, uintptr_t retaddr);
218
+ MemOpIdx oi, uintptr_t retaddr);
219
tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
220
- TCGMemOpIdx oi, uintptr_t retaddr);
221
+ MemOpIdx oi, uintptr_t retaddr);
222
tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
223
- TCGMemOpIdx oi, uintptr_t retaddr);
224
+ MemOpIdx oi, uintptr_t retaddr);
225
tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
226
- TCGMemOpIdx oi, uintptr_t retaddr);
227
+ MemOpIdx oi, uintptr_t retaddr);
228
229
void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
230
- TCGMemOpIdx oi, uintptr_t retaddr);
231
+ MemOpIdx oi, uintptr_t retaddr);
232
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
233
- TCGMemOpIdx oi, uintptr_t retaddr);
234
+ MemOpIdx oi, uintptr_t retaddr);
235
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
236
- TCGMemOpIdx oi, uintptr_t retaddr);
237
+ MemOpIdx oi, uintptr_t retaddr);
238
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
239
- TCGMemOpIdx oi, uintptr_t retaddr);
240
+ MemOpIdx oi, uintptr_t retaddr);
241
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
242
- TCGMemOpIdx oi, uintptr_t retaddr);
243
+ MemOpIdx oi, uintptr_t retaddr);
244
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
245
- TCGMemOpIdx oi, uintptr_t retaddr);
246
+ MemOpIdx oi, uintptr_t retaddr);
247
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
248
- TCGMemOpIdx oi, uintptr_t retaddr);
249
+ MemOpIdx oi, uintptr_t retaddr);
250
251
/* Temporary aliases until backends are converted. */
252
#ifdef TARGET_WORDS_BIGENDIAN
253
@@ -XXX,XX +XXX,XX @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
254
255
uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
256
uint32_t cmpv, uint32_t newv,
257
- TCGMemOpIdx oi, uintptr_t retaddr);
258
+ MemOpIdx oi, uintptr_t retaddr);
259
uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
260
uint32_t cmpv, uint32_t newv,
261
- TCGMemOpIdx oi, uintptr_t retaddr);
262
+ MemOpIdx oi, uintptr_t retaddr);
263
uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
264
uint32_t cmpv, uint32_t newv,
265
- TCGMemOpIdx oi, uintptr_t retaddr);
266
+ MemOpIdx oi, uintptr_t retaddr);
267
uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
268
uint64_t cmpv, uint64_t newv,
269
- TCGMemOpIdx oi, uintptr_t retaddr);
270
+ MemOpIdx oi, uintptr_t retaddr);
271
uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
272
uint32_t cmpv, uint32_t newv,
273
- TCGMemOpIdx oi, uintptr_t retaddr);
274
+ MemOpIdx oi, uintptr_t retaddr);
275
uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
276
uint32_t cmpv, uint32_t newv,
277
- TCGMemOpIdx oi, uintptr_t retaddr);
278
+ MemOpIdx oi, uintptr_t retaddr);
279
uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
280
uint64_t cmpv, uint64_t newv,
281
- TCGMemOpIdx oi, uintptr_t retaddr);
282
+ MemOpIdx oi, uintptr_t retaddr);
283
284
#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
285
TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \
286
(CPUArchState *env, target_ulong addr, TYPE val, \
287
- TCGMemOpIdx oi, uintptr_t retaddr);
288
+ MemOpIdx oi, uintptr_t retaddr);
289
290
#ifdef CONFIG_ATOMIC64
291
#define GEN_ATOMIC_HELPER_ALL(NAME) \
292
@@ -XXX,XX +XXX,XX @@ GEN_ATOMIC_HELPER_ALL(xchg)
293
294
Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
295
Int128 cmpv, Int128 newv,
296
- TCGMemOpIdx oi, uintptr_t retaddr);
297
+ MemOpIdx oi, uintptr_t retaddr);
298
Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
299
Int128 cmpv, Int128 newv,
300
- TCGMemOpIdx oi, uintptr_t retaddr);
301
+ MemOpIdx oi, uintptr_t retaddr);
302
303
Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
304
- TCGMemOpIdx oi, uintptr_t retaddr);
305
+ MemOpIdx oi, uintptr_t retaddr);
306
Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
307
- TCGMemOpIdx oi, uintptr_t retaddr);
308
+ MemOpIdx oi, uintptr_t retaddr);
309
void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
310
- TCGMemOpIdx oi, uintptr_t retaddr);
311
+ MemOpIdx oi, uintptr_t retaddr);
312
void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
313
- TCGMemOpIdx oi, uintptr_t retaddr);
314
+ MemOpIdx oi, uintptr_t retaddr);
315
316
#ifdef CONFIG_DEBUG_TCG
317
void tcg_assert_listed_vecop(TCGOpcode);
318
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
319
index XXXXXXX..XXXXXXX 100644
320
--- a/accel/tcg/cputlb.c
321
+++ b/accel/tcg/cputlb.c
322
@@ -XXX,XX +XXX,XX @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
323
* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
324
*/
325
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
326
- TCGMemOpIdx oi, int size, int prot,
327
+ MemOpIdx oi, int size, int prot,
328
uintptr_t retaddr)
329
{
330
size_t mmu_idx = get_mmuidx(oi);
331
@@ -XXX,XX +XXX,XX @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
332
*/
333
334
typedef uint64_t FullLoadHelper(CPUArchState *env, target_ulong addr,
335
- TCGMemOpIdx oi, uintptr_t retaddr);
336
+ MemOpIdx oi, uintptr_t retaddr);
337
338
static inline uint64_t QEMU_ALWAYS_INLINE
339
load_memop(const void *haddr, MemOp op)
340
@@ -XXX,XX +XXX,XX @@ load_memop(const void *haddr, MemOp op)
341
}
342
343
static inline uint64_t QEMU_ALWAYS_INLINE
344
-load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
345
+load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
346
uintptr_t retaddr, MemOp op, bool code_read,
347
FullLoadHelper *full_load)
348
{
349
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
350
*/
351
352
static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr,
353
- TCGMemOpIdx oi, uintptr_t retaddr)
354
+ MemOpIdx oi, uintptr_t retaddr)
355
{
356
return load_helper(env, addr, oi, retaddr, MO_UB, false, full_ldub_mmu);
357
}
358
359
tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
360
- TCGMemOpIdx oi, uintptr_t retaddr)
361
+ MemOpIdx oi, uintptr_t retaddr)
362
{
363
return full_ldub_mmu(env, addr, oi, retaddr);
364
}
365
366
static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr,
367
- TCGMemOpIdx oi, uintptr_t retaddr)
368
+ MemOpIdx oi, uintptr_t retaddr)
369
{
370
return load_helper(env, addr, oi, retaddr, MO_LEUW, false,
371
full_le_lduw_mmu);
372
}
373
374
tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
375
- TCGMemOpIdx oi, uintptr_t retaddr)
376
+ MemOpIdx oi, uintptr_t retaddr)
377
{
378
return full_le_lduw_mmu(env, addr, oi, retaddr);
379
}
380
381
static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr,
382
- TCGMemOpIdx oi, uintptr_t retaddr)
383
+ MemOpIdx oi, uintptr_t retaddr)
384
{
385
return load_helper(env, addr, oi, retaddr, MO_BEUW, false,
386
full_be_lduw_mmu);
387
}
388
389
tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
390
- TCGMemOpIdx oi, uintptr_t retaddr)
391
+ MemOpIdx oi, uintptr_t retaddr)
392
{
393
return full_be_lduw_mmu(env, addr, oi, retaddr);
394
}
395
396
static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr,
397
- TCGMemOpIdx oi, uintptr_t retaddr)
398
+ MemOpIdx oi, uintptr_t retaddr)
399
{
400
return load_helper(env, addr, oi, retaddr, MO_LEUL, false,
401
full_le_ldul_mmu);
402
}
403
404
tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
405
- TCGMemOpIdx oi, uintptr_t retaddr)
406
+ MemOpIdx oi, uintptr_t retaddr)
407
{
408
return full_le_ldul_mmu(env, addr, oi, retaddr);
409
}
410
411
static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr,
412
- TCGMemOpIdx oi, uintptr_t retaddr)
413
+ MemOpIdx oi, uintptr_t retaddr)
414
{
415
return load_helper(env, addr, oi, retaddr, MO_BEUL, false,
416
full_be_ldul_mmu);
417
}
418
419
tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
420
- TCGMemOpIdx oi, uintptr_t retaddr)
421
+ MemOpIdx oi, uintptr_t retaddr)
422
{
423
return full_be_ldul_mmu(env, addr, oi, retaddr);
424
}
425
426
uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
427
- TCGMemOpIdx oi, uintptr_t retaddr)
428
+ MemOpIdx oi, uintptr_t retaddr)
429
{
430
return load_helper(env, addr, oi, retaddr, MO_LEQ, false,
431
helper_le_ldq_mmu);
432
}
433
434
uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
435
- TCGMemOpIdx oi, uintptr_t retaddr)
436
+ MemOpIdx oi, uintptr_t retaddr)
437
{
438
return load_helper(env, addr, oi, retaddr, MO_BEQ, false,
439
helper_be_ldq_mmu);
440
@@ -XXX,XX +XXX,XX @@ uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
441
442
443
tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
444
- TCGMemOpIdx oi, uintptr_t retaddr)
445
+ MemOpIdx oi, uintptr_t retaddr)
446
{
447
return (int8_t)helper_ret_ldub_mmu(env, addr, oi, retaddr);
448
}
449
450
tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
451
- TCGMemOpIdx oi, uintptr_t retaddr)
452
+ MemOpIdx oi, uintptr_t retaddr)
453
{
454
return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr);
455
}
456
457
tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
458
- TCGMemOpIdx oi, uintptr_t retaddr)
459
+ MemOpIdx oi, uintptr_t retaddr)
460
{
461
return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr);
462
}
463
464
tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
465
- TCGMemOpIdx oi, uintptr_t retaddr)
466
+ MemOpIdx oi, uintptr_t retaddr)
467
{
468
return (int32_t)helper_le_ldul_mmu(env, addr, oi, retaddr);
469
}
470
471
tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
472
- TCGMemOpIdx oi, uintptr_t retaddr)
473
+ MemOpIdx oi, uintptr_t retaddr)
474
{
475
return (int32_t)helper_be_ldul_mmu(env, addr, oi, retaddr);
476
}
477
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
478
MemOp op, FullLoadHelper *full_load)
479
{
480
uint16_t meminfo;
481
- TCGMemOpIdx oi;
482
+ MemOpIdx oi;
483
uint64_t ret;
484
485
meminfo = trace_mem_get_info(op, mmu_idx, false);
486
@@ -XXX,XX +XXX,XX @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
487
uintptr_t index, index2;
488
CPUTLBEntry *entry, *entry2;
489
target_ulong page2, tlb_addr, tlb_addr2;
490
- TCGMemOpIdx oi;
491
+ MemOpIdx oi;
492
size_t size2;
493
int i;
494
495
@@ -XXX,XX +XXX,XX @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
496
497
static inline void QEMU_ALWAYS_INLINE
498
store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
499
- TCGMemOpIdx oi, uintptr_t retaddr, MemOp op)
500
+ MemOpIdx oi, uintptr_t retaddr, MemOp op)
501
{
502
uintptr_t mmu_idx = get_mmuidx(oi);
503
uintptr_t index = tlb_index(env, mmu_idx, addr);
504
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
505
506
void __attribute__((noinline))
507
helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
508
- TCGMemOpIdx oi, uintptr_t retaddr)
509
+ MemOpIdx oi, uintptr_t retaddr)
510
{
511
store_helper(env, addr, val, oi, retaddr, MO_UB);
512
}
513
514
void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
515
- TCGMemOpIdx oi, uintptr_t retaddr)
516
+ MemOpIdx oi, uintptr_t retaddr)
517
{
518
store_helper(env, addr, val, oi, retaddr, MO_LEUW);
519
}
520
521
void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
522
- TCGMemOpIdx oi, uintptr_t retaddr)
523
+ MemOpIdx oi, uintptr_t retaddr)
524
{
525
store_helper(env, addr, val, oi, retaddr, MO_BEUW);
526
}
527
528
void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
529
- TCGMemOpIdx oi, uintptr_t retaddr)
530
+ MemOpIdx oi, uintptr_t retaddr)
531
{
532
store_helper(env, addr, val, oi, retaddr, MO_LEUL);
533
}
534
535
void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
536
- TCGMemOpIdx oi, uintptr_t retaddr)
537
+ MemOpIdx oi, uintptr_t retaddr)
538
{
539
store_helper(env, addr, val, oi, retaddr, MO_BEUL);
540
}
541
542
void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
543
- TCGMemOpIdx oi, uintptr_t retaddr)
544
+ MemOpIdx oi, uintptr_t retaddr)
545
{
546
store_helper(env, addr, val, oi, retaddr, MO_LEQ);
547
}
548
549
void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
550
- TCGMemOpIdx oi, uintptr_t retaddr)
551
+ MemOpIdx oi, uintptr_t retaddr)
552
{
553
store_helper(env, addr, val, oi, retaddr, MO_BEQ);
554
}
555
@@ -XXX,XX +XXX,XX @@ static inline void QEMU_ALWAYS_INLINE
556
cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
557
int mmu_idx, uintptr_t retaddr, MemOp op)
558
{
559
- TCGMemOpIdx oi;
560
+ MemOpIdx oi;
561
uint16_t meminfo;
562
563
meminfo = trace_mem_get_info(op, mmu_idx, true);
564
@@ -XXX,XX +XXX,XX @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
565
/* Code access functions. */
566
567
static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr,
568
- TCGMemOpIdx oi, uintptr_t retaddr)
569
+ MemOpIdx oi, uintptr_t retaddr)
570
{
571
return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_code);
572
}
573
574
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
575
{
576
- TCGMemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
577
+ MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true));
578
return full_ldub_code(env, addr, oi, 0);
579
}
580
581
static uint64_t full_lduw_code(CPUArchState *env, target_ulong addr,
582
- TCGMemOpIdx oi, uintptr_t retaddr)
583
+ MemOpIdx oi, uintptr_t retaddr)
584
{
585
return load_helper(env, addr, oi, retaddr, MO_TEUW, true, full_lduw_code);
586
}
587
588
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
589
{
590
- TCGMemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
591
+ MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
592
return full_lduw_code(env, addr, oi, 0);
593
}
594
595
static uint64_t full_ldl_code(CPUArchState *env, target_ulong addr,
596
- TCGMemOpIdx oi, uintptr_t retaddr)
597
+ MemOpIdx oi, uintptr_t retaddr)
598
{
599
return load_helper(env, addr, oi, retaddr, MO_TEUL, true, full_ldl_code);
600
}
601
602
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
603
{
604
- TCGMemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
605
+ MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
606
return full_ldl_code(env, addr, oi, 0);
607
}
608
609
static uint64_t full_ldq_code(CPUArchState *env, target_ulong addr,
610
- TCGMemOpIdx oi, uintptr_t retaddr)
611
+ MemOpIdx oi, uintptr_t retaddr)
612
{
613
return load_helper(env, addr, oi, retaddr, MO_TEQ, true, full_ldq_code);
614
}
615
616
uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
617
{
618
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
619
+ MemOpIdx oi = make_memop_idx(MO_TEQ, cpu_mmu_index(env, true));
620
return full_ldq_code(env, addr, oi, 0);
621
}
622
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
623
index XXXXXXX..XXXXXXX 100644
624
--- a/accel/tcg/user-exec.c
625
+++ b/accel/tcg/user-exec.c
626
@@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr)
627
* @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE.
628
*/
629
static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
630
- TCGMemOpIdx oi, int size, int prot,
631
+ MemOpIdx oi, int size, int prot,
632
uintptr_t retaddr)
633
{
634
/* Enforce qemu required alignment. */
635
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
636
index XXXXXXX..XXXXXXX 100644
637
--- a/target/arm/helper-a64.c
638
+++ b/target/arm/helper-a64.c
639
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
640
clear_helper_retaddr();
641
#else
642
int mem_idx = cpu_mmu_index(env, false);
643
- TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
644
- TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
645
+ MemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
646
+ MemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
647
648
o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
649
o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
650
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr,
651
uintptr_t ra = GETPC();
652
bool success;
653
int mem_idx;
654
- TCGMemOpIdx oi;
655
+ MemOpIdx oi;
656
657
assert(HAVE_CMPXCHG128);
658
659
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
660
clear_helper_retaddr();
661
#else
662
int mem_idx = cpu_mmu_index(env, false);
663
- TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
664
- TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
665
+ MemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
666
+ MemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
667
668
o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
669
o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
670
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
671
uintptr_t ra = GETPC();
672
bool success;
673
int mem_idx;
674
- TCGMemOpIdx oi;
675
+ MemOpIdx oi;
676
677
assert(HAVE_CMPXCHG128);
678
679
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
680
Int128 oldv, cmpv, newv;
681
uintptr_t ra = GETPC();
682
int mem_idx;
683
- TCGMemOpIdx oi;
684
+ MemOpIdx oi;
685
686
assert(HAVE_CMPXCHG128);
687
688
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
689
Int128 oldv, cmpv, newv;
690
uintptr_t ra = GETPC();
691
int mem_idx;
692
- TCGMemOpIdx oi;
693
+ MemOpIdx oi;
694
695
assert(HAVE_CMPXCHG128);
696
697
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
698
index XXXXXXX..XXXXXXX 100644
699
--- a/target/arm/m_helper.c
700
+++ b/target/arm/m_helper.c
701
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
702
703
{
704
bool threadmode, spsel;
705
- TCGMemOpIdx oi;
706
+ MemOpIdx oi;
707
ARMMMUIdx mmu_idx;
708
uint32_t *frame_sp_p;
709
uint32_t frameptr;
710
diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c
711
index XXXXXXX..XXXXXXX 100644
712
--- a/target/i386/tcg/mem_helper.c
713
+++ b/target/i386/tcg/mem_helper.c
714
@@ -XXX,XX +XXX,XX @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0)
715
{
716
uintptr_t ra = GETPC();
717
int mem_idx = cpu_mmu_index(env, false);
718
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
719
+ MemOpIdx oi = make_memop_idx(MO_TEQ, mem_idx);
720
oldv = cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra);
721
}
722
723
@@ -XXX,XX +XXX,XX @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0)
724
Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]);
725
726
int mem_idx = cpu_mmu_index(env, false);
727
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
728
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
729
Int128 oldv = cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi, ra);
730
731
if (int128_eq(oldv, cmpv)) {
732
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
733
index XXXXXXX..XXXXXXX 100644
734
--- a/target/m68k/op_helper.c
735
+++ b/target/m68k/op_helper.c
736
@@ -XXX,XX +XXX,XX @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
737
uintptr_t ra = GETPC();
738
#if defined(CONFIG_ATOMIC64)
739
int mmu_idx = cpu_mmu_index(env, 0);
740
- TCGMemOpIdx oi = make_memop_idx(MO_BEQ, mmu_idx);
741
+ MemOpIdx oi = make_memop_idx(MO_BEQ, mmu_idx);
742
#endif
743
744
if (parallel) {
745
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
746
index XXXXXXX..XXXXXXX 100644
747
--- a/target/mips/tcg/msa_helper.c
748
+++ b/target/mips/tcg/msa_helper.c
749
@@ -XXX,XX +XXX,XX @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
750
#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
751
752
#if !defined(CONFIG_USER_ONLY)
753
-#define MEMOP_IDX(DF) \
754
- TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
755
- cpu_mmu_index(env, false));
756
+#define MEMOP_IDX(DF) \
757
+ MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
758
+ cpu_mmu_index(env, false));
759
#else
760
#define MEMOP_IDX(DF)
761
#endif
762
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
763
index XXXXXXX..XXXXXXX 100644
764
--- a/target/s390x/tcg/mem_helper.c
765
+++ b/target/s390x/tcg/mem_helper.c
766
@@ -XXX,XX +XXX,XX @@ static void do_access_memset(CPUS390XState *env, vaddr vaddr, char *haddr,
767
g_assert(haddr);
768
memset(haddr, byte, size);
769
#else
770
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
771
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
772
int i;
773
774
if (likely(haddr)) {
775
@@ -XXX,XX +XXX,XX @@ static uint8_t do_access_get_byte(CPUS390XState *env, vaddr vaddr, char **haddr,
776
#ifdef CONFIG_USER_ONLY
777
return ldub_p(*haddr + offset);
778
#else
779
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
780
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
781
uint8_t byte;
782
783
if (likely(*haddr)) {
784
@@ -XXX,XX +XXX,XX @@ static void do_access_set_byte(CPUS390XState *env, vaddr vaddr, char **haddr,
785
#ifdef CONFIG_USER_ONLY
786
stb_p(*haddr + offset, byte);
787
#else
788
- TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
789
+ MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
790
791
if (likely(*haddr)) {
792
stb_p(*haddr + offset, byte);
793
@@ -XXX,XX +XXX,XX @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr,
794
Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]);
795
Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]);
796
int mem_idx;
797
- TCGMemOpIdx oi;
798
+ MemOpIdx oi;
799
Int128 oldv;
800
bool fail;
801
802
@@ -XXX,XX +XXX,XX @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
803
uint32_t *haddr = g2h(env_cpu(env), a1);
804
ov = qatomic_cmpxchg__nocheck(haddr, cv, nv);
805
#else
806
- TCGMemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
807
+ MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mem_idx);
808
ov = cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra);
809
#endif
810
} else {
811
@@ -XXX,XX +XXX,XX @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
812
813
if (parallel) {
814
#ifdef CONFIG_ATOMIC64
815
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
816
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN, mem_idx);
817
ov = cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra);
818
#else
819
/* Note that we asserted !parallel above. */
820
@@ -XXX,XX +XXX,XX @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
821
cpu_stq_data_ra(env, a1 + 0, int128_gethi(nv), ra);
822
cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra);
823
} else if (HAVE_CMPXCHG128) {
824
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
825
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
826
ov = cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra);
827
cc = !int128_eq(ov, cv);
828
} else {
829
@@ -XXX,XX +XXX,XX @@ static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1,
830
cpu_stq_data_ra(env, a2 + 0, svh, ra);
831
cpu_stq_data_ra(env, a2 + 8, svl, ra);
832
} else if (HAVE_ATOMIC128) {
833
- TCGMemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
834
+ MemOpIdx oi = make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx);
835
Int128 sv = int128_make128(svl, svh);
836
cpu_atomic_sto_be_mmu(env, a2, sv, oi, ra);
837
} else {
838
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr)
839
uintptr_t ra = GETPC();
840
uint64_t hi, lo;
841
int mem_idx;
842
- TCGMemOpIdx oi;
843
+ MemOpIdx oi;
844
Int128 v;
845
846
assert(HAVE_ATOMIC128);
847
@@ -XXX,XX +XXX,XX @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr,
848
{
849
uintptr_t ra = GETPC();
850
int mem_idx;
851
- TCGMemOpIdx oi;
852
+ MemOpIdx oi;
853
Int128 v;
854
855
assert(HAVE_ATOMIC128);
856
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
857
index XXXXXXX..XXXXXXX 100644
858
--- a/target/sparc/ldst_helper.c
859
+++ b/target/sparc/ldst_helper.c
860
@@ -XXX,XX +XXX,XX @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
861
case ASI_SNF:
862
case ASI_SNFL:
863
{
864
- TCGMemOpIdx oi;
865
+ MemOpIdx oi;
866
int idx = (env->pstate & PS_PRIV
867
? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX)
868
: (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX));
869
diff --git a/tcg/optimize.c b/tcg/optimize.c
870
index XXXXXXX..XXXXXXX 100644
871
--- a/tcg/optimize.c
872
+++ b/tcg/optimize.c
873
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
874
875
CASE_OP_32_64(qemu_ld):
876
{
877
- TCGMemOpIdx oi = op->args[nb_oargs + nb_iargs];
878
+ MemOpIdx oi = op->args[nb_oargs + nb_iargs];
879
MemOp mop = get_memop(oi);
880
if (!(mop & MO_SIGN)) {
881
mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
882
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
883
index XXXXXXX..XXXXXXX 100644
884
--- a/tcg/tcg-op.c
885
+++ b/tcg/tcg-op.c
886
@@ -XXX,XX +XXX,XX @@ static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
887
static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
888
MemOp memop, TCGArg idx)
889
{
890
- TCGMemOpIdx oi = make_memop_idx(memop, idx);
891
+ MemOpIdx oi = make_memop_idx(memop, idx);
892
#if TARGET_LONG_BITS == 32
893
tcg_gen_op3i_i32(opc, val, addr, oi);
894
#else
895
@@ -XXX,XX +XXX,XX @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
896
static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
897
MemOp memop, TCGArg idx)
898
{
899
- TCGMemOpIdx oi = make_memop_idx(memop, idx);
900
+ MemOpIdx oi = make_memop_idx(memop, idx);
901
#if TARGET_LONG_BITS == 32
902
if (TCG_TARGET_REG_BITS == 32) {
903
tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
904
@@ -XXX,XX +XXX,XX @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
905
tcg_temp_free_i32(t1);
906
} else {
907
gen_atomic_cx_i32 gen;
908
- TCGMemOpIdx oi;
909
+ MemOpIdx oi;
910
911
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
912
tcg_debug_assert(gen != NULL);
913
@@ -XXX,XX +XXX,XX @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
914
} else if ((memop & MO_SIZE) == MO_64) {
915
#ifdef CONFIG_ATOMIC64
916
gen_atomic_cx_i64 gen;
917
- TCGMemOpIdx oi;
918
+ MemOpIdx oi;
919
920
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
921
tcg_debug_assert(gen != NULL);
922
@@ -XXX,XX +XXX,XX @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
923
TCGArg idx, MemOp memop, void * const table[])
924
{
925
gen_atomic_op_i32 gen;
926
- TCGMemOpIdx oi;
927
+ MemOpIdx oi;
928
929
memop = tcg_canonicalize_memop(memop, 0, 0);
930
931
@@ -XXX,XX +XXX,XX @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
932
if ((memop & MO_SIZE) == MO_64) {
933
#ifdef CONFIG_ATOMIC64
934
gen_atomic_op_i64 gen;
935
- TCGMemOpIdx oi;
936
+ MemOpIdx oi;
937
938
gen = table[memop & (MO_SIZE | MO_BSWAP)];
939
tcg_debug_assert(gen != NULL);
32
diff --git a/tcg/tcg.c b/tcg/tcg.c
940
diff --git a/tcg/tcg.c b/tcg/tcg.c
33
index XXXXXXX..XXXXXXX 100644
941
index XXXXXXX..XXXXXXX 100644
34
--- a/tcg/tcg.c
942
--- a/tcg/tcg.c
35
+++ b/tcg/tcg.c
943
+++ b/tcg/tcg.c
36
@@ -XXX,XX +XXX,XX @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
944
@@ -XXX,XX +XXX,XX @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
37
/* we give more priority to constraints with less registers */
945
case INDEX_op_qemu_ld_i64:
38
static int get_constraint_priority(const TCGOpDef *def, int k)
946
case INDEX_op_qemu_st_i64:
39
{
947
{
40
- const TCGArgConstraint *arg_ct;
948
- TCGMemOpIdx oi = op->args[k++];
41
+ const TCGArgConstraint *arg_ct = &def->args_ct[k];
949
+ MemOpIdx oi = op->args[k++];
42
+ int n;
950
MemOp op = get_memop(oi);
43
951
unsigned ix = get_mmuidx(oi);
44
- int i, n;
952
45
- arg_ct = &def->args_ct[k];
953
diff --git a/tcg/tci.c b/tcg/tci.c
46
if (arg_ct->ct & TCG_CT_ALIAS) {
954
index XXXXXXX..XXXXXXX 100644
47
/* an alias is equivalent to a single register */
955
--- a/tcg/tci.c
48
n = 1;
956
+++ b/tcg/tci.c
49
} else {
957
@@ -XXX,XX +XXX,XX @@ static uint64_t tci_uint64(uint32_t high, uint32_t low)
50
- if (!(arg_ct->ct & TCG_CT_REG))
958
* i = immediate (uint32_t)
51
- return 0;
959
* I = immediate (tcg_target_ulong)
52
- n = 0;
960
* l = label or pointer
53
- for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
961
- * m = immediate (TCGMemOpIdx)
54
- if (tcg_regset_test_reg(arg_ct->regs, i))
962
+ * m = immediate (MemOpIdx)
55
- n++;
963
* n = immediate (call return length)
56
- }
964
* r = register
57
+ n = ctpop64(arg_ct->regs);
965
* s = signed ldst offset
58
}
966
@@ -XXX,XX +XXX,XX @@ static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1)
59
return TCG_TARGET_NB_REGS - n + 1;
967
}
60
}
968
61
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
969
static void tci_args_rrm(uint32_t insn, TCGReg *r0,
62
int oarg = *ct_str - '0';
970
- TCGReg *r1, TCGMemOpIdx *m2)
63
tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
971
+ TCGReg *r1, MemOpIdx *m2)
64
tcg_debug_assert(oarg < def->nb_oargs);
972
{
65
- tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
973
*r0 = extract32(insn, 8, 4);
66
+ tcg_debug_assert(def->args_ct[oarg].regs != 0);
974
*r1 = extract32(insn, 12, 4);
67
/* TCG_CT_ALIAS is for the output arguments.
975
@@ -XXX,XX +XXX,XX @@ static void tci_args_rrrc(uint32_t insn,
68
The input is tagged with TCG_CT_IALIAS. */
976
}
69
def->args_ct[i] = def->args_ct[oarg];
977
978
static void tci_args_rrrm(uint32_t insn,
979
- TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGMemOpIdx *m3)
980
+ TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3)
981
{
982
*r0 = extract32(insn, 8, 4);
983
*r1 = extract32(insn, 12, 4);
984
@@ -XXX,XX +XXX,XX @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
985
}
986
987
static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
988
- TCGMemOpIdx oi, const void *tb_ptr)
989
+ MemOpIdx oi, const void *tb_ptr)
990
{
991
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
992
uintptr_t ra = (uintptr_t)tb_ptr;
993
@@ -XXX,XX +XXX,XX @@ static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
994
}
995
996
static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
997
- TCGMemOpIdx oi, const void *tb_ptr)
998
+ MemOpIdx oi, const void *tb_ptr)
999
{
1000
MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
1001
uintptr_t ra = (uintptr_t)tb_ptr;
1002
@@ -XXX,XX +XXX,XX @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
1003
uint32_t tmp32;
1004
uint64_t tmp64;
1005
uint64_t T1, T2;
1006
- TCGMemOpIdx oi;
1007
+ MemOpIdx oi;
1008
int32_t ofs;
1009
void *ptr;
1010
1011
@@ -XXX,XX +XXX,XX @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
1012
tcg_target_ulong i1;
1013
int32_t s2;
1014
TCGCond c;
1015
- TCGMemOpIdx oi;
1016
+ MemOpIdx oi;
1017
uint8_t pos, len;
1018
void *ptr;
1019
1020
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
1021
index XXXXXXX..XXXXXXX 100644
1022
--- a/accel/tcg/atomic_common.c.inc
1023
+++ b/accel/tcg/atomic_common.c.inc
1024
@@ -XXX,XX +XXX,XX @@
1025
*/
1026
1027
static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
1028
- TCGMemOpIdx oi)
1029
+ MemOpIdx oi)
1030
{
1031
CPUState *cpu = env_cpu(env);
1032
uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
1033
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
1034
1035
#if HAVE_ATOMIC128
1036
static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
1037
- TCGMemOpIdx oi)
1038
+ MemOpIdx oi)
1039
{
1040
uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
1041
1042
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
1043
}
1044
1045
static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
1046
- TCGMemOpIdx oi)
1047
+ MemOpIdx oi)
1048
{
1049
uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), true);
1050
70
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
1051
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
71
index XXXXXXX..XXXXXXX 100644
1052
index XXXXXXX..XXXXXXX 100644
72
--- a/tcg/aarch64/tcg-target.c.inc
1053
--- a/tcg/aarch64/tcg-target.c.inc
73
+++ b/tcg/aarch64/tcg-target.c.inc
1054
+++ b/tcg/aarch64/tcg-target.c.inc
74
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1055
@@ -XXX,XX +XXX,XX @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
75
{
1056
#include "../tcg-ldst.c.inc"
76
switch (*ct_str++) {
1057
77
case 'r': /* general registers */
1058
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
78
- ct->ct |= TCG_CT_REG;
1059
- * TCGMemOpIdx oi, uintptr_t ra)
79
ct->regs |= 0xffffffffu;
1060
+ * MemOpIdx oi, uintptr_t ra)
80
break;
1061
*/
81
case 'w': /* advsimd registers */
1062
static void * const qemu_ld_helpers[MO_SIZE + 1] = {
82
- ct->ct |= TCG_CT_REG;
1063
[MO_8] = helper_ret_ldub_mmu,
83
ct->regs |= 0xffffffff00000000ull;
1064
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[MO_SIZE + 1] = {
84
break;
1065
};
85
case 'l': /* qemu_ld / qemu_st address, data_reg */
1066
86
- ct->ct |= TCG_CT_REG;
1067
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
87
ct->regs = 0xffffffffu;
1068
- * uintxx_t val, TCGMemOpIdx oi,
88
#ifdef CONFIG_SOFTMMU
1069
+ * uintxx_t val, MemOpIdx oi,
89
/* x0 and x1 will be overwritten when reading the tlb entry,
1070
* uintptr_t ra)
1071
*/
1072
static void * const qemu_st_helpers[MO_SIZE + 1] = {
1073
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
1074
1075
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1076
{
1077
- TCGMemOpIdx oi = lb->oi;
1078
+ MemOpIdx oi = lb->oi;
1079
MemOp opc = get_memop(oi);
1080
MemOp size = opc & MO_SIZE;
1081
1082
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1083
1084
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1085
{
1086
- TCGMemOpIdx oi = lb->oi;
1087
+ MemOpIdx oi = lb->oi;
1088
MemOp opc = get_memop(oi);
1089
MemOp size = opc & MO_SIZE;
1090
1091
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1092
return true;
1093
}
1094
1095
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
1096
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
1097
TCGType ext, TCGReg data_reg, TCGReg addr_reg,
1098
tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
1099
{
1100
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
1101
}
1102
1103
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1104
- TCGMemOpIdx oi, TCGType ext)
1105
+ MemOpIdx oi, TCGType ext)
1106
{
1107
MemOp memop = get_memop(oi);
1108
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
1109
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1110
}
1111
1112
static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1113
- TCGMemOpIdx oi)
1114
+ MemOpIdx oi)
1115
{
1116
MemOp memop = get_memop(oi);
1117
const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
90
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
1118
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
91
index XXXXXXX..XXXXXXX 100644
1119
index XXXXXXX..XXXXXXX 100644
92
--- a/tcg/arm/tcg-target.c.inc
1120
--- a/tcg/arm/tcg-target.c.inc
93
+++ b/tcg/arm/tcg-target.c.inc
1121
+++ b/tcg/arm/tcg-target.c.inc
94
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1122
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
95
break;
1123
/* Record the context of a call to the out of line helper code for the slow
96
1124
path for a load or store, so that we can later generate the correct
97
case 'r':
1125
helper code. */
98
- ct->ct |= TCG_CT_REG;
1126
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
99
ct->regs = 0xffff;
1127
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
100
break;
1128
TCGReg datalo, TCGReg datahi, TCGReg addrlo,
101
1129
TCGReg addrhi, tcg_insn_unit *raddr,
102
/* qemu_ld address */
1130
tcg_insn_unit *label_ptr)
103
case 'l':
1131
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
104
- ct->ct |= TCG_CT_REG;
1132
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
105
ct->regs = 0xffff;
1133
{
1134
TCGReg argreg, datalo, datahi;
1135
- TCGMemOpIdx oi = lb->oi;
1136
+ MemOpIdx oi = lb->oi;
1137
MemOp opc = get_memop(oi);
1138
void *func;
1139
1140
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1141
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1142
{
1143
TCGReg argreg, datalo, datahi;
1144
- TCGMemOpIdx oi = lb->oi;
1145
+ MemOpIdx oi = lb->oi;
1146
MemOp opc = get_memop(oi);
1147
1148
if (!reloc_pc24(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
1149
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
1150
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
1151
{
1152
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
1153
- TCGMemOpIdx oi;
1154
+ MemOpIdx oi;
1155
MemOp opc;
106
#ifdef CONFIG_SOFTMMU
1156
#ifdef CONFIG_SOFTMMU
107
/* r0-r2,lr will be overwritten when reading the tlb entry,
1157
int mem_index;
108
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1158
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
109
1159
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
110
/* qemu_st address & data */
1160
{
111
case 's':
1161
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
112
- ct->ct |= TCG_CT_REG;
1162
- TCGMemOpIdx oi;
113
ct->regs = 0xffff;
1163
+ MemOpIdx oi;
114
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
1164
MemOp opc;
115
and r0-r1 doing the byte swapping, so don't use these. */
1165
#ifdef CONFIG_SOFTMMU
1166
int mem_index;
116
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
1167
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
117
index XXXXXXX..XXXXXXX 100644
1168
index XXXXXXX..XXXXXXX 100644
118
--- a/tcg/i386/tcg-target.c.inc
1169
--- a/tcg/i386/tcg-target.c.inc
119
+++ b/tcg/i386/tcg-target.c.inc
1170
+++ b/tcg/i386/tcg-target.c.inc
120
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1171
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
121
{
1172
* for a load or store, so that we can later generate the correct helper code
122
switch(*ct_str++) {
1173
*/
123
case 'a':
1174
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
124
- ct->ct |= TCG_CT_REG;
1175
- TCGMemOpIdx oi,
125
tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
1176
+ MemOpIdx oi,
126
break;
1177
TCGReg datalo, TCGReg datahi,
127
case 'b':
1178
TCGReg addrlo, TCGReg addrhi,
128
- ct->ct |= TCG_CT_REG;
1179
tcg_insn_unit *raddr,
129
tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
1180
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
130
break;
1181
*/
131
case 'c':
1182
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
132
- ct->ct |= TCG_CT_REG;
1183
{
133
tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
1184
- TCGMemOpIdx oi = l->oi;
134
break;
1185
+ MemOpIdx oi = l->oi;
135
case 'd':
1186
MemOp opc = get_memop(oi);
136
- ct->ct |= TCG_CT_REG;
1187
TCGReg data_reg;
137
tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
1188
tcg_insn_unit **label_ptr = &l->label_ptr[0];
138
break;
1189
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
139
case 'S':
1190
*/
140
- ct->ct |= TCG_CT_REG;
1191
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
141
tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
1192
{
142
break;
1193
- TCGMemOpIdx oi = l->oi;
143
case 'D':
1194
+ MemOpIdx oi = l->oi;
144
- ct->ct |= TCG_CT_REG;
1195
MemOp opc = get_memop(oi);
145
tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
1196
MemOp s_bits = opc & MO_SIZE;
146
break;
1197
tcg_insn_unit **label_ptr = &l->label_ptr[0];
147
case 'q':
1198
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
148
/* A register that can be used as a byte operand. */
1199
{
149
- ct->ct |= TCG_CT_REG;
1200
TCGReg datalo, datahi, addrlo;
150
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
1201
TCGReg addrhi __attribute__((unused));
151
break;
1202
- TCGMemOpIdx oi;
152
case 'Q':
1203
+ MemOpIdx oi;
153
/* A register with an addressable second byte (e.g. %ah). */
1204
MemOp opc;
154
- ct->ct |= TCG_CT_REG;
1205
#if defined(CONFIG_SOFTMMU)
155
ct->regs = 0xf;
1206
int mem_index;
156
break;
1207
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
157
case 'r':
1208
{
158
/* A general register. */
1209
TCGReg datalo, datahi, addrlo;
159
- ct->ct |= TCG_CT_REG;
1210
TCGReg addrhi __attribute__((unused));
160
ct->regs |= ALL_GENERAL_REGS;
1211
- TCGMemOpIdx oi;
161
break;
1212
+ MemOpIdx oi;
162
case 'W':
1213
MemOp opc;
163
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1214
#if defined(CONFIG_SOFTMMU)
164
break;
1215
int mem_index;
165
case 'x':
166
/* A vector register. */
167
- ct->ct |= TCG_CT_REG;
168
ct->regs |= ALL_VECTOR_REGS;
169
break;
170
171
/* qemu_ld/st address constraint */
172
case 'L':
173
- ct->ct |= TCG_CT_REG;
174
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
175
tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
176
tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
177
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
1216
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
178
index XXXXXXX..XXXXXXX 100644
1217
index XXXXXXX..XXXXXXX 100644
179
--- a/tcg/mips/tcg-target.c.inc
1218
--- a/tcg/mips/tcg-target.c.inc
180
+++ b/tcg/mips/tcg-target.c.inc
1219
+++ b/tcg/mips/tcg-target.c.inc
181
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1220
@@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768);
182
{
1221
* Clobbers TMP0, TMP1, TMP2, TMP3.
183
switch(*ct_str++) {
1222
*/
184
case 'r':
1223
static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
185
- ct->ct |= TCG_CT_REG;
1224
- TCGReg addrh, TCGMemOpIdx oi,
186
ct->regs = 0xffffffff;
1225
+ TCGReg addrh, MemOpIdx oi,
187
break;
1226
tcg_insn_unit *label_ptr[2], bool is_load)
188
case 'L': /* qemu_ld input arg constraint */
1227
{
189
- ct->ct |= TCG_CT_REG;
1228
MemOp opc = get_memop(oi);
190
ct->regs = 0xffffffff;
1229
@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
191
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
1230
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl);
1231
}
1232
1233
-static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1234
+static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
1235
TCGType ext,
1236
TCGReg datalo, TCGReg datahi,
1237
TCGReg addrlo, TCGReg addrhi,
1238
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1239
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1240
{
1241
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1242
- TCGMemOpIdx oi = l->oi;
1243
+ MemOpIdx oi = l->oi;
1244
MemOp opc = get_memop(oi);
1245
TCGReg v0;
1246
int i;
1247
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1248
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1249
{
1250
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1251
- TCGMemOpIdx oi = l->oi;
1252
+ MemOpIdx oi = l->oi;
1253
MemOp opc = get_memop(oi);
1254
MemOp s_bits = opc & MO_SIZE;
1255
int i;
1256
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1257
{
1258
TCGReg addr_regl, addr_regh __attribute__((unused));
1259
TCGReg data_regl, data_regh;
1260
- TCGMemOpIdx oi;
1261
+ MemOpIdx oi;
1262
MemOp opc;
192
#if defined(CONFIG_SOFTMMU)
1263
#if defined(CONFIG_SOFTMMU)
193
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1264
tcg_insn_unit *label_ptr[2];
194
#endif
1265
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
195
break;
1266
{
196
case 'S': /* qemu_st constraint */
1267
TCGReg addr_regl, addr_regh __attribute__((unused));
197
- ct->ct |= TCG_CT_REG;
1268
TCGReg data_regl, data_regh;
198
ct->regs = 0xffffffff;
1269
- TCGMemOpIdx oi;
199
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
1270
+ MemOpIdx oi;
1271
MemOp opc;
200
#if defined(CONFIG_SOFTMMU)
1272
#if defined(CONFIG_SOFTMMU)
1273
tcg_insn_unit *label_ptr[2];
201
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
1274
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
202
index XXXXXXX..XXXXXXX 100644
1275
index XXXXXXX..XXXXXXX 100644
203
--- a/tcg/ppc/tcg-target.c.inc
1276
--- a/tcg/ppc/tcg-target.c.inc
204
+++ b/tcg/ppc/tcg-target.c.inc
1277
+++ b/tcg/ppc/tcg-target.c.inc
205
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1278
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc,
206
{
1279
/* Record the context of a call to the out of line helper code for the slow
207
switch (*ct_str++) {
1280
path for a load or store, so that we can later generate the correct
208
case 'A': case 'B': case 'C': case 'D':
1281
helper code. */
209
- ct->ct |= TCG_CT_REG;
1282
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
210
tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
1283
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
211
break;
1284
TCGReg datalo_reg, TCGReg datahi_reg,
212
case 'r':
1285
TCGReg addrlo_reg, TCGReg addrhi_reg,
213
- ct->ct |= TCG_CT_REG;
1286
tcg_insn_unit *raddr, tcg_insn_unit *lptr)
214
ct->regs = 0xffffffff;
1287
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
215
break;
1288
216
case 'v':
1289
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
217
- ct->ct |= TCG_CT_REG;
1290
{
218
ct->regs = 0xffffffff00000000ull;
1291
- TCGMemOpIdx oi = lb->oi;
219
break;
1292
+ MemOpIdx oi = lb->oi;
220
case 'L': /* qemu_ld constraint */
1293
MemOp opc = get_memop(oi);
221
- ct->ct |= TCG_CT_REG;
1294
TCGReg hi, lo, arg = TCG_REG_R3;
222
ct->regs = 0xffffffff;
1295
223
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
1296
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1297
1298
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1299
{
1300
- TCGMemOpIdx oi = lb->oi;
1301
+ MemOpIdx oi = lb->oi;
1302
MemOp opc = get_memop(oi);
1303
MemOp s_bits = opc & MO_SIZE;
1304
TCGReg hi, lo, arg = TCG_REG_R3;
1305
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1306
{
1307
TCGReg datalo, datahi, addrlo, rbase;
1308
TCGReg addrhi __attribute__((unused));
1309
- TCGMemOpIdx oi;
1310
+ MemOpIdx oi;
1311
MemOp opc, s_bits;
224
#ifdef CONFIG_SOFTMMU
1312
#ifdef CONFIG_SOFTMMU
225
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1313
int mem_index;
226
#endif
1314
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
227
break;
1315
{
228
case 'S': /* qemu_st constraint */
1316
TCGReg datalo, datahi, addrlo, rbase;
229
- ct->ct |= TCG_CT_REG;
1317
TCGReg addrhi __attribute__((unused));
230
ct->regs = 0xffffffff;
1318
- TCGMemOpIdx oi;
231
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
1319
+ MemOpIdx oi;
1320
MemOp opc, s_bits;
232
#ifdef CONFIG_SOFTMMU
1321
#ifdef CONFIG_SOFTMMU
1322
int mem_index;
233
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
1323
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
234
index XXXXXXX..XXXXXXX 100644
1324
index XXXXXXX..XXXXXXX 100644
235
--- a/tcg/riscv/tcg-target.c.inc
1325
--- a/tcg/riscv/tcg-target.c.inc
236
+++ b/tcg/riscv/tcg-target.c.inc
1326
+++ b/tcg/riscv/tcg-target.c.inc
237
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1327
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
238
{
1328
#include "../tcg-ldst.c.inc"
239
switch (*ct_str++) {
1329
240
case 'r':
1330
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
241
- ct->ct |= TCG_CT_REG;
1331
- * TCGMemOpIdx oi, uintptr_t ra)
242
ct->regs = 0xffffffff;
1332
+ * MemOpIdx oi, uintptr_t ra)
243
break;
1333
*/
244
case 'L':
1334
static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
245
/* qemu_ld/qemu_st constraint */
1335
[MO_UB] = helper_ret_ldub_mmu,
246
- ct->ct |= TCG_CT_REG;
1336
@@ -XXX,XX +XXX,XX @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
247
ct->regs = 0xffffffff;
1337
};
248
/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
1338
1339
/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
1340
- * uintxx_t val, TCGMemOpIdx oi,
1341
+ * uintxx_t val, MemOpIdx oi,
1342
* uintptr_t ra)
1343
*/
1344
static void * const qemu_st_helpers[MO_SIZE + 1] = {
1345
@@ -XXX,XX +XXX,XX @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
1346
}
1347
1348
static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
1349
- TCGReg addrh, TCGMemOpIdx oi,
1350
+ TCGReg addrh, MemOpIdx oi,
1351
tcg_insn_unit **label_ptr, bool is_load)
1352
{
1353
MemOp opc = get_memop(oi);
1354
@@ -XXX,XX +XXX,XX @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
1355
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
1356
}
1357
1358
-static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1359
+static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi,
1360
TCGType ext,
1361
TCGReg datalo, TCGReg datahi,
1362
TCGReg addrlo, TCGReg addrhi,
1363
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1364
1365
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1366
{
1367
- TCGMemOpIdx oi = l->oi;
1368
+ MemOpIdx oi = l->oi;
1369
MemOp opc = get_memop(oi);
1370
TCGReg a0 = tcg_target_call_iarg_regs[0];
1371
TCGReg a1 = tcg_target_call_iarg_regs[1];
1372
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1373
1374
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1375
{
1376
- TCGMemOpIdx oi = l->oi;
1377
+ MemOpIdx oi = l->oi;
1378
MemOp opc = get_memop(oi);
1379
MemOp s_bits = opc & MO_SIZE;
1380
TCGReg a0 = tcg_target_call_iarg_regs[0];
1381
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1382
{
1383
TCGReg addr_regl, addr_regh __attribute__((unused));
1384
TCGReg data_regl, data_regh;
1385
- TCGMemOpIdx oi;
1386
+ MemOpIdx oi;
1387
MemOp opc;
249
#if defined(CONFIG_SOFTMMU)
1388
#if defined(CONFIG_SOFTMMU)
1389
tcg_insn_unit *label_ptr[1];
1390
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1391
{
1392
TCGReg addr_regl, addr_regh __attribute__((unused));
1393
TCGReg data_regl, data_regh;
1394
- TCGMemOpIdx oi;
1395
+ MemOpIdx oi;
1396
MemOp opc;
1397
#if defined(CONFIG_SOFTMMU)
1398
tcg_insn_unit *label_ptr[1];
250
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
1399
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
251
index XXXXXXX..XXXXXXX 100644
1400
index XXXXXXX..XXXXXXX 100644
252
--- a/tcg/s390/tcg-target.c.inc
1401
--- a/tcg/s390/tcg-target.c.inc
253
+++ b/tcg/s390/tcg-target.c.inc
1402
+++ b/tcg/s390/tcg-target.c.inc
254
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1403
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
255
{
1404
return addr_reg;
256
switch (*ct_str++) {
1405
}
257
case 'r': /* all registers */
1406
258
- ct->ct |= TCG_CT_REG;
1407
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
259
ct->regs = 0xffff;
1408
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
260
break;
1409
TCGReg data, TCGReg addr,
261
case 'L': /* qemu_ld/st constraint */
1410
tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
262
- ct->ct |= TCG_CT_REG;
1411
{
263
ct->regs = 0xffff;
1412
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
264
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
1413
{
265
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
1414
TCGReg addr_reg = lb->addrlo_reg;
266
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
1415
TCGReg data_reg = lb->datalo_reg;
267
break;
1416
- TCGMemOpIdx oi = lb->oi;
268
case 'a': /* force R2 for division */
1417
+ MemOpIdx oi = lb->oi;
269
- ct->ct |= TCG_CT_REG;
1418
MemOp opc = get_memop(oi);
270
ct->regs = 0;
1419
271
tcg_regset_set_reg(ct->regs, TCG_REG_R2);
1420
if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
272
break;
1421
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
273
case 'b': /* force R3 for division */
1422
{
274
- ct->ct |= TCG_CT_REG;
1423
TCGReg addr_reg = lb->addrlo_reg;
275
ct->regs = 0;
1424
TCGReg data_reg = lb->datalo_reg;
276
tcg_regset_set_reg(ct->regs, TCG_REG_R3);
1425
- TCGMemOpIdx oi = lb->oi;
277
break;
1426
+ MemOpIdx oi = lb->oi;
1427
MemOp opc = get_memop(oi);
1428
1429
if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
1430
@@ -XXX,XX +XXX,XX @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
1431
#endif /* CONFIG_SOFTMMU */
1432
1433
static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
1434
- TCGMemOpIdx oi)
1435
+ MemOpIdx oi)
1436
{
1437
MemOp opc = get_memop(oi);
1438
#ifdef CONFIG_SOFTMMU
1439
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
1440
}
1441
1442
static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
1443
- TCGMemOpIdx oi)
1444
+ MemOpIdx oi)
1445
{
1446
MemOp opc = get_memop(oi);
1447
#ifdef CONFIG_SOFTMMU
278
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
1448
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
279
index XXXXXXX..XXXXXXX 100644
1449
index XXXXXXX..XXXXXXX 100644
280
--- a/tcg/sparc/tcg-target.c.inc
1450
--- a/tcg/sparc/tcg-target.c.inc
281
+++ b/tcg/sparc/tcg-target.c.inc
1451
+++ b/tcg/sparc/tcg-target.c.inc
282
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1452
@@ -XXX,XX +XXX,XX @@ static const int qemu_st_opc[(MO_SIZE | MO_BSWAP) + 1] = {
283
{
1453
};
284
switch (*ct_str++) {
1454
285
case 'r':
1455
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
286
- ct->ct |= TCG_CT_REG;
1456
- TCGMemOpIdx oi, bool is_64)
287
ct->regs = 0xffffffff;
1457
+ MemOpIdx oi, bool is_64)
288
break;
1458
{
289
case 'R':
1459
MemOp memop = get_memop(oi);
290
- ct->ct |= TCG_CT_REG;
1460
#ifdef CONFIG_SOFTMMU
291
ct->regs = ALL_64;
1461
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
292
break;
1462
}
293
case 'A': /* qemu_ld/st address constraint */
1463
294
- ct->ct |= TCG_CT_REG;
1464
static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
295
ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
1465
- TCGMemOpIdx oi)
296
reserve_helpers:
1466
+ MemOpIdx oi)
297
tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
1467
{
298
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
1468
MemOp memop = get_memop(oi);
299
tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
1469
#ifdef CONFIG_SOFTMMU
300
break;
1470
diff --git a/tcg/tcg-ldst.c.inc b/tcg/tcg-ldst.c.inc
301
case 's': /* qemu_st data 32-bit constraint */
1471
index XXXXXXX..XXXXXXX 100644
302
- ct->ct |= TCG_CT_REG;
1472
--- a/tcg/tcg-ldst.c.inc
303
ct->regs = 0xffffffff;
1473
+++ b/tcg/tcg-ldst.c.inc
304
goto reserve_helpers;
1474
@@ -XXX,XX +XXX,XX @@
305
case 'S': /* qemu_st data 64-bit constraint */
1475
306
- ct->ct |= TCG_CT_REG;
1476
typedef struct TCGLabelQemuLdst {
307
ct->regs = ALL_64;
1477
bool is_ld; /* qemu_ld: true, qemu_st: false */
308
goto reserve_helpers;
1478
- TCGMemOpIdx oi;
309
case 'I':
1479
+ MemOpIdx oi;
310
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
1480
TCGType type; /* result type of a load */
311
index XXXXXXX..XXXXXXX 100644
1481
TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */
312
--- a/tcg/tci/tcg-target.c.inc
1482
TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */
313
+++ b/tcg/tci/tcg-target.c.inc
314
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
315
case 'r':
316
case 'L': /* qemu_ld constraint */
317
case 'S': /* qemu_st constraint */
318
- ct->ct |= TCG_CT_REG;
319
ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
320
break;
321
default:
322
--
1483
--
323
2.25.1
1484
2.25.1
324
1485
325
1486
diff view generated by jsdifflib
[PULL 06/11] tcg: Remove TCGOpDef.used
[PULL 07/28] tcg: Split out MemOpIdx to exec/memopidx.h
1
The last user of this field disappeared in f69d277ece4.
1
Move this code from tcg/tcg.h to its own header.
2
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
5
---
6
include/tcg/tcg.h | 3 ---
6
include/exec/memopidx.h | 55 +++++++++++++++++++++++++++++++++++++++++
7
1 file changed, 3 deletions(-)
7
include/tcg/tcg.h | 39 +----------------------------
8
2 files changed, 56 insertions(+), 38 deletions(-)
9
create mode 100644 include/exec/memopidx.h
8
10
11
diff --git a/include/exec/memopidx.h b/include/exec/memopidx.h
12
new file mode 100644
13
index XXXXXXX..XXXXXXX
14
--- /dev/null
15
+++ b/include/exec/memopidx.h
16
@@ -XXX,XX +XXX,XX @@
17
+/*
18
+ * Combine the MemOp and mmu_idx parameters into a single value.
19
+ *
20
+ * Authors:
21
+ * Richard Henderson <rth@twiddle.net>
22
+ *
23
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
24
+ * See the COPYING file in the top-level directory.
25
+ */
26
+
27
+#ifndef EXEC_MEMOPIDX_H
28
+#define EXEC_MEMOPIDX_H 1
29
+
30
+#include "exec/memop.h"
31
+
32
+typedef uint32_t MemOpIdx;
33
+
34
+/**
35
+ * make_memop_idx
36
+ * @op: memory operation
37
+ * @idx: mmu index
38
+ *
39
+ * Encode these values into a single parameter.
40
+ */
41
+static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx)
42
+{
43
+#ifdef CONFIG_DEBUG_TCG
44
+ assert(idx <= 15);
45
+#endif
46
+ return (op << 4) | idx;
47
+}
48
+
49
+/**
50
+ * get_memop
51
+ * @oi: combined op/idx parameter
52
+ *
53
+ * Extract the memory operation from the combined value.
54
+ */
55
+static inline MemOp get_memop(MemOpIdx oi)
56
+{
57
+ return oi >> 4;
58
+}
59
+
60
+/**
61
+ * get_mmuidx
62
+ * @oi: combined op/idx parameter
63
+ *
64
+ * Extract the mmu index from the combined value.
65
+ */
66
+static inline unsigned get_mmuidx(MemOpIdx oi)
67
+{
68
+ return oi & 15;
69
+}
70
+
71
+#endif
9
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
72
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
10
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
11
--- a/include/tcg/tcg.h
74
--- a/include/tcg/tcg.h
12
+++ b/include/tcg/tcg.h
75
+++ b/include/tcg/tcg.h
13
@@ -XXX,XX +XXX,XX @@ typedef struct TCGOpDef {
76
@@ -XXX,XX +XXX,XX @@
14
uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
77
15
uint8_t flags;
78
#include "cpu.h"
16
TCGArgConstraint *args_ct;
79
#include "exec/memop.h"
17
-#if defined(CONFIG_DEBUG_TCG)
80
+#include "exec/memopidx.h"
18
- int used;
81
#include "qemu/bitops.h"
19
-#endif
82
#include "qemu/plugin.h"
20
} TCGOpDef;
83
#include "qemu/queue.h"
21
84
@@ -XXX,XX +XXX,XX @@ static inline size_t tcg_current_code_size(TCGContext *s)
22
extern TCGOpDef tcg_op_defs[];
85
return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
86
}
87
88
-/* Combine the MemOp and mmu_idx parameters into a single value. */
89
-typedef uint32_t MemOpIdx;
90
-
91
-/**
92
- * make_memop_idx
93
- * @op: memory operation
94
- * @idx: mmu index
95
- *
96
- * Encode these values into a single parameter.
97
- */
98
-static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx)
99
-{
100
- tcg_debug_assert(idx <= 15);
101
- return (op << 4) | idx;
102
-}
103
-
104
-/**
105
- * get_memop
106
- * @oi: combined op/idx parameter
107
- *
108
- * Extract the memory operation from the combined value.
109
- */
110
-static inline MemOp get_memop(MemOpIdx oi)
111
-{
112
- return oi >> 4;
113
-}
114
-
115
-/**
116
- * get_mmuidx
117
- * @oi: combined op/idx parameter
118
- *
119
- * Extract the mmu index from the combined value.
120
- */
121
-static inline unsigned get_mmuidx(MemOpIdx oi)
122
-{
123
- return oi & 15;
124
-}
125
-
126
/**
127
* tcg_qemu_tb_exec:
128
* @env: pointer to CPUArchState for the CPU
23
--
129
--
24
2.25.1
130
2.25.1
25
131
26
132
diff view generated by jsdifflib
[PULL 11/11] accel/tcg: Fix computing of is_write for MIPS
[PULL 08/28] trace/mem: Pass MemOpIdx to trace_mem_get_info
1
From: Kele Huang <kele.hwang@gmail.com>
1
We (will) often have the complete MemOpIdx handy, so use that.
2
2
3
Detect all MIPS store instructions in cpu_signal_handler for all available
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
MIPS versions, and set is_write if encountering such store instructions.
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
6
This fixed the error while dealing with self-modified code for MIPS.
7
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Kele Huang <kele.hwang@gmail.com>
10
Signed-off-by: Xu Zou <iwatchnima@gmail.com>
11
Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>
12
[rth: Use uintptr_t for pc to fix n32 build error.]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
---
6
---
15
accel/tcg/user-exec.c | 43 +++++++++++++++++++++++++++++++++++++++----
7
trace/mem.h | 32 +++++++++-----------------
16
1 file changed, 39 insertions(+), 4 deletions(-)
8
accel/tcg/cputlb.c | 12 ++++------
9
accel/tcg/user-exec.c | 42 +++++++++++++++++++++++------------
10
tcg/tcg-op.c | 8 +++----
11
accel/tcg/atomic_common.c.inc | 6 ++---
12
5 files changed, 49 insertions(+), 51 deletions(-)
17
13
14
diff --git a/trace/mem.h b/trace/mem.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/trace/mem.h
17
+++ b/trace/mem.h
18
@@ -XXX,XX +XXX,XX @@
19
#ifndef TRACE__MEM_H
20
#define TRACE__MEM_H
21
22
-#include "tcg/tcg.h"
23
+#include "exec/memopidx.h"
24
25
#define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */
26
#define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */
27
@@ -XXX,XX +XXX,XX @@
28
#define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */
29
30
/**
31
- * trace_mem_build_info:
32
+ * trace_mem_get_info:
33
*
34
* Return a value for the 'info' argument in guest memory access traces.
35
*/
36
-static inline uint16_t trace_mem_build_info(int size_shift, bool sign_extend,
37
- MemOp endianness, bool store,
38
- unsigned int mmu_idx)
39
+static inline uint16_t trace_mem_get_info(MemOpIdx oi, bool store)
40
{
41
+ MemOp op = get_memop(oi);
42
+ uint32_t size_shift = op & MO_SIZE;
43
+ bool sign_extend = op & MO_SIGN;
44
+ bool big_endian = (op & MO_BSWAP) == MO_BE;
45
uint16_t res;
46
47
res = size_shift & TRACE_MEM_SZ_SHIFT_MASK;
48
if (sign_extend) {
49
res |= TRACE_MEM_SE;
50
}
51
- if (endianness == MO_BE) {
52
+ if (big_endian) {
53
res |= TRACE_MEM_BE;
54
}
55
if (store) {
56
res |= TRACE_MEM_ST;
57
}
58
#ifdef CONFIG_SOFTMMU
59
- res |= mmu_idx << TRACE_MEM_MMU_SHIFT;
60
+ res |= get_mmuidx(oi) << TRACE_MEM_MMU_SHIFT;
61
#endif
62
+
63
return res;
64
}
65
66
-
67
-/**
68
- * trace_mem_get_info:
69
- *
70
- * Return a value for the 'info' argument in guest memory access traces.
71
- */
72
-static inline uint16_t trace_mem_get_info(MemOp op,
73
- unsigned int mmu_idx,
74
- bool store)
75
-{
76
- return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN),
77
- op & MO_BSWAP, store,
78
- mmu_idx);
79
-}
80
-
81
#endif /* TRACE__MEM_H */
82
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
83
index XXXXXXX..XXXXXXX 100644
84
--- a/accel/tcg/cputlb.c
85
+++ b/accel/tcg/cputlb.c
86
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
87
int mmu_idx, uintptr_t retaddr,
88
MemOp op, FullLoadHelper *full_load)
89
{
90
- uint16_t meminfo;
91
- MemOpIdx oi;
92
+ MemOpIdx oi = make_memop_idx(op, mmu_idx);
93
+ uint16_t meminfo = trace_mem_get_info(oi, false);
94
uint64_t ret;
95
96
- meminfo = trace_mem_get_info(op, mmu_idx, false);
97
trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
98
99
- oi = make_memop_idx(op, mmu_idx);
100
ret = full_load(env, addr, oi, retaddr);
101
102
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
103
@@ -XXX,XX +XXX,XX @@ static inline void QEMU_ALWAYS_INLINE
104
cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
105
int mmu_idx, uintptr_t retaddr, MemOp op)
106
{
107
- MemOpIdx oi;
108
- uint16_t meminfo;
109
+ MemOpIdx oi = make_memop_idx(op, mmu_idx);
110
+ uint16_t meminfo = trace_mem_get_info(oi, true);
111
112
- meminfo = trace_mem_get_info(op, mmu_idx, true);
113
trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
114
115
- oi = make_memop_idx(op, mmu_idx);
116
store_helper(env, addr, val, oi, retaddr, op);
117
118
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
18
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
119
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
19
index XXXXXXX..XXXXXXX 100644
120
index XXXXXXX..XXXXXXX 100644
20
--- a/accel/tcg/user-exec.c
121
--- a/accel/tcg/user-exec.c
21
+++ b/accel/tcg/user-exec.c
122
+++ b/accel/tcg/user-exec.c
22
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
123
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
23
124
24
#elif defined(__mips__)
125
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
25
126
{
26
+#if defined(__misp16) || defined(__mips_micromips)
127
+ MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
27
+#error "Unsupported encoding"
128
+ uint16_t meminfo = trace_mem_get_info(oi, false);
28
+#endif
129
uint32_t ret;
29
+
130
- uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, false);
30
int cpu_signal_handler(int host_signum, void *pinfo,
131
31
void *puc)
132
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
32
{
133
ret = ldub_p(g2h(env_cpu(env), ptr));
33
siginfo_t *info = pinfo;
134
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
34
ucontext_t *uc = puc;
135
35
- greg_t pc = uc->uc_mcontext.pc;
136
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
36
- int is_write;
137
{
37
+ uintptr_t pc = uc->uc_mcontext.pc;
138
+ MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
38
+ uint32_t insn = *(uint32_t *)pc;
139
+ uint16_t meminfo = trace_mem_get_info(oi, false);
39
+ int is_write = 0;
140
uint32_t ret;
40
+
141
- uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, false);
41
+ /* Detect all store instructions at program counter. */
142
42
+ switch((insn >> 26) & 077) {
143
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
43
+ case 050: /* SB */
144
ret = lduw_be_p(g2h(env_cpu(env), ptr));
44
+ case 051: /* SH */
145
@@ -XXX,XX +XXX,XX @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
45
+ case 052: /* SWL */
146
46
+ case 053: /* SW */
147
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
47
+ case 054: /* SDL */
148
{
48
+ case 055: /* SDR */
149
+ MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
49
+ case 056: /* SWR */
150
+ uint16_t meminfo = trace_mem_get_info(oi, false);
50
+ case 070: /* SC */
151
uint32_t ret;
51
+ case 071: /* SWC1 */
152
- uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, false);
52
+ case 074: /* SCD */
153
53
+ case 075: /* SDC1 */
154
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
54
+ case 077: /* SD */
155
ret = ldl_be_p(g2h(env_cpu(env), ptr));
55
+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
156
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
56
+ case 072: /* SWC2 */
157
57
+ case 076: /* SDC2 */
158
uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
58
+#endif
159
{
59
+ is_write = 1;
160
+ MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
60
+ break;
161
+ uint16_t meminfo = trace_mem_get_info(oi, false);
61
+ case 023: /* COP1X */
162
uint64_t ret;
62
+ /* Required in all versions of MIPS64 since
163
- uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, false);
63
+ MIPS64r1 and subsequent versions of MIPS32r2. */
164
64
+ switch (insn & 077) {
165
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
65
+ case 010: /* SWXC1 */
166
ret = ldq_be_p(g2h(env_cpu(env), ptr));
66
+ case 011: /* SDXC1 */
167
@@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
67
+ case 015: /* SUXC1 */
168
68
+ is_write = 1;
169
uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
69
+ }
170
{
70
+ break;
171
+ MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
71
+ }
172
+ uint16_t meminfo = trace_mem_get_info(oi, false);
72
173
uint32_t ret;
73
- /* XXX: compute is_write */
174
- uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, false);
74
- is_write = 0;
175
75
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
176
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
76
}
177
ret = lduw_le_p(g2h(env_cpu(env), ptr));
178
@@ -XXX,XX +XXX,XX @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
179
180
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
181
{
182
+ MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
183
+ uint16_t meminfo = trace_mem_get_info(oi, false);
184
uint32_t ret;
185
- uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, false);
186
187
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
188
ret = ldl_le_p(g2h(env_cpu(env), ptr));
189
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
190
191
uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
192
{
193
+ MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
194
+ uint16_t meminfo = trace_mem_get_info(oi, false);
195
uint64_t ret;
196
- uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, false);
197
198
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
199
ret = ldq_le_p(g2h(env_cpu(env), ptr));
200
@@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
201
202
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
203
{
204
- uint16_t meminfo = trace_mem_get_info(MO_UB, MMU_USER_IDX, true);
205
+ MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
206
+ uint16_t meminfo = trace_mem_get_info(oi, true);
207
208
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
209
stb_p(g2h(env_cpu(env), ptr), val);
210
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
211
212
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
213
{
214
- uint16_t meminfo = trace_mem_get_info(MO_BEUW, MMU_USER_IDX, true);
215
+ MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
216
+ uint16_t meminfo = trace_mem_get_info(oi, true);
217
218
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
219
stw_be_p(g2h(env_cpu(env), ptr), val);
220
@@ -XXX,XX +XXX,XX @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
221
222
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
223
{
224
- uint16_t meminfo = trace_mem_get_info(MO_BEUL, MMU_USER_IDX, true);
225
+ MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
226
+ uint16_t meminfo = trace_mem_get_info(oi, true);
227
228
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
229
stl_be_p(g2h(env_cpu(env), ptr), val);
230
@@ -XXX,XX +XXX,XX @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
231
232
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
233
{
234
- uint16_t meminfo = trace_mem_get_info(MO_BEQ, MMU_USER_IDX, true);
235
+ MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
236
+ uint16_t meminfo = trace_mem_get_info(oi, true);
237
238
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
239
stq_be_p(g2h(env_cpu(env), ptr), val);
240
@@ -XXX,XX +XXX,XX @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
241
242
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
243
{
244
- uint16_t meminfo = trace_mem_get_info(MO_LEUW, MMU_USER_IDX, true);
245
+ MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
246
+ uint16_t meminfo = trace_mem_get_info(oi, true);
247
248
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
249
stw_le_p(g2h(env_cpu(env), ptr), val);
250
@@ -XXX,XX +XXX,XX @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
251
252
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
253
{
254
- uint16_t meminfo = trace_mem_get_info(MO_LEUL, MMU_USER_IDX, true);
255
+ MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
256
+ uint16_t meminfo = trace_mem_get_info(oi, true);
257
258
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
259
stl_le_p(g2h(env_cpu(env), ptr), val);
260
@@ -XXX,XX +XXX,XX @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
261
262
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
263
{
264
- uint16_t meminfo = trace_mem_get_info(MO_LEQ, MMU_USER_IDX, true);
265
+ MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
266
+ uint16_t meminfo = trace_mem_get_info(oi, true);
267
268
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
269
stq_le_p(g2h(env_cpu(env), ptr), val);
270
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
271
index XXXXXXX..XXXXXXX 100644
272
--- a/tcg/tcg-op.c
273
+++ b/tcg/tcg-op.c
274
@@ -XXX,XX +XXX,XX @@ static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info)
275
void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
276
{
277
MemOp orig_memop;
278
- uint16_t info = trace_mem_get_info(memop, idx, 0);
279
+ uint16_t info = trace_mem_get_info(make_memop_idx(memop, idx), 0);
280
281
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
282
memop = tcg_canonicalize_memop(memop, 0, 0);
283
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
284
void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
285
{
286
TCGv_i32 swap = NULL;
287
- uint16_t info = trace_mem_get_info(memop, idx, 1);
288
+ uint16_t info = trace_mem_get_info(make_memop_idx(memop, idx), 1);
289
290
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
291
memop = tcg_canonicalize_memop(memop, 0, 1);
292
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
293
294
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
295
memop = tcg_canonicalize_memop(memop, 1, 0);
296
- info = trace_mem_get_info(memop, idx, 0);
297
+ info = trace_mem_get_info(make_memop_idx(memop, idx), 0);
298
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
299
300
orig_memop = memop;
301
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
302
303
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
304
memop = tcg_canonicalize_memop(memop, 1, 1);
305
- info = trace_mem_get_info(memop, idx, 1);
306
+ info = trace_mem_get_info(make_memop_idx(memop, idx), 1);
307
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
308
309
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
310
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
311
index XXXXXXX..XXXXXXX 100644
312
--- a/accel/tcg/atomic_common.c.inc
313
+++ b/accel/tcg/atomic_common.c.inc
314
@@ -XXX,XX +XXX,XX @@ static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
315
MemOpIdx oi)
316
{
317
CPUState *cpu = env_cpu(env);
318
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
319
+ uint16_t info = trace_mem_get_info(oi, false);
320
321
trace_guest_mem_before_exec(cpu, addr, info);
322
trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
323
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
324
static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
325
MemOpIdx oi)
326
{
327
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), false);
328
+ uint16_t info = trace_mem_get_info(oi, false);
329
330
trace_guest_mem_before_exec(env_cpu(env), addr, info);
331
332
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
333
static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
334
MemOpIdx oi)
335
{
336
- uint16_t info = trace_mem_get_info(get_memop(oi), get_mmuidx(oi), true);
337
+ uint16_t info = trace_mem_get_info(oi, true);
338
339
trace_guest_mem_before_exec(env_cpu(env), addr, info);
77
340
78
--
341
--
79
2.25.1
342
2.25.1
80
343
81
344
diff view generated by jsdifflib
New patch
[PULL 09/28] accel/tcg: Pass MemOpIdx to atomic_trace_*_post
1
1
We will shortly use the MemOpIdx directly, but in the meantime
2
re-compute the trace meminfo.
3
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
accel/tcg/atomic_template.h | 48 +++++++++++++++++------------------
8
accel/tcg/atomic_common.c.inc | 30 +++++++++++-----------
9
2 files changed, 39 insertions(+), 39 deletions(-)
10
11
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/accel/tcg/atomic_template.h
14
+++ b/accel/tcg/atomic_template.h
15
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
16
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
17
PAGE_READ | PAGE_WRITE, retaddr);
18
DATA_TYPE ret;
19
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
20
21
+ atomic_trace_rmw_pre(env, addr, oi);
22
#if DATA_SIZE == 16
23
ret = atomic16_cmpxchg(haddr, cmpv, newv);
24
#else
25
ret = qatomic_cmpxchg__nocheck(haddr, cmpv, newv);
26
#endif
27
ATOMIC_MMU_CLEANUP;
28
- atomic_trace_rmw_post(env, addr, info);
29
+ atomic_trace_rmw_post(env, addr, oi);
30
return ret;
31
}
32
33
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
34
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
35
PAGE_READ, retaddr);
36
DATA_TYPE val;
37
- uint16_t info = atomic_trace_ld_pre(env, addr, oi);
38
39
+ atomic_trace_ld_pre(env, addr, oi);
40
val = atomic16_read(haddr);
41
ATOMIC_MMU_CLEANUP;
42
- atomic_trace_ld_post(env, addr, info);
43
+ atomic_trace_ld_post(env, addr, oi);
44
return val;
45
}
46
47
@@ -XXX,XX +XXX,XX @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
48
{
49
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
50
PAGE_WRITE, retaddr);
51
- uint16_t info = atomic_trace_st_pre(env, addr, oi);
52
53
+ atomic_trace_st_pre(env, addr, oi);
54
atomic16_set(haddr, val);
55
ATOMIC_MMU_CLEANUP;
56
- atomic_trace_st_post(env, addr, info);
57
+ atomic_trace_st_post(env, addr, oi);
58
}
59
#endif
60
#else
61
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
62
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
63
PAGE_READ | PAGE_WRITE, retaddr);
64
DATA_TYPE ret;
65
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
66
67
+ atomic_trace_rmw_pre(env, addr, oi);
68
ret = qatomic_xchg__nocheck(haddr, val);
69
ATOMIC_MMU_CLEANUP;
70
- atomic_trace_rmw_post(env, addr, info);
71
+ atomic_trace_rmw_post(env, addr, oi);
72
return ret;
73
}
74
75
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
76
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
77
PAGE_READ | PAGE_WRITE, retaddr); \
78
DATA_TYPE ret; \
79
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
80
+ atomic_trace_rmw_pre(env, addr, oi); \
81
ret = qatomic_##X(haddr, val); \
82
ATOMIC_MMU_CLEANUP; \
83
- atomic_trace_rmw_post(env, addr, info); \
84
+ atomic_trace_rmw_post(env, addr, oi); \
85
return ret; \
86
}
87
88
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
89
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
90
PAGE_READ | PAGE_WRITE, retaddr); \
91
XDATA_TYPE cmp, old, new, val = xval; \
92
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
93
+ atomic_trace_rmw_pre(env, addr, oi); \
94
smp_mb(); \
95
cmp = qatomic_read__nocheck(haddr); \
96
do { \
97
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
98
cmp = qatomic_cmpxchg__nocheck(haddr, old, new); \
99
} while (cmp != old); \
100
ATOMIC_MMU_CLEANUP; \
101
- atomic_trace_rmw_post(env, addr, info); \
102
+ atomic_trace_rmw_post(env, addr, oi); \
103
return RET; \
104
}
105
106
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
107
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
108
PAGE_READ | PAGE_WRITE, retaddr);
109
DATA_TYPE ret;
110
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
111
112
+ atomic_trace_rmw_pre(env, addr, oi);
113
#if DATA_SIZE == 16
114
ret = atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv));
115
#else
116
ret = qatomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv));
117
#endif
118
ATOMIC_MMU_CLEANUP;
119
- atomic_trace_rmw_post(env, addr, info);
120
+ atomic_trace_rmw_post(env, addr, oi);
121
return BSWAP(ret);
122
}
123
124
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr,
125
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
126
PAGE_READ, retaddr);
127
DATA_TYPE val;
128
- uint16_t info = atomic_trace_ld_pre(env, addr, oi);
129
130
+ atomic_trace_ld_pre(env, addr, oi);
131
val = atomic16_read(haddr);
132
ATOMIC_MMU_CLEANUP;
133
- atomic_trace_ld_post(env, addr, info);
134
+ atomic_trace_ld_post(env, addr, oi);
135
return BSWAP(val);
136
}
137
138
@@ -XXX,XX +XXX,XX @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
139
{
140
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
141
PAGE_WRITE, retaddr);
142
- uint16_t info = atomic_trace_st_pre(env, addr, oi);
143
144
+ atomic_trace_st_pre(env, addr, oi);
145
val = BSWAP(val);
146
atomic16_set(haddr, val);
147
ATOMIC_MMU_CLEANUP;
148
- atomic_trace_st_post(env, addr, info);
149
+ atomic_trace_st_post(env, addr, oi);
150
}
151
#endif
152
#else
153
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
154
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE,
155
PAGE_READ | PAGE_WRITE, retaddr);
156
ABI_TYPE ret;
157
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi);
158
159
+ atomic_trace_rmw_pre(env, addr, oi);
160
ret = qatomic_xchg__nocheck(haddr, BSWAP(val));
161
ATOMIC_MMU_CLEANUP;
162
- atomic_trace_rmw_post(env, addr, info);
163
+ atomic_trace_rmw_post(env, addr, oi);
164
return BSWAP(ret);
165
}
166
167
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
168
DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
169
PAGE_READ | PAGE_WRITE, retaddr); \
170
DATA_TYPE ret; \
171
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
172
+ atomic_trace_rmw_pre(env, addr, oi); \
173
ret = qatomic_##X(haddr, BSWAP(val)); \
174
ATOMIC_MMU_CLEANUP; \
175
- atomic_trace_rmw_post(env, addr, info); \
176
+ atomic_trace_rmw_post(env, addr, oi); \
177
return BSWAP(ret); \
178
}
179
180
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
181
XDATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \
182
PAGE_READ | PAGE_WRITE, retaddr); \
183
XDATA_TYPE ldo, ldn, old, new, val = xval; \
184
- uint16_t info = atomic_trace_rmw_pre(env, addr, oi); \
185
+ atomic_trace_rmw_pre(env, addr, oi); \
186
smp_mb(); \
187
ldn = qatomic_read__nocheck(haddr); \
188
do { \
189
@@ -XXX,XX +XXX,XX @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
190
ldn = qatomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \
191
} while (ldo != ldn); \
192
ATOMIC_MMU_CLEANUP; \
193
- atomic_trace_rmw_post(env, addr, info); \
194
+ atomic_trace_rmw_post(env, addr, oi); \
195
return RET; \
196
}
197
198
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
199
index XXXXXXX..XXXXXXX 100644
200
--- a/accel/tcg/atomic_common.c.inc
201
+++ b/accel/tcg/atomic_common.c.inc
202
@@ -XXX,XX +XXX,XX @@
203
* See the COPYING file in the top-level directory.
204
*/
205
206
-static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
207
- MemOpIdx oi)
208
+static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
209
+ MemOpIdx oi)
210
{
211
CPUState *cpu = env_cpu(env);
212
uint16_t info = trace_mem_get_info(oi, false);
213
214
trace_guest_mem_before_exec(cpu, addr, info);
215
trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
216
-
217
- return info;
218
}
219
220
static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
221
- uint16_t info)
222
+ MemOpIdx oi)
223
{
224
+ uint16_t info = trace_mem_get_info(oi, false);
225
+
226
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
227
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST);
228
}
229
230
#if HAVE_ATOMIC128
231
-static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
232
- MemOpIdx oi)
233
+static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
234
+ MemOpIdx oi)
235
{
236
uint16_t info = trace_mem_get_info(oi, false);
237
238
trace_guest_mem_before_exec(env_cpu(env), addr, info);
239
-
240
- return info;
241
}
242
243
static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
244
- uint16_t info)
245
+ MemOpIdx oi)
246
{
247
+ uint16_t info = trace_mem_get_info(oi, false);
248
+
249
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
250
}
251
252
-static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
253
- MemOpIdx oi)
254
+static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
255
+ MemOpIdx oi)
256
{
257
uint16_t info = trace_mem_get_info(oi, true);
258
259
trace_guest_mem_before_exec(env_cpu(env), addr, info);
260
-
261
- return info;
262
}
263
264
static void atomic_trace_st_post(CPUArchState *env, target_ulong addr,
265
- uint16_t info)
266
+ MemOpIdx oi)
267
{
268
+ uint16_t info = trace_mem_get_info(oi, false);
269
+
270
qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
271
}
272
#endif
273
--
274
2.25.1
275
276
diff view generated by jsdifflib
New patch
[PULL 10/28] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb
1
Use the MemOpIdx directly, rather than the rearrangement
2
of the same bits currently done by the trace infrastructure.
3
Pass in enum qemu_plugin_mem_rw so that we are able to treat
4
read-modify-write operations as a single operation.
1
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/qemu/plugin.h | 26 ++++++++++++++++++++++++--
10
accel/tcg/cputlb.c | 4 ++--
11
accel/tcg/plugin-gen.c | 5 ++---
12
accel/tcg/user-exec.c | 28 ++++++++++++++--------------
13
plugins/api.c | 19 +++++++++++--------
14
plugins/core.c | 10 +++++-----
15
tcg/tcg-op.c | 30 +++++++++++++++++++++---------
16
accel/tcg/atomic_common.c.inc | 13 +++----------
17
8 files changed, 82 insertions(+), 53 deletions(-)
18
19
diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/qemu/plugin.h
22
+++ b/include/qemu/plugin.h
23
@@ -XXX,XX +XXX,XX @@
24
#include "qemu/error-report.h"
25
#include "qemu/queue.h"
26
#include "qemu/option.h"
27
+#include "exec/memopidx.h"
28
29
/*
30
* Events that plugins can subscribe to.
31
@@ -XXX,XX +XXX,XX @@ enum qemu_plugin_event {
32
struct qemu_plugin_desc;
33
typedef QTAILQ_HEAD(, qemu_plugin_desc) QemuPluginList;
34
35
+/*
36
+ * Construct a qemu_plugin_meminfo_t.
37
+ */
38
+static inline qemu_plugin_meminfo_t
39
+make_plugin_meminfo(MemOpIdx oi, enum qemu_plugin_mem_rw rw)
40
+{
41
+ return oi | (rw << 16);
42
+}
43
+
44
+/*
45
+ * Extract the memory operation direction from a qemu_plugin_meminfo_t.
46
+ * Other portions may be extracted via get_memop and get_mmuidx.
47
+ */
48
+static inline enum qemu_plugin_mem_rw
49
+get_plugin_meminfo_rw(qemu_plugin_meminfo_t i)
50
+{
51
+ return i >> 16;
52
+}
53
+
54
#ifdef CONFIG_PLUGIN
55
extern QemuOptsList qemu_plugin_opts;
56
57
@@ -XXX,XX +XXX,XX @@ qemu_plugin_vcpu_syscall(CPUState *cpu, int64_t num, uint64_t a1,
58
uint64_t a6, uint64_t a7, uint64_t a8);
59
void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret);
60
61
-void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t meminfo);
62
+void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
63
+ MemOpIdx oi, enum qemu_plugin_mem_rw rw);
64
65
void qemu_plugin_flush_cb(void);
66
67
@@ -XXX,XX +XXX,XX @@ void qemu_plugin_vcpu_syscall_ret(CPUState *cpu, int64_t num, int64_t ret)
68
{ }
69
70
static inline void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
71
- uint32_t meminfo)
72
+ MemOpIdx oi,
73
+ enum qemu_plugin_mem_rw rw)
74
{ }
75
76
static inline void qemu_plugin_flush_cb(void)
77
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/accel/tcg/cputlb.c
80
+++ b/accel/tcg/cputlb.c
81
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
82
83
ret = full_load(env, addr, oi, retaddr);
84
85
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
86
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
87
88
return ret;
89
}
90
@@ -XXX,XX +XXX,XX @@ cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
91
92
store_helper(env, addr, val, oi, retaddr, op);
93
94
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, meminfo);
95
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
96
}
97
98
void cpu_stb_mmuidx_ra(CPUArchState *env, target_ulong addr, uint32_t val,
99
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/accel/tcg/plugin-gen.c
102
+++ b/accel/tcg/plugin-gen.c
103
@@ -XXX,XX +XXX,XX @@
104
#include "qemu/osdep.h"
105
#include "tcg/tcg.h"
106
#include "tcg/tcg-op.h"
107
-#include "trace/mem.h"
108
#include "exec/exec-all.h"
109
#include "exec/plugin-gen.h"
110
#include "exec/translator.h"
111
@@ -XXX,XX +XXX,XX @@ static void gen_mem_wrapped(enum plugin_gen_cb type,
112
const union mem_gen_fn *f, TCGv addr,
113
uint32_t info, bool is_mem)
114
{
115
- int wr = !!(info & TRACE_MEM_ST);
116
+ enum qemu_plugin_mem_rw rw = get_plugin_meminfo_rw(info);
117
118
- gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, wr);
119
+ gen_plugin_cb_start(PLUGIN_GEN_FROM_MEM, type, rw);
120
if (is_mem) {
121
f->mem_fn(addr, info);
122
} else {
123
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/accel/tcg/user-exec.c
126
+++ b/accel/tcg/user-exec.c
127
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
128
129
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
130
ret = ldub_p(g2h(env_cpu(env), ptr));
131
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
132
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
133
return ret;
134
}
135
136
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
137
138
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
139
ret = lduw_be_p(g2h(env_cpu(env), ptr));
140
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
141
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
142
return ret;
143
}
144
145
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
146
147
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
148
ret = ldl_be_p(g2h(env_cpu(env), ptr));
149
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
150
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
151
return ret;
152
}
153
154
@@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
155
156
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
157
ret = ldq_be_p(g2h(env_cpu(env), ptr));
158
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
159
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
160
return ret;
161
}
162
163
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
164
165
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
166
ret = lduw_le_p(g2h(env_cpu(env), ptr));
167
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
168
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
169
return ret;
170
}
171
172
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
173
174
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
175
ret = ldl_le_p(g2h(env_cpu(env), ptr));
176
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
177
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
178
return ret;
179
}
180
181
@@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
182
183
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
184
ret = ldq_le_p(g2h(env_cpu(env), ptr));
185
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
186
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
187
return ret;
188
}
189
190
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
191
192
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
193
stb_p(g2h(env_cpu(env), ptr), val);
194
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
195
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
196
}
197
198
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
199
@@ -XXX,XX +XXX,XX @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
200
201
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
202
stw_be_p(g2h(env_cpu(env), ptr), val);
203
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
204
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
205
}
206
207
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
208
@@ -XXX,XX +XXX,XX @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
209
210
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
211
stl_be_p(g2h(env_cpu(env), ptr), val);
212
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
213
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
214
}
215
216
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
217
@@ -XXX,XX +XXX,XX @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
218
219
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
220
stq_be_p(g2h(env_cpu(env), ptr), val);
221
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
222
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
223
}
224
225
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
226
@@ -XXX,XX +XXX,XX @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
227
228
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
229
stw_le_p(g2h(env_cpu(env), ptr), val);
230
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
231
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
232
}
233
234
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
235
@@ -XXX,XX +XXX,XX @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
236
237
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
238
stl_le_p(g2h(env_cpu(env), ptr), val);
239
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
240
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
241
}
242
243
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
244
@@ -XXX,XX +XXX,XX @@ void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
245
246
trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
247
stq_le_p(g2h(env_cpu(env), ptr), val);
248
- qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, meminfo);
249
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
250
}
251
252
void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
253
diff --git a/plugins/api.c b/plugins/api.c
254
index XXXXXXX..XXXXXXX 100644
255
--- a/plugins/api.c
256
+++ b/plugins/api.c
257
@@ -XXX,XX +XXX,XX @@
258
#include "qemu/plugin-memory.h"
259
#include "hw/boards.h"
260
#endif
261
-#include "trace/mem.h"
262
263
/* Uninstall and Reset handlers */
264
265
@@ -XXX,XX +XXX,XX @@ const char *qemu_plugin_insn_symbol(const struct qemu_plugin_insn *insn)
266
267
unsigned qemu_plugin_mem_size_shift(qemu_plugin_meminfo_t info)
268
{
269
- return info & TRACE_MEM_SZ_SHIFT_MASK;
270
+ MemOp op = get_memop(info);
271
+ return op & MO_SIZE;
272
}
273
274
bool qemu_plugin_mem_is_sign_extended(qemu_plugin_meminfo_t info)
275
{
276
- return !!(info & TRACE_MEM_SE);
277
+ MemOp op = get_memop(info);
278
+ return op & MO_SIGN;
279
}
280
281
bool qemu_plugin_mem_is_big_endian(qemu_plugin_meminfo_t info)
282
{
283
- return !!(info & TRACE_MEM_BE);
284
+ MemOp op = get_memop(info);
285
+ return (op & MO_BSWAP) == MO_BE;
286
}
287
288
bool qemu_plugin_mem_is_store(qemu_plugin_meminfo_t info)
289
{
290
- return !!(info & TRACE_MEM_ST);
291
+ return get_plugin_meminfo_rw(info) & QEMU_PLUGIN_MEM_W;
292
}
293
294
/*
295
@@ -XXX,XX +XXX,XX @@ struct qemu_plugin_hwaddr *qemu_plugin_get_hwaddr(qemu_plugin_meminfo_t info,
296
{
297
#ifdef CONFIG_SOFTMMU
298
CPUState *cpu = current_cpu;
299
- unsigned int mmu_idx = info >> TRACE_MEM_MMU_SHIFT;
300
- hwaddr_info.is_store = info & TRACE_MEM_ST;
301
+ unsigned int mmu_idx = get_mmuidx(info);
302
+ enum qemu_plugin_mem_rw rw = get_plugin_meminfo_rw(info);
303
+ hwaddr_info.is_store = (rw & QEMU_PLUGIN_MEM_W) != 0;
304
305
if (!tlb_plugin_lookup(cpu, vaddr, mmu_idx,
306
- info & TRACE_MEM_ST, &hwaddr_info)) {
307
+ hwaddr_info.is_store, &hwaddr_info)) {
308
error_report("invalid use of qemu_plugin_get_hwaddr");
309
return NULL;
310
}
311
diff --git a/plugins/core.c b/plugins/core.c
312
index XXXXXXX..XXXXXXX 100644
313
--- a/plugins/core.c
314
+++ b/plugins/core.c
315
@@ -XXX,XX +XXX,XX @@
316
#include "exec/helper-proto.h"
317
#include "tcg/tcg.h"
318
#include "tcg/tcg-op.h"
319
-#include "trace/mem.h" /* mem_info macros */
320
#include "plugin.h"
321
#include "qemu/compiler.h"
322
323
@@ -XXX,XX +XXX,XX @@ void exec_inline_op(struct qemu_plugin_dyn_cb *cb)
324
}
325
}
326
327
-void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t info)
328
+void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr,
329
+ MemOpIdx oi, enum qemu_plugin_mem_rw rw)
330
{
331
GArray *arr = cpu->plugin_mem_cbs;
332
size_t i;
333
@@ -XXX,XX +XXX,XX @@ void qemu_plugin_vcpu_mem_cb(CPUState *cpu, uint64_t vaddr, uint32_t info)
334
for (i = 0; i < arr->len; i++) {
335
struct qemu_plugin_dyn_cb *cb =
336
&g_array_index(arr, struct qemu_plugin_dyn_cb, i);
337
- int w = !!(info & TRACE_MEM_ST) + 1;
338
339
- if (!(w & cb->rw)) {
340
+ if (!(rw & cb->rw)) {
341
break;
342
}
343
switch (cb->type) {
344
case PLUGIN_CB_REGULAR:
345
- cb->f.vcpu_mem(cpu->cpu_index, info, vaddr, cb->userp);
346
+ cb->f.vcpu_mem(cpu->cpu_index, make_plugin_meminfo(oi, rw),
347
+ vaddr, cb->userp);
348
break;
349
case PLUGIN_CB_INLINE:
350
exec_inline_op(cb);
351
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
352
index XXXXXXX..XXXXXXX 100644
353
--- a/tcg/tcg-op.c
354
+++ b/tcg/tcg-op.c
355
@@ -XXX,XX +XXX,XX @@ static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr)
356
return vaddr;
357
}
358
359
-static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info)
360
+static void plugin_gen_mem_callbacks(TCGv vaddr, MemOpIdx oi,
361
+ enum qemu_plugin_mem_rw rw)
362
{
363
#ifdef CONFIG_PLUGIN
364
if (tcg_ctx->plugin_insn != NULL) {
365
+ qemu_plugin_meminfo_t info = make_plugin_meminfo(oi, rw);
366
plugin_gen_empty_mem_callback(vaddr, info);
367
tcg_temp_free(vaddr);
368
}
369
@@ -XXX,XX +XXX,XX @@ static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info)
370
void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
371
{
372
MemOp orig_memop;
373
- uint16_t info = trace_mem_get_info(make_memop_idx(memop, idx), 0);
374
+ MemOpIdx oi;
375
+ uint16_t info;
376
377
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
378
memop = tcg_canonicalize_memop(memop, 0, 0);
379
+ oi = make_memop_idx(memop, idx);
380
+ info = trace_mem_get_info(oi, 0);
381
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
382
383
orig_memop = memop;
384
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
385
386
addr = plugin_prep_mem_callbacks(addr);
387
gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);
388
- plugin_gen_mem_callbacks(addr, info);
389
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R);
390
391
if ((orig_memop ^ memop) & MO_BSWAP) {
392
switch (orig_memop & MO_SIZE) {
393
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
394
void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
395
{
396
TCGv_i32 swap = NULL;
397
- uint16_t info = trace_mem_get_info(make_memop_idx(memop, idx), 1);
398
+ MemOpIdx oi;
399
+ uint16_t info;
400
401
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
402
memop = tcg_canonicalize_memop(memop, 0, 1);
403
+ oi = make_memop_idx(memop, idx);
404
+ info = trace_mem_get_info(oi, 1);
405
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
406
407
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
408
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
409
} else {
410
gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);
411
}
412
- plugin_gen_mem_callbacks(addr, info);
413
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W);
414
415
if (swap) {
416
tcg_temp_free_i32(swap);
417
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
418
void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
419
{
420
MemOp orig_memop;
421
+ MemOpIdx oi;
422
uint16_t info;
423
424
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
425
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
426
427
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
428
memop = tcg_canonicalize_memop(memop, 1, 0);
429
- info = trace_mem_get_info(make_memop_idx(memop, idx), 0);
430
+ oi = make_memop_idx(memop, idx);
431
+ info = trace_mem_get_info(oi, 0);
432
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
433
434
orig_memop = memop;
435
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
436
437
addr = plugin_prep_mem_callbacks(addr);
438
gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx);
439
- plugin_gen_mem_callbacks(addr, info);
440
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R);
441
442
if ((orig_memop ^ memop) & MO_BSWAP) {
443
int flags = (orig_memop & MO_SIGN
444
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
445
void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
446
{
447
TCGv_i64 swap = NULL;
448
+ MemOpIdx oi;
449
uint16_t info;
450
451
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
452
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
453
454
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
455
memop = tcg_canonicalize_memop(memop, 1, 1);
456
- info = trace_mem_get_info(make_memop_idx(memop, idx), 1);
457
+ oi = make_memop_idx(memop, idx);
458
+ info = trace_mem_get_info(oi, 1);
459
trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
460
461
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
462
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
463
464
addr = plugin_prep_mem_callbacks(addr);
465
gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);
466
- plugin_gen_mem_callbacks(addr, info);
467
+ plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W);
468
469
if (swap) {
470
tcg_temp_free_i64(swap);
471
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
472
index XXXXXXX..XXXXXXX 100644
473
--- a/accel/tcg/atomic_common.c.inc
474
+++ b/accel/tcg/atomic_common.c.inc
475
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
476
static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
477
MemOpIdx oi)
478
{
479
- uint16_t info = trace_mem_get_info(oi, false);
480
-
481
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
482
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST);
483
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_RW);
484
}
485
486
#if HAVE_ATOMIC128
487
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
488
static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
489
MemOpIdx oi)
490
{
491
- uint16_t info = trace_mem_get_info(oi, false);
492
-
493
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
494
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R);
495
}
496
497
static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
498
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
499
static void atomic_trace_st_post(CPUArchState *env, target_ulong addr,
500
MemOpIdx oi)
501
{
502
- uint16_t info = trace_mem_get_info(oi, false);
503
-
504
- qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info);
505
+ qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W);
506
}
507
#endif
508
509
--
510
2.25.1
511
512
diff view generated by jsdifflib
New patch
[PULL 11/28] trace: Split guest_mem_before
1
There is no point in encoding load/store within a bit of
2
the memory trace info operand. Represent atomic operations
3
as a single read-modify-write tracepoint. Use MemOpIdx
4
instead of inventing a form specifically for traces.
1
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
accel/tcg/atomic_template.h | 1 -
10
trace/mem.h | 51 -----------------------------------
11
accel/tcg/cputlb.c | 7 ++---
12
accel/tcg/user-exec.c | 44 +++++++++++-------------------
13
tcg/tcg-op.c | 17 +++---------
14
accel/tcg/atomic_common.c.inc | 12 +++------
15
trace-events | 18 +++----------
16
7 files changed, 28 insertions(+), 122 deletions(-)
17
delete mode 100644 trace/mem.h
18
19
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/accel/tcg/atomic_template.h
22
+++ b/accel/tcg/atomic_template.h
23
@@ -XXX,XX +XXX,XX @@
24
*/
25
26
#include "qemu/plugin.h"
27
-#include "trace/mem.h"
28
29
#if DATA_SIZE == 16
30
# define SUFFIX o
31
diff --git a/trace/mem.h b/trace/mem.h
32
deleted file mode 100644
33
index XXXXXXX..XXXXXXX
34
--- a/trace/mem.h
35
+++ /dev/null
36
@@ -XXX,XX +XXX,XX @@
37
-/*
38
- * Helper functions for guest memory tracing
39
- *
40
- * Copyright (C) 2016 Lluís Vilanova <vilanova@ac.upc.edu>
41
- *
42
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
43
- * See the COPYING file in the top-level directory.
44
- */
45
-
46
-#ifndef TRACE__MEM_H
47
-#define TRACE__MEM_H
48
-
49
-#include "exec/memopidx.h"
50
-
51
-#define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */
52
-#define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */
53
-#define TRACE_MEM_BE (1ULL << 5) /* big endian (y/n) */
54
-#define TRACE_MEM_ST (1ULL << 6) /* store (y/n) */
55
-#define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */
56
-
57
-/**
58
- * trace_mem_get_info:
59
- *
60
- * Return a value for the 'info' argument in guest memory access traces.
61
- */
62
-static inline uint16_t trace_mem_get_info(MemOpIdx oi, bool store)
63
-{
64
- MemOp op = get_memop(oi);
65
- uint32_t size_shift = op & MO_SIZE;
66
- bool sign_extend = op & MO_SIGN;
67
- bool big_endian = (op & MO_BSWAP) == MO_BE;
68
- uint16_t res;
69
-
70
- res = size_shift & TRACE_MEM_SZ_SHIFT_MASK;
71
- if (sign_extend) {
72
- res |= TRACE_MEM_SE;
73
- }
74
- if (big_endian) {
75
- res |= TRACE_MEM_BE;
76
- }
77
- if (store) {
78
- res |= TRACE_MEM_ST;
79
- }
80
-#ifdef CONFIG_SOFTMMU
81
- res |= get_mmuidx(oi) << TRACE_MEM_MMU_SHIFT;
82
-#endif
83
-
84
- return res;
85
-}
86
-
87
-#endif /* TRACE__MEM_H */
88
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/accel/tcg/cputlb.c
91
+++ b/accel/tcg/cputlb.c
92
@@ -XXX,XX +XXX,XX @@
93
#include "qemu/atomic128.h"
94
#include "exec/translate-all.h"
95
#include "trace/trace-root.h"
96
-#include "trace/mem.h"
97
#include "tb-hash.h"
98
#include "internal.h"
99
#ifdef CONFIG_PLUGIN
100
@@ -XXX,XX +XXX,XX @@ static inline uint64_t cpu_load_helper(CPUArchState *env, abi_ptr addr,
101
MemOp op, FullLoadHelper *full_load)
102
{
103
MemOpIdx oi = make_memop_idx(op, mmu_idx);
104
- uint16_t meminfo = trace_mem_get_info(oi, false);
105
uint64_t ret;
106
107
- trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
108
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
109
110
ret = full_load(env, addr, oi, retaddr);
111
112
@@ -XXX,XX +XXX,XX @@ cpu_store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
113
int mmu_idx, uintptr_t retaddr, MemOp op)
114
{
115
MemOpIdx oi = make_memop_idx(op, mmu_idx);
116
- uint16_t meminfo = trace_mem_get_info(oi, true);
117
118
- trace_guest_mem_before_exec(env_cpu(env), addr, meminfo);
119
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
120
121
store_helper(env, addr, val, oi, retaddr, op);
122
123
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/accel/tcg/user-exec.c
126
+++ b/accel/tcg/user-exec.c
127
@@ -XXX,XX +XXX,XX @@
128
#include "exec/helper-proto.h"
129
#include "qemu/atomic128.h"
130
#include "trace/trace-root.h"
131
-#include "trace/mem.h"
132
+#include "internal.h"
133
134
#undef EAX
135
#undef ECX
136
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
137
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr)
138
{
139
MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
140
- uint16_t meminfo = trace_mem_get_info(oi, false);
141
uint32_t ret;
142
143
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
144
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
145
ret = ldub_p(g2h(env_cpu(env), ptr));
146
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
147
return ret;
148
@@ -XXX,XX +XXX,XX @@ int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr)
149
uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr)
150
{
151
MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
152
- uint16_t meminfo = trace_mem_get_info(oi, false);
153
uint32_t ret;
154
155
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
156
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
157
ret = lduw_be_p(g2h(env_cpu(env), ptr));
158
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
159
return ret;
160
@@ -XXX,XX +XXX,XX @@ int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr)
161
uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
162
{
163
MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
164
- uint16_t meminfo = trace_mem_get_info(oi, false);
165
uint32_t ret;
166
167
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
168
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
169
ret = ldl_be_p(g2h(env_cpu(env), ptr));
170
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
171
return ret;
172
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr)
173
uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
174
{
175
MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
176
- uint16_t meminfo = trace_mem_get_info(oi, false);
177
uint64_t ret;
178
179
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
180
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
181
ret = ldq_be_p(g2h(env_cpu(env), ptr));
182
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
183
return ret;
184
@@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr)
185
uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr)
186
{
187
MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
188
- uint16_t meminfo = trace_mem_get_info(oi, false);
189
uint32_t ret;
190
191
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
192
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
193
ret = lduw_le_p(g2h(env_cpu(env), ptr));
194
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
195
return ret;
196
@@ -XXX,XX +XXX,XX @@ int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr)
197
uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
198
{
199
MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
200
- uint16_t meminfo = trace_mem_get_info(oi, false);
201
uint32_t ret;
202
203
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
204
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
205
ret = ldl_le_p(g2h(env_cpu(env), ptr));
206
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
207
return ret;
208
@@ -XXX,XX +XXX,XX @@ uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr)
209
uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr)
210
{
211
MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
212
- uint16_t meminfo = trace_mem_get_info(oi, false);
213
uint64_t ret;
214
215
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
216
+ trace_guest_ld_before_exec(env_cpu(env), ptr, oi);
217
ret = ldq_le_p(g2h(env_cpu(env), ptr));
218
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_R);
219
return ret;
220
@@ -XXX,XX +XXX,XX @@ uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr)
221
void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
222
{
223
MemOpIdx oi = make_memop_idx(MO_UB, MMU_USER_IDX);
224
- uint16_t meminfo = trace_mem_get_info(oi, true);
225
226
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
227
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
228
stb_p(g2h(env_cpu(env), ptr), val);
229
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
230
}
231
@@ -XXX,XX +XXX,XX @@ void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
232
void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
233
{
234
MemOpIdx oi = make_memop_idx(MO_BEUW, MMU_USER_IDX);
235
- uint16_t meminfo = trace_mem_get_info(oi, true);
236
237
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
238
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
239
stw_be_p(g2h(env_cpu(env), ptr), val);
240
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
241
}
242
@@ -XXX,XX +XXX,XX @@ void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
243
void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
244
{
245
MemOpIdx oi = make_memop_idx(MO_BEUL, MMU_USER_IDX);
246
- uint16_t meminfo = trace_mem_get_info(oi, true);
247
248
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
249
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
250
stl_be_p(g2h(env_cpu(env), ptr), val);
251
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
252
}
253
@@ -XXX,XX +XXX,XX @@ void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
254
void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
255
{
256
MemOpIdx oi = make_memop_idx(MO_BEQ, MMU_USER_IDX);
257
- uint16_t meminfo = trace_mem_get_info(oi, true);
258
259
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
260
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
261
stq_be_p(g2h(env_cpu(env), ptr), val);
262
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
263
}
264
@@ -XXX,XX +XXX,XX @@ void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
265
void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
266
{
267
MemOpIdx oi = make_memop_idx(MO_LEUW, MMU_USER_IDX);
268
- uint16_t meminfo = trace_mem_get_info(oi, true);
269
270
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
271
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
272
stw_le_p(g2h(env_cpu(env), ptr), val);
273
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
274
}
275
@@ -XXX,XX +XXX,XX @@ void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
276
void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
277
{
278
MemOpIdx oi = make_memop_idx(MO_LEUL, MMU_USER_IDX);
279
- uint16_t meminfo = trace_mem_get_info(oi, true);
280
281
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
282
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
283
stl_le_p(g2h(env_cpu(env), ptr), val);
284
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
285
}
286
@@ -XXX,XX +XXX,XX @@ void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val)
287
void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val)
288
{
289
MemOpIdx oi = make_memop_idx(MO_LEQ, MMU_USER_IDX);
290
- uint16_t meminfo = trace_mem_get_info(oi, true);
291
292
- trace_guest_mem_before_exec(env_cpu(env), ptr, meminfo);
293
+ trace_guest_st_before_exec(env_cpu(env), ptr, oi);
294
stq_le_p(g2h(env_cpu(env), ptr), val);
295
qemu_plugin_vcpu_mem_cb(env_cpu(env), ptr, oi, QEMU_PLUGIN_MEM_W);
296
}
297
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
298
index XXXXXXX..XXXXXXX 100644
299
--- a/tcg/tcg-op.c
300
+++ b/tcg/tcg-op.c
301
@@ -XXX,XX +XXX,XX @@
302
#include "tcg/tcg-op.h"
303
#include "tcg/tcg-mo.h"
304
#include "trace-tcg.h"
305
-#include "trace/mem.h"
306
#include "exec/plugin-gen.h"
307
308
/* Reduce the number of ifdefs below. This assumes that all uses of
309
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
310
{
311
MemOp orig_memop;
312
MemOpIdx oi;
313
- uint16_t info;
314
315
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
316
memop = tcg_canonicalize_memop(memop, 0, 0);
317
oi = make_memop_idx(memop, idx);
318
- info = trace_mem_get_info(oi, 0);
319
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
320
+ trace_guest_ld_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
321
322
orig_memop = memop;
323
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
324
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop)
325
{
326
TCGv_i32 swap = NULL;
327
MemOpIdx oi;
328
- uint16_t info;
329
330
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
331
memop = tcg_canonicalize_memop(memop, 0, 1);
332
oi = make_memop_idx(memop, idx);
333
- info = trace_mem_get_info(oi, 1);
334
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
335
+ trace_guest_st_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
336
337
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
338
swap = tcg_temp_new_i32();
339
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
340
{
341
MemOp orig_memop;
342
MemOpIdx oi;
343
- uint16_t info;
344
345
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
346
tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
347
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
348
tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
349
memop = tcg_canonicalize_memop(memop, 1, 0);
350
oi = make_memop_idx(memop, idx);
351
- info = trace_mem_get_info(oi, 0);
352
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
353
+ trace_guest_ld_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
354
355
orig_memop = memop;
356
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
357
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
358
{
359
TCGv_i64 swap = NULL;
360
MemOpIdx oi;
361
- uint16_t info;
362
363
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
364
tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
365
@@ -XXX,XX +XXX,XX @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop)
366
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
367
memop = tcg_canonicalize_memop(memop, 1, 1);
368
oi = make_memop_idx(memop, idx);
369
- info = trace_mem_get_info(oi, 1);
370
- trace_guest_mem_before_tcg(tcg_ctx->cpu, cpu_env, addr, info);
371
+ trace_guest_st_before_tcg(tcg_ctx->cpu, cpu_env, addr, oi);
372
373
if (!TCG_TARGET_HAS_MEMORY_BSWAP && (memop & MO_BSWAP)) {
374
swap = tcg_temp_new_i64();
375
diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc
376
index XXXXXXX..XXXXXXX 100644
377
--- a/accel/tcg/atomic_common.c.inc
378
+++ b/accel/tcg/atomic_common.c.inc
379
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr,
380
MemOpIdx oi)
381
{
382
CPUState *cpu = env_cpu(env);
383
- uint16_t info = trace_mem_get_info(oi, false);
384
385
- trace_guest_mem_before_exec(cpu, addr, info);
386
- trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST);
387
+ trace_guest_rmw_before_exec(cpu, addr, oi);
388
}
389
390
static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
391
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr,
392
static void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr,
393
MemOpIdx oi)
394
{
395
- uint16_t info = trace_mem_get_info(oi, false);
396
-
397
- trace_guest_mem_before_exec(env_cpu(env), addr, info);
398
+ trace_guest_ld_before_exec(env_cpu(env), addr, oi);
399
}
400
401
static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
402
@@ -XXX,XX +XXX,XX @@ static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr,
403
static void atomic_trace_st_pre(CPUArchState *env, target_ulong addr,
404
MemOpIdx oi)
405
{
406
- uint16_t info = trace_mem_get_info(oi, true);
407
-
408
- trace_guest_mem_before_exec(env_cpu(env), addr, info);
409
+ trace_guest_st_before_exec(env_cpu(env), addr, oi);
410
}
411
412
static void atomic_trace_st_post(CPUArchState *env, target_ulong addr,
413
diff --git a/trace-events b/trace-events
414
index XXXXXXX..XXXXXXX 100644
415
--- a/trace-events
416
+++ b/trace-events
417
@@ -XXX,XX +XXX,XX @@ vcpu guest_cpu_reset(void)
418
# tcg/tcg-op.c
419
420
# @vaddr: Access' virtual address.
421
-# @info : Access' information (see below).
422
+# @memopidx: Access' information (see below).
423
#
424
# Start virtual memory access (before any potential access violation).
425
-#
426
# Does not include memory accesses performed by devices.
427
#
428
-# Access information can be parsed as:
429
-#
430
-# struct mem_info {
431
-# uint8_t size_shift : 4; /* interpreted as "1 << size_shift" bytes */
432
-# bool sign_extend: 1; /* sign-extended */
433
-# uint8_t endianness : 1; /* 0: little, 1: big */
434
-# bool store : 1; /* whether it is a store operation */
435
-# pad : 1;
436
-# uint8_t mmuidx : 4; /* mmuidx (softmmu only) */
437
-# };
438
-#
439
# Mode: user, softmmu
440
# Targets: TCG(all)
441
-vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d"
442
+vcpu tcg guest_ld_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
443
+vcpu tcg guest_st_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
444
+vcpu tcg guest_rmw_before(TCGv vaddr, uint32_t memopidx) "info=%d", "vaddr=0x%016"PRIx64" memopidx=0x%x"
445
446
# include/user/syscall-trace.h
447
448
--
449
2.25.1
450
451
diff view generated by jsdifflib
[PULL 10/11] tcg: Remove TCG_TARGET_HAS_cmp_vec
[PULL 12/28] hw/core/cpu: Re-sort the non-pointers to the end of CPUClass
1
The cmp_vec opcode is mandatory; this symbol is unused.
1
Despite the comment, the members were not kept at the end.
2
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
5
---
6
tcg/aarch64/tcg-target.h | 1 -
6
include/hw/core/cpu.h | 11 +++++++----
7
tcg/i386/tcg-target.h | 1 -
7
1 file changed, 7 insertions(+), 4 deletions(-)
8
tcg/ppc/tcg-target.h | 1 -
9
3 files changed, 3 deletions(-)
10
8
11
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
9
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
12
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/aarch64/tcg-target.h
11
--- a/include/hw/core/cpu.h
14
+++ b/tcg/aarch64/tcg-target.h
12
+++ b/include/hw/core/cpu.h
15
@@ -XXX,XX +XXX,XX @@ typedef enum {
13
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
16
#define TCG_TARGET_HAS_shi_vec 1
14
ObjectClass *(*class_by_name)(const char *cpu_model);
17
#define TCG_TARGET_HAS_shs_vec 0
15
void (*parse_features)(const char *typename, char *str, Error **errp);
18
#define TCG_TARGET_HAS_shv_vec 1
16
19
-#define TCG_TARGET_HAS_cmp_vec 1
17
- int reset_dump_flags;
20
#define TCG_TARGET_HAS_mul_vec 1
18
bool (*has_work)(CPUState *cpu);
21
#define TCG_TARGET_HAS_sat_vec 1
19
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
22
#define TCG_TARGET_HAS_minmax_vec 1
20
uint8_t *buf, int len, bool is_write);
23
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
21
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
24
index XXXXXXX..XXXXXXX 100644
22
void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
25
--- a/tcg/i386/tcg-target.h
23
26
+++ b/tcg/i386/tcg-target.h
24
const char *deprecation_note;
27
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
25
- /* Keep non-pointer data at the end to minimize holes. */
28
#define TCG_TARGET_HAS_shi_vec 1
26
- int gdb_num_core_regs;
29
#define TCG_TARGET_HAS_shs_vec 1
27
- bool gdb_stop_before_watchpoint;
30
#define TCG_TARGET_HAS_shv_vec have_avx2
28
struct AccelCPUClass *accel_cpu;
31
-#define TCG_TARGET_HAS_cmp_vec 1
29
32
#define TCG_TARGET_HAS_mul_vec 1
30
/* when system emulation is not available, this pointer is NULL */
33
#define TCG_TARGET_HAS_sat_vec 1
31
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
34
#define TCG_TARGET_HAS_minmax_vec 1
32
* class data that depends on the accelerator, see accel/accel-common.c.
35
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
33
*/
36
index XXXXXXX..XXXXXXX 100644
34
void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc);
37
--- a/tcg/ppc/tcg-target.h
35
+
38
+++ b/tcg/ppc/tcg-target.h
36
+ /*
39
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
37
+ * Keep non-pointer data at the end to minimize holes.
40
#define TCG_TARGET_HAS_shi_vec 0
38
+ */
41
#define TCG_TARGET_HAS_shs_vec 0
39
+ int reset_dump_flags;
42
#define TCG_TARGET_HAS_shv_vec 1
40
+ int gdb_num_core_regs;
43
-#define TCG_TARGET_HAS_cmp_vec 1
41
+ bool gdb_stop_before_watchpoint;
44
#define TCG_TARGET_HAS_mul_vec 1
42
};
45
#define TCG_TARGET_HAS_sat_vec 1
43
46
#define TCG_TARGET_HAS_minmax_vec 1
44
/*
47
--
45
--
48
2.25.1
46
2.25.1
49
47
50
48
diff view generated by jsdifflib
[PULL 08/11] tcg: Fix generation of dupi_vec for 32-bit host
[PULL 13/28] tcg: Expand usadd/ussub with umin/umax
1
The definition of INDEX_op_dupi_vec is that it operates on
1
For usadd, we only have to consider overflow. Since ~B + B == -1,
2
units of tcg_target_ulong -- in this case 32 bits. It does
2
the maximum value for A that saturates is ~B.
3
not work to use this for a uint64_t value that happens to be
4
small enough to fit in tcg_target_ulong.
5
3
6
Fixes: d2fd745fe8b
4
For ussub, we only have to consider underflow. The minimum value
7
Fixes: db432672dc5
5
that saturates to 0 from A - B is B.
8
Cc: qemu-stable@nongnu.org
6
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
8
---
11
tcg/tcg-op-vec.c | 12 ++++++++----
9
tcg/tcg-op-vec.c | 37 +++++++++++++++++++++++++++++++++++--
12
1 file changed, 8 insertions(+), 4 deletions(-)
10
1 file changed, 35 insertions(+), 2 deletions(-)
13
11
14
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
12
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/tcg-op-vec.c
14
--- a/tcg/tcg-op-vec.c
17
+++ b/tcg/tcg-op-vec.c
15
+++ b/tcg/tcg-op-vec.c
18
@@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
16
@@ -XXX,XX +XXX,XX @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
19
17
continue;
20
void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
18
}
19
break;
20
+ case INDEX_op_usadd_vec:
21
+ if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece) ||
22
+ tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) {
23
+ continue;
24
+ }
25
+ break;
26
+ case INDEX_op_ussub_vec:
27
+ if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece) ||
28
+ tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) {
29
+ continue;
30
+ }
31
+ break;
32
case INDEX_op_cmpsel_vec:
33
case INDEX_op_smin_vec:
34
case INDEX_op_smax_vec:
35
@@ -XXX,XX +XXX,XX @@ void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
36
37
void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
21
{
38
{
22
- if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
39
- do_op3_nofail(vece, r, a, b, INDEX_op_usadd_vec);
23
- do_dupi_vec(r, MO_32, a);
40
+ if (!do_op3(vece, r, a, b, INDEX_op_usadd_vec)) {
24
- } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
41
+ const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
25
+ if (TCG_TARGET_REG_BITS == 64) {
42
+ TCGv_vec t = tcg_temp_new_vec_matching(r);
26
do_dupi_vec(r, MO_64, a);
43
+
27
+ } else if (a == dup_const(MO_32, a)) {
44
+ /* usadd(a, b) = min(a, ~b) + b */
28
+ do_dupi_vec(r, MO_32, a);
45
+ tcg_gen_not_vec(vece, t, b);
29
} else {
46
+ tcg_gen_umin_vec(vece, t, t, a);
30
TCGv_i64 c = tcg_const_i64(a);
47
+ tcg_gen_add_vec(vece, r, t, b);
31
tcg_gen_dup_i64_vec(MO_64, r, c);
48
+
32
@@ -XXX,XX +XXX,XX @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
49
+ tcg_temp_free_vec(t);
33
50
+ tcg_swap_vecop_list(hold_list);
34
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
35
{
36
- do_dupi_vec(r, MO_REG, dup_const(vece, a));
37
+ if (vece == MO_64) {
38
+ tcg_gen_dup64i_vec(r, a);
39
+ } else {
40
+ do_dupi_vec(r, MO_REG, dup_const(vece, a));
41
+ }
51
+ }
42
}
52
}
43
53
44
void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
54
void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
55
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
56
57
void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
58
{
59
- do_op3_nofail(vece, r, a, b, INDEX_op_ussub_vec);
60
+ if (!do_op3(vece, r, a, b, INDEX_op_ussub_vec)) {
61
+ const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
62
+ TCGv_vec t = tcg_temp_new_vec_matching(r);
63
+
64
+ /* ussub(a, b) = max(a, b) - b */
65
+ tcg_gen_umax_vec(vece, t, a, b);
66
+ tcg_gen_sub_vec(vece, r, t, b);
67
+
68
+ tcg_temp_free_vec(t);
69
+ tcg_swap_vecop_list(hold_list);
70
+ }
71
}
72
73
static void do_minmax(unsigned vece, TCGv_vec r, TCGv_vec a,
45
--
74
--
46
2.25.1
75
2.25.1
47
76
48
77
diff view generated by jsdifflib
New patch
[PULL 14/28] tcg/s390x: Rename from tcg/s390
1
This emphasizes that we don't support s390, only 64-bit s390x hosts.
1
2
3
Reviewed-by: Thomas Huth <thuth@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: David Hildenbrand <david@redhat.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
meson.build | 2 --
9
tcg/{s390 => s390x}/tcg-target-con-set.h | 0
10
tcg/{s390 => s390x}/tcg-target-con-str.h | 0
11
tcg/{s390 => s390x}/tcg-target.h | 0
12
tcg/{s390 => s390x}/tcg-target.c.inc | 0
13
5 files changed, 2 deletions(-)
14
rename tcg/{s390 => s390x}/tcg-target-con-set.h (100%)
15
rename tcg/{s390 => s390x}/tcg-target-con-str.h (100%)
16
rename tcg/{s390 => s390x}/tcg-target.h (100%)
17
rename tcg/{s390 => s390x}/tcg-target.c.inc (100%)
18
19
diff --git a/meson.build b/meson.build
20
index XXXXXXX..XXXXXXX 100644
21
--- a/meson.build
22
+++ b/meson.build
23
@@ -XXX,XX +XXX,XX @@ if not get_option('tcg').disabled()
24
tcg_arch = 'tci'
25
elif config_host['ARCH'] == 'sparc64'
26
tcg_arch = 'sparc'
27
- elif config_host['ARCH'] == 's390x'
28
- tcg_arch = 's390'
29
elif config_host['ARCH'] in ['x86_64', 'x32']
30
tcg_arch = 'i386'
31
elif config_host['ARCH'] == 'ppc64'
32
diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
33
similarity index 100%
34
rename from tcg/s390/tcg-target-con-set.h
35
rename to tcg/s390x/tcg-target-con-set.h
36
diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h
37
similarity index 100%
38
rename from tcg/s390/tcg-target-con-str.h
39
rename to tcg/s390x/tcg-target-con-str.h
40
diff --git a/tcg/s390/tcg-target.h b/tcg/s390x/tcg-target.h
41
similarity index 100%
42
rename from tcg/s390/tcg-target.h
43
rename to tcg/s390x/tcg-target.h
44
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
45
similarity index 100%
46
rename from tcg/s390/tcg-target.c.inc
47
rename to tcg/s390x/tcg-target.c.inc
48
--
49
2.25.1
50
51
diff view generated by jsdifflib
[PULL 03/11] tcg: Move sorted_args into TCGArgConstraint.sort_index
[PULL 15/28] tcg/s390x: Change FACILITY representation
1
This uses an existing hole in the TCGArgConstraint structure
1
We will shortly need to be able to check facilities beyond the
2
and will be convenient for keeping the data in one place.
2
first 64. Instead of explicitly masking against s390_facilities,
3
create a HAVE_FACILITY macro that indexes an array.
3
4
5
Reviewed-by: David Hildenbrand <david@redhat.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
7
---
6
include/tcg/tcg.h | 2 +-
8
v2: Change name to HAVE_FACILITY (david)
7
tcg/tcg.c | 35 +++++++++++++++++------------------
9
---
8
2 files changed, 18 insertions(+), 19 deletions(-)
10
tcg/s390x/tcg-target.h | 29 ++++++++-------
11
tcg/s390x/tcg-target.c.inc | 74 +++++++++++++++++++-------------------
12
2 files changed, 52 insertions(+), 51 deletions(-)
9
13
10
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
14
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
11
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
12
--- a/include/tcg/tcg.h
16
--- a/tcg/s390x/tcg-target.h
13
+++ b/include/tcg/tcg.h
17
+++ b/tcg/s390x/tcg-target.h
14
@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
18
@@ -XXX,XX +XXX,XX @@ typedef enum TCGReg {
15
typedef struct TCGArgConstraint {
19
/* A list of relevant facilities used by this translator. Some of these
16
uint16_t ct;
20
are required for proper operation, and these are checked at startup. */
17
uint8_t alias_index;
21
18
+ uint8_t sort_index;
22
-#define FACILITY_ZARCH_ACTIVE (1ULL << (63 - 2))
19
TCGRegSet regs;
23
-#define FACILITY_LONG_DISP (1ULL << (63 - 18))
20
} TCGArgConstraint;
24
-#define FACILITY_EXT_IMM (1ULL << (63 - 21))
21
25
-#define FACILITY_GEN_INST_EXT (1ULL << (63 - 34))
22
@@ -XXX,XX +XXX,XX @@ typedef struct TCGOpDef {
26
-#define FACILITY_LOAD_ON_COND (1ULL << (63 - 45))
23
uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
27
+#define FACILITY_ZARCH_ACTIVE 2
24
uint8_t flags;
28
+#define FACILITY_LONG_DISP 18
25
TCGArgConstraint *args_ct;
29
+#define FACILITY_EXT_IMM 21
26
- int *sorted_args;
30
+#define FACILITY_GEN_INST_EXT 34
27
#if defined(CONFIG_DEBUG_TCG)
31
+#define FACILITY_LOAD_ON_COND 45
28
int used;
32
#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
33
#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
34
-#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53))
35
+#define FACILITY_LOAD_ON_COND2 53
36
37
-extern uint64_t s390_facilities;
38
+extern uint64_t s390_facilities[1];
39
+
40
+#define HAVE_FACILITY(X) \
41
+ ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1)
42
43
/* optional instructions */
44
#define TCG_TARGET_HAS_div2_i32 1
45
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
46
#define TCG_TARGET_HAS_clz_i32 0
47
#define TCG_TARGET_HAS_ctz_i32 0
48
#define TCG_TARGET_HAS_ctpop_i32 0
49
-#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
50
-#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
51
+#define TCG_TARGET_HAS_deposit_i32 HAVE_FACILITY(GEN_INST_EXT)
52
+#define TCG_TARGET_HAS_extract_i32 HAVE_FACILITY(GEN_INST_EXT)
53
#define TCG_TARGET_HAS_sextract_i32 0
54
#define TCG_TARGET_HAS_extract2_i32 0
55
#define TCG_TARGET_HAS_movcond_i32 1
56
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
57
#define TCG_TARGET_HAS_mulsh_i32 0
58
#define TCG_TARGET_HAS_extrl_i64_i32 0
59
#define TCG_TARGET_HAS_extrh_i64_i32 0
60
-#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST_EXT)
61
+#define TCG_TARGET_HAS_direct_jump HAVE_FACILITY(GEN_INST_EXT)
62
#define TCG_TARGET_HAS_qemu_st8_i32 0
63
64
#define TCG_TARGET_HAS_div2_i64 1
65
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
66
#define TCG_TARGET_HAS_eqv_i64 0
67
#define TCG_TARGET_HAS_nand_i64 0
68
#define TCG_TARGET_HAS_nor_i64 0
69
-#define TCG_TARGET_HAS_clz_i64 (s390_facilities & FACILITY_EXT_IMM)
70
+#define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM)
71
#define TCG_TARGET_HAS_ctz_i64 0
72
#define TCG_TARGET_HAS_ctpop_i64 0
73
-#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
74
-#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
75
+#define TCG_TARGET_HAS_deposit_i64 HAVE_FACILITY(GEN_INST_EXT)
76
+#define TCG_TARGET_HAS_extract_i64 HAVE_FACILITY(GEN_INST_EXT)
77
#define TCG_TARGET_HAS_sextract_i64 0
78
#define TCG_TARGET_HAS_extract2_i64 0
79
#define TCG_TARGET_HAS_movcond_i64 1
80
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
81
index XXXXXXX..XXXXXXX 100644
82
--- a/tcg/s390x/tcg-target.c.inc
83
+++ b/tcg/s390x/tcg-target.c.inc
84
@@ -XXX,XX +XXX,XX @@
85
We don't need this when we have pc-relative loads with the general
86
instructions extension facility. */
87
#define TCG_REG_TB TCG_REG_R12
88
-#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT))
89
+#define USE_REG_TB (!HAVE_FACILITY(GEN_INST_EXT))
90
91
#ifndef CONFIG_SOFTMMU
92
#define TCG_GUEST_BASE_REG TCG_REG_R13
93
@@ -XXX,XX +XXX,XX @@ static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
29
#endif
94
#endif
30
diff --git a/tcg/tcg.c b/tcg/tcg.c
95
31
index XXXXXXX..XXXXXXX 100644
96
static const tcg_insn_unit *tb_ret_addr;
32
--- a/tcg/tcg.c
97
-uint64_t s390_facilities;
33
+++ b/tcg/tcg.c
98
+uint64_t s390_facilities[1];
34
@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
99
35
int op, total_args, n, i;
100
static bool patch_reloc(tcg_insn_unit *src_rw, int type,
36
TCGOpDef *def;
101
intptr_t value, intptr_t addend)
37
TCGArgConstraint *args_ct;
102
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
38
- int *sorted_args;
103
}
39
TCGTemp *ts;
104
40
105
/* Try all 48-bit insns that can load it in one go. */
41
memset(s, 0, sizeof(*s));
106
- if (s390_facilities & FACILITY_EXT_IMM) {
42
@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
107
+ if (HAVE_FACILITY(EXT_IMM)) {
43
}
108
if (sval == (int32_t)sval) {
44
109
tcg_out_insn(s, RIL, LGFI, ret, sval);
45
args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
110
return;
46
- sorted_args = g_malloc(sizeof(int) * total_args);
111
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
47
112
}
48
for(op = 0; op < NB_OPS; op++) {
113
49
def = &tcg_op_defs[op];
114
/* Otherwise, stuff it in the constant pool. */
50
def->args_ct = args_ct;
115
- if (s390_facilities & FACILITY_GEN_INST_EXT) {
51
- def->sorted_args = sorted_args;
116
+ if (HAVE_FACILITY(GEN_INST_EXT)) {
52
n = def->nb_iargs + def->nb_oargs;
117
tcg_out_insn(s, RIL, LGRL, ret, 0);
53
- sorted_args += n;
118
new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
54
args_ct += n;
119
} else if (USE_REG_TB && !in_prologue) {
55
}
120
@@ -XXX,XX +XXX,XX @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type,
56
121
{
57
@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
122
intptr_t addr = (intptr_t)abs;
58
/* sort from highest priority to lowest */
123
59
static void sort_constraints(TCGOpDef *def, int start, int n)
124
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) {
60
{
125
+ if (HAVE_FACILITY(GEN_INST_EXT) && !(addr & 1)) {
61
- int i, j, p1, p2, tmp;
126
ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1;
62
+ int i, j;
127
if (disp == (int32_t)disp) {
63
+ TCGArgConstraint *a = def->args_ct;
128
if (type == TCG_TYPE_I32) {
64
129
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
65
- for(i = 0; i < n; i++)
130
66
- def->sorted_args[start + i] = start + i;
131
static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
67
- if (n <= 1)
132
{
68
+ for (i = 0; i < n; i++) {
133
- if (s390_facilities & FACILITY_EXT_IMM) {
69
+ a[start + i].sort_index = start + i;
134
+ if (HAVE_FACILITY(EXT_IMM)) {
70
+ }
135
tcg_out_insn(s, RRE, LGBR, dest, src);
71
+ if (n <= 1) {
136
return;
72
return;
137
}
73
- for(i = 0; i < n - 1; i++) {
138
@@ -XXX,XX +XXX,XX @@ static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
74
- for(j = i + 1; j < n; j++) {
139
75
- p1 = get_constraint_priority(def, def->sorted_args[start + i]);
140
static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
76
- p2 = get_constraint_priority(def, def->sorted_args[start + j]);
141
{
77
+ }
142
- if (s390_facilities & FACILITY_EXT_IMM) {
78
+ for (i = 0; i < n - 1; i++) {
143
+ if (HAVE_FACILITY(EXT_IMM)) {
79
+ for (j = i + 1; j < n; j++) {
144
tcg_out_insn(s, RRE, LLGCR, dest, src);
80
+ int p1 = get_constraint_priority(def, a[start + i].sort_index);
145
return;
81
+ int p2 = get_constraint_priority(def, a[start + j].sort_index);
146
}
82
if (p1 < p2) {
147
@@ -XXX,XX +XXX,XX @@ static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
83
- tmp = def->sorted_args[start + i];
148
84
- def->sorted_args[start + i] = def->sorted_args[start + j];
149
static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
85
- def->sorted_args[start + j] = tmp;
150
{
86
+ int tmp = a[start + i].sort_index;
151
- if (s390_facilities & FACILITY_EXT_IMM) {
87
+ a[start + i].sort_index = a[start + j].sort_index;
152
+ if (HAVE_FACILITY(EXT_IMM)) {
88
+ a[start + j].sort_index = tmp;
153
tcg_out_insn(s, RRE, LGHR, dest, src);
154
return;
155
}
156
@@ -XXX,XX +XXX,XX @@ static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
157
158
static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
159
{
160
- if (s390_facilities & FACILITY_EXT_IMM) {
161
+ if (HAVE_FACILITY(EXT_IMM)) {
162
tcg_out_insn(s, RRE, LLGHR, dest, src);
163
return;
164
}
165
@@ -XXX,XX +XXX,XX @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
166
tgen_ext32u(s, dest, dest);
167
return;
168
}
169
- if (s390_facilities & FACILITY_EXT_IMM) {
170
+ if (HAVE_FACILITY(EXT_IMM)) {
171
if ((val & valid) == 0xff) {
172
tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
173
return;
174
@@ -XXX,XX +XXX,XX @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
175
}
176
177
/* Try all 48-bit insns that can perform it in one go. */
178
- if (s390_facilities & FACILITY_EXT_IMM) {
179
+ if (HAVE_FACILITY(EXT_IMM)) {
180
for (i = 0; i < 2; i++) {
181
tcg_target_ulong mask = ~(0xffffffffull << i*32);
182
if (((val | ~valid) & mask) == mask) {
183
@@ -XXX,XX +XXX,XX @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
89
}
184
}
90
}
185
}
91
}
186
}
92
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
187
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) {
93
for (k = 0; k < nb_iargs; k++) {
188
+ if (HAVE_FACILITY(GEN_INST_EXT) && risbg_mask(val)) {
94
TCGRegSet i_preferred_regs, o_preferred_regs;
189
tgen_andi_risbg(s, dest, dest, val);
95
190
return;
96
- i = def->sorted_args[nb_oargs + k];
191
}
97
+ i = def->args_ct[nb_oargs + k].sort_index;
192
@@ -XXX,XX +XXX,XX @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
98
arg = op->args[i];
193
}
99
arg_ct = &def->args_ct[i];
194
100
ts = arg_temp(arg);
195
/* Try all 48-bit insns that can perform it in one go. */
101
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
196
- if (s390_facilities & FACILITY_EXT_IMM) {
102
int k2, i2;
197
+ if (HAVE_FACILITY(EXT_IMM)) {
103
reg = ts->reg;
198
for (i = 0; i < 2; i++) {
104
for (k2 = 0 ; k2 < k ; k2++) {
199
tcg_target_ulong mask = (0xffffffffull << i*32);
105
- i2 = def->sorted_args[nb_oargs + k2];
200
if ((val & mask) != 0 && (val & ~mask) == 0) {
106
+ i2 = def->args_ct[nb_oargs + k2].sort_index;
201
@@ -XXX,XX +XXX,XX @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
107
if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
202
/* Perform the OR via sequential modifications to the high and
108
reg == new_args[i2]) {
203
low parts. Do this via recursion to handle 16-bit vs 32-bit
109
goto allocate_in_reg;
204
masks in each half. */
110
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
205
- tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
111
206
+ tcg_debug_assert(HAVE_FACILITY(EXT_IMM));
112
/* satisfy the output constraints */
207
tgen_ori(s, type, dest, val & 0x00000000ffffffffull);
113
for(k = 0; k < nb_oargs; k++) {
208
tgen_ori(s, type, dest, val & 0xffffffff00000000ull);
114
- i = def->sorted_args[k];
209
}
115
+ i = def->args_ct[k].sort_index;
210
@@ -XXX,XX +XXX,XX @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
116
arg = op->args[i];
211
static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
117
arg_ct = &def->args_ct[i];
212
{
118
ts = arg_temp(arg);
213
/* Try all 48-bit insns that can perform it in one go. */
214
- if (s390_facilities & FACILITY_EXT_IMM) {
215
+ if (HAVE_FACILITY(EXT_IMM)) {
216
if ((val & 0xffffffff00000000ull) == 0) {
217
tcg_out_insn(s, RIL, XILF, dest, val);
218
return;
219
@@ -XXX,XX +XXX,XX @@ static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
220
tcg_tbrel_diff(s, NULL));
221
} else {
222
/* Perform the xor by parts. */
223
- tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
224
+ tcg_debug_assert(HAVE_FACILITY(EXT_IMM));
225
if (val & 0xffffffff) {
226
tcg_out_insn(s, RIL, XILF, dest, val);
227
}
228
@@ -XXX,XX +XXX,XX @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
229
goto exit;
230
}
231
232
- if (s390_facilities & FACILITY_EXT_IMM) {
233
+ if (HAVE_FACILITY(EXT_IMM)) {
234
if (type == TCG_TYPE_I32) {
235
op = (is_unsigned ? RIL_CLFI : RIL_CFI);
236
tcg_out_insn_RIL(s, op, r1, c2);
237
@@ -XXX,XX +XXX,XX @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
238
bool have_loc;
239
240
/* With LOC2, we can always emit the minimum 3 insns. */
241
- if (s390_facilities & FACILITY_LOAD_ON_COND2) {
242
+ if (HAVE_FACILITY(LOAD_ON_COND2)) {
243
/* Emit: d = 0, d = (cc ? 1 : d). */
244
cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
245
tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
246
@@ -XXX,XX +XXX,XX @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
247
return;
248
}
249
250
- have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0;
251
+ have_loc = HAVE_FACILITY(LOAD_ON_COND);
252
253
/* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */
254
restart:
255
@@ -XXX,XX +XXX,XX @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
256
TCGArg v3, int v3const)
257
{
258
int cc;
259
- if (s390_facilities & FACILITY_LOAD_ON_COND) {
260
+ if (HAVE_FACILITY(LOAD_ON_COND)) {
261
cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
262
if (v3const) {
263
tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
264
@@ -XXX,XX +XXX,XX @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
265
} else {
266
tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
267
}
268
- if (s390_facilities & FACILITY_LOAD_ON_COND) {
269
+ if (HAVE_FACILITY(LOAD_ON_COND)) {
270
/* Emit: if (one bit found) dest = r0. */
271
tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
272
} else {
273
@@ -XXX,XX +XXX,XX @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
274
{
275
int cc;
276
277
- if (s390_facilities & FACILITY_GEN_INST_EXT) {
278
+ if (HAVE_FACILITY(GEN_INST_EXT)) {
279
bool is_unsigned = is_unsigned_cond(c);
280
bool in_range;
281
S390Opcode opc;
282
@@ -XXX,XX +XXX,XX @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
283
cross pages using the address of the last byte of the access. */
284
a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask);
285
tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
286
- if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off == 0) {
287
+ if (HAVE_FACILITY(GEN_INST_EXT) && a_off == 0) {
288
tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
289
} else {
290
tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
291
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
292
tcg_out_insn(s, RI, AHI, a0, a2);
293
break;
294
}
295
- if (s390_facilities & FACILITY_EXT_IMM) {
296
+ if (HAVE_FACILITY(EXT_IMM)) {
297
tcg_out_insn(s, RIL, AFI, a0, a2);
298
break;
299
}
300
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
301
tcg_out_insn(s, RI, AGHI, a0, a2);
302
break;
303
}
304
- if (s390_facilities & FACILITY_EXT_IMM) {
305
+ if (HAVE_FACILITY(EXT_IMM)) {
306
if (a2 == (int32_t)a2) {
307
tcg_out_insn(s, RIL, AGFI, a0, a2);
308
break;
309
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
310
/* The host memory model is quite strong, we simply need to
311
serialize the instruction stream. */
312
if (args[0] & TCG_MO_ST_LD) {
313
- tcg_out_insn(s, RR, BCR,
314
- s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
315
+ tcg_out_insn(s, RR, BCR, HAVE_FACILITY(FAST_BCR_SER) ? 14 : 15, 0);
316
}
317
break;
318
319
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
320
case INDEX_op_or_i64:
321
case INDEX_op_xor_i32:
322
case INDEX_op_xor_i64:
323
- return (s390_facilities & FACILITY_DISTINCT_OPS
324
+ return (HAVE_FACILITY(DISTINCT_OPS)
325
? C_O1_I2(r, r, ri)
326
: C_O1_I2(r, 0, ri));
327
328
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
329
/* If we have the general-instruction-extensions, then we have
330
MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
331
have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
332
- return (s390_facilities & FACILITY_GEN_INST_EXT
333
+ return (HAVE_FACILITY(GEN_INST_EXT)
334
? C_O1_I2(r, 0, ri)
335
: C_O1_I2(r, 0, rI));
336
337
case INDEX_op_mul_i64:
338
- return (s390_facilities & FACILITY_GEN_INST_EXT
339
+ return (HAVE_FACILITY(GEN_INST_EXT)
340
? C_O1_I2(r, 0, rJ)
341
: C_O1_I2(r, 0, rI));
342
343
case INDEX_op_shl_i32:
344
case INDEX_op_shr_i32:
345
case INDEX_op_sar_i32:
346
- return (s390_facilities & FACILITY_DISTINCT_OPS
347
+ return (HAVE_FACILITY(DISTINCT_OPS)
348
? C_O1_I2(r, r, ri)
349
: C_O1_I2(r, 0, ri));
350
351
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
352
353
case INDEX_op_movcond_i32:
354
case INDEX_op_movcond_i64:
355
- return (s390_facilities & FACILITY_LOAD_ON_COND2
356
+ return (HAVE_FACILITY(LOAD_ON_COND2)
357
? C_O1_I4(r, r, ri, rI, 0)
358
: C_O1_I4(r, r, ri, r, 0));
359
360
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
361
362
case INDEX_op_add2_i32:
363
case INDEX_op_sub2_i32:
364
- return (s390_facilities & FACILITY_EXT_IMM
365
+ return (HAVE_FACILITY(EXT_IMM)
366
? C_O2_I4(r, r, 0, 1, ri, r)
367
: C_O2_I4(r, r, 0, 1, r, r));
368
369
case INDEX_op_add2_i64:
370
case INDEX_op_sub2_i64:
371
- return (s390_facilities & FACILITY_EXT_IMM
372
+ return (HAVE_FACILITY(EXT_IMM)
373
? C_O2_I4(r, r, 0, 1, rA, r)
374
: C_O2_I4(r, r, 0, 1, r, r));
375
376
@@ -XXX,XX +XXX,XX @@ static void query_s390_facilities(void)
377
/* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
378
is present on all 64-bit systems, but let's check for it anyway. */
379
if (hwcap & HWCAP_S390_STFLE) {
380
- register int r0 __asm__("0");
381
- register void *r1 __asm__("1");
382
+ register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1;
383
+ register void *r1 __asm__("1") = s390_facilities;
384
385
/* stfle 0(%r1) */
386
- r1 = &s390_facilities;
387
asm volatile(".word 0xb2b0,0x1000"
388
- : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");
389
+ : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc");
390
}
391
}
392
119
--
393
--
120
2.25.1
394
2.25.1
121
395
122
396
diff view generated by jsdifflib
New patch
[PULL 16/28] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg
1
They are rightly values in the same enumeration.
1
2
3
Reviewed-by: David Hildenbrand <david@redhat.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/s390x/tcg-target.h | 28 +++++++---------------------
7
1 file changed, 7 insertions(+), 21 deletions(-)
8
9
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/s390x/tcg-target.h
12
+++ b/tcg/s390x/tcg-target.h
13
@@ -XXX,XX +XXX,XX @@
14
#define MAX_CODE_GEN_BUFFER_SIZE (3 * GiB)
15
16
typedef enum TCGReg {
17
- TCG_REG_R0 = 0,
18
- TCG_REG_R1,
19
- TCG_REG_R2,
20
- TCG_REG_R3,
21
- TCG_REG_R4,
22
- TCG_REG_R5,
23
- TCG_REG_R6,
24
- TCG_REG_R7,
25
- TCG_REG_R8,
26
- TCG_REG_R9,
27
- TCG_REG_R10,
28
- TCG_REG_R11,
29
- TCG_REG_R12,
30
- TCG_REG_R13,
31
- TCG_REG_R14,
32
- TCG_REG_R15
33
+ TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,
34
+ TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7,
35
+ TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11,
36
+ TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15,
37
+
38
+ TCG_AREG0 = TCG_REG_R10,
39
+ TCG_REG_CALL_STACK = TCG_REG_R15
40
} TCGReg;
41
42
#define TCG_TARGET_NB_REGS 16
43
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[1];
44
#define TCG_TARGET_HAS_mulsh_i64 0
45
46
/* used for function call generation */
47
-#define TCG_REG_CALL_STACK        TCG_REG_R15
48
#define TCG_TARGET_STACK_ALIGN        8
49
#define TCG_TARGET_CALL_STACK_OFFSET    160
50
51
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[1];
52
53
#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
54
55
-enum {
56
- TCG_AREG0 = TCG_REG_R10,
57
-};
58
-
59
static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
60
uintptr_t jmp_rw, uintptr_t addr)
61
{
62
--
63
2.25.1
64
65
diff view generated by jsdifflib
New patch
[PULL 17/28] tcg/s390x: Add host vector framework
1
1
Add registers and function stubs. The functionality
2
is disabled via squashing s390_facilities[2] to 0.
3
4
We must still include results for the mandatory opcodes in
5
tcg_target_op_def, as all opcodes are checked during tcg init.
6
7
Reviewed-by: David Hildenbrand <david@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
tcg/s390x/tcg-target-con-set.h | 4 +
11
tcg/s390x/tcg-target-con-str.h | 1 +
12
tcg/s390x/tcg-target.h | 35 ++++++++-
13
tcg/s390x/tcg-target.opc.h | 12 +++
14
tcg/s390x/tcg-target.c.inc | 137 ++++++++++++++++++++++++++++++++-
15
5 files changed, 184 insertions(+), 5 deletions(-)
16
create mode 100644 tcg/s390x/tcg-target.opc.h
17
18
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/tcg/s390x/tcg-target-con-set.h
21
+++ b/tcg/s390x/tcg-target-con-set.h
22
@@ -XXX,XX +XXX,XX @@ C_O0_I1(r)
23
C_O0_I2(L, L)
24
C_O0_I2(r, r)
25
C_O0_I2(r, ri)
26
+C_O0_I2(v, r)
27
C_O1_I1(r, L)
28
C_O1_I1(r, r)
29
+C_O1_I1(v, r)
30
+C_O1_I1(v, vr)
31
C_O1_I2(r, 0, ri)
32
C_O1_I2(r, 0, rI)
33
C_O1_I2(r, 0, rJ)
34
C_O1_I2(r, r, ri)
35
C_O1_I2(r, rZ, r)
36
+C_O1_I2(v, v, v)
37
C_O1_I4(r, r, ri, r, 0)
38
C_O1_I4(r, r, ri, rI, 0)
39
C_O2_I2(b, a, 0, r)
40
diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/tcg/s390x/tcg-target-con-str.h
43
+++ b/tcg/s390x/tcg-target-con-str.h
44
@@ -XXX,XX +XXX,XX @@
45
*/
46
REGS('r', ALL_GENERAL_REGS)
47
REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS)
48
+REGS('v', ALL_VECTOR_REGS)
49
/*
50
* A (single) even/odd pair for division.
51
* TODO: Add something to the register allocator to allow
52
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
53
index XXXXXXX..XXXXXXX 100644
54
--- a/tcg/s390x/tcg-target.h
55
+++ b/tcg/s390x/tcg-target.h
56
@@ -XXX,XX +XXX,XX @@ typedef enum TCGReg {
57
TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11,
58
TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15,
59
60
+ TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
61
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
62
+ TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
63
+ TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
64
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
65
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
66
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
67
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
68
+
69
TCG_AREG0 = TCG_REG_R10,
70
TCG_REG_CALL_STACK = TCG_REG_R15
71
} TCGReg;
72
73
-#define TCG_TARGET_NB_REGS 16
74
+#define TCG_TARGET_NB_REGS 64
75
76
/* A list of relevant facilities used by this translator. Some of these
77
are required for proper operation, and these are checked at startup. */
78
@@ -XXX,XX +XXX,XX @@ typedef enum TCGReg {
79
#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
80
#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
81
#define FACILITY_LOAD_ON_COND2 53
82
+#define FACILITY_VECTOR 129
83
84
-extern uint64_t s390_facilities[1];
85
+extern uint64_t s390_facilities[3];
86
87
#define HAVE_FACILITY(X) \
88
((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1)
89
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[1];
90
#define TCG_TARGET_HAS_muluh_i64 0
91
#define TCG_TARGET_HAS_mulsh_i64 0
92
93
+#define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR)
94
+#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR)
95
+#define TCG_TARGET_HAS_v256 0
96
+
97
+#define TCG_TARGET_HAS_andc_vec 0
98
+#define TCG_TARGET_HAS_orc_vec 0
99
+#define TCG_TARGET_HAS_not_vec 0
100
+#define TCG_TARGET_HAS_neg_vec 0
101
+#define TCG_TARGET_HAS_abs_vec 0
102
+#define TCG_TARGET_HAS_roti_vec 0
103
+#define TCG_TARGET_HAS_rots_vec 0
104
+#define TCG_TARGET_HAS_rotv_vec 0
105
+#define TCG_TARGET_HAS_shi_vec 0
106
+#define TCG_TARGET_HAS_shs_vec 0
107
+#define TCG_TARGET_HAS_shv_vec 0
108
+#define TCG_TARGET_HAS_mul_vec 0
109
+#define TCG_TARGET_HAS_sat_vec 0
110
+#define TCG_TARGET_HAS_minmax_vec 0
111
+#define TCG_TARGET_HAS_bitsel_vec 0
112
+#define TCG_TARGET_HAS_cmpsel_vec 0
113
+
114
/* used for function call generation */
115
#define TCG_TARGET_STACK_ALIGN        8
116
#define TCG_TARGET_CALL_STACK_OFFSET    160
117
diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target.opc.h
118
new file mode 100644
119
index XXXXXXX..XXXXXXX
120
--- /dev/null
121
+++ b/tcg/s390x/tcg-target.opc.h
122
@@ -XXX,XX +XXX,XX @@
123
+/*
124
+ * Copyright (c) 2021 Linaro
125
+ *
126
+ * This work is licensed under the terms of the GNU GPL, version 2 or
127
+ * (at your option) any later version.
128
+ *
129
+ * See the COPYING file in the top-level directory for details.
130
+ *
131
+ * Target-specific opcodes for host vector expansion. These will be
132
+ * emitted by tcg_expand_vec_op. For those familiar with GCC internals,
133
+ * consider these to be UNSPEC with names.
134
+ */
135
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
136
index XXXXXXX..XXXXXXX 100644
137
--- a/tcg/s390x/tcg-target.c.inc
138
+++ b/tcg/s390x/tcg-target.c.inc
139
@@ -XXX,XX +XXX,XX @@
140
#define TCG_CT_CONST_ZERO 0x800
141
142
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
143
+#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
144
+
145
/*
146
* For softmmu, we need to avoid conflicts with the first 3
147
* argument registers to perform the tlb lookup, and to call
148
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
149
150
#ifdef CONFIG_DEBUG_TCG
151
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
152
- "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
153
- "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15"
154
+ "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
155
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
156
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
157
+ "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
158
+ "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
159
+ "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
160
+ "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
161
};
162
#endif
163
164
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
165
TCG_REG_R4,
166
TCG_REG_R3,
167
TCG_REG_R2,
168
+
169
+ /* V8-V15 are call saved, and omitted. */
170
+ TCG_REG_V0,
171
+ TCG_REG_V1,
172
+ TCG_REG_V2,
173
+ TCG_REG_V3,
174
+ TCG_REG_V4,
175
+ TCG_REG_V5,
176
+ TCG_REG_V6,
177
+ TCG_REG_V7,
178
+ TCG_REG_V16,
179
+ TCG_REG_V17,
180
+ TCG_REG_V18,
181
+ TCG_REG_V19,
182
+ TCG_REG_V20,
183
+ TCG_REG_V21,
184
+ TCG_REG_V22,
185
+ TCG_REG_V23,
186
+ TCG_REG_V24,
187
+ TCG_REG_V25,
188
+ TCG_REG_V26,
189
+ TCG_REG_V27,
190
+ TCG_REG_V28,
191
+ TCG_REG_V29,
192
+ TCG_REG_V30,
193
+ TCG_REG_V31,
194
};
195
196
static const int tcg_target_call_iarg_regs[] = {
197
@@ -XXX,XX +XXX,XX @@ static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
198
#endif
199
200
static const tcg_insn_unit *tb_ret_addr;
201
-uint64_t s390_facilities[1];
202
+uint64_t s390_facilities[3];
203
204
static bool patch_reloc(tcg_insn_unit *src_rw, int type,
205
intptr_t value, intptr_t addend)
206
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
207
}
208
}
209
210
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
211
+ TCGReg dst, TCGReg src)
212
+{
213
+ g_assert_not_reached();
214
+}
215
+
216
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
217
+ TCGReg dst, TCGReg base, intptr_t offset)
218
+{
219
+ g_assert_not_reached();
220
+}
221
+
222
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
223
+ TCGReg dst, int64_t val)
224
+{
225
+ g_assert_not_reached();
226
+}
227
+
228
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
229
+ unsigned vecl, unsigned vece,
230
+ const TCGArg *args, const int *const_args)
231
+{
232
+ g_assert_not_reached();
233
+}
234
+
235
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
236
+{
237
+ return 0;
238
+}
239
+
240
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
241
+ TCGArg a0, ...)
242
+{
243
+ g_assert_not_reached();
244
+}
245
+
246
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
247
{
248
switch (op) {
249
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
250
? C_O2_I4(r, r, 0, 1, rA, r)
251
: C_O2_I4(r, r, 0, 1, r, r));
252
253
+ case INDEX_op_st_vec:
254
+ return C_O0_I2(v, r);
255
+ case INDEX_op_ld_vec:
256
+ case INDEX_op_dupm_vec:
257
+ return C_O1_I1(v, r);
258
+ case INDEX_op_dup_vec:
259
+ return C_O1_I1(v, vr);
260
+ case INDEX_op_add_vec:
261
+ case INDEX_op_sub_vec:
262
+ case INDEX_op_and_vec:
263
+ case INDEX_op_or_vec:
264
+ case INDEX_op_xor_vec:
265
+ case INDEX_op_cmp_vec:
266
+ return C_O1_I2(v, v, v);
267
+
268
default:
269
g_assert_not_reached();
270
}
271
}
272
273
+/*
274
+ * Mainline glibc added HWCAP_S390_VX before it was kernel abi.
275
+ * Some distros have fixed this up locally, others have not.
276
+ */
277
+#ifndef HWCAP_S390_VXRS
278
+#define HWCAP_S390_VXRS 2048
279
+#endif
280
+
281
static void query_s390_facilities(void)
282
{
283
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
284
@@ -XXX,XX +XXX,XX @@ static void query_s390_facilities(void)
285
asm volatile(".word 0xb2b0,0x1000"
286
: "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc");
287
}
288
+
289
+ /*
290
+ * Use of vector registers requires os support beyond the facility bit.
291
+ * If the kernel does not advertise support, disable the facility bits.
292
+ * There is nothing else we currently care about in the 3rd word, so
293
+ * disable VECTOR with one store.
294
+ */
295
+ if (1 || !(hwcap & HWCAP_S390_VXRS)) {
296
+ s390_facilities[2] = 0;
297
+ }
298
}
299
300
static void tcg_target_init(TCGContext *s)
301
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
302
303
tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
304
tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
305
+ if (HAVE_FACILITY(VECTOR)) {
306
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
307
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
308
+ }
309
310
tcg_target_call_clobber_regs = 0;
311
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
312
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
313
/* The return register can be considered call-clobbered. */
314
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
315
316
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
317
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
318
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
319
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
320
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
321
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
322
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
323
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
324
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
325
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
326
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
327
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
328
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20);
329
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21);
330
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22);
331
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23);
332
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
333
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
334
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26);
335
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27);
336
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28);
337
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29);
338
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30);
339
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31);
340
+
341
s->reserved_regs = 0;
342
tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
343
/* XXX many insns can't be used with R0, so we better avoid it for now */
344
--
345
2.25.1
346
347
diff view generated by jsdifflib
New patch
[PULL 18/28] tcg/s390x: Implement tcg_out_ld/st for vector types
1
Reviewed-by: David Hildenbrand <david@redhat.com>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/s390x/tcg-target.c.inc | 132 +++++++++++++++++++++++++++++++++----
5
1 file changed, 120 insertions(+), 12 deletions(-)
1
6
7
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/s390x/tcg-target.c.inc
10
+++ b/tcg/s390x/tcg-target.c.inc
11
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
12
RX_STC = 0x42,
13
RX_STH = 0x40,
14
15
+ VRX_VL = 0xe706,
16
+ VRX_VLLEZ = 0xe704,
17
+ VRX_VST = 0xe70e,
18
+ VRX_VSTEF = 0xe70b,
19
+ VRX_VSTEG = 0xe70a,
20
+
21
NOP = 0x0707,
22
} S390Opcode;
23
24
@@ -XXX,XX +XXX,XX @@ static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
25
static const tcg_insn_unit *tb_ret_addr;
26
uint64_t s390_facilities[3];
27
28
+static inline bool is_general_reg(TCGReg r)
29
+{
30
+ return r <= TCG_REG_R15;
31
+}
32
+
33
+static inline bool is_vector_reg(TCGReg r)
34
+{
35
+ return r >= TCG_REG_V0 && r <= TCG_REG_V31;
36
+}
37
+
38
static bool patch_reloc(tcg_insn_unit *src_rw, int type,
39
intptr_t value, intptr_t addend)
40
{
41
@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
42
#define tcg_out_insn_RX tcg_out_insn_RS
43
#define tcg_out_insn_RXY tcg_out_insn_RSY
44
45
+static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
46
+{
47
+ /*
48
+ * Shift bit 4 of each regno to its corresponding bit of RXB.
49
+ * RXB itself begins at bit 8 of the instruction so 8 - 4 = 4
50
+ * is the left-shift of the 4th operand.
51
+ */
52
+ return ((v1 & 0x10) << (4 + 3))
53
+ | ((v2 & 0x10) << (4 + 2))
54
+ | ((v3 & 0x10) << (4 + 1))
55
+ | ((v4 & 0x10) << (4 + 0));
56
+}
57
+
58
+static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,
59
+ TCGReg b2, TCGReg x2, intptr_t d2, int m3)
60
+{
61
+ tcg_debug_assert(is_vector_reg(v1));
62
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
63
+ tcg_debug_assert(is_general_reg(x2));
64
+ tcg_debug_assert(is_general_reg(b2));
65
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | x2);
66
+ tcg_out16(s, (b2 << 12) | d2);
67
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12));
68
+}
69
+
70
/* Emit an opcode with "type-checking" of the format. */
71
#define tcg_out_insn(S, FMT, OP, ...) \
72
glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
73
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
74
}
75
}
76
77
+static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx,
78
+ TCGReg data, TCGReg base, TCGReg index,
79
+ tcg_target_long ofs, int m3)
80
+{
81
+ if (ofs < 0 || ofs >= 0x1000) {
82
+ if (ofs >= -0x80000 && ofs < 0x80000) {
83
+ tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs);
84
+ base = TCG_TMP0;
85
+ index = TCG_REG_NONE;
86
+ ofs = 0;
87
+ } else {
88
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs);
89
+ if (index != TCG_REG_NONE) {
90
+ tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
91
+ }
92
+ index = TCG_TMP0;
93
+ ofs = 0;
94
+ }
95
+ }
96
+ tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3);
97
+}
98
99
/* load data without address translation or endianness conversion */
100
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
101
- TCGReg base, intptr_t ofs)
102
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
103
+ TCGReg base, intptr_t ofs)
104
{
105
- if (type == TCG_TYPE_I32) {
106
- tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
107
- } else {
108
- tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
109
+ switch (type) {
110
+ case TCG_TYPE_I32:
111
+ if (likely(is_general_reg(data))) {
112
+ tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
113
+ break;
114
+ }
115
+ tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32);
116
+ break;
117
+
118
+ case TCG_TYPE_I64:
119
+ if (likely(is_general_reg(data))) {
120
+ tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
121
+ break;
122
+ }
123
+ /* fallthru */
124
+
125
+ case TCG_TYPE_V64:
126
+ tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64);
127
+ break;
128
+
129
+ case TCG_TYPE_V128:
130
+ /* Hint quadword aligned. */
131
+ tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4);
132
+ break;
133
+
134
+ default:
135
+ g_assert_not_reached();
136
}
137
}
138
139
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
140
- TCGReg base, intptr_t ofs)
141
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
142
+ TCGReg base, intptr_t ofs)
143
{
144
- if (type == TCG_TYPE_I32) {
145
- tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
146
- } else {
147
- tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
148
+ switch (type) {
149
+ case TCG_TYPE_I32:
150
+ if (likely(is_general_reg(data))) {
151
+ tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
152
+ } else {
153
+ tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1);
154
+ }
155
+ break;
156
+
157
+ case TCG_TYPE_I64:
158
+ if (likely(is_general_reg(data))) {
159
+ tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
160
+ break;
161
+ }
162
+ /* fallthru */
163
+
164
+ case TCG_TYPE_V64:
165
+ tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0);
166
+ break;
167
+
168
+ case TCG_TYPE_V128:
169
+ /* Hint quadword aligned. */
170
+ tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4);
171
+ break;
172
+
173
+ default:
174
+ g_assert_not_reached();
175
}
176
}
177
178
--
179
2.25.1
180
181
diff view generated by jsdifflib
New patch
[PULL 19/28] tcg/s390x: Implement tcg_out_mov for vector types
1
Reviewed-by: David Hildenbrand <david@redhat.com>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/s390x/tcg-target.c.inc | 72 +++++++++++++++++++++++++++++++++++---
5
1 file changed, 68 insertions(+), 4 deletions(-)
1
6
7
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
8
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/s390x/tcg-target.c.inc
10
+++ b/tcg/s390x/tcg-target.c.inc
11
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
12
RX_STC = 0x42,
13
RX_STH = 0x40,
14
15
+ VRRa_VLR = 0xe756,
16
+
17
+ VRSb_VLVG = 0xe722,
18
+ VRSc_VLGV = 0xe721,
19
+
20
VRX_VL = 0xe706,
21
VRX_VLLEZ = 0xe704,
22
VRX_VST = 0xe70e,
23
@@ -XXX,XX +XXX,XX @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
24
| ((v4 & 0x10) << (4 + 0));
25
}
26
27
+static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
28
+ TCGReg v1, TCGReg v2, int m3)
29
+{
30
+ tcg_debug_assert(is_vector_reg(v1));
31
+ tcg_debug_assert(is_vector_reg(v2));
32
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
33
+ tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
34
+}
35
+
36
+static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
37
+ intptr_t d2, TCGReg b2, TCGReg r3, int m4)
38
+{
39
+ tcg_debug_assert(is_vector_reg(v1));
40
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
41
+ tcg_debug_assert(is_general_reg(b2));
42
+ tcg_debug_assert(is_general_reg(r3));
43
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r3);
44
+ tcg_out16(s, b2 << 12 | d2);
45
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
46
+}
47
+
48
+static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1,
49
+ intptr_t d2, TCGReg b2, TCGReg v3, int m4)
50
+{
51
+ tcg_debug_assert(is_general_reg(r1));
52
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
53
+ tcg_debug_assert(is_general_reg(b2));
54
+ tcg_debug_assert(is_vector_reg(v3));
55
+ tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 0xf));
56
+ tcg_out16(s, b2 << 12 | d2);
57
+ tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12));
58
+}
59
+
60
static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1,
61
TCGReg b2, TCGReg x2, intptr_t d2, int m3)
62
{
63
@@ -XXX,XX +XXX,XX @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
64
65
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
66
{
67
- if (src != dst) {
68
- if (type == TCG_TYPE_I32) {
69
+ if (src == dst) {
70
+ return true;
71
+ }
72
+ switch (type) {
73
+ case TCG_TYPE_I32:
74
+ if (likely(is_general_reg(dst) && is_general_reg(src))) {
75
tcg_out_insn(s, RR, LR, dst, src);
76
- } else {
77
- tcg_out_insn(s, RRE, LGR, dst, src);
78
+ break;
79
}
80
+ /* fallthru */
81
+
82
+ case TCG_TYPE_I64:
83
+ if (likely(is_general_reg(dst))) {
84
+ if (likely(is_general_reg(src))) {
85
+ tcg_out_insn(s, RRE, LGR, dst, src);
86
+ } else {
87
+ tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3);
88
+ }
89
+ break;
90
+ } else if (is_general_reg(src)) {
91
+ tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3);
92
+ break;
93
+ }
94
+ /* fallthru */
95
+
96
+ case TCG_TYPE_V64:
97
+ case TCG_TYPE_V128:
98
+ tcg_out_insn(s, VRRa, VLR, dst, src, 0);
99
+ break;
100
+
101
+ default:
102
+ g_assert_not_reached();
103
}
104
return true;
105
}
106
--
107
2.25.1
108
109
diff view generated by jsdifflib
[PULL 01/11] tcg: Adjust simd_desc size encoding
[PULL 20/28] tcg/s390x: Implement tcg_out_dup*_vec
1
With larger vector sizes, it turns out oprsz == maxsz, and we only
2
need to represent mismatch for oprsz <= 32. We do, however, need
3
to represent larger oprsz and do so without reducing SIMD_DATA_BITS.
4
5
Reduce the size of the oprsz field and increase the maxsz field.
6
Steal the oprsz value of 24 to indicate equality with maxsz.
7
8
Tested-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Frank Chang <frank.chang@sifive.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
2
---
13
include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++-------------
3
tcg/s390x/tcg-target.c.inc | 122 ++++++++++++++++++++++++++++++++++++-
14
tcg/tcg-op-gvec.c | 35 ++++++++++++++++++++++++++--------
4
1 file changed, 119 insertions(+), 3 deletions(-)
15
2 files changed, 52 insertions(+), 21 deletions(-)
16
5
17
diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h
6
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
18
index XXXXXXX..XXXXXXX 100644
7
index XXXXXXX..XXXXXXX 100644
19
--- a/include/tcg/tcg-gvec-desc.h
8
--- a/tcg/s390x/tcg-target.c.inc
20
+++ b/include/tcg/tcg-gvec-desc.h
9
+++ b/tcg/s390x/tcg-target.c.inc
21
@@ -XXX,XX +XXX,XX @@
10
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
22
#ifndef TCG_TCG_GVEC_DESC_H
11
RX_STC = 0x42,
23
#define TCG_TCG_GVEC_DESC_H
12
RX_STH = 0x40,
24
13
25
-/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
14
+ VRIa_VGBM = 0xe744,
26
-#define SIMD_OPRSZ_SHIFT 0
15
+ VRIa_VREPI = 0xe745,
27
-#define SIMD_OPRSZ_BITS 5
16
+ VRIb_VGM = 0xe746,
28
+/*
17
+ VRIc_VREP = 0xe74d,
29
+ * This configuration allows MAXSZ to represent 2048 bytes, and
18
+
30
+ * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
19
VRRa_VLR = 0xe756,
31
+ *
20
+ VRRf_VLVGP = 0xe762,
32
+ * Encode this with:
21
33
+ * 0, 1, 3 -> 8, 16, 32
22
VRSb_VLVG = 0xe722,
34
+ * 2 -> maxsz
23
VRSc_VLGV = 0xe721,
35
+ *
24
36
+ * This steals the input that would otherwise map to 24 to match maxsz.
25
VRX_VL = 0xe706,
37
+ */
26
VRX_VLLEZ = 0xe704,
38
+#define SIMD_MAXSZ_SHIFT 0
27
+ VRX_VLREP = 0xe705,
39
+#define SIMD_MAXSZ_BITS 8
28
VRX_VST = 0xe70e,
40
29
VRX_VSTEF = 0xe70b,
41
-#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
30
VRX_VSTEG = 0xe70a,
42
-#define SIMD_MAXSZ_BITS 5
31
@@ -XXX,XX +XXX,XX @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
43
+#define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
32
| ((v4 & 0x10) << (4 + 0));
44
+#define SIMD_OPRSZ_BITS 2
33
}
45
34
46
-#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
35
+static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op,
47
+#define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
36
+ TCGReg v1, uint16_t i2, int m3)
48
#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
37
+{
49
38
+ tcg_debug_assert(is_vector_reg(v1));
50
/* Create a descriptor from components. */
39
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4));
51
uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
40
+ tcg_out16(s, i2);
52
41
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12));
53
-/* Extract the operation size from a descriptor. */
54
-static inline intptr_t simd_oprsz(uint32_t desc)
55
-{
56
- return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
57
-}
58
-
59
/* Extract the max vector size from a descriptor. */
60
static inline intptr_t simd_maxsz(uint32_t desc)
61
{
62
- return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
63
+ return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
64
+}
42
+}
65
+
43
+
66
+/* Extract the operation size from a descriptor. */
44
+static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op,
67
+static inline intptr_t simd_oprsz(uint32_t desc)
45
+ TCGReg v1, uint8_t i2, uint8_t i3, int m4)
68
+{
46
+{
69
+ uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
47
+ tcg_debug_assert(is_vector_reg(v1));
70
+ intptr_t o = f * 8 + 8;
48
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4));
71
+ intptr_t m = simd_maxsz(desc);
49
+ tcg_out16(s, (i2 << 8) | (i3 & 0xff));
72
+ return f == 2 ? m : o;
50
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12));
51
+}
52
+
53
+static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op,
54
+ TCGReg v1, uint16_t i2, TCGReg v3, int m4)
55
+{
56
+ tcg_debug_assert(is_vector_reg(v1));
57
+ tcg_debug_assert(is_vector_reg(v3));
58
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
59
+ tcg_out16(s, i2);
60
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
61
+}
62
+
63
static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
64
TCGReg v1, TCGReg v2, int m3)
65
{
66
@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
67
tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
73
}
68
}
74
69
75
/* Extract the operation-specific data from a descriptor. */
70
+static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
76
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
71
+ TCGReg v1, TCGReg r2, TCGReg r3)
77
index XXXXXXX..XXXXXXX 100644
72
+{
78
--- a/tcg/tcg-op-gvec.c
73
+ tcg_debug_assert(is_vector_reg(v1));
79
+++ b/tcg/tcg-op-gvec.c
74
+ tcg_debug_assert(is_general_reg(r2));
80
@@ -XXX,XX +XXX,XX @@ static const TCGOpcode vecop_list_empty[1] = { 0 };
75
+ tcg_debug_assert(is_general_reg(r3));
81
of the operand offsets so that we can check them all at once. */
76
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2);
82
static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
77
+ tcg_out16(s, r3 << 12);
78
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0));
79
+}
80
+
81
static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
82
intptr_t d2, TCGReg b2, TCGReg r3, int m4)
83
{
83
{
84
- uint32_t opr_align = oprsz >= 16 ? 15 : 7;
84
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
85
- uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
85
static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
86
- tcg_debug_assert(oprsz > 0);
86
TCGReg dst, TCGReg src)
87
- tcg_debug_assert(oprsz <= maxsz);
87
{
88
- tcg_debug_assert((oprsz & opr_align) == 0);
88
- g_assert_not_reached();
89
+ uint32_t max_align;
89
+ if (is_general_reg(src)) {
90
+
90
+ /* Replicate general register into two MO_64. */
91
+ switch (oprsz) {
91
+ tcg_out_insn(s, VRRf, VLVGP, dst, src, src);
92
+ case 8:
92
+ if (vece == MO_64) {
93
+ case 16:
93
+ return true;
94
+ case 32:
94
+ }
95
+ tcg_debug_assert(oprsz <= maxsz);
96
+ break;
97
+ default:
98
+ tcg_debug_assert(oprsz == maxsz);
99
+ break;
100
+ }
95
+ }
101
+ tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));
102
+
103
+ max_align = maxsz >= 16 ? 15 : 7;
104
tcg_debug_assert((maxsz & max_align) == 0);
105
tcg_debug_assert((ofs & max_align) == 0);
106
}
107
@@ -XXX,XX +XXX,XX @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
108
{
109
uint32_t desc = 0;
110
111
- assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
112
- assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
113
- assert(data == sextract32(data, 0, SIMD_DATA_BITS));
114
+ check_size_align(oprsz, maxsz, 0);
115
+ tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));
116
117
oprsz = (oprsz / 8) - 1;
118
maxsz = (maxsz / 8) - 1;
119
+
96
+
120
+ /*
97
+ /*
121
+ * We have just asserted in check_size_align that either
98
+ * Recall that the "standard" integer, within a vector, is the
122
+ * oprsz is {8,16,32} or matches maxsz. Encode the final
99
+ * rightmost element of the leftmost doubleword, a-la VLLEZ.
123
+ * case with '2', as that would otherwise map to 24.
124
+ */
100
+ */
125
+ if (oprsz == maxsz) {
101
+ tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece);
126
+ oprsz = 2;
102
+ return true;
103
}
104
105
static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
106
TCGReg dst, TCGReg base, intptr_t offset)
107
{
108
- g_assert_not_reached();
109
+ tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece);
110
+ return true;
111
}
112
113
static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
114
TCGReg dst, int64_t val)
115
{
116
- g_assert_not_reached();
117
+ int i, mask, msb, lsb;
118
+
119
+ /* Look for int16_t elements. */
120
+ if (vece <= MO_16 ||
121
+ (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) {
122
+ tcg_out_insn(s, VRIa, VREPI, dst, val, vece);
123
+ return;
127
+ }
124
+ }
128
+
125
+
129
desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
126
+ /* Look for bit masks. */
130
desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
127
+ if (vece == MO_32) {
131
desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
128
+ if (risbg_mask((int32_t)val)) {
129
+ /* Handle wraparound by swapping msb and lsb. */
130
+ if ((val & 0x80000001u) == 0x80000001u) {
131
+ msb = 32 - ctz32(~val);
132
+ lsb = clz32(~val) - 1;
133
+ } else {
134
+ msb = clz32(val);
135
+ lsb = 31 - ctz32(val);
136
+ }
137
+ tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
138
+ return;
139
+ }
140
+ } else {
141
+ if (risbg_mask(val)) {
142
+ /* Handle wraparound by swapping msb and lsb. */
143
+ if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
144
+ /* Handle wraparound by swapping msb and lsb. */
145
+ msb = 64 - ctz64(~val);
146
+ lsb = clz64(~val) - 1;
147
+ } else {
148
+ msb = clz64(val);
149
+ lsb = 63 - ctz64(val);
150
+ }
151
+ tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
152
+ return;
153
+ }
154
+ }
155
+
156
+ /* Look for all bytes 0x00 or 0xff. */
157
+ for (i = mask = 0; i < 8; i++) {
158
+ uint8_t byte = val >> (i * 8);
159
+ if (byte == 0xff) {
160
+ mask |= 1 << i;
161
+ } else if (byte != 0) {
162
+ break;
163
+ }
164
+ }
165
+ if (i == 8) {
166
+ tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0);
167
+ return;
168
+ }
169
+
170
+ /* Otherwise, stuff it in the constant pool. */
171
+ tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0);
172
+ new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2);
173
+ tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64);
174
}
175
176
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
132
--
177
--
133
2.25.1
178
2.25.1
134
179
135
180
diff view generated by jsdifflib
New patch
[PULL 21/28] tcg/s390x: Implement minimal vector operations
1
1
Implementing add, sub, and, or, xor as the minimal set.
2
This allows us to actually enable vectors in query_s390_facilities.
3
4
Reviewed-by: David Hildenbrand <david@redhat.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
tcg/s390x/tcg-target.c.inc | 154 ++++++++++++++++++++++++++++++++++++-
8
1 file changed, 150 insertions(+), 4 deletions(-)
9
10
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
11
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/s390x/tcg-target.c.inc
13
+++ b/tcg/s390x/tcg-target.c.inc
14
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
15
VRIc_VREP = 0xe74d,
16
17
VRRa_VLR = 0xe756,
18
+ VRRc_VA = 0xe7f3,
19
+ VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
20
+ VRRc_VCH = 0xe7fb, /* " */
21
+ VRRc_VCHL = 0xe7f9, /* " */
22
+ VRRc_VN = 0xe768,
23
+ VRRc_VO = 0xe76a,
24
+ VRRc_VS = 0xe7f7,
25
+ VRRc_VX = 0xe76d,
26
VRRf_VLVGP = 0xe762,
27
28
VRSb_VLVG = 0xe722,
29
@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op,
30
tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12));
31
}
32
33
+static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op,
34
+ TCGReg v1, TCGReg v2, TCGReg v3, int m4)
35
+{
36
+ tcg_debug_assert(is_vector_reg(v1));
37
+ tcg_debug_assert(is_vector_reg(v2));
38
+ tcg_debug_assert(is_vector_reg(v3));
39
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
40
+ tcg_out16(s, v3 << 12);
41
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12));
42
+}
43
+
44
static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
45
TCGReg v1, TCGReg r2, TCGReg r3)
46
{
47
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
48
unsigned vecl, unsigned vece,
49
const TCGArg *args, const int *const_args)
50
{
51
- g_assert_not_reached();
52
+ TCGType type = vecl + TCG_TYPE_V64;
53
+ TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
54
+
55
+ switch (opc) {
56
+ case INDEX_op_ld_vec:
57
+ tcg_out_ld(s, type, a0, a1, a2);
58
+ break;
59
+ case INDEX_op_st_vec:
60
+ tcg_out_st(s, type, a0, a1, a2);
61
+ break;
62
+ case INDEX_op_dupm_vec:
63
+ tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
64
+ break;
65
+
66
+ case INDEX_op_add_vec:
67
+ tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece);
68
+ break;
69
+ case INDEX_op_sub_vec:
70
+ tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece);
71
+ break;
72
+ case INDEX_op_and_vec:
73
+ tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0);
74
+ break;
75
+ case INDEX_op_or_vec:
76
+ tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
77
+ break;
78
+ case INDEX_op_xor_vec:
79
+ tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
80
+ break;
81
+
82
+ case INDEX_op_cmp_vec:
83
+ switch ((TCGCond)args[3]) {
84
+ case TCG_COND_EQ:
85
+ tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece);
86
+ break;
87
+ case TCG_COND_GT:
88
+ tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece);
89
+ break;
90
+ case TCG_COND_GTU:
91
+ tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece);
92
+ break;
93
+ default:
94
+ g_assert_not_reached();
95
+ }
96
+ break;
97
+
98
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
99
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
100
+ default:
101
+ g_assert_not_reached();
102
+ }
103
}
104
105
int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
106
{
107
- return 0;
108
+ switch (opc) {
109
+ case INDEX_op_add_vec:
110
+ case INDEX_op_and_vec:
111
+ case INDEX_op_or_vec:
112
+ case INDEX_op_sub_vec:
113
+ case INDEX_op_xor_vec:
114
+ return 1;
115
+ case INDEX_op_cmp_vec:
116
+ return -1;
117
+ default:
118
+ return 0;
119
+ }
120
+}
121
+
122
+static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
123
+ TCGv_vec v1, TCGv_vec v2, TCGCond cond)
124
+{
125
+ bool need_swap = false, need_inv = false;
126
+
127
+ switch (cond) {
128
+ case TCG_COND_EQ:
129
+ case TCG_COND_GT:
130
+ case TCG_COND_GTU:
131
+ break;
132
+ case TCG_COND_NE:
133
+ case TCG_COND_LE:
134
+ case TCG_COND_LEU:
135
+ need_inv = true;
136
+ break;
137
+ case TCG_COND_LT:
138
+ case TCG_COND_LTU:
139
+ need_swap = true;
140
+ break;
141
+ case TCG_COND_GE:
142
+ case TCG_COND_GEU:
143
+ need_swap = need_inv = true;
144
+ break;
145
+ default:
146
+ g_assert_not_reached();
147
+ }
148
+
149
+ if (need_inv) {
150
+ cond = tcg_invert_cond(cond);
151
+ }
152
+ if (need_swap) {
153
+ TCGv_vec t1;
154
+ t1 = v1, v1 = v2, v2 = t1;
155
+ cond = tcg_swap_cond(cond);
156
+ }
157
+
158
+ vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
159
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
160
+
161
+ return need_inv;
162
+}
163
+
164
+static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
165
+ TCGv_vec v1, TCGv_vec v2, TCGCond cond)
166
+{
167
+ if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) {
168
+ tcg_gen_not_vec(vece, v0, v0);
169
+ }
170
}
171
172
void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
173
TCGArg a0, ...)
174
{
175
- g_assert_not_reached();
176
+ va_list va;
177
+ TCGv_vec v0, v1, v2;
178
+
179
+ va_start(va, a0);
180
+ v0 = temp_tcgv_vec(arg_temp(a0));
181
+ v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
182
+ v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
183
+
184
+ switch (opc) {
185
+ case INDEX_op_cmp_vec:
186
+ expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
187
+ break;
188
+
189
+ default:
190
+ g_assert_not_reached();
191
+ }
192
+ va_end(va);
193
}
194
195
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
196
@@ -XXX,XX +XXX,XX @@ static void query_s390_facilities(void)
197
* There is nothing else we currently care about in the 3rd word, so
198
* disable VECTOR with one store.
199
*/
200
- if (1 || !(hwcap & HWCAP_S390_VXRS)) {
201
+ if (!(hwcap & HWCAP_S390_VXRS)) {
202
s390_facilities[2] = 0;
203
}
204
}
205
--
206
2.25.1
207
208
diff view generated by jsdifflib
New patch
[PULL 22/28] tcg/s390x: Implement andc, orc, abs, neg, not vector operations
1
These logical and arithmetic operations are optional but trivial.
1
2
3
Reviewed-by: David Hildenbrand <david@redhat.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
tcg/s390x/tcg-target-con-set.h | 1 +
7
tcg/s390x/tcg-target.h | 11 ++++++-----
8
tcg/s390x/tcg-target.c.inc | 32 ++++++++++++++++++++++++++++++++
9
3 files changed, 39 insertions(+), 5 deletions(-)
10
11
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/s390x/tcg-target-con-set.h
14
+++ b/tcg/s390x/tcg-target-con-set.h
15
@@ -XXX,XX +XXX,XX @@ C_O0_I2(v, r)
16
C_O1_I1(r, L)
17
C_O1_I1(r, r)
18
C_O1_I1(v, r)
19
+C_O1_I1(v, v)
20
C_O1_I1(v, vr)
21
C_O1_I2(r, 0, ri)
22
C_O1_I2(r, 0, rI)
23
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/tcg/s390x/tcg-target.h
26
+++ b/tcg/s390x/tcg-target.h
27
@@ -XXX,XX +XXX,XX @@ typedef enum TCGReg {
28
#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
29
#define FACILITY_LOAD_ON_COND2 53
30
#define FACILITY_VECTOR 129
31
+#define FACILITY_VECTOR_ENH1 135
32
33
extern uint64_t s390_facilities[3];
34
35
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
36
#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR)
37
#define TCG_TARGET_HAS_v256 0
38
39
-#define TCG_TARGET_HAS_andc_vec 0
40
-#define TCG_TARGET_HAS_orc_vec 0
41
-#define TCG_TARGET_HAS_not_vec 0
42
-#define TCG_TARGET_HAS_neg_vec 0
43
-#define TCG_TARGET_HAS_abs_vec 0
44
+#define TCG_TARGET_HAS_andc_vec 1
45
+#define TCG_TARGET_HAS_orc_vec HAVE_FACILITY(VECTOR_ENH1)
46
+#define TCG_TARGET_HAS_not_vec 1
47
+#define TCG_TARGET_HAS_neg_vec 1
48
+#define TCG_TARGET_HAS_abs_vec 1
49
#define TCG_TARGET_HAS_roti_vec 0
50
#define TCG_TARGET_HAS_rots_vec 0
51
#define TCG_TARGET_HAS_rotv_vec 0
52
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
53
index XXXXXXX..XXXXXXX 100644
54
--- a/tcg/s390x/tcg-target.c.inc
55
+++ b/tcg/s390x/tcg-target.c.inc
56
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
57
VRIb_VGM = 0xe746,
58
VRIc_VREP = 0xe74d,
59
60
+ VRRa_VLC = 0xe7de,
61
+ VRRa_VLP = 0xe7df,
62
VRRa_VLR = 0xe756,
63
VRRc_VA = 0xe7f3,
64
VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
65
VRRc_VCH = 0xe7fb, /* " */
66
VRRc_VCHL = 0xe7f9, /* " */
67
VRRc_VN = 0xe768,
68
+ VRRc_VNC = 0xe769,
69
+ VRRc_VNO = 0xe76b,
70
VRRc_VO = 0xe76a,
71
+ VRRc_VOC = 0xe76f,
72
VRRc_VS = 0xe7f7,
73
VRRc_VX = 0xe76d,
74
VRRf_VLVGP = 0xe762,
75
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
76
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
77
break;
78
79
+ case INDEX_op_abs_vec:
80
+ tcg_out_insn(s, VRRa, VLP, a0, a1, vece);
81
+ break;
82
+ case INDEX_op_neg_vec:
83
+ tcg_out_insn(s, VRRa, VLC, a0, a1, vece);
84
+ break;
85
+ case INDEX_op_not_vec:
86
+ tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0);
87
+ break;
88
+
89
case INDEX_op_add_vec:
90
tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece);
91
break;
92
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
93
case INDEX_op_and_vec:
94
tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0);
95
break;
96
+ case INDEX_op_andc_vec:
97
+ tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0);
98
+ break;
99
case INDEX_op_or_vec:
100
tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
101
break;
102
+ case INDEX_op_orc_vec:
103
+ tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0);
104
+ break;
105
case INDEX_op_xor_vec:
106
tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
107
break;
108
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
109
int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
110
{
111
switch (opc) {
112
+ case INDEX_op_abs_vec:
113
case INDEX_op_add_vec:
114
case INDEX_op_and_vec:
115
+ case INDEX_op_andc_vec:
116
+ case INDEX_op_neg_vec:
117
+ case INDEX_op_not_vec:
118
case INDEX_op_or_vec:
119
+ case INDEX_op_orc_vec:
120
case INDEX_op_sub_vec:
121
case INDEX_op_xor_vec:
122
return 1;
123
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
124
return C_O1_I1(v, r);
125
case INDEX_op_dup_vec:
126
return C_O1_I1(v, vr);
127
+ case INDEX_op_abs_vec:
128
+ case INDEX_op_neg_vec:
129
+ case INDEX_op_not_vec:
130
+ return C_O1_I1(v, v);
131
case INDEX_op_add_vec:
132
case INDEX_op_sub_vec:
133
case INDEX_op_and_vec:
134
+ case INDEX_op_andc_vec:
135
case INDEX_op_or_vec:
136
+ case INDEX_op_orc_vec:
137
case INDEX_op_xor_vec:
138
case INDEX_op_cmp_vec:
139
return C_O1_I2(v, v, v);
140
--
141
2.25.1
142
143
diff view generated by jsdifflib
New patch
[PULL 23/28] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec
1
Reviewed-by: David Hildenbrand <david@redhat.com>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/s390x/tcg-target.h | 2 +-
5
tcg/s390x/tcg-target.c.inc | 7 +++++++
6
2 files changed, 8 insertions(+), 1 deletion(-)
1
7
8
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/s390x/tcg-target.h
11
+++ b/tcg/s390x/tcg-target.h
12
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
13
#define TCG_TARGET_HAS_shi_vec 0
14
#define TCG_TARGET_HAS_shs_vec 0
15
#define TCG_TARGET_HAS_shv_vec 0
16
-#define TCG_TARGET_HAS_mul_vec 0
17
+#define TCG_TARGET_HAS_mul_vec 1
18
#define TCG_TARGET_HAS_sat_vec 0
19
#define TCG_TARGET_HAS_minmax_vec 0
20
#define TCG_TARGET_HAS_bitsel_vec 0
21
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/tcg/s390x/tcg-target.c.inc
24
+++ b/tcg/s390x/tcg-target.c.inc
25
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
26
VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
27
VRRc_VCH = 0xe7fb, /* " */
28
VRRc_VCHL = 0xe7f9, /* " */
29
+ VRRc_VML = 0xe7a2,
30
VRRc_VN = 0xe768,
31
VRRc_VNC = 0xe769,
32
VRRc_VNO = 0xe76b,
33
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
34
case INDEX_op_andc_vec:
35
tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0);
36
break;
37
+ case INDEX_op_mul_vec:
38
+ tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece);
39
+ break;
40
case INDEX_op_or_vec:
41
tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
42
break;
43
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
44
return 1;
45
case INDEX_op_cmp_vec:
46
return -1;
47
+ case INDEX_op_mul_vec:
48
+ return vece < MO_64;
49
default:
50
return 0;
51
}
52
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
53
case INDEX_op_orc_vec:
54
case INDEX_op_xor_vec:
55
case INDEX_op_cmp_vec:
56
+ case INDEX_op_mul_vec:
57
return C_O1_I2(v, v, v);
58
59
default:
60
--
61
2.25.1
62
63
diff view generated by jsdifflib
New patch
[PULL 24/28] tcg/s390x: Implement vector shift operations
1
Reviewed-by: David Hildenbrand <david@redhat.com>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/s390x/tcg-target-con-set.h | 1 +
5
tcg/s390x/tcg-target.h | 12 ++---
6
tcg/s390x/tcg-target.c.inc | 93 +++++++++++++++++++++++++++++++++-
7
3 files changed, 99 insertions(+), 7 deletions(-)
1
8
9
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/s390x/tcg-target-con-set.h
12
+++ b/tcg/s390x/tcg-target-con-set.h
13
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, 0, rI)
14
C_O1_I2(r, 0, rJ)
15
C_O1_I2(r, r, ri)
16
C_O1_I2(r, rZ, r)
17
+C_O1_I2(v, v, r)
18
C_O1_I2(v, v, v)
19
C_O1_I4(r, r, ri, r, 0)
20
C_O1_I4(r, r, ri, rI, 0)
21
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/tcg/s390x/tcg-target.h
24
+++ b/tcg/s390x/tcg-target.h
25
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
26
#define TCG_TARGET_HAS_not_vec 1
27
#define TCG_TARGET_HAS_neg_vec 1
28
#define TCG_TARGET_HAS_abs_vec 1
29
-#define TCG_TARGET_HAS_roti_vec 0
30
-#define TCG_TARGET_HAS_rots_vec 0
31
-#define TCG_TARGET_HAS_rotv_vec 0
32
-#define TCG_TARGET_HAS_shi_vec 0
33
-#define TCG_TARGET_HAS_shs_vec 0
34
-#define TCG_TARGET_HAS_shv_vec 0
35
+#define TCG_TARGET_HAS_roti_vec 1
36
+#define TCG_TARGET_HAS_rots_vec 1
37
+#define TCG_TARGET_HAS_rotv_vec 1
38
+#define TCG_TARGET_HAS_shi_vec 1
39
+#define TCG_TARGET_HAS_shs_vec 1
40
+#define TCG_TARGET_HAS_shv_vec 1
41
#define TCG_TARGET_HAS_mul_vec 1
42
#define TCG_TARGET_HAS_sat_vec 0
43
#define TCG_TARGET_HAS_minmax_vec 0
44
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/tcg/s390x/tcg-target.c.inc
47
+++ b/tcg/s390x/tcg-target.c.inc
48
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
49
VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */
50
VRRc_VCH = 0xe7fb, /* " */
51
VRRc_VCHL = 0xe7f9, /* " */
52
+ VRRc_VERLLV = 0xe773,
53
+ VRRc_VESLV = 0xe770,
54
+ VRRc_VESRAV = 0xe77a,
55
+ VRRc_VESRLV = 0xe778,
56
VRRc_VML = 0xe7a2,
57
VRRc_VN = 0xe768,
58
VRRc_VNC = 0xe769,
59
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
60
VRRc_VX = 0xe76d,
61
VRRf_VLVGP = 0xe762,
62
63
+ VRSa_VERLL = 0xe733,
64
+ VRSa_VESL = 0xe730,
65
+ VRSa_VESRA = 0xe73a,
66
+ VRSa_VESRL = 0xe738,
67
VRSb_VLVG = 0xe722,
68
VRSc_VLGV = 0xe721,
69
70
@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
71
tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0));
72
}
73
74
+static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1,
75
+ intptr_t d2, TCGReg b2, TCGReg v3, int m4)
76
+{
77
+ tcg_debug_assert(is_vector_reg(v1));
78
+ tcg_debug_assert(d2 >= 0 && d2 <= 0xfff);
79
+ tcg_debug_assert(is_general_reg(b2));
80
+ tcg_debug_assert(is_vector_reg(v3));
81
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf));
82
+ tcg_out16(s, b2 << 12 | d2);
83
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12));
84
+}
85
+
86
static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1,
87
intptr_t d2, TCGReg b2, TCGReg r3, int m4)
88
{
89
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
90
tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
91
break;
92
93
+ case INDEX_op_shli_vec:
94
+ tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece);
95
+ break;
96
+ case INDEX_op_shri_vec:
97
+ tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece);
98
+ break;
99
+ case INDEX_op_sari_vec:
100
+ tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece);
101
+ break;
102
+ case INDEX_op_rotli_vec:
103
+ tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece);
104
+ break;
105
+ case INDEX_op_shls_vec:
106
+ tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece);
107
+ break;
108
+ case INDEX_op_shrs_vec:
109
+ tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece);
110
+ break;
111
+ case INDEX_op_sars_vec:
112
+ tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece);
113
+ break;
114
+ case INDEX_op_rotls_vec:
115
+ tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece);
116
+ break;
117
+ case INDEX_op_shlv_vec:
118
+ tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece);
119
+ break;
120
+ case INDEX_op_shrv_vec:
121
+ tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece);
122
+ break;
123
+ case INDEX_op_sarv_vec:
124
+ tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece);
125
+ break;
126
+ case INDEX_op_rotlv_vec:
127
+ tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece);
128
+ break;
129
+
130
case INDEX_op_cmp_vec:
131
switch ((TCGCond)args[3]) {
132
case TCG_COND_EQ:
133
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
134
case INDEX_op_not_vec:
135
case INDEX_op_or_vec:
136
case INDEX_op_orc_vec:
137
+ case INDEX_op_rotli_vec:
138
+ case INDEX_op_rotls_vec:
139
+ case INDEX_op_rotlv_vec:
140
+ case INDEX_op_sari_vec:
141
+ case INDEX_op_sars_vec:
142
+ case INDEX_op_sarv_vec:
143
+ case INDEX_op_shli_vec:
144
+ case INDEX_op_shls_vec:
145
+ case INDEX_op_shlv_vec:
146
+ case INDEX_op_shri_vec:
147
+ case INDEX_op_shrs_vec:
148
+ case INDEX_op_shrv_vec:
149
case INDEX_op_sub_vec:
150
case INDEX_op_xor_vec:
151
return 1;
152
case INDEX_op_cmp_vec:
153
+ case INDEX_op_rotrv_vec:
154
return -1;
155
case INDEX_op_mul_vec:
156
return vece < MO_64;
157
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
158
TCGArg a0, ...)
159
{
160
va_list va;
161
- TCGv_vec v0, v1, v2;
162
+ TCGv_vec v0, v1, v2, t0;
163
164
va_start(va, a0);
165
v0 = temp_tcgv_vec(arg_temp(a0));
166
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
167
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
168
break;
169
170
+ case INDEX_op_rotrv_vec:
171
+ t0 = tcg_temp_new_vec(type);
172
+ tcg_gen_neg_vec(vece, t0, v2);
173
+ tcg_gen_rotlv_vec(vece, v0, v1, t0);
174
+ tcg_temp_free_vec(t0);
175
+ break;
176
+
177
default:
178
g_assert_not_reached();
179
}
180
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
181
case INDEX_op_abs_vec:
182
case INDEX_op_neg_vec:
183
case INDEX_op_not_vec:
184
+ case INDEX_op_rotli_vec:
185
+ case INDEX_op_sari_vec:
186
+ case INDEX_op_shli_vec:
187
+ case INDEX_op_shri_vec:
188
return C_O1_I1(v, v);
189
case INDEX_op_add_vec:
190
case INDEX_op_sub_vec:
191
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
192
case INDEX_op_xor_vec:
193
case INDEX_op_cmp_vec:
194
case INDEX_op_mul_vec:
195
+ case INDEX_op_rotlv_vec:
196
+ case INDEX_op_rotrv_vec:
197
+ case INDEX_op_shlv_vec:
198
+ case INDEX_op_shrv_vec:
199
+ case INDEX_op_sarv_vec:
200
return C_O1_I2(v, v, v);
201
+ case INDEX_op_rotls_vec:
202
+ case INDEX_op_shls_vec:
203
+ case INDEX_op_shrs_vec:
204
+ case INDEX_op_sars_vec:
205
+ return C_O1_I2(v, v, r);
206
207
default:
208
g_assert_not_reached();
209
--
210
2.25.1
211
212
diff view generated by jsdifflib
New patch
[PULL 25/28] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec
1
Reviewed-by: David Hildenbrand <david@redhat.com>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
4
tcg/s390x/tcg-target.h | 2 +-
5
tcg/s390x/tcg-target.c.inc | 25 +++++++++++++++++++++++++
6
2 files changed, 26 insertions(+), 1 deletion(-)
1
7
8
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
9
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/s390x/tcg-target.h
11
+++ b/tcg/s390x/tcg-target.h
12
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
13
#define TCG_TARGET_HAS_shv_vec 1
14
#define TCG_TARGET_HAS_mul_vec 1
15
#define TCG_TARGET_HAS_sat_vec 0
16
-#define TCG_TARGET_HAS_minmax_vec 0
17
+#define TCG_TARGET_HAS_minmax_vec 1
18
#define TCG_TARGET_HAS_bitsel_vec 0
19
#define TCG_TARGET_HAS_cmpsel_vec 0
20
21
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/tcg/s390x/tcg-target.c.inc
24
+++ b/tcg/s390x/tcg-target.c.inc
25
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
26
VRRc_VESRAV = 0xe77a,
27
VRRc_VESRLV = 0xe778,
28
VRRc_VML = 0xe7a2,
29
+ VRRc_VMN = 0xe7fe,
30
+ VRRc_VMNL = 0xe7fc,
31
+ VRRc_VMX = 0xe7ff,
32
+ VRRc_VMXL = 0xe7fd,
33
VRRc_VN = 0xe768,
34
VRRc_VNC = 0xe769,
35
VRRc_VNO = 0xe76b,
36
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
37
tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece);
38
break;
39
40
+ case INDEX_op_smin_vec:
41
+ tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece);
42
+ break;
43
+ case INDEX_op_smax_vec:
44
+ tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece);
45
+ break;
46
+ case INDEX_op_umin_vec:
47
+ tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece);
48
+ break;
49
+ case INDEX_op_umax_vec:
50
+ tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece);
51
+ break;
52
+
53
case INDEX_op_cmp_vec:
54
switch ((TCGCond)args[3]) {
55
case TCG_COND_EQ:
56
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
57
case INDEX_op_shri_vec:
58
case INDEX_op_shrs_vec:
59
case INDEX_op_shrv_vec:
60
+ case INDEX_op_smax_vec:
61
+ case INDEX_op_smin_vec:
62
case INDEX_op_sub_vec:
63
+ case INDEX_op_umax_vec:
64
+ case INDEX_op_umin_vec:
65
case INDEX_op_xor_vec:
66
return 1;
67
case INDEX_op_cmp_vec:
68
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
69
case INDEX_op_shlv_vec:
70
case INDEX_op_shrv_vec:
71
case INDEX_op_sarv_vec:
72
+ case INDEX_op_smax_vec:
73
+ case INDEX_op_smin_vec:
74
+ case INDEX_op_umax_vec:
75
+ case INDEX_op_umin_vec:
76
return C_O1_I2(v, v, v);
77
case INDEX_op_rotls_vec:
78
case INDEX_op_shls_vec:
79
--
80
2.25.1
81
82
diff view generated by jsdifflib
New patch
[PULL 26/28] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec
1
The unsigned saturations are handled via generic code
2
using min/max. The signed saturations are expanded using
3
double-sized arithmetic and a saturating pack.
1
4
5
Since all operations are done via expansion, do not
6
actually set TCG_TARGET_HAS_sat_vec.
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
---
10
tcg/s390x/tcg-target.opc.h | 3 ++
11
tcg/s390x/tcg-target.c.inc | 63 ++++++++++++++++++++++++++++++++++++++
12
2 files changed, 66 insertions(+)
13
14
diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target.opc.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tcg/s390x/tcg-target.opc.h
17
+++ b/tcg/s390x/tcg-target.opc.h
18
@@ -XXX,XX +XXX,XX @@
19
* emitted by tcg_expand_vec_op. For those familiar with GCC internals,
20
* consider these to be UNSPEC with names.
21
*/
22
+DEF(s390_vuph_vec, 1, 1, 0, IMPLVEC)
23
+DEF(s390_vupl_vec, 1, 1, 0, IMPLVEC)
24
+DEF(s390_vpks_vec, 1, 2, 0, IMPLVEC)
25
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tcg/s390x/tcg-target.c.inc
28
+++ b/tcg/s390x/tcg-target.c.inc
29
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
30
VRRc_VNO = 0xe76b,
31
VRRc_VO = 0xe76a,
32
VRRc_VOC = 0xe76f,
33
+ VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */
34
VRRc_VS = 0xe7f7,
35
+ VRRa_VUPH = 0xe7d7,
36
+ VRRa_VUPL = 0xe7d6,
37
VRRc_VX = 0xe76d,
38
VRRf_VLVGP = 0xe762,
39
40
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
41
}
42
break;
43
44
+ case INDEX_op_s390_vuph_vec:
45
+ tcg_out_insn(s, VRRa, VUPH, a0, a1, vece);
46
+ break;
47
+ case INDEX_op_s390_vupl_vec:
48
+ tcg_out_insn(s, VRRa, VUPL, a0, a1, vece);
49
+ break;
50
+ case INDEX_op_s390_vpks_vec:
51
+ tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece);
52
+ break;
53
+
54
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
55
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
56
default:
57
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
58
return -1;
59
case INDEX_op_mul_vec:
60
return vece < MO_64;
61
+ case INDEX_op_ssadd_vec:
62
+ case INDEX_op_sssub_vec:
63
+ return vece < MO_64 ? -1 : 0;
64
default:
65
return 0;
66
}
67
@@ -XXX,XX +XXX,XX @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
68
}
69
}
70
71
+static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0,
72
+ TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc)
73
+{
74
+ TCGv_vec h1 = tcg_temp_new_vec(type);
75
+ TCGv_vec h2 = tcg_temp_new_vec(type);
76
+ TCGv_vec l1 = tcg_temp_new_vec(type);
77
+ TCGv_vec l2 = tcg_temp_new_vec(type);
78
+
79
+ tcg_debug_assert (vece < MO_64);
80
+
81
+ /* Unpack with sign-extension. */
82
+ vec_gen_2(INDEX_op_s390_vuph_vec, type, vece,
83
+ tcgv_vec_arg(h1), tcgv_vec_arg(v1));
84
+ vec_gen_2(INDEX_op_s390_vuph_vec, type, vece,
85
+ tcgv_vec_arg(h2), tcgv_vec_arg(v2));
86
+
87
+ vec_gen_2(INDEX_op_s390_vupl_vec, type, vece,
88
+ tcgv_vec_arg(l1), tcgv_vec_arg(v1));
89
+ vec_gen_2(INDEX_op_s390_vupl_vec, type, vece,
90
+ tcgv_vec_arg(l2), tcgv_vec_arg(v2));
91
+
92
+ /* Arithmetic on a wider element size. */
93
+ vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1),
94
+ tcgv_vec_arg(h1), tcgv_vec_arg(h2));
95
+ vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1),
96
+ tcgv_vec_arg(l1), tcgv_vec_arg(l2));
97
+
98
+ /* Pack with saturation. */
99
+ vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1,
100
+ tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1));
101
+
102
+ tcg_temp_free_vec(h1);
103
+ tcg_temp_free_vec(h2);
104
+ tcg_temp_free_vec(l1);
105
+ tcg_temp_free_vec(l2);
106
+}
107
+
108
void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
109
TCGArg a0, ...)
110
{
111
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
112
tcg_temp_free_vec(t0);
113
break;
114
115
+ case INDEX_op_ssadd_vec:
116
+ expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec);
117
+ break;
118
+ case INDEX_op_sssub_vec:
119
+ expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec);
120
+ break;
121
+
122
default:
123
g_assert_not_reached();
124
}
125
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
126
case INDEX_op_sari_vec:
127
case INDEX_op_shli_vec:
128
case INDEX_op_shri_vec:
129
+ case INDEX_op_s390_vuph_vec:
130
+ case INDEX_op_s390_vupl_vec:
131
return C_O1_I1(v, v);
132
case INDEX_op_add_vec:
133
case INDEX_op_sub_vec:
134
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
135
case INDEX_op_smin_vec:
136
case INDEX_op_umax_vec:
137
case INDEX_op_umin_vec:
138
+ case INDEX_op_s390_vpks_vec:
139
return C_O1_I2(v, v, v);
140
case INDEX_op_rotls_vec:
141
case INDEX_op_shls_vec:
142
--
143
2.25.1
144
145
diff view generated by jsdifflib
[PULL 07/11] tcg/i386: Fix dupi for avx2 32-bit hosts
[PULL 27/28] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec
1
The previous change wrongly stated that 32-bit avx2 should have
2
used VPBROADCASTW. But that's a 16-bit broadcast and we want a
3
32-bit broadcast.
4
5
Fixes: 7b60ef3264e
6
Cc: qemu-stable@nongnu.org
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
2
---
9
tcg/i386/tcg-target.c.inc | 2 +-
3
tcg/s390x/tcg-target-con-set.h | 1 +
10
1 file changed, 1 insertion(+), 1 deletion(-)
4
tcg/s390x/tcg-target.h | 2 +-
5
tcg/s390x/tcg-target.c.inc | 20 ++++++++++++++++++++
6
3 files changed, 22 insertions(+), 1 deletion(-)
11
7
12
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
8
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
13
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
14
--- a/tcg/i386/tcg-target.c.inc
10
--- a/tcg/s390x/tcg-target-con-set.h
15
+++ b/tcg/i386/tcg-target.c.inc
11
+++ b/tcg/s390x/tcg-target-con-set.h
16
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
12
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, ri)
17
new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
13
C_O1_I2(r, rZ, r)
18
} else {
14
C_O1_I2(v, v, r)
19
if (have_avx2) {
15
C_O1_I2(v, v, v)
20
- tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret);
16
+C_O1_I3(v, v, v, v)
21
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
17
C_O1_I4(r, r, ri, r, 0)
22
} else {
18
C_O1_I4(r, r, ri, rI, 0)
23
tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
19
C_O2_I2(b, a, 0, r)
24
}
20
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/tcg/s390x/tcg-target.h
23
+++ b/tcg/s390x/tcg-target.h
24
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities[3];
25
#define TCG_TARGET_HAS_mul_vec 1
26
#define TCG_TARGET_HAS_sat_vec 0
27
#define TCG_TARGET_HAS_minmax_vec 1
28
-#define TCG_TARGET_HAS_bitsel_vec 0
29
+#define TCG_TARGET_HAS_bitsel_vec 1
30
#define TCG_TARGET_HAS_cmpsel_vec 0
31
32
/* used for function call generation */
33
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
34
index XXXXXXX..XXXXXXX 100644
35
--- a/tcg/s390x/tcg-target.c.inc
36
+++ b/tcg/s390x/tcg-target.c.inc
37
@@ -XXX,XX +XXX,XX @@ typedef enum S390Opcode {
38
VRRa_VUPH = 0xe7d7,
39
VRRa_VUPL = 0xe7d6,
40
VRRc_VX = 0xe76d,
41
+ VRRe_VSEL = 0xe78d,
42
VRRf_VLVGP = 0xe762,
43
44
VRSa_VERLL = 0xe733,
45
@@ -XXX,XX +XXX,XX @@ static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op,
46
tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12));
47
}
48
49
+static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op,
50
+ TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4)
51
+{
52
+ tcg_debug_assert(is_vector_reg(v1));
53
+ tcg_debug_assert(is_vector_reg(v2));
54
+ tcg_debug_assert(is_vector_reg(v3));
55
+ tcg_debug_assert(is_vector_reg(v4));
56
+ tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v2 & 0xf));
57
+ tcg_out16(s, v3 << 12);
58
+ tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | (v4 << 12));
59
+}
60
+
61
static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op,
62
TCGReg v1, TCGReg r2, TCGReg r3)
63
{
64
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
65
tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece);
66
break;
67
68
+ case INDEX_op_bitsel_vec:
69
+ tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
70
+ break;
71
+
72
case INDEX_op_cmp_vec:
73
switch ((TCGCond)args[3]) {
74
case TCG_COND_EQ:
75
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
76
case INDEX_op_add_vec:
77
case INDEX_op_and_vec:
78
case INDEX_op_andc_vec:
79
+ case INDEX_op_bitsel_vec:
80
case INDEX_op_neg_vec:
81
case INDEX_op_not_vec:
82
case INDEX_op_or_vec:
83
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
84
case INDEX_op_shrs_vec:
85
case INDEX_op_sars_vec:
86
return C_O1_I2(v, v, r);
87
+ case INDEX_op_bitsel_vec:
88
+ return C_O1_I3(v, v, v, v);
89
90
default:
91
g_assert_not_reached();
25
--
92
--
26
2.25.1
93
2.25.1
27
94
28
95
diff view generated by jsdifflib
[PULL 09/11] tcg/optimize: Fold dup2_vec
[PULL 28/28] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec
1
When the two arguments are identical, this can be reduced to
1
This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec.
2
dup_vec or to mov_vec from a tcg_constant_vec.
3
2
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
4
---
6
tcg/optimize.c | 15 +++++++++++++++
5
tcg/s390x/tcg-target.c.inc | 24 +++++++++++++++++++++++-
7
1 file changed, 15 insertions(+)
6
1 file changed, 23 insertions(+), 1 deletion(-)
8
7
9
diff --git a/tcg/optimize.c b/tcg/optimize.c
8
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
10
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/optimize.c
10
--- a/tcg/s390x/tcg-target.c.inc
12
+++ b/tcg/optimize.c
11
+++ b/tcg/s390x/tcg-target.c.inc
13
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
12
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
14
}
13
case INDEX_op_xor_vec:
15
goto do_default;
14
return 1;
16
15
case INDEX_op_cmp_vec:
17
+ case INDEX_op_dup2_vec:
16
+ case INDEX_op_cmpsel_vec:
18
+ assert(TCG_TARGET_REG_BITS == 32);
17
case INDEX_op_rotrv_vec:
19
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
18
return -1;
20
+ tmp = arg_info(op->args[1])->val;
19
case INDEX_op_mul_vec:
21
+ if (tmp == arg_info(op->args[2])->val) {
20
@@ -XXX,XX +XXX,XX @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
22
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
21
}
23
+ break;
22
}
24
+ }
23
25
+ } else if (args_are_copies(op->args[1], op->args[2])) {
24
+static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0,
26
+ op->opc = INDEX_op_dup_vec;
25
+ TCGv_vec c1, TCGv_vec c2,
27
+ TCGOP_VECE(op) = MO_32;
26
+ TCGv_vec v3, TCGv_vec v4, TCGCond cond)
28
+ nb_iargs = 1;
27
+{
29
+ }
28
+ TCGv_vec t = tcg_temp_new_vec(type);
30
+ goto do_default;
31
+
29
+
32
CASE_OP_32_64(not):
30
+ if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) {
33
CASE_OP_32_64(neg):
31
+ /* Invert the sense of the compare by swapping arguments. */
34
CASE_OP_32_64(ext8s):
32
+ tcg_gen_bitsel_vec(vece, v0, t, v4, v3);
33
+ } else {
34
+ tcg_gen_bitsel_vec(vece, v0, t, v3, v4);
35
+ }
36
+ tcg_temp_free_vec(t);
37
+}
38
+
39
static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0,
40
TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc)
41
{
42
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
43
TCGArg a0, ...)
44
{
45
va_list va;
46
- TCGv_vec v0, v1, v2, t0;
47
+ TCGv_vec v0, v1, v2, v3, v4, t0;
48
49
va_start(va, a0);
50
v0 = temp_tcgv_vec(arg_temp(a0));
51
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
52
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
53
break;
54
55
+ case INDEX_op_cmpsel_vec:
56
+ v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
57
+ v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
58
+ expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg));
59
+ break;
60
+
61
case INDEX_op_rotrv_vec:
62
t0 = tcg_temp_new_vec(type);
63
tcg_gen_neg_vec(vece, t0, v2);
35
--
64
--
36
2.25.1
65
2.25.1
37
66
38
67
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.