The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)

https://github.com/rth7680/qemu.git tags/pull-tcg-20201008

for you to fetch changes up to 62475e9d007d83db4d0a6ccebcda8914f392e9c9:

accel/tcg: Fix computing of is_write for MIPS (2020-10-08 05:57:32 -0500)

Extend maximum gvec vector size

Fix i386 avx2 dupi

Fix mips host user-only write detection

Misc cleanups.

Kele Huang (1):

accel/tcg: Fix computing of is_write for MIPS

Richard Henderson (10):

tcg: Adjust simd_desc size encoding

tcg: Drop union from TCGArgConstraint

tcg: Move sorted_args into TCGArgConstraint.sort_index

tcg: Remove TCG_CT_REG

tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields

tcg: Remove TCGOpDef.used

tcg/i386: Fix dupi for avx2 32-bit hosts

tcg: Fix generation of dupi_vec for 32-bit host

tcg/optimize: Fold dup2_vec

tcg: Remove TCG_TARGET_HAS_cmp_vec

include/tcg/tcg-gvec-desc.h | 38 ++++++++++++------

include/tcg/tcg.h | 22 ++++------

tcg/aarch64/tcg-target.h | 1 -

tcg/i386/tcg-target.h | 1 -

tcg/ppc/tcg-target.h | 1 -

accel/tcg/user-exec.c | 43 ++++++++++++++++++--

tcg/optimize.c | 15 +++++++

tcg/tcg-op-gvec.c | 35 ++++++++++++----

tcg/tcg-op-vec.c | 12 ++++--

tcg/tcg.c | 96 +++++++++++++++++++-------------------------

tcg/aarch64/tcg-target.c.inc | 17 ++++----

tcg/arm/tcg-target.c.inc | 29 ++++++-------

tcg/i386/tcg-target.c.inc | 39 +++++++-----------

tcg/mips/tcg-target.c.inc | 21 +++++-----

tcg/ppc/tcg-target.c.inc | 29 ++++++-------

tcg/riscv/tcg-target.c.inc | 16 ++++----

tcg/s390/tcg-target.c.inc | 22 +++++-----

tcg/sparc/tcg-target.c.inc | 21 ++++------

tcg/tci/tcg-target.c.inc | 3 +-

19 files changed, 244 insertions(+), 217 deletions(-)

From: Kele Huang <kele.hwang@gmail.com>

Detect all MIPS store instructions in cpu_signal_handler for all available

MIPS versions, and set is_write if encountering such store instructions.

This fixed the error while dealing with self-modified code for MIPS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Kele Huang <kele.hwang@gmail.com>

Signed-off-by: Xu Zou <iwatchnima@gmail.com>

Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>

[rth: Use uintptr_t for pc to fix n32 build error.]

accel/tcg/user-exec.c | 43 +++++++++++++++++++++++++++++++++++++++----

1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/user-exec.c

+++ b/accel/tcg/user-exec.c

@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,

#elif defined(__mips__)

+#if defined(__misp16) || defined(__mips_micromips)

+#error "Unsupported encoding"

+#endif

+

int cpu_signal_handler(int host_signum, void *pinfo,

void *puc)

{

siginfo_t *info = pinfo;

ucontext_t *uc = puc;

- greg_t pc = uc->uc_mcontext.pc;

- int is_write;

+ uintptr_t pc = uc->uc_mcontext.pc;

+ uint32_t insn = *(uint32_t *)pc;

+ int is_write = 0;

+

+ /* Detect all store instructions at program counter. */

+ switch((insn >> 26) & 077) {

+ case 050: /* SB */

+ case 051: /* SH */

+ case 052: /* SWL */

+ case 053: /* SW */

+ case 054: /* SDL */

+ case 055: /* SDR */

+ case 056: /* SWR */

+ case 070: /* SC */

+ case 071: /* SWC1 */

+ case 074: /* SCD */

+ case 075: /* SDC1 */

+ case 077: /* SD */

+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6

+ case 072: /* SWC2 */

+ case 076: /* SDC2 */

+#endif

+ is_write = 1;

+ break;

+ case 023: /* COP1X */

+ /* Required in all versions of MIPS64 since

+ MIPS64r1 and subsequent versions of MIPS32r2. */

+ switch (insn & 077) {

+ case 010: /* SWXC1 */

+ case 011: /* SDXC1 */

+ case 015: /* SUXC1 */

+ is_write = 1;

+ }

+ break;

+ }

- /* XXX: compute is_write */

- is_write = 0;

return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);

}

These are easier to set and test when they have their own fields.

Reduce the size of alias_index and sort_index to 4 bits, which is

sufficient for TCG_MAX_OP_ARGS. This leaves only the bits indicating

constants within the ct field.

Move all initialization to allocation time, rather than init

individual fields in process_op_defs.

include/tcg/tcg.h | 14 +++++++-------

tcg/tcg.c | 28 ++++++++++++----------------

2 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h

index XXXXXXX..XXXXXXX 100644

--- a/include/tcg/tcg.h

+++ b/include/tcg/tcg.h

@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void);

void tcg_dump_info(void);

void tcg_dump_op_count(void);

-#define TCG_CT_ALIAS 0x80

-#define TCG_CT_IALIAS 0x40

-#define TCG_CT_NEWREG 0x20 /* output requires a new register */

-#define TCG_CT_CONST 0x02 /* any constant of register size */

+#define TCG_CT_CONST 1 /* any constant of register size */

typedef struct TCGArgConstraint {

- uint16_t ct;

- uint8_t alias_index;

- uint8_t sort_index;

+ unsigned ct : 16;

+ unsigned alias_index : 4;

+ unsigned sort_index : 4;

+ bool oalias : 1;

+ bool ialias : 1;

+ bool newreg : 1;

TCGRegSet regs;

} TCGArgConstraint;

diff --git a/tcg/tcg.c b/tcg/tcg.c

index XXXXXXX..XXXXXXX 100644

--- a/tcg/tcg.c

+++ b/tcg/tcg.c

@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)

total_args += n;

- args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);

+ args_ct = g_new0(TCGArgConstraint, total_args);

for(op = 0; op < NB_OPS; op++) {

def = &tcg_op_defs[op];

@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)

const TCGArgConstraint *arg_ct = &def->args_ct[k];

int n;

- if (arg_ct->ct & TCG_CT_ALIAS) {

+ if (arg_ct->oalias) {

/* an alias is equivalent to a single register */

n = 1;

} else {

@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)

/* Incomplete TCGTargetOpDef entry. */

tcg_debug_assert(ct_str != NULL);

- def->args_ct[i].regs = 0;

- def->args_ct[i].ct = 0;

while (*ct_str != '\0') {

switch(*ct_str) {

case '0' ... '9':

@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)

tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);

tcg_debug_assert(oarg < def->nb_oargs);

tcg_debug_assert(def->args_ct[oarg].regs != 0);

- /* TCG_CT_ALIAS is for the output arguments.

- The input is tagged with TCG_CT_IALIAS. */

def->args_ct[i] = def->args_ct[oarg];

- def->args_ct[oarg].ct |= TCG_CT_ALIAS;

+ /* The output sets oalias. */

+ def->args_ct[oarg].oalias = true;

def->args_ct[oarg].alias_index = i;

- def->args_ct[i].ct |= TCG_CT_IALIAS;

+ /* The input sets ialias. */

+ def->args_ct[i].ialias = true;

def->args_ct[i].alias_index = oarg;

}

ct_str++;

break;

case '&':

- def->args_ct[i].ct |= TCG_CT_NEWREG;

+ def->args_ct[i].newreg = true;

ct_str++;

break;

case 'i':

@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)

set = *pset;

set &= ct->regs;

- if (ct->ct & TCG_CT_IALIAS) {

+ if (ct->ialias) {

set &= op->output_pref[ct->alias_index];

}

/* If the combination is not possible, restart. */

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

}

i_preferred_regs = o_preferred_regs = 0;

- if (arg_ct->ct & TCG_CT_IALIAS) {

+ if (arg_ct->ialias) {

o_preferred_regs = op->output_pref[arg_ct->alias_index];

if (ts->fixed_reg) {

/* if fixed register, we must allocate a new register

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

reg = ts->reg;

for (k2 = 0 ; k2 < k ; k2++) {

i2 = def->args_ct[nb_oargs + k2].sort_index;

- if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&

- reg == new_args[i2]) {

+ if (def->args_ct[i2].ialias && reg == new_args[i2]) {

goto allocate_in_reg;

}

}

@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)

/* ENV should not be modified. */

tcg_debug_assert(!ts->fixed_reg);

- if ((arg_ct->ct & TCG_CT_ALIAS)

- && !const_args[arg_ct->alias_index]) {

+ if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {

reg = new_args[arg_ct->alias_index];

- } else if (arg_ct->ct & TCG_CT_NEWREG) {

+ } else if (arg_ct->newreg) {

reg = tcg_reg_alloc(s, arg_ct->regs,

i_allocated_regs | o_allocated_regs,

op->output_pref[k], ts->indirect_base);

The previous change wrongly stated that 32-bit avx2 should have

used VPBROADCASTW. But that's a 16-bit broadcast and we want a

32-bit broadcast.

Fixes: 7b60ef3264e

Cc: qemu-stable@nongnu.org

tcg/i386/tcg-target.c.inc | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,

new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);

} else {

if (have_avx2) {

- tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret);

+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);

} else {

tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);

}

The cmp_vec opcode is mandatory; this symbol is unused.

tcg/aarch64/tcg-target.h | 1 -

tcg/i386/tcg-target.h | 1 -

tcg/ppc/tcg-target.h | 1 -

3 files changed, 3 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h

--- a/tcg/aarch64/tcg-target.h

+++ b/tcg/aarch64/tcg-target.h

@@ -XXX,XX +XXX,XX @@ typedef enum {

#define TCG_TARGET_HAS_shi_vec 1

#define TCG_TARGET_HAS_shs_vec 0

#define TCG_TARGET_HAS_shv_vec 1

-#define TCG_TARGET_HAS_cmp_vec 1

#define TCG_TARGET_HAS_mul_vec 1

#define TCG_TARGET_HAS_sat_vec 1

#define TCG_TARGET_HAS_minmax_vec 1

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h

index XXXXXXX..XXXXXXX 100644

--- a/tcg/i386/tcg-target.h

+++ b/tcg/i386/tcg-target.h

@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;

#define TCG_TARGET_HAS_shi_vec 1

#define TCG_TARGET_HAS_shs_vec 1

#define TCG_TARGET_HAS_shv_vec have_avx2

-#define TCG_TARGET_HAS_cmp_vec 1

#define TCG_TARGET_HAS_mul_vec 1

#define TCG_TARGET_HAS_sat_vec 1

#define TCG_TARGET_HAS_minmax_vec 1

diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h

index XXXXXXX..XXXXXXX 100644

--- a/tcg/ppc/tcg-target.h

+++ b/tcg/ppc/tcg-target.h

@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;

#define TCG_TARGET_HAS_shi_vec 0

#define TCG_TARGET_HAS_shs_vec 0

#define TCG_TARGET_HAS_shv_vec 1

-#define TCG_TARGET_HAS_cmp_vec 1

#define TCG_TARGET_HAS_mul_vec 1

#define TCG_TARGET_HAS_sat_vec 1

#define TCG_TARGET_HAS_minmax_vec 1

When the two arguments are identical, this can be reduced to

dup_vec or to mov_vec from a tcg_constant_vec.

tcg/optimize.c | 15 +++++++++++++++

1 file changed, 15 insertions(+)

diff --git a/tcg/optimize.c b/tcg/optimize.c

--- a/tcg/optimize.c

+++ b/tcg/optimize.c

@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)

}

goto do_default;

+ case INDEX_op_dup2_vec:

+ assert(TCG_TARGET_REG_BITS == 32);

+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {

+ tmp = arg_info(op->args[1])->val;

+ if (tmp == arg_info(op->args[2])->val) {

+ tcg_opt_gen_movi(s, op, op->args[0], tmp);

+ break;

+ }

+ } else if (args_are_copies(op->args[1], op->args[2])) {

+ op->opc = INDEX_op_dup_vec;

+ TCGOP_VECE(op) = MO_32;

+ nb_iargs = 1;

+ }

+ goto do_default;

+

CASE_OP_32_64(not):

CASE_OP_32_64(neg):

CASE_OP_32_64(ext8s):

The definition of INDEX_op_dupi_vec is that it operates on

units of tcg_target_ulong -- in this case 32 bits. It does

not work to use this for a uint64_t value that happens to be

small enough to fit in tcg_target_ulong.

Fixes: d2fd745fe8b

Fixes: db432672dc5

Cc: qemu-stable@nongnu.org

tcg/tcg-op-vec.c | 12 ++++++++----

1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c

--- a/tcg/tcg-op-vec.c

+++ b/tcg/tcg-op-vec.c

@@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)

void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)

- if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {

- do_dupi_vec(r, MO_32, a);

- } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {

+ if (TCG_TARGET_REG_BITS == 64) {

do_dupi_vec(r, MO_64, a);

+ } else if (a == dup_const(MO_32, a)) {

+ do_dupi_vec(r, MO_32, a);

} else {

TCGv_i64 c = tcg_const_i64(a);

tcg_gen_dup_i64_vec(MO_64, r, c);

@@ -XXX,XX +XXX,XX @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)

void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)

- do_dupi_vec(r, MO_REG, dup_const(vece, a));

+ if (vece == MO_64) {

+ tcg_gen_dup64i_vec(r, a);

+ } else {