Series comparison

-[PULL 00/11] tcg patch queue
+[PULL 00/15] tcg patch queue
-The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:
+The following changes since commit 1cbd2d914939ee6028e9688d4ba859a528c28405:
-  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)
+  Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-06-04 13:38:49 +0100)
 are available in the Git repository at:
-  https://github.com/rth7680/qemu.git tags/pull-tcg-20201008
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210604
-for you to fetch changes up to 62475e9d007d83db4d0a6ccebcda8914f392e9c9:
+for you to fetch changes up to 0006039e29b9e6118beab300146f7c4931f7a217:
-  accel/tcg: Fix computing of is_write for MIPS (2020-10-08 05:57:32 -0500)
+  tcg/arm: Implement TCG_TARGET_HAS_rotv_vec (2021-06-04 11:50:11 -0700)
 ----------------------------------------------------------------
-Extend maximum gvec vector size
+Host vector support for arm neon.
 Fix i386 avx2 dupi
 Fix mips host user-only write detection
 Misc cleanups.
 ----------------------------------------------------------------
-Kele Huang (1):
+Richard Henderson (15):
-      accel/tcg: Fix computing of is_write for MIPS
+      tcg: Change parameters for tcg_target_const_match
       tcg/arm: Add host vector framework
       tcg/arm: Implement tcg_out_ld/st for vector types
       tcg/arm: Implement tcg_out_mov for vector types
       tcg/arm: Implement tcg_out_dup*_vec
       tcg/arm: Implement minimal vector operations
       tcg/arm: Implement andc, orc, abs, neg, not vector operations
       tcg/arm: Implement TCG_TARGET_HAS_shi_vec
       tcg/arm: Implement TCG_TARGET_HAS_mul_vec
       tcg/arm: Implement TCG_TARGET_HAS_sat_vec
       tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
       tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
       tcg/arm: Implement TCG_TARGET_HAS_shv_vec
       tcg/arm: Implement TCG_TARGET_HAS_roti_vec
       tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
-Richard Henderson (10):
+ tcg/arm/tcg-target-con-set.h |  10 +
-      tcg: Adjust simd_desc size encoding
+ tcg/arm/tcg-target-con-str.h |   3 +
-      tcg: Drop union from TCGArgConstraint
+ tcg/arm/tcg-target.h         |  52 ++-
-      tcg: Move sorted_args into TCGArgConstraint.sort_index
+ tcg/arm/tcg-target.opc.h     |  16 +
-      tcg: Remove TCG_CT_REG
+ tcg/tcg.c                    |   5 +-
-      tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
+ tcg/aarch64/tcg-target.c.inc |   5 +-
-      tcg: Remove TCGOpDef.used
+ tcg/arm/tcg-target.c.inc     | 956 +++++++++++++++++++++++++++++++++++++++++--
-      tcg/i386: Fix dupi for avx2 32-bit hosts
+ tcg/i386/tcg-target.c.inc    |   4 +-
-      tcg: Fix generation of dupi_vec for 32-bit host
+ tcg/mips/tcg-target.c.inc    |   5 +-
-      tcg/optimize: Fold dup2_vec
+ tcg/ppc/tcg-target.c.inc     |   4 +-
-      tcg: Remove TCG_TARGET_HAS_cmp_vec
+ tcg/riscv/tcg-target.c.inc   |   4 +-
  tcg/s390/tcg-target.c.inc    |   5 +-
  tcg/sparc/tcg-target.c.inc   |   5 +-
  tcg/tci/tcg-target.c.inc     |   6 +-
 files changed, 1001 insertions(+), 79 deletions(-)
  create mode 100644 tcg/arm/tcg-target.opc.h
- include/tcg/tcg-gvec-desc.h  | 38 ++++++++++++------
- include/tcg/tcg.h            | 22 ++++------
- tcg/aarch64/tcg-target.h     |  1 -
- tcg/i386/tcg-target.h        |  1 -
- tcg/ppc/tcg-target.h         |  1 -
- accel/tcg/user-exec.c        | 43 ++++++++++++++++++--
- tcg/optimize.c               | 15 +++++++
- tcg/tcg-op-gvec.c            | 35 ++++++++++++----
- tcg/tcg-op-vec.c             | 12 ++++--
- tcg/tcg.c                    | 96 +++++++++++++++++++-------------------------
- tcg/aarch64/tcg-target.c.inc | 17 ++++----
- tcg/arm/tcg-target.c.inc     | 29 ++++++-------
- tcg/i386/tcg-target.c.inc    | 39 +++++++-----------
- tcg/mips/tcg-target.c.inc    | 21 +++++-----
- tcg/ppc/tcg-target.c.inc     | 29 ++++++-------
- tcg/riscv/tcg-target.c.inc   | 16 ++++----
- tcg/s390/tcg-target.c.inc    | 22 +++++-----
- tcg/sparc/tcg-target.c.inc   | 21 ++++------
- tcg/tci/tcg-target.c.inc     |  3 +-
-files changed, 244 insertions(+), 217 deletions(-)

-[PULL 04/11] tcg: Remove TCG_CT_REG
+[PULL 01/15] tcg: Change parameters for tcg_target_const_match
-This wasn't actually used for anything, really.  All variable
+Change the return value to bool, because that's what is should
-operands must accept registers, and which are indicated by the
+have been from the start.  Pass the ct mask instead of the whole
-set in TCGArgConstraint.regs.
+TCGArgConstraint, as that's the only part that's relevant.
 Change the value argument to int64_t.  We will need the extra
 width for 32-bit hosts wanting to match vector constants.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/tcg/tcg.h            |  1 -
+ tcg/tcg.c                    | 5 ++---
- tcg/tcg.c                    | 15 ++++-----------
+ tcg/aarch64/tcg-target.c.inc | 5 +----
- tcg/aarch64/tcg-target.c.inc |  3 ---
+ tcg/arm/tcg-target.c.inc     | 5 +----
- tcg/arm/tcg-target.c.inc     |  3 ---
+ tcg/i386/tcg-target.c.inc    | 4 +---
- tcg/i386/tcg-target.c.inc    | 11 -----------
+ tcg/mips/tcg-target.c.inc    | 5 +----
- tcg/mips/tcg-target.c.inc    |  3 ---
+ tcg/ppc/tcg-target.c.inc     | 4 +---
- tcg/ppc/tcg-target.c.inc     |  5 -----
+ tcg/riscv/tcg-target.c.inc   | 4 +---
- tcg/riscv/tcg-target.c.inc   |  2 --
+ tcg/s390/tcg-target.c.inc    | 5 +----
- tcg/s390/tcg-target.c.inc    |  4 ----
+ tcg/sparc/tcg-target.c.inc   | 5 +----
- tcg/sparc/tcg-target.c.inc   |  5 -----
+ tcg/tci/tcg-target.c.inc     | 6 ++----
- tcg/tci/tcg-target.c.inc     |  1 -
+files changed, 12 insertions(+), 36 deletions(-)
-files changed, 4 insertions(+), 49 deletions(-)
 diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/tcg/tcg.h
 +++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
  #define TCG_CT_ALIAS  0x80
  #define TCG_CT_IALIAS 0x40
  #define TCG_CT_NEWREG 0x20 /* output requires a new register */
 -#define TCG_CT_REG    0x01
  #define TCG_CT_CONST  0x02 /* any constant of register size */
  typedef struct TCGArgConstraint {
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tcg.c
 +++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
- /* we give more priority to constraints with less registers */
+ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
- static int get_constraint_priority(const TCGOpDef *def, int k)
+                         TCGReg base, intptr_t ofs);
- {
+ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target);
--    const TCGArgConstraint *arg_ct;
+-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-+    const TCGArgConstraint *arg_ct = &def->args_ct[k];
+-                                  const TCGArgConstraint *arg_ct);
-+    int n;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct);
+ #ifdef TCG_TARGET_NEED_LDST_LABELS
--    int i, n;
+ static int tcg_out_ldst_finalize(TCGContext *s);
--    arg_ct = &def->args_ct[k];
+ #endif
-     if (arg_ct->ct & TCG_CT_ALIAS) {
+@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-         /* an alias is equivalent to a single register */
+         ts = arg_temp(arg);
-         n = 1;
-     } else {
+         if (ts->val_type == TEMP_VAL_CONST
--        if (!(arg_ct->ct & TCG_CT_REG))
+-            && tcg_target_const_match(ts->val, ts->type, arg_ct)) {
--            return 0;
++            && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) {
--        n = 0;
+             /* constant is OK for instruction */
--        for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
+             const_args[i] = 1;
--            if (tcg_regset_test_reg(arg_ct->regs, i))
+             new_args[i] = ts->val;
 -                n++;
 -        }
 +        n = ctpop64(arg_ct->regs);
      }
      return TCG_TARGET_NB_REGS - n + 1;
  }
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                          int oarg = *ct_str - '0';
                          tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
                          tcg_debug_assert(oarg < def->nb_oargs);
 -                        tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
 +                        tcg_debug_assert(def->args_ct[oarg].regs != 0);
                          /* TCG_CT_ALIAS is for the output arguments.
                             The input is tagged with TCG_CT_IALIAS. */
                          def->args_ct[i] = def->args_ct[oarg];
 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/aarch64/tcg-target.c.inc
 +++ b/tcg/aarch64/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
- {
+     }
-     switch (*ct_str++) {
+ }
-     case 'r': /* general registers */
--        ct->ct |= TCG_CT_REG;
+-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-         ct->regs |= 0xffffffffu;
+-                                  const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     case 'w': /* advsimd registers */
+ {
--        ct->ct |= TCG_CT_REG;
+-    int ct = arg_ct->ct;
-         ct->regs |= 0xffffffff00000000ull;
+-
-         break;
+     if (ct & TCG_CT_CONST) {
-     case 'l': /* qemu_ld / qemu_st address, data_reg */
+         return 1;
--        ct->ct |= TCG_CT_REG;
+     }
          ct->regs = 0xffffffffu;
  #ifdef CONFIG_SOFTMMU
          /* x0 and x1 will be overwritten when reading the tlb entry,
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
-         break;
+  * mov operand2:     values represented with x << (2 * y), x < 0x100
+  * add, sub, eor...: ditto
-     case 'r':
+  */
--        ct->ct |= TCG_CT_REG;
+-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-         ct->regs = 0xffff;
+-                                         const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
+ {
-     /* qemu_ld address */
+-    int ct;
-     case 'l':
+-    ct = arg_ct->ct;
--        ct->ct |= TCG_CT_REG;
+     if (ct & TCG_CT_CONST) {
-         ct->regs = 0xffff;
+         return 1;
- #ifdef CONFIG_SOFTMMU
+     } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
          /* r0-r2,lr will be overwritten when reading the tlb entry,
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      /* qemu_st address & data */
      case 's':
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0xffff;
          /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
             and r0-r1 doing the byte swapping, so don't use these. */
 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.c.inc
 +++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- {
+ }
-     switch(*ct_str++) {
-     case 'a':
+ /* test if a constant matches the constraint */
--        ct->ct |= TCG_CT_REG;
+-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-         tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
+-                                         const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     case 'b':
+ {
--        ct->ct |= TCG_CT_REG;
+-    int ct = arg_ct->ct;
-         tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
+     if (ct & TCG_CT_CONST) {
-         break;
+         return 1;
-     case 'c':
+     }
 -        ct->ct |= TCG_CT_REG;
          tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
          break;
      case 'd':
 -        ct->ct |= TCG_CT_REG;
          tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
          break;
      case 'S':
 -        ct->ct |= TCG_CT_REG;
          tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
          break;
      case 'D':
 -        ct->ct |= TCG_CT_REG;
          tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
          break;
      case 'q':
          /* A register that can be used as a byte operand.  */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
          break;
      case 'Q':
          /* A register with an addressable second byte (e.g. %ah).  */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0xf;
          break;
      case 'r':
          /* A general register.  */
 -        ct->ct |= TCG_CT_REG;
          ct->regs |= ALL_GENERAL_REGS;
          break;
      case 'W':
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
          break;
      case 'x':
          /* A vector register.  */
 -        ct->ct |= TCG_CT_REG;
          ct->regs |= ALL_VECTOR_REGS;
          break;
          /* qemu_ld/st address constraint */
      case 'L':
 -        ct->ct |= TCG_CT_REG;
          ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
          tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
          tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/mips/tcg-target.c.inc
 +++ b/tcg/mips/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static inline bool is_p2m1(tcg_target_long val)
- {
+ }
-     switch(*ct_str++) {
-     case 'r':
+ /* test if a constant matches the constraint */
--        ct->ct |= TCG_CT_REG;
+-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-         ct->regs = 0xffffffff;
+-                                         const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     case 'L': /* qemu_ld input arg constraint */
+ {
--        ct->ct |= TCG_CT_REG;
+-    int ct;
-         ct->regs = 0xffffffff;
+-    ct = arg_ct->ct;
-         tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
+     if (ct & TCG_CT_CONST) {
- #if defined(CONFIG_SOFTMMU)
+         return 1;
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
  #endif
          break;
      case 'S': /* qemu_st constraint */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0xffffffff;
          tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
  #if defined(CONFIG_SOFTMMU)
 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.c.inc
 +++ b/tcg/ppc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
- {
+ }
-     switch (*ct_str++) {
-     case 'A': case 'B': case 'C': case 'D':
+ /* test if a constant matches the constraint */
--        ct->ct |= TCG_CT_REG;
+-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-         tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
+-                                  const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     case 'r':
+ {
--        ct->ct |= TCG_CT_REG;
+-    int ct = arg_ct->ct;
-         ct->regs = 0xffffffff;
+     if (ct & TCG_CT_CONST) {
-         break;
+         return 1;
-     case 'v':
+     }
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0xffffffff00000000ull;
          break;
      case 'L':                   /* qemu_ld constraint */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0xffffffff;
          tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
  #ifdef CONFIG_SOFTMMU
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
  #endif
          break;
      case 'S':                   /* qemu_st constraint */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0xffffffff;
          tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
  #ifdef CONFIG_SOFTMMU
 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/riscv/tcg-target.c.inc
 +++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
- {
+ }
-     switch (*ct_str++) {
-     case 'r':
+ /* test if a constant matches the constraint */
--        ct->ct |= TCG_CT_REG;
+-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-         ct->regs = 0xffffffff;
+-                                  const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     case 'L':
+ {
-         /* qemu_ld/qemu_st constraint */
+-    int ct = arg_ct->ct;
--        ct->ct |= TCG_CT_REG;
+     if (ct & TCG_CT_CONST) {
-         ct->regs = 0xffffffff;
+         return 1;
-         /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
+     }
  #if defined(CONFIG_SOFTMMU)
 diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/s390/tcg-target.c.inc
 +++ b/tcg/s390/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
- {
+ }
-     switch (*ct_str++) {
-     case 'r':                  /* all registers */
+ /* Test if a constant matches the constraint. */
--        ct->ct |= TCG_CT_REG;
+-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-         ct->regs = 0xffff;
+-                                  const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     case 'L':                  /* qemu_ld/st constraint */
+ {
--        ct->ct |= TCG_CT_REG;
+-    int ct = arg_ct->ct;
-         ct->regs = 0xffff;
+-
-         tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
+     if (ct & TCG_CT_CONST) {
-         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
+         return 1;
-         tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
+     }
          break;
      case 'a':                  /* force R2 for division */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0;
          tcg_regset_set_reg(ct->regs, TCG_REG_R2);
          break;
      case 'b':                  /* force R3 for division */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0;
          tcg_regset_set_reg(ct->regs, TCG_REG_R3);
          break;
 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/sparc/tcg-target.c.inc
 +++ b/tcg/sparc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
- {
+ }
-     switch (*ct_str++) {
-     case 'r':
+ /* test if a constant matches the constraint */
--        ct->ct |= TCG_CT_REG;
+-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-         ct->regs = 0xffffffff;
+-                                         const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     case 'R':
+ {
--        ct->ct |= TCG_CT_REG;
+-    int ct = arg_ct->ct;
-         ct->regs = ALL_64;
+-
-         break;
+     if (ct & TCG_CT_CONST) {
-     case 'A': /* qemu_ld/st address constraint */
+         return 1;
--        ct->ct |= TCG_CT_REG;
+     }
          ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
      reserve_helpers:
          tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
          tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
          break;
      case 's': /* qemu_st data 32-bit constraint */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = 0xffffffff;
          goto reserve_helpers;
      case 'S': /* qemu_st data 64-bit constraint */
 -        ct->ct |= TCG_CT_REG;
          ct->regs = ALL_64;
          goto reserve_helpers;
      case 'I':
 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tci/tcg-target.c.inc
 +++ b/tcg/tci/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
-     case 'r':
+ }
-     case 'L':                   /* qemu_ld constraint */
-     case 'S':                   /* qemu_st constraint */
+ /* Test if a constant matches the constraint. */
--        ct->ct |= TCG_CT_REG;
+-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-         ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
+-                                  const TCGArgConstraint *arg_ct)
-         break;
++static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-     default:
+ {
 -    /* No need to return 0 or 1, 0 or != 0 is good enough. */
 -    return arg_ct->ct & TCG_CT_CONST;
 +    return ct & TCG_CT_CONST;
  }
  static void tcg_target_init(TCGContext *s)
 --
 .25.1

-[PULL 03/11] tcg: Move sorted_args into TCGArgConstraint.sort_index
+[PULL 02/15] tcg/arm: Add host vector framework
-This uses an existing hole in the TCGArgConstraint structure
+Add registers and function stubs.  The functionality
-and will be convenient for keeping the data in one place.
+is disabled via use_neon_instructions defined to 0.
 We must still include results for the mandatory opcodes in
 tcg_target_op_def, as all opcodes are checked during tcg init.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/tcg/tcg.h |  2 +-
+ tcg/arm/tcg-target-con-set.h |   4 ++
- tcg/tcg.c         | 35 +++++++++++++++++------------------
+ tcg/arm/tcg-target-con-str.h |   1 +
-files changed, 18 insertions(+), 19 deletions(-)
+ tcg/arm/tcg-target.h         |  48 ++++++++++++--
+ tcg/arm/tcg-target.opc.h     |  12 ++++
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
+ tcg/arm/tcg-target.c.inc     | 117 +++++++++++++++++++++++++++++------
 files changed, 158 insertions(+), 24 deletions(-)
  create mode 100644 tcg/arm/tcg-target.opc.h
 diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
+--- a/tcg/arm/tcg-target-con-set.h
-+++ b/include/tcg/tcg.h
++++ b/tcg/arm/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
+@@ -XXX,XX +XXX,XX @@ C_O0_I1(r)
- typedef struct TCGArgConstraint {
+ C_O0_I2(r, r)
-     uint16_t ct;
+ C_O0_I2(r, rIN)
-     uint8_t alias_index;
+ C_O0_I2(s, s)
-+    uint8_t sort_index;
++C_O0_I2(w, r)
-     TCGRegSet regs;
+ C_O0_I3(s, s, s)
- } TCGArgConstraint;
+ C_O0_I4(r, r, rI, rI)
+ C_O0_I4(s, s, s, s)
-@@ -XXX,XX +XXX,XX @@ typedef struct TCGOpDef {
+ C_O1_I1(r, l)
-     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
+ C_O1_I1(r, r)
-     uint8_t flags;
++C_O1_I1(w, r)
-     TCGArgConstraint *args_ct;
++C_O1_I1(w, wr)
--    int *sorted_args;
+ C_O1_I2(r, 0, rZ)
- #if defined(CONFIG_DEBUG_TCG)
+ C_O1_I2(r, l, l)
-     int used;
+ C_O1_I2(r, r, r)
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
  C_O1_I2(r, r, rIN)
  C_O1_I2(r, r, ri)
  C_O1_I2(r, rZ, rZ)
 +C_O1_I2(w, w, w)
  C_O1_I4(r, r, r, rI, rI)
  C_O1_I4(r, r, rIN, rIK, 0)
  C_O2_I1(r, r, l)
 diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target-con-str.h
 +++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
  REGS('r', ALL_GENERAL_REGS)
  REGS('l', ALL_QLOAD_REGS)
  REGS('s', ALL_QSTORE_REGS)
 +REGS('w', ALL_VECTOR_REGS)
  /*
   * Define constraint letters for constants:
 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.h
 +++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
      TCG_REG_R13,
      TCG_REG_R14,
      TCG_REG_PC,
 +
 +    TCG_REG_Q0,
 +    TCG_REG_Q1,
 +    TCG_REG_Q2,
 +    TCG_REG_Q3,
 +    TCG_REG_Q4,
 +    TCG_REG_Q5,
 +    TCG_REG_Q6,
 +    TCG_REG_Q7,
 +    TCG_REG_Q8,
 +    TCG_REG_Q9,
 +    TCG_REG_Q10,
 +    TCG_REG_Q11,
 +    TCG_REG_Q12,
 +    TCG_REG_Q13,
 +    TCG_REG_Q14,
 +    TCG_REG_Q15,
 +
 +    TCG_AREG0 = TCG_REG_R6,
 +    TCG_REG_CALL_STACK = TCG_REG_R13,
  } TCGReg;
 -#define TCG_TARGET_NB_REGS 16
 +#define TCG_TARGET_NB_REGS 32
  #ifdef __ARM_ARCH_EXT_IDIV__
  #define use_idiv_instructions  1
  #else
  extern bool use_idiv_instructions;
  #endif
-diff --git a/tcg/tcg.c b/tcg/tcg.c
+-
 +#define use_neon_instructions  0
  /* used for function call generation */
 -#define TCG_REG_CALL_STACK        TCG_REG_R13
  #define TCG_TARGET_STACK_ALIGN        8
  #define TCG_TARGET_CALL_ALIGN_ARGS    1
  #define TCG_TARGET_CALL_STACK_OFFSET    0
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
  #define TCG_TARGET_HAS_direct_jump      0
  #define TCG_TARGET_HAS_qemu_st8_i32     0
 -enum {
 -    TCG_AREG0 = TCG_REG_R6,
 -};
 +#define TCG_TARGET_HAS_v64              use_neon_instructions
 +#define TCG_TARGET_HAS_v128             use_neon_instructions
 +#define TCG_TARGET_HAS_v256             0
 +
 +#define TCG_TARGET_HAS_andc_vec         0
 +#define TCG_TARGET_HAS_orc_vec          0
 +#define TCG_TARGET_HAS_not_vec          0
 +#define TCG_TARGET_HAS_neg_vec          0
 +#define TCG_TARGET_HAS_abs_vec          0
 +#define TCG_TARGET_HAS_roti_vec         0
 +#define TCG_TARGET_HAS_rots_vec         0
 +#define TCG_TARGET_HAS_rotv_vec         0
 +#define TCG_TARGET_HAS_shi_vec          0
 +#define TCG_TARGET_HAS_shs_vec          0
 +#define TCG_TARGET_HAS_shv_vec          0
 +#define TCG_TARGET_HAS_mul_vec          0
 +#define TCG_TARGET_HAS_sat_vec          0
 +#define TCG_TARGET_HAS_minmax_vec       0
 +#define TCG_TARGET_HAS_bitsel_vec       0
 +#define TCG_TARGET_HAS_cmpsel_vec       0
  #define TCG_TARGET_DEFAULT_MO (0)
  #define TCG_TARGET_HAS_MEMORY_BSWAP     1
 diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tcg/arm/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Copyright (c) 2019 Linaro
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or
 + * (at your option) any later version.
 + *
 + * See the COPYING file in the top-level directory for details.
 + *
 + * Target-specific opcodes for host vector expansion.  These will be
 + * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
 + * consider these to be UNSPEC with names.
 + */
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
+--- a/tcg/arm/tcg-target.c.inc
-+++ b/tcg/tcg.c
++++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
+@@ -XXX,XX +XXX,XX @@ bool use_idiv_instructions;
-     int op, total_args, n, i;
-     TCGOpDef *def;
+ #ifdef CONFIG_DEBUG_TCG
-     TCGArgConstraint *args_ct;
+ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
--    int *sorted_args;
+-    "%r0",
-     TCGTemp *ts;
+-    "%r1",
+-    "%r2",
-     memset(s, 0, sizeof(*s));
+-    "%r3",
-@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
+-    "%r4",
 -    "%r5",
 -    "%r6",
 -    "%r7",
 -    "%r8",
 -    "%r9",
 -    "%r10",
 -    "%r11",
 -    "%r12",
 -    "%r13",
 -    "%r14",
 -    "%pc",
 +    "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
 +    "%r8",  "%r9",  "%r10", "%r11", "%r12", "%sp",  "%r14", "%pc",
 +    "%q0",  "%q1",  "%q2",  "%q3",  "%q4",  "%q5",  "%q6",  "%q7",
 +    "%q8",  "%q9",  "%q10", "%q11", "%q12", "%q13", "%q14", "%q15",
  };
  #endif
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
      TCG_REG_R3,
      TCG_REG_R12,
      TCG_REG_R14,
 +
 +    TCG_REG_Q0,
 +    TCG_REG_Q1,
 +    TCG_REG_Q2,
 +    TCG_REG_Q3,
 +    /* Q4 - Q7 are call-saved, and skipped. */
 +    TCG_REG_Q8,
 +    TCG_REG_Q9,
 +    TCG_REG_Q10,
 +    TCG_REG_Q11,
 +    TCG_REG_Q12,
 +    TCG_REG_Q13,
 +    TCG_REG_Q14,
 +    TCG_REG_Q15,
  };
  static const int tcg_target_call_iarg_regs[4] = {
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[2] = {
  };
  #define TCG_REG_TMP  TCG_REG_R12
 +#define TCG_VEC_TMP  TCG_REG_Q15
  enum arm_cond_code_e {
      COND_EQ = 0x0,
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
  #define TCG_CT_CONST_ZERO 0x800
  #define ALL_GENERAL_REGS  0xffffu
 +#define ALL_VECTOR_REGS   0xffff0000u
  /*
   * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_qemu_st_i64:
          return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
 +    case INDEX_op_st_vec:
 +        return C_O0_I2(w, r);
 +    case INDEX_op_ld_vec:
 +    case INDEX_op_dupm_vec:
 +        return C_O1_I1(w, r);
 +    case INDEX_op_dup_vec:
 +        return C_O1_I1(w, wr);
 +    case INDEX_op_dup2_vec:
 +    case INDEX_op_add_vec:
 +    case INDEX_op_sub_vec:
 +    case INDEX_op_xor_vec:
 +    case INDEX_op_or_vec:
 +    case INDEX_op_and_vec:
 +    case INDEX_op_cmp_vec:
 +        return C_O1_I2(w, w, w);
 +
      default:
          g_assert_not_reached();
      }
+@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
-     args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
+ {
--    sorted_args = g_malloc(sizeof(int) * total_args);
+     /* Only probe for the platform and capabilities if we havn't already
+        determined maximum values at compile time.  */
-     for(op = 0; op < NB_OPS; op++) {
+-#ifndef use_idiv_instructions
-         def = &tcg_op_defs[op];
++#if !defined(use_idiv_instructions) || !defined(use_neon_instructions)
-         def->args_ct = args_ct;
+     {
--        def->sorted_args = sorted_args;
+         unsigned long hwcap = qemu_getauxval(AT_HWCAP);
-         n = def->nb_iargs + def->nb_oargs;
++#ifndef use_idiv_instructions
--        sorted_args += n;
+         use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
-         args_ct += n;
++#endif
 +#ifndef use_neon_instructions
 +        use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0;
 +#endif
      }
+ #endif
-@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
++
- /* sort from highest priority to lowest */
+     if (__ARM_ARCH < 7) {
- static void sort_constraints(TCGOpDef *def, int start, int n)
+         const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
- {
+         if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
--    int i, j, p1, p2, tmp;
+@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
 +    int i, j;
 +    TCGArgConstraint *a = def->args_ct;
 -    for(i = 0; i < n; i++)
 -        def->sorted_args[start + i] = start + i;
 -    if (n <= 1)
 +    for (i = 0; i < n; i++) {
 +        a[start + i].sort_index = start + i;
 +    }
 +    if (n <= 1) {
          return;
 -    for(i = 0; i < n - 1; i++) {
 -        for(j = i + 1; j < n; j++) {
 -            p1 = get_constraint_priority(def, def->sorted_args[start + i]);
 -            p2 = get_constraint_priority(def, def->sorted_args[start + j]);
 +    }
 +    for (i = 0; i < n - 1; i++) {
 +        for (j = i + 1; j < n; j++) {
 +            int p1 = get_constraint_priority(def, a[start + i].sort_index);
 +            int p2 = get_constraint_priority(def, a[start + j].sort_index);
              if (p1 < p2) {
 -                tmp = def->sorted_args[start + i];
 -                def->sorted_args[start + i] = def->sorted_args[start + j];
 -                def->sorted_args[start + j] = tmp;
 +                int tmp = a[start + i].sort_index;
 +                a[start + i].sort_index = a[start + j].sort_index;
 +                a[start + j].sort_index = tmp;
              }
          }
      }
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-     for (k = 0; k < nb_iargs; k++) {
+-    tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
-         TCGRegSet i_preferred_regs, o_preferred_regs;
++    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
--        i = def->sorted_args[nb_oargs + k];
+     tcg_target_call_clobber_regs = 0;
-+        i = def->args_ct[nb_oargs + k].sort_index;
+     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
-         arg = op->args[i];
+@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
-         arg_ct = &def->args_ct[i];
+     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
-         ts = arg_temp(arg);
+     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-                     int k2, i2;
++    if (use_neon_instructions) {
-                     reg = ts->reg;
++        tcg_target_available_regs[TCG_TYPE_V64]  = ALL_VECTOR_REGS;
-                     for (k2 = 0 ; k2 < k ; k2++) {
++        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
--                        i2 = def->sorted_args[nb_oargs + k2];
++
-+                        i2 = def->args_ct[nb_oargs + k2].sort_index;
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
-                         if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
-                             reg == new_args[i2]) {
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
-                             goto allocate_in_reg;
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8);
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9);
-         /* satisfy the output constraints */
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10);
-         for(k = 0; k < nb_oargs; k++) {
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11);
--            i = def->sorted_args[k];
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12);
-+            i = def->args_ct[k].sort_index;
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13);
-             arg = op->args[i];
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14);
-             arg_ct = &def->args_ct[i];
++        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15);
-             ts = arg_temp(arg);
++    }
 +
      s->reserved_regs = 0;
      tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
      tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
      tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
 +    tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
  }
  static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
      tcg_out_movi32(s, COND_AL, ret, arg);
  }
 +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
 +                            TCGReg rd, TCGReg rs)
 +{
 +    g_assert_not_reached();
 +}
 +
 +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
 +                             TCGReg rd, TCGReg base, intptr_t offset)
 +{
 +    g_assert_not_reached();
 +}
 +
 +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
 +                             TCGReg rd, int64_t v64)
 +{
 +    g_assert_not_reached();
 +}
 +
 +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
 +                           unsigned vecl, unsigned vece,
 +                           const TCGArg *args, const int *const_args)
 +{
 +    g_assert_not_reached();
 +}
 +
 +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 +{
 +    return 0;
 +}
 +
 +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
 +                       TCGArg a0, ...)
 +{
 +    g_assert_not_reached();
 +}
 +
  static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
  {
      int i;
 --
 .25.1

-New patch
+[PULL 03/15] tcg/arm: Implement tcg_out_ld/st for vector types
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++----
+file changed, 64 insertions(+), 6 deletions(-)
+diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/arm/tcg-target.c.inc
++++ b/tcg/arm/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ typedef enum {
+     INSN_NOP_v6k   = 0xe320f000,
+     /* Otherwise the assembler uses mov r0,r0 */
+     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
++
++    INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
++    INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
+ } ARMInsn;
+ #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
+@@ -XXX,XX +XXX,XX @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
+     }
+ }
++/*
++ * Note that TCGReg references Q-registers.
++ * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
++ */
++static uint32_t encode_vd(TCGReg rd)
++{
++    tcg_debug_assert(rd >= TCG_REG_Q0);
++    return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
++}
++
++static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
++                          TCGReg rd, TCGReg rn, int offset)
++{
++    if (offset != 0) {
++        if (check_fit_imm(offset) || check_fit_imm(-offset)) {
++            tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
++                            TCG_REG_TMP, rn, offset, true);
++        } else {
++            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
++            tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
++                            TCG_REG_TMP, TCG_REG_TMP, rn, 0);
++        }
++        rn = TCG_REG_TMP;
++    }
++    tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
++}
++
+ #ifdef CONFIG_SOFTMMU
+ #include "../tcg-ldst.c.inc"
+@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
+     tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
+ }
+-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+-                              TCGReg arg1, intptr_t arg2)
++static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
++                       TCGReg arg1, intptr_t arg2)
+ {
+-    tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
++    switch (type) {
++    case TCG_TYPE_I32:
++        tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
++        return;
++    case TCG_TYPE_V64:
++        /* regs 1; size 8; align 8 */
++        tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
++        return;
++    case TCG_TYPE_V128:
++        /* regs 2; size 8; align 16 */
++        tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2);
++        return;
++    default:
++        g_assert_not_reached();
++    }
+ }
+-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+-                              TCGReg arg1, intptr_t arg2)
++static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
++                       TCGReg arg1, intptr_t arg2)
+ {
+-    tcg_out_st32(s, COND_AL, arg, arg1, arg2);
++    switch (type) {
++    case TCG_TYPE_I32:
++        tcg_out_st32(s, COND_AL, arg, arg1, arg2);
++        return;
++    case TCG_TYPE_V64:
++        /* regs 1; size 8; align 8 */
++        tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
++        return;
++    case TCG_TYPE_V128:
++        /* regs 2; size 8; align 16 */
++        tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2);
++        return;
++    default:
++        g_assert_not_reached();
++    }
+ }
+ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+--
+.25.1

-[PULL 11/11] accel/tcg: Fix computing of is_write for MIPS
+[PULL 04/15] tcg/arm: Implement tcg_out_mov for vector types
-From: Kele Huang <kele.hwang@gmail.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Detect all MIPS store instructions in cpu_signal_handler for all available
 MIPS versions, and set is_write if encountering such store instructions.
 This fixed the error while dealing with self-modified code for MIPS.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Kele Huang <kele.hwang@gmail.com>
 Signed-off-by: Xu Zou <iwatchnima@gmail.com>
 Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>
 [rth: Use uintptr_t for pc to fix n32 build error.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/user-exec.c | 43 +++++++++++++++++++++++++++++++++++++++----
+ tcg/arm/tcg-target.c.inc | 52 +++++++++++++++++++++++++++++++++++-----
-file changed, 39 insertions(+), 4 deletions(-)
+file changed, 46 insertions(+), 6 deletions(-)
-diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
+diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/user-exec.c
+--- a/tcg/arm/tcg-target.c.inc
-+++ b/accel/tcg/user-exec.c
++++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
+@@ -XXX,XX +XXX,XX @@ typedef enum {
+     /* Otherwise the assembler uses mov r0,r0 */
- #elif defined(__mips__)
+     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
-+#if defined(__misp16) || defined(__mips_micromips)
++    INSN_VORR      = 0xf2200110,
 +#error "Unsupported encoding"
 +#endif
 +
- int cpu_signal_handler(int host_signum, void *pinfo,
+     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
-                        void *puc)
+     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
  } ARMInsn;
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vd(TCGReg rd)
      return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
  }
 +static uint32_t encode_vn(TCGReg rn)
 +{
 +    tcg_debug_assert(rn >= TCG_REG_Q0);
 +    return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
 +}
 +
 +static uint32_t encode_vm(TCGReg rm)
 +{
 +    tcg_debug_assert(rm >= TCG_REG_Q0);
 +    return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
 +}
 +
 +static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
 +                          TCGReg d, TCGReg n, TCGReg m)
 +{
 +    tcg_out32(s, insn | (vece << 20) | (q << 6) |
 +              encode_vd(d) | encode_vn(n) | encode_vm(m));
 +}
 +
  static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                            TCGReg rd, TCGReg rn, int offset)
  {
-     siginfo_t *info = pinfo;
+@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
-     ucontext_t *uc = puc;
+     return false;
--    greg_t pc = uc->uc_mcontext.pc;
+ }
--    int is_write;
-+    uintptr_t pc = uc->uc_mcontext.pc;
+-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
-+    uint32_t insn = *(uint32_t *)pc;
+-                               TCGReg ret, TCGReg arg)
-+    int is_write = 0;
++static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
  {
 -    tcg_out_mov_reg(s, COND_AL, ret, arg);
 -    return true;
 +    if (ret == arg) {
 +        return true;
 +    }
 +    switch (type) {
 +    case TCG_TYPE_I32:
 +        if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
 +            tcg_out_mov_reg(s, COND_AL, ret, arg);
 +            return true;
 +        }
 +        return false;
 +
-+    /* Detect all store instructions at program counter. */
++    case TCG_TYPE_V64:
-+    switch((insn >> 26) & 077) {
++    case TCG_TYPE_V128:
-+    case 050: /* SB */
++        /* "VMOV D,N" is an alias for "VORR D,N,N". */
-+    case 051: /* SH */
++        tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
-+    case 052: /* SWL */
++        return true;
-+    case 053: /* SW */
++
-+    case 054: /* SDL */
++    default:
-+    case 055: /* SDR */
++        g_assert_not_reached();
 +    case 056: /* SWR */
 +    case 070: /* SC */
 +    case 071: /* SWC1 */
 +    case 074: /* SCD */
 +    case 075: /* SDC1 */
 +    case 077: /* SD */
 +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
 +    case 072: /* SWC2 */
 +    case 076: /* SDC2 */
 +#endif
 +        is_write = 1;
 +        break;
 +    case 023: /* COP1X */
 +        /* Required in all versions of MIPS64 since
 +           MIPS64r1 and subsequent versions of MIPS32r2. */
 +        switch (insn & 077) {
 +        case 010: /* SWXC1 */
 +        case 011: /* SDXC1 */
 +        case 015: /* SUXC1 */
 +            is_write = 1;
 +        }
 +        break;
 +    }
--    /* XXX: compute is_write */
--    is_write = 0;
-     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
  }
+-static inline void tcg_out_movi(TCGContext *s, TCGType type,
+-                                TCGReg ret, tcg_target_long arg)
++static void tcg_out_movi(TCGContext *s, TCGType type,
++                         TCGReg ret, tcg_target_long arg)
+ {
++    tcg_debug_assert(type == TCG_TYPE_I32);
++    tcg_debug_assert(ret < TCG_REG_Q0);
+     tcg_out_movi32(s, COND_AL, ret, arg);
+ }
 --
 .25.1

-New patch
+[PULL 05/15] tcg/arm: Implement tcg_out_dup*_vec
+Most of dupi is copied from tcg/aarch64, which has the same
+encoding for AdvSimdExpandImm.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/arm/tcg-target.c.inc | 283 +++++++++++++++++++++++++++++++++++++--
+file changed, 275 insertions(+), 8 deletions(-)
+diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/arm/tcg-target.c.inc
++++ b/tcg/arm/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ typedef enum {
+     INSN_VORR      = 0xf2200110,
++    INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
++    INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
++    INSN_VLDR_D    = 0xed100b00,  /* VLDR.64 */
+     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
++    INSN_VLD1R     = 0xf4a00c00,  /* VLD1 (single element to all lanes) */
+     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
++    INSN_VMOVI     = 0xf2800010,  /* VMOV (immediate) */
+ } ARMInsn;
+ #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
+@@ -XXX,XX +XXX,XX @@ static const uint8_t tcg_cond_to_arm_cond[] = {
+     [TCG_COND_GTU] = COND_HI,
+ };
++static int encode_imm(uint32_t imm);
++
++/* TCG private relocation type: add with pc+imm8 */
++#define R_ARM_PC8  11
++
++/* TCG private relocation type: vldr with imm8 << 2 */
++#define R_ARM_PC11 12
++
+ static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+ {
+     const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+@@ -XXX,XX +XXX,XX @@ static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+     return false;
+ }
++static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
++{
++    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
++    ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
++
++    if (offset >= -0xff && offset <= 0xff) {
++        tcg_insn_unit insn = *src_rw;
++        bool u = (offset >= 0);
++        if (!u) {
++            offset = -offset;
++        }
++        insn = deposit32(insn, 23, 1, u);
++        insn = deposit32(insn, 0, 8, offset);
++        *src_rw = insn;
++        return true;
++    }
++    return false;
++}
++
++static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
++{
++    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
++    ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
++    int rot = encode_imm(offset);
++
++    if (rot >= 0) {
++        *src_rw = deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot << 7));
++        return true;
++    }
++    return false;
++}
++
+ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+                         intptr_t value, intptr_t addend)
+ {
+     tcg_debug_assert(addend == 0);
+-
+-    if (type == R_ARM_PC24) {
++    switch (type) {
++    case R_ARM_PC24:
+         return reloc_pc24(code_ptr, (const tcg_insn_unit *)value);
+-    } else if (type == R_ARM_PC13) {
++    case R_ARM_PC13:
+         return reloc_pc13(code_ptr, (const tcg_insn_unit *)value);
+-    } else {
++    case R_ARM_PC11:
++        return reloc_pc11(code_ptr, (const tcg_insn_unit *)value);
++    case R_ARM_PC8:
++        return reloc_pc8(code_ptr, (const tcg_insn_unit *)value);
++    default:
+         g_assert_not_reached();
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t rotl(uint32_t val, int n)
+ /* ARM immediates for ALU instructions are made of an unsigned 8-bit
+    right-rotated by an even amount between 0 and 30. */
+-static inline int encode_imm(uint32_t imm)
++static int encode_imm(uint32_t imm)
+ {
+     int shift;
+@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
+     return encode_imm(imm) >= 0;
+ }
++/* Return true if v16 is a valid 16-bit shifted immediate.  */
++static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
++{
++    if (v16 == (v16 & 0xff)) {
++        *cmode = 0x8;
++        *imm8 = v16 & 0xff;
++        return true;
++    } else if (v16 == (v16 & 0xff00)) {
++        *cmode = 0xa;
++        *imm8 = v16 >> 8;
++        return true;
++    }
++    return false;
++}
++
++/* Return true if v32 is a valid 32-bit shifted immediate.  */
++static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
++{
++    if (v32 == (v32 & 0xff)) {
++        *cmode = 0x0;
++        *imm8 = v32 & 0xff;
++        return true;
++    } else if (v32 == (v32 & 0xff00)) {
++        *cmode = 0x2;
++        *imm8 = (v32 >> 8) & 0xff;
++        return true;
++    } else if (v32 == (v32 & 0xff0000)) {
++        *cmode = 0x4;
++        *imm8 = (v32 >> 16) & 0xff;
++        return true;
++    } else if (v32 == (v32 & 0xff000000)) {
++        *cmode = 0x6;
++        *imm8 = v32 >> 24;
++        return true;
++    }
++    return false;
++}
++
++/* Return true if v32 is a valid 32-bit shifting ones immediate.  */
++static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
++{
++    if ((v32 & 0xffff00ff) == 0xff) {
++        *cmode = 0xc;
++        *imm8 = (v32 >> 8) & 0xff;
++        return true;
++    } else if ((v32 & 0xff00ffff) == 0xffff) {
++        *cmode = 0xd;
++        *imm8 = (v32 >> 16) & 0xff;
++        return true;
++    }
++    return false;
++}
++
++/*
++ * Return non-zero if v32 can be formed by MOVI+ORR.
++ * Place the parameters for MOVI in (cmode, imm8).
++ * Return the cmode for ORR; the imm8 can be had via extraction from v32.
++ */
++static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
++{
++    int i;
++
++    for (i = 6; i > 0; i -= 2) {
++        /* Mask out one byte we can add with ORR.  */
++        uint32_t tmp = v32 & ~(0xffu << (i * 4));
++        if (is_shimm32(tmp, cmode, imm8) ||
++            is_soimm32(tmp, cmode, imm8)) {
++            break;
++        }
++    }
++    return i;
++}
++
+ /* Test if a constant matches the constraint.
+  * TODO: define constraints for:
+  *
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
+               encode_vd(d) | encode_vn(n) | encode_vm(m));
+ }
++static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
++                          int q, int op, int cmode, uint8_t imm8)
++{
++    tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
++              | (cmode << 8) | extract32(imm8, 0, 4)
++              | (extract32(imm8, 4, 3) << 16)
++              | (extract32(imm8, 7, 1) << 24));
++}
++
+ static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+                           TCGReg rd, TCGReg rn, int offset)
+ {
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type,
+     tcg_out_movi32(s, COND_AL, ret, arg);
+ }
++/* Type is always V128, with I64 elements.  */
++static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
++{
++    /* Move high element into place first. */
++    /* VMOV Dd+1, Ds */
++    tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);
++    /* Move low element into place; tcg_out_mov will check for nop. */
++    tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
++}
++
+ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+                             TCGReg rd, TCGReg rs)
+ {
+-    g_assert_not_reached();
++    int q = type - TCG_TYPE_V64;
++
++    if (vece == MO_64) {
++        if (type == TCG_TYPE_V128) {
++            tcg_out_dup2_vec(s, rd, rs, rs);
++        } else {
++            tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
++        }
++    } else if (rs < TCG_REG_Q0) {
++        int b = (vece == MO_8);
++        int e = (vece == MO_16);
++        tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
++                  encode_vn(rd) | (rs << 12));
++    } else {
++        int imm4 = 1 << vece;
++        tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
++                  encode_vd(rd) | encode_vm(rs));
++    }
++    return true;
+ }
+ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+                              TCGReg rd, TCGReg base, intptr_t offset)
+ {
+-    g_assert_not_reached();
++    if (vece == MO_64) {
++        tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
++        if (type == TCG_TYPE_V128) {
++            tcg_out_dup2_vec(s, rd, rd, rd);
++        }
++    } else {
++        int q = type - TCG_TYPE_V64;
++        tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
++                      rd, base, offset);
++    }
++    return true;
+ }
+ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+                              TCGReg rd, int64_t v64)
+ {
+-    g_assert_not_reached();
++    int q = type - TCG_TYPE_V64;
++    int cmode, imm8, i;
++
++    /* Test all bytes equal first.  */
++    if (vece == MO_8) {
++        tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
++        return;
++    }
++
++    /*
++     * Test all bytes 0x00 or 0xff second.  This can match cases that
++     * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
++     */
++    for (i = imm8 = 0; i < 8; i++) {
++        uint8_t byte = v64 >> (i * 8);
++        if (byte == 0xff) {
++            imm8 |= 1 << i;
++        } else if (byte != 0) {
++            goto fail_bytes;
++        }
++    }
++    tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
++    return;
++ fail_bytes:
++
++    /*
++     * Tests for various replications.  For each element width, if we
++     * cannot find an expansion there's no point checking a larger
++     * width because we already know by replication it cannot match.
++     */
++    if (vece == MO_16) {
++        uint16_t v16 = v64;
++
++        if (is_shimm16(v16, &cmode, &imm8)) {
++            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
++            return;
++        }
++        if (is_shimm16(~v16, &cmode, &imm8)) {
++            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
++            return;
++        }
++
++        /*
++         * Otherwise, all remaining constants can be loaded in two insns:
++         * rd = v16 & 0xff, rd |= v16 & 0xff00.
++         */
++        tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
++        tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8);   /* VORRI */
++        return;
++    }
++
++    if (vece == MO_32) {
++        uint32_t v32 = v64;
++
++        if (is_shimm32(v32, &cmode, &imm8) ||
++            is_soimm32(v32, &cmode, &imm8)) {
++            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
++            return;
++        }
++        if (is_shimm32(~v32, &cmode, &imm8) ||
++            is_soimm32(~v32, &cmode, &imm8)) {
++            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
++            return;
++        }
++
++        /*
++         * Restrict the set of constants to those we can load with
++         * two instructions.  Others we load from the pool.
++         */
++        i = is_shimm32_pair(v32, &cmode, &imm8);
++        if (i) {
++            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
++            tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8));
++            return;
++        }
++        i = is_shimm32_pair(~v32, &cmode, &imm8);
++        if (i) {
++            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
++            tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8));
++            return;
++        }
++    }
++
++    /*
++     * As a last resort, load from the constant pool.
++     */
++    if (!q || vece == MO_64) {
++        new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
++        /* VLDR Dd, [pc + offset] */
++        tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
++        if (q) {
++            tcg_out_dup2_vec(s, rd, rd, rd);
++        }
++    } else {
++        new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
++        /* add tmp, pc, offset */
++        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
++        tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
++    }
+ }
+ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+--
+.25.1

-[PULL 01/11] tcg: Adjust simd_desc size encoding
+[PULL 06/15] tcg/arm: Implement minimal vector operations
-With larger vector sizes, it turns out oprsz == maxsz, and we only
+Implementing dup2, add, sub, and, or, xor as the minimal set.
-need to represent mismatch for oprsz <= 32.  We do, however, need
+This allows us to actually enable neon in the header file.
 to represent larger oprsz and do so without reducing SIMD_DATA_BITS.
-Reduce the size of the oprsz field and increase the maxsz field.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Steal the oprsz value of 24 to indicate equality with maxsz.
 Tested-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++-------------
+ tcg/arm/tcg-target-con-set.h |   3 +
- tcg/tcg-op-gvec.c           | 35 ++++++++++++++++++++++++++--------
+ tcg/arm/tcg-target-con-str.h |   2 +
-files changed, 52 insertions(+), 21 deletions(-)
+ tcg/arm/tcg-target.h         |   6 +-
  tcg/arm/tcg-target.c.inc     | 201 +++++++++++++++++++++++++++++++++--
 files changed, 204 insertions(+), 8 deletions(-)
-diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h
+diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg-gvec-desc.h
+--- a/tcg/arm/tcg-target-con-set.h
-+++ b/include/tcg/tcg-gvec-desc.h
++++ b/tcg/arm/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIN)
- #ifndef TCG_TCG_GVEC_DESC_H
+ C_O1_I2(r, r, ri)
- #define TCG_TCG_GVEC_DESC_H
+ C_O1_I2(r, rZ, rZ)
+ C_O1_I2(w, w, w)
--/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
++C_O1_I2(w, w, wO)
--#define SIMD_OPRSZ_SHIFT   0
++C_O1_I2(w, w, wV)
--#define SIMD_OPRSZ_BITS    5
++C_O1_I2(w, w, wZ)
-+/*
+ C_O1_I4(r, r, r, rI, rI)
-+ * This configuration allows MAXSZ to represent 2048 bytes, and
+ C_O1_I4(r, r, rIN, rIK, 0)
-+ * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
+ C_O2_I1(r, r, l)
-+ *
+diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
-+ * Encode this with:
+index XXXXXXX..XXXXXXX 100644
-+ *   0, 1, 3 -> 8, 16, 32
+--- a/tcg/arm/tcg-target-con-str.h
-+ *   2       -> maxsz
++++ b/tcg/arm/tcg-target-con-str.h
-+ *
+@@ -XXX,XX +XXX,XX @@ REGS('w', ALL_VECTOR_REGS)
-+ * This steals the input that would otherwise map to 24 to match maxsz.
+ CONST('I', TCG_CT_CONST_ARM)
-+ */
+ CONST('K', TCG_CT_CONST_INV)
-+#define SIMD_MAXSZ_SHIFT   0
+ CONST('N', TCG_CT_CONST_NEG)
-+#define SIMD_MAXSZ_BITS    8
++CONST('O', TCG_CT_CONST_ORRI)
++CONST('V', TCG_CT_CONST_ANDI)
--#define SIMD_MAXSZ_SHIFT   (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
+ CONST('Z', TCG_CT_CONST_ZERO)
--#define SIMD_MAXSZ_BITS    5
+diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
-+#define SIMD_OPRSZ_SHIFT   (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+index XXXXXXX..XXXXXXX 100644
-+#define SIMD_OPRSZ_BITS    2
+--- a/tcg/arm/tcg-target.h
++++ b/tcg/arm/tcg-target.h
--#define SIMD_DATA_SHIFT    (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+@@ -XXX,XX +XXX,XX @@ typedef enum {
-+#define SIMD_DATA_SHIFT    (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
+ #else
- #define SIMD_DATA_BITS     (32 - SIMD_DATA_SHIFT)
+ extern bool use_idiv_instructions;
+ #endif
- /* Create a descriptor from components.  */
+-#define use_neon_instructions  0
- uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
++#ifdef __ARM_NEON__
++#define use_neon_instructions  1
--/* Extract the operation size from a descriptor.  */
++#else
--static inline intptr_t simd_oprsz(uint32_t desc)
++extern bool use_neon_instructions;
--{
++#endif
--    return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
--}
+ /* used for function call generation */
--
+ #define TCG_TARGET_STACK_ALIGN        8
- /* Extract the max vector size from a descriptor.  */
+diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
- static inline intptr_t simd_maxsz(uint32_t desc)
+index XXXXXXX..XXXXXXX 100644
- {
+--- a/tcg/arm/tcg-target.c.inc
--    return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
++++ b/tcg/arm/tcg-target.c.inc
-+    return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
+@@ -XXX,XX +XXX,XX @@ int arm_arch = __ARM_ARCH;
  #ifndef use_idiv_instructions
  bool use_idiv_instructions;
  #endif
 +#ifndef use_neon_instructions
 +bool use_neon_instructions;
 +#endif
  /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined.  */
  #ifdef CONFIG_SOFTMMU
@@ -XXX,XX +XXX,XX @@ typedef enum {
      /* Otherwise the assembler uses mov r0,r0 */
      INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 +    INSN_VADD      = 0xf2000800,
 +    INSN_VAND      = 0xf2000110,
 +    INSN_VEOR      = 0xf3000110,
      INSN_VORR      = 0xf2200110,
 +    INSN_VSUB      = 0xf3000800,
 +
 +    INSN_VMVN      = 0xf3b00580,
 +
 +    INSN_VCEQ0     = 0xf3b10100,
 +    INSN_VCGT0     = 0xf3b10000,
 +    INSN_VCGE0     = 0xf3b10080,
 +    INSN_VCLE0     = 0xf3b10180,
 +    INSN_VCLT0     = 0xf3b10200,
 +
 +    INSN_VCEQ      = 0xf3000810,
 +    INSN_VCGE      = 0xf2000310,
 +    INSN_VCGT      = 0xf2000300,
 +    INSN_VCGE_U    = 0xf3000310,
 +    INSN_VCGT_U    = 0xf3000300,
 +
 +    INSN_VTST      = 0xf2000810,
      INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
      INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
  #define TCG_CT_CONST_INV  0x200
  #define TCG_CT_CONST_NEG  0x400
  #define TCG_CT_CONST_ZERO 0x800
 +#define TCG_CT_CONST_ORRI 0x1000
 +#define TCG_CT_CONST_ANDI 0x2000
  #define ALL_GENERAL_REGS  0xffffu
  #define ALL_VECTOR_REGS   0xffff0000u
@@ -XXX,XX +XXX,XX @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
      return i;
  }
 +/* Return true if V is a valid 16-bit or 32-bit shifted immediate.  */
 +static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
 +{
 +    if (v32 == deposit32(v32, 16, 16, v32)) {
 +        return is_shimm16(v32, cmode, imm8);
 +    } else {
 +        return is_shimm32(v32, cmode, imm8);
 +    }
 +}
 +
-+/* Extract the operation size from a descriptor.  */
+ /* Test if a constant matches the constraint.
-+static inline intptr_t simd_oprsz(uint32_t desc)
+  * TODO: define constraints for:
-+{
+  *
-+    uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
+@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
-+    intptr_t o = f * 8 + 8;
+         return 1;
-+    intptr_t m = simd_maxsz(desc);
+     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
-+    return f == 2 ? m : o;
+         return 1;
- }
+-    } else {
+-        return 0;
- /* Extract the operation-specific data from a descriptor.  */
+     }
-diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
++
-index XXXXXXX..XXXXXXX 100644
++    switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
---- a/tcg/tcg-op-gvec.c
++    case 0:
-+++ b/tcg/tcg-op-gvec.c
++        break;
-@@ -XXX,XX +XXX,XX @@ static const TCGOpcode vecop_list_empty[1] = { 0 };
++    case TCG_CT_CONST_ANDI:
-    of the operand offsets so that we can check them all at once.  */
++        val = ~val;
- static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
++        /* fallthru */
- {
++    case TCG_CT_CONST_ORRI:
--    uint32_t opr_align = oprsz >= 16 ? 15 : 7;
++        if (val == deposit64(val, 32, 32, val)) {
--    uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
++            int cmode, imm8;
--    tcg_debug_assert(oprsz > 0);
++            return is_shimm1632(val, &cmode, &imm8);
--    tcg_debug_assert(oprsz <= maxsz);
++        }
 -    tcg_debug_assert((oprsz & opr_align) == 0);
 +    uint32_t max_align;
 +
 +    switch (oprsz) {
 +    case 8:
 +    case 16:
 +    case 32:
 +        tcg_debug_assert(oprsz <= maxsz);
 +        break;
 +    default:
-+        tcg_debug_assert(oprsz == maxsz);
++        /* Both bits should not be set for the same insn.  */
-+        break;
++        g_assert_not_reached();
 +    }
-+    tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));
++
-+
++    return 0;
-+    max_align = maxsz >= 16 ? 15 : 7;
+ }
-     tcg_debug_assert((maxsz & max_align) == 0);
-     tcg_debug_assert((ofs & max_align) == 0);
+ static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
- }
+@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vm(TCGReg rm)
-@@ -XXX,XX +XXX,XX @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
+     return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
  }
 +static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece,
 +                          TCGReg d, TCGReg m)
 +{
 +    tcg_out32(s, insn | (vece << 18) | (q << 6) |
 +              encode_vd(d) | encode_vm(m));
 +}
 +
  static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
                            TCGReg d, TCGReg n, TCGReg m)
  {
-     uint32_t desc = 0;
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_add_vec:
--    assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
+     case INDEX_op_sub_vec:
--    assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
+     case INDEX_op_xor_vec:
--    assert(data == sextract32(data, 0, SIMD_DATA_BITS));
+-    case INDEX_op_or_vec:
-+    check_size_align(oprsz, maxsz, 0);
+-    case INDEX_op_and_vec:
-+    tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));
+-    case INDEX_op_cmp_vec:
+         return C_O1_I2(w, w, w);
-     oprsz = (oprsz / 8) - 1;
++    case INDEX_op_or_vec:
-     maxsz = (maxsz / 8) - 1;
++        return C_O1_I2(w, w, wO);
-+
++    case INDEX_op_and_vec:
-+    /*
++        return C_O1_I2(w, w, wV);
-+     * We have just asserted in check_size_align that either
++    case INDEX_op_cmp_vec:
-+     * oprsz is {8,16,32} or matches maxsz.  Encode the final
++        return C_O1_I2(w, w, wZ);
-+     * case with '2', as that would otherwise map to 24.
-+     */
+     default:
-+    if (oprsz == maxsz) {
+         g_assert_not_reached();
-+        oprsz = 2;
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
      }
  }
 +static const ARMInsn vec_cmp_insn[16] = {
 +    [TCG_COND_EQ] = INSN_VCEQ,
 +    [TCG_COND_GT] = INSN_VCGT,
 +    [TCG_COND_GE] = INSN_VCGE,
 +    [TCG_COND_GTU] = INSN_VCGT_U,
 +    [TCG_COND_GEU] = INSN_VCGE_U,
 +};
 +
 +static const ARMInsn vec_cmp0_insn[16] = {
 +    [TCG_COND_EQ] = INSN_VCEQ0,
 +    [TCG_COND_GT] = INSN_VCGT0,
 +    [TCG_COND_GE] = INSN_VCGE0,
 +    [TCG_COND_LT] = INSN_VCLT0,
 +    [TCG_COND_LE] = INSN_VCLE0,
 +};
 +
  static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                             unsigned vecl, unsigned vece,
                             const TCGArg *args, const int *const_args)
  {
 -    g_assert_not_reached();
 +    TCGType type = vecl + TCG_TYPE_V64;
 +    unsigned q = vecl;
 +    TCGArg a0, a1, a2;
 +    int cmode, imm8;
 +
 +    a0 = args[0];
 +    a1 = args[1];
 +    a2 = args[2];
 +
 +    switch (opc) {
 +    case INDEX_op_ld_vec:
 +        tcg_out_ld(s, type, a0, a1, a2);
 +        return;
 +    case INDEX_op_st_vec:
 +        tcg_out_st(s, type, a0, a1, a2);
 +        return;
 +    case INDEX_op_dupm_vec:
 +        tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_dup2_vec:
 +        tcg_out_dup2_vec(s, a0, a1, a2);
 +        return;
 +    case INDEX_op_add_vec:
 +        tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_sub_vec:
 +        tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_xor_vec:
 +        tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
 +        return;
 +
 +    case INDEX_op_and_vec:
 +        if (const_args[2]) {
 +            is_shimm1632(~a2, &cmode, &imm8);
 +            if (a0 == a1) {
 +                tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
 +                return;
 +            }
 +            tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
 +            a2 = a0;
 +        }
 +        tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
 +        return;
 +
 +    case INDEX_op_or_vec:
 +        if (const_args[2]) {
 +            is_shimm1632(a2, &cmode, &imm8);
 +            if (a0 == a1) {
 +                tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */
 +                return;
 +            }
 +            tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
 +            a2 = a0;
 +        }
 +        tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
 +        return;
 +
 +    case INDEX_op_cmp_vec:
 +        {
 +            TCGCond cond = args[3];
 +
 +            if (cond == TCG_COND_NE) {
 +                if (const_args[2]) {
 +                    tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
 +                } else {
 +                    tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
 +                    tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
 +                }
 +            } else {
 +                ARMInsn insn;
 +
 +                if (const_args[2]) {
 +                    insn = vec_cmp0_insn[cond];
 +                    if (insn) {
 +                        tcg_out_vreg2(s, insn, q, vece, a0, a1);
 +                        return;
 +                    }
 +                    tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
 +                    a2 = TCG_VEC_TMP;
 +                }
 +                insn = vec_cmp_insn[cond];
 +                if (insn == 0) {
 +                    TCGArg t;
 +                    t = a1, a1 = a2, a2 = t;
 +                    cond = tcg_swap_cond(cond);
 +                    insn = vec_cmp_insn[cond];
 +                    tcg_debug_assert(insn != 0);
 +                }
 +                tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
 +            }
 +        }
 +        return;
 +
 +    case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
 +    case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
 +    default:
 +        g_assert_not_reached();
 +    }
-+
+ }
-     desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
-     desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
+ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
-     desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
+ {
 -    return 0;
 +    switch (opc) {
 +    case INDEX_op_add_vec:
 +    case INDEX_op_sub_vec:
 +    case INDEX_op_and_vec:
 +    case INDEX_op_or_vec:
 +    case INDEX_op_xor_vec:
 +        return 1;
 +    case INDEX_op_cmp_vec:
 +        return vece < MO_64;
 +    default:
 +        return 0;
 +    }
  }
  void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
 --
 .25.1

-New patch
+[PULL 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations
+These logical and arithmetic operations are optional, but are
+trivial to accomplish with the existing infrastructure.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/arm/tcg-target-con-set.h |  1 +
+ tcg/arm/tcg-target.h         | 10 +++++-----
+ tcg/arm/tcg-target.c.inc     | 38 ++++++++++++++++++++++++++++++++++++
+files changed, 44 insertions(+), 5 deletions(-)
+diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/arm/tcg-target-con-set.h
++++ b/tcg/arm/tcg-target-con-set.h
+@@ -XXX,XX +XXX,XX @@ C_O0_I4(s, s, s, s)
+ C_O1_I1(r, l)
+ C_O1_I1(r, r)
+ C_O1_I1(w, r)
++C_O1_I1(w, w)
+ C_O1_I1(w, wr)
+ C_O1_I2(r, 0, rZ)
+ C_O1_I2(r, l, l)
+diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/arm/tcg-target.h
++++ b/tcg/arm/tcg-target.h
+@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+ #define TCG_TARGET_HAS_v128             use_neon_instructions
+ #define TCG_TARGET_HAS_v256             0
+-#define TCG_TARGET_HAS_andc_vec         0
+-#define TCG_TARGET_HAS_orc_vec          0
+-#define TCG_TARGET_HAS_not_vec          0
+-#define TCG_TARGET_HAS_neg_vec          0
+-#define TCG_TARGET_HAS_abs_vec          0
++#define TCG_TARGET_HAS_andc_vec         1
++#define TCG_TARGET_HAS_orc_vec          1
++#define TCG_TARGET_HAS_not_vec          1
++#define TCG_TARGET_HAS_neg_vec          1
++#define TCG_TARGET_HAS_abs_vec          1
+ #define TCG_TARGET_HAS_roti_vec         0
+ #define TCG_TARGET_HAS_rots_vec         0
+ #define TCG_TARGET_HAS_rotv_vec         0
+diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/arm/tcg-target.c.inc
++++ b/tcg/arm/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ typedef enum {
+     INSN_VADD      = 0xf2000800,
+     INSN_VAND      = 0xf2000110,
++    INSN_VBIC      = 0xf2100110,
+     INSN_VEOR      = 0xf3000110,
++    INSN_VORN      = 0xf2300110,
+     INSN_VORR      = 0xf2200110,
+     INSN_VSUB      = 0xf3000800,
++    INSN_VABS      = 0xf3b10300,
+     INSN_VMVN      = 0xf3b00580,
++    INSN_VNEG      = 0xf3b10380,
+     INSN_VCEQ0     = 0xf3b10100,
+     INSN_VCGT0     = 0xf3b10000,
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+         return C_O1_I1(w, r);
+     case INDEX_op_dup_vec:
+         return C_O1_I1(w, wr);
++    case INDEX_op_abs_vec:
++    case INDEX_op_neg_vec:
++    case INDEX_op_not_vec:
++        return C_O1_I1(w, w);
+     case INDEX_op_dup2_vec:
+     case INDEX_op_add_vec:
+     case INDEX_op_sub_vec:
+     case INDEX_op_xor_vec:
+         return C_O1_I2(w, w, w);
+     case INDEX_op_or_vec:
++    case INDEX_op_andc_vec:
+         return C_O1_I2(w, w, wO);
+     case INDEX_op_and_vec:
++    case INDEX_op_orc_vec:
+         return C_O1_I2(w, w, wV);
+     case INDEX_op_cmp_vec:
+         return C_O1_I2(w, w, wZ);
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     case INDEX_op_dup2_vec:
+         tcg_out_dup2_vec(s, a0, a1, a2);
+         return;
++    case INDEX_op_abs_vec:
++        tcg_out_vreg2(s, INSN_VABS, q, vece, a0, a1);
++        return;
++    case INDEX_op_neg_vec:
++        tcg_out_vreg2(s, INSN_VNEG, q, vece, a0, a1);
++        return;
++    case INDEX_op_not_vec:
++        tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a1);
++        return;
+     case INDEX_op_add_vec:
+         tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
+         return;
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
+         return;
++    case INDEX_op_andc_vec:
++        if (!const_args[2]) {
++            tcg_out_vreg3(s, INSN_VBIC, q, 0, a0, a1, a2);
++            return;
++        }
++        a2 = ~a2;
++        /* fall through */
+     case INDEX_op_and_vec:
+         if (const_args[2]) {
+             is_shimm1632(~a2, &cmode, &imm8);
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+         tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
+         return;
++    case INDEX_op_orc_vec:
++        if (!const_args[2]) {
++            tcg_out_vreg3(s, INSN_VORN, q, 0, a0, a1, a2);
++            return;
++        }
++        a2 = ~a2;
++        /* fall through */
+     case INDEX_op_or_vec:
+         if (const_args[2]) {
+             is_shimm1632(a2, &cmode, &imm8);
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_add_vec:
+     case INDEX_op_sub_vec:
+     case INDEX_op_and_vec:
++    case INDEX_op_andc_vec:
+     case INDEX_op_or_vec:
++    case INDEX_op_orc_vec:
+     case INDEX_op_xor_vec:
++    case INDEX_op_not_vec:
+         return 1;
++    case INDEX_op_abs_vec:
+     case INDEX_op_cmp_vec:
++    case INDEX_op_neg_vec:
+         return vece < MO_64;
+     default:
+         return 0;
+--
+.25.1

-New patch
+[PULL 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec
+This consists of the three immediate shifts: shli, shri, sari.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+---
+ tcg/arm/tcg-target.h     |  2 +-
+ tcg/arm/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
+files changed, 28 insertions(+), 1 deletion(-)
+diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/arm/tcg-target.h
++++ b/tcg/arm/tcg-target.h
+@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
+ #define TCG_TARGET_HAS_roti_vec         0
+ #define TCG_TARGET_HAS_rots_vec         0
+ #define TCG_TARGET_HAS_rotv_vec         0
+-#define TCG_TARGET_HAS_shi_vec          0
++#define TCG_TARGET_HAS_shi_vec          1
+ #define TCG_TARGET_HAS_shs_vec          0
+ #define TCG_TARGET_HAS_shv_vec          0
+ #define TCG_TARGET_HAS_mul_vec          0
+diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/tcg/arm/tcg-target.c.inc
++++ b/tcg/arm/tcg-target.c.inc
+@@ -XXX,XX +XXX,XX @@ typedef enum {
+     INSN_VCGE_U    = 0xf3000310,
+     INSN_VCGT_U    = 0xf3000300,
++    INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
++    INSN_VSARI     = 0xf2800010,  /* VSHR.S */
++    INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
++
+     INSN_VTST      = 0xf2000810,
+     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
+               | (extract32(imm8, 7, 1) << 24));
+ }
++static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q,
++                            TCGReg rd, TCGReg rm, int l_imm6)
++{
++    tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) |
++              (extract32(l_imm6, 6, 1) << 7) |
++              (extract32(l_imm6, 0, 6) << 16));
++}
++
+ static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+                           TCGReg rd, TCGReg rn, int offset)
+ {
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
+     case INDEX_op_abs_vec:
+     case INDEX_op_neg_vec:
+     case INDEX_op_not_vec:
++    case INDEX_op_shli_vec:
++    case INDEX_op_shri_vec:
++    case INDEX_op_sari_vec:
+         return C_O1_I1(w, w);
+     case INDEX_op_dup2_vec:
+     case INDEX_op_add_vec:
+@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+     case INDEX_op_xor_vec:
+         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
+         return;
++    case INDEX_op_shli_vec:
++        tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
++        return;
++    case INDEX_op_shri_vec:
++        tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
++        return;
++    case INDEX_op_sari_vec:
++        tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
++        return;
+     case INDEX_op_andc_vec:
+         if (!const_args[2]) {
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_orc_vec:
+     case INDEX_op_xor_vec:
+     case INDEX_op_not_vec:
++    case INDEX_op_shli_vec:
++    case INDEX_op_shri_vec:
++    case INDEX_op_sari_vec:
+         return 1;
+     case INDEX_op_abs_vec:
+     case INDEX_op_cmp_vec:
+--
+.25.1

-[PULL 09/11] tcg/optimize: Fold dup2_vec
+[PULL 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec
-When the two arguments are identical, this can be reduced to
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 dup_vec or to mov_vec from a tcg_constant_vec.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/optimize.c | 15 +++++++++++++++
+ tcg/arm/tcg-target.h     | 2 +-
-file changed, 15 insertions(+)
+ tcg/arm/tcg-target.c.inc | 6 ++++++
 files changed, 7 insertions(+), 1 deletion(-)
-diff --git a/tcg/optimize.c b/tcg/optimize.c
+diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/optimize.c
+--- a/tcg/arm/tcg-target.h
-+++ b/tcg/optimize.c
++++ b/tcg/arm/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
+@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
-             }
+ #define TCG_TARGET_HAS_shi_vec          1
-             goto do_default;
+ #define TCG_TARGET_HAS_shs_vec          0
+ #define TCG_TARGET_HAS_shv_vec          0
-+        case INDEX_op_dup2_vec:
+-#define TCG_TARGET_HAS_mul_vec          0
-+            assert(TCG_TARGET_REG_BITS == 32);
++#define TCG_TARGET_HAS_mul_vec          1
-+            if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ #define TCG_TARGET_HAS_sat_vec          0
-+                tmp = arg_info(op->args[1])->val;
+ #define TCG_TARGET_HAS_minmax_vec       0
-+                if (tmp == arg_info(op->args[2])->val) {
+ #define TCG_TARGET_HAS_bitsel_vec       0
-+                    tcg_opt_gen_movi(s, op, op->args[0], tmp);
+diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
-+                    break;
+index XXXXXXX..XXXXXXX 100644
-+                }
+--- a/tcg/arm/tcg-target.c.inc
-+            } else if (args_are_copies(op->args[1], op->args[2])) {
++++ b/tcg/arm/tcg-target.c.inc
-+                op->opc = INDEX_op_dup_vec;
+@@ -XXX,XX +XXX,XX @@ typedef enum {
-+                TCGOP_VECE(op) = MO_32;
+     INSN_VORN      = 0xf2300110,
-+                nb_iargs = 1;
+     INSN_VORR      = 0xf2200110,
-+            }
+     INSN_VSUB      = 0xf3000800,
-+            goto do_default;
++    INSN_VMUL      = 0xf2000910,
-+
-         CASE_OP_32_64(not):
+     INSN_VABS      = 0xf3b10300,
-         CASE_OP_32_64(neg):
+     INSN_VMVN      = 0xf3b00580,
-         CASE_OP_32_64(ext8s):
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
          return C_O1_I1(w, w);
      case INDEX_op_dup2_vec:
      case INDEX_op_add_vec:
 +    case INDEX_op_mul_vec:
      case INDEX_op_sub_vec:
      case INDEX_op_xor_vec:
          return C_O1_I2(w, w, w);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_add_vec:
          tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
          return;
 +    case INDEX_op_mul_vec:
 +        tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_sub_vec:
          tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 +    case INDEX_op_mul_vec:
      case INDEX_op_neg_vec:
          return vece < MO_64;
      default:
 --
 .25.1

-[PULL 07/11] tcg/i386: Fix dupi for avx2 32-bit hosts
+[PULL 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec
-The previous change wrongly stated that 32-bit avx2 should have
+This is saturating add and subtract, signed and unsigned.
 used VPBROADCASTW.  But that's a 16-bit broadcast and we want a
 -bit broadcast.
-Fixes: 7b60ef3264e
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/i386/tcg-target.c.inc | 2 +-
+ tcg/arm/tcg-target.h     |  2 +-
-file changed, 1 insertion(+), 1 deletion(-)
+ tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
 files changed, 25 insertions(+), 1 deletion(-)
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
+diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
+--- a/tcg/arm/tcg-target.h
-+++ b/tcg/i386/tcg-target.c.inc
++++ b/tcg/arm/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
-         new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
+ #define TCG_TARGET_HAS_shs_vec          0
-     } else {
+ #define TCG_TARGET_HAS_shv_vec          0
-         if (have_avx2) {
+ #define TCG_TARGET_HAS_mul_vec          1
--            tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret);
+-#define TCG_TARGET_HAS_sat_vec          0
-+            tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
++#define TCG_TARGET_HAS_sat_vec          1
-         } else {
+ #define TCG_TARGET_HAS_minmax_vec       0
-             tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
+ #define TCG_TARGET_HAS_bitsel_vec       0
-         }
+ #define TCG_TARGET_HAS_cmpsel_vec       0
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
      INSN_VORR      = 0xf2200110,
      INSN_VSUB      = 0xf3000800,
      INSN_VMUL      = 0xf2000910,
 +    INSN_VQADD     = 0xf2000010,
 +    INSN_VQADD_U   = 0xf3000010,
 +    INSN_VQSUB     = 0xf2000210,
 +    INSN_VQSUB_U   = 0xf3000210,
      INSN_VABS      = 0xf3b10300,
      INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_dup2_vec:
      case INDEX_op_add_vec:
      case INDEX_op_mul_vec:
 +    case INDEX_op_ssadd_vec:
 +    case INDEX_op_sssub_vec:
      case INDEX_op_sub_vec:
 +    case INDEX_op_usadd_vec:
 +    case INDEX_op_ussub_vec:
      case INDEX_op_xor_vec:
          return C_O1_I2(w, w, w);
      case INDEX_op_or_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_sub_vec:
          tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
          return;
 +    case INDEX_op_ssadd_vec:
 +        tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_sssub_vec:
 +        tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_usadd_vec:
 +        tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_ussub_vec:
 +        tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_xor_vec:
          tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_shli_vec:
      case INDEX_op_shri_vec:
      case INDEX_op_sari_vec:
 +    case INDEX_op_ssadd_vec:
 +    case INDEX_op_sssub_vec:
 +    case INDEX_op_usadd_vec:
 +    case INDEX_op_ussub_vec:
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 --
 .25.1

-[PULL 06/11] tcg: Remove TCGOpDef.used
+[PULL 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
-The last user of this field disappeared in f69d277ece4.
+This is minimum and maximum, signed and unsigned.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/tcg/tcg.h | 3 ---
+ tcg/arm/tcg-target.h     |  2 +-
-file changed, 3 deletions(-)
+ tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
 files changed, 25 insertions(+), 1 deletion(-)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
+diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
+--- a/tcg/arm/tcg-target.h
-+++ b/include/tcg/tcg.h
++++ b/tcg/arm/tcg-target.h
-@@ -XXX,XX +XXX,XX @@ typedef struct TCGOpDef {
+@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
-     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
+ #define TCG_TARGET_HAS_shv_vec          0
-     uint8_t flags;
+ #define TCG_TARGET_HAS_mul_vec          1
-     TCGArgConstraint *args_ct;
+ #define TCG_TARGET_HAS_sat_vec          1
--#if defined(CONFIG_DEBUG_TCG)
+-#define TCG_TARGET_HAS_minmax_vec       0
--    int used;
++#define TCG_TARGET_HAS_minmax_vec       1
--#endif
+ #define TCG_TARGET_HAS_bitsel_vec       0
- } TCGOpDef;
+ #define TCG_TARGET_HAS_cmpsel_vec       0
- extern TCGOpDef tcg_op_defs[];
+diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
      INSN_VQADD_U   = 0xf3000010,
      INSN_VQSUB     = 0xf2000210,
      INSN_VQSUB_U   = 0xf3000210,
 +    INSN_VMAX      = 0xf2000600,
 +    INSN_VMAX_U    = 0xf3000600,
 +    INSN_VMIN      = 0xf2000610,
 +    INSN_VMIN_U    = 0xf3000610,
      INSN_VABS      = 0xf3b10300,
      INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_dup2_vec:
      case INDEX_op_add_vec:
      case INDEX_op_mul_vec:
 +    case INDEX_op_smax_vec:
 +    case INDEX_op_smin_vec:
      case INDEX_op_ssadd_vec:
      case INDEX_op_sssub_vec:
      case INDEX_op_sub_vec:
 +    case INDEX_op_umax_vec:
 +    case INDEX_op_umin_vec:
      case INDEX_op_usadd_vec:
      case INDEX_op_ussub_vec:
      case INDEX_op_xor_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_mul_vec:
          tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
          return;
 +    case INDEX_op_smax_vec:
 +        tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_smin_vec:
 +        tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_sub_vec:
          tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_sssub_vec:
          tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
          return;
 +    case INDEX_op_umax_vec:
 +        tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
 +        return;
 +    case INDEX_op_umin_vec:
 +        tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
 +        return;
      case INDEX_op_usadd_vec:
          tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_cmp_vec:
      case INDEX_op_mul_vec:
      case INDEX_op_neg_vec:
 +    case INDEX_op_smax_vec:
 +    case INDEX_op_smin_vec:
 +    case INDEX_op_umax_vec:
 +    case INDEX_op_umin_vec:
          return vece < MO_64;
      default:
          return 0;
 --
 .25.1

-[PULL 10/11] tcg: Remove TCG_TARGET_HAS_cmp_vec
+[PULL 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
-The cmp_vec opcode is mandatory; this symbol is unused.
+NEON has 3 instructions implementing this 4 argument operation,
 with each insn overlapping a different logical input onto the
 destination register.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/aarch64/tcg-target.h | 1 -
+ tcg/arm/tcg-target-con-set.h |  1 +
- tcg/i386/tcg-target.h    | 1 -
+ tcg/arm/tcg-target.h         |  2 +-
- tcg/ppc/tcg-target.h     | 1 -
+ tcg/arm/tcg-target.c.inc     | 22 ++++++++++++++++++++--
-files changed, 3 deletions(-)
+files changed, 22 insertions(+), 3 deletions(-)
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
+diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.h
+--- a/tcg/arm/tcg-target-con-set.h
-+++ b/tcg/aarch64/tcg-target.h
++++ b/tcg/arm/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ C_O1_I2(w, w, w)
- #define TCG_TARGET_HAS_shi_vec          1
+ C_O1_I2(w, w, wO)
- #define TCG_TARGET_HAS_shs_vec          0
+ C_O1_I2(w, w, wV)
- #define TCG_TARGET_HAS_shv_vec          1
+ C_O1_I2(w, w, wZ)
--#define TCG_TARGET_HAS_cmp_vec          1
++C_O1_I3(w, w, w, w)
  C_O1_I4(r, r, r, rI, rI)
  C_O1_I4(r, r, rIN, rIK, 0)
  C_O2_I1(r, r, l)
 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.h
 +++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
  #define TCG_TARGET_HAS_mul_vec          1
  #define TCG_TARGET_HAS_sat_vec          1
  #define TCG_TARGET_HAS_minmax_vec       1
-diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
+-#define TCG_TARGET_HAS_bitsel_vec       0
 +#define TCG_TARGET_HAS_bitsel_vec       1
  #define TCG_TARGET_HAS_cmpsel_vec       0
  #define TCG_TARGET_DEFAULT_MO (0)
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.h
+--- a/tcg/arm/tcg-target.c.inc
-+++ b/tcg/i386/tcg-target.h
++++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
+@@ -XXX,XX +XXX,XX @@ typedef enum {
- #define TCG_TARGET_HAS_shi_vec          1
+     INSN_VSARI     = 0xf2800010,  /* VSHR.S */
- #define TCG_TARGET_HAS_shs_vec          1
+     INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
- #define TCG_TARGET_HAS_shv_vec          have_avx2
--#define TCG_TARGET_HAS_cmp_vec          1
++    INSN_VBSL      = 0xf3100110,
- #define TCG_TARGET_HAS_mul_vec          1
++    INSN_VBIT      = 0xf3200110,
- #define TCG_TARGET_HAS_sat_vec          1
++    INSN_VBIF      = 0xf3300110,
- #define TCG_TARGET_HAS_minmax_vec       1
++
-diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
+     INSN_VTST      = 0xf2000810,
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.h
+     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
-+++ b/tcg/ppc/tcg-target.h
+@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
-@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
+         return C_O1_I2(w, w, wV);
- #define TCG_TARGET_HAS_shi_vec          0
+     case INDEX_op_cmp_vec:
- #define TCG_TARGET_HAS_shs_vec          0
+         return C_O1_I2(w, w, wZ);
- #define TCG_TARGET_HAS_shv_vec          1
+-
--#define TCG_TARGET_HAS_cmp_vec          1
++    case INDEX_op_bitsel_vec:
- #define TCG_TARGET_HAS_mul_vec          1
++        return C_O1_I3(w, w, w, w);
- #define TCG_TARGET_HAS_sat_vec          1
+     default:
- #define TCG_TARGET_HAS_minmax_vec       1
+         g_assert_not_reached();
      }
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
  {
      TCGType type = vecl + TCG_TYPE_V64;
      unsigned q = vecl;
 -    TCGArg a0, a1, a2;
 +    TCGArg a0, a1, a2, a3;
      int cmode, imm8;
      a0 = args[0];
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
          }
          return;
 +    case INDEX_op_bitsel_vec:
 +        a3 = args[3];
 +        if (a0 == a3) {
 +            tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1);
 +        } else if (a0 == a2) {
 +            tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1);
 +        } else {
 +            tcg_out_mov(s, type, a0, a1);
 +            tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3);
 +        }
 +        return;
 +
      case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
      case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
      default:
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_sssub_vec:
      case INDEX_op_usadd_vec:
      case INDEX_op_ussub_vec:
 +    case INDEX_op_bitsel_vec:
          return 1;
      case INDEX_op_abs_vec:
      case INDEX_op_cmp_vec:
 --
 .25.1

-[PULL 08/11] tcg: Fix generation of dupi_vec for 32-bit host
+[PULL 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec
-The definition of INDEX_op_dupi_vec is that it operates on
+The three vector shift by vector operations are all implemented via
-units of tcg_target_ulong -- in this case 32 bits.  It does
+expansion.  Therefore do not actually set TCG_TARGET_HAS_shv_vec,
-not work to use this for a uint64_t value that happens to be
+as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
-small enough to fit in tcg_target_ulong.
+instruction stream, and therefore also do not appear in tcg_target_op_def.
-Fixes: d2fd745fe8b
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Fixes: db432672dc5
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/tcg-op-vec.c | 12 ++++++++----
+ tcg/arm/tcg-target.opc.h |  3 ++
-file changed, 8 insertions(+), 4 deletions(-)
+ tcg/arm/tcg-target.c.inc | 61 +++++++++++++++++++++++++++++++++++++++-
 files changed, 63 insertions(+), 1 deletion(-)
-diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
+diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-vec.c
+--- a/tcg/arm/tcg-target.opc.h
-+++ b/tcg/tcg-op-vec.c
++++ b/tcg/arm/tcg-target.opc.h
-@@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
+@@ -XXX,XX +XXX,XX @@
+  * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
- void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
+  * consider these to be UNSPEC with names.
   */
 +
 +DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
 +DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
      INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
      INSN_VSARI     = 0xf2800010,  /* VSHR.S */
      INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
 +    INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
 +    INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
      INSN_VBSL      = 0xf3100110,
      INSN_VBIT      = 0xf3200110,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_usadd_vec:
      case INDEX_op_ussub_vec:
      case INDEX_op_xor_vec:
 +    case INDEX_op_arm_sshl_vec:
 +    case INDEX_op_arm_ushl_vec:
          return C_O1_I2(w, w, w);
      case INDEX_op_or_vec:
      case INDEX_op_andc_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_xor_vec:
          tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
          return;
 +    case INDEX_op_arm_sshl_vec:
 +        /*
 +         * Note that Vm is the data and Vn is the shift count,
 +         * therefore the arguments appear reversed.
 +         */
 +        tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
 +        return;
 +    case INDEX_op_arm_ushl_vec:
 +        /* See above. */
 +        tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
 +        return;
      case INDEX_op_shli_vec:
          tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
          return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_umax_vec:
      case INDEX_op_umin_vec:
          return vece < MO_64;
 +    case INDEX_op_shlv_vec:
 +    case INDEX_op_shrv_vec:
 +    case INDEX_op_sarv_vec:
 +        return -1;
      default:
          return 0;
      }
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
  void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                         TCGArg a0, ...)
  {
--    if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
+-    g_assert_not_reached();
--        do_dupi_vec(r, MO_32, a);
++    va_list va;
--    } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
++    TCGv_vec v0, v1, v2, t1;
-+    if (TCG_TARGET_REG_BITS == 64) {
++    TCGArg a2;
-         do_dupi_vec(r, MO_64, a);
++
-+    } else if (a == dup_const(MO_32, a)) {
++    va_start(va, a0);
-+        do_dupi_vec(r, MO_32, a);
++    v0 = temp_tcgv_vec(arg_temp(a0));
-     } else {
++    v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
-         TCGv_i64 c = tcg_const_i64(a);
++    a2 = va_arg(va, TCGArg);
-         tcg_gen_dup_i64_vec(MO_64, r, c);
++    va_end(va);
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
++
++    switch (opc) {
- void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
++    case INDEX_op_shlv_vec:
- {
++        /*
--    do_dupi_vec(r, MO_REG, dup_const(vece, a));
++         * Merely propagate shlv_vec to arm_ushl_vec.
-+    if (vece == MO_64) {
++         * In this way we don't set TCG_TARGET_HAS_shv_vec
-+        tcg_gen_dup64i_vec(r, a);
++         * because everything is done via expansion.
-+    } else {
++         */
-+        do_dupi_vec(r, MO_REG, dup_const(vece, a));
++        v2 = temp_tcgv_vec(arg_temp(a2));
 +        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
 +        break;
 +
 +    case INDEX_op_shrv_vec:
 +    case INDEX_op_sarv_vec:
 +        /* Right shifts are negative left shifts for NEON.  */
 +        v2 = temp_tcgv_vec(arg_temp(a2));
 +        t1 = tcg_temp_new_vec(type);
 +        tcg_gen_neg_vec(vece, t1, v2);
 +        if (opc == INDEX_op_shrv_vec) {
 +            opc = INDEX_op_arm_ushl_vec;
 +        } else {
 +            opc = INDEX_op_arm_sshl_vec;
 +        }
 +        vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
 +                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
 +        tcg_temp_free_vec(t1);
 +        break;
 +
 +    default:
 +        g_assert_not_reached();
 +    }
  }
- void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
+ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
 --
 .25.1

-[PULL 05/11] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
+[PULL 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec
-These are easier to set and test when they have their own fields.
+Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
-Reduce the size of alias_index and sort_index to 4 bits, which is
+For NEON, this is shift-right followed by shift-left-and-insert.
 sufficient for TCG_MAX_OP_ARGS.  This leaves only the bits indicating
 constants within the ct field.
-Move all initialization to allocation time, rather than init
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 individual fields in process_op_defs.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/tcg/tcg.h | 14 +++++++-------
+ tcg/arm/tcg-target-con-set.h |  1 +
- tcg/tcg.c         | 28 ++++++++++++----------------
+ tcg/arm/tcg-target.opc.h     |  1 +
-files changed, 19 insertions(+), 23 deletions(-)
+ tcg/arm/tcg-target.c.inc     | 15 +++++++++++++++
 files changed, 17 insertions(+)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
+diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
+--- a/tcg/arm/tcg-target-con-set.h
-+++ b/include/tcg/tcg.h
++++ b/tcg/arm/tcg-target-con-set.h
-@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void);
+@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
- void tcg_dump_info(void);
+ C_O1_I2(r, r, rIN)
- void tcg_dump_op_count(void);
+ C_O1_I2(r, r, ri)
+ C_O1_I2(r, rZ, rZ)
--#define TCG_CT_ALIAS  0x80
++C_O1_I2(w, 0, w)
--#define TCG_CT_IALIAS 0x40
+ C_O1_I2(w, w, w)
--#define TCG_CT_NEWREG 0x20 /* output requires a new register */
+ C_O1_I2(w, w, wO)
--#define TCG_CT_CONST  0x02 /* any constant of register size */
+ C_O1_I2(w, w, wV)
-+#define TCG_CT_CONST  1 /* any constant of register size */
+diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
  typedef struct TCGArgConstraint {
 -    uint16_t ct;
 -    uint8_t alias_index;
 -    uint8_t sort_index;
 +    unsigned ct : 16;
 +    unsigned alias_index : 4;
 +    unsigned sort_index : 4;
 +    bool oalias : 1;
 +    bool ialias : 1;
 +    bool newreg : 1;
      TCGRegSet regs;
  } TCGArgConstraint;
 diff --git a/tcg/tcg.c b/tcg/tcg.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
+--- a/tcg/arm/tcg-target.opc.h
-+++ b/tcg/tcg.c
++++ b/tcg/arm/tcg-target.opc.h
-@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
+@@ -XXX,XX +XXX,XX @@
-         total_args += n;
+  * consider these to be UNSPEC with names.
   */
 +DEF(arm_sli_vec, 1, 2, 1, IMPLVEC)
  DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
  DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
      INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
      INSN_VSARI     = 0xf2800010,  /* VSHR.S */
      INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
 +    INSN_VSLI      = 0xf3800510,
      INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
      INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
      case INDEX_op_arm_sshl_vec:
      case INDEX_op_arm_ushl_vec:
          return C_O1_I2(w, w, w);
 +    case INDEX_op_arm_sli_vec:
 +        return C_O1_I2(w, 0, w);
      case INDEX_op_or_vec:
      case INDEX_op_andc_vec:
          return C_O1_I2(w, w, wO);
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
      case INDEX_op_sari_vec:
          tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
          return;
 +    case INDEX_op_arm_sli_vec:
 +        tcg_out_vshifti(s, INSN_VSLI, q, a0, a2, args[3] + (8 << vece));
 +        return;
      case INDEX_op_andc_vec:
          if (!const_args[2]) {
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
      case INDEX_op_shlv_vec:
      case INDEX_op_shrv_vec:
      case INDEX_op_sarv_vec:
 +    case INDEX_op_rotli_vec:
          return -1;
      default:
          return 0;
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
          tcg_temp_free_vec(t1);
          break;
 +    case INDEX_op_rotli_vec:
 +        t1 = tcg_temp_new_vec(type);
 +        tcg_gen_shri_vec(vece, t1, v1, -a2 & ((8 << vece) - 1));
 +        vec_gen_4(INDEX_op_arm_sli_vec, type, vece,
 +                  tcgv_vec_arg(v0), tcgv_vec_arg(t1), tcgv_vec_arg(v1), a2);
 +        tcg_temp_free_vec(t1);
 +        break;
 +
      default:
          g_assert_not_reached();
      }
--    args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
-+    args_ct = g_new0(TCGArgConstraint, total_args);
-     for(op = 0; op < NB_OPS; op++) {
-         def = &tcg_op_defs[op];
-@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
-     const TCGArgConstraint *arg_ct = &def->args_ct[k];
-     int n;
--    if (arg_ct->ct & TCG_CT_ALIAS) {
-+    if (arg_ct->oalias) {
-         /* an alias is equivalent to a single register */
-         n = 1;
-     } else {
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-             /* Incomplete TCGTargetOpDef entry. */
-             tcg_debug_assert(ct_str != NULL);
--            def->args_ct[i].regs = 0;
--            def->args_ct[i].ct = 0;
-             while (*ct_str != '\0') {
-                 switch(*ct_str) {
-                 case '0' ... '9':
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-                         tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
-                         tcg_debug_assert(oarg < def->nb_oargs);
-                         tcg_debug_assert(def->args_ct[oarg].regs != 0);
--                        /* TCG_CT_ALIAS is for the output arguments.
--                           The input is tagged with TCG_CT_IALIAS. */
-                         def->args_ct[i] = def->args_ct[oarg];
--                        def->args_ct[oarg].ct |= TCG_CT_ALIAS;
-+                        /* The output sets oalias.  */
-+                        def->args_ct[oarg].oalias = true;
-                         def->args_ct[oarg].alias_index = i;
--                        def->args_ct[i].ct |= TCG_CT_IALIAS;
-+                        /* The input sets ialias. */
-+                        def->args_ct[i].ialias = true;
-                         def->args_ct[i].alias_index = oarg;
-                     }
-                     ct_str++;
-                     break;
-                 case '&':
--                    def->args_ct[i].ct |= TCG_CT_NEWREG;
-+                    def->args_ct[i].newreg = true;
-                     ct_str++;
-                     break;
-                 case 'i':
-@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
-                     set = *pset;
-                     set &= ct->regs;
--                    if (ct->ct & TCG_CT_IALIAS) {
-+                    if (ct->ialias) {
-                         set &= op->output_pref[ct->alias_index];
-                     }
-                     /* If the combination is not possible, restart.  */
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-         }
-         i_preferred_regs = o_preferred_regs = 0;
--        if (arg_ct->ct & TCG_CT_IALIAS) {
-+        if (arg_ct->ialias) {
-             o_preferred_regs = op->output_pref[arg_ct->alias_index];
-             if (ts->fixed_reg) {
-                 /* if fixed register, we must allocate a new register
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-                     reg = ts->reg;
-                     for (k2 = 0 ; k2 < k ; k2++) {
-                         i2 = def->args_ct[nb_oargs + k2].sort_index;
--                        if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
--                            reg == new_args[i2]) {
-+                        if (def->args_ct[i2].ialias && reg == new_args[i2]) {
-                             goto allocate_in_reg;
-                         }
-                     }
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-             /* ENV should not be modified.  */
-             tcg_debug_assert(!ts->fixed_reg);
--            if ((arg_ct->ct & TCG_CT_ALIAS)
--                && !const_args[arg_ct->alias_index]) {
-+            if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
-                 reg = new_args[arg_ct->alias_index];
--            } else if (arg_ct->ct & TCG_CT_NEWREG) {
-+            } else if (arg_ct->newreg) {
-                 reg = tcg_reg_alloc(s, arg_ct->regs,
-                                     i_allocated_regs | o_allocated_regs,
-                                     op->output_pref[k], ts->indirect_base);
 --
 .25.1

-[PULL 02/11] tcg: Drop union from TCGArgConstraint
+[PULL 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
-The union is unused; let "regs" appear in the main structure
+Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.
 without the "u.regs" wrapping.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/tcg/tcg.h            |  4 +---
+ tcg/arm/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++-
- tcg/tcg.c                    | 22 +++++++++++-----------
+file changed, 34 insertions(+), 1 deletion(-)
  tcg/aarch64/tcg-target.c.inc | 14 +++++++-------
  tcg/arm/tcg-target.c.inc     | 26 +++++++++++++-------------
  tcg/i386/tcg-target.c.inc    | 26 +++++++++++++-------------
  tcg/mips/tcg-target.c.inc    | 18 +++++++++---------
  tcg/ppc/tcg-target.c.inc     | 24 ++++++++++++------------
  tcg/riscv/tcg-target.c.inc   | 14 +++++++-------
  tcg/s390/tcg-target.c.inc    | 18 +++++++++---------
  tcg/sparc/tcg-target.c.inc   | 16 ++++++++--------
  tcg/tci/tcg-target.c.inc     |  2 +-
 files changed, 91 insertions(+), 93 deletions(-)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
-+++ b/include/tcg/tcg.h
-@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
- typedef struct TCGArgConstraint {
-     uint16_t ct;
-     uint8_t alias_index;
--    union {
--        TCGRegSet regs;
--    } u;
-+    TCGRegSet regs;
- } TCGArgConstraint;
- #define TCG_MAX_OP_ARGS 16
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
-             return 0;
-         n = 0;
-         for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
--            if (tcg_regset_test_reg(arg_ct->u.regs, i))
-+            if (tcg_regset_test_reg(arg_ct->regs, i))
-                 n++;
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-             /* Incomplete TCGTargetOpDef entry. */
-             tcg_debug_assert(ct_str != NULL);
--            def->args_ct[i].u.regs = 0;
-+            def->args_ct[i].regs = 0;
-             def->args_ct[i].ct = 0;
-             while (*ct_str != '\0') {
-                 switch(*ct_str) {
-@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
-                     pset = la_temp_pref(ts);
-                     set = *pset;
--                    set &= ct->u.regs;
-+                    set &= ct->regs;
-                     if (ct->ct & TCG_CT_IALIAS) {
-                         set &= op->output_pref[ct->alias_index];
-                     }
-                     /* If the combination is not possible, restart.  */
-                     if (set == 0) {
--                        set = ct->u.regs;
-+                        set = ct->regs;
-                     }
-                     *pset = set;
-                 }
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
-         return;
-     }
--    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
--    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
-+    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
-+    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
-     /* Allocate the output register now.  */
-     if (ots->val_type != TEMP_VAL_REG) {
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-             }
-         }
--        temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);
-+        temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
-         reg = ts->reg;
--        if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
-+        if (tcg_regset_test_reg(arg_ct->regs, reg)) {
-             /* nothing to do : the constraint is satisfied */
-         } else {
-         allocate_in_reg:
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-                and move the temporary register into it */
-             temp_load(s, ts, tcg_target_available_regs[ts->type],
-                       i_allocated_regs, 0);
--            reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
-+            reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
-                                 o_preferred_regs, ts->indirect_base);
-             if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
-                 /*
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-                 && !const_args[arg_ct->alias_index]) {
-                 reg = new_args[arg_ct->alias_index];
-             } else if (arg_ct->ct & TCG_CT_NEWREG) {
--                reg = tcg_reg_alloc(s, arg_ct->u.regs,
-+                reg = tcg_reg_alloc(s, arg_ct->regs,
-                                     i_allocated_regs | o_allocated_regs,
-                                     op->output_pref[k], ts->indirect_base);
-             } else {
--                reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
-+                reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
-                                     op->output_pref[k], ts->indirect_base);
-             }
-             tcg_regset_set_reg(o_allocated_regs, reg);
-diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.c.inc
-+++ b/tcg/aarch64/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-     switch (*ct_str++) {
-     case 'r': /* general registers */
-         ct->ct |= TCG_CT_REG;
--        ct->u.regs |= 0xffffffffu;
-+        ct->regs |= 0xffffffffu;
-         break;
-     case 'w': /* advsimd registers */
-         ct->ct |= TCG_CT_REG;
--        ct->u.regs |= 0xffffffff00000000ull;
-+        ct->regs |= 0xffffffff00000000ull;
-         break;
-     case 'l': /* qemu_ld / qemu_st address, data_reg */
-         ct->ct |= TCG_CT_REG;
--        ct->u.regs = 0xffffffffu;
-+        ct->regs = 0xffffffffu;
- #ifdef CONFIG_SOFTMMU
-         /* x0 and x1 will be overwritten when reading the tlb entry,
-            and x2, and x3 for helper args, better to avoid using them. */
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
- #endif
-         break;
-     case 'A': /* Valid for arithmetic immediate (positive or negative).  */
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
+@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+     case INDEX_op_shrv_vec:
-     case 'r':
+     case INDEX_op_sarv_vec:
-         ct->ct |= TCG_CT_REG;
+     case INDEX_op_rotli_vec:
--        ct->u.regs = 0xffff;
++    case INDEX_op_rotlv_vec:
-+        ct->regs = 0xffff;
++    case INDEX_op_rotrv_vec:
          return -1;
      default:
          return 0;
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                         TCGArg a0, ...)
  {
      va_list va;
 -    TCGv_vec v0, v1, v2, t1;
 +    TCGv_vec v0, v1, v2, t1, t2, c1;
      TCGArg a2;
      va_start(va, a0);
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
          tcg_temp_free_vec(t1);
          break;
-     /* qemu_ld address */
++    case INDEX_op_rotlv_vec:
-     case 'l':
++        v2 = temp_tcgv_vec(arg_temp(a2));
-         ct->ct |= TCG_CT_REG;
++        t1 = tcg_temp_new_vec(type);
--        ct->u.regs = 0xffff;
++        c1 = tcg_constant_vec(type, vece, 8 << vece);
-+        ct->regs = 0xffff;
++        tcg_gen_sub_vec(vece, t1, v2, c1);
- #ifdef CONFIG_SOFTMMU
++        /* Right shifts are negative left shifts for NEON.  */
-         /* r0-r2,lr will be overwritten when reading the tlb entry,
++        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
-            so don't use these. */
++                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
++        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
++                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
++        tcg_gen_or_vec(vece, v0, v0, t1);
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
++        tcg_temp_free_vec(t1);
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
++        break;
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
++
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
++    case INDEX_op_rotrv_vec:
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
++        v2 = temp_tcgv_vec(arg_temp(a2));
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
++        t1 = tcg_temp_new_vec(type);
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
++        t2 = tcg_temp_new_vec(type);
- #endif
++        c1 = tcg_constant_vec(type, vece, 8 << vece);
-         break;
++        tcg_gen_neg_vec(vece, t1, v2);
++        tcg_gen_sub_vec(vece, t2, c1, v2);
-     /* qemu_st address & data */
++        /* Right shifts are negative left shifts for NEON.  */
-     case 's':
++        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
-         ct->ct |= TCG_CT_REG;
++                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
--        ct->u.regs = 0xffff;
++        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
-+        ct->regs = 0xffff;
++                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));
-         /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
++        tcg_gen_or_vec(vece, v0, t1, t2);
-            and r0-r1 doing the byte swapping, so don't use these. */
++        tcg_temp_free_vec(t1);
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
++        tcg_temp_free_vec(t2);
--        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
++        break;
-+        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
++
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
  #if defined(CONFIG_SOFTMMU)
          /* Avoid clashes with registers being used for helper args */
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
  #if TARGET_LONG_BITS == 64
          /* Avoid clashes with registers being used for helper args */
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
  #endif
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
  #endif
          break;
 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.c.inc
 +++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch(*ct_str++) {
      case 'a':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
          break;
      case 'b':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
          break;
      case 'c':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
          break;
      case 'd':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
          break;
      case 'S':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
          break;
      case 'D':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
          break;
      case 'q':
          /* A register that can be used as a byte operand.  */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
 +        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
          break;
      case 'Q':
          /* A register with an addressable second byte (e.g. %ah).  */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xf;
 +        ct->regs = 0xf;
          break;
      case 'r':
          /* A general register.  */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs |= ALL_GENERAL_REGS;
 +        ct->regs |= ALL_GENERAL_REGS;
          break;
      case 'W':
          /* With TZCNT/LZCNT, we can have operand-size as an input.  */
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      case 'x':
          /* A vector register.  */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs |= ALL_VECTOR_REGS;
 +        ct->regs |= ALL_VECTOR_REGS;
          break;
          /* qemu_ld/st address constraint */
      case 'L':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
 +        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
          break;
      case 'e':
 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/mips/tcg-target.c.inc
 +++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch(*ct_str++) {
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          break;
      case 'L': /* qemu_ld input arg constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
 +        ct->regs = 0xffffffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
  #if defined(CONFIG_SOFTMMU)
          if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
 -            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
 +            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
          }
  #endif
          break;
      case 'S': /* qemu_st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
 +        ct->regs = 0xffffffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
  #if defined(CONFIG_SOFTMMU)
          if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
 -            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
 -            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
 +            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
 +            tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
          } else {
 -            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
 +            tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
          }
  #endif
          break;
 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.c.inc
 +++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'A': case 'B': case 'C': case 'D':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
 +        tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
          break;
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          break;
      case 'v':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff00000000ull;
 +        ct->regs = 0xffffffff00000000ull;
          break;
      case 'L':                   /* qemu_ld constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 +        ct->regs = 0xffffffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
  #ifdef CONFIG_SOFTMMU
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
  #endif
          break;
      case 'S':                   /* qemu_st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 +        ct->regs = 0xffffffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
  #ifdef CONFIG_SOFTMMU
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
  #endif
          break;
      case 'I':
 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/riscv/tcg-target.c.inc
 +++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          break;
      case 'L':
          /* qemu_ld/qemu_st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
  #if defined(CONFIG_SOFTMMU)
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
  #endif
          break;
      case 'I':
 diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/s390/tcg-target.c.inc
 +++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'r':                  /* all registers */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffff;
 +        ct->regs = 0xffff;
          break;
      case 'L':                  /* qemu_ld/st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
 +        ct->regs = 0xffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
          break;
      case 'a':                  /* force R2 for division */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
 +        ct->regs = 0;
 +        tcg_regset_set_reg(ct->regs, TCG_REG_R2);
          break;
      case 'b':                  /* force R3 for division */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
 +        ct->regs = 0;
 +        tcg_regset_set_reg(ct->regs, TCG_REG_R3);
          break;
      case 'A':
          ct->ct |= TCG_CT_CONST_S33;
 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/sparc/tcg-target.c.inc
 +++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          break;
      case 'R':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = ALL_64;
 +        ct->regs = ALL_64;
          break;
      case 'A': /* qemu_ld/st address constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
 +        ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
      reserve_helpers:
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
          break;
      case 's': /* qemu_st data 32-bit constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          goto reserve_helpers;
      case 'S': /* qemu_st data 64-bit constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = ALL_64;
 +        ct->regs = ALL_64;
          goto reserve_helpers;
      case 'I':
          ct->ct |= TCG_CT_CONST_S11;
 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tci/tcg-target.c.inc
 +++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      case 'L':                   /* qemu_ld constraint */
      case 'S':                   /* qemu_st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
 +        ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
          break;
      default:
-         return NULL;
+         g_assert_not_reached();
      }
 --
 .25.1

The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)

are available in the Git repository at:

https://github.com/rth7680/qemu.git tags/pull-tcg-20201008

for you to fetch changes up to 62475e9d007d83db4d0a6ccebcda8914f392e9c9:

accel/tcg: Fix computing of is_write for MIPS (2020-10-08 05:57:32 -0500)

----------------------------------------------------------------
Extend maximum gvec vector size
Fix i386 avx2 dupi
Fix mips host user-only write detection
Misc cleanups.

----------------------------------------------------------------
Kele Huang (1):
      accel/tcg: Fix computing of is_write for MIPS

Richard Henderson (10):
      tcg: Adjust simd_desc size encoding
      tcg: Drop union from TCGArgConstraint
      tcg: Move sorted_args into TCGArgConstraint.sort_index
      tcg: Remove TCG_CT_REG
      tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
      tcg: Remove TCGOpDef.used
      tcg/i386: Fix dupi for avx2 32-bit hosts
      tcg: Fix generation of dupi_vec for 32-bit host
      tcg/optimize: Fold dup2_vec
      tcg: Remove TCG_TARGET_HAS_cmp_vec

With larger vector sizes, it turns out oprsz == maxsz, and we only
need to represent mismatch for oprsz <= 32.  We do, however, need
to represent larger oprsz and do so without reducing SIMD_DATA_BITS.

Reduce the size of the oprsz field and increase the maxsz field.
Steal the oprsz value of 24 to indicate equality with maxsz.

Tested-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++-------------
 tcg/tcg-op-gvec.c           | 35 ++++++++++++++++++++++++++--------
 2 files changed, 52 insertions(+), 21 deletions(-)

diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-gvec-desc.h
+++ b/include/tcg/tcg-gvec-desc.h
@@ -XXX,XX +XXX,XX @@
 #ifndef TCG_TCG_GVEC_DESC_H
 #define TCG_TCG_GVEC_DESC_H
 
-/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
-#define SIMD_OPRSZ_SHIFT   0
-#define SIMD_OPRSZ_BITS    5
+/*
+ * This configuration allows MAXSZ to represent 2048 bytes, and
+ * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
+ *
+ * Encode this with:
+ *   0, 1, 3 -> 8, 16, 32
+ *   2       -> maxsz
+ *
+ * This steals the input that would otherwise map to 24 to match maxsz.
+ */
+#define SIMD_MAXSZ_SHIFT   0
+#define SIMD_MAXSZ_BITS    8
 
-#define SIMD_MAXSZ_SHIFT   (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
-#define SIMD_MAXSZ_BITS    5
+#define SIMD_OPRSZ_SHIFT   (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_OPRSZ_BITS    2
 
-#define SIMD_DATA_SHIFT    (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_DATA_SHIFT    (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
 #define SIMD_DATA_BITS     (32 - SIMD_DATA_SHIFT)
 
 /* Create a descriptor from components.  */
 uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
 
-/* Extract the operation size from a descriptor.  */
-static inline intptr_t simd_oprsz(uint32_t desc)
-{
-    return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
-}
-
 /* Extract the max vector size from a descriptor.  */
 static inline intptr_t simd_maxsz(uint32_t desc)
 {
-    return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
+    return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
+}
+
+/* Extract the operation size from a descriptor.  */
+static inline intptr_t simd_oprsz(uint32_t desc)
+{
+    uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
+    intptr_t o = f * 8 + 8;
+    intptr_t m = simd_maxsz(desc);
+    return f == 2 ? m : o;
 }
 
 /* Extract the operation-specific data from a descriptor.  */
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -XXX,XX +XXX,XX @@ static const TCGOpcode vecop_list_empty[1] = { 0 };
    of the operand offsets so that we can check them all at once.  */
 static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
 {
-    uint32_t opr_align = oprsz >= 16 ? 15 : 7;
-    uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
-    tcg_debug_assert(oprsz > 0);
-    tcg_debug_assert(oprsz <= maxsz);
-    tcg_debug_assert((oprsz & opr_align) == 0);
+    uint32_t max_align;
+
+    switch (oprsz) {
+    case 8:
+    case 16:
+    case 32:
+        tcg_debug_assert(oprsz <= maxsz);
+        break;
+    default:
+        tcg_debug_assert(oprsz == maxsz);
+        break;
+    }
+    tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));
+
+    max_align = maxsz >= 16 ? 15 : 7;
     tcg_debug_assert((maxsz & max_align) == 0);
     tcg_debug_assert((ofs & max_align) == 0);
 }
@@ -XXX,XX +XXX,XX @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
 {
     uint32_t desc = 0;
 
-    assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
-    assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
-    assert(data == sextract32(data, 0, SIMD_DATA_BITS));
+    check_size_align(oprsz, maxsz, 0);
+    tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));
 
     oprsz = (oprsz / 8) - 1;
     maxsz = (maxsz / 8) - 1;
+
+    /*
+     * We have just asserted in check_size_align that either
+     * oprsz is {8,16,32} or matches maxsz.  Encode the final
+     * case with '2', as that would otherwise map to 24.
+     */
+    if (oprsz == maxsz) {
+        oprsz = 2;
+    }
+
     desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
     desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
     desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
-- 
2.25.1

The union is unused; let "regs" appear in the main structure
without the "u.regs" wrapping.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h            |  4 +---
 tcg/tcg.c                    | 22 +++++++++++-----------
 tcg/aarch64/tcg-target.c.inc | 14 +++++++-------
 tcg/arm/tcg-target.c.inc     | 26 +++++++++++++-------------
 tcg/i386/tcg-target.c.inc    | 26 +++++++++++++-------------
 tcg/mips/tcg-target.c.inc    | 18 +++++++++---------
 tcg/ppc/tcg-target.c.inc     | 24 ++++++++++++------------
 tcg/riscv/tcg-target.c.inc   | 14 +++++++-------
 tcg/s390/tcg-target.c.inc    | 18 +++++++++---------
 tcg/sparc/tcg-target.c.inc   | 16 ++++++++--------
 tcg/tci/tcg-target.c.inc     |  2 +-
 11 files changed, 91 insertions(+), 93 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
 typedef struct TCGArgConstraint {
     uint16_t ct;
     uint8_t alias_index;
-    union {
-        TCGRegSet regs;
-    } u;
+    TCGRegSet regs;
 } TCGArgConstraint;
 
 #define TCG_MAX_OP_ARGS 16
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
             return 0;
         n = 0;
         for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
-            if (tcg_regset_test_reg(arg_ct->u.regs, i))
+            if (tcg_regset_test_reg(arg_ct->regs, i))
                 n++;
         }
     }
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
             /* Incomplete TCGTargetOpDef entry. */
             tcg_debug_assert(ct_str != NULL);
 
-            def->args_ct[i].u.regs = 0;
+            def->args_ct[i].regs = 0;
             def->args_ct[i].ct = 0;
             while (*ct_str != '\0') {
                 switch(*ct_str) {
@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
                     pset = la_temp_pref(ts);
                     set = *pset;
 
-                    set &= ct->u.regs;
+                    set &= ct->regs;
                     if (ct->ct & TCG_CT_IALIAS) {
                         set &= op->output_pref[ct->alias_index];
                     }
                     /* If the combination is not possible, restart.  */
                     if (set == 0) {
-                        set = ct->u.regs;
+                        set = ct->regs;
                     }
                     *pset = set;
                 }
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
         return;
     }
 
-    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
-    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
+    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
+    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
 
     /* Allocate the output register now.  */
     if (ots->val_type != TEMP_VAL_REG) {
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             }
         }
 
-        temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);
+        temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
         reg = ts->reg;
 
-        if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
+        if (tcg_regset_test_reg(arg_ct->regs, reg)) {
             /* nothing to do : the constraint is satisfied */
         } else {
         allocate_in_reg:
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                and move the temporary register into it */
             temp_load(s, ts, tcg_target_available_regs[ts->type],
                       i_allocated_regs, 0);
-            reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
+            reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
                                 o_preferred_regs, ts->indirect_base);
             if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
                 /*
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                 && !const_args[arg_ct->alias_index]) {
                 reg = new_args[arg_ct->alias_index];
             } else if (arg_ct->ct & TCG_CT_NEWREG) {
-                reg = tcg_reg_alloc(s, arg_ct->u.regs,
+                reg = tcg_reg_alloc(s, arg_ct->regs,
                                     i_allocated_regs | o_allocated_regs,
                                     op->output_pref[k], ts->indirect_base);
             } else {
-                reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
+                reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
                                     op->output_pref[k], ts->indirect_base);
             }
             tcg_regset_set_reg(o_allocated_regs, reg);
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'r': /* general registers */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs |= 0xffffffffu;
+        ct->regs |= 0xffffffffu;
         break;
     case 'w': /* advsimd registers */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs |= 0xffffffff00000000ull;
+        ct->regs |= 0xffffffff00000000ull;
         break;
     case 'l': /* qemu_ld / qemu_st address, data_reg */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffffu;
+        ct->regs = 0xffffffffu;
 #ifdef CONFIG_SOFTMMU
         /* x0 and x1 will be overwritten when reading the tlb entry,
            and x2, and x3 for helper args, better to avoid using them. */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
 #endif
         break;
     case 'A': /* Valid for arithmetic immediate (positive or negative).  */
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
+        ct->regs = 0xffff;
         break;
 
     /* qemu_ld address */
     case 'l':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
+        ct->regs = 0xffff;
 #ifdef CONFIG_SOFTMMU
         /* r0-r2,lr will be overwritten when reading the tlb entry,
            so don't use these. */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
 #endif
         break;
 
     /* qemu_st address & data */
     case 's':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
+        ct->regs = 0xffff;
         /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
            and r0-r1 doing the byte swapping, so don't use these. */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
 #if defined(CONFIG_SOFTMMU)
         /* Avoid clashes with registers being used for helper args */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
 #if TARGET_LONG_BITS == 64
         /* Avoid clashes with registers being used for helper args */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #endif
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
 #endif
         break;
 
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch(*ct_str++) {
     case 'a':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
+        tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
         break;
     case 'b':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
+        tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
         break;
     case 'c':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
+        tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
         break;
     case 'd':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
+        tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
         break;
     case 'S':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
+        tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
         break;
     case 'D':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
+        tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
         break;
     case 'q':
         /* A register that can be used as a byte operand.  */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
+        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
         break;
     case 'Q':
         /* A register with an addressable second byte (e.g. %ah).  */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xf;
+        ct->regs = 0xf;
         break;
     case 'r':
         /* A general register.  */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs |= ALL_GENERAL_REGS;
+        ct->regs |= ALL_GENERAL_REGS;
         break;
     case 'W':
         /* With TZCNT/LZCNT, we can have operand-size as an input.  */
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     case 'x':
         /* A vector register.  */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs |= ALL_VECTOR_REGS;
+        ct->regs |= ALL_VECTOR_REGS;
         break;
 
         /* qemu_ld/st address constraint */
     case 'L':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
+        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
         break;
 
     case 'e':
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch(*ct_str++) {
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         break;
     case 'L': /* qemu_ld input arg constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
+        ct->regs = 0xffffffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
 #if defined(CONFIG_SOFTMMU)
         if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
+            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
         }
 #endif
         break;
     case 'S': /* qemu_st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
+        ct->regs = 0xffffffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
 #if defined(CONFIG_SOFTMMU)
         if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
-            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
+            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
+            tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
         } else {
-            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
+            tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
         }
 #endif
         break;
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'A': case 'B': case 'C': case 'D':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
+        tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
         break;
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         break;
     case 'v':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff00000000ull;
+        ct->regs = 0xffffffff00000000ull;
         break;
     case 'L':                   /* qemu_ld constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+        ct->regs = 0xffffffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #ifdef CONFIG_SOFTMMU
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
 #endif
         break;
     case 'S':                   /* qemu_st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+        ct->regs = 0xffffffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #ifdef CONFIG_SOFTMMU
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
 #endif
         break;
     case 'I':
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         break;
     case 'L':
         /* qemu_ld/qemu_st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
 #if defined(CONFIG_SOFTMMU)
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
 #endif
         break;
     case 'I':
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'r':                  /* all registers */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
+        ct->regs = 0xffff;
         break;
     case 'L':                  /* qemu_ld/st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
+        ct->regs = 0xffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
         break;
     case 'a':                  /* force R2 for division */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
+        ct->regs = 0;
+        tcg_regset_set_reg(ct->regs, TCG_REG_R2);
         break;
     case 'b':                  /* force R3 for division */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
+        ct->regs = 0;
+        tcg_regset_set_reg(ct->regs, TCG_REG_R3);
         break;
     case 'A':
         ct->ct |= TCG_CT_CONST_S33;
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         break;
     case 'R':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = ALL_64;
+        ct->regs = ALL_64;
         break;
     case 'A': /* qemu_ld/st address constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
+        ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
     reserve_helpers:
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
         break;
     case 's': /* qemu_st data 32-bit constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         goto reserve_helpers;
     case 'S': /* qemu_st data 64-bit constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = ALL_64;
+        ct->regs = ALL_64;
         goto reserve_helpers;
     case 'I':
         ct->ct |= TCG_CT_CONST_S11;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     case 'L':                   /* qemu_ld constraint */
     case 'S':                   /* qemu_st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
+        ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
         break;
     default:
         return NULL;
-- 
2.25.1

This uses an existing hole in the TCGArgConstraint structure
and will be convenient for keeping the data in one place.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h |  2 +-
 tcg/tcg.c         | 35 +++++++++++++++++------------------
 2 files changed, 18 insertions(+), 19 deletions(-)

This wasn't actually used for anything, really.  All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
 #define TCG_CT_ALIAS  0x80
 #define TCG_CT_IALIAS 0x40
 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
-#define TCG_CT_REG    0x01
 #define TCG_CT_CONST  0x02 /* any constant of register size */
 
 typedef struct TCGArgConstraint {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
 /* we give more priority to constraints with less registers */
 static int get_constraint_priority(const TCGOpDef *def, int k)
 {
-    const TCGArgConstraint *arg_ct;
+    const TCGArgConstraint *arg_ct = &def->args_ct[k];
+    int n;
 
-    int i, n;
-    arg_ct = &def->args_ct[k];
     if (arg_ct->ct & TCG_CT_ALIAS) {
         /* an alias is equivalent to a single register */
         n = 1;
     } else {
-        if (!(arg_ct->ct & TCG_CT_REG))
-            return 0;
-        n = 0;
-        for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
-            if (tcg_regset_test_reg(arg_ct->regs, i))
-                n++;
-        }
+        n = ctpop64(arg_ct->regs);
     }
     return TCG_TARGET_NB_REGS - n + 1;
 }
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                         int oarg = *ct_str - '0';
                         tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
                         tcg_debug_assert(oarg < def->nb_oargs);
-                        tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
+                        tcg_debug_assert(def->args_ct[oarg].regs != 0);
                         /* TCG_CT_ALIAS is for the output arguments.
                            The input is tagged with TCG_CT_IALIAS. */
                         def->args_ct[i] = def->args_ct[oarg];
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r': /* general registers */
-        ct->ct |= TCG_CT_REG;
         ct->regs |= 0xffffffffu;
         break;
     case 'w': /* advsimd registers */
-        ct->ct |= TCG_CT_REG;
         ct->regs |= 0xffffffff00000000ull;
         break;
     case 'l': /* qemu_ld / qemu_st address, data_reg */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffffu;
 #ifdef CONFIG_SOFTMMU
         /* x0 and x1 will be overwritten when reading the tlb entry,
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
         break;
 
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
         break;
 
     /* qemu_ld address */
     case 'l':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
 #ifdef CONFIG_SOFTMMU
         /* r0-r2,lr will be overwritten when reading the tlb entry,
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 
     /* qemu_st address & data */
     case 's':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
         /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
            and r0-r1 doing the byte swapping, so don't use these. */
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch(*ct_str++) {
     case 'a':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
         break;
     case 'b':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
         break;
     case 'c':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
         break;
     case 'd':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
         break;
     case 'S':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
         break;
     case 'D':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
         break;
     case 'q':
         /* A register that can be used as a byte operand.  */
-        ct->ct |= TCG_CT_REG;
         ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
         break;
     case 'Q':
         /* A register with an addressable second byte (e.g. %ah).  */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xf;
         break;
     case 'r':
         /* A general register.  */
-        ct->ct |= TCG_CT_REG;
         ct->regs |= ALL_GENERAL_REGS;
         break;
     case 'W':
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
         break;
     case 'x':
         /* A vector register.  */
-        ct->ct |= TCG_CT_REG;
         ct->regs |= ALL_VECTOR_REGS;
         break;
 
         /* qemu_ld/st address constraint */
     case 'L':
-        ct->ct |= TCG_CT_REG;
         ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
         tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch(*ct_str++) {
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         break;
     case 'L': /* qemu_ld input arg constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
 #if defined(CONFIG_SOFTMMU)
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 #endif
         break;
     case 'S': /* qemu_st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
 #if defined(CONFIG_SOFTMMU)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'A': case 'B': case 'C': case 'D':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
         break;
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         break;
     case 'v':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff00000000ull;
         break;
     case 'L':                   /* qemu_ld constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #ifdef CONFIG_SOFTMMU
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 #endif
         break;
     case 'S':                   /* qemu_st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #ifdef CONFIG_SOFTMMU
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         break;
     case 'L':
         /* qemu_ld/qemu_st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
 #if defined(CONFIG_SOFTMMU)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r':                  /* all registers */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
         break;
     case 'L':                  /* qemu_ld/st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
         tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
         break;
     case 'a':                  /* force R2 for division */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0;
         tcg_regset_set_reg(ct->regs, TCG_REG_R2);
         break;
     case 'b':                  /* force R3 for division */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0;
         tcg_regset_set_reg(ct->regs, TCG_REG_R3);
         break;
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         break;
     case 'R':
-        ct->ct |= TCG_CT_REG;
         ct->regs = ALL_64;
         break;
     case 'A': /* qemu_ld/st address constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
     reserve_helpers:
         tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
         tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
         break;
     case 's': /* qemu_st data 32-bit constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         goto reserve_helpers;
     case 'S': /* qemu_st data 64-bit constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = ALL_64;
         goto reserve_helpers;
     case 'I':
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     case 'r':
     case 'L':                   /* qemu_ld constraint */
     case 'S':                   /* qemu_st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
         break;
     default:
-- 
2.25.1

These are easier to set and test when they have their own fields.
Reduce the size of alias_index and sort_index to 4 bits, which is
sufficient for TCG_MAX_OP_ARGS.  This leaves only the bits indicating
constants within the ct field.

Move all initialization to allocation time, rather than init
individual fields in process_op_defs.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h | 14 +++++++-------
 tcg/tcg.c         | 28 ++++++++++++----------------
 2 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void);
 void tcg_dump_info(void);
 void tcg_dump_op_count(void);
 
-#define TCG_CT_ALIAS  0x80
-#define TCG_CT_IALIAS 0x40
-#define TCG_CT_NEWREG 0x20 /* output requires a new register */
-#define TCG_CT_CONST  0x02 /* any constant of register size */
+#define TCG_CT_CONST  1 /* any constant of register size */
 
 typedef struct TCGArgConstraint {
-    uint16_t ct;
-    uint8_t alias_index;
-    uint8_t sort_index;
+    unsigned ct : 16;
+    unsigned alias_index : 4;
+    unsigned sort_index : 4;
+    bool oalias : 1;
+    bool ialias : 1;
+    bool newreg : 1;
     TCGRegSet regs;
 } TCGArgConstraint;
 
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
         total_args += n;
     }
 
-    args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
+    args_ct = g_new0(TCGArgConstraint, total_args);
 
     for(op = 0; op < NB_OPS; op++) {
         def = &tcg_op_defs[op];
@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
     const TCGArgConstraint *arg_ct = &def->args_ct[k];
     int n;
 
-    if (arg_ct->ct & TCG_CT_ALIAS) {
+    if (arg_ct->oalias) {
         /* an alias is equivalent to a single register */
         n = 1;
     } else {
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
             /* Incomplete TCGTargetOpDef entry. */
             tcg_debug_assert(ct_str != NULL);
 
-            def->args_ct[i].regs = 0;
-            def->args_ct[i].ct = 0;
             while (*ct_str != '\0') {
                 switch(*ct_str) {
                 case '0' ... '9':
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                         tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
                         tcg_debug_assert(oarg < def->nb_oargs);
                         tcg_debug_assert(def->args_ct[oarg].regs != 0);
-                        /* TCG_CT_ALIAS is for the output arguments.
-                           The input is tagged with TCG_CT_IALIAS. */
                         def->args_ct[i] = def->args_ct[oarg];
-                        def->args_ct[oarg].ct |= TCG_CT_ALIAS;
+                        /* The output sets oalias.  */
+                        def->args_ct[oarg].oalias = true;
                         def->args_ct[oarg].alias_index = i;
-                        def->args_ct[i].ct |= TCG_CT_IALIAS;
+                        /* The input sets ialias. */
+                        def->args_ct[i].ialias = true;
                         def->args_ct[i].alias_index = oarg;
                     }
                     ct_str++;
                     break;
                 case '&':
-                    def->args_ct[i].ct |= TCG_CT_NEWREG;
+                    def->args_ct[i].newreg = true;
                     ct_str++;
                     break;
                 case 'i':
@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
                     set = *pset;
 
                     set &= ct->regs;
-                    if (ct->ct & TCG_CT_IALIAS) {
+                    if (ct->ialias) {
                         set &= op->output_pref[ct->alias_index];
                     }
                     /* If the combination is not possible, restart.  */
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
         }
 
         i_preferred_regs = o_preferred_regs = 0;
-        if (arg_ct->ct & TCG_CT_IALIAS) {
+        if (arg_ct->ialias) {
             o_preferred_regs = op->output_pref[arg_ct->alias_index];
             if (ts->fixed_reg) {
                 /* if fixed register, we must allocate a new register
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                     reg = ts->reg;
                     for (k2 = 0 ; k2 < k ; k2++) {
                         i2 = def->args_ct[nb_oargs + k2].sort_index;
-                        if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
-                            reg == new_args[i2]) {
+                        if (def->args_ct[i2].ialias && reg == new_args[i2]) {
                             goto allocate_in_reg;
                         }
                     }
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             /* ENV should not be modified.  */
             tcg_debug_assert(!ts->fixed_reg);
 
-            if ((arg_ct->ct & TCG_CT_ALIAS)
-                && !const_args[arg_ct->alias_index]) {
+            if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
                 reg = new_args[arg_ct->alias_index];
-            } else if (arg_ct->ct & TCG_CT_NEWREG) {
+            } else if (arg_ct->newreg) {
                 reg = tcg_reg_alloc(s, arg_ct->regs,
                                     i_allocated_regs | o_allocated_regs,
                                     op->output_pref[k], ts->indirect_base);
-- 
2.25.1

The definition of INDEX_op_dupi_vec is that it operates on
units of tcg_target_ulong -- in this case 32 bits.  It does
not work to use this for a uint64_t value that happens to be
small enough to fit in tcg_target_ulong.

Fixes: d2fd745fe8b
Fixes: db432672dc5
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg-op-vec.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
 
 void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
 {
-    if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
-        do_dupi_vec(r, MO_32, a);
-    } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
+    if (TCG_TARGET_REG_BITS == 64) {
         do_dupi_vec(r, MO_64, a);
+    } else if (a == dup_const(MO_32, a)) {
+        do_dupi_vec(r, MO_32, a);
     } else {
         TCGv_i64 c = tcg_const_i64(a);
         tcg_gen_dup_i64_vec(MO_64, r, c);
@@ -XXX,XX +XXX,XX @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
 
 void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
 {
-    do_dupi_vec(r, MO_REG, dup_const(vece, a));
+    if (vece == MO_64) {
+        tcg_gen_dup64i_vec(r, a);
+    } else {
+        do_dupi_vec(r, MO_REG, dup_const(vece, a));
+    }
 }
 
 void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
-- 
2.25.1

When the two arguments are identical, this can be reduced to
dup_vec or to mov_vec from a tcg_constant_vec.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/optimize.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/tcg/optimize.c b/tcg/optimize.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
             }
             goto do_default;
 
+        case INDEX_op_dup2_vec:
+            assert(TCG_TARGET_REG_BITS == 32);
+            if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+                tmp = arg_info(op->args[1])->val;
+                if (tmp == arg_info(op->args[2])->val) {
+                    tcg_opt_gen_movi(s, op, op->args[0], tmp);
+                    break;
+                }
+            } else if (args_are_copies(op->args[1], op->args[2])) {
+                op->opc = INDEX_op_dup_vec;
+                TCGOP_VECE(op) = MO_32;
+                nb_iargs = 1;
+            }
+            goto do_default;
+
         CASE_OP_32_64(not):
         CASE_OP_32_64(neg):
         CASE_OP_32_64(ext8s):
-- 
2.25.1

The cmp_vec opcode is mandatory; this symbol is unused.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.h | 1 -
 tcg/i386/tcg-target.h    | 1 -
 tcg/ppc/tcg-target.h     | 1 -
 3 files changed, 3 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
-#define TCG_TARGET_HAS_cmp_vec          1
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          1
 #define TCG_TARGET_HAS_shv_vec          have_avx2
-#define TCG_TARGET_HAS_cmp_vec          1
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
-#define TCG_TARGET_HAS_cmp_vec          1
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
-- 
2.25.1

From: Kele Huang <kele.hwang@gmail.com>

Detect all MIPS store instructions in cpu_signal_handler for all available
MIPS versions, and set is_write if encountering such store instructions.

This fixed the error while dealing with self-modified code for MIPS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kele Huang <kele.hwang@gmail.com>
Signed-off-by: Xu Zou <iwatchnima@gmail.com>
Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>
[rth: Use uintptr_t for pc to fix n32 build error.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/user-exec.c | 43 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
 
 #elif defined(__mips__)
 
+#if defined(__misp16) || defined(__mips_micromips)
+#error "Unsupported encoding"
+#endif
+
 int cpu_signal_handler(int host_signum, void *pinfo,
                        void *puc)
 {
     siginfo_t *info = pinfo;
     ucontext_t *uc = puc;
-    greg_t pc = uc->uc_mcontext.pc;
-    int is_write;
+    uintptr_t pc = uc->uc_mcontext.pc;
+    uint32_t insn = *(uint32_t *)pc;
+    int is_write = 0;
+
+    /* Detect all store instructions at program counter. */
+    switch((insn >> 26) & 077) {
+    case 050: /* SB */
+    case 051: /* SH */
+    case 052: /* SWL */
+    case 053: /* SW */
+    case 054: /* SDL */
+    case 055: /* SDR */
+    case 056: /* SWR */
+    case 070: /* SC */
+    case 071: /* SWC1 */
+    case 074: /* SCD */
+    case 075: /* SDC1 */
+    case 077: /* SD */
+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
+    case 072: /* SWC2 */
+    case 076: /* SDC2 */
+#endif
+        is_write = 1;
+        break;
+    case 023: /* COP1X */
+        /* Required in all versions of MIPS64 since
+           MIPS64r1 and subsequent versions of MIPS32r2. */
+        switch (insn & 077) {
+        case 010: /* SWXC1 */
+        case 011: /* SDXC1 */
+        case 015: /* SUXC1 */
+            is_write = 1;
+        }
+        break;
+    }
 
-    /* XXX: compute is_write */
-    is_write = 0;
     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 }
 
-- 
2.25.1

The following changes since commit 1cbd2d914939ee6028e9688d4ba859a528c28405:

Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2021-06-04 13:38:49 +0100)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210604

for you to fetch changes up to 0006039e29b9e6118beab300146f7c4931f7a217:

tcg/arm: Implement TCG_TARGET_HAS_rotv_vec (2021-06-04 11:50:11 -0700)

----------------------------------------------------------------
Host vector support for arm neon.

----------------------------------------------------------------
Richard Henderson (15):
      tcg: Change parameters for tcg_target_const_match
      tcg/arm: Add host vector framework
      tcg/arm: Implement tcg_out_ld/st for vector types
      tcg/arm: Implement tcg_out_mov for vector types
      tcg/arm: Implement tcg_out_dup*_vec
      tcg/arm: Implement minimal vector operations
      tcg/arm: Implement andc, orc, abs, neg, not vector operations
      tcg/arm: Implement TCG_TARGET_HAS_shi_vec
      tcg/arm: Implement TCG_TARGET_HAS_mul_vec
      tcg/arm: Implement TCG_TARGET_HAS_sat_vec
      tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
      tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
      tcg/arm: Implement TCG_TARGET_HAS_shv_vec
      tcg/arm: Implement TCG_TARGET_HAS_roti_vec
      tcg/arm: Implement TCG_TARGET_HAS_rotv_vec

Change the return value to bool, because that's what is should
have been from the start.  Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.

Change the value argument to int64_t.  We will need the extra
width for 32-bit hosts wanting to match vector constants.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg.c                    | 5 ++---
 tcg/aarch64/tcg-target.c.inc | 5 +----
 tcg/arm/tcg-target.c.inc     | 5 +----
 tcg/i386/tcg-target.c.inc    | 4 +---
 tcg/mips/tcg-target.c.inc    | 5 +----
 tcg/ppc/tcg-target.c.inc     | 4 +---
 tcg/riscv/tcg-target.c.inc   | 4 +---
 tcg/s390/tcg-target.c.inc    | 5 +----
 tcg/sparc/tcg-target.c.inc   | 5 +----
 tcg/tci/tcg-target.c.inc     | 6 ++----
 10 files changed, 12 insertions(+), 36 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
                         TCGReg base, intptr_t ofs);
 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target);
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct);
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct);
 #ifdef TCG_TARGET_NEED_LDST_LABELS
 static int tcg_out_ldst_finalize(TCGContext *s);
 #endif
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
         ts = arg_temp(arg);
 
         if (ts->val_type == TEMP_VAL_CONST
-            && tcg_target_const_match(ts->val, ts->type, arg_ct)) {
+            && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) {
             /* constant is OK for instruction */
             const_args[i] = 1;
             new_args[i] = ts->val;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
     }
 }
 
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
  * mov operand2:     values represented with x << (2 * y), x < 0x100
  * add, sub, eor...: ditto
  */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct;
-    ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     } else if ((ct & TCG_CT_CONST_ARM) && check_fit_imm(val)) {
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool is_p2m1(tcg_target_long val)
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct;
-    ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
 }
 
 /* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
 }
 
 /* test if a constant matches the constraint */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
 }
 
 /* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type,
 }
 
 /* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                         const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    int ct = arg_ct->ct;
-
     if (ct & TCG_CT_CONST) {
         return 1;
     }
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
 }
 
 /* Test if a constant matches the constraint. */
-static int tcg_target_const_match(tcg_target_long val, TCGType type,
-                                  const TCGArgConstraint *arg_ct)
+static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
 {
-    /* No need to return 0 or 1, 0 or != 0 is good enough. */
-    return arg_ct->ct & TCG_CT_CONST;
+    return ct & TCG_CT_CONST;
 }
 
 static void tcg_target_init(TCGContext *s)
-- 
2.25.1

Add registers and function stubs.  The functionality
is disabled via use_neon_instructions defined to 0.

We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |   4 ++
 tcg/arm/tcg-target-con-str.h |   1 +
 tcg/arm/tcg-target.h         |  48 ++++++++++++--
 tcg/arm/tcg-target.opc.h     |  12 ++++
 tcg/arm/tcg-target.c.inc     | 117 +++++++++++++++++++++++++++++------
 5 files changed, 158 insertions(+), 24 deletions(-)
 create mode 100644 tcg/arm/tcg-target.opc.h

diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-set.h
+++ b/tcg/arm/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@ C_O0_I1(r)
 C_O0_I2(r, r)
 C_O0_I2(r, rIN)
 C_O0_I2(s, s)
+C_O0_I2(w, r)
 C_O0_I3(s, s, s)
 C_O0_I4(r, r, rI, rI)
 C_O0_I4(s, s, s, s)
 C_O1_I1(r, l)
 C_O1_I1(r, r)
+C_O1_I1(w, r)
+C_O1_I1(w, wr)
 C_O1_I2(r, 0, rZ)
 C_O1_I2(r, l, l)
 C_O1_I2(r, r, r)
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIK)
 C_O1_I2(r, r, rIN)
 C_O1_I2(r, r, ri)
 C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, w, w)
 C_O1_I4(r, r, r, rI, rI)
 C_O1_I4(r, r, rIN, rIK, 0)
 C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-str.h
+++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@
 REGS('r', ALL_GENERAL_REGS)
 REGS('l', ALL_QLOAD_REGS)
 REGS('s', ALL_QSTORE_REGS)
+REGS('w', ALL_VECTOR_REGS)
 
 /*
  * Define constraint letters for constants:
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
     TCG_REG_R13,
     TCG_REG_R14,
     TCG_REG_PC,
+
+    TCG_REG_Q0,
+    TCG_REG_Q1,
+    TCG_REG_Q2,
+    TCG_REG_Q3,
+    TCG_REG_Q4,
+    TCG_REG_Q5,
+    TCG_REG_Q6,
+    TCG_REG_Q7,
+    TCG_REG_Q8,
+    TCG_REG_Q9,
+    TCG_REG_Q10,
+    TCG_REG_Q11,
+    TCG_REG_Q12,
+    TCG_REG_Q13,
+    TCG_REG_Q14,
+    TCG_REG_Q15,
+
+    TCG_AREG0 = TCG_REG_R6,
+    TCG_REG_CALL_STACK = TCG_REG_R13,
 } TCGReg;
 
-#define TCG_TARGET_NB_REGS 16
+#define TCG_TARGET_NB_REGS 32
 
 #ifdef __ARM_ARCH_EXT_IDIV__
 #define use_idiv_instructions  1
 #else
 extern bool use_idiv_instructions;
 #endif
-
+#define use_neon_instructions  0
 
 /* used for function call generation */
-#define TCG_REG_CALL_STACK		TCG_REG_R13
 #define TCG_TARGET_STACK_ALIGN		8
 #define TCG_TARGET_CALL_ALIGN_ARGS	1
 #define TCG_TARGET_CALL_STACK_OFFSET	0
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
 #define TCG_TARGET_HAS_direct_jump      0
 #define TCG_TARGET_HAS_qemu_st8_i32     0
 
-enum {
-    TCG_AREG0 = TCG_REG_R6,
-};
+#define TCG_TARGET_HAS_v64              use_neon_instructions
+#define TCG_TARGET_HAS_v128             use_neon_instructions
+#define TCG_TARGET_HAS_v256             0
+
+#define TCG_TARGET_HAS_andc_vec         0
+#define TCG_TARGET_HAS_orc_vec          0
+#define TCG_TARGET_HAS_not_vec          0
+#define TCG_TARGET_HAS_neg_vec          0
+#define TCG_TARGET_HAS_abs_vec          0
+#define TCG_TARGET_HAS_roti_vec         0
+#define TCG_TARGET_HAS_rots_vec         0
+#define TCG_TARGET_HAS_rotv_vec         0
+#define TCG_TARGET_HAS_shi_vec          0
+#define TCG_TARGET_HAS_shs_vec          0
+#define TCG_TARGET_HAS_shv_vec          0
+#define TCG_TARGET_HAS_mul_vec          0
+#define TCG_TARGET_HAS_sat_vec          0
+#define TCG_TARGET_HAS_minmax_vec       0
+#define TCG_TARGET_HAS_bitsel_vec       0
+#define TCG_TARGET_HAS_cmpsel_vec       0
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_HAS_MEMORY_BSWAP     1
diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tcg/arm/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Copyright (c) 2019 Linaro
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version.
+ *
+ * See the COPYING file in the top-level directory for details.
+ *
+ * Target-specific opcodes for host vector expansion.  These will be
+ * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
+ * consider these to be UNSPEC with names.
+ */
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ bool use_idiv_instructions;
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
-    "%r0",
-    "%r1",
-    "%r2",
-    "%r3",
-    "%r4",
-    "%r5",
-    "%r6",
-    "%r7",
-    "%r8",
-    "%r9",
-    "%r10",
-    "%r11",
-    "%r12",
-    "%r13",
-    "%r14",
-    "%pc",
+    "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
+    "%r8",  "%r9",  "%r10", "%r11", "%r12", "%sp",  "%r14", "%pc",
+    "%q0",  "%q1",  "%q2",  "%q3",  "%q4",  "%q5",  "%q6",  "%q7",
+    "%q8",  "%q9",  "%q10", "%q11", "%q12", "%q13", "%q14", "%q15",
 };
 #endif
 
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_reg_alloc_order[] = {
     TCG_REG_R3,
     TCG_REG_R12,
     TCG_REG_R14,
+
+    TCG_REG_Q0,
+    TCG_REG_Q1,
+    TCG_REG_Q2,
+    TCG_REG_Q3,
+    /* Q4 - Q7 are call-saved, and skipped. */
+    TCG_REG_Q8,
+    TCG_REG_Q9,
+    TCG_REG_Q10,
+    TCG_REG_Q11,
+    TCG_REG_Q12,
+    TCG_REG_Q13,
+    TCG_REG_Q14,
+    TCG_REG_Q15,
 };
 
 static const int tcg_target_call_iarg_regs[4] = {
@@ -XXX,XX +XXX,XX @@ static const int tcg_target_call_oarg_regs[2] = {
 };
 
 #define TCG_REG_TMP  TCG_REG_R12
+#define TCG_VEC_TMP  TCG_REG_Q15
 
 enum arm_cond_code_e {
     COND_EQ = 0x0,
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_ZERO 0x800
 
 #define ALL_GENERAL_REGS  0xffffu
+#define ALL_VECTOR_REGS   0xffff0000u
 
 /*
  * r0-r2 will be overwritten when reading the tlb entry (softmmu only)
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_qemu_st_i64:
         return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
 
+    case INDEX_op_st_vec:
+        return C_O0_I2(w, r);
+    case INDEX_op_ld_vec:
+    case INDEX_op_dupm_vec:
+        return C_O1_I1(w, r);
+    case INDEX_op_dup_vec:
+        return C_O1_I1(w, wr);
+    case INDEX_op_dup2_vec:
+    case INDEX_op_add_vec:
+    case INDEX_op_sub_vec:
+    case INDEX_op_xor_vec:
+    case INDEX_op_or_vec:
+    case INDEX_op_and_vec:
+    case INDEX_op_cmp_vec:
+        return C_O1_I2(w, w, w);
+
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
 {
     /* Only probe for the platform and capabilities if we havn't already
        determined maximum values at compile time.  */
-#ifndef use_idiv_instructions
+#if !defined(use_idiv_instructions) || !defined(use_neon_instructions)
     {
         unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+#ifndef use_idiv_instructions
         use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
+#endif
+#ifndef use_neon_instructions
+        use_neon_instructions = (hwcap & HWCAP_ARM_NEON) != 0;
+#endif
     }
 #endif
+
     if (__ARM_ARCH < 7) {
         const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
         if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
         }
     }
 
-    tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
+    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
 
     tcg_target_call_clobber_regs = 0;
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
 
+    if (use_neon_instructions) {
+        tcg_target_available_regs[TCG_TYPE_V64]  = ALL_VECTOR_REGS;
+        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
+
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q0);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q1);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q2);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q3);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q8);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q9);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q10);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q11);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q12);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q13);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q14);
+        tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_Q15);
+    }
+
     s->reserved_regs = 0;
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
     tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
+    tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
 }
 
 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+                            TCGReg rd, TCGReg rs)
+{
+    g_assert_not_reached();
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+                             TCGReg rd, TCGReg base, intptr_t offset)
+{
+    g_assert_not_reached();
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+                             TCGReg rd, int64_t v64)
+{
+    g_assert_not_reached();
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+                           unsigned vecl, unsigned vece,
+                           const TCGArg *args, const int *const_args)
+{
+    g_assert_not_reached();
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+    return 0;
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+                       TCGArg a0, ...)
+{
+    g_assert_not_reached();
+}
+
 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
 {
     int i;
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 70 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 64 insertions(+), 6 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_NOP_v6k   = 0xe320f000,
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
+
+    INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
+    INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
 } ARMInsn;
 
 #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
     }
 }
 
+/*
+ * Note that TCGReg references Q-registers.
+ * Q-regno = 2 * D-regno, so shift left by 1 whlie inserting.
+ */
+static uint32_t encode_vd(TCGReg rd)
+{
+    tcg_debug_assert(rd >= TCG_REG_Q0);
+    return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
+}
+
+static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
+                          TCGReg rd, TCGReg rn, int offset)
+{
+    if (offset != 0) {
+        if (check_fit_imm(offset) || check_fit_imm(-offset)) {
+            tcg_out_dat_rIN(s, COND_AL, ARITH_ADD, ARITH_SUB,
+                            TCG_REG_TMP, rn, offset, true);
+        } else {
+            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP, offset);
+            tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
+                            TCG_REG_TMP, TCG_REG_TMP, rn, 0);
+        }
+        rn = TCG_REG_TMP;
+    }
+    tcg_out32(s, insn | (rn << 16) | encode_vd(rd) | 0xf);
+}
+
 #ifdef CONFIG_SOFTMMU
 #include "../tcg-ldst.c.inc"
 
@@ -XXX,XX +XXX,XX @@ static void tcg_target_init(TCGContext *s)
     tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
 }
 
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
-                              TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+                       TCGReg arg1, intptr_t arg2)
 {
-    tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+    switch (type) {
+    case TCG_TYPE_I32:
+        tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V64:
+        /* regs 1; size 8; align 8 */
+        tcg_out_vldst(s, INSN_VLD1 | 0x7d0, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V128:
+        /* regs 2; size 8; align 16 */
+        tcg_out_vldst(s, INSN_VLD1 | 0xae0, arg, arg1, arg2);
+        return;
+    default:
+        g_assert_not_reached();
+    }
 }
 
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
-                              TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+                       TCGReg arg1, intptr_t arg2)
 {
-    tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+    switch (type) {
+    case TCG_TYPE_I32:
+        tcg_out_st32(s, COND_AL, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V64:
+        /* regs 1; size 8; align 8 */
+        tcg_out_vldst(s, INSN_VST1 | 0x7d0, arg, arg1, arg2);
+        return;
+    case TCG_TYPE_V128:
+        /* regs 2; size 8; align 16 */
+        tcg_out_vldst(s, INSN_VST1 | 0xae0, arg, arg1, arg2);
+        return;
+    default:
+        g_assert_not_reached();
+    }
 }
 
 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 52 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 46 insertions(+), 6 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 
+    INSN_VORR      = 0xf2200110,
+
     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
 } ARMInsn;
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vd(TCGReg rd)
     return (extract32(rd, 3, 1) << 22) | (extract32(rd, 0, 3) << 13);
 }
 
+static uint32_t encode_vn(TCGReg rn)
+{
+    tcg_debug_assert(rn >= TCG_REG_Q0);
+    return (extract32(rn, 3, 1) << 7) | (extract32(rn, 0, 3) << 17);
+}
+
+static uint32_t encode_vm(TCGReg rm)
+{
+    tcg_debug_assert(rm >= TCG_REG_Q0);
+    return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
+}
+
+static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
+                          TCGReg d, TCGReg n, TCGReg m)
+{
+    tcg_out32(s, insn | (vece << 20) | (q << 6) |
+              encode_vd(d) | encode_vn(n) | encode_vm(m));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
     return false;
 }
 
-static inline bool tcg_out_mov(TCGContext *s, TCGType type,
-                               TCGReg ret, TCGReg arg)
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 {
-    tcg_out_mov_reg(s, COND_AL, ret, arg);
-    return true;
+    if (ret == arg) {
+        return true;
+    }
+    switch (type) {
+    case TCG_TYPE_I32:
+        if (ret < TCG_REG_Q0 && arg < TCG_REG_Q0) {
+            tcg_out_mov_reg(s, COND_AL, ret, arg);
+            return true;
+        }
+        return false;
+
+    case TCG_TYPE_V64:
+    case TCG_TYPE_V128:
+        /* "VMOV D,N" is an alias for "VORR D,N,N". */
+        tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
+        return true;
+
+    default:
+        g_assert_not_reached();
+    }
 }
 
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
-                                TCGReg ret, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+                         TCGReg ret, tcg_target_long arg)
 {
+    tcg_debug_assert(type == TCG_TYPE_I32);
+    tcg_debug_assert(ret < TCG_REG_Q0);
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
-- 
2.25.1

Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 283 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 275 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
 
     INSN_VORR      = 0xf2200110,
 
+    INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
+    INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
+    INSN_VLDR_D    = 0xed100b00,  /* VLDR.64 */
     INSN_VLD1      = 0xf4200000,  /* VLD1 (multiple single elements) */
+    INSN_VLD1R     = 0xf4a00c00,  /* VLD1 (single element to all lanes) */
     INSN_VST1      = 0xf4000000,  /* VST1 (multiple single elements) */
+    INSN_VMOVI     = 0xf2800010,  /* VMOV (immediate) */
 } ARMInsn;
 
 #define INSN_NOP   (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)
@@ -XXX,XX +XXX,XX @@ static const uint8_t tcg_cond_to_arm_cond[] = {
     [TCG_COND_GTU] = COND_HI,
 };
 
+static int encode_imm(uint32_t imm);
+
+/* TCG private relocation type: add with pc+imm8 */
+#define R_ARM_PC8  11
+
+/* TCG private relocation type: vldr with imm8 << 2 */
+#define R_ARM_PC11 12
+
 static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
 {
     const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
@@ -XXX,XX +XXX,XX @@ static bool reloc_pc13(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
     return false;
 }
 
+static bool reloc_pc11(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+{
+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+    ptrdiff_t offset = (tcg_ptr_byte_diff(target, src_rx) - 8) / 4;
+
+    if (offset >= -0xff && offset <= 0xff) {
+        tcg_insn_unit insn = *src_rw;
+        bool u = (offset >= 0);
+        if (!u) {
+            offset = -offset;
+        }
+        insn = deposit32(insn, 23, 1, u);
+        insn = deposit32(insn, 0, 8, offset);
+        *src_rw = insn;
+        return true;
+    }
+    return false;
+}
+
+static bool reloc_pc8(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
+{
+    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+    ptrdiff_t offset = tcg_ptr_byte_diff(target, src_rx) - 8;
+    int rot = encode_imm(offset);
+
+    if (rot >= 0) {
+        *src_rw = deposit32(*src_rw, 0, 12, rol32(offset, rot) | (rot << 7));
+        return true;
+    }
+    return false;
+}
+
 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
                         intptr_t value, intptr_t addend)
 {
     tcg_debug_assert(addend == 0);
-
-    if (type == R_ARM_PC24) {
+    switch (type) {
+    case R_ARM_PC24:
         return reloc_pc24(code_ptr, (const tcg_insn_unit *)value);
-    } else if (type == R_ARM_PC13) {
+    case R_ARM_PC13:
         return reloc_pc13(code_ptr, (const tcg_insn_unit *)value);
-    } else {
+    case R_ARM_PC11:
+        return reloc_pc11(code_ptr, (const tcg_insn_unit *)value);
+    case R_ARM_PC8:
+        return reloc_pc8(code_ptr, (const tcg_insn_unit *)value);
+    default:
         g_assert_not_reached();
     }
 }
@@ -XXX,XX +XXX,XX @@ static inline uint32_t rotl(uint32_t val, int n)
 
 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
    right-rotated by an even amount between 0 and 30. */
-static inline int encode_imm(uint32_t imm)
+static int encode_imm(uint32_t imm)
 {
     int shift;
 
@@ -XXX,XX +XXX,XX @@ static inline int check_fit_imm(uint32_t imm)
     return encode_imm(imm) >= 0;
 }
 
+/* Return true if v16 is a valid 16-bit shifted immediate.  */
+static bool is_shimm16(uint16_t v16, int *cmode, int *imm8)
+{
+    if (v16 == (v16 & 0xff)) {
+        *cmode = 0x8;
+        *imm8 = v16 & 0xff;
+        return true;
+    } else if (v16 == (v16 & 0xff00)) {
+        *cmode = 0xa;
+        *imm8 = v16 >> 8;
+        return true;
+    }
+    return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifted immediate.  */
+static bool is_shimm32(uint32_t v32, int *cmode, int *imm8)
+{
+    if (v32 == (v32 & 0xff)) {
+        *cmode = 0x0;
+        *imm8 = v32 & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff00)) {
+        *cmode = 0x2;
+        *imm8 = (v32 >> 8) & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff0000)) {
+        *cmode = 0x4;
+        *imm8 = (v32 >> 16) & 0xff;
+        return true;
+    } else if (v32 == (v32 & 0xff000000)) {
+        *cmode = 0x6;
+        *imm8 = v32 >> 24;
+        return true;
+    }
+    return false;
+}
+
+/* Return true if v32 is a valid 32-bit shifting ones immediate.  */
+static bool is_soimm32(uint32_t v32, int *cmode, int *imm8)
+{
+    if ((v32 & 0xffff00ff) == 0xff) {
+        *cmode = 0xc;
+        *imm8 = (v32 >> 8) & 0xff;
+        return true;
+    } else if ((v32 & 0xff00ffff) == 0xffff) {
+        *cmode = 0xd;
+        *imm8 = (v32 >> 16) & 0xff;
+        return true;
+    }
+    return false;
+}
+
+/*
+ * Return non-zero if v32 can be formed by MOVI+ORR.
+ * Place the parameters for MOVI in (cmode, imm8).
+ * Return the cmode for ORR; the imm8 can be had via extraction from v32.
+ */
+static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
+{
+    int i;
+
+    for (i = 6; i > 0; i -= 2) {
+        /* Mask out one byte we can add with ORR.  */
+        uint32_t tmp = v32 & ~(0xffu << (i * 4));
+        if (is_shimm32(tmp, cmode, imm8) ||
+            is_soimm32(tmp, cmode, imm8)) {
+            break;
+        }
+    }
+    return i;
+}
+
 /* Test if a constant matches the constraint.
  * TODO: define constraints for:
  *
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
               encode_vd(d) | encode_vn(n) | encode_vm(m));
 }
 
+static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
+                          int q, int op, int cmode, uint8_t imm8)
+{
+    tcg_out32(s, INSN_VMOVI | encode_vd(rd) | (q << 6) | (op << 5)
+              | (cmode << 8) | extract32(imm8, 0, 4)
+              | (extract32(imm8, 4, 3) << 16)
+              | (extract32(imm8, 7, 1) << 24));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi(TCGContext *s, TCGType type,
     tcg_out_movi32(s, COND_AL, ret, arg);
 }
 
+/* Type is always V128, with I64 elements.  */
+static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh)
+{
+    /* Move high element into place first. */
+    /* VMOV Dd+1, Ds */
+    tcg_out_vreg3(s, INSN_VORR | (1 << 12), 0, 0, rd, rh, rh);
+    /* Move low element into place; tcg_out_mov will check for nop. */
+    tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
+}
+
 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
                             TCGReg rd, TCGReg rs)
 {
-    g_assert_not_reached();
+    int q = type - TCG_TYPE_V64;
+
+    if (vece == MO_64) {
+        if (type == TCG_TYPE_V128) {
+            tcg_out_dup2_vec(s, rd, rs, rs);
+        } else {
+            tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
+        }
+    } else if (rs < TCG_REG_Q0) {
+        int b = (vece == MO_8);
+        int e = (vece == MO_16);
+        tcg_out32(s, INSN_VDUP_G | (b << 22) | (q << 21) | (e << 5) |
+                  encode_vn(rd) | (rs << 12));
+    } else {
+        int imm4 = 1 << vece;
+        tcg_out32(s, INSN_VDUP_S | (imm4 << 16) | (q << 6) |
+                  encode_vd(rd) | encode_vm(rs));
+    }
+    return true;
 }
 
 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg rd, TCGReg base, intptr_t offset)
 {
-    g_assert_not_reached();
+    if (vece == MO_64) {
+        tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
+        if (type == TCG_TYPE_V128) {
+            tcg_out_dup2_vec(s, rd, rd, rd);
+        }
+    } else {
+        int q = type - TCG_TYPE_V64;
+        tcg_out_vldst(s, INSN_VLD1R | (vece << 6) | (q << 5),
+                      rd, base, offset);
+    }
+    return true;
 }
 
 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
                              TCGReg rd, int64_t v64)
 {
-    g_assert_not_reached();
+    int q = type - TCG_TYPE_V64;
+    int cmode, imm8, i;
+
+    /* Test all bytes equal first.  */
+    if (vece == MO_8) {
+        tcg_out_vmovi(s, rd, q, 0, 0xe, v64);
+        return;
+    }
+
+    /*
+     * Test all bytes 0x00 or 0xff second.  This can match cases that
+     * might otherwise take 2 or 3 insns for MO_16 or MO_32 below.
+     */
+    for (i = imm8 = 0; i < 8; i++) {
+        uint8_t byte = v64 >> (i * 8);
+        if (byte == 0xff) {
+            imm8 |= 1 << i;
+        } else if (byte != 0) {
+            goto fail_bytes;
+        }
+    }
+    tcg_out_vmovi(s, rd, q, 1, 0xe, imm8);
+    return;
+ fail_bytes:
+
+    /*
+     * Tests for various replications.  For each element width, if we
+     * cannot find an expansion there's no point checking a larger
+     * width because we already know by replication it cannot match.
+     */
+    if (vece == MO_16) {
+        uint16_t v16 = v64;
+
+        if (is_shimm16(v16, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            return;
+        }
+        if (is_shimm16(~v16, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            return;
+        }
+
+        /*
+         * Otherwise, all remaining constants can be loaded in two insns:
+         * rd = v16 & 0xff, rd |= v16 & 0xff00.
+         */
+        tcg_out_vmovi(s, rd, q, 0, 0x8, v16 & 0xff);
+        tcg_out_vmovi(s, rd, q, 0, 0xb, v16 >> 8);   /* VORRI */
+        return;
+    }
+
+    if (vece == MO_32) {
+        uint32_t v32 = v64;
+
+        if (is_shimm32(v32, &cmode, &imm8) ||
+            is_soimm32(v32, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            return;
+        }
+        if (is_shimm32(~v32, &cmode, &imm8) ||
+            is_soimm32(~v32, &cmode, &imm8)) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            return;
+        }
+
+        /*
+         * Restrict the set of constants to those we can load with
+         * two instructions.  Others we load from the pool.
+         */
+        i = is_shimm32_pair(v32, &cmode, &imm8);
+        if (i) {
+            tcg_out_vmovi(s, rd, q, 0, cmode, imm8);
+            tcg_out_vmovi(s, rd, q, 0, i | 1, extract32(v32, i * 4, 8));
+            return;
+        }
+        i = is_shimm32_pair(~v32, &cmode, &imm8);
+        if (i) {
+            tcg_out_vmovi(s, rd, q, 1, cmode, imm8);
+            tcg_out_vmovi(s, rd, q, 1, i | 1, extract32(~v32, i * 4, 8));
+            return;
+        }
+    }
+
+    /*
+     * As a last resort, load from the constant pool.
+     */
+    if (!q || vece == MO_64) {
+        new_pool_l2(s, R_ARM_PC11, s->code_ptr, 0, v64, v64 >> 32);
+        /* VLDR Dd, [pc + offset] */
+        tcg_out32(s, INSN_VLDR_D | encode_vd(rd) | (0xf << 16));
+        if (q) {
+            tcg_out_dup2_vec(s, rd, rd, rd);
+        }
+    } else {
+        new_pool_label(s, (uint32_t)v64, R_ARM_PC8, s->code_ptr, 0);
+        /* add tmp, pc, offset */
+        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_TMP, TCG_REG_PC, 0);
+        tcg_out_dupm_vec(s, type, MO_32, rd, TCG_REG_TMP, 0);
+    }
 }
 
 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
-- 
2.25.1

Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |   3 +
 tcg/arm/tcg-target-con-str.h |   2 +
 tcg/arm/tcg-target.h         |   6 +-
 tcg/arm/tcg-target.c.inc     | 201 +++++++++++++++++++++++++++++++++--
 4 files changed, 204 insertions(+), 8 deletions(-)

diff --git a/tcg/arm/tcg-target-con-set.h b/tcg/arm/tcg-target-con-set.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-set.h
+++ b/tcg/arm/tcg-target-con-set.h
@@ -XXX,XX +XXX,XX @@ C_O1_I2(r, r, rIN)
 C_O1_I2(r, r, ri)
 C_O1_I2(r, rZ, rZ)
 C_O1_I2(w, w, w)
+C_O1_I2(w, w, wO)
+C_O1_I2(w, w, wV)
+C_O1_I2(w, w, wZ)
 C_O1_I4(r, r, r, rI, rI)
 C_O1_I4(r, r, rIN, rIK, 0)
 C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target-con-str.h b/tcg/arm/tcg-target-con-str.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target-con-str.h
+++ b/tcg/arm/tcg-target-con-str.h
@@ -XXX,XX +XXX,XX @@ REGS('w', ALL_VECTOR_REGS)
 CONST('I', TCG_CT_CONST_ARM)
 CONST('K', TCG_CT_CONST_INV)
 CONST('N', TCG_CT_CONST_NEG)
+CONST('O', TCG_CT_CONST_ORRI)
+CONST('V', TCG_CT_CONST_ANDI)
 CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #else
 extern bool use_idiv_instructions;
 #endif
-#define use_neon_instructions  0
+#ifdef __ARM_NEON__
+#define use_neon_instructions  1
+#else
+extern bool use_neon_instructions;
+#endif
 
 /* used for function call generation */
 #define TCG_TARGET_STACK_ALIGN		8
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int arm_arch = __ARM_ARCH;
 #ifndef use_idiv_instructions
 bool use_idiv_instructions;
 #endif
+#ifndef use_neon_instructions
+bool use_neon_instructions;
+#endif
 
 /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined.  */
 #ifdef CONFIG_SOFTMMU
@@ -XXX,XX +XXX,XX @@ typedef enum {
     /* Otherwise the assembler uses mov r0,r0 */
     INSN_NOP_v4    = (COND_AL << 28) | ARITH_MOV,
 
+    INSN_VADD      = 0xf2000800,
+    INSN_VAND      = 0xf2000110,
+    INSN_VEOR      = 0xf3000110,
     INSN_VORR      = 0xf2200110,
+    INSN_VSUB      = 0xf3000800,
+
+    INSN_VMVN      = 0xf3b00580,
+
+    INSN_VCEQ0     = 0xf3b10100,
+    INSN_VCGT0     = 0xf3b10000,
+    INSN_VCGE0     = 0xf3b10080,
+    INSN_VCLE0     = 0xf3b10180,
+    INSN_VCLT0     = 0xf3b10200,
+
+    INSN_VCEQ      = 0xf3000810,
+    INSN_VCGE      = 0xf2000310,
+    INSN_VCGT      = 0xf2000300,
+    INSN_VCGE_U    = 0xf3000310,
+    INSN_VCGT_U    = 0xf3000300,
+
+    INSN_VTST      = 0xf2000810,
 
     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
     INSN_VDUP_S    = 0xf3b00c00,  /* VDUP (scalar) */
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
 #define TCG_CT_CONST_INV  0x200
 #define TCG_CT_CONST_NEG  0x400
 #define TCG_CT_CONST_ZERO 0x800
+#define TCG_CT_CONST_ORRI 0x1000
+#define TCG_CT_CONST_ANDI 0x2000
 
 #define ALL_GENERAL_REGS  0xffffu
 #define ALL_VECTOR_REGS   0xffff0000u
@@ -XXX,XX +XXX,XX @@ static int is_shimm32_pair(uint32_t v32, int *cmode, int *imm8)
     return i;
 }
 
+/* Return true if V is a valid 16-bit or 32-bit shifted immediate.  */
+static bool is_shimm1632(uint32_t v32, int *cmode, int *imm8)
+{
+    if (v32 == deposit32(v32, 16, 16, v32)) {
+        return is_shimm16(v32, cmode, imm8);
+    } else {
+        return is_shimm32(v32, cmode, imm8);
+    }
+}
+
 /* Test if a constant matches the constraint.
  * TODO: define constraints for:
  *
@@ -XXX,XX +XXX,XX @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
         return 1;
     } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
         return 1;
-    } else {
-        return 0;
     }
+
+    switch (ct & (TCG_CT_CONST_ORRI | TCG_CT_CONST_ANDI)) {
+    case 0:
+        break;
+    case TCG_CT_CONST_ANDI:
+        val = ~val;
+        /* fallthru */
+    case TCG_CT_CONST_ORRI:
+        if (val == deposit64(val, 32, 32, val)) {
+            int cmode, imm8;
+            return is_shimm1632(val, &cmode, &imm8);
+        }
+        break;
+    default:
+        /* Both bits should not be set for the same insn.  */
+        g_assert_not_reached();
+    }
+
+    return 0;
 }
 
 static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
@@ -XXX,XX +XXX,XX @@ static uint32_t encode_vm(TCGReg rm)
     return (extract32(rm, 3, 1) << 5) | (extract32(rm, 0, 3) << 1);
 }
 
+static void tcg_out_vreg2(TCGContext *s, ARMInsn insn, int q, int vece,
+                          TCGReg d, TCGReg m)
+{
+    tcg_out32(s, insn | (vece << 18) | (q << 6) |
+              encode_vd(d) | encode_vm(m));
+}
+
 static void tcg_out_vreg3(TCGContext *s, ARMInsn insn, int q, int vece,
                           TCGReg d, TCGReg n, TCGReg m)
 {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
     case INDEX_op_xor_vec:
-    case INDEX_op_or_vec:
-    case INDEX_op_and_vec:
-    case INDEX_op_cmp_vec:
         return C_O1_I2(w, w, w);
+    case INDEX_op_or_vec:
+        return C_O1_I2(w, w, wO);
+    case INDEX_op_and_vec:
+        return C_O1_I2(w, w, wV);
+    case INDEX_op_cmp_vec:
+        return C_O1_I2(w, w, wZ);
 
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
     }
 }
 
+static const ARMInsn vec_cmp_insn[16] = {
+    [TCG_COND_EQ] = INSN_VCEQ,
+    [TCG_COND_GT] = INSN_VCGT,
+    [TCG_COND_GE] = INSN_VCGE,
+    [TCG_COND_GTU] = INSN_VCGT_U,
+    [TCG_COND_GEU] = INSN_VCGE_U,
+};
+
+static const ARMInsn vec_cmp0_insn[16] = {
+    [TCG_COND_EQ] = INSN_VCEQ0,
+    [TCG_COND_GT] = INSN_VCGT0,
+    [TCG_COND_GE] = INSN_VCGE0,
+    [TCG_COND_LT] = INSN_VCLT0,
+    [TCG_COND_LE] = INSN_VCLE0,
+};
+
 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
                            unsigned vecl, unsigned vece,
                            const TCGArg *args, const int *const_args)
 {
-    g_assert_not_reached();
+    TCGType type = vecl + TCG_TYPE_V64;
+    unsigned q = vecl;
+    TCGArg a0, a1, a2;
+    int cmode, imm8;
+
+    a0 = args[0];
+    a1 = args[1];
+    a2 = args[2];
+
+    switch (opc) {
+    case INDEX_op_ld_vec:
+        tcg_out_ld(s, type, a0, a1, a2);
+        return;
+    case INDEX_op_st_vec:
+        tcg_out_st(s, type, a0, a1, a2);
+        return;
+    case INDEX_op_dupm_vec:
+        tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+        return;
+    case INDEX_op_dup2_vec:
+        tcg_out_dup2_vec(s, a0, a1, a2);
+        return;
+    case INDEX_op_add_vec:
+        tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_sub_vec:
+        tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_xor_vec:
+        tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_and_vec:
+        if (const_args[2]) {
+            is_shimm1632(~a2, &cmode, &imm8);
+            if (a0 == a1) {
+                tcg_out_vmovi(s, a0, q, 1, cmode | 1, imm8); /* VBICI */
+                return;
+            }
+            tcg_out_vmovi(s, a0, q, 1, cmode, imm8); /* VMVNI */
+            a2 = a0;
+        }
+        tcg_out_vreg3(s, INSN_VAND, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_or_vec:
+        if (const_args[2]) {
+            is_shimm1632(a2, &cmode, &imm8);
+            if (a0 == a1) {
+                tcg_out_vmovi(s, a0, q, 0, cmode | 1, imm8); /* VORRI */
+                return;
+            }
+            tcg_out_vmovi(s, a0, q, 0, cmode, imm8); /* VMOVI */
+            a2 = a0;
+        }
+        tcg_out_vreg3(s, INSN_VORR, q, 0, a0, a1, a2);
+        return;
+
+    case INDEX_op_cmp_vec:
+        {
+            TCGCond cond = args[3];
+
+            if (cond == TCG_COND_NE) {
+                if (const_args[2]) {
+                    tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
+                } else {
+                    tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
+                    tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
+                }
+            } else {
+                ARMInsn insn;
+
+                if (const_args[2]) {
+                    insn = vec_cmp0_insn[cond];
+                    if (insn) {
+                        tcg_out_vreg2(s, insn, q, vece, a0, a1);
+                        return;
+                    }
+                    tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
+                    a2 = TCG_VEC_TMP;
+                }
+                insn = vec_cmp_insn[cond];
+                if (insn == 0) {
+                    TCGArg t;
+                    t = a1, a1 = a2, a2 = t;
+                    cond = tcg_swap_cond(cond);
+                    insn = vec_cmp_insn[cond];
+                    tcg_debug_assert(insn != 0);
+                }
+                tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
+            }
+        }
+        return;
+
+    case INDEX_op_mov_vec:  /* Always emitted via tcg_out_mov.  */
+    case INDEX_op_dup_vec:  /* Always emitted via tcg_out_dup_vec.  */
+    default:
+        g_assert_not_reached();
+    }
 }
 
 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 {
-    return 0;
+    switch (opc) {
+    case INDEX_op_add_vec:
+    case INDEX_op_sub_vec:
+    case INDEX_op_and_vec:
+    case INDEX_op_or_vec:
+    case INDEX_op_xor_vec:
+        return 1;
+    case INDEX_op_cmp_vec:
+        return vece < MO_64;
+    default:
+        return 0;
+    }
 }
 
 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
-- 
2.25.1

These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.h         | 10 +++++-----
 tcg/arm/tcg-target.c.inc     | 38 ++++++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 5 deletions(-)

This consists of the three immediate shifts: shli, shri, sari.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 27 +++++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_roti_vec         0
 #define TCG_TARGET_HAS_rots_vec         0
 #define TCG_TARGET_HAS_rotv_vec         0
-#define TCG_TARGET_HAS_shi_vec          0
+#define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VCGE_U    = 0xf3000310,
     INSN_VCGT_U    = 0xf3000300,
 
+    INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
+    INSN_VSARI     = 0xf2800010,  /* VSHR.S */
+    INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+
     INSN_VTST      = 0xf2000810,
 
     INSN_VDUP_G    = 0xee800b10,  /* VDUP (ARM core register) */
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vmovi(TCGContext *s, TCGReg rd,
               | (extract32(imm8, 7, 1) << 24));
 }
 
+static void tcg_out_vshifti(TCGContext *s, ARMInsn insn, int q,
+                            TCGReg rd, TCGReg rm, int l_imm6)
+{
+    tcg_out32(s, insn | (q << 6) | encode_vd(rd) | encode_vm(rm) |
+              (extract32(l_imm6, 6, 1) << 7) |
+              (extract32(l_imm6, 0, 6) << 16));
+}
+
 static void tcg_out_vldst(TCGContext *s, ARMInsn insn,
                           TCGReg rd, TCGReg rn, int offset)
 {
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_abs_vec:
     case INDEX_op_neg_vec:
     case INDEX_op_not_vec:
+    case INDEX_op_shli_vec:
+    case INDEX_op_shri_vec:
+    case INDEX_op_sari_vec:
         return C_O1_I1(w, w);
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
+    case INDEX_op_shli_vec:
+        tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
+        return;
+    case INDEX_op_shri_vec:
+        tcg_out_vshifti(s, INSN_VSHRI, q, a0, a1, (16 << vece) - a2);
+        return;
+    case INDEX_op_sari_vec:
+        tcg_out_vshifti(s, INSN_VSARI, q, a0, a1, (16 << vece) - a2);
+        return;
 
     case INDEX_op_andc_vec:
         if (!const_args[2]) {
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_orc_vec:
     case INDEX_op_xor_vec:
     case INDEX_op_not_vec:
+    case INDEX_op_shli_vec:
+    case INDEX_op_shri_vec:
+    case INDEX_op_sari_vec:
         return 1;
     case INDEX_op_abs_vec:
     case INDEX_op_cmp_vec:
-- 
2.25.1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     | 2 +-
 tcg/arm/tcg-target.c.inc | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

This is saturating add and subtract, signed and unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          1
-#define TCG_TARGET_HAS_sat_vec          0
+#define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       0
 #define TCG_TARGET_HAS_bitsel_vec       0
 #define TCG_TARGET_HAS_cmpsel_vec       0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VORR      = 0xf2200110,
     INSN_VSUB      = 0xf3000800,
     INSN_VMUL      = 0xf2000910,
+    INSN_VQADD     = 0xf2000010,
+    INSN_VQADD_U   = 0xf3000010,
+    INSN_VQSUB     = 0xf2000210,
+    INSN_VQSUB_U   = 0xf3000210,
 
     INSN_VABS      = 0xf3b10300,
     INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
     case INDEX_op_mul_vec:
+    case INDEX_op_ssadd_vec:
+    case INDEX_op_sssub_vec:
     case INDEX_op_sub_vec:
+    case INDEX_op_usadd_vec:
+    case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
         return C_O1_I2(w, w, w);
     case INDEX_op_or_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sub_vec:
         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_ssadd_vec:
+        tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_sssub_vec:
+        tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_usadd_vec:
+        tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_ussub_vec:
+        tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shli_vec:
     case INDEX_op_shri_vec:
     case INDEX_op_sari_vec:
+    case INDEX_op_ssadd_vec:
+    case INDEX_op_sssub_vec:
+    case INDEX_op_usadd_vec:
+    case INDEX_op_ussub_vec:
         return 1;
     case INDEX_op_abs_vec:
     case INDEX_op_cmp_vec:
-- 
2.25.1

This is minimum and maximum, signed and unsigned.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     |  2 +-
 tcg/arm/tcg-target.c.inc | 24 ++++++++++++++++++++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_shv_vec          0
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
-#define TCG_TARGET_HAS_minmax_vec       0
+#define TCG_TARGET_HAS_minmax_vec       1
 #define TCG_TARGET_HAS_bitsel_vec       0
 #define TCG_TARGET_HAS_cmpsel_vec       0
 
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VQADD_U   = 0xf3000010,
     INSN_VQSUB     = 0xf2000210,
     INSN_VQSUB_U   = 0xf3000210,
+    INSN_VMAX      = 0xf2000600,
+    INSN_VMAX_U    = 0xf3000600,
+    INSN_VMIN      = 0xf2000610,
+    INSN_VMIN_U    = 0xf3000610,
 
     INSN_VABS      = 0xf3b10300,
     INSN_VMVN      = 0xf3b00580,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_dup2_vec:
     case INDEX_op_add_vec:
     case INDEX_op_mul_vec:
+    case INDEX_op_smax_vec:
+    case INDEX_op_smin_vec:
     case INDEX_op_ssadd_vec:
     case INDEX_op_sssub_vec:
     case INDEX_op_sub_vec:
+    case INDEX_op_umax_vec:
+    case INDEX_op_umin_vec:
     case INDEX_op_usadd_vec:
     case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_mul_vec:
         tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_smax_vec:
+        tcg_out_vreg3(s, INSN_VMAX, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_smin_vec:
+        tcg_out_vreg3(s, INSN_VMIN, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_sub_vec:
         tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_sssub_vec:
         tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2);
         return;
+    case INDEX_op_umax_vec:
+        tcg_out_vreg3(s, INSN_VMAX_U, q, vece, a0, a1, a2);
+        return;
+    case INDEX_op_umin_vec:
+        tcg_out_vreg3(s, INSN_VMIN_U, q, vece, a0, a1, a2);
+        return;
     case INDEX_op_usadd_vec:
         tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2);
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_cmp_vec:
     case INDEX_op_mul_vec:
     case INDEX_op_neg_vec:
+    case INDEX_op_smax_vec:
+    case INDEX_op_smin_vec:
+    case INDEX_op_umax_vec:
+    case INDEX_op_umin_vec:
         return vece < MO_64;
     default:
         return 0;
-- 
2.25.1

NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.h         |  2 +-
 tcg/arm/tcg-target.c.inc     | 22 ++++++++++++++++++++--
 3 files changed, 22 insertions(+), 3 deletions(-)

The three vector shift by vector operations are all implemented via
expansion.  Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.opc.h |  3 ++
 tcg/arm/tcg-target.c.inc | 61 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.opc.h
+++ b/tcg/arm/tcg-target.opc.h
@@ -XXX,XX +XXX,XX @@
  * emitted by tcg_expand_vec_op.  For those familiar with GCC internals,
  * consider these to be UNSPEC with names.
  */
+
+DEF(arm_sshl_vec, 1, 2, 0, IMPLVEC)
+DEF(arm_ushl_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ typedef enum {
     INSN_VSHLI     = 0xf2800510,  /* VSHL (immediate) */
     INSN_VSARI     = 0xf2800010,  /* VSHR.S */
     INSN_VSHRI     = 0xf3800010,  /* VSHR.U */
+    INSN_VSHL_S    = 0xf2000400,  /* VSHL.S (register) */
+    INSN_VSHL_U    = 0xf3000400,  /* VSHL.U (register) */
 
     INSN_VBSL      = 0xf3100110,
     INSN_VBIT      = 0xf3200110,
@@ -XXX,XX +XXX,XX @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_usadd_vec:
     case INDEX_op_ussub_vec:
     case INDEX_op_xor_vec:
+    case INDEX_op_arm_sshl_vec:
+    case INDEX_op_arm_ushl_vec:
         return C_O1_I2(w, w, w);
     case INDEX_op_or_vec:
     case INDEX_op_andc_vec:
@@ -XXX,XX +XXX,XX @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_xor_vec:
         tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2);
         return;
+    case INDEX_op_arm_sshl_vec:
+        /*
+         * Note that Vm is the data and Vn is the shift count,
+         * therefore the arguments appear reversed.
+         */
+        tcg_out_vreg3(s, INSN_VSHL_S, q, vece, a0, a2, a1);
+        return;
+    case INDEX_op_arm_ushl_vec:
+        /* See above. */
+        tcg_out_vreg3(s, INSN_VSHL_U, q, vece, a0, a2, a1);
+        return;
     case INDEX_op_shli_vec:
         tcg_out_vshifti(s, INSN_VSHLI, q, a0, a1, a2 + (8 << vece));
         return;
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_umax_vec:
     case INDEX_op_umin_vec:
         return vece < MO_64;
+    case INDEX_op_shlv_vec:
+    case INDEX_op_shrv_vec:
+    case INDEX_op_sarv_vec:
+        return -1;
     default:
         return 0;
     }
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                        TCGArg a0, ...)
 {
-    g_assert_not_reached();
+    va_list va;
+    TCGv_vec v0, v1, v2, t1;
+    TCGArg a2;
+
+    va_start(va, a0);
+    v0 = temp_tcgv_vec(arg_temp(a0));
+    v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+    a2 = va_arg(va, TCGArg);
+    va_end(va);
+
+    switch (opc) {
+    case INDEX_op_shlv_vec:
+        /*
+         * Merely propagate shlv_vec to arm_ushl_vec.
+         * In this way we don't set TCG_TARGET_HAS_shv_vec
+         * because everything is done via expansion.
+         */
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+        break;
+
+    case INDEX_op_shrv_vec:
+    case INDEX_op_sarv_vec:
+        /* Right shifts are negative left shifts for NEON.  */
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        tcg_gen_neg_vec(vece, t1, v2);
+        if (opc == INDEX_op_shrv_vec) {
+            opc = INDEX_op_arm_ushl_vec;
+        } else {
+            opc = INDEX_op_arm_sshl_vec;
+        }
+        vec_gen_3(opc, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        tcg_temp_free_vec(t1);
+        break;
+
+    default:
+        g_assert_not_reached();
+    }
 }
 
 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
-- 
2.25.1

Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target-con-set.h |  1 +
 tcg/arm/tcg-target.opc.h     |  1 +
 tcg/arm/tcg-target.c.inc     | 15 +++++++++++++++
 3 files changed, 17 insertions(+)

Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.c.inc | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
     case INDEX_op_shrv_vec:
     case INDEX_op_sarv_vec:
     case INDEX_op_rotli_vec:
+    case INDEX_op_rotlv_vec:
+    case INDEX_op_rotrv_vec:
         return -1;
     default:
         return 0;
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
                        TCGArg a0, ...)
 {
     va_list va;
-    TCGv_vec v0, v1, v2, t1;
+    TCGv_vec v0, v1, v2, t1, t2, c1;
     TCGArg a2;
 
     va_start(va, a0);
@@ -XXX,XX +XXX,XX @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
         tcg_temp_free_vec(t1);
         break;
 
+    case INDEX_op_rotlv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+        tcg_gen_sub_vec(vece, t1, v2, c1);
+        /* Right shifts are negative left shifts for NEON.  */
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(v0),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+        tcg_gen_or_vec(vece, v0, v0, t1);
+        tcg_temp_free_vec(t1);
+        break;
+
+    case INDEX_op_rotrv_vec:
+        v2 = temp_tcgv_vec(arg_temp(a2));
+        t1 = tcg_temp_new_vec(type);
+        t2 = tcg_temp_new_vec(type);
+        c1 = tcg_constant_vec(type, vece, 8 << vece);
+        tcg_gen_neg_vec(vece, t1, v2);
+        tcg_gen_sub_vec(vece, t2, c1, v2);
+        /* Right shifts are negative left shifts for NEON.  */
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t1),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+        vec_gen_3(INDEX_op_arm_ushl_vec, type, vece, tcgv_vec_arg(t2),
+                  tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+        tcg_gen_or_vec(vece, v0, t1, t2);
+        tcg_temp_free_vec(t1);
+        tcg_temp_free_vec(t2);
+        break;
+
     default:
         g_assert_not_reached();
     }
-- 
2.25.1