Series comparison

-[PULL 00/11] tcg patch queue
+[PULL 0/5] tcg patch queue
-The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:
+The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
-  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)
+  Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into staging (2021-04-30 16:02:00 +0100)
 are available in the Git repository at:
-  https://github.com/rth7680/qemu.git tags/pull-tcg-20201008
+  https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210501
-for you to fetch changes up to 62475e9d007d83db4d0a6ccebcda8914f392e9c9:
+for you to fetch changes up to af93ccacc772019298be4c3e47251cdaa60d0c21:
-  accel/tcg: Fix computing of is_write for MIPS (2020-10-08 05:57:32 -0500)
+  decodetree: Extend argument set syntax to allow types (2021-05-01 11:45:35 -0700)
 ----------------------------------------------------------------
-Extend maximum gvec vector size
+Include cleanups.
-Fix i386 avx2 dupi
+Decodetree enhancements for power10.
 Fix mips host user-only write detection
 Misc cleanups.
 ----------------------------------------------------------------
-Kele Huang (1):
+Luis Fernando Fujita Pires (1):
-      accel/tcg: Fix computing of is_write for MIPS
+      decodetree: Add support for 64-bit instructions
-Richard Henderson (10):
+Philippe Mathieu-Daudé (1):
-      tcg: Adjust simd_desc size encoding
+      exec: Remove accel/tcg/ from include paths
       tcg: Drop union from TCGArgConstraint
       tcg: Move sorted_args into TCGArgConstraint.sort_index
       tcg: Remove TCG_CT_REG
       tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
       tcg: Remove TCGOpDef.used
       tcg/i386: Fix dupi for avx2 32-bit hosts
       tcg: Fix generation of dupi_vec for 32-bit host
       tcg/optimize: Fold dup2_vec
       tcg: Remove TCG_TARGET_HAS_cmp_vec
- include/tcg/tcg-gvec-desc.h  | 38 ++++++++++++------
+Richard Henderson (3):
- include/tcg/tcg.h            | 22 ++++------
+      decodetree: Introduce whex and whexC helpers
- tcg/aarch64/tcg-target.h     |  1 -
+      decodetree: More use of f-strings
- tcg/i386/tcg-target.h        |  1 -
+      decodetree: Extend argument set syntax to allow types
  tcg/ppc/tcg-target.h         |  1 -
  accel/tcg/user-exec.c        | 43 ++++++++++++++++++--
  tcg/optimize.c               | 15 +++++++
  tcg/tcg-op-gvec.c            | 35 ++++++++++++----
  tcg/tcg-op-vec.c             | 12 ++++--
  tcg/tcg.c                    | 96 +++++++++++++++++++-------------------------
  tcg/aarch64/tcg-target.c.inc | 17 ++++----
  tcg/arm/tcg-target.c.inc     | 29 ++++++-------
  tcg/i386/tcg-target.c.inc    | 39 +++++++-----------
  tcg/mips/tcg-target.c.inc    | 21 +++++-----
  tcg/ppc/tcg-target.c.inc     | 29 ++++++-------
  tcg/riscv/tcg-target.c.inc   | 16 ++++----
  tcg/s390/tcg-target.c.inc    | 22 +++++-----
  tcg/sparc/tcg-target.c.inc   | 21 ++++------
  tcg/tci/tcg-target.c.inc     |  3 +-
 files changed, 244 insertions(+), 217 deletions(-)
+ docs/devel/decodetree.rst             |  11 ++-
+ meson.build                           |   1 -
+ include/exec/helper-gen.h             |   4 +-
+ include/exec/helper-proto.h           |   4 +-
+ include/exec/helper-tcg.h             |   4 +-
+ tests/decode/succ_argset_type1.decode |   1 +
+ scripts/decodetree.py                 | 172 +++++++++++++++++++---------------
+files changed, 112 insertions(+), 85 deletions(-)
+ create mode 100644 tests/decode/succ_argset_type1.decode

-[PULL 01/11] tcg: Adjust simd_desc size encoding
+Deleted patch
-With larger vector sizes, it turns out oprsz == maxsz, and we only
-need to represent mismatch for oprsz <= 32.  We do, however, need
-to represent larger oprsz and do so without reducing SIMD_DATA_BITS.
-Reduce the size of the oprsz field and increase the maxsz field.
-Steal the oprsz value of 24 to indicate equality with maxsz.
-Tested-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++-------------
- tcg/tcg-op-gvec.c           | 35 ++++++++++++++++++++++++++--------
-files changed, 52 insertions(+), 21 deletions(-)
-diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg-gvec-desc.h
-+++ b/include/tcg/tcg-gvec-desc.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef TCG_TCG_GVEC_DESC_H
- #define TCG_TCG_GVEC_DESC_H
--/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
--#define SIMD_OPRSZ_SHIFT   0
--#define SIMD_OPRSZ_BITS    5
-+/*
-+ * This configuration allows MAXSZ to represent 2048 bytes, and
-+ * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
-+ *
-+ * Encode this with:
-+ *   0, 1, 3 -> 8, 16, 32
-+ *   2       -> maxsz
-+ *
-+ * This steals the input that would otherwise map to 24 to match maxsz.
-+ */
-+#define SIMD_MAXSZ_SHIFT   0
-+#define SIMD_MAXSZ_BITS    8
--#define SIMD_MAXSZ_SHIFT   (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
--#define SIMD_MAXSZ_BITS    5
-+#define SIMD_OPRSZ_SHIFT   (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
-+#define SIMD_OPRSZ_BITS    2
--#define SIMD_DATA_SHIFT    (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
-+#define SIMD_DATA_SHIFT    (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
- #define SIMD_DATA_BITS     (32 - SIMD_DATA_SHIFT)
- /* Create a descriptor from components.  */
- uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
--/* Extract the operation size from a descriptor.  */
--static inline intptr_t simd_oprsz(uint32_t desc)
--{
--    return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
--}
--
- /* Extract the max vector size from a descriptor.  */
- static inline intptr_t simd_maxsz(uint32_t desc)
- {
--    return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
-+    return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
-+}
-+
-+/* Extract the operation size from a descriptor.  */
-+static inline intptr_t simd_oprsz(uint32_t desc)
-+{
-+    uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
-+    intptr_t o = f * 8 + 8;
-+    intptr_t m = simd_maxsz(desc);
-+    return f == 2 ? m : o;
- }
- /* Extract the operation-specific data from a descriptor.  */
-diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-gvec.c
-+++ b/tcg/tcg-op-gvec.c
-@@ -XXX,XX +XXX,XX @@ static const TCGOpcode vecop_list_empty[1] = { 0 };
-    of the operand offsets so that we can check them all at once.  */
- static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
- {
--    uint32_t opr_align = oprsz >= 16 ? 15 : 7;
--    uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
--    tcg_debug_assert(oprsz > 0);
--    tcg_debug_assert(oprsz <= maxsz);
--    tcg_debug_assert((oprsz & opr_align) == 0);
-+    uint32_t max_align;
-+
-+    switch (oprsz) {
-+    case 8:
-+    case 16:
-+    case 32:
-+        tcg_debug_assert(oprsz <= maxsz);
-+        break;
-+    default:
-+        tcg_debug_assert(oprsz == maxsz);
-+        break;
-+    }
-+    tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));
-+
-+    max_align = maxsz >= 16 ? 15 : 7;
-     tcg_debug_assert((maxsz & max_align) == 0);
-     tcg_debug_assert((ofs & max_align) == 0);
- }
-@@ -XXX,XX +XXX,XX @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
- {
-     uint32_t desc = 0;
--    assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
--    assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
--    assert(data == sextract32(data, 0, SIMD_DATA_BITS));
-+    check_size_align(oprsz, maxsz, 0);
-+    tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));
-     oprsz = (oprsz / 8) - 1;
-     maxsz = (maxsz / 8) - 1;
-+
-+    /*
-+     * We have just asserted in check_size_align that either
-+     * oprsz is {8,16,32} or matches maxsz.  Encode the final
-+     * case with '2', as that would otherwise map to 24.
-+     */
-+    if (oprsz == maxsz) {
-+        oprsz = 2;
-+    }
-+
-     desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
-     desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
-     desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
---
-.25.1

-[PULL 10/11] tcg: Remove TCG_TARGET_HAS_cmp_vec
+[PULL 1/5] exec: Remove accel/tcg/ from include paths
-The cmp_vec opcode is mandatory; this symbol is unused.
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+When TCG is enabled, the accel/tcg/ include path is added to the
 project global include search list. This accel/tcg/ directory
 contains a header named "internal.h" which, while intented to
 be internal to accel/tcg/, is accessible by all files compiled
 when TCG is enabled. This might lead to problem with other
 directories using the same "internal.h" header name:
   $ git ls-files | fgrep /internal.h
   accel/tcg/internal.h
   include/hw/ide/internal.h
   target/hexagon/internal.h
   target/mips/internal.h
   target/ppc/internal.h
   target/s390x/internal.h
 As we don't need to expose accel/tcg/ internals to the rest of
 the code base, simplify by removing it from the include search
 list, and include the accel/tcg/ public headers relative to the
 project root search path (which is already in the generic include
 search path).
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Claudio Fontana <cfontana@suse.de>
 Message-Id: <20210413081008.3409459-1-f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/aarch64/tcg-target.h | 1 -
+ meson.build                 | 1 -
- tcg/i386/tcg-target.h    | 1 -
+ include/exec/helper-gen.h   | 4 ++--
- tcg/ppc/tcg-target.h     | 1 -
+ include/exec/helper-proto.h | 4 ++--
-files changed, 3 deletions(-)
+ include/exec/helper-tcg.h   | 4 ++--
 files changed, 6 insertions(+), 7 deletions(-)
-diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
+diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.h
+--- a/meson.build
-+++ b/tcg/aarch64/tcg-target.h
++++ b/meson.build
-@@ -XXX,XX +XXX,XX @@ typedef enum {
+@@ -XXX,XX +XXX,XX @@ if not get_option('tcg').disabled()
- #define TCG_TARGET_HAS_shi_vec          1
+     tcg_arch = 'riscv'
- #define TCG_TARGET_HAS_shs_vec          0
+   endif
- #define TCG_TARGET_HAS_shv_vec          1
+   add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch,
--#define TCG_TARGET_HAS_cmp_vec          1
+-                        '-iquote', meson.current_source_dir() / 'accel/tcg',
- #define TCG_TARGET_HAS_mul_vec          1
+                         language: ['c', 'cpp', 'objc'])
- #define TCG_TARGET_HAS_sat_vec          1
- #define TCG_TARGET_HAS_minmax_vec       1
+   accelerators += 'CONFIG_TCG'
-diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
+diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.h
+--- a/include/exec/helper-gen.h
-+++ b/tcg/i386/tcg-target.h
++++ b/include/exec/helper-gen.h
-@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
+@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret)          \
- #define TCG_TARGET_HAS_shi_vec          1
+ #include "helper.h"
- #define TCG_TARGET_HAS_shs_vec          1
+ #include "trace/generated-helpers.h"
- #define TCG_TARGET_HAS_shv_vec          have_avx2
+ #include "trace/generated-helpers-wrappers.h"
--#define TCG_TARGET_HAS_cmp_vec          1
+-#include "tcg-runtime.h"
- #define TCG_TARGET_HAS_mul_vec          1
+-#include "plugin-helpers.h"
- #define TCG_TARGET_HAS_sat_vec          1
++#include "accel/tcg/tcg-runtime.h"
- #define TCG_TARGET_HAS_minmax_vec       1
++#include "accel/tcg/plugin-helpers.h"
-diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
  #undef DEF_HELPER_FLAGS_0
  #undef DEF_HELPER_FLAGS_1
 diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.h
+--- a/include/exec/helper-proto.h
-+++ b/tcg/ppc/tcg-target.h
++++ b/include/exec/helper-proto.h
-@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
+@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
- #define TCG_TARGET_HAS_shi_vec          0
- #define TCG_TARGET_HAS_shs_vec          0
+ #include "helper.h"
- #define TCG_TARGET_HAS_shv_vec          1
+ #include "trace/generated-helpers.h"
--#define TCG_TARGET_HAS_cmp_vec          1
+-#include "tcg-runtime.h"
- #define TCG_TARGET_HAS_mul_vec          1
+-#include "plugin-helpers.h"
- #define TCG_TARGET_HAS_sat_vec          1
++#include "accel/tcg/tcg-runtime.h"
- #define TCG_TARGET_HAS_minmax_vec       1
++#include "accel/tcg/plugin-helpers.h"
  #undef IN_HELPER_PROTO
 diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/exec/helper-tcg.h
 +++ b/include/exec/helper-tcg.h
@@ -XXX,XX +XXX,XX @@
  #include "helper.h"
  #include "trace/generated-helpers.h"
 -#include "tcg-runtime.h"
 -#include "plugin-helpers.h"
 +#include "accel/tcg/tcg-runtime.h"
 +#include "accel/tcg/plugin-helpers.h"
  #undef str
  #undef DEF_HELPER_FLAGS_0
 --
 .25.1

-[PULL 09/11] tcg/optimize: Fold dup2_vec
+[PULL 2/5] decodetree: Introduce whex and whexC helpers
-When the two arguments are identical, this can be reduced to
+Form a hex constant of the appropriate insnwidth.
-dup_vec or to mov_vec from a tcg_constant_vec.
+Begin using f-strings on changed lines.
+Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/optimize.c | 15 +++++++++++++++
+ scripts/decodetree.py | 66 +++++++++++++++++++++++++------------------
-file changed, 15 insertions(+)
+file changed, 38 insertions(+), 28 deletions(-)
-diff --git a/tcg/optimize.c b/tcg/optimize.c
+diff --git a/scripts/decodetree.py b/scripts/decodetree.py
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/optimize.c
+--- a/scripts/decodetree.py
-+++ b/tcg/optimize.c
++++ b/scripts/decodetree.py
-@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
+@@ -XXX,XX +XXX,XX @@ def str_fields(fields):
-             }
+     return r[1:]
-             goto do_default;
-+        case INDEX_op_dup2_vec:
++def whex(val):
-+            assert(TCG_TARGET_REG_BITS == 32);
++    """Return a hex string for val padded for insnwidth"""
-+            if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
++    global insnwidth
-+                tmp = arg_info(op->args[1])->val;
++    return f'0x{val:0{insnwidth // 4}x}'
 +                if (tmp == arg_info(op->args[2])->val) {
 +                    tcg_opt_gen_movi(s, op, op->args[0], tmp);
 +                    break;
 +                }
 +            } else if (args_are_copies(op->args[1], op->args[2])) {
 +                op->opc = INDEX_op_dup_vec;
 +                TCGOP_VECE(op) = MO_32;
 +                nb_iargs = 1;
 +            }
 +            goto do_default;
 +
-         CASE_OP_32_64(not):
++
-         CASE_OP_32_64(neg):
++def whexC(val):
-         CASE_OP_32_64(ext8s):
++    """Return a hex string for val padded for insnwidth,
 +       and with the proper suffix for a C constant."""
 +    suffix = ''
 +    if val >= 0x80000000:
 +        suffix = 'u'
 +    return whex(val) + suffix
 +
 +
  def str_match_bits(bits, mask):
      """Return a string pretty-printing BITS/MASK"""
      global insnwidth
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
              if outermask != p.fixedmask:
                  innermask = p.fixedmask & ~outermask
                  innerbits = p.fixedbits & ~outermask
 -                output(ind, 'if ((insn & ',
 -                       '0x{0:08x}) == 0x{1:08x}'.format(innermask, innerbits),
 -                       ') {\n')
 -                output(ind, '    /* ',
 -                       str_match_bits(p.fixedbits, p.fixedmask), ' */\n')
 +                output(ind, f'if ((insn & {whexC(innermask)}) == {whexC(innerbits)}) {{\n')
 +                output(ind, f'    /* {str_match_bits(p.fixedbits, p.fixedmask)} */\n')
                  p.output_code(i + 4, extracted, p.fixedbits, p.fixedmask)
                  output(ind, '}\n')
              else:
@@ -XXX,XX +XXX,XX @@ def __init__(self, fm, tm):
      def str1(self, i):
          ind = str_indent(i)
 -        r = '{0}{1:08x}'.format(ind, self.fixedmask)
 +        r = ind + whex(self.fixedmask)
          if self.format:
              r += ' ' + self.format.name
          r += ' [\n'
          for (b, s) in self.subs:
 -            r += '{0}  {1:08x}:\n'.format(ind, b)
 +            r += ind + f'  {whex(b)}:\n'
              r += s.str1(i + 4) + '\n'
          r += ind + ']'
          return r
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
          if sh > 0:
              # Propagate SH down into the local functions.
              def str_switch(b, sh=sh):
 -                return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
 +                return f'(insn >> {sh}) & {b >> sh:#x}'
              def str_case(b, sh=sh):
 -                return '0x{0:x}'.format(b >> sh)
 +                return hex(b >> sh)
          else:
              def str_switch(b):
 -                return 'insn & 0x{0:08x}'.format(b)
 +                return f'insn & {whexC(b)}'
              def str_case(b):
 -                return '0x{0:08x}'.format(b)
 +                return whexC(b)
          output(ind, 'switch (', str_switch(self.thismask), ') {\n')
          for b, s in sorted(self.subs):
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
      # Validate the masks that we have assembled.
      if fieldmask & fixedmask:
 -        error(lineno, 'fieldmask overlaps fixedmask (0x{0:08x} & 0x{1:08x})'
 -                      .format(fieldmask, fixedmask))
 +        error(lineno, 'fieldmask overlaps fixedmask ',
 +              f'({whex(fieldmask)} & {whex(fixedmask)})')
      if fieldmask & undefmask:
 -        error(lineno, 'fieldmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
 -                      .format(fieldmask, undefmask))
 +        error(lineno, 'fieldmask overlaps undefmask ',
 +              f'({whex(fieldmask)} & {whex(undefmask)})')
      if fixedmask & undefmask:
 -        error(lineno, 'fixedmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
 -                      .format(fixedmask, undefmask))
 +        error(lineno, 'fixedmask overlaps undefmask ',
 +              f'({whex(fixedmask)} & {whex(undefmask)})')
      if not is_format:
          allbits = fieldmask | fixedmask | undefmask
          if allbits != insnmask:
 -            error(lineno, 'bits left unspecified (0x{0:08x})'
 -                          .format(allbits ^ insnmask))
 +            error(lineno, 'bits left unspecified ',
 +                  f'({whex(allbits ^ insnmask)})')
  # end parse_general
@@ -XXX,XX +XXX,XX @@ def __init__(self, m, w):
      def str1(self, i):
          ind = str_indent(i)
 -        r = '{0}{1:08x}'.format(ind, self.mask)
 -        r += ' [\n'
 +        r = ind + whex(self.mask) + ' [\n'
          for (b, s) in self.subs:
 -            r += '{0}  {1:08x}:\n'.format(ind, b)
 +            r += ind + f'  {whex(b)}:\n'
              r += s.str1(i + 4) + '\n'
          r += ind + ']'
          return r
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
          if sh > 0:
              # Propagate SH down into the local functions.
              def str_switch(b, sh=sh):
 -                return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
 +                return f'(insn >> {sh}) & {b >> sh:#x}'
              def str_case(b, sh=sh):
 -                return '0x{0:x}'.format(b >> sh)
 +                return hex(b >> sh)
          else:
              def str_switch(b):
 -                return 'insn & 0x{0:08x}'.format(b)
 +                return f'insn & {whexC(b)}'
              def str_case(b):
 -                return '0x{0:08x}'.format(b)
 +                return whexC(b)
          output(ind, 'switch (', str_switch(self.mask), ') {\n')
          for b, s in sorted(self.subs):
@@ -XXX,XX +XXX,XX @@ def __init__(self, m, w):
          self.width = w
      def str1(self, i):
 -        ind = str_indent(i)
 -        return '{0}{1:08x}'.format(ind, self.mask)
 +        return str_indent(i) + whex(self.mask)
      def __str__(self):
          return self.str1(0)
 --
 .25.1

-[PULL 08/11] tcg: Fix generation of dupi_vec for 32-bit host
+[PULL 3/5] decodetree: More use of f-strings
-The definition of INDEX_op_dupi_vec is that it operates on
+Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
 units of tcg_target_ulong -- in this case 32 bits.  It does
 not work to use this for a uint64_t value that happens to be
 small enough to fit in tcg_target_ulong.
 Fixes: d2fd745fe8b
 Fixes: db432672dc5
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- tcg/tcg-op-vec.c | 12 ++++++++----
+ scripts/decodetree.py | 50 ++++++++++++++++++++-----------------------
-file changed, 8 insertions(+), 4 deletions(-)
+file changed, 23 insertions(+), 27 deletions(-)
-diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
+diff --git a/scripts/decodetree.py b/scripts/decodetree.py
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-vec.c
+--- a/scripts/decodetree.py
-+++ b/tcg/tcg-op-vec.c
++++ b/scripts/decodetree.py
-@@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
+@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
- void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
+     prefix = ''
- {
+     if file:
--    if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
+-        prefix += '{0}:'.format(file)
--        do_dupi_vec(r, MO_32, a);
++        prefix += f'{file}:'
--    } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
+     if lineno:
-+    if (TCG_TARGET_REG_BITS == 64) {
+-        prefix += '{0}:'.format(lineno)
-         do_dupi_vec(r, MO_64, a);
++        prefix += f'{lineno}:'
-+    } else if (a == dup_const(MO_32, a)) {
+     if prefix:
-+        do_dupi_vec(r, MO_32, a);
+         prefix += ' '
-     } else {
+     print(prefix, end='error: ', file=sys.stderr)
-         TCGv_i64 c = tcg_const_i64(a);
+@@ -XXX,XX +XXX,XX @@ def str_extract(self):
-         tcg_gen_dup_i64_vec(MO_64, r, c);
+             extr = 'sextract32'
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
+         else:
+             extr = 'extract32'
- void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
+-        return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len)
- {
++        return f'{extr}(insn, {self.pos}, {self.len})'
--    do_dupi_vec(r, MO_REG, dup_const(vece, a));
-+    if (vece == MO_64) {
+     def __eq__(self, other):
-+        tcg_gen_dup64i_vec(r, a);
+         return self.sign == other.sign and self.mask == other.mask
-+    } else {
+@@ -XXX,XX +XXX,XX @@ def str_extract(self):
-+        do_dupi_vec(r, MO_REG, dup_const(vece, a));
+         ret = '0'
-+    }
+         pos = 0
- }
+         for f in reversed(self.subs):
++            ext = f.str_extract()
- void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
+             if pos == 0:
 -                ret = f.str_extract()
 +                ret = ext
              else:
 -                ret = 'deposit32({0}, {1}, {2}, {3})' \
 -                      .format(ret, pos, 32 - pos, f.str_extract())
 +                ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
              pos += f.len
          return ret
@@ -XXX,XX +XXX,XX @@ def parse_field(lineno, name, toks):
              subtoks = t.split(':')
              sign = False
          else:
 -            error(lineno, 'invalid field token "{0}"'.format(t))
 +            error(lineno, f'invalid field token "{t}"')
          po = int(subtoks[0])
          le = int(subtoks[1])
          if po + le > insnwidth:
 -            error(lineno, 'field {0} too large'.format(t))
 +            error(lineno, f'field {t} too large')
          f = Field(sign, po, le)
          subs.append(f)
          width += le
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
              anyextern = True
              continue
          if not re.fullmatch(re_C_ident, t):
 -            error(lineno, 'invalid argument set token "{0}"'.format(t))
 +            error(lineno, f'invalid argument set token "{t}"')
          if t in flds:
 -            error(lineno, 'duplicate argument "{0}"'.format(t))
 +            error(lineno, f'duplicate argument "{t}"')
          flds.append(t)
      if name in arguments:
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
                  flen = flen[1:]
              shift = int(flen, 10)
              if shift + width > insnwidth:
 -                error(lineno, 'field {0} exceeds insnwidth'.format(fname))
 +                error(lineno, f'field {fname} exceeds insnwidth')
              f = Field(sign, insnwidth - width - shift, shift)
              flds = add_field(lineno, flds, fname, f)
              fixedbits <<= shift
              fixedmask <<= shift
              undefmask <<= shift
          else:
 -            error(lineno, 'invalid token "{0}"'.format(t))
 +            error(lineno, f'invalid token "{t}"')
          width += shift
      if variablewidth and width < insnwidth and width % 8 == 0:
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
      # We should have filled in all of the bits of the instruction.
      elif not (is_format and width == 0) and width != insnwidth:
 -        error(lineno, 'definition has {0} bits'.format(width))
 +        error(lineno, f'definition has {width} bits')
      # Do not check for fields overlapping fields; one valid usage
      # is to be able to duplicate fields via import.
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
          if arg:
              for f in flds.keys():
                  if f not in arg.fields:
 -                    error(lineno, 'field {0} not in argument set {1}'
 -                                  .format(f, arg.name))
 +                    error(lineno, f'field {f} not in argument set {arg.name}')
          else:
              arg = infer_argument_set(flds)
          if name in formats:
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
          arg = fmt.base
          for f in flds.keys():
              if f not in arg.fields:
 -                error(lineno, 'field {0} not in argument set {1}'
 -                              .format(f, arg.name))
 +                error(lineno, f'field {f} not in argument set {arg.name}')
              if f in fmt.fields.keys():
 -                error(lineno, 'field {0} set by format and pattern'.format(f))
 +                error(lineno, f'field {f} set by format and pattern')
          for f in arg.fields:
              if f not in flds.keys() and f not in fmt.fields.keys():
 -                error(lineno, 'field {0} not initialized'.format(f))
 +                error(lineno, f'field {f} not initialized')
          pat = Pattern(name, lineno, fmt, fixedbits, fixedmask,
                        undefmask, fieldmask, flds, width)
          parent_pat.pats.append(pat)
@@ -XXX,XX +XXX,XX @@ def parse_file(f, parent_pat):
          elif re.fullmatch(re_pat_ident, name):
              parse_generic(start_lineno, parent_pat, name, toks)
          else:
 -            error(lineno, 'invalid token "{0}"'.format(name))
 +            error(lineno, f'invalid token "{name}"')
          toks = []
      if nesting != 0:
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
          # If we need to load more bytes to test, do so now.
          if extracted < self.width:
 -            output(ind, 'insn = ', decode_function,
 -                   '_load_bytes(ctx, insn, {0}, {1});\n'
 -                   .format(extracted // 8, self.width // 8));
 +            output(ind, f'insn = {decode_function}_load_bytes',
 +                   f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
              extracted = self.width
          # Attempt to aid the compiler in producing compact switch statements.
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
          # If we need to load more bytes, do so now.
          if extracted < self.width:
 -            output(ind, 'insn = ', decode_function,
 -                   '_load_bytes(ctx, insn, {0}, {1});\n'
 -                   .format(extracted // 8, self.width // 8));
 +            output(ind, f'insn = {decode_function}_load_bytes',
 +                   f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
              extracted = self.width
          output(ind, 'return insn;\n')
  # end SizeLeaf
@@ -XXX,XX +XXX,XX @@ def build_size_tree(pats, width, outerbits, outermask):
          for p in pats:
              pnames.append(p.name + ':' + p.file + ':' + str(p.lineno))
          error_with_file(pats[0].file, pats[0].lineno,
 -                        'overlapping patterns size {0}:'.format(width), pnames)
 +                        f'overlapping patterns size {width}:', pnames)
      bins = {}
      for i in pats:
 --
 .25.1

-[PULL 02/11] tcg: Drop union from TCGArgConstraint
+[PULL 4/5] decodetree: Add support for 64-bit instructions
-The union is unused; let "regs" appear in the main structure
+From: Luis Fernando Fujita Pires <luis.pires@eldorado.org.br>
-without the "u.regs" wrapping.
 Allow '64' to be specified for the instruction width command line params
 and use the appropriate extract and deposit functions in that case.
 This will be used to implement the new 64-bit Power ISA 3.1 instructions.
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
+Message-Id: <CP2PR80MB3668E123E2EFDB0ACD3A46F1DA759@CP2PR80MB3668.lamprd80.prod.outlook.com>
+[rth: Drop the change to the field type; use bitop_width instead of separate
+variables for extract/deposit; use "ull" for 64-bit constants.]
+Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- include/tcg/tcg.h            |  4 +---
+ scripts/decodetree.py | 21 ++++++++++++++-------
- tcg/tcg.c                    | 22 +++++++++++-----------
+file changed, 14 insertions(+), 7 deletions(-)
  tcg/aarch64/tcg-target.c.inc | 14 +++++++-------
  tcg/arm/tcg-target.c.inc     | 26 +++++++++++++-------------
  tcg/i386/tcg-target.c.inc    | 26 +++++++++++++-------------
  tcg/mips/tcg-target.c.inc    | 18 +++++++++---------
  tcg/ppc/tcg-target.c.inc     | 24 ++++++++++++------------
  tcg/riscv/tcg-target.c.inc   | 14 +++++++-------
  tcg/s390/tcg-target.c.inc    | 18 +++++++++---------
  tcg/sparc/tcg-target.c.inc   | 16 ++++++++--------
  tcg/tci/tcg-target.c.inc     |  2 +-
 files changed, 91 insertions(+), 93 deletions(-)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
+diff --git a/scripts/decodetree.py b/scripts/decodetree.py
 index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
+--- a/scripts/decodetree.py
-+++ b/include/tcg/tcg.h
++++ b/scripts/decodetree.py
-@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
+@@ -XXX,XX +XXX,XX @@
- typedef struct TCGArgConstraint {
+ import getopt
-     uint16_t ct;
-     uint8_t alias_index;
+ insnwidth = 32
--    union {
++bitop_width = 32
--        TCGRegSet regs;
+ insnmask = 0xffffffff
--    } u;
+ variablewidth = False
-+    TCGRegSet regs;
+ fields = {}
- } TCGArgConstraint;
+@@ -XXX,XX +XXX,XX @@ def whexC(val):
+     """Return a hex string for val padded for insnwidth,
- #define TCG_MAX_OP_ARGS 16
+        and with the proper suffix for a C constant."""
-diff --git a/tcg/tcg.c b/tcg/tcg.c
+     suffix = ''
-index XXXXXXX..XXXXXXX 100644
+-    if val >= 0x80000000:
---- a/tcg/tcg.c
++    if val >= 0x100000000:
-+++ b/tcg/tcg.c
++        suffix = 'ull'
-@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
++    elif val >= 0x80000000:
-             return 0;
+         suffix = 'u'
-         n = 0;
+     return whex(val) + suffix
-         for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
--            if (tcg_regset_test_reg(arg_ct->u.regs, i))
+@@ -XXX,XX +XXX,XX @@ def __str__(self):
-+            if (tcg_regset_test_reg(arg_ct->regs, i))
+         return str(self.pos) + ':' + s + str(self.len)
-                 n++;
-         }
+     def str_extract(self):
-     }
+-        if self.sign:
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
+-            extr = 'sextract32'
-             /* Incomplete TCGTargetOpDef entry. */
+-        else:
-             tcg_debug_assert(ct_str != NULL);
+-            extr = 'extract32'
+-        return f'{extr}(insn, {self.pos}, {self.len})'
--            def->args_ct[i].u.regs = 0;
++        global bitop_width
-+            def->args_ct[i].regs = 0;
++        s = 's' if self.sign else ''
-             def->args_ct[i].ct = 0;
++        return f'{s}extract{bitop_width}(insn, {self.pos}, {self.len})'
-             while (*ct_str != '\0') {
-                 switch(*ct_str) {
+     def __eq__(self, other):
-@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
+         return self.sign == other.sign and self.mask == other.mask
-                     pset = la_temp_pref(ts);
+@@ -XXX,XX +XXX,XX @@ def __str__(self):
-                     set = *pset;
+         return str(self.subs)
--                    set &= ct->u.regs;
+     def str_extract(self):
-+                    set &= ct->regs;
++        global bitop_width
-                     if (ct->ct & TCG_CT_IALIAS) {
+         ret = '0'
-                         set &= op->output_pref[ct->alias_index];
+         pos = 0
-                     }
+         for f in reversed(self.subs):
-                     /* If the combination is not possible, restart.  */
+@@ -XXX,XX +XXX,XX @@ def str_extract(self):
-                     if (set == 0) {
+             if pos == 0:
--                        set = ct->u.regs;
+                 ret = ext
-+                        set = ct->regs;
+             else:
-                     }
+-                ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
-                     *pset = set;
++                ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - pos}, {ext})'
-                 }
+             pos += f.len
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
+         return ret
-         return;
-     }
+@@ -XXX,XX +XXX,XX @@ def main():
+     global insntype
--    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
+     global insnmask
--    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
+     global decode_function
-+    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
++    global bitop_width
-+    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
+     global variablewidth
+     global anyextern
-     /* Allocate the output register now.  */
-     if (ots->val_type != TEMP_VAL_REG) {
+@@ -XXX,XX +XXX,XX @@ def main():
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
+             if insnwidth == 16:
-             }
+                 insntype = 'uint16_t'
-         }
+                 insnmask = 0xffff
++            elif insnwidth == 64:
--        temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);
++                insntype = 'uint64_t'
-+        temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
++                insnmask = 0xffffffffffffffff
-         reg = ts->reg;
++                bitop_width = 64
+             elif insnwidth != 32:
--        if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
+                 error(0, 'cannot handle insns of width', insnwidth)
-+        if (tcg_regset_test_reg(arg_ct->regs, reg)) {
+         else:
              /* nothing to do : the constraint is satisfied */
          } else {
          allocate_in_reg:
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                 and move the temporary register into it */
              temp_load(s, ts, tcg_target_available_regs[ts->type],
                        i_allocated_regs, 0);
 -            reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
 +            reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
                                  o_preferred_regs, ts->indirect_base);
              if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
                  /*
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                  && !const_args[arg_ct->alias_index]) {
                  reg = new_args[arg_ct->alias_index];
              } else if (arg_ct->ct & TCG_CT_NEWREG) {
 -                reg = tcg_reg_alloc(s, arg_ct->u.regs,
 +                reg = tcg_reg_alloc(s, arg_ct->regs,
                                      i_allocated_regs | o_allocated_regs,
                                      op->output_pref[k], ts->indirect_base);
              } else {
 -                reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
 +                reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
                                      op->output_pref[k], ts->indirect_base);
              }
              tcg_regset_set_reg(o_allocated_regs, reg);
 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/aarch64/tcg-target.c.inc
 +++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'r': /* general registers */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs |= 0xffffffffu;
 +        ct->regs |= 0xffffffffu;
          break;
      case 'w': /* advsimd registers */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs |= 0xffffffff00000000ull;
 +        ct->regs |= 0xffffffff00000000ull;
          break;
      case 'l': /* qemu_ld / qemu_st address, data_reg */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffffu;
 +        ct->regs = 0xffffffffu;
  #ifdef CONFIG_SOFTMMU
          /* x0 and x1 will be overwritten when reading the tlb entry,
             and x2, and x3 for helper args, better to avoid using them. */
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
  #endif
          break;
      case 'A': /* Valid for arithmetic immediate (positive or negative).  */
 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/arm/tcg-target.c.inc
 +++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffff;
 +        ct->regs = 0xffff;
          break;
      /* qemu_ld address */
      case 'l':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffff;
 +        ct->regs = 0xffff;
  #ifdef CONFIG_SOFTMMU
          /* r0-r2,lr will be overwritten when reading the tlb entry,
             so don't use these. */
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
  #endif
          break;
      /* qemu_st address & data */
      case 's':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffff;
 +        ct->regs = 0xffff;
          /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
             and r0-r1 doing the byte swapping, so don't use these. */
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
  #if defined(CONFIG_SOFTMMU)
          /* Avoid clashes with registers being used for helper args */
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
  #if TARGET_LONG_BITS == 64
          /* Avoid clashes with registers being used for helper args */
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
  #endif
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
  #endif
          break;
 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/i386/tcg-target.c.inc
 +++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch(*ct_str++) {
      case 'a':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
          break;
      case 'b':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
          break;
      case 'c':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
          break;
      case 'd':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
          break;
      case 'S':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
          break;
      case 'D':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
 +        tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
          break;
      case 'q':
          /* A register that can be used as a byte operand.  */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
 +        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
          break;
      case 'Q':
          /* A register with an addressable second byte (e.g. %ah).  */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xf;
 +        ct->regs = 0xf;
          break;
      case 'r':
          /* A general register.  */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs |= ALL_GENERAL_REGS;
 +        ct->regs |= ALL_GENERAL_REGS;
          break;
      case 'W':
          /* With TZCNT/LZCNT, we can have operand-size as an input.  */
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      case 'x':
          /* A vector register.  */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs |= ALL_VECTOR_REGS;
 +        ct->regs |= ALL_VECTOR_REGS;
          break;
          /* qemu_ld/st address constraint */
      case 'L':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
 +        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
          break;
      case 'e':
 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/mips/tcg-target.c.inc
 +++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch(*ct_str++) {
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          break;
      case 'L': /* qemu_ld input arg constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
 +        ct->regs = 0xffffffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
  #if defined(CONFIG_SOFTMMU)
          if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
 -            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
 +            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
          }
  #endif
          break;
      case 'S': /* qemu_st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
 +        ct->regs = 0xffffffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
  #if defined(CONFIG_SOFTMMU)
          if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
 -            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
 -            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
 +            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
 +            tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
          } else {
 -            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
 +            tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
          }
  #endif
          break;
 diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/ppc/tcg-target.c.inc
 +++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'A': case 'B': case 'C': case 'D':
          ct->ct |= TCG_CT_REG;
 -        tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
 +        tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
          break;
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          break;
      case 'v':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff00000000ull;
 +        ct->regs = 0xffffffff00000000ull;
          break;
      case 'L':                   /* qemu_ld constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 +        ct->regs = 0xffffffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
  #ifdef CONFIG_SOFTMMU
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
  #endif
          break;
      case 'S':                   /* qemu_st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 +        ct->regs = 0xffffffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
  #ifdef CONFIG_SOFTMMU
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
  #endif
          break;
      case 'I':
 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/riscv/tcg-target.c.inc
 +++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          break;
      case 'L':
          /* qemu_ld/qemu_st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
  #if defined(CONFIG_SOFTMMU)
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
 -        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
 +        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
  #endif
          break;
      case 'I':
 diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/s390/tcg-target.c.inc
 +++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'r':                  /* all registers */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffff;
 +        ct->regs = 0xffff;
          break;
      case 'L':                  /* qemu_ld/st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffff;
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
 +        ct->regs = 0xffff;
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
          break;
      case 'a':                  /* force R2 for division */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
 +        ct->regs = 0;
 +        tcg_regset_set_reg(ct->regs, TCG_REG_R2);
          break;
      case 'b':                  /* force R3 for division */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0;
 -        tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
 +        ct->regs = 0;
 +        tcg_regset_set_reg(ct->regs, TCG_REG_R3);
          break;
      case 'A':
          ct->ct |= TCG_CT_CONST_S33;
 diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/sparc/tcg-target.c.inc
 +++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      switch (*ct_str++) {
      case 'r':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          break;
      case 'R':
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = ALL_64;
 +        ct->regs = ALL_64;
          break;
      case 'A': /* qemu_ld/st address constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
 +        ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
      reserve_helpers:
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
 -        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
 +        tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
          break;
      case 's': /* qemu_st data 32-bit constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = 0xffffffff;
 +        ct->regs = 0xffffffff;
          goto reserve_helpers;
      case 'S': /* qemu_st data 64-bit constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = ALL_64;
 +        ct->regs = ALL_64;
          goto reserve_helpers;
      case 'I':
          ct->ct |= TCG_CT_CONST_S11;
 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/tcg/tci/tcg-target.c.inc
 +++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
      case 'L':                   /* qemu_ld constraint */
      case 'S':                   /* qemu_st constraint */
          ct->ct |= TCG_CT_REG;
 -        ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
 +        ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
          break;
      default:
          return NULL;
 --
 .25.1

-[PULL 03/11] tcg: Move sorted_args into TCGArgConstraint.sort_index
+Deleted patch
-This uses an existing hole in the TCGArgConstraint structure
-and will be convenient for keeping the data in one place.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/tcg/tcg.h |  2 +-
- tcg/tcg.c         | 35 +++++++++++++++++------------------
-files changed, 18 insertions(+), 19 deletions(-)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
-+++ b/include/tcg/tcg.h
-@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
- typedef struct TCGArgConstraint {
-     uint16_t ct;
-     uint8_t alias_index;
-+    uint8_t sort_index;
-     TCGRegSet regs;
- } TCGArgConstraint;
-@@ -XXX,XX +XXX,XX @@ typedef struct TCGOpDef {
-     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
-     uint8_t flags;
-     TCGArgConstraint *args_ct;
--    int *sorted_args;
- #if defined(CONFIG_DEBUG_TCG)
-     int used;
- #endif
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
-     int op, total_args, n, i;
-     TCGOpDef *def;
-     TCGArgConstraint *args_ct;
--    int *sorted_args;
-     TCGTemp *ts;
-     memset(s, 0, sizeof(*s));
-@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
-     }
-     args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
--    sorted_args = g_malloc(sizeof(int) * total_args);
-     for(op = 0; op < NB_OPS; op++) {
-         def = &tcg_op_defs[op];
-         def->args_ct = args_ct;
--        def->sorted_args = sorted_args;
-         n = def->nb_iargs + def->nb_oargs;
--        sorted_args += n;
-         args_ct += n;
-     }
-@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
- /* sort from highest priority to lowest */
- static void sort_constraints(TCGOpDef *def, int start, int n)
- {
--    int i, j, p1, p2, tmp;
-+    int i, j;
-+    TCGArgConstraint *a = def->args_ct;
--    for(i = 0; i < n; i++)
--        def->sorted_args[start + i] = start + i;
--    if (n <= 1)
-+    for (i = 0; i < n; i++) {
-+        a[start + i].sort_index = start + i;
-+    }
-+    if (n <= 1) {
-         return;
--    for(i = 0; i < n - 1; i++) {
--        for(j = i + 1; j < n; j++) {
--            p1 = get_constraint_priority(def, def->sorted_args[start + i]);
--            p2 = get_constraint_priority(def, def->sorted_args[start + j]);
-+    }
-+    for (i = 0; i < n - 1; i++) {
-+        for (j = i + 1; j < n; j++) {
-+            int p1 = get_constraint_priority(def, a[start + i].sort_index);
-+            int p2 = get_constraint_priority(def, a[start + j].sort_index);
-             if (p1 < p2) {
--                tmp = def->sorted_args[start + i];
--                def->sorted_args[start + i] = def->sorted_args[start + j];
--                def->sorted_args[start + j] = tmp;
-+                int tmp = a[start + i].sort_index;
-+                a[start + i].sort_index = a[start + j].sort_index;
-+                a[start + j].sort_index = tmp;
-             }
-         }
-     }
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-     for (k = 0; k < nb_iargs; k++) {
-         TCGRegSet i_preferred_regs, o_preferred_regs;
--        i = def->sorted_args[nb_oargs + k];
-+        i = def->args_ct[nb_oargs + k].sort_index;
-         arg = op->args[i];
-         arg_ct = &def->args_ct[i];
-         ts = arg_temp(arg);
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-                     int k2, i2;
-                     reg = ts->reg;
-                     for (k2 = 0 ; k2 < k ; k2++) {
--                        i2 = def->sorted_args[nb_oargs + k2];
-+                        i2 = def->args_ct[nb_oargs + k2].sort_index;
-                         if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
-                             reg == new_args[i2]) {
-                             goto allocate_in_reg;
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-         /* satisfy the output constraints */
-         for(k = 0; k < nb_oargs; k++) {
--            i = def->sorted_args[k];
-+            i = def->args_ct[k].sort_index;
-             arg = op->args[i];
-             arg_ct = &def->args_ct[i];
-             ts = arg_temp(arg);
---
-.25.1

-[PULL 04/11] tcg: Remove TCG_CT_REG
+Deleted patch
-This wasn't actually used for anything, really.  All variable
-operands must accept registers, and which are indicated by the
-set in TCGArgConstraint.regs.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/tcg/tcg.h            |  1 -
- tcg/tcg.c                    | 15 ++++-----------
- tcg/aarch64/tcg-target.c.inc |  3 ---
- tcg/arm/tcg-target.c.inc     |  3 ---
- tcg/i386/tcg-target.c.inc    | 11 -----------
- tcg/mips/tcg-target.c.inc    |  3 ---
- tcg/ppc/tcg-target.c.inc     |  5 -----
- tcg/riscv/tcg-target.c.inc   |  2 --
- tcg/s390/tcg-target.c.inc    |  4 ----
- tcg/sparc/tcg-target.c.inc   |  5 -----
- tcg/tci/tcg-target.c.inc     |  1 -
-files changed, 4 insertions(+), 49 deletions(-)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
-+++ b/include/tcg/tcg.h
-@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
- #define TCG_CT_ALIAS  0x80
- #define TCG_CT_IALIAS 0x40
- #define TCG_CT_NEWREG 0x20 /* output requires a new register */
--#define TCG_CT_REG    0x01
- #define TCG_CT_CONST  0x02 /* any constant of register size */
- typedef struct TCGArgConstraint {
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
- /* we give more priority to constraints with less registers */
- static int get_constraint_priority(const TCGOpDef *def, int k)
- {
--    const TCGArgConstraint *arg_ct;
-+    const TCGArgConstraint *arg_ct = &def->args_ct[k];
-+    int n;
--    int i, n;
--    arg_ct = &def->args_ct[k];
-     if (arg_ct->ct & TCG_CT_ALIAS) {
-         /* an alias is equivalent to a single register */
-         n = 1;
-     } else {
--        if (!(arg_ct->ct & TCG_CT_REG))
--            return 0;
--        n = 0;
--        for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
--            if (tcg_regset_test_reg(arg_ct->regs, i))
--                n++;
--        }
-+        n = ctpop64(arg_ct->regs);
-     }
-     return TCG_TARGET_NB_REGS - n + 1;
- }
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-                         int oarg = *ct_str - '0';
-                         tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
-                         tcg_debug_assert(oarg < def->nb_oargs);
--                        tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
-+                        tcg_debug_assert(def->args_ct[oarg].regs != 0);
-                         /* TCG_CT_ALIAS is for the output arguments.
-                            The input is tagged with TCG_CT_IALIAS. */
-                         def->args_ct[i] = def->args_ct[oarg];
-diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/aarch64/tcg-target.c.inc
-+++ b/tcg/aarch64/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- {
-     switch (*ct_str++) {
-     case 'r': /* general registers */
--        ct->ct |= TCG_CT_REG;
-         ct->regs |= 0xffffffffu;
-         break;
-     case 'w': /* advsimd registers */
--        ct->ct |= TCG_CT_REG;
-         ct->regs |= 0xffffffff00000000ull;
-         break;
-     case 'l': /* qemu_ld / qemu_st address, data_reg */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffffu;
- #ifdef CONFIG_SOFTMMU
-         /* x0 and x1 will be overwritten when reading the tlb entry,
-diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/arm/tcg-target.c.inc
-+++ b/tcg/arm/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-         break;
-     case 'r':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffff;
-         break;
-     /* qemu_ld address */
-     case 'l':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffff;
- #ifdef CONFIG_SOFTMMU
-         /* r0-r2,lr will be overwritten when reading the tlb entry,
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-     /* qemu_st address & data */
-     case 's':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffff;
-         /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
-            and r0-r1 doing the byte swapping, so don't use these. */
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
-+++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- {
-     switch(*ct_str++) {
-     case 'a':
--        ct->ct |= TCG_CT_REG;
-         tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
-         break;
-     case 'b':
--        ct->ct |= TCG_CT_REG;
-         tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
-         break;
-     case 'c':
--        ct->ct |= TCG_CT_REG;
-         tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
-         break;
-     case 'd':
--        ct->ct |= TCG_CT_REG;
-         tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
-         break;
-     case 'S':
--        ct->ct |= TCG_CT_REG;
-         tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
-         break;
-     case 'D':
--        ct->ct |= TCG_CT_REG;
-         tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
-         break;
-     case 'q':
-         /* A register that can be used as a byte operand.  */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
-         break;
-     case 'Q':
-         /* A register with an addressable second byte (e.g. %ah).  */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xf;
-         break;
-     case 'r':
-         /* A general register.  */
--        ct->ct |= TCG_CT_REG;
-         ct->regs |= ALL_GENERAL_REGS;
-         break;
-     case 'W':
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-         break;
-     case 'x':
-         /* A vector register.  */
--        ct->ct |= TCG_CT_REG;
-         ct->regs |= ALL_VECTOR_REGS;
-         break;
-         /* qemu_ld/st address constraint */
-     case 'L':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
-         tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
-         tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
-diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/mips/tcg-target.c.inc
-+++ b/tcg/mips/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- {
-     switch(*ct_str++) {
-     case 'r':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         break;
-     case 'L': /* qemu_ld input arg constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
- #if defined(CONFIG_SOFTMMU)
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- #endif
-         break;
-     case 'S': /* qemu_st constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
- #if defined(CONFIG_SOFTMMU)
-diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/ppc/tcg-target.c.inc
-+++ b/tcg/ppc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- {
-     switch (*ct_str++) {
-     case 'A': case 'B': case 'C': case 'D':
--        ct->ct |= TCG_CT_REG;
-         tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
-         break;
-     case 'r':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         break;
-     case 'v':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff00000000ull;
-         break;
-     case 'L':                   /* qemu_ld constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
- #ifdef CONFIG_SOFTMMU
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- #endif
-         break;
-     case 'S':                   /* qemu_st constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
- #ifdef CONFIG_SOFTMMU
-diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/riscv/tcg-target.c.inc
-+++ b/tcg/riscv/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- {
-     switch (*ct_str++) {
-     case 'r':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         break;
-     case 'L':
-         /* qemu_ld/qemu_st constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
- #if defined(CONFIG_SOFTMMU)
-diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/s390/tcg-target.c.inc
-+++ b/tcg/s390/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- {
-     switch (*ct_str++) {
-     case 'r':                  /* all registers */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffff;
-         break;
-     case 'L':                  /* qemu_ld/st constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffff;
-         tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
-         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
-         tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
-         break;
-     case 'a':                  /* force R2 for division */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0;
-         tcg_regset_set_reg(ct->regs, TCG_REG_R2);
-         break;
-     case 'b':                  /* force R3 for division */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0;
-         tcg_regset_set_reg(ct->regs, TCG_REG_R3);
-         break;
-diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/sparc/tcg-target.c.inc
-+++ b/tcg/sparc/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
- {
-     switch (*ct_str++) {
-     case 'r':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         break;
-     case 'R':
--        ct->ct |= TCG_CT_REG;
-         ct->regs = ALL_64;
-         break;
-     case 'A': /* qemu_ld/st address constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
-     reserve_helpers:
-         tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-         tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
-         break;
-     case 's': /* qemu_st data 32-bit constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = 0xffffffff;
-         goto reserve_helpers;
-     case 'S': /* qemu_st data 64-bit constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = ALL_64;
-         goto reserve_helpers;
-     case 'I':
-diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tci/tcg-target.c.inc
-+++ b/tcg/tci/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
-     case 'r':
-     case 'L':                   /* qemu_ld constraint */
-     case 'S':                   /* qemu_st constraint */
--        ct->ct |= TCG_CT_REG;
-         ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
-         break;
-     default:
---
-.25.1

-[PULL 05/11] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
+Deleted patch
-These are easier to set and test when they have their own fields.
-Reduce the size of alias_index and sort_index to 4 bits, which is
-sufficient for TCG_MAX_OP_ARGS.  This leaves only the bits indicating
-constants within the ct field.
-Move all initialization to allocation time, rather than init
-individual fields in process_op_defs.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/tcg/tcg.h | 14 +++++++-------
- tcg/tcg.c         | 28 ++++++++++++----------------
-files changed, 19 insertions(+), 23 deletions(-)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
-+++ b/include/tcg/tcg.h
-@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void);
- void tcg_dump_info(void);
- void tcg_dump_op_count(void);
--#define TCG_CT_ALIAS  0x80
--#define TCG_CT_IALIAS 0x40
--#define TCG_CT_NEWREG 0x20 /* output requires a new register */
--#define TCG_CT_CONST  0x02 /* any constant of register size */
-+#define TCG_CT_CONST  1 /* any constant of register size */
- typedef struct TCGArgConstraint {
--    uint16_t ct;
--    uint8_t alias_index;
--    uint8_t sort_index;
-+    unsigned ct : 16;
-+    unsigned alias_index : 4;
-+    unsigned sort_index : 4;
-+    bool oalias : 1;
-+    bool ialias : 1;
-+    bool newreg : 1;
-     TCGRegSet regs;
- } TCGArgConstraint;
-diff --git a/tcg/tcg.c b/tcg/tcg.c
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.c
-+++ b/tcg/tcg.c
-@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
-         total_args += n;
-     }
--    args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
-+    args_ct = g_new0(TCGArgConstraint, total_args);
-     for(op = 0; op < NB_OPS; op++) {
-         def = &tcg_op_defs[op];
-@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
-     const TCGArgConstraint *arg_ct = &def->args_ct[k];
-     int n;
--    if (arg_ct->ct & TCG_CT_ALIAS) {
-+    if (arg_ct->oalias) {
-         /* an alias is equivalent to a single register */
-         n = 1;
-     } else {
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-             /* Incomplete TCGTargetOpDef entry. */
-             tcg_debug_assert(ct_str != NULL);
--            def->args_ct[i].regs = 0;
--            def->args_ct[i].ct = 0;
-             while (*ct_str != '\0') {
-                 switch(*ct_str) {
-                 case '0' ... '9':
-@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
-                         tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
-                         tcg_debug_assert(oarg < def->nb_oargs);
-                         tcg_debug_assert(def->args_ct[oarg].regs != 0);
--                        /* TCG_CT_ALIAS is for the output arguments.
--                           The input is tagged with TCG_CT_IALIAS. */
-                         def->args_ct[i] = def->args_ct[oarg];
--                        def->args_ct[oarg].ct |= TCG_CT_ALIAS;
-+                        /* The output sets oalias.  */
-+                        def->args_ct[oarg].oalias = true;
-                         def->args_ct[oarg].alias_index = i;
--                        def->args_ct[i].ct |= TCG_CT_IALIAS;
-+                        /* The input sets ialias. */
-+                        def->args_ct[i].ialias = true;
-                         def->args_ct[i].alias_index = oarg;
-                     }
-                     ct_str++;
-                     break;
-                 case '&':
--                    def->args_ct[i].ct |= TCG_CT_NEWREG;
-+                    def->args_ct[i].newreg = true;
-                     ct_str++;
-                     break;
-                 case 'i':
-@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
-                     set = *pset;
-                     set &= ct->regs;
--                    if (ct->ct & TCG_CT_IALIAS) {
-+                    if (ct->ialias) {
-                         set &= op->output_pref[ct->alias_index];
-                     }
-                     /* If the combination is not possible, restart.  */
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-         }
-         i_preferred_regs = o_preferred_regs = 0;
--        if (arg_ct->ct & TCG_CT_IALIAS) {
-+        if (arg_ct->ialias) {
-             o_preferred_regs = op->output_pref[arg_ct->alias_index];
-             if (ts->fixed_reg) {
-                 /* if fixed register, we must allocate a new register
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-                     reg = ts->reg;
-                     for (k2 = 0 ; k2 < k ; k2++) {
-                         i2 = def->args_ct[nb_oargs + k2].sort_index;
--                        if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
--                            reg == new_args[i2]) {
-+                        if (def->args_ct[i2].ialias && reg == new_args[i2]) {
-                             goto allocate_in_reg;
-                         }
-                     }
-@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
-             /* ENV should not be modified.  */
-             tcg_debug_assert(!ts->fixed_reg);
--            if ((arg_ct->ct & TCG_CT_ALIAS)
--                && !const_args[arg_ct->alias_index]) {
-+            if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
-                 reg = new_args[arg_ct->alias_index];
--            } else if (arg_ct->ct & TCG_CT_NEWREG) {
-+            } else if (arg_ct->newreg) {
-                 reg = tcg_reg_alloc(s, arg_ct->regs,
-                                     i_allocated_regs | o_allocated_regs,
-                                     op->output_pref[k], ts->indirect_base);
---
-.25.1

-[PULL 06/11] tcg: Remove TCGOpDef.used
+Deleted patch
-The last user of this field disappeared in f69d277ece4.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- include/tcg/tcg.h | 3 ---
-file changed, 3 deletions(-)
-diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/tcg/tcg.h
-+++ b/include/tcg/tcg.h
-@@ -XXX,XX +XXX,XX @@ typedef struct TCGOpDef {
-     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
-     uint8_t flags;
-     TCGArgConstraint *args_ct;
--#if defined(CONFIG_DEBUG_TCG)
--    int used;
--#endif
- } TCGOpDef;
- extern TCGOpDef tcg_op_defs[];
---
-.25.1

-[PULL 07/11] tcg/i386: Fix dupi for avx2 32-bit hosts
+Deleted patch
-The previous change wrongly stated that 32-bit avx2 should have
-used VPBROADCASTW.  But that's a 16-bit broadcast and we want a
--bit broadcast.
-Fixes: 7b60ef3264e
-Cc: qemu-stable@nongnu.org
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
----
- tcg/i386/tcg-target.c.inc | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/tcg/i386/tcg-target.c.inc
-+++ b/tcg/i386/tcg-target.c.inc
-@@ -XXX,XX +XXX,XX @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
-         new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
-     } else {
-         if (have_avx2) {
--            tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret);
-+            tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
-         } else {
-             tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
-         }
---
-.25.1

-[PULL 11/11] accel/tcg: Fix computing of is_write for MIPS
+[PULL 5/5] decodetree: Extend argument set syntax to allow types
-From: Kele Huang <kele.hwang@gmail.com>
+Rather than force all structure members to be 'int',
 allow the type of the member to be specified.
-Detect all MIPS store instructions in cpu_signal_handler for all available
+Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
 MIPS versions, and set is_write if encountering such store instructions.
 This fixed the error while dealing with self-modified code for MIPS.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Kele Huang <kele.hwang@gmail.com>
 Signed-off-by: Xu Zou <iwatchnima@gmail.com>
 Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>
 [rth: Use uintptr_t for pc to fix n32 build error.]
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 ---
- accel/tcg/user-exec.c | 43 +++++++++++++++++++++++++++++++++++++++----
+ docs/devel/decodetree.rst             | 11 ++++---
-file changed, 39 insertions(+), 4 deletions(-)
+ tests/decode/succ_argset_type1.decode |  1 +
  scripts/decodetree.py                 | 45 +++++++++++++++++----------
 files changed, 36 insertions(+), 21 deletions(-)
  create mode 100644 tests/decode/succ_argset_type1.decode
-diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
+diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/user-exec.c
+--- a/docs/devel/decodetree.rst
-+++ b/accel/tcg/user-exec.c
++++ b/docs/devel/decodetree.rst
-@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
+@@ -XXX,XX +XXX,XX @@ and returns an integral value extracted from there.
- #elif defined(__mips__)
+ A field with no ``unnamed_fields`` and no ``!function`` is in error.
-+#if defined(__misp16) || defined(__mips_micromips)
+-FIXME: the fields of the structure into which this result will be stored
-+#error "Unsupported encoding"
+-is restricted to ``int``.  Which means that we cannot expand 64-bit items.
-+#endif
+-
  Field examples:
  +---------------------------+---------------------------------------------+
@@ -XXX,XX +XXX,XX @@ Argument Sets
  Syntax::
    args_def    := '&' identifier ( args_elt )+ ( !extern )?
 -  args_elt    := identifier
 +  args_elt    := identifier (':' identifier)?
  Each *args_elt* defines an argument within the argument set.
 +If the form of the *args_elt* contains a colon, the first
 +identifier is the argument name and the second identifier is
 +the argument type.  If the colon is missing, the argument
 +type will be ``int``.
 +
- int cpu_signal_handler(int host_signum, void *pinfo,
+ Each argument set will be rendered as a C structure "arg_$name"
-                        void *puc)
+ with each of the fields being one of the member arguments.
- {
-     siginfo_t *info = pinfo;
+@@ -XXX,XX +XXX,XX @@ Argument set examples::
-     ucontext_t *uc = puc;
--    greg_t pc = uc->uc_mcontext.pc;
+   &reg3       ra rb rc
--    int is_write;
+   &loadstore  reg base offset
-+    uintptr_t pc = uc->uc_mcontext.pc;
++  &longldst   reg base offset:int64_t
-+    uint32_t insn = *(uint32_t *)pc;
-+    int is_write = 0;
-+
+ Formats
-+    /* Detect all store instructions at program counter. */
+diff --git a/tests/decode/succ_argset_type1.decode b/tests/decode/succ_argset_type1.decode
-+    switch((insn >> 26) & 077) {
+new file mode 100644
-+    case 050: /* SB */
+index XXXXXXX..XXXXXXX
-+    case 051: /* SH */
+--- /dev/null
-+    case 052: /* SWL */
++++ b/tests/decode/succ_argset_type1.decode
-+    case 053: /* SW */
+@@ -0,0 +1 @@
-+    case 054: /* SDL */
++&asdf b:bool c:uint64_t a
-+    case 055: /* SDR */
+diff --git a/scripts/decodetree.py b/scripts/decodetree.py
-+    case 056: /* SWR */
+index XXXXXXX..XXXXXXX 100644
-+    case 070: /* SC */
+--- a/scripts/decodetree.py
-+    case 071: /* SWC1 */
++++ b/scripts/decodetree.py
-+    case 074: /* SCD */
+@@ -XXX,XX +XXX,XX @@ def is_contiguous(bits):
-+    case 075: /* SDC1 */
+         return -1
-+    case 077: /* SD */
-+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
-+    case 072: /* SWC2 */
+-def eq_fields_for_args(flds_a, flds_b):
-+    case 076: /* SDC2 */
+-    if len(flds_a) != len(flds_b):
-+#endif
++def eq_fields_for_args(flds_a, arg):
-+        is_write = 1;
++    if len(flds_a) != len(arg.fields):
-+        break;
+         return False
-+    case 023: /* COP1X */
++    # Only allow inference on default types
-+        /* Required in all versions of MIPS64 since
++    for t in arg.types:
-+           MIPS64r1 and subsequent versions of MIPS32r2. */
++        if t != 'int':
-+        switch (insn & 077) {
++            return False
-+        case 010: /* SWXC1 */
+     for k, a in flds_a.items():
-+        case 011: /* SDXC1 */
+-        if k not in flds_b:
-+        case 015: /* SUXC1 */
++        if k not in arg.fields:
-+            is_write = 1;
+             return False
-+        }
+     return True
-+        break;
-+    }
+@@ -XXX,XX +XXX,XX @@ def __ne__(self, other):
--    /* XXX: compute is_write */
+ class Arguments:
--    is_write = 0;
+     """Class representing the extracted fields of a format"""
-     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
+-    def __init__(self, nm, flds, extern):
- }
++    def __init__(self, nm, flds, types, extern):
          self.name = nm
          self.extern = extern
 -        self.fields = sorted(flds)
 +        self.fields = flds
 +        self.types = types
      def __str__(self):
          return self.name + ' ' + str(self.fields)
@@ -XXX,XX +XXX,XX @@ def struct_name(self):
      def output_def(self):
          if not self.extern:
              output('typedef struct {\n')
 -            for n in self.fields:
 -                output('    int ', n, ';\n')
 +            for (n, t) in zip(self.fields, self.types):
 +                output(f'    {t} {n};\n')
              output('} ', self.struct_name(), ';\n\n')
  # end Arguments
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
      global anyextern
      flds = []
 +    types = []
      extern = False
 -    for t in toks:
 -        if re.fullmatch('!extern', t):
 +    for n in toks:
 +        if re.fullmatch('!extern', n):
              extern = True
              anyextern = True
              continue
 -        if not re.fullmatch(re_C_ident, t):
 -            error(lineno, f'invalid argument set token "{t}"')
 -        if t in flds:
 -            error(lineno, f'duplicate argument "{t}"')
 -        flds.append(t)
 +        if re.fullmatch(re_C_ident + ':' + re_C_ident, n):
 +            (n, t) = n.split(':')
 +        elif re.fullmatch(re_C_ident, n):
 +            t = 'int'
 +        else:
 +            error(lineno, f'invalid argument set token "{n}"')
 +        if n in flds:
 +            error(lineno, f'duplicate argument "{n}"')
 +        flds.append(n)
 +        types.append(t)
      if name in arguments:
          error(lineno, 'duplicate argument set', name)
 -    arguments[name] = Arguments(name, flds, extern)
 +    arguments[name] = Arguments(name, flds, types, extern)
  # end parse_arguments
@@ -XXX,XX +XXX,XX @@ def infer_argument_set(flds):
      global decode_function
      for arg in arguments.values():
 -        if eq_fields_for_args(flds, arg.fields):
 +        if eq_fields_for_args(flds, arg):
              return arg
      name = decode_function + str(len(arguments))
 -    arg = Arguments(name, flds.keys(), False)
 +    arg = Arguments(name, flds.keys(), ['int'] * len(flds), False)
      arguments[name] = arg
      return arg
 --
 .25.1

The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)

are available in the Git repository at:

https://github.com/rth7680/qemu.git tags/pull-tcg-20201008

for you to fetch changes up to 62475e9d007d83db4d0a6ccebcda8914f392e9c9:

accel/tcg: Fix computing of is_write for MIPS (2020-10-08 05:57:32 -0500)

----------------------------------------------------------------
Extend maximum gvec vector size
Fix i386 avx2 dupi
Fix mips host user-only write detection
Misc cleanups.

----------------------------------------------------------------
Kele Huang (1):
      accel/tcg: Fix computing of is_write for MIPS

Richard Henderson (10):
      tcg: Adjust simd_desc size encoding
      tcg: Drop union from TCGArgConstraint
      tcg: Move sorted_args into TCGArgConstraint.sort_index
      tcg: Remove TCG_CT_REG
      tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
      tcg: Remove TCGOpDef.used
      tcg/i386: Fix dupi for avx2 32-bit hosts
      tcg: Fix generation of dupi_vec for 32-bit host
      tcg/optimize: Fold dup2_vec
      tcg: Remove TCG_TARGET_HAS_cmp_vec

With larger vector sizes, it turns out oprsz == maxsz, and we only
need to represent mismatch for oprsz <= 32.  We do, however, need
to represent larger oprsz and do so without reducing SIMD_DATA_BITS.

Reduce the size of the oprsz field and increase the maxsz field.
Steal the oprsz value of 24 to indicate equality with maxsz.

Tested-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++-------------
 tcg/tcg-op-gvec.c           | 35 ++++++++++++++++++++++++++--------
 2 files changed, 52 insertions(+), 21 deletions(-)

diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg-gvec-desc.h
+++ b/include/tcg/tcg-gvec-desc.h
@@ -XXX,XX +XXX,XX @@
 #ifndef TCG_TCG_GVEC_DESC_H
 #define TCG_TCG_GVEC_DESC_H
 
-/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
-#define SIMD_OPRSZ_SHIFT   0
-#define SIMD_OPRSZ_BITS    5
+/*
+ * This configuration allows MAXSZ to represent 2048 bytes, and
+ * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
+ *
+ * Encode this with:
+ *   0, 1, 3 -> 8, 16, 32
+ *   2       -> maxsz
+ *
+ * This steals the input that would otherwise map to 24 to match maxsz.
+ */
+#define SIMD_MAXSZ_SHIFT   0
+#define SIMD_MAXSZ_BITS    8
 
-#define SIMD_MAXSZ_SHIFT   (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
-#define SIMD_MAXSZ_BITS    5
+#define SIMD_OPRSZ_SHIFT   (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_OPRSZ_BITS    2
 
-#define SIMD_DATA_SHIFT    (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_DATA_SHIFT    (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
 #define SIMD_DATA_BITS     (32 - SIMD_DATA_SHIFT)
 
 /* Create a descriptor from components.  */
 uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
 
-/* Extract the operation size from a descriptor.  */
-static inline intptr_t simd_oprsz(uint32_t desc)
-{
-    return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
-}
-
 /* Extract the max vector size from a descriptor.  */
 static inline intptr_t simd_maxsz(uint32_t desc)
 {
-    return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
+    return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
+}
+
+/* Extract the operation size from a descriptor.  */
+static inline intptr_t simd_oprsz(uint32_t desc)
+{
+    uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
+    intptr_t o = f * 8 + 8;
+    intptr_t m = simd_maxsz(desc);
+    return f == 2 ? m : o;
 }
 
 /* Extract the operation-specific data from a descriptor.  */
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -XXX,XX +XXX,XX @@ static const TCGOpcode vecop_list_empty[1] = { 0 };
    of the operand offsets so that we can check them all at once.  */
 static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
 {
-    uint32_t opr_align = oprsz >= 16 ? 15 : 7;
-    uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
-    tcg_debug_assert(oprsz > 0);
-    tcg_debug_assert(oprsz <= maxsz);
-    tcg_debug_assert((oprsz & opr_align) == 0);
+    uint32_t max_align;
+
+    switch (oprsz) {
+    case 8:
+    case 16:
+    case 32:
+        tcg_debug_assert(oprsz <= maxsz);
+        break;
+    default:
+        tcg_debug_assert(oprsz == maxsz);
+        break;
+    }
+    tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));
+
+    max_align = maxsz >= 16 ? 15 : 7;
     tcg_debug_assert((maxsz & max_align) == 0);
     tcg_debug_assert((ofs & max_align) == 0);
 }
@@ -XXX,XX +XXX,XX @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
 {
     uint32_t desc = 0;
 
-    assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
-    assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
-    assert(data == sextract32(data, 0, SIMD_DATA_BITS));
+    check_size_align(oprsz, maxsz, 0);
+    tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));
 
     oprsz = (oprsz / 8) - 1;
     maxsz = (maxsz / 8) - 1;
+
+    /*
+     * We have just asserted in check_size_align that either
+     * oprsz is {8,16,32} or matches maxsz.  Encode the final
+     * case with '2', as that would otherwise map to 24.
+     */
+    if (oprsz == maxsz) {
+        oprsz = 2;
+    }
+
     desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
     desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
     desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
-- 
2.25.1

The union is unused; let "regs" appear in the main structure
without the "u.regs" wrapping.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h            |  4 +---
 tcg/tcg.c                    | 22 +++++++++++-----------
 tcg/aarch64/tcg-target.c.inc | 14 +++++++-------
 tcg/arm/tcg-target.c.inc     | 26 +++++++++++++-------------
 tcg/i386/tcg-target.c.inc    | 26 +++++++++++++-------------
 tcg/mips/tcg-target.c.inc    | 18 +++++++++---------
 tcg/ppc/tcg-target.c.inc     | 24 ++++++++++++------------
 tcg/riscv/tcg-target.c.inc   | 14 +++++++-------
 tcg/s390/tcg-target.c.inc    | 18 +++++++++---------
 tcg/sparc/tcg-target.c.inc   | 16 ++++++++--------
 tcg/tci/tcg-target.c.inc     |  2 +-
 11 files changed, 91 insertions(+), 93 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
 typedef struct TCGArgConstraint {
     uint16_t ct;
     uint8_t alias_index;
-    union {
-        TCGRegSet regs;
-    } u;
+    TCGRegSet regs;
 } TCGArgConstraint;
 
 #define TCG_MAX_OP_ARGS 16
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
             return 0;
         n = 0;
         for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
-            if (tcg_regset_test_reg(arg_ct->u.regs, i))
+            if (tcg_regset_test_reg(arg_ct->regs, i))
                 n++;
         }
     }
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
             /* Incomplete TCGTargetOpDef entry. */
             tcg_debug_assert(ct_str != NULL);
 
-            def->args_ct[i].u.regs = 0;
+            def->args_ct[i].regs = 0;
             def->args_ct[i].ct = 0;
             while (*ct_str != '\0') {
                 switch(*ct_str) {
@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
                     pset = la_temp_pref(ts);
                     set = *pset;
 
-                    set &= ct->u.regs;
+                    set &= ct->regs;
                     if (ct->ct & TCG_CT_IALIAS) {
                         set &= op->output_pref[ct->alias_index];
                     }
                     /* If the combination is not possible, restart.  */
                     if (set == 0) {
-                        set = ct->u.regs;
+                        set = ct->regs;
                     }
                     *pset = set;
                 }
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
         return;
     }
 
-    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
-    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
+    dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
+    dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
 
     /* Allocate the output register now.  */
     if (ots->val_type != TEMP_VAL_REG) {
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             }
         }
 
-        temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);
+        temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
         reg = ts->reg;
 
-        if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
+        if (tcg_regset_test_reg(arg_ct->regs, reg)) {
             /* nothing to do : the constraint is satisfied */
         } else {
         allocate_in_reg:
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                and move the temporary register into it */
             temp_load(s, ts, tcg_target_available_regs[ts->type],
                       i_allocated_regs, 0);
-            reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
+            reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
                                 o_preferred_regs, ts->indirect_base);
             if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
                 /*
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                 && !const_args[arg_ct->alias_index]) {
                 reg = new_args[arg_ct->alias_index];
             } else if (arg_ct->ct & TCG_CT_NEWREG) {
-                reg = tcg_reg_alloc(s, arg_ct->u.regs,
+                reg = tcg_reg_alloc(s, arg_ct->regs,
                                     i_allocated_regs | o_allocated_regs,
                                     op->output_pref[k], ts->indirect_base);
             } else {
-                reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
+                reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
                                     op->output_pref[k], ts->indirect_base);
             }
             tcg_regset_set_reg(o_allocated_regs, reg);
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'r': /* general registers */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs |= 0xffffffffu;
+        ct->regs |= 0xffffffffu;
         break;
     case 'w': /* advsimd registers */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs |= 0xffffffff00000000ull;
+        ct->regs |= 0xffffffff00000000ull;
         break;
     case 'l': /* qemu_ld / qemu_st address, data_reg */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffffu;
+        ct->regs = 0xffffffffu;
 #ifdef CONFIG_SOFTMMU
         /* x0 and x1 will be overwritten when reading the tlb entry,
            and x2, and x3 for helper args, better to avoid using them. */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
 #endif
         break;
     case 'A': /* Valid for arithmetic immediate (positive or negative).  */
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
+        ct->regs = 0xffff;
         break;
 
     /* qemu_ld address */
     case 'l':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
+        ct->regs = 0xffff;
 #ifdef CONFIG_SOFTMMU
         /* r0-r2,lr will be overwritten when reading the tlb entry,
            so don't use these. */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
 #endif
         break;
 
     /* qemu_st address & data */
     case 's':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
+        ct->regs = 0xffff;
         /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
            and r0-r1 doing the byte swapping, so don't use these. */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
 #if defined(CONFIG_SOFTMMU)
         /* Avoid clashes with registers being used for helper args */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
 #if TARGET_LONG_BITS == 64
         /* Avoid clashes with registers being used for helper args */
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #endif
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
 #endif
         break;
 
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch(*ct_str++) {
     case 'a':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
+        tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
         break;
     case 'b':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
+        tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
         break;
     case 'c':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
+        tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
         break;
     case 'd':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
+        tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
         break;
     case 'S':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
+        tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
         break;
     case 'D':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
+        tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
         break;
     case 'q':
         /* A register that can be used as a byte operand.  */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
+        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
         break;
     case 'Q':
         /* A register with an addressable second byte (e.g. %ah).  */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xf;
+        ct->regs = 0xf;
         break;
     case 'r':
         /* A general register.  */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs |= ALL_GENERAL_REGS;
+        ct->regs |= ALL_GENERAL_REGS;
         break;
     case 'W':
         /* With TZCNT/LZCNT, we can have operand-size as an input.  */
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     case 'x':
         /* A vector register.  */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs |= ALL_VECTOR_REGS;
+        ct->regs |= ALL_VECTOR_REGS;
         break;
 
         /* qemu_ld/st address constraint */
     case 'L':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
+        ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
         break;
 
     case 'e':
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch(*ct_str++) {
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         break;
     case 'L': /* qemu_ld input arg constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
+        ct->regs = 0xffffffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
 #if defined(CONFIG_SOFTMMU)
         if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
+            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
         }
 #endif
         break;
     case 'S': /* qemu_st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
+        ct->regs = 0xffffffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
 #if defined(CONFIG_SOFTMMU)
         if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
-            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
-            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
+            tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
+            tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
         } else {
-            tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
+            tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
         }
 #endif
         break;
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'A': case 'B': case 'C': case 'D':
         ct->ct |= TCG_CT_REG;
-        tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
+        tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
         break;
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         break;
     case 'v':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff00000000ull;
+        ct->regs = 0xffffffff00000000ull;
         break;
     case 'L':                   /* qemu_ld constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+        ct->regs = 0xffffffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #ifdef CONFIG_SOFTMMU
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
 #endif
         break;
     case 'S':                   /* qemu_st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+        ct->regs = 0xffffffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #ifdef CONFIG_SOFTMMU
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
 #endif
         break;
     case 'I':
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         break;
     case 'L':
         /* qemu_ld/qemu_st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
 #if defined(CONFIG_SOFTMMU)
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
-        tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
+        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
 #endif
         break;
     case 'I':
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'r':                  /* all registers */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
+        ct->regs = 0xffff;
         break;
     case 'L':                  /* qemu_ld/st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffff;
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
+        ct->regs = 0xffff;
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
         break;
     case 'a':                  /* force R2 for division */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
+        ct->regs = 0;
+        tcg_regset_set_reg(ct->regs, TCG_REG_R2);
         break;
     case 'b':                  /* force R3 for division */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0;
-        tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
+        ct->regs = 0;
+        tcg_regset_set_reg(ct->regs, TCG_REG_R3);
         break;
     case 'A':
         ct->ct |= TCG_CT_CONST_S33;
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     switch (*ct_str++) {
     case 'r':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         break;
     case 'R':
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = ALL_64;
+        ct->regs = ALL_64;
         break;
     case 'A': /* qemu_ld/st address constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
+        ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
     reserve_helpers:
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
-        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
+        tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
         break;
     case 's': /* qemu_st data 32-bit constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = 0xffffffff;
+        ct->regs = 0xffffffff;
         goto reserve_helpers;
     case 'S': /* qemu_st data 64-bit constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = ALL_64;
+        ct->regs = ALL_64;
         goto reserve_helpers;
     case 'I':
         ct->ct |= TCG_CT_CONST_S11;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     case 'L':                   /* qemu_ld constraint */
     case 'S':                   /* qemu_st constraint */
         ct->ct |= TCG_CT_REG;
-        ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
+        ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
         break;
     default:
         return NULL;
-- 
2.25.1

This uses an existing hole in the TCGArgConstraint structure
and will be convenient for keeping the data in one place.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h |  2 +-
 tcg/tcg.c         | 35 +++++++++++++++++------------------
 2 files changed, 18 insertions(+), 19 deletions(-)

This wasn't actually used for anything, really.  All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ void tcg_dump_op_count(void);
 #define TCG_CT_ALIAS  0x80
 #define TCG_CT_IALIAS 0x40
 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
-#define TCG_CT_REG    0x01
 #define TCG_CT_CONST  0x02 /* any constant of register size */
 
 typedef struct TCGArgConstraint {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
 /* we give more priority to constraints with less registers */
 static int get_constraint_priority(const TCGOpDef *def, int k)
 {
-    const TCGArgConstraint *arg_ct;
+    const TCGArgConstraint *arg_ct = &def->args_ct[k];
+    int n;
 
-    int i, n;
-    arg_ct = &def->args_ct[k];
     if (arg_ct->ct & TCG_CT_ALIAS) {
         /* an alias is equivalent to a single register */
         n = 1;
     } else {
-        if (!(arg_ct->ct & TCG_CT_REG))
-            return 0;
-        n = 0;
-        for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
-            if (tcg_regset_test_reg(arg_ct->regs, i))
-                n++;
-        }
+        n = ctpop64(arg_ct->regs);
     }
     return TCG_TARGET_NB_REGS - n + 1;
 }
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                         int oarg = *ct_str - '0';
                         tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
                         tcg_debug_assert(oarg < def->nb_oargs);
-                        tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
+                        tcg_debug_assert(def->args_ct[oarg].regs != 0);
                         /* TCG_CT_ALIAS is for the output arguments.
                            The input is tagged with TCG_CT_IALIAS. */
                         def->args_ct[i] = def->args_ct[oarg];
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r': /* general registers */
-        ct->ct |= TCG_CT_REG;
         ct->regs |= 0xffffffffu;
         break;
     case 'w': /* advsimd registers */
-        ct->ct |= TCG_CT_REG;
         ct->regs |= 0xffffffff00000000ull;
         break;
     case 'l': /* qemu_ld / qemu_st address, data_reg */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffffu;
 #ifdef CONFIG_SOFTMMU
         /* x0 and x1 will be overwritten when reading the tlb entry,
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
         break;
 
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
         break;
 
     /* qemu_ld address */
     case 'l':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
 #ifdef CONFIG_SOFTMMU
         /* r0-r2,lr will be overwritten when reading the tlb entry,
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 
     /* qemu_st address & data */
     case 's':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
         /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
            and r0-r1 doing the byte swapping, so don't use these. */
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch(*ct_str++) {
     case 'a':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
         break;
     case 'b':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
         break;
     case 'c':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
         break;
     case 'd':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
         break;
     case 'S':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
         break;
     case 'D':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
         break;
     case 'q':
         /* A register that can be used as a byte operand.  */
-        ct->ct |= TCG_CT_REG;
         ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
         break;
     case 'Q':
         /* A register with an addressable second byte (e.g. %ah).  */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xf;
         break;
     case 'r':
         /* A general register.  */
-        ct->ct |= TCG_CT_REG;
         ct->regs |= ALL_GENERAL_REGS;
         break;
     case 'W':
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
         break;
     case 'x':
         /* A vector register.  */
-        ct->ct |= TCG_CT_REG;
         ct->regs |= ALL_VECTOR_REGS;
         break;
 
         /* qemu_ld/st address constraint */
     case 'L':
-        ct->ct |= TCG_CT_REG;
         ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
         tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch(*ct_str++) {
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         break;
     case 'L': /* qemu_ld input arg constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
 #if defined(CONFIG_SOFTMMU)
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 #endif
         break;
     case 'S': /* qemu_st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
 #if defined(CONFIG_SOFTMMU)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'A': case 'B': case 'C': case 'D':
-        ct->ct |= TCG_CT_REG;
         tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
         break;
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         break;
     case 'v':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff00000000ull;
         break;
     case 'L':                   /* qemu_ld constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #ifdef CONFIG_SOFTMMU
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 #endif
         break;
     case 'S':                   /* qemu_st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
 #ifdef CONFIG_SOFTMMU
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         break;
     case 'L':
         /* qemu_ld/qemu_st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
 #if defined(CONFIG_SOFTMMU)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r':                  /* all registers */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
         break;
     case 'L':                  /* qemu_ld/st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffff;
         tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
         tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
         tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
         break;
     case 'a':                  /* force R2 for division */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0;
         tcg_regset_set_reg(ct->regs, TCG_REG_R2);
         break;
     case 'b':                  /* force R3 for division */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0;
         tcg_regset_set_reg(ct->regs, TCG_REG_R3);
         break;
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
 {
     switch (*ct_str++) {
     case 'r':
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         break;
     case 'R':
-        ct->ct |= TCG_CT_REG;
         ct->regs = ALL_64;
         break;
     case 'A': /* qemu_ld/st address constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
     reserve_helpers:
         tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
         tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
         break;
     case 's': /* qemu_st data 32-bit constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = 0xffffffff;
         goto reserve_helpers;
     case 'S': /* qemu_st data 64-bit constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = ALL_64;
         goto reserve_helpers;
     case 'I':
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -XXX,XX +XXX,XX @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
     case 'r':
     case 'L':                   /* qemu_ld constraint */
     case 'S':                   /* qemu_st constraint */
-        ct->ct |= TCG_CT_REG;
         ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
         break;
     default:
-- 
2.25.1

These are easier to set and test when they have their own fields.
Reduce the size of alias_index and sort_index to 4 bits, which is
sufficient for TCG_MAX_OP_ARGS.  This leaves only the bits indicating
constants within the ct field.

Move all initialization to allocation time, rather than init
individual fields in process_op_defs.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/tcg/tcg.h | 14 +++++++-------
 tcg/tcg.c         | 28 ++++++++++++----------------
 2 files changed, 19 insertions(+), 23 deletions(-)

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void);
 void tcg_dump_info(void);
 void tcg_dump_op_count(void);
 
-#define TCG_CT_ALIAS  0x80
-#define TCG_CT_IALIAS 0x40
-#define TCG_CT_NEWREG 0x20 /* output requires a new register */
-#define TCG_CT_CONST  0x02 /* any constant of register size */
+#define TCG_CT_CONST  1 /* any constant of register size */
 
 typedef struct TCGArgConstraint {
-    uint16_t ct;
-    uint8_t alias_index;
-    uint8_t sort_index;
+    unsigned ct : 16;
+    unsigned alias_index : 4;
+    unsigned sort_index : 4;
+    bool oalias : 1;
+    bool ialias : 1;
+    bool newreg : 1;
     TCGRegSet regs;
 } TCGArgConstraint;
 
diff --git a/tcg/tcg.c b/tcg/tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -XXX,XX +XXX,XX @@ void tcg_context_init(TCGContext *s)
         total_args += n;
     }
 
-    args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
+    args_ct = g_new0(TCGArgConstraint, total_args);
 
     for(op = 0; op < NB_OPS; op++) {
         def = &tcg_op_defs[op];
@@ -XXX,XX +XXX,XX @@ static int get_constraint_priority(const TCGOpDef *def, int k)
     const TCGArgConstraint *arg_ct = &def->args_ct[k];
     int n;
 
-    if (arg_ct->ct & TCG_CT_ALIAS) {
+    if (arg_ct->oalias) {
         /* an alias is equivalent to a single register */
         n = 1;
     } else {
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
             /* Incomplete TCGTargetOpDef entry. */
             tcg_debug_assert(ct_str != NULL);
 
-            def->args_ct[i].regs = 0;
-            def->args_ct[i].ct = 0;
             while (*ct_str != '\0') {
                 switch(*ct_str) {
                 case '0' ... '9':
@@ -XXX,XX +XXX,XX @@ static void process_op_defs(TCGContext *s)
                         tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
                         tcg_debug_assert(oarg < def->nb_oargs);
                         tcg_debug_assert(def->args_ct[oarg].regs != 0);
-                        /* TCG_CT_ALIAS is for the output arguments.
-                           The input is tagged with TCG_CT_IALIAS. */
                         def->args_ct[i] = def->args_ct[oarg];
-                        def->args_ct[oarg].ct |= TCG_CT_ALIAS;
+                        /* The output sets oalias.  */
+                        def->args_ct[oarg].oalias = true;
                         def->args_ct[oarg].alias_index = i;
-                        def->args_ct[i].ct |= TCG_CT_IALIAS;
+                        /* The input sets ialias. */
+                        def->args_ct[i].ialias = true;
                         def->args_ct[i].alias_index = oarg;
                     }
                     ct_str++;
                     break;
                 case '&':
-                    def->args_ct[i].ct |= TCG_CT_NEWREG;
+                    def->args_ct[i].newreg = true;
                     ct_str++;
                     break;
                 case 'i':
@@ -XXX,XX +XXX,XX @@ static void liveness_pass_1(TCGContext *s)
                     set = *pset;
 
                     set &= ct->regs;
-                    if (ct->ct & TCG_CT_IALIAS) {
+                    if (ct->ialias) {
                         set &= op->output_pref[ct->alias_index];
                     }
                     /* If the combination is not possible, restart.  */
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
         }
 
         i_preferred_regs = o_preferred_regs = 0;
-        if (arg_ct->ct & TCG_CT_IALIAS) {
+        if (arg_ct->ialias) {
             o_preferred_regs = op->output_pref[arg_ct->alias_index];
             if (ts->fixed_reg) {
                 /* if fixed register, we must allocate a new register
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
                     reg = ts->reg;
                     for (k2 = 0 ; k2 < k ; k2++) {
                         i2 = def->args_ct[nb_oargs + k2].sort_index;
-                        if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
-                            reg == new_args[i2]) {
+                        if (def->args_ct[i2].ialias && reg == new_args[i2]) {
                             goto allocate_in_reg;
                         }
                     }
@@ -XXX,XX +XXX,XX @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
             /* ENV should not be modified.  */
             tcg_debug_assert(!ts->fixed_reg);
 
-            if ((arg_ct->ct & TCG_CT_ALIAS)
-                && !const_args[arg_ct->alias_index]) {
+            if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
                 reg = new_args[arg_ct->alias_index];
-            } else if (arg_ct->ct & TCG_CT_NEWREG) {
+            } else if (arg_ct->newreg) {
                 reg = tcg_reg_alloc(s, arg_ct->regs,
                                     i_allocated_regs | o_allocated_regs,
                                     op->output_pref[k], ts->indirect_base);
-- 
2.25.1

The definition of INDEX_op_dupi_vec is that it operates on
units of tcg_target_ulong -- in this case 32 bits.  It does
not work to use this for a uint64_t value that happens to be
small enough to fit in tcg_target_ulong.

Fixes: d2fd745fe8b
Fixes: db432672dc5
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg-op-vec.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -XXX,XX +XXX,XX @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
 
 void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
 {
-    if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
-        do_dupi_vec(r, MO_32, a);
-    } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
+    if (TCG_TARGET_REG_BITS == 64) {
         do_dupi_vec(r, MO_64, a);
+    } else if (a == dup_const(MO_32, a)) {
+        do_dupi_vec(r, MO_32, a);
     } else {
         TCGv_i64 c = tcg_const_i64(a);
         tcg_gen_dup_i64_vec(MO_64, r, c);
@@ -XXX,XX +XXX,XX @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
 
 void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
 {
-    do_dupi_vec(r, MO_REG, dup_const(vece, a));
+    if (vece == MO_64) {
+        tcg_gen_dup64i_vec(r, a);
+    } else {
+        do_dupi_vec(r, MO_REG, dup_const(vece, a));
+    }
 }
 
 void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
-- 
2.25.1

When the two arguments are identical, this can be reduced to
dup_vec or to mov_vec from a tcg_constant_vec.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/optimize.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/tcg/optimize.c b/tcg/optimize.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
             }
             goto do_default;
 
+        case INDEX_op_dup2_vec:
+            assert(TCG_TARGET_REG_BITS == 32);
+            if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+                tmp = arg_info(op->args[1])->val;
+                if (tmp == arg_info(op->args[2])->val) {
+                    tcg_opt_gen_movi(s, op, op->args[0], tmp);
+                    break;
+                }
+            } else if (args_are_copies(op->args[1], op->args[2])) {
+                op->opc = INDEX_op_dup_vec;
+                TCGOP_VECE(op) = MO_32;
+                nb_iargs = 1;
+            }
+            goto do_default;
+
         CASE_OP_32_64(not):
         CASE_OP_32_64(neg):
         CASE_OP_32_64(ext8s):
-- 
2.25.1

The cmp_vec opcode is mandatory; this symbol is unused.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/aarch64/tcg-target.h | 1 -
 tcg/i386/tcg-target.h    | 1 -
 tcg/ppc/tcg-target.h     | 1 -
 3 files changed, 3 deletions(-)

diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
-#define TCG_TARGET_HAS_cmp_vec          1
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          1
 #define TCG_TARGET_HAS_shv_vec          have_avx2
-#define TCG_TARGET_HAS_cmp_vec          1
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -XXX,XX +XXX,XX @@ extern bool have_vsx;
 #define TCG_TARGET_HAS_shi_vec          0
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
-#define TCG_TARGET_HAS_cmp_vec          1
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
-- 
2.25.1

From: Kele Huang <kele.hwang@gmail.com>

Detect all MIPS store instructions in cpu_signal_handler for all available
MIPS versions, and set is_write if encountering such store instructions.

This fixed the error while dealing with self-modified code for MIPS.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kele Huang <kele.hwang@gmail.com>
Signed-off-by: Xu Zou <iwatchnima@gmail.com>
Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>
[rth: Use uintptr_t for pc to fix n32 build error.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/user-exec.c | 43 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -XXX,XX +XXX,XX @@ int cpu_signal_handler(int host_signum, void *pinfo,
 
 #elif defined(__mips__)
 
+#if defined(__misp16) || defined(__mips_micromips)
+#error "Unsupported encoding"
+#endif
+
 int cpu_signal_handler(int host_signum, void *pinfo,
                        void *puc)
 {
     siginfo_t *info = pinfo;
     ucontext_t *uc = puc;
-    greg_t pc = uc->uc_mcontext.pc;
-    int is_write;
+    uintptr_t pc = uc->uc_mcontext.pc;
+    uint32_t insn = *(uint32_t *)pc;
+    int is_write = 0;
+
+    /* Detect all store instructions at program counter. */
+    switch((insn >> 26) & 077) {
+    case 050: /* SB */
+    case 051: /* SH */
+    case 052: /* SWL */
+    case 053: /* SW */
+    case 054: /* SDL */
+    case 055: /* SDR */
+    case 056: /* SWR */
+    case 070: /* SC */
+    case 071: /* SWC1 */
+    case 074: /* SCD */
+    case 075: /* SDC1 */
+    case 077: /* SD */
+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
+    case 072: /* SWC2 */
+    case 076: /* SDC2 */
+#endif
+        is_write = 1;
+        break;
+    case 023: /* COP1X */
+        /* Required in all versions of MIPS64 since
+           MIPS64r1 and subsequent versions of MIPS32r2. */
+        switch (insn & 077) {
+        case 010: /* SWXC1 */
+        case 011: /* SDXC1 */
+        case 015: /* SUXC1 */
+            is_write = 1;
+        }
+        break;
+    }
 
-    /* XXX: compute is_write */
-    is_write = 0;
     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 }
 
-- 
2.25.1

The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:

Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into staging (2021-04-30 16:02:00 +0100)

are available in the Git repository at:

https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210501

for you to fetch changes up to af93ccacc772019298be4c3e47251cdaa60d0c21:

decodetree: Extend argument set syntax to allow types (2021-05-01 11:45:35 -0700)

----------------------------------------------------------------
Include cleanups.
Decodetree enhancements for power10.

----------------------------------------------------------------
Luis Fernando Fujita Pires (1):
      decodetree: Add support for 64-bit instructions

Philippe Mathieu-Daudé (1):
      exec: Remove accel/tcg/ from include paths

Richard Henderson (3):
      decodetree: Introduce whex and whexC helpers
      decodetree: More use of f-strings
      decodetree: Extend argument set syntax to allow types

docs/devel/decodetree.rst             |  11 ++-
 meson.build                           |   1 -
 include/exec/helper-gen.h             |   4 +-
 include/exec/helper-proto.h           |   4 +-
 include/exec/helper-tcg.h             |   4 +-
 tests/decode/succ_argset_type1.decode |   1 +
 scripts/decodetree.py                 | 172 +++++++++++++++++++---------------
 7 files changed, 112 insertions(+), 85 deletions(-)
 create mode 100644 tests/decode/succ_argset_type1.decode

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

When TCG is enabled, the accel/tcg/ include path is added to the
project global include search list. This accel/tcg/ directory
contains a header named "internal.h" which, while intented to
be internal to accel/tcg/, is accessible by all files compiled
when TCG is enabled. This might lead to problem with other
directories using the same "internal.h" header name:

$ git ls-files | fgrep /internal.h
  accel/tcg/internal.h
  include/hw/ide/internal.h
  target/hexagon/internal.h
  target/mips/internal.h
  target/ppc/internal.h
  target/s390x/internal.h

As we don't need to expose accel/tcg/ internals to the rest of
the code base, simplify by removing it from the include search
list, and include the accel/tcg/ public headers relative to the
project root search path (which is already in the generic include
search path).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210413081008.3409459-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 meson.build                 | 1 -
 include/exec/helper-gen.h   | 4 ++--
 include/exec/helper-proto.h | 4 ++--
 include/exec/helper-tcg.h   | 4 ++--
 4 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if not get_option('tcg').disabled()
     tcg_arch = 'riscv'
   endif
   add_project_arguments('-iquote', meson.current_source_dir() / 'tcg' / tcg_arch,
-                        '-iquote', meson.current_source_dir() / 'accel/tcg',
                         language: ['c', 'cpp', 'objc'])
 
   accelerators += 'CONFIG_TCG'
diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-gen.h
+++ b/include/exec/helper-gen.h
@@ -XXX,XX +XXX,XX @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret)          \
 #include "helper.h"
 #include "trace/generated-helpers.h"
 #include "trace/generated-helpers-wrappers.h"
-#include "tcg-runtime.h"
-#include "plugin-helpers.h"
+#include "accel/tcg/tcg-runtime.h"
+#include "accel/tcg/plugin-helpers.h"
 
 #undef DEF_HELPER_FLAGS_0
 #undef DEF_HELPER_FLAGS_1
diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-proto.h
+++ b/include/exec/helper-proto.h
@@ -XXX,XX +XXX,XX @@ dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \
 
 #include "helper.h"
 #include "trace/generated-helpers.h"
-#include "tcg-runtime.h"
-#include "plugin-helpers.h"
+#include "accel/tcg/tcg-runtime.h"
+#include "accel/tcg/plugin-helpers.h"
 
 #undef IN_HELPER_PROTO
 
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-tcg.h
+++ b/include/exec/helper-tcg.h
@@ -XXX,XX +XXX,XX @@
 
 #include "helper.h"
 #include "trace/generated-helpers.h"
-#include "tcg-runtime.h"
-#include "plugin-helpers.h"
+#include "accel/tcg/tcg-runtime.h"
+#include "accel/tcg/plugin-helpers.h"
 
 #undef str
 #undef DEF_HELPER_FLAGS_0
-- 
2.25.1

Form a hex constant of the appropriate insnwidth.
Begin using f-strings on changed lines.

Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 scripts/decodetree.py | 66 +++++++++++++++++++++++++------------------
 1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index XXXXXXX..XXXXXXX 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -XXX,XX +XXX,XX @@ def str_fields(fields):
     return r[1:]
 
 
+def whex(val):
+    """Return a hex string for val padded for insnwidth"""
+    global insnwidth
+    return f'0x{val:0{insnwidth // 4}x}'
+
+
+def whexC(val):
+    """Return a hex string for val padded for insnwidth,
+       and with the proper suffix for a C constant."""
+    suffix = ''
+    if val >= 0x80000000:
+        suffix = 'u'
+    return whex(val) + suffix
+
+
 def str_match_bits(bits, mask):
     """Return a string pretty-printing BITS/MASK"""
     global insnwidth
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
             if outermask != p.fixedmask:
                 innermask = p.fixedmask & ~outermask
                 innerbits = p.fixedbits & ~outermask
-                output(ind, 'if ((insn & ',
-                       '0x{0:08x}) == 0x{1:08x}'.format(innermask, innerbits),
-                       ') {\n')
-                output(ind, '    /* ',
-                       str_match_bits(p.fixedbits, p.fixedmask), ' */\n')
+                output(ind, f'if ((insn & {whexC(innermask)}) == {whexC(innerbits)}) {{\n')
+                output(ind, f'    /* {str_match_bits(p.fixedbits, p.fixedmask)} */\n')
                 p.output_code(i + 4, extracted, p.fixedbits, p.fixedmask)
                 output(ind, '}\n')
             else:
@@ -XXX,XX +XXX,XX @@ def __init__(self, fm, tm):
 
     def str1(self, i):
         ind = str_indent(i)
-        r = '{0}{1:08x}'.format(ind, self.fixedmask)
+        r = ind + whex(self.fixedmask)
         if self.format:
             r += ' ' + self.format.name
         r += ' [\n'
         for (b, s) in self.subs:
-            r += '{0}  {1:08x}:\n'.format(ind, b)
+            r += ind + f'  {whex(b)}:\n'
             r += s.str1(i + 4) + '\n'
         r += ind + ']'
         return r
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
         if sh > 0:
             # Propagate SH down into the local functions.
             def str_switch(b, sh=sh):
-                return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
+                return f'(insn >> {sh}) & {b >> sh:#x}'
 
             def str_case(b, sh=sh):
-                return '0x{0:x}'.format(b >> sh)
+                return hex(b >> sh)
         else:
             def str_switch(b):
-                return 'insn & 0x{0:08x}'.format(b)
+                return f'insn & {whexC(b)}'
 
             def str_case(b):
-                return '0x{0:08x}'.format(b)
+                return whexC(b)
 
         output(ind, 'switch (', str_switch(self.thismask), ') {\n')
         for b, s in sorted(self.subs):
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
 
     # Validate the masks that we have assembled.
     if fieldmask & fixedmask:
-        error(lineno, 'fieldmask overlaps fixedmask (0x{0:08x} & 0x{1:08x})'
-                      .format(fieldmask, fixedmask))
+        error(lineno, 'fieldmask overlaps fixedmask ',
+              f'({whex(fieldmask)} & {whex(fixedmask)})')
     if fieldmask & undefmask:
-        error(lineno, 'fieldmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
-                      .format(fieldmask, undefmask))
+        error(lineno, 'fieldmask overlaps undefmask ',
+              f'({whex(fieldmask)} & {whex(undefmask)})')
     if fixedmask & undefmask:
-        error(lineno, 'fixedmask overlaps undefmask (0x{0:08x} & 0x{1:08x})'
-                      .format(fixedmask, undefmask))
+        error(lineno, 'fixedmask overlaps undefmask ',
+              f'({whex(fixedmask)} & {whex(undefmask)})')
     if not is_format:
         allbits = fieldmask | fixedmask | undefmask
         if allbits != insnmask:
-            error(lineno, 'bits left unspecified (0x{0:08x})'
-                          .format(allbits ^ insnmask))
+            error(lineno, 'bits left unspecified ',
+                  f'({whex(allbits ^ insnmask)})')
 # end parse_general
 
 
@@ -XXX,XX +XXX,XX @@ def __init__(self, m, w):
 
     def str1(self, i):
         ind = str_indent(i)
-        r = '{0}{1:08x}'.format(ind, self.mask)
-        r += ' [\n'
+        r = ind + whex(self.mask) + ' [\n'
         for (b, s) in self.subs:
-            r += '{0}  {1:08x}:\n'.format(ind, b)
+            r += ind + f'  {whex(b)}:\n'
             r += s.str1(i + 4) + '\n'
         r += ind + ']'
         return r
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
         if sh > 0:
             # Propagate SH down into the local functions.
             def str_switch(b, sh=sh):
-                return '(insn >> {0}) & 0x{1:x}'.format(sh, b >> sh)
+                return f'(insn >> {sh}) & {b >> sh:#x}'
 
             def str_case(b, sh=sh):
-                return '0x{0:x}'.format(b >> sh)
+                return hex(b >> sh)
         else:
             def str_switch(b):
-                return 'insn & 0x{0:08x}'.format(b)
+                return f'insn & {whexC(b)}'
 
             def str_case(b):
-                return '0x{0:08x}'.format(b)
+                return whexC(b)
 
         output(ind, 'switch (', str_switch(self.mask), ') {\n')
         for b, s in sorted(self.subs):
@@ -XXX,XX +XXX,XX @@ def __init__(self, m, w):
         self.width = w
 
     def str1(self, i):
-        ind = str_indent(i)
-        return '{0}{1:08x}'.format(ind, self.mask)
+        return str_indent(i) + whex(self.mask)
 
     def __str__(self):
         return self.str1(0)
-- 
2.25.1

Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 scripts/decodetree.py | 50 ++++++++++++++++++++-----------------------
 1 file changed, 23 insertions(+), 27 deletions(-)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index XXXXXXX..XXXXXXX 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -XXX,XX +XXX,XX @@ def error_with_file(file, lineno, *args):
 
     prefix = ''
     if file:
-        prefix += '{0}:'.format(file)
+        prefix += f'{file}:'
     if lineno:
-        prefix += '{0}:'.format(lineno)
+        prefix += f'{lineno}:'
     if prefix:
         prefix += ' '
     print(prefix, end='error: ', file=sys.stderr)
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
             extr = 'sextract32'
         else:
             extr = 'extract32'
-        return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len)
+        return f'{extr}(insn, {self.pos}, {self.len})'
 
     def __eq__(self, other):
         return self.sign == other.sign and self.mask == other.mask
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
         ret = '0'
         pos = 0
         for f in reversed(self.subs):
+            ext = f.str_extract()
             if pos == 0:
-                ret = f.str_extract()
+                ret = ext
             else:
-                ret = 'deposit32({0}, {1}, {2}, {3})' \
-                      .format(ret, pos, 32 - pos, f.str_extract())
+                ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
             pos += f.len
         return ret
 
@@ -XXX,XX +XXX,XX @@ def parse_field(lineno, name, toks):
             subtoks = t.split(':')
             sign = False
         else:
-            error(lineno, 'invalid field token "{0}"'.format(t))
+            error(lineno, f'invalid field token "{t}"')
         po = int(subtoks[0])
         le = int(subtoks[1])
         if po + le > insnwidth:
-            error(lineno, 'field {0} too large'.format(t))
+            error(lineno, f'field {t} too large')
         f = Field(sign, po, le)
         subs.append(f)
         width += le
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
             anyextern = True
             continue
         if not re.fullmatch(re_C_ident, t):
-            error(lineno, 'invalid argument set token "{0}"'.format(t))
+            error(lineno, f'invalid argument set token "{t}"')
         if t in flds:
-            error(lineno, 'duplicate argument "{0}"'.format(t))
+            error(lineno, f'duplicate argument "{t}"')
         flds.append(t)
 
     if name in arguments:
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
                 flen = flen[1:]
             shift = int(flen, 10)
             if shift + width > insnwidth:
-                error(lineno, 'field {0} exceeds insnwidth'.format(fname))
+                error(lineno, f'field {fname} exceeds insnwidth')
             f = Field(sign, insnwidth - width - shift, shift)
             flds = add_field(lineno, flds, fname, f)
             fixedbits <<= shift
             fixedmask <<= shift
             undefmask <<= shift
         else:
-            error(lineno, 'invalid token "{0}"'.format(t))
+            error(lineno, f'invalid token "{t}"')
         width += shift
 
     if variablewidth and width < insnwidth and width % 8 == 0:
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
 
     # We should have filled in all of the bits of the instruction.
     elif not (is_format and width == 0) and width != insnwidth:
-        error(lineno, 'definition has {0} bits'.format(width))
+        error(lineno, f'definition has {width} bits')
 
     # Do not check for fields overlapping fields; one valid usage
     # is to be able to duplicate fields via import.
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
         if arg:
             for f in flds.keys():
                 if f not in arg.fields:
-                    error(lineno, 'field {0} not in argument set {1}'
-                                  .format(f, arg.name))
+                    error(lineno, f'field {f} not in argument set {arg.name}')
         else:
             arg = infer_argument_set(flds)
         if name in formats:
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
         arg = fmt.base
         for f in flds.keys():
             if f not in arg.fields:
-                error(lineno, 'field {0} not in argument set {1}'
-                              .format(f, arg.name))
+                error(lineno, f'field {f} not in argument set {arg.name}')
             if f in fmt.fields.keys():
-                error(lineno, 'field {0} set by format and pattern'.format(f))
+                error(lineno, f'field {f} set by format and pattern')
         for f in arg.fields:
             if f not in flds.keys() and f not in fmt.fields.keys():
-                error(lineno, 'field {0} not initialized'.format(f))
+                error(lineno, f'field {f} not initialized')
         pat = Pattern(name, lineno, fmt, fixedbits, fixedmask,
                       undefmask, fieldmask, flds, width)
         parent_pat.pats.append(pat)
@@ -XXX,XX +XXX,XX @@ def parse_file(f, parent_pat):
         elif re.fullmatch(re_pat_ident, name):
             parse_generic(start_lineno, parent_pat, name, toks)
         else:
-            error(lineno, 'invalid token "{0}"'.format(name))
+            error(lineno, f'invalid token "{name}"')
         toks = []
 
     if nesting != 0:
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
 
         # If we need to load more bytes to test, do so now.
         if extracted < self.width:
-            output(ind, 'insn = ', decode_function,
-                   '_load_bytes(ctx, insn, {0}, {1});\n'
-                   .format(extracted // 8, self.width // 8));
+            output(ind, f'insn = {decode_function}_load_bytes',
+                   f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
             extracted = self.width
 
         # Attempt to aid the compiler in producing compact switch statements.
@@ -XXX,XX +XXX,XX @@ def output_code(self, i, extracted, outerbits, outermask):
 
         # If we need to load more bytes, do so now.
         if extracted < self.width:
-            output(ind, 'insn = ', decode_function,
-                   '_load_bytes(ctx, insn, {0}, {1});\n'
-                   .format(extracted // 8, self.width // 8));
+            output(ind, f'insn = {decode_function}_load_bytes',
+                   f'(ctx, insn, {extracted // 8}, {self.width // 8});\n')
             extracted = self.width
         output(ind, 'return insn;\n')
 # end SizeLeaf
@@ -XXX,XX +XXX,XX @@ def build_size_tree(pats, width, outerbits, outermask):
         for p in pats:
             pnames.append(p.name + ':' + p.file + ':' + str(p.lineno))
         error_with_file(pats[0].file, pats[0].lineno,
-                        'overlapping patterns size {0}:'.format(width), pnames)
+                        f'overlapping patterns size {width}:', pnames)
 
     bins = {}
     for i in pats:
-- 
2.25.1

From: Luis Fernando Fujita Pires <luis.pires@eldorado.org.br>

Allow '64' to be specified for the instruction width command line params
and use the appropriate extract and deposit functions in that case.

This will be used to implement the new 64-bit Power ISA 3.1 instructions.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Message-Id: <CP2PR80MB3668E123E2EFDB0ACD3A46F1DA759@CP2PR80MB3668.lamprd80.prod.outlook.com>
[rth: Drop the change to the field type; use bitop_width instead of separate
variables for extract/deposit; use "ull" for 64-bit constants.]
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 scripts/decodetree.py | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index XXXXXXX..XXXXXXX 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -XXX,XX +XXX,XX @@
 import getopt
 
 insnwidth = 32
+bitop_width = 32
 insnmask = 0xffffffff
 variablewidth = False
 fields = {}
@@ -XXX,XX +XXX,XX @@ def whexC(val):
     """Return a hex string for val padded for insnwidth,
        and with the proper suffix for a C constant."""
     suffix = ''
-    if val >= 0x80000000:
+    if val >= 0x100000000:
+        suffix = 'ull'
+    elif val >= 0x80000000:
         suffix = 'u'
     return whex(val) + suffix
 
@@ -XXX,XX +XXX,XX @@ def __str__(self):
         return str(self.pos) + ':' + s + str(self.len)
 
     def str_extract(self):
-        if self.sign:
-            extr = 'sextract32'
-        else:
-            extr = 'extract32'
-        return f'{extr}(insn, {self.pos}, {self.len})'
+        global bitop_width
+        s = 's' if self.sign else ''
+        return f'{s}extract{bitop_width}(insn, {self.pos}, {self.len})'
 
     def __eq__(self, other):
         return self.sign == other.sign and self.mask == other.mask
@@ -XXX,XX +XXX,XX @@ def __str__(self):
         return str(self.subs)
 
     def str_extract(self):
+        global bitop_width
         ret = '0'
         pos = 0
         for f in reversed(self.subs):
@@ -XXX,XX +XXX,XX @@ def str_extract(self):
             if pos == 0:
                 ret = ext
             else:
-                ret = f'deposit32({ret}, {pos}, {32 - pos}, {ext})'
+                ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - pos}, {ext})'
             pos += f.len
         return ret
 
@@ -XXX,XX +XXX,XX @@ def main():
     global insntype
     global insnmask
     global decode_function
+    global bitop_width
     global variablewidth
     global anyextern
 
@@ -XXX,XX +XXX,XX @@ def main():
             if insnwidth == 16:
                 insntype = 'uint16_t'
                 insnmask = 0xffff
+            elif insnwidth == 64:
+                insntype = 'uint64_t'
+                insnmask = 0xffffffffffffffff
+                bitop_width = 64
             elif insnwidth != 32:
                 error(0, 'cannot handle insns of width', insnwidth)
         else:
-- 
2.25.1

Rather than force all structure members to be 'int',
allow the type of the member to be specified.

Reviewed-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 docs/devel/decodetree.rst             | 11 ++++---
 tests/decode/succ_argset_type1.decode |  1 +
 scripts/decodetree.py                 | 45 +++++++++++++++++----------
 3 files changed, 36 insertions(+), 21 deletions(-)
 create mode 100644 tests/decode/succ_argset_type1.decode

diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/devel/decodetree.rst
+++ b/docs/devel/decodetree.rst
@@ -XXX,XX +XXX,XX @@ and returns an integral value extracted from there.
 
 A field with no ``unnamed_fields`` and no ``!function`` is in error.
 
-FIXME: the fields of the structure into which this result will be stored
-is restricted to ``int``.  Which means that we cannot expand 64-bit items.
-
 Field examples:
 
 +---------------------------+---------------------------------------------+
@@ -XXX,XX +XXX,XX @@ Argument Sets
 Syntax::
 
   args_def    := '&' identifier ( args_elt )+ ( !extern )?
-  args_elt    := identifier
+  args_elt    := identifier (':' identifier)?
 
 Each *args_elt* defines an argument within the argument set.
+If the form of the *args_elt* contains a colon, the first
+identifier is the argument name and the second identifier is
+the argument type.  If the colon is missing, the argument
+type will be ``int``.
+
 Each argument set will be rendered as a C structure "arg_$name"
 with each of the fields being one of the member arguments.
 
@@ -XXX,XX +XXX,XX @@ Argument set examples::
 
   &reg3       ra rb rc
   &loadstore  reg base offset
+  &longldst   reg base offset:int64_t
 
 
 Formats
diff --git a/tests/decode/succ_argset_type1.decode b/tests/decode/succ_argset_type1.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/decode/succ_argset_type1.decode
@@ -0,0 +1 @@
+&asdf b:bool c:uint64_t a
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index XXXXXXX..XXXXXXX 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -XXX,XX +XXX,XX @@ def is_contiguous(bits):
         return -1
 
 
-def eq_fields_for_args(flds_a, flds_b):
-    if len(flds_a) != len(flds_b):
+def eq_fields_for_args(flds_a, arg):
+    if len(flds_a) != len(arg.fields):
         return False
+    # Only allow inference on default types
+    for t in arg.types:
+        if t != 'int':
+            return False
     for k, a in flds_a.items():
-        if k not in flds_b:
+        if k not in arg.fields:
             return False
     return True
 
@@ -XXX,XX +XXX,XX @@ def __ne__(self, other):
 
 class Arguments:
     """Class representing the extracted fields of a format"""
-    def __init__(self, nm, flds, extern):
+    def __init__(self, nm, flds, types, extern):
         self.name = nm
         self.extern = extern
-        self.fields = sorted(flds)
+        self.fields = flds
+        self.types = types
 
     def __str__(self):
         return self.name + ' ' + str(self.fields)
@@ -XXX,XX +XXX,XX @@ def struct_name(self):
     def output_def(self):
         if not self.extern:
             output('typedef struct {\n')
-            for n in self.fields:
-                output('    int ', n, ';\n')
+            for (n, t) in zip(self.fields, self.types):
+                output(f'    {t} {n};\n')
             output('} ', self.struct_name(), ';\n\n')
 # end Arguments
 
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
     global anyextern
 
     flds = []
+    types = []
     extern = False
-    for t in toks:
-        if re.fullmatch('!extern', t):
+    for n in toks:
+        if re.fullmatch('!extern', n):
             extern = True
             anyextern = True
             continue
-        if not re.fullmatch(re_C_ident, t):
-            error(lineno, f'invalid argument set token "{t}"')
-        if t in flds:
-            error(lineno, f'duplicate argument "{t}"')
-        flds.append(t)
+        if re.fullmatch(re_C_ident + ':' + re_C_ident, n):
+            (n, t) = n.split(':')
+        elif re.fullmatch(re_C_ident, n):
+            t = 'int'
+        else:
+            error(lineno, f'invalid argument set token "{n}"')
+        if n in flds:
+            error(lineno, f'duplicate argument "{n}"')
+        flds.append(n)
+        types.append(t)
 
     if name in arguments:
         error(lineno, 'duplicate argument set', name)
-    arguments[name] = Arguments(name, flds, extern)
+    arguments[name] = Arguments(name, flds, types, extern)
 # end parse_arguments
 
 
@@ -XXX,XX +XXX,XX @@ def infer_argument_set(flds):
     global decode_function
 
     for arg in arguments.values():
-        if eq_fields_for_args(flds, arg.fields):
+        if eq_fields_for_args(flds, arg):
             return arg
 
     name = decode_function + str(len(arguments))
-    arg = Arguments(name, flds.keys(), False)
+    arg = Arguments(name, flds.keys(), ['int'] * len(flds), False)
     arguments[name] = arg
     return arg
 
-- 
2.25.1