[PULL 00/18] target-arm queue
[PULL 00/24] target-arm queue
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Nothing very exciting this time around...
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The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
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3
-- PMM
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Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
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5
The following changes since commit 37a712a0f969ca2df7f01182409a6c4825cebfb5:
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Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-10-01 12:23:19 +0100)
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4
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are available in the Git repository at:
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are available in the Git repository at:
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6
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201001
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
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8
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for you to fetch changes up to cdfaa57dcb53ba012439765a1462247dfda8595d:
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for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
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10
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hw/arm/raspi: Remove use of the 'version' value in the board code (2020-10-01 15:31:01 +0100)
11
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
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12
17
----------------------------------------------------------------
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----------------------------------------------------------------
18
target-arm queue:
14
target-arm queue:
19
* Make isar_feature_aa32_fp16_arith() handle M-profile
15
* more MVE instructions
20
* Fix SVE splice
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
21
* Fix SVE LDR/STR
17
* target/arm: Check NaN mode before silencing NaN
22
* Remove ignore_memory_transaction_failures on the raspi2
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
23
* raspi: Various cleanup/refactoring
19
* hw/arm: Add basic power management to raspi.
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
24
21
25
----------------------------------------------------------------
22
----------------------------------------------------------------
26
Peter Maydell (5):
23
Joe Komlodi (1):
27
target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
24
target/arm: Check NaN mode before silencing NaN
28
target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
29
hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
30
target/arm: Add ID register values for Cortex-M0
31
target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
32
25
33
Philippe Mathieu-Daudé (11):
26
Maxim Uvarov (1):
34
hw/arm/raspi: Define various blocks base addresses
27
hw/gpio/gpio_pwr: use shutdown function for reboot
35
hw/arm/bcm2835: Add more unimplemented peripherals
36
hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
37
hw/arm/raspi: Display the board revision in the machine description
38
hw/arm/raspi: Load the firmware on the first core
39
hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
40
hw/arm/raspi: Avoid using TypeInfo::class_data pointer
41
hw/arm/raspi: Use more specific machine names
42
hw/arm/raspi: Introduce RaspiProcessorId enum
43
hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
44
hw/arm/raspi: Remove use of the 'version' value in the board code
45
28
46
Richard Henderson (2):
29
Nolan Leake (1):
47
target/arm: Fix sve ldr/str
30
hw/arm: Add basic power management to raspi.
48
target/arm: Fix SVE splice
49
31
50
include/hw/arm/bcm2835_peripherals.h | 2 +
32
Patrick Venture (2):
51
include/hw/arm/raspi_platform.h | 51 ++++++++++--
33
docs/system/arm: Add quanta-q7l1-bmc reference
52
target/arm/cpu.h | 50 +++++++++--
34
docs/system/arm: Add quanta-gbs-bmc reference
53
hw/arm/bcm2835_peripherals.c | 2 +
54
hw/arm/raspi.c | 155 +++++++++++++++++++----------------
55
hw/intc/armv7m_nvic.c | 46 ++++++++++-
56
target/arm/cpu.c | 21 +++--
57
target/arm/cpu64.c | 12 +--
58
target/arm/cpu_tcg.c | 60 ++++++++++----
59
target/arm/helper.c | 9 +-
60
target/arm/kvm64.c | 4 +
61
target/arm/translate-sve.c | 6 +-
62
12 files changed, 286 insertions(+), 132 deletions(-)
63
35
36
Peter Maydell (18):
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
39
target/arm: Make asimd_imm_const() public
40
target/arm: Use asimd_imm_const for A64 decode
41
target/arm: Use dup_const() instead of bitfield_replicate()
42
target/arm: Implement MVE logical immediate insns
43
target/arm: Implement MVE vector shift left by immediate insns
44
target/arm: Implement MVE vector shift right by immediate insns
45
target/arm: Implement MVE VSHLL
46
target/arm: Implement MVE VSRI, VSLI
47
target/arm: Implement MVE VSHRN, VRSHRN
48
target/arm: Implement MVE saturating narrowing shifts
49
target/arm: Implement MVE VSHLC
50
target/arm: Implement MVE VADDLV
51
target/arm: Implement MVE long shifts by immediate
52
target/arm: Implement MVE long shifts by register
53
target/arm: Implement MVE shifts by immediate
54
target/arm: Implement MVE shifts by register
55
56
Philippe Mathieu-Daudé (1):
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
58
59
docs/system/arm/aspeed.rst | 1 +
60
docs/system/arm/nuvoton.rst | 5 +-
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
82
diff view generated by jsdifflib
[PULL 17/18] hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
The firmware load address depends on the SoC ("processor id") used,
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
not on the version of the board.
4
entry.
5
5
6
Suggested-by: Luc Michel <luc.michel@greensocs.com>
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210615192848.1065297-2-venture@google.com
9
Message-id: 20200924111808.77168-8-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
hw/arm/raspi.c | 3 ++-
11
docs/system/arm/aspeed.rst | 1 +
13
1 file changed, 2 insertions(+), 1 deletion(-)
12
1 file changed, 1 insertion(+)
14
13
15
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/raspi.c
16
--- a/docs/system/arm/aspeed.rst
18
+++ b/hw/arm/raspi.c
17
+++ b/docs/system/arm/aspeed.rst
19
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
18
@@ -XXX,XX +XXX,XX @@ etc.
20
* the normal Linux boot process
19
AST2400 SoC based machines :
21
*/
20
22
if (machine->firmware) {
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
23
- hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
24
+ hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836
23
25
+ ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3;
24
AST2500 SoC based machines :
26
/* load the firmware image (typically kernel.img) */
25
27
r = load_image_targphys(machine->firmware, firmware_addr,
28
ram_size - firmware_addr);
29
--
26
--
30
2.20.1
27
2.20.1
31
28
32
29
diff view generated by jsdifflib
[PULL 15/18] hw/arm/raspi: Use more specific machine names
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
Now that we can instantiate different machines based on their
3
Add line item reference to quanta-gbs-bmc machine.
4
board_rev register value, we can have various raspi2 and raspi3.
5
4
6
In commit fc78a990ec103 we corrected the machine description.
5
Signed-off-by: Patrick Venture <venture@google.com>
7
Correct the machine names too. For backward compatibility, add
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
an alias to the previous generic name.
7
Message-id: 20210615192848.1065297-3-venture@google.com
9
8
[PMM: fixed underline Sphinx warning]
10
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20200924111808.77168-6-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
hw/arm/raspi.c | 6 ++++--
11
docs/system/arm/nuvoton.rst | 5 +++--
16
1 file changed, 4 insertions(+), 2 deletions(-)
12
1 file changed, 3 insertions(+), 2 deletions(-)
17
13
18
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/raspi.c
16
--- a/docs/system/arm/nuvoton.rst
21
+++ b/hw/arm/raspi.c
17
+++ b/docs/system/arm/nuvoton.rst
22
@@ -XXX,XX +XXX,XX @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
18
@@ -XXX,XX +XXX,XX @@
23
MachineClass *mc = MACHINE_CLASS(oc);
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
24
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
20
-=====================================================
25
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
26
+ mc->alias = "raspi2";
22
+================================================================
27
rmc->board_rev = 0xa21041;
23
28
raspi_machine_class_common_init(mc, rmc->board_rev);
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
29
};
25
designed to be used as Baseboard Management Controllers (BMCs) in various
30
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
31
MachineClass *mc = MACHINE_CLASS(oc);
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
32
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
28
Hyperscale applications. The following machines are based on this chip :
33
29
34
+ mc->alias = "raspi3";
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
35
rmc->board_rev = 0xa02082;
31
- ``quanta-gsj`` Quanta GSJ server BMC
36
raspi_machine_class_common_init(mc, rmc->board_rev);
32
37
};
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
38
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
39
40
static const TypeInfo raspi_machine_types[] = {
41
{
42
- .name = MACHINE_TYPE_NAME("raspi2"),
43
+ .name = MACHINE_TYPE_NAME("raspi2b"),
44
.parent = TYPE_RASPI_MACHINE,
45
.class_init = raspi2b_machine_class_init,
46
#ifdef TARGET_AARCH64
47
}, {
48
- .name = MACHINE_TYPE_NAME("raspi3"),
49
+ .name = MACHINE_TYPE_NAME("raspi3b"),
50
.parent = TYPE_RASPI_MACHINE,
51
.class_init = raspi3b_machine_class_init,
52
#endif
53
--
34
--
54
2.20.1
35
2.20.1
55
36
56
37
diff view generated by jsdifflib
[PULL 09/18] hw/arm/bcm2835: Add more unimplemented peripherals
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
The bcm2835-v3d is used since Linux 4.7, see commit
3
This is just enough to make reboot and poweroff work. Works for
4
49ac67e0c39c ("ARM: bcm2835: Add VC4 to the device tree"),
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
and the bcm2835-txp since Linux 4.19, see commit
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
b7dd29b401f5 ("ARM: dts: bcm283x: Add Transposer block").
6
do what linux does for reset.
7
7
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
The watchdog timer functionality is not yet implemented.
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
10
Message-id: 20200921034729.432931-3-f4bug@amsat.org
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
18
---
13
include/hw/arm/bcm2835_peripherals.h | 2 ++
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
14
hw/arm/bcm2835_peripherals.c | 2 ++
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
15
2 files changed, 4 insertions(+)
21
hw/arm/bcm2835_peripherals.c | 13 ++-
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
23
hw/misc/meson.build | 1 +
24
5 files changed, 204 insertions(+), 2 deletions(-)
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
26
create mode 100644 hw/misc/bcm2835_powermgt.c
16
27
17
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
18
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/bcm2835_peripherals.h
30
--- a/include/hw/arm/bcm2835_peripherals.h
20
+++ b/include/hw/arm/bcm2835_peripherals.h
31
+++ b/include/hw/arm/bcm2835_peripherals.h
32
@@ -XXX,XX +XXX,XX @@
33
#include "hw/misc/bcm2835_mphi.h"
34
#include "hw/misc/bcm2835_thermal.h"
35
#include "hw/misc/bcm2835_cprman.h"
36
+#include "hw/misc/bcm2835_powermgt.h"
37
#include "hw/sd/sdhci.h"
38
#include "hw/sd/bcm2835_sdhost.h"
39
#include "hw/gpio/bcm2835_gpio.h"
21
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
22
23
BCM2835SystemTimerState systmr;
24
BCM2835MphiState mphi;
41
BCM2835MphiState mphi;
25
+ UnimplementedDeviceState txp;
42
UnimplementedDeviceState txp;
26
UnimplementedDeviceState armtmr;
43
UnimplementedDeviceState armtmr;
27
UnimplementedDeviceState cprman;
44
- UnimplementedDeviceState powermgt;
28
UnimplementedDeviceState a2w;
45
+ BCM2835PowerMgtState powermgt;
29
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
46
BCM2835CprmanState cprman;
30
UnimplementedDeviceState otp;
47
PL011State uart0;
31
UnimplementedDeviceState dbus;
48
BCM2835AuxState aux;
32
UnimplementedDeviceState ave0;
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
33
+ UnimplementedDeviceState v3d;
50
new file mode 100644
34
UnimplementedDeviceState bscsl;
51
index XXXXXXX..XXXXXXX
35
UnimplementedDeviceState smi;
52
--- /dev/null
36
DWC2State dwc2;
53
+++ b/include/hw/misc/bcm2835_powermgt.h
54
@@ -XXX,XX +XXX,XX @@
55
+/*
56
+ * BCM2835 Power Management emulation
57
+ *
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
60
+ *
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
62
+ * See the COPYING file in the top-level directory.
63
+ */
64
+
65
+#ifndef BCM2835_POWERMGT_H
66
+#define BCM2835_POWERMGT_H
67
+
68
+#include "hw/sysbus.h"
69
+#include "qom/object.h"
70
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
73
+
74
+struct BCM2835PowerMgtState {
75
+ SysBusDevice busdev;
76
+ MemoryRegion iomem;
77
+
78
+ uint32_t rstc;
79
+ uint32_t rsts;
80
+ uint32_t wdog;
81
+};
82
+
83
+#endif
37
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
38
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/bcm2835_peripherals.c
86
--- a/hw/arm/bcm2835_peripherals.c
40
+++ b/hw/arm/bcm2835_peripherals.c
87
+++ b/hw/arm/bcm2835_peripherals.c
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
89
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
91
OBJECT(&s->gpu_bus_mr));
92
+
93
+ /* Power Management */
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
95
+ TYPE_BCM2835_POWERMGT);
96
}
97
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
41
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
42
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
43
INTERRUPT_USB));
101
INTERRUPT_USB));
44
102
45
+ create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
103
+ /* Power Management */
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
105
+ return;
106
+ }
107
+
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
110
+
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
46
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
47
create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
48
create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
50
create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
51
create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
52
create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
118
new file mode 100644
53
+ create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000);
119
index XXXXXXX..XXXXXXX
54
create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
120
--- /dev/null
55
}
121
+++ b/hw/misc/bcm2835_powermgt.c
56
122
@@ -XXX,XX +XXX,XX @@
123
+/*
124
+ * BCM2835 Power Management emulation
125
+ *
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
128
+ *
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
130
+ * See the COPYING file in the top-level directory.
131
+ */
132
+
133
+#include "qemu/osdep.h"
134
+#include "qemu/log.h"
135
+#include "qemu/module.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
137
+#include "migration/vmstate.h"
138
+#include "sysemu/runstate.h"
139
+
140
+#define PASSWORD 0x5a000000
141
+#define PASSWORD_MASK 0xff000000
142
+
143
+#define R_RSTC 0x1c
144
+#define V_RSTC_RESET 0x20
145
+#define R_RSTS 0x20
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
147
+#define R_WDOG 0x24
148
+
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
150
+ unsigned size)
151
+{
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
153
+ uint32_t res = 0;
154
+
155
+ switch (offset) {
156
+ case R_RSTC:
157
+ res = s->rstc;
158
+ break;
159
+ case R_RSTS:
160
+ res = s->rsts;
161
+ break;
162
+ case R_WDOG:
163
+ res = s->wdog;
164
+ break;
165
+
166
+ default:
167
+ qemu_log_mask(LOG_UNIMP,
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
169
+ "\n", offset);
170
+ res = 0;
171
+ break;
172
+ }
173
+
174
+ return res;
175
+}
176
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
187
+ return;
188
+ }
189
+
190
+ value = value & ~PASSWORD_MASK;
191
+
192
+ switch (offset) {
193
+ case R_RSTC:
194
+ s->rstc = value;
195
+ if (value & V_RSTC_RESET) {
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
198
+ } else {
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
200
+ }
201
+ }
202
+ break;
203
+ case R_RSTS:
204
+ qemu_log_mask(LOG_UNIMP,
205
+ "bcm2835_powermgt_write: RSTS\n");
206
+ s->rsts = value;
207
+ break;
208
+ case R_WDOG:
209
+ qemu_log_mask(LOG_UNIMP,
210
+ "bcm2835_powermgt_write: WDOG\n");
211
+ s->wdog = value;
212
+ break;
213
+
214
+ default:
215
+ qemu_log_mask(LOG_UNIMP,
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
217
+ "\n", offset);
218
+ break;
219
+ }
220
+}
221
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
223
+ .read = bcm2835_powermgt_read,
224
+ .write = bcm2835_powermgt_write,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
226
+ .impl.min_access_size = 4,
227
+ .impl.max_access_size = 4,
228
+};
229
+
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
231
+ .name = TYPE_BCM2835_POWERMGT,
232
+ .version_id = 1,
233
+ .minimum_version_id = 1,
234
+ .fields = (VMStateField[]) {
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
238
+ VMSTATE_END_OF_LIST()
239
+ }
240
+};
241
+
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
262
+{
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
264
+
265
+ dc->reset = bcm2835_powermgt_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
267
+}
268
+
269
+static TypeInfo bcm2835_powermgt_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
273
+ .class_init = bcm2835_powermgt_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
275
+};
276
+
277
+static void bcm2835_powermgt_register_types(void)
278
+{
279
+ type_register_static(&bcm2835_powermgt_info);
280
+}
281
+
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
57
--
295
--
58
2.20.1
296
2.20.1
59
297
60
298
diff view generated by jsdifflib
[PULL 11/18] hw/arm/raspi: Display the board revision in the machine description
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Display the board revision in the machine description.
3
Add a test booting and quickly shutdown a raspi2 machine,
4
to test the power management model:
4
5
5
Before:
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
6
44
7
$ qemu-system-aarch64 -M help | fgrep raspi
8
raspi2 Raspberry Pi 2B
9
raspi3 Raspberry Pi 3B
10
11
After:
12
13
raspi2 Raspberry Pi 2B (revision 1.1)
14
raspi3 Raspberry Pi 3B (revision 1.2)
15
16
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200924111808.77168-2-f4bug@amsat.org
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
49
---
21
hw/arm/raspi.c | 4 +++-
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
22
1 file changed, 3 insertions(+), 1 deletion(-)
51
1 file changed, 43 insertions(+)
23
52
24
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
25
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/raspi.c
55
--- a/tests/acceptance/boot_linux_console.py
27
+++ b/hw/arm/raspi.c
56
+++ b/tests/acceptance/boot_linux_console.py
28
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
57
@@ -XXX,XX +XXX,XX @@
29
uint32_t board_rev = (uint32_t)(uintptr_t)data;
58
from avocado import skip
30
59
from avocado import skipUnless
31
rmc->board_rev = board_rev;
60
from avocado_qemu import Test
32
- mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
61
+from avocado_qemu import exec_command
33
+ mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
62
from avocado_qemu import exec_command_and_wait_for_pattern
34
+ board_type(board_rev),
63
from avocado_qemu import interrupt_interactive_console_until_pattern
35
+ FIELD_EX32(board_rev, REV_CODE, REVISION));
64
from avocado_qemu import wait_for_console_pattern
36
mc->init = raspi_machine_init;
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
37
mc->block_default_type = IF_SD;
66
"""
38
mc->no_parallel = 1;
67
self.do_test_arm_raspi2(0)
68
69
+ def test_arm_raspi2_initrd(self):
70
+ """
71
+ :avocado: tags=arch:arm
72
+ :avocado: tags=machine:raspi2
73
+ """
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
75
+ 'pool/main/r/raspberrypi-firmware/'
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
81
+
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
84
+ 'arm/rootfs-armv7a.cpio.gz')
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
89
+
90
+ self.vm.set_console()
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
93
+ 'panic=-1 noreboot ' +
94
+ 'dwc_otg.fiq_fsm_enable=0')
95
+ self.vm.add_args('-kernel', kernel_path,
96
+ '-dtb', dtb_path,
97
+ '-initrd', initrd_path,
98
+ '-append', kernel_command_line,
99
+ '-no-reboot')
100
+ self.vm.launch()
101
+ self.wait_for_console_pattern('Boot successful.')
102
+
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
104
+ 'BCM2835')
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
106
+ '/soc/cprman@7e101000')
107
+ exec_command(self, 'halt')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
110
+
111
def test_arm_exynos4210_initrd(self):
112
"""
113
:avocado: tags=arch:arm
39
--
114
--
40
2.20.1
115
2.20.1
41
116
42
117
diff view generated by jsdifflib
[PULL 06/18] target/arm: Fix sve ldr/str
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
The mte update missed a bit when producing clean addresses.
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
assert due to fpst->default_nan_mode being set.
4
6
5
Fixes: b2aa8879b88
7
To avoid this, we check to see what NaN mode we're running in before we call
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
floatxx_silence_nan().
7
Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org
9
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
15
---
11
target/arm/translate-sve.c | 4 ++--
16
target/arm/helper-a64.c | 12 +++++++++---
12
1 file changed, 2 insertions(+), 2 deletions(-)
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
18
2 files changed, 27 insertions(+), 9 deletions(-)
13
19
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
22
--- a/target/arm/helper-a64.c
17
+++ b/target/arm/translate-sve.c
23
+++ b/target/arm/helper-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
19
for (i = 0; i < len_align; i += 8) {
25
float16 nan = a;
20
tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ);
26
if (float16_is_signaling_nan(a, fpst)) {
21
tcg_gen_st_i64(t0, cpu_env, vofs + i);
27
float_raise(float_flag_invalid, fpst);
22
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
28
- nan = float16_silence_nan(a, fpst);
23
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
29
+ if (!fpst->default_nan_mode) {
30
+ nan = float16_silence_nan(a, fpst);
31
+ }
24
}
32
}
25
tcg_temp_free_i64(t0);
33
if (fpst->default_nan_mode) {
26
} else {
34
nan = float16_default_nan(fpst);
27
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
28
for (i = 0; i < len_align; i += 8) {
36
float32 nan = a;
29
tcg_gen_ld_i64(t0, cpu_env, vofs + i);
37
if (float32_is_signaling_nan(a, fpst)) {
30
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
38
float_raise(float_flag_invalid, fpst);
31
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
39
- nan = float32_silence_nan(a, fpst);
32
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
40
+ if (!fpst->default_nan_mode) {
41
+ nan = float32_silence_nan(a, fpst);
42
+ }
33
}
43
}
34
tcg_temp_free_i64(t0);
44
if (fpst->default_nan_mode) {
35
} else {
45
nan = float32_default_nan(fpst);
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
47
float64 nan = a;
48
if (float64_is_signaling_nan(a, fpst)) {
49
float_raise(float_flag_invalid, fpst);
50
- nan = float64_silence_nan(a, fpst);
51
+ if (!fpst->default_nan_mode) {
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
54
}
55
if (fpst->default_nan_mode) {
56
nan = float64_default_nan(fpst);
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/vfp_helper.c
60
+++ b/target/arm/vfp_helper.c
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
62
float16 nan = f16;
63
if (float16_is_signaling_nan(f16, fpst)) {
64
float_raise(float_flag_invalid, fpst);
65
- nan = float16_silence_nan(f16, fpst);
66
+ if (!fpst->default_nan_mode) {
67
+ nan = float16_silence_nan(f16, fpst);
68
+ }
69
}
70
if (fpst->default_nan_mode) {
71
nan = float16_default_nan(fpst);
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
73
float32 nan = f32;
74
if (float32_is_signaling_nan(f32, fpst)) {
75
float_raise(float_flag_invalid, fpst);
76
- nan = float32_silence_nan(f32, fpst);
77
+ if (!fpst->default_nan_mode) {
78
+ nan = float32_silence_nan(f32, fpst);
79
+ }
80
}
81
if (fpst->default_nan_mode) {
82
nan = float32_default_nan(fpst);
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
84
float64 nan = f64;
85
if (float64_is_signaling_nan(f64, fpst)) {
86
float_raise(float_flag_invalid, fpst);
87
- nan = float64_silence_nan(f64, fpst);
88
+ if (!fpst->default_nan_mode) {
89
+ nan = float64_silence_nan(f64, fpst);
90
+ }
91
}
92
if (fpst->default_nan_mode) {
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
36
--
127
--
37
2.20.1
128
2.20.1
38
129
39
130
diff view generated by jsdifflib
[PULL 10/18] hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
Commit 1c3db49d39 added the raspi3, which uses the same peripherals
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
than the raspi2 (but with different ARM cores). The raspi3 was
4
function has to be used for machine shutdown. Otherwise we cause
5
introduced without the ignore_memory_transaction_failures flag.
5
a reset with a bogus "cause" value, when we intended a shutdown.
6
Almost 2 years later, the machine is usable running U-Boot and
7
Linux.
8
In commit 00cbd5bd74 we mapped a lot of unimplemented devices,
9
commit d442d95f added thermal block and commit 0e5bbd7406 the
10
system timer.
11
As we are happy with the raspi3, let's remove this flag on the
12
raspi2.
13
6
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
15
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
17
Message-id: 20200921034729.432931-4-f4bug@amsat.org
10
[PMM: tweaked commit message]
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
12
---
20
hw/arm/raspi.c | 3 ---
13
hw/gpio/gpio_pwr.c | 2 +-
21
1 file changed, 3 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
22
15
23
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
24
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/raspi.c
18
--- a/hw/gpio/gpio_pwr.c
26
+++ b/hw/arm/raspi.c
19
+++ b/hw/gpio/gpio_pwr.c
27
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
28
mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
29
mc->default_ram_size = board_ram_size(board_rev);
22
{
30
mc->default_ram_id = "ram";
23
if (level) {
31
- if (board_version(board_rev) == 2) {
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
32
- mc->ignore_memory_transaction_failures = true;
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
33
- }
26
}
34
};
27
}
35
28
36
static const TypeInfo raspi_machine_types[] = {
37
--
29
--
38
2.20.1
30
2.20.1
39
31
40
32
diff view generated by jsdifflib
[PULL 12/18] hw/arm/raspi: Load the firmware on the first core
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
In do_ldst(), the calculation of the offset needs to be based on the
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
2
5
3
The 'first_cpu' is more a QEMU accelerator-related concept
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
than a variable the machine requires to use.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Since the machine is aware of its CPUs, directly use the
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
6
first one to load the firmware.
9
---
10
target/arm/translate-mve.c | 17 +++++++++--------
11
1 file changed, 9 insertions(+), 8 deletions(-)
7
12
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200924111808.77168-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/raspi.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
15
--- a/target/arm/translate-mve.c
19
+++ b/hw/arm/raspi.c
16
+++ b/target/arm/translate-mve.c
20
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
21
18
}
22
static void setup_boot(MachineState *machine, int version, size_t ram_size)
19
}
20
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
23
+ unsigned msize)
23
{
24
{
24
+ RaspiMachineState *s = RASPI_MACHINE(machine);
25
TCGv_i32 addr;
25
static struct arm_boot_info binfo;
26
uint32_t offset;
26
int r;
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
27
28
return true;
28
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
29
binfo.firmware_loaded = true;
30
}
29
}
31
30
32
- arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
31
- offset = a->imm << a->size;
33
+ arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
32
+ offset = a->imm << msize;
33
if (!a->a) {
34
offset = -offset;
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
38
{ NULL, NULL }
39
};
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
34
}
42
}
35
43
36
static void raspi_machine_init(MachineState *machine)
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
55
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
37
--
65
--
38
2.20.1
66
2.20.1
39
67
40
68
diff view generated by jsdifflib
[PULL 08/18] hw/arm/raspi: Define various blocks base addresses
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
insns had some bugs:
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
2
9
3
The Raspberry firmware is closed-source. While running it, it
10
In particular, fixing the second of these allows us to recast
4
accesses various I/O registers. Logging these accesses as UNIMP
11
the implementation to avoid 128-bit arithmetic entirely.
5
(unimplemented) help to understand what the firmware is doing
6
(ideally we want it able to boot a Linux kernel).
7
12
8
Document various blocks we might use later.
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
9
15
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
13
Message-id: 20200921034729.432931-2-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
15
---
20
---
16
include/hw/arm/raspi_platform.h | 51 +++++++++++++++++++++++++++------
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
17
1 file changed, 43 insertions(+), 8 deletions(-)
22
1 file changed, 21 insertions(+), 17 deletions(-)
18
23
19
diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
20
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/raspi_platform.h
26
--- a/target/arm/mve_helper.c
22
+++ b/include/hw/arm/raspi_platform.h
27
+++ b/target/arm/mve_helper.c
23
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
24
* You should have received a copy of the GNU General Public License
25
* along with this program; if not, write to the Free Software
26
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27
+ *
28
+ * Various undocumented addresses and names come from Herman Hermitage's VC4
29
+ * documentation:
30
+ * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
31
*/
29
*/
32
30
33
#ifndef HW_ARM_RASPI_PLATFORM_H
31
#include "qemu/osdep.h"
34
#define HW_ARM_RASPI_PLATFORM_H
32
-#include "qemu/int128.h"
35
33
#include "cpu.h"
36
#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
34
#include "internals.h"
37
-#define IC0_OFFSET 0x2000
35
#include "vec_internal.h"
38
+#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
39
+#define INTE_OFFSET 0x2000 /* VC Interrupt controller */
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
40
#define ST_OFFSET 0x3000 /* System Timer */
38
41
+#define TXP_OFFSET 0x4000 /* Transposer */
39
/*
42
+#define JPEG_OFFSET 0x5000
40
- * Rounding multiply add long dual accumulate high: we must keep
43
#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
41
- * a 72-bit internal accumulator value and return the top 64 bits.
44
#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
45
-#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
43
+ * this is implemented with a 72-bit internal accumulator value of which
46
+#define ARBA_OFFSET 0x9000
44
+ * the top 64 bits are returned. We optimize this to avoid having to
47
+#define BRDG_OFFSET 0xa000
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
48
+#define ARM_OFFSET 0xB000 /* ARM control block */
46
+ * is squashed back into 64-bits after each beat.
49
#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
47
*/
50
#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
51
-#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
52
+#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
53
#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
51
void *vm, uint64_t a) \
54
* Doorbells & Mailboxes */
52
{ \
55
#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
53
uint16_t mask = mve_element_mask(env); \
56
@@ -XXX,XX +XXX,XX @@
54
unsigned e; \
57
#define AVS_OFFSET 0x103000 /* Audio Video Standard */
55
TYPE *n = vn, *m = vm; \
58
#define RNG_OFFSET 0x104000
56
- Int128 acc = int128_lshift(TO128(a), 8); \
59
#define GPIO_OFFSET 0x200000
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
60
-#define UART0_OFFSET 0x201000
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
61
-#define MMCI0_OFFSET 0x202000
59
if (mask & 1) { \
62
-#define I2S_OFFSET 0x203000
60
+ LTYPE mul; \
63
-#define SPI0_OFFSET 0x204000
61
if (e & 1) { \
64
+#define UART0_OFFSET 0x201000 /* PL011 */
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
65
+#define MMCI0_OFFSET 0x202000 /* Legacy MMC */
63
- m[H##ESIZE(e)])); \
66
+#define I2S_OFFSET 0x203000 /* PCM */
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
67
+#define SPI0_OFFSET 0x204000 /* SPI master */
65
+ if (SUB) { \
68
#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
66
+ mul = -mul; \
69
+#define PIXV0_OFFSET 0x206000
67
+ } \
70
+#define PIXV1_OFFSET 0x207000
68
} else { \
71
+#define DPI_OFFSET 0x208000
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
72
+#define DSI0_OFFSET 0x209000 /* Display Serial Interface */
70
- m[H##ESIZE(e)])); \
73
+#define PWM_OFFSET 0x20c000
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
74
+#define PERM_OFFSET 0x20d000
72
} \
75
+#define TEC_OFFSET 0x20e000
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
76
#define OTP_OFFSET 0x20f000
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
77
+#define SLIM_OFFSET 0x210000 /* SLIMbus */
75
+ a += mul; \
78
+#define CPG_OFFSET 0x211000
76
} \
79
#define THERMAL_OFFSET 0x212000
77
} \
80
-#define BSC_SL_OFFSET 0x214000 /* SPI slave */
78
mve_advance_vpt(env); \
81
+#define AVSP_OFFSET 0x213000
79
- return int128_getlo(int128_rshift(acc, 8)); \
82
+#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */
80
+ return a; \
83
#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */
81
}
84
#define EMMC1_OFFSET 0x300000
82
85
+#define EMMC2_OFFSET 0x340000
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
86
+#define HVS_OFFSET 0x400000
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
87
#define SMI_OFFSET 0x600000
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
88
+#define DSI1_OFFSET 0x700000
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
89
+#define UCAM_OFFSET 0x800000
87
90
+#define CMI_OFFSET 0x802000
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
91
#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
92
#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */
90
93
+#define VECA_OFFSET 0x806000
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
94
+#define PIXV2_OFFSET 0x807000
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
95
+#define HDMI_OFFSET 0x808000
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
96
+#define HDCP_OFFSET 0x809000
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
97
+#define ARBR0_OFFSET 0x80a000
95
98
#define DBUS_OFFSET 0x900000
96
/* Vector add across vector */
99
#define AVE0_OFFSET 0x910000
97
#define DO_VADDV(OP, ESIZE, TYPE) \
100
#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */
101
+#define V3D_OFFSET 0xc00000
102
#define SDRAMC_OFFSET 0xe00000
103
+#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */
104
+#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */
105
+#define ARBR1_OFFSET 0xe04000
106
#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
107
+#define DCRC_OFFSET 0xe07000
108
+#define AXIP_OFFSET 0xe08000
109
110
/* GPU interrupts */
111
#define INTERRUPT_TIMER0 0
112
--
98
--
113
2.20.1
99
2.20.1
114
100
115
101
diff view generated by jsdifflib
[PULL 18/18] hw/arm/raspi: Remove use of the 'version' value in the board code
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The function asimd_imm_const() in translate-neon.c is an
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
2
5
3
We expected the 'version' ID to match the board processor ID,
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
but this is not always true (for example boards with revision
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
id 0xa02042/0xa22042 are Raspberry Pi 2 with a BCM2837 SoC).
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
6
This was not important because we were not modelling them, but
9
---
7
since the recent refactor now allow to model these boards, it
10
target/arm/translate.h | 16 ++++++++++
8
is safer to check the processor id directly. Remove the version
11
target/arm/translate-neon.c | 63 -------------------------------------
9
check.
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
10
14
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
12
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200924111808.77168-9-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/raspi.c | 29 +++++++++++++----------------
18
1 file changed, 13 insertions(+), 16 deletions(-)
19
20
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/raspi.c
17
--- a/target/arm/translate.h
23
+++ b/hw/arm/raspi.c
18
+++ b/target/arm/translate.h
24
@@ -XXX,XX +XXX,XX @@ static RaspiProcessorId board_processor_id(uint32_t board_rev)
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
25
return proc_id;
20
return opc | s->be_data;
26
}
21
}
27
22
28
-static int board_version(uint32_t board_rev)
23
+/**
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
25
+ *
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ *
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
29
-{
49
-{
30
- return board_processor_id(board_rev) + 1;
50
- /*
51
- * Expand the encoded constant.
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
31
-}
109
-}
32
-
110
-
33
static const char *board_soc_type(uint32_t board_rev)
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
112
GVecGen2iFn *fn)
34
{
113
{
35
return soc_property[board_processor_id(board_rev)].type;
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
36
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
115
index XXXXXXX..XXXXXXX 100644
37
cpu_set_pc(cs, info->smp_loader_start);
116
--- a/target/arm/translate.c
117
+++ b/target/arm/translate.c
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
119
a64_translate_init();
38
}
120
}
39
121
40
-static void setup_boot(MachineState *machine, int version, size_t ram_size)
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
41
+static void setup_boot(MachineState *machine, RaspiProcessorId processor_id,
123
+{
42
+ size_t ram_size)
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
125
+ switch (cmode) {
126
+ case 0: case 1:
127
+ /* no-op */
128
+ break;
129
+ case 2: case 3:
130
+ imm <<= 8;
131
+ break;
132
+ case 4: case 5:
133
+ imm <<= 16;
134
+ break;
135
+ case 6: case 7:
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
159
+ for (n = 0; n < 8; n++) {
160
+ if (imm & (1 << n)) {
161
+ imm64 |= (0xffULL << (n * 8));
162
+ }
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
43
{
181
{
44
RaspiMachineState *s = RASPI_MACHINE(machine);
45
int r;
46
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
47
s->binfo.ram_size = ram_size;
48
s->binfo.nb_cpus = machine->smp.cpus;
49
50
- if (version <= 2) {
51
- /* The rpi1 and 2 require some custom setup code to run in Secure
52
- * mode before booting a kernel (to set up the SMC vectors so
53
- * that we get a no-op SMC; this is used by Linux to call the
54
+ if (processor_id <= PROCESSOR_ID_BCM2836) {
55
+ /*
56
+ * The BCM2835 and BCM2836 require some custom setup code to run
57
+ * in Secure mode before booting a kernel (to set up the SMC vectors
58
+ * so that we get a no-op SMC; this is used by Linux to call the
59
* firmware for some cache maintenance operations.
60
- * The rpi3 doesn't need this.
61
+ * The BCM2837 doesn't need this.
62
*/
63
s->binfo.board_setup_addr = BOARDSETUP_ADDR;
64
s->binfo.write_board_setup = write_board_setup;
65
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
66
s->binfo.secure_boot = true;
67
}
68
69
- /* Pi2 and Pi3 requires SMP setup */
70
- if (version >= 2) {
71
+ /* BCM2836 and BCM2837 requires SMP setup */
72
+ if (processor_id >= PROCESSOR_ID_BCM2836) {
73
s->binfo.smp_loader_start = SMPBOOT_ADDR;
74
- if (version == 2) {
75
+ if (processor_id == PROCESSOR_ID_BCM2836) {
76
s->binfo.write_secondary_boot = write_smpboot;
77
} else {
78
s->binfo.write_secondary_boot = write_smpboot64;
79
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
80
RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
81
RaspiMachineState *s = RASPI_MACHINE(machine);
82
uint32_t board_rev = mc->board_rev;
83
- int version = board_version(board_rev);
84
uint64_t ram_size = board_ram_size(board_rev);
85
uint32_t vcram_size;
86
DriveInfo *di;
87
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
88
89
vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
90
&error_abort);
91
- setup_boot(machine, version, machine->ram_size - vcram_size);
92
+ setup_boot(machine, board_processor_id(mc->board_rev),
93
+ machine->ram_size - vcram_size);
94
}
95
96
static void raspi_machine_class_common_init(MachineClass *mc,
97
--
182
--
98
2.20.1
183
2.20.1
99
184
100
185
diff view generated by jsdifflib
[PULL 13/18] hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
2
5
3
The arm_boot_info structure belong to the machine,
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
move it to RaspiMachineState.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
9
---
10
target/arm/translate.h | 3 +-
11
target/arm/translate-a64.c | 86 ++++----------------------------------
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
5
14
6
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200924111808.77168-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/raspi.c | 30 +++++++++++++++---------------
12
1 file changed, 15 insertions(+), 15 deletions(-)
13
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
17
--- a/target/arm/translate.h
17
+++ b/hw/arm/raspi.c
18
+++ b/target/arm/translate.h
18
@@ -XXX,XX +XXX,XX @@ struct RaspiMachineState {
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
19
MachineState parent_obj;
20
* VMVN and VBIC (when cmode < 14 && op == 1).
20
/*< public >*/
21
*
21
BCM283XState soc;
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
22
+ struct arm_boot_info binfo;
23
- * callers must catch this.
23
};
24
+ * callers must catch this; we return the 64-bit constant value defined
24
typedef struct RaspiMachineState RaspiMachineState;
25
+ * for AArch64.
25
26
*
26
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
27
static void setup_boot(MachineState *machine, int version, size_t ram_size)
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/translate-a64.c
32
+++ b/target/arm/translate-a64.c
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
28
{
34
{
29
RaspiMachineState *s = RASPI_MACHINE(machine);
35
int rd = extract32(insn, 0, 5);
30
- static struct arm_boot_info binfo;
36
int cmode = extract32(insn, 12, 4);
31
int r;
37
- int cmode_3_1 = extract32(cmode, 1, 3);
32
38
- int cmode_0 = extract32(cmode, 0, 1);
33
- binfo.board_id = MACH_TYPE_BCM2708;
39
int o2 = extract32(insn, 11, 1);
34
- binfo.ram_size = ram_size;
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
35
- binfo.nb_cpus = machine->smp.cpus;
41
bool is_neg = extract32(insn, 29, 1);
36
+ s->binfo.board_id = MACH_TYPE_BCM2708;
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
37
+ s->binfo.ram_size = ram_size;
43
return;
38
+ s->binfo.nb_cpus = machine->smp.cpus;
39
40
if (version <= 2) {
41
/* The rpi1 and 2 require some custom setup code to run in Secure
42
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
43
* firmware for some cache maintenance operations.
44
* The rpi3 doesn't need this.
45
*/
46
- binfo.board_setup_addr = BOARDSETUP_ADDR;
47
- binfo.write_board_setup = write_board_setup;
48
- binfo.secure_board_setup = true;
49
- binfo.secure_boot = true;
50
+ s->binfo.board_setup_addr = BOARDSETUP_ADDR;
51
+ s->binfo.write_board_setup = write_board_setup;
52
+ s->binfo.secure_board_setup = true;
53
+ s->binfo.secure_boot = true;
54
}
44
}
55
45
56
/* Pi2 and Pi3 requires SMP setup */
46
- /* See AdvSIMDExpandImm() in ARM ARM */
57
if (version >= 2) {
47
- switch (cmode_3_1) {
58
- binfo.smp_loader_start = SMPBOOT_ADDR;
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
59
+ s->binfo.smp_loader_start = SMPBOOT_ADDR;
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
60
if (version == 2) {
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
61
- binfo.write_secondary_boot = write_smpboot;
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
62
+ s->binfo.write_secondary_boot = write_smpboot;
52
- {
63
} else {
53
- int shift = cmode_3_1 * 8;
64
- binfo.write_secondary_boot = write_smpboot64;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
65
+ s->binfo.write_secondary_boot = write_smpboot64;
55
- break;
66
}
56
- }
67
- binfo.secondary_cpu_reset_hook = reset_secondary;
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
68
+ s->binfo.secondary_cpu_reset_hook = reset_secondary;
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
120
-
121
- if (cmode_3_1 != 7 && is_neg) {
122
- imm = ~imm;
123
+ if (cmode == 15 && o2 && !is_neg) {
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
69
}
130
}
70
131
71
/* If the user specified a "firmware" image (e.g. UEFI), we bypass
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
72
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
73
exit(1);
134
index XXXXXXX..XXXXXXX 100644
74
}
135
--- a/target/arm/translate.c
75
136
+++ b/target/arm/translate.c
76
- binfo.entry = firmware_addr;
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
77
- binfo.firmware_loaded = true;
138
case 14:
78
+ s->binfo.entry = firmware_addr;
139
if (op) {
79
+ s->binfo.firmware_loaded = true;
140
/*
80
}
141
- * This is the only case where the top and bottom 32 bits
81
142
- * of the encoded constant differ.
82
- arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
143
+ * This and cmode == 15 op == 1 are the only cases where
83
+ arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo);
144
+ * the top and bottom 32 bits of the encoded constant differ.
84
}
145
*/
85
146
uint64_t imm64 = 0;
86
static void raspi_machine_init(MachineState *machine)
147
int n;
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
150
break;
151
case 15:
152
+ if (op) {
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
155
+ if (imm & 0x80) {
156
+ imm64 |= 0x8000000000000000ULL;
157
+ }
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
87
--
168
--
88
2.20.1
169
2.20.1
89
170
90
171
diff view generated by jsdifflib
New patch
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
Use dup_const() instead of bitfield_replicate() in
2
disas_simd_mod_imm().
1
3
4
(We can't replace the other use of bitfield_replicate() in this file,
5
in logic_imm_decode_wmask(), because that location needs to handle 2
6
and 4 bit elements, which dup_const() cannot.)
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
11
---
12
target/arm/translate-a64.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
20
/* FMOV (vector, immediate) - half-precision */
21
imm = vfp_expand_imm(MO_16, abcdefgh);
22
/* now duplicate across the lanes */
23
- imm = bitfield_replicate(imm, 16);
24
+ imm = dup_const(MO_16, imm);
25
} else {
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
27
}
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
New patch
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 4 +++
11
target/arm/mve.decode | 17 +++++++++++++
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
15
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/mve.decode
31
+++ b/target/arm/mve.decode
32
@@ -XXX,XX +XXX,XX @@
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
34
%size_28 28:1 !function=plus_1
35
36
+# 1imm format immediate
37
+%imm_28_16_0 28:1 16:3 0:4
38
+
39
&vldr_vstr rn qd imm p a w size l u
40
&1op qd qm size
41
&2op qd qm qn size
42
&2scalar qd qn rm size
43
+&1imm qd imm cmode op
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
74
+++ b/target/arm/mve_helper.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
79
+/*
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
81
+ * All these insns work at 64-bit widths.
82
+ */
83
+#define DO_1OP_IMM(OP, FN) \
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
85
+ { \
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
93
+ }
94
+
95
+#define DO_MOVI(N, I) (I)
96
+#define DO_ANDI(N, I) ((N) & (I))
97
+#define DO_ORRI(N, I) ((N) | (I))
98
+
99
+DO_1OP_IMM(vmovi, DO_MOVI)
100
+DO_1OP_IMM(vandi, DO_ANDI)
101
+DO_1OP_IMM(vorri, DO_ORRI)
102
+
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
122
+
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
124
+{
125
+ TCGv_ptr qd;
126
+ uint64_t imm;
127
+
128
+ if (!dc_isar_feature(aa32_mve, s) ||
129
+ !mve_check_qreg_bank(s, a->qd) ||
130
+ !fn) {
131
+ return false;
132
+ }
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ return true;
135
+ }
136
+
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
138
+
139
+ qd = mve_qreg_ptr(a->qd);
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
141
+ tcg_temp_free_ptr(qd);
142
+ mve_update_eci(s);
143
+ return true;
144
+}
145
+
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
147
+{
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
150
+
151
+ if ((a->cmode & 1) && a->cmode < 12) {
152
+ if (a->op) {
153
+ /*
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
155
+ * so the VBIC becomes a logical AND operation.
156
+ */
157
+ fn = gen_helper_mve_vandi;
158
+ } else {
159
+ fn = gen_helper_mve_vorri;
160
+ }
161
+ } else {
162
+ /* There is one unallocated cmode/op combination in this space */
163
+ if (a->cmode == 15 && a->op == 1) {
164
+ return false;
165
+ }
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
167
+ fn = gen_helper_mve_vmovi;
168
+ }
169
+ return do_1imm(s, a, fn);
170
+}
171
--
172
2.20.1
173
174
diff view generated by jsdifflib
New patch
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
and VQSHLU.
3
4
The size-and-immediate encoding here is the same as Neon, and we
5
handle it the same way neon-dp.decode does.
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
10
---
11
target/arm/helper-mve.h | 16 +++++++++++
12
target/arm/mve.decode | 23 +++++++++++++++
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
15
4 files changed, 147 insertions(+)
16
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper-mve.h
20
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
+
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
173
}
174
+
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
176
+ bool negateshift)
177
+{
178
+ TCGv_ptr qd, qm;
179
+ int shift = a->shift;
180
+
181
+ if (!dc_isar_feature(aa32_mve, s) ||
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
183
+ !fn) {
184
+ return false;
185
+ }
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
187
+ return true;
188
+ }
189
+
190
+ /*
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
194
+ */
195
+ if (negateshift) {
196
+ shift = -shift;
197
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
206
+}
207
+
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
210
+ { \
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
212
+ gen_helper_mve_##FN##b, \
213
+ gen_helper_mve_##FN##h, \
214
+ gen_helper_mve_##FN##w, \
215
+ NULL, \
216
+ }; \
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
218
+ }
219
+
220
+DO_2SHIFT(VSHLI, vshli_u, false)
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
224
--
225
2.20.1
226
227
diff view generated by jsdifflib
[PULL 05/18] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
The M-profile definition of the MVFR1 ID register differs slightly
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
from the A-profile one, and in particular the check for "does the CPU
2
VRSHRI. As with Neon, we implement these by using helper functions
3
support fp16 arithmetic" is not the same.
3
which perform left shifts but allow negative shift counts to indicate
4
4
right shifts.
5
We don't currently implement any M-profile CPUs with fp16 arithmetic,
6
so this is not yet a visible bug, but correcting the logic now
7
disarms this beartrap for when we eventually do.
8
5
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
12
---
9
---
13
target/arm/cpu.h | 31 ++++++++++++++++++++++++++-----
10
target/arm/helper-mve.h | 12 ++++++++++++
14
1 file changed, 26 insertions(+), 5 deletions(-)
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
15
17
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
20
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/cpu.h
21
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
21
FIELD(ID_MMFR4, CCIDX, 24, 4)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
22
FIELD(ID_MMFR4, EVT, 28, 4)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
23
25
24
+FIELD(ID_PFR1, PROGMOD, 0, 4)
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+FIELD(ID_PFR1, SECURITY, 4, 4)
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+FIELD(ID_PFR1, MPROGMOD, 8, 4)
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
28
+FIELD(ID_PFR1, GENTIMER, 16, 4)
29
+FIELD(ID_PFR1, SEC_FRAC, 20, 4)
30
+FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
31
+FIELD(ID_PFR1, GIC, 28, 4)
32
+
29
+
33
FIELD(ID_AA64ISAR0, AES, 4, 4)
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
@@ -XXX,XX +XXX,XX @@ FIELD(MVFR0, FPROUND, 28, 4)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
FIELD(MVFR1, FPFTZ, 0, 4)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
FIELD(MVFR1, FPDNAN, 4, 4)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
-FIELD(MVFR1, SIMDLS, 8, 4)
37
+
41
-FIELD(MVFR1, SIMDINT, 12, 4)
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
-FIELD(MVFR1, SIMDSP, 16, 4)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
-FIELD(MVFR1, SIMDHP, 20, 4)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
41
+
45
+FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
49
+FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
46
index XXXXXXX..XXXXXXX 100644
50
FIELD(MVFR1, FPHP, 24, 4)
47
--- a/target/arm/translate.h
51
FIELD(MVFR1, SIMDFMAC, 28, 4)
48
+++ b/target/arm/translate.h
52
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
53
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
50
return x * 2 + 1;
54
return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
55
}
51
}
56
52
57
+static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
53
+static inline int rsub_64(DisasContext *s, int x)
58
+{
54
+{
59
+ return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
55
+ return 64 - x;
60
+}
56
+}
61
+
57
+
62
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
58
+static inline int rsub_32(DisasContext *s, int x)
59
+{
60
+ return 32 - x;
61
+}
62
+
63
+static inline int rsub_16(DisasContext *s, int x)
64
+{
65
+ return 16 - x;
66
+}
67
+
68
+static inline int rsub_8(DisasContext *s, int x)
69
+{
70
+ return 8 - x;
71
+}
72
+
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
63
{
74
{
64
- return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
75
return (dc->features & (1ULL << feature)) != 0;
65
+ /* Sadly this is encoded differently for A-profile and M-profile */
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
66
+ if (isar_feature_aa32_mprofile(id)) {
77
index XXXXXXX..XXXXXXX 100644
67
+ return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
78
--- a/target/arm/mve.decode
68
+ } else {
79
+++ b/target/arm/mve.decode
69
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
80
@@ -XXX,XX +XXX,XX @@
70
+ }
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
83
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
88
+
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
90
+ size=0 shift=%rshift_i3
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
92
+ size=1 shift=%rshift_i4
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
95
+
96
# Vector loads and stores
97
98
# Widening loads and narrowing stores:
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
71
}
163
}
72
164
73
static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
165
-static inline int rsub_64(DisasContext *s, int x)
166
-{
167
- return 64 - x;
168
-}
169
-
170
-static inline int rsub_32(DisasContext *s, int x)
171
-{
172
- return 32 - x;
173
-}
174
-static inline int rsub_16(DisasContext *s, int x)
175
-{
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
181
-}
182
-
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
184
{
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
74
--
186
--
75
2.20.1
187
2.20.1
76
188
77
189
diff view generated by jsdifflib
New patch
[PULL 15/24] target/arm: Implement MVE VSHLL
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
and the T2 encoding is a special case where the shift count is always
4
equal to the element size.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 9 +++++++
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
15
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
40
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
43
+# VSHLL encoding T2 where shift == esize
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
45
+ qd=%qd qm=%qm size=0 shift=8
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
47
+ qd=%qd qm=%qm size=1 shift=16
48
+
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
50
%rshift_i5 16:5 !function=rsub_32
51
%rshift_i4 16:4 !function=rsub_16
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
55
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
59
+# overlaps what would be size=0b11 VMULH/VRMULH
60
+{
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
63
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
67
+}
68
+
69
+{
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
72
+
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
74
+}
75
+
76
+{
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
79
+
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
81
+}
82
+
83
+{
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
86
+
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
88
+}
89
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
96
+
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
100
+
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
103
+
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
106
+
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/arm/mve_helper.c
112
+++ b/target/arm/mve_helper.c
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
117
+
118
+/*
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
121
+ * the input, and LESIZE, LTYPE for the output.
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
123
+ * because the long shift is strictly left-only.
124
+ */
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
139
+ }
140
+
141
+#define DO_VSHLL_ALL(OP, TOP) \
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
146
+
147
+DO_VSHLL_ALL(vshllb, false)
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
+
158
+#define DO_VSHLL(INSN, FN) \
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
160
+ { \
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
167
+
168
+DO_VSHLL(VSHLL_BS, vshllbs)
169
+DO_VSHLL(VSHLL_BU, vshllbu)
170
+DO_VSHLL(VSHLL_TS, vshllts)
171
+DO_VSHLL(VSHLL_TU, vshlltu)
172
--
173
2.20.1
174
175
diff view generated by jsdifflib
New patch
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
Implement the MVE VSRI and VSLI insns, which perform a
2
shift-and-insert operation.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
7
---
8
target/arm/helper-mve.h | 8 ++++++++
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
13
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper-mve.h
17
+++ b/target/arm/helper-mve.h
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/mve.decode
33
+++ b/target/arm/mve.decode
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
35
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
38
+
39
+# Shift-and-insert
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
43
+
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
114
--
115
2.20.1
116
117
diff view generated by jsdifflib
New patch
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
1
2
3
do_urshr() is borrowed from sve_helper.c.
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 10 ++++++++++
10
target/arm/mve.decode | 11 +++++++++++
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
14
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-mve.h
18
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
41
+
42
+# Narrowing shifts (which only support b and h sizes)
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
47
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
61
+/*
62
+ * Narrowing right shifts, taking a double sized input, shifting it
63
+ * and putting the result in either the top or bottom half of the output.
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
65
+ */
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
68
+ void *vm, uint32_t shift) \
69
+ { \
70
+ LTYPE *m = vm; \
71
+ TYPE *d = vd; \
72
+ uint16_t mask = mve_element_mask(env); \
73
+ unsigned le; \
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
79
+ }
80
+
81
+#define DO_VSHRN_ALL(OP, FN) \
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
86
+
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
88
+{
89
+ if (likely(sh < 64)) {
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
91
+ } else if (sh == 64) {
92
+ return x >> 63;
93
+ } else {
94
+ return 0;
95
+ }
96
+}
97
+
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
105
DO_VSHLL(VSHLL_BU, vshllbu)
106
DO_VSHLL(VSHLL_TS, vshllts)
107
DO_VSHLL(VSHLL_TU, vshlltu)
108
+
109
+#define DO_2SHIFT_N(INSN, FN) \
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
111
+ { \
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
113
+ gen_helper_mve_##FN##b, \
114
+ gen_helper_mve_##FN##h, \
115
+ }; \
116
+ return do_2shift(s, a, fns[a->size], false); \
117
+ }
118
+
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
123
--
124
2.20.1
125
126
diff view generated by jsdifflib
[PULL 14/18] hw/arm/raspi: Avoid using TypeInfo::class_data pointer
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE saturating shift-right-and-narrow insns
2
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
Using class_data pointer to create a MachineClass is not
3
4
the recommended way anymore. The correct way is to open-code
4
do_srshr() is borrowed from sve_helper.c.
5
the MachineClass::fields in the class_init() method.
5
6
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
We can not use TYPE_RASPI_MACHINE::class_base_init() because
8
it is called *before* each machine class_init(), therefore the
9
board_rev field is not populated. We have to manually call
10
raspi_machine_class_common_init() for each machine.
11
12
This partly reverts commit a03bde3674e.
13
14
Suggested-by: Igor Mammedov <imammedo@redhat.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200924111808.77168-5-f4bug@amsat.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
9
---
21
hw/arm/raspi.c | 34 ++++++++++++++++++++++++----------
10
target/arm/helper-mve.h | 30 +++++++++++
22
1 file changed, 24 insertions(+), 10 deletions(-)
11
target/arm/mve.decode | 28 ++++++++++
23
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
24
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
13
target/arm/translate-mve.c | 12 +++++
25
index XXXXXXX..XXXXXXX 100644
14
4 files changed, 174 insertions(+)
26
--- a/hw/arm/raspi.c
15
27
+++ b/hw/arm/raspi.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
28
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
17
index XXXXXXX..XXXXXXX 100644
29
setup_boot(machine, version, machine->ram_size - vcram_size);
18
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
57
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
62
+
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
95
}
30
}
96
}
31
97
32
-static void raspi_machine_class_init(ObjectClass *oc, void *data)
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
33
+static void raspi_machine_class_common_init(MachineClass *mc,
34
+ uint32_t board_rev)
35
{
36
- MachineClass *mc = MACHINE_CLASS(oc);
37
- RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
38
- uint32_t board_rev = (uint32_t)(uintptr_t)data;
39
-
40
- rmc->board_rev = board_rev;
41
mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
42
board_type(board_rev),
43
FIELD_EX32(board_rev, REV_CODE, REVISION));
44
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
45
mc->default_ram_id = "ram";
46
};
47
48
+static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
49
+{
99
+{
50
+ MachineClass *mc = MACHINE_CLASS(oc);
100
+ if (likely(sh < 64)) {
51
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
52
+
102
+ } else {
53
+ rmc->board_rev = 0xa21041;
103
+ /* Rounding the sign bit always produces 0. */
54
+ raspi_machine_class_common_init(mc, rmc->board_rev);
104
+ return 0;
55
+};
105
+ }
56
+
106
+}
57
+#ifdef TARGET_AARCH64
107
+
58
+static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
108
DO_VSHRN_ALL(vshrn, DO_SHR)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
59
+{
113
+{
60
+ MachineClass *mc = MACHINE_CLASS(oc);
114
+ if (val > max) {
61
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
115
+ *satp = true;
62
+
116
+ return max;
63
+ rmc->board_rev = 0xa02082;
117
+ } else if (val < min) {
64
+ raspi_machine_class_common_init(mc, rmc->board_rev);
118
+ *satp = true;
65
+};
119
+ return min;
66
+#endif /* TARGET_AARCH64 */
120
+ } else {
67
+
121
+ return val;
68
static const TypeInfo raspi_machine_types[] = {
122
+ }
69
{
123
+}
70
.name = MACHINE_TYPE_NAME("raspi2"),
124
+
71
.parent = TYPE_RASPI_MACHINE,
125
+/* Saturating narrowing right shifts */
72
- .class_init = raspi_machine_class_init,
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
73
- .class_data = (void *)0xa21041,
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
74
+ .class_init = raspi2b_machine_class_init,
128
+ void *vm, uint32_t shift) \
75
#ifdef TARGET_AARCH64
129
+ { \
76
}, {
130
+ LTYPE *m = vm; \
77
.name = MACHINE_TYPE_NAME("raspi3"),
131
+ TYPE *d = vd; \
78
.parent = TYPE_RASPI_MACHINE,
132
+ uint16_t mask = mve_element_mask(env); \
79
- .class_init = raspi_machine_class_init,
133
+ bool qc = false; \
80
- .class_data = (void *)0xa02082,
134
+ unsigned le; \
81
+ .class_init = raspi3b_machine_class_init,
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
82
#endif
136
+ bool sat = false; \
83
}, {
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
84
.name = TYPE_RASPI_MACHINE,
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
140
+ } \
141
+ if (qc) { \
142
+ env->vfp.qc[0] = qc; \
143
+ } \
144
+ mve_advance_vpt(env); \
145
+ }
146
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
150
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
154
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
85
--
224
--
86
2.20.1
225
2.20.1
87
226
88
227
diff view generated by jsdifflib
[PULL 04/18] target/arm: Add ID register values for Cortex-M0
[PULL 19/24] target/arm: Implement MVE VSHLC
1
Give the Cortex-M0 ID register values corresponding to its
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
implemented behaviour. These will not be guest-visible but will be
2
entire vector with carry in bits provided from a general purpose
3
used to govern the behaviour of QEMU's emulation. We use the same
3
register and carry out bits written back to that register.
4
values that the Cortex-M3 does.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
9
---
8
---
10
target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++
9
target/arm/helper-mve.h | 2 ++
11
1 file changed, 24 insertions(+)
10
target/arm/mve.decode | 2 ++
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
12
14
13
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu_tcg.c
17
--- a/target/arm/helper-mve.h
16
+++ b/target/arm/cpu_tcg.c
18
+++ b/target/arm/helper-mve.h
17
@@ -XXX,XX +XXX,XX @@ static void cortex_m0_initfn(Object *obj)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
set_feature(&cpu->env, ARM_FEATURE_M);
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
cpu->midr = 0x410cc200;
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/mve.decode
28
+++ b/target/arm/mve.decode
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
33
+
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
21
+
51
+
22
+ /*
52
+ /*
23
+ * These ID register values are not guest visible, because
53
+ * For each 32-bit element, we shift it left, bringing in the
24
+ * we do not implement the Main Extension. They must be set
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
25
+ * to values corresponding to the Cortex-M0's implemented
55
+ * the top become the new rdm, if the predicate mask permits.
26
+ * features, because QEMU generally controls its emulation
56
+ * The final rdm value is returned to update the register.
27
+ * by looking at ID register fields. We use the same values as
57
+ * shift == 0 here means "shift by 32 bits".
28
+ * for the M3.
29
+ */
58
+ */
30
+ cpu->isar.id_pfr0 = 0x00000030;
59
+ if (shift == 0) {
31
+ cpu->isar.id_pfr1 = 0x00000200;
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
32
+ cpu->isar.id_dfr0 = 0x00100000;
61
+ r = rdm;
33
+ cpu->id_afr0 = 0x00000000;
62
+ if (mask & 1) {
34
+ cpu->isar.id_mmfr0 = 0x00000030;
63
+ rdm = d[H4(e)];
35
+ cpu->isar.id_mmfr1 = 0x00000000;
64
+ }
36
+ cpu->isar.id_mmfr2 = 0x00000000;
65
+ mergemask(&d[H4(e)], r, mask);
37
+ cpu->isar.id_mmfr3 = 0x00000000;
66
+ }
38
+ cpu->isar.id_isar0 = 0x01141110;
67
+ } else {
39
+ cpu->isar.id_isar1 = 0x02111000;
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
40
+ cpu->isar.id_isar2 = 0x21112231;
69
+
41
+ cpu->isar.id_isar3 = 0x01111110;
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
42
+ cpu->isar.id_isar4 = 0x01310102;
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
43
+ cpu->isar.id_isar5 = 0x00000000;
72
+ if (mask & 1) {
44
+ cpu->isar.id_isar6 = 0x00000000;
73
+ rdm = d[H4(e)] >> (32 - shift);
45
}
74
+ }
46
75
+ mergemask(&d[H4(e)], r, mask);
47
static void cortex_m3_initfn(Object *obj)
76
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
89
+
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
91
+{
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
99
+
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
101
+ return false;
102
+ }
103
+ if (a->rdm == 13 || a->rdm == 15) {
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
109
+ }
110
+
111
+ qd = mve_qreg_ptr(a->qd);
112
+ rdm = load_reg(s, a->rdm);
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
117
+ return true;
118
+}
48
--
119
--
49
2.20.1
120
2.20.1
50
121
51
122
diff view generated by jsdifflib
[PULL 01/18] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
[PULL 20/24] target/arm: Implement MVE VADDLV
1
The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
bit in short-descriptor translation table format descriptors. This
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the
3
stored in a pair of general-purpose registers.
4
feature bit with an ID register check, in line with our preference
5
for ID register checks over feature bits.
6
4
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
10
---
8
---
11
target/arm/cpu.h | 15 ++++++++++++++-
9
target/arm/helper-mve.h | 3 ++
12
target/arm/cpu.c | 1 -
10
target/arm/mve.decode | 6 +++-
13
target/arm/helper.c | 5 +++--
11
target/arm/mve_helper.c | 19 ++++++++++++
14
3 files changed, 17 insertions(+), 4 deletions(-)
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
15
14
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
17
--- a/target/arm/helper-mve.h
19
+++ b/target/arm/cpu.h
18
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
FIELD(ID_ISAR6, SB, 12, 4)
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
FIELD(ID_ISAR6, SPECRES, 16, 4)
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
22
24
+FIELD(ID_MMFR0, VMSA, 0, 4)
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
25
+FIELD(ID_MMFR0, PMSA, 4, 4)
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
26
+FIELD(ID_MMFR0, OUTERSHR, 8, 4)
27
+FIELD(ID_MMFR0, SHARELVL, 12, 4)
28
+FIELD(ID_MMFR0, TCM, 16, 4)
29
+FIELD(ID_MMFR0, AUXREG, 20, 4)
30
+FIELD(ID_MMFR0, FCSE, 24, 4)
31
+FIELD(ID_MMFR0, INNERSHR, 28, 4)
32
+
25
+
33
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
34
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
35
FIELD(ID_MMFR3, BPMAINT, 8, 4)
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
36
@@ -XXX,XX +XXX,XX @@ enum arm_features {
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
37
ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
30
index XXXXXXX..XXXXXXX 100644
38
ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
31
--- a/target/arm/mve.decode
39
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
32
+++ b/target/arm/mve.decode
40
- ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
41
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
42
ARM_FEATURE_V8,
35
43
ARM_FEATURE_AARCH64, /* supports 64 bit mode */
36
# Vector add across vector
44
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
45
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
46
}
82
}
47
83
48
+static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
49
+{
85
+{
50
+ return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
86
+ /*
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
88
+ * elements of the vector into a 64-bit result stored in
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
91
+ */
92
+ TCGv_ptr qm;
93
+ TCGv_i64 rda;
94
+ TCGv_i32 rdalo, rdahi;
95
+
96
+ if (!dc_isar_feature(aa32_mve, s)) {
97
+ return false;
98
+ }
99
+ /*
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
102
+ */
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
104
+ return false;
105
+ }
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
107
+ return true;
108
+ }
109
+
110
+ /*
111
+ * This insn is subject to beat-wise execution. Partial execution
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
114
+ */
115
+ if (a->a || mve_skip_first_beat(s)) {
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
126
+ }
127
+
128
+ qm = mve_qreg_ptr(a->qm);
129
+ if (a->u) {
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
135
+
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
51
+}
145
+}
52
+
146
+
53
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
54
{
148
{
55
return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
149
TCGv_ptr qd;
56
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu.c
59
+++ b/target/arm/cpu.c
60
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
61
}
62
if (arm_feature(env, ARM_FEATURE_LPAE)) {
63
set_feature(env, ARM_FEATURE_V7MP);
64
- set_feature(env, ARM_FEATURE_PXN);
65
}
66
if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
67
set_feature(env, ARM_FEATURE_CBAR);
68
diff --git a/target/arm/helper.c b/target/arm/helper.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/helper.c
71
+++ b/target/arm/helper.c
72
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
73
target_ulong *page_size, ARMMMUFaultInfo *fi)
74
{
75
CPUState *cs = env_cpu(env);
76
+ ARMCPU *cpu = env_archcpu(env);
77
int level = 1;
78
uint32_t table;
79
uint32_t desc;
80
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
81
goto do_fault;
82
}
83
type = (desc & 3);
84
- if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
85
+ if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
86
/* Section translation fault, or attempt to use the encoding
87
* which is Reserved on implementations without PXN.
88
*/
89
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
90
pxn = desc & 1;
91
ns = extract32(desc, 19, 1);
92
} else {
93
- if (arm_feature(env, ARM_FEATURE_PXN)) {
94
+ if (cpu_isar_feature(aa32_pxn, cpu)) {
95
pxn = (desc >> 2) & 1;
96
}
97
ns = extract32(desc, 3, 1);
98
--
150
--
99
2.20.1
151
2.20.1
100
152
101
153
diff view generated by jsdifflib
[PULL 07/18] target/arm: Fix SVE splice
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The MVE extension to v8.1M includes some new shift instructions which
2
2
sit entirely within the non-coprocessor part of the encoding space
3
While converting to gen_gvec_ool_zzzp, we lost passing
3
and which operate only on general-purpose registers. They take up
4
a->esz as the data argument to the function.
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
5
with Rm == 13 or 15.
6
Fixes: 36cbb7a8e71
6
7
Cc: qemu-stable@nongnu.org
7
Implement the long shifts by immediate, which perform shifts on a
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org
9
an immediate shift count between 1 and 32.
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
23
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
12
---
27
---
13
target/arm/translate-sve.c | 2 +-
28
target/arm/helper-mve.h | 3 ++
14
1 file changed, 1 insertion(+), 1 deletion(-)
29
target/arm/translate.h | 1 +
15
30
target/arm/t32.decode | 28 +++++++++++++
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
31
target/arm/mve_helper.c | 10 +++++
17
index XXXXXXX..XXXXXXX 100644
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
18
--- a/target/arm/translate-sve.c
33
5 files changed, 132 insertions(+)
19
+++ b/target/arm/translate-sve.c
34
20
@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper-mve.h
38
+++ b/target/arm/helper-mve.h
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
43
+
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
49
+++ b/target/arm/translate.h
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@
63
&mcr !extern cp opc1 crn crm opc2 rt
64
&mcrr !extern cp opc1 crm rt rt2
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
21
{
83
{
22
if (sve_access_check(s)) {
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
23
gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
24
- a->rd, a->rn, a->rm, a->pg, 0);
86
}
25
+ a->rd, a->rn, a->rm, a->pg, a->esz);
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
26
}
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
27
return true;
133
return true;
28
}
134
}
135
136
+/*
137
+ * v8.1M MVE wide-shifts
138
+ */
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
140
+ WideShiftImmFn *fn)
141
+{
142
+ TCGv_i64 rda;
143
+ TCGv_i32 rdalo, rdahi;
144
+
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
147
+ return false;
148
+ }
149
+ if (a->rdahi == 15) {
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
151
+ return false;
152
+ }
153
+ if (!dc_isar_feature(aa32_mve, s) ||
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
155
+ a->rdahi == 13) {
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
157
+ unallocated_encoding(s);
158
+ return true;
159
+ }
160
+
161
+ if (a->shim == 0) {
162
+ a->shim = 32;
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
29
--
229
--
30
2.20.1
230
2.20.1
31
231
32
232
diff view generated by jsdifflib
[PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
M-profile CPUs only implement the ID registers as guest-visible if
1
Implement the MVE long shifts by register, which perform shifts on a
2
the CPU implements the Main Extension (all our current CPUs except
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
the Cortex-M0 do).
3
the shift count in another general-purpose register, which might be
4
4
either positive or negative.
5
Currently we handle this by having the Cortex-M0 leave the ID
5
6
register values in the ARMCPU struct as zero, but this conflicts with
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
our design decision to make QEMU behaviour be keyed off ID register
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
fields wherever possible.
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
Explicitly code the ID registers in the NVIC to return 0 if the Main
10
we have to move the CSEL pattern into the same decodetree group.
11
Extension is not implemented, so we can make the M0 model set the
12
ARMCPU struct fields to obtain the correct behaviour without those
13
values becoming guest-visible.
14
11
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20200910173855.4068-4-peter.maydell@linaro.org
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
18
---
15
---
19
hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++
16
target/arm/helper-mve.h | 6 +++
20
1 file changed, 42 insertions(+)
17
target/arm/translate.h | 1 +
21
18
target/arm/t32.decode | 16 +++++--
22
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
23
index XXXXXXX..XXXXXXX 100644
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
24
--- a/hw/intc/armv7m_nvic.c
21
5 files changed, 182 insertions(+), 3 deletions(-)
25
+++ b/hw/intc/armv7m_nvic.c
22
26
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
27
"Aux Fault status registers unimplemented\n");
24
index XXXXXXX..XXXXXXX 100644
28
return 0;
25
--- a/target/arm/helper-mve.h
29
case 0xd40: /* PFR0. */
26
+++ b/target/arm/helper-mve.h
30
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+ goto bad_offset;
28
32
+ }
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
33
return cpu->isar.id_pfr0;
30
34
case 0xd44: /* PFR1. */
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
36
+ goto bad_offset;
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
37
+ }
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
38
return cpu->isar.id_pfr1;
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
39
case 0xd48: /* DFR0. */
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
40
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
41
+ goto bad_offset;
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
42
+ }
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
43
return cpu->isar.id_dfr0;
40
index XXXXXXX..XXXXXXX 100644
44
case 0xd4c: /* AFR0. */
41
--- a/target/arm/translate.h
45
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
42
+++ b/target/arm/translate.h
46
+ goto bad_offset;
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
47
+ }
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
48
return cpu->id_afr0;
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
49
case 0xd50: /* MMFR0. */
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
50
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
51
+ goto bad_offset;
48
52
+ }
49
/**
53
return cpu->isar.id_mmfr0;
50
* arm_tbflags_from_tb:
54
case 0xd54: /* MMFR1. */
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
55
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
52
index XXXXXXX..XXXXXXX 100644
56
+ goto bad_offset;
53
--- a/target/arm/t32.decode
57
+ }
54
+++ b/target/arm/t32.decode
58
return cpu->isar.id_mmfr1;
55
@@ -XXX,XX +XXX,XX @@
59
case 0xd58: /* MMFR2. */
56
&mcrr !extern cp opc1 crm rt rt2
60
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
57
61
+ goto bad_offset;
58
&mve_shl_ri rdalo rdahi shim
62
+ }
59
+&mve_shl_rr rdalo rdahi rm
63
return cpu->isar.id_mmfr2;
60
64
case 0xd5c: /* MMFR3. */
61
# rdahi: bits [3:1] from insn, bit 0 is 1
65
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
62
# rdalo: bits [3:1] from insn, bit 0 is 0
66
+ goto bad_offset;
63
@@ -XXX,XX +XXX,XX @@
67
+ }
64
68
return cpu->isar.id_mmfr3;
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
69
case 0xd60: /* ISAR0. */
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
70
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
71
+ goto bad_offset;
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
72
+ }
69
73
return cpu->isar.id_isar0;
70
{
74
case 0xd64: /* ISAR1. */
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
75
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
76
+ goto bad_offset;
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
+ }
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
return cpu->isar.id_isar1;
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
case 0xd68: /* ISAR2. */
76
+
80
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
81
+ goto bad_offset;
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
82
+ }
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
83
return cpu->isar.id_isar2;
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
84
case 0xd6c: /* ISAR3. */
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
85
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
86
+ goto bad_offset;
83
]
87
+ }
84
88
return cpu->isar.id_isar3;
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
89
case 0xd70: /* ISAR4. */
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
90
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
87
+
91
+ goto bad_offset;
88
+ # v8.1M CSEL and friends
92
+ }
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
93
return cpu->isar.id_isar4;
90
}
94
case 0xd74: /* ISAR5. */
91
{
95
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
96
+ goto bad_offset;
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
97
+ }
94
}
98
return cpu->isar.id_isar5;
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
99
case 0xd78: /* CLIDR */
96
100
return cpu->clidr;
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
99
-
100
# Data-processing (register-shifted register)
101
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/mve_helper.c
106
+++ b/target/arm/mve_helper.c
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
108
return rdm;
109
}
110
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
112
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
114
+}
115
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
117
+{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
217
}
218
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
220
+{
221
+ TCGv_i64 rda;
222
+ TCGv_i32 rdalo, rdahi;
223
+
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
226
+ return false;
227
+ }
228
+ if (a->rdahi == 15) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
230
+ return false;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
238
+ return true;
239
+ }
240
+
241
+ rda = tcg_temp_new_i64();
242
+ rdalo = load_reg(s, a->rdalo);
243
+ rdahi = load_reg(s, a->rdahi);
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
245
+
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
248
+
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
251
+ store_reg(s, a->rdalo, rdalo);
252
+ store_reg(s, a->rdahi, rdahi);
253
+ tcg_temp_free_i64(rda);
254
+
255
+ return true;
256
+}
257
+
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
259
+{
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
261
+}
262
+
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
264
+{
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
266
+}
267
+
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
269
+{
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
271
+}
272
+
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
274
+{
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
276
+}
277
+
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
279
+{
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
281
+}
282
+
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
286
+}
287
+
288
/*
289
* Multiply and multiply accumulate
290
*/
101
--
291
--
102
2.20.1
292
2.20.1
103
293
104
294
diff view generated by jsdifflib
[PULL 16/18] hw/arm/raspi: Introduce RaspiProcessorId enum
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE shifts by immediate, which perform shifts
2
2
on a single general-purpose register.
3
As we only support a reduced set of the REV_CODE_PROCESSOR id
3
4
encoded in the board revision, define the PROCESSOR_ID values
4
These patterns overlap with the long-shift-by-immediates,
5
as an enum. We can simplify the board_soc_type and cores_count
5
so we have to rearrange the grouping a little here.
6
methods.
6
7
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200924111808.77168-7-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
12
---
10
---
13
hw/arm/raspi.c | 45 +++++++++++++++++++++------------------------
11
target/arm/helper-mve.h | 3 ++
14
1 file changed, 21 insertions(+), 24 deletions(-)
12
target/arm/translate.h | 1 +
15
13
target/arm/t32.decode | 31 ++++++++++++++-----
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
target/arm/mve_helper.c | 10 ++++++
17
index XXXXXXX..XXXXXXX 100644
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
18
--- a/hw/arm/raspi.c
16
5 files changed, 104 insertions(+), 9 deletions(-)
19
+++ b/hw/arm/raspi.c
17
20
@@ -XXX,XX +XXX,XX @@ FIELD(REV_CODE, MANUFACTURER, 16, 4);
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
21
FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
19
index XXXXXXX..XXXXXXX 100644
22
FIELD(REV_CODE, STYLE, 23, 1);
20
--- a/target/arm/helper-mve.h
23
21
+++ b/target/arm/helper-mve.h
24
+typedef enum RaspiProcessorId {
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
+ PROCESSOR_ID_BCM2836 = 1,
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
+ PROCESSOR_ID_BCM2837 = 2,
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
27
+} RaspiProcessorId;
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
28
+
26
+
29
+static const struct {
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
30
+ const char *type;
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
31
+ int cores_count;
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
32
+} soc_property[] = {
30
index XXXXXXX..XXXXXXX 100644
33
+ [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
31
--- a/target/arm/translate.h
34
+ [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
32
+++ b/target/arm/translate.h
35
+};
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
36
+
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
37
static uint64_t board_ram_size(uint32_t board_rev)
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
38
{
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
39
assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
40
return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
38
39
/**
40
* arm_tbflags_from_tb:
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/t32.decode
44
+++ b/target/arm/t32.decode
45
@@ -XXX,XX +XXX,XX @@
46
47
&mve_shl_ri rdalo rdahi shim
48
&mve_shl_rr rdalo rdahi rm
49
+&mve_sh_ri rda shim
50
51
# rdahi: bits [3:1] from insn, bit 0 is 1
52
# rdalo: bits [3:1] from insn, bit 0 is 0
53
@@ -XXX,XX +XXX,XX @@
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
58
+ &mve_sh_ri shim=%imm5_12_6
59
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
41
}
105
}
42
106
+
43
-static int board_processor_id(uint32_t board_rev)
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
44
+static RaspiProcessorId board_processor_id(uint32_t board_rev)
108
+{
45
{
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
46
+ int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
110
+}
47
+
111
+
48
assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
49
- return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
113
+{
50
+ assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type);
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
51
+
115
+}
52
+ return proc_id;
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/arm/translate.c
119
+++ b/target/arm/translate.c
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
121
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
123
{
124
- TCGv_i32 t = tcg_temp_new_i32();
125
+ TCGv_i32 t;
126
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
128
+ if (sh == 32) {
129
+ tcg_gen_movi_i32(d, 0);
130
+ return;
131
+ }
132
+ t = tcg_temp_new_i32();
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
134
tcg_gen_sari_i32(d, a, sh);
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
53
}
154
}
54
155
55
static int board_version(uint32_t board_rev)
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
56
@@ -XXX,XX +XXX,XX @@ static int board_version(uint32_t board_rev)
157
+{
57
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
58
static const char *board_soc_type(uint32_t board_rev)
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
59
{
160
+ return false;
60
- static const char *soc_types[] = {
161
+ }
61
- NULL, TYPE_BCM2836, TYPE_BCM2837,
162
+ if (!dc_isar_feature(aa32_mve, s) ||
62
- };
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
63
- int proc_id = board_processor_id(board_rev);
164
+ a->rda == 13 || a->rda == 15) {
64
-
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
65
- if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
166
+ unallocated_encoding(s);
66
- error_report("Unsupported processor id '%d' (board revision: 0x%x)",
167
+ return true;
67
- proc_id, board_rev);
168
+ }
68
- exit(1);
169
+
69
- }
170
+ if (a->shim == 0) {
70
- return soc_types[proc_id];
171
+ a->shim = 32;
71
+ return soc_property[board_processor_id(board_rev)].type;
172
+ }
72
}
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
73
174
+
74
static int cores_count(uint32_t board_rev)
175
+ return true;
75
{
176
+}
76
- static const int soc_cores_count[] = {
177
+
77
- 0, BCM283X_NCPUS, BCM283X_NCPUS,
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
78
- };
179
+{
79
- int proc_id = board_processor_id(board_rev);
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
80
-
181
+}
81
- if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
182
+
82
- error_report("Unsupported processor id '%d' (board revision: 0x%x)",
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
83
- proc_id, board_rev);
184
+{
84
- exit(1);
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
85
- }
186
+}
86
- return soc_cores_count[proc_id];
187
+
87
+ return soc_property[board_processor_id(board_rev)].cores_count;
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
88
}
189
+{
89
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
90
static const char *board_type(uint32_t board_rev)
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
91
--
211
--
92
2.20.1
212
2.20.1
93
213
94
214
diff view generated by jsdifflib
[PULL 02/18] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
[PULL 24/24] target/arm: Implement MVE shifts by register
1
Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
1
Implement the MVE shifts by register, which perform
2
sub-struct. We're going to want id_pfr1 for an isar_features
2
shifts on a single general-purpose register.
3
check, and moving both at the same time avoids an odd
4
inconsistency.
5
6
Changes other than the ones to cpu.h and kvm64.c made
7
automatically with:
8
perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c
9
3
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
13
---
7
---
14
target/arm/cpu.h | 4 ++--
8
target/arm/helper-mve.h | 2 ++
15
hw/intc/armv7m_nvic.c | 4 ++--
9
target/arm/translate.h | 1 +
16
target/arm/cpu.c | 20 ++++++++++----------
10
target/arm/t32.decode | 18 ++++++++++++++----
17
target/arm/cpu64.c | 12 ++++++------
11
target/arm/mve_helper.c | 10 ++++++++++
18
target/arm/cpu_tcg.c | 36 ++++++++++++++++++------------------
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
19
target/arm/helper.c | 4 ++--
13
5 files changed, 57 insertions(+), 4 deletions(-)
20
target/arm/kvm64.c | 4 ++++
21
7 files changed, 44 insertions(+), 40 deletions(-)
22
14
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
17
--- a/target/arm/helper-mve.h
26
+++ b/target/arm/cpu.h
18
+++ b/target/arm/helper-mve.h
27
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
28
uint32_t id_mmfr2;
20
29
uint32_t id_mmfr3;
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
30
uint32_t id_mmfr4;
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
31
+ uint32_t id_pfr0;
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
32
+ uint32_t id_pfr1;
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
33
uint32_t mvfr0;
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
34
uint32_t mvfr1;
35
uint32_t mvfr2;
36
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
37
uint32_t reset_fpsid;
38
uint32_t ctr;
39
uint32_t reset_sctlr;
40
- uint32_t id_pfr0;
41
- uint32_t id_pfr1;
42
uint64_t pmceid0;
43
uint64_t pmceid1;
44
uint32_t id_afr0;
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
27
--- a/target/arm/translate.h
48
+++ b/hw/intc/armv7m_nvic.c
28
+++ b/target/arm/translate.h
49
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
50
"Aux Fault status registers unimplemented\n");
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
51
return 0;
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
52
case 0xd40: /* PFR0. */
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
53
- return cpu->id_pfr0;
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
54
+ return cpu->isar.id_pfr0;
34
55
case 0xd44: /* PFR1. */
35
/**
56
- return cpu->id_pfr1;
36
* arm_tbflags_from_tb:
57
+ return cpu->isar.id_pfr1;
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
58
case 0xd48: /* DFR0. */
59
return cpu->isar.id_dfr0;
60
case 0xd4c: /* AFR0. */
61
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
62
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/cpu.c
39
--- a/target/arm/t32.decode
64
+++ b/target/arm/cpu.c
40
+++ b/target/arm/t32.decode
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
41
@@ -XXX,XX +XXX,XX @@
66
/* Disable the security extension feature bits in the processor feature
42
&mve_shl_ri rdalo rdahi shim
67
* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
43
&mve_shl_rr rdalo rdahi rm
68
*/
44
&mve_sh_ri rda shim
69
- cpu->id_pfr1 &= ~0xf0;
45
+&mve_sh_rr rda rm
70
+ cpu->isar.id_pfr1 &= ~0xf0;
46
71
cpu->isar.id_aa64pfr0 &= ~0xf000;
47
# rdahi: bits [3:1] from insn, bit 0 is 1
48
# rdalo: bits [3:1] from insn, bit 0 is 0
49
@@ -XXX,XX +XXX,XX @@
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
52
&mve_sh_ri shim=%imm5_12_6
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
54
55
{
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
72
}
59
}
73
60
74
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
75
* id_aa64pfr0_el1[11:8].
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
76
*/
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
77
cpu->isar.id_aa64pfr0 &= ~0xf00;
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
78
- cpu->id_pfr1 &= ~0xf000;
65
+ {
79
+ cpu->isar.id_pfr1 &= ~0xf000;
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
80
}
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
81
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
82
#ifndef CONFIG_USER_ONLY
69
+ }
83
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
70
+
84
cpu->isar.mvfr1 = 0x00011111;
71
+ {
85
cpu->ctr = 0x82048004;
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
86
cpu->reset_sctlr = 0x00c50078;
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
87
- cpu->id_pfr0 = 0x1031;
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
88
- cpu->id_pfr1 = 0x11;
75
+ }
89
+ cpu->isar.id_pfr0 = 0x1031;
76
+
90
+ cpu->isar.id_pfr1 = 0x11;
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
91
cpu->isar.id_dfr0 = 0x400;
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
92
cpu->id_afr0 = 0;
79
]
93
cpu->isar.id_mmfr0 = 0x31100003;
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
95
cpu->isar.mvfr1 = 0x01111111;
96
cpu->ctr = 0x80038003;
97
cpu->reset_sctlr = 0x00c50078;
98
- cpu->id_pfr0 = 0x1031;
99
- cpu->id_pfr1 = 0x11;
100
+ cpu->isar.id_pfr0 = 0x1031;
101
+ cpu->isar.id_pfr1 = 0x11;
102
cpu->isar.id_dfr0 = 0x000;
103
cpu->id_afr0 = 0;
104
cpu->isar.id_mmfr0 = 0x00100103;
105
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
106
cpu->isar.mvfr1 = 0x11111111;
107
cpu->ctr = 0x84448003;
108
cpu->reset_sctlr = 0x00c50078;
109
- cpu->id_pfr0 = 0x00001131;
110
- cpu->id_pfr1 = 0x00011011;
111
+ cpu->isar.id_pfr0 = 0x00001131;
112
+ cpu->isar.id_pfr1 = 0x00011011;
113
cpu->isar.id_dfr0 = 0x02010555;
114
cpu->id_afr0 = 0x00000000;
115
cpu->isar.id_mmfr0 = 0x10101105;
116
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
117
cpu->isar.mvfr1 = 0x11111111;
118
cpu->ctr = 0x8444c004;
119
cpu->reset_sctlr = 0x00c50078;
120
- cpu->id_pfr0 = 0x00001131;
121
- cpu->id_pfr1 = 0x00011011;
122
+ cpu->isar.id_pfr0 = 0x00001131;
123
+ cpu->isar.id_pfr1 = 0x00011011;
124
cpu->isar.id_dfr0 = 0x02010555;
125
cpu->id_afr0 = 0x00000000;
126
cpu->isar.id_mmfr0 = 0x10201105;
127
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
128
index XXXXXXX..XXXXXXX 100644
81
index XXXXXXX..XXXXXXX 100644
129
--- a/target/arm/cpu64.c
82
--- a/target/arm/mve_helper.c
130
+++ b/target/arm/cpu64.c
83
+++ b/target/arm/mve_helper.c
131
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
132
cpu->isar.mvfr2 = 0x00000043;
85
{
133
cpu->ctr = 0x8444c004;
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
134
cpu->reset_sctlr = 0x00c50838;
87
}
135
- cpu->id_pfr0 = 0x00000131;
88
+
136
- cpu->id_pfr1 = 0x00011011;
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
137
+ cpu->isar.id_pfr0 = 0x00000131;
90
+{
138
+ cpu->isar.id_pfr1 = 0x00011011;
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
139
cpu->isar.id_dfr0 = 0x03010066;
92
+}
140
cpu->id_afr0 = 0x00000000;
93
+
141
cpu->isar.id_mmfr0 = 0x10101105;
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
142
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
95
+{
143
cpu->isar.mvfr2 = 0x00000043;
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
144
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
97
+}
145
cpu->reset_sctlr = 0x00c50838;
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
146
- cpu->id_pfr0 = 0x00000131;
147
- cpu->id_pfr1 = 0x00011011;
148
+ cpu->isar.id_pfr0 = 0x00000131;
149
+ cpu->isar.id_pfr1 = 0x00011011;
150
cpu->isar.id_dfr0 = 0x03010066;
151
cpu->id_afr0 = 0x00000000;
152
cpu->isar.id_mmfr0 = 0x10101105;
153
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
154
cpu->isar.mvfr2 = 0x00000043;
155
cpu->ctr = 0x8444c004;
156
cpu->reset_sctlr = 0x00c50838;
157
- cpu->id_pfr0 = 0x00000131;
158
- cpu->id_pfr1 = 0x00011011;
159
+ cpu->isar.id_pfr0 = 0x00000131;
160
+ cpu->isar.id_pfr1 = 0x00011011;
161
cpu->isar.id_dfr0 = 0x03010066;
162
cpu->id_afr0 = 0x00000000;
163
cpu->isar.id_mmfr0 = 0x10201105;
164
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
165
index XXXXXXX..XXXXXXX 100644
99
index XXXXXXX..XXXXXXX 100644
166
--- a/target/arm/cpu_tcg.c
100
--- a/target/arm/translate.c
167
+++ b/target/arm/cpu_tcg.c
101
+++ b/target/arm/translate.c
168
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
169
cpu->isar.mvfr1 = 0x00000000;
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
170
cpu->ctr = 0x1dd20d2;
104
}
171
cpu->reset_sctlr = 0x00050078;
105
172
- cpu->id_pfr0 = 0x111;
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
173
- cpu->id_pfr1 = 0x1;
107
+{
174
+ cpu->isar.id_pfr0 = 0x111;
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
175
+ cpu->isar.id_pfr1 = 0x1;
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
176
cpu->isar.id_dfr0 = 0x2;
110
+ return false;
177
cpu->id_afr0 = 0x3;
111
+ }
178
cpu->isar.id_mmfr0 = 0x01130003;
112
+ if (!dc_isar_feature(aa32_mve, s) ||
179
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
180
cpu->isar.mvfr1 = 0x00000000;
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
181
cpu->ctr = 0x1dd20d2;
115
+ a->rm == a->rda) {
182
cpu->reset_sctlr = 0x00050078;
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
183
- cpu->id_pfr0 = 0x111;
117
+ unallocated_encoding(s);
184
- cpu->id_pfr1 = 0x1;
118
+ return true;
185
+ cpu->isar.id_pfr0 = 0x111;
119
+ }
186
+ cpu->isar.id_pfr1 = 0x1;
120
+
187
cpu->isar.id_dfr0 = 0x2;
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
188
cpu->id_afr0 = 0x3;
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
189
cpu->isar.id_mmfr0 = 0x01130003;
123
+ return true;
190
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
124
+}
191
cpu->isar.mvfr1 = 0x00000000;
125
+
192
cpu->ctr = 0x1dd20d2;
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
193
cpu->reset_sctlr = 0x00050078;
127
+{
194
- cpu->id_pfr0 = 0x111;
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
195
- cpu->id_pfr1 = 0x11;
129
+}
196
+ cpu->isar.id_pfr0 = 0x111;
130
+
197
+ cpu->isar.id_pfr1 = 0x11;
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
198
cpu->isar.id_dfr0 = 0x33;
132
+{
199
cpu->id_afr0 = 0;
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
200
cpu->isar.id_mmfr0 = 0x01130003;
134
+}
201
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
135
+
202
cpu->isar.mvfr0 = 0x11111111;
136
/*
203
cpu->isar.mvfr1 = 0x00000000;
137
* Multiply and multiply accumulate
204
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
138
*/
205
- cpu->id_pfr0 = 0x111;
206
- cpu->id_pfr1 = 0x1;
207
+ cpu->isar.id_pfr0 = 0x111;
208
+ cpu->isar.id_pfr1 = 0x1;
209
cpu->isar.id_dfr0 = 0;
210
cpu->id_afr0 = 0x2;
211
cpu->isar.id_mmfr0 = 0x01100103;
212
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
213
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
214
cpu->midr = 0x410fc231;
215
cpu->pmsav7_dregion = 8;
216
- cpu->id_pfr0 = 0x00000030;
217
- cpu->id_pfr1 = 0x00000200;
218
+ cpu->isar.id_pfr0 = 0x00000030;
219
+ cpu->isar.id_pfr1 = 0x00000200;
220
cpu->isar.id_dfr0 = 0x00100000;
221
cpu->id_afr0 = 0x00000000;
222
cpu->isar.id_mmfr0 = 0x00000030;
223
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
224
cpu->isar.mvfr0 = 0x10110021;
225
cpu->isar.mvfr1 = 0x11000011;
226
cpu->isar.mvfr2 = 0x00000000;
227
- cpu->id_pfr0 = 0x00000030;
228
- cpu->id_pfr1 = 0x00000200;
229
+ cpu->isar.id_pfr0 = 0x00000030;
230
+ cpu->isar.id_pfr1 = 0x00000200;
231
cpu->isar.id_dfr0 = 0x00100000;
232
cpu->id_afr0 = 0x00000000;
233
cpu->isar.id_mmfr0 = 0x00000030;
234
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
235
cpu->isar.mvfr0 = 0x10110221;
236
cpu->isar.mvfr1 = 0x12000011;
237
cpu->isar.mvfr2 = 0x00000040;
238
- cpu->id_pfr0 = 0x00000030;
239
- cpu->id_pfr1 = 0x00000200;
240
+ cpu->isar.id_pfr0 = 0x00000030;
241
+ cpu->isar.id_pfr1 = 0x00000200;
242
cpu->isar.id_dfr0 = 0x00100000;
243
cpu->id_afr0 = 0x00000000;
244
cpu->isar.id_mmfr0 = 0x00100030;
245
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
246
cpu->isar.mvfr0 = 0x10110021;
247
cpu->isar.mvfr1 = 0x11000011;
248
cpu->isar.mvfr2 = 0x00000040;
249
- cpu->id_pfr0 = 0x00000030;
250
- cpu->id_pfr1 = 0x00000210;
251
+ cpu->isar.id_pfr0 = 0x00000030;
252
+ cpu->isar.id_pfr1 = 0x00000210;
253
cpu->isar.id_dfr0 = 0x00200000;
254
cpu->id_afr0 = 0x00000000;
255
cpu->isar.id_mmfr0 = 0x00101F40;
256
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
257
set_feature(&cpu->env, ARM_FEATURE_PMSA);
258
set_feature(&cpu->env, ARM_FEATURE_PMU);
259
cpu->midr = 0x411fc153; /* r1p3 */
260
- cpu->id_pfr0 = 0x0131;
261
- cpu->id_pfr1 = 0x001;
262
+ cpu->isar.id_pfr0 = 0x0131;
263
+ cpu->isar.id_pfr1 = 0x001;
264
cpu->isar.id_dfr0 = 0x010400;
265
cpu->id_afr0 = 0x0;
266
cpu->isar.id_mmfr0 = 0x0210030;
267
diff --git a/target/arm/helper.c b/target/arm/helper.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/target/arm/helper.c
270
+++ b/target/arm/helper.c
271
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
272
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
273
{
274
ARMCPU *cpu = env_archcpu(env);
275
- uint64_t pfr1 = cpu->id_pfr1;
276
+ uint64_t pfr1 = cpu->isar.id_pfr1;
277
278
if (env->gicv3state) {
279
pfr1 |= 1 << 28;
280
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa32_tid3,
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- .resetvalue = cpu->id_pfr0 },
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+ .resetvalue = cpu->isar.id_pfr0 },
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/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
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* the value of the GIC field until after we define these regs.
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*/
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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* than skipping the reads and leaving 0, as we must avoid
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* considering the values in every case.
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*/
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+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
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+ ARM64_SYS_REG(3, 0, 0, 1, 0));
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+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
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+ ARM64_SYS_REG(3, 0, 0, 1, 1));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
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ARM64_SYS_REG(3, 0, 0, 1, 2));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
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--
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--
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2.20.1
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2.20.1
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141
307
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Patchew 2.1-devel-b67e4c2

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