1
Nothing very exciting this time around...
1
The following changes since commit 7e7eb9f852a46b51a71ae9d82590b2e4d28827ee:
2
2
3
-- PMM
3
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-01-28' into staging (2021-01-28 22:43:18 +0000)
4
5
The following changes since commit 37a712a0f969ca2df7f01182409a6c4825cebfb5:
6
7
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-10-01 12:23:19 +0100)
8
4
9
are available in the Git repository at:
5
are available in the Git repository at:
10
6
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201001
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210129
12
8
13
for you to fetch changes up to cdfaa57dcb53ba012439765a1462247dfda8595d:
9
for you to fetch changes up to 11749122e1a86866591306d43603d2795a3dea1a:
14
10
15
hw/arm/raspi: Remove use of the 'version' value in the board code (2020-10-01 15:31:01 +0100)
11
hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS (2021-01-29 10:47:29 +0000)
16
12
17
----------------------------------------------------------------
13
----------------------------------------------------------------
18
target-arm queue:
14
target-arm queue:
19
* Make isar_feature_aa32_fp16_arith() handle M-profile
15
* Implement ID_PFR2
20
* Fix SVE splice
16
* Conditionalize DBGDIDR
21
* Fix SVE LDR/STR
17
* rename xlnx-zcu102.canbusN properties
22
* Remove ignore_memory_transaction_failures on the raspi2
18
* provide powerdown/reset mechanism for secure firmware on 'virt' board
23
* raspi: Various cleanup/refactoring
19
* hw/misc: Fix arith overflow in NPCM7XX PWM module
20
* target/arm: Replace magic value by MMU_DATA_LOAD definition
21
* configure: fix preadv errors on Catalina macOS with new XCode
22
* Various configure and other cleanups in preparation for iOS support
23
* hvf: Add hypervisor entitlement to output binaries (needed for Big Sur)
24
* Implement pvpanic-pci device
25
* Convert the CMSDK timer devices to the Clock framework
24
26
25
----------------------------------------------------------------
27
----------------------------------------------------------------
26
Peter Maydell (5):
28
Alexander Graf (1):
27
target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
29
hvf: Add hypervisor entitlement to output binaries
28
target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
29
hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
30
target/arm: Add ID register values for Cortex-M0
31
target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
32
30
33
Philippe Mathieu-Daudé (11):
31
Hao Wu (1):
34
hw/arm/raspi: Define various blocks base addresses
32
hw/misc: Fix arith overflow in NPCM7XX PWM module
35
hw/arm/bcm2835: Add more unimplemented peripherals
33
36
hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
34
Joelle van Dyne (7):
37
hw/arm/raspi: Display the board revision in the machine description
35
configure: cross-compiling with empty cross_prefix
38
hw/arm/raspi: Load the firmware on the first core
36
osdep: build with non-working system() function
39
hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
37
darwin: remove redundant dependency declaration
40
hw/arm/raspi: Avoid using TypeInfo::class_data pointer
38
darwin: fix cross-compiling for Darwin
41
hw/arm/raspi: Use more specific machine names
39
configure: cross compile should use x86_64 cpu_family
42
hw/arm/raspi: Introduce RaspiProcessorId enum
40
darwin: detect CoreAudio for build
43
hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
41
darwin: remove 64-bit build detection on 32-bit OS
44
hw/arm/raspi: Remove use of the 'version' value in the board code
42
43
Maxim Uvarov (3):
44
hw: gpio: implement gpio-pwr driver for qemu reset/poweroff
45
arm-virt: refactor gpios creation
46
arm-virt: add secure pl061 for reset/power down
47
48
Mihai Carabas (4):
49
hw/misc/pvpanic: split-out generic and bus dependent code
50
hw/misc/pvpanic: add PCI interface support
51
pvpanic : update pvpanic spec document
52
tests/qtest: add a test case for pvpanic-pci
53
54
Paolo Bonzini (1):
55
arm: rename xlnx-zcu102.canbusN properties
56
57
Peter Maydell (26):
58
configure: Move preadv check to meson.build
59
ptimer: Add new ptimer_set_period_from_clock() function
60
clock: Add new clock_has_source() function
61
tests: Add a simple test of the CMSDK APB timer
62
tests: Add a simple test of the CMSDK APB watchdog
63
tests: Add a simple test of the CMSDK APB dual timer
64
hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer
65
hw/timer/cmsdk-apb-timer: Add Clock input
66
hw/timer/cmsdk-apb-dualtimer: Add Clock input
67
hw/watchdog/cmsdk-apb-watchdog: Add Clock input
68
hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
69
hw/arm/armsse: Wire up clocks
70
hw/arm/mps2: Inline CMSDK_APB_TIMER creation
71
hw/arm/mps2: Create and connect SYSCLK Clock
72
hw/arm/mps2-tz: Create and connect ARMSSE Clocks
73
hw/arm/musca: Create and connect ARMSSE Clocks
74
hw/arm/stellaris: Convert SSYS to QOM device
75
hw/arm/stellaris: Create Clock input for watchdog
76
hw/timer/cmsdk-apb-timer: Convert to use Clock input
77
hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
78
hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input
79
tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
80
hw/arm/armsse: Use Clock to set system_clock_scale
81
arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
82
arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
83
hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS
84
85
Philippe Mathieu-Daudé (1):
86
target/arm: Replace magic value by MMU_DATA_LOAD definition
45
87
46
Richard Henderson (2):
88
Richard Henderson (2):
47
target/arm: Fix sve ldr/str
89
target/arm: Implement ID_PFR2
48
target/arm: Fix SVE splice
90
target/arm: Conditionalize DBGDIDR
49
91
50
include/hw/arm/bcm2835_peripherals.h | 2 +
92
docs/devel/clocks.rst | 16 +++
51
include/hw/arm/raspi_platform.h | 51 ++++++++++--
93
docs/specs/pci-ids.txt | 1 +
52
target/arm/cpu.h | 50 +++++++++--
94
docs/specs/pvpanic.txt | 13 ++-
53
hw/arm/bcm2835_peripherals.c | 2 +
95
docs/system/arm/virt.rst | 2 +
54
hw/arm/raspi.c | 155 +++++++++++++++++++----------------
96
configure | 78 ++++++++------
55
hw/intc/armv7m_nvic.c | 46 ++++++++++-
97
meson.build | 34 ++++++-
56
target/arm/cpu.c | 21 +++--
98
include/hw/arm/armsse.h | 14 ++-
57
target/arm/cpu64.c | 12 +--
99
include/hw/arm/virt.h | 2 +
58
target/arm/cpu_tcg.c | 60 ++++++++++----
100
include/hw/clock.h | 15 +++
59
target/arm/helper.c | 9 +-
101
include/hw/misc/pvpanic.h | 24 ++++-
60
target/arm/kvm64.c | 4 +
102
include/hw/pci/pci.h | 1 +
61
target/arm/translate-sve.c | 6 +-
103
include/hw/ptimer.h | 22 ++++
62
12 files changed, 286 insertions(+), 132 deletions(-)
104
include/hw/timer/cmsdk-apb-dualtimer.h | 5 +-
105
include/hw/timer/cmsdk-apb-timer.h | 34 ++-----
106
include/hw/watchdog/cmsdk-apb-watchdog.h | 5 +-
107
include/qemu/osdep.h | 12 +++
108
include/qemu/typedefs.h | 1 +
109
target/arm/cpu.h | 1 +
110
hw/arm/armsse.c | 48 ++++++---
111
hw/arm/mps2-tz.c | 14 ++-
112
hw/arm/mps2.c | 28 ++++-
113
hw/arm/musca.c | 13 ++-
114
hw/arm/stellaris.c | 170 +++++++++++++++++++++++--------
115
hw/arm/virt.c | 111 ++++++++++++++++----
116
hw/arm/xlnx-zcu102.c | 4 +-
117
hw/core/ptimer.c | 34 +++++++
118
hw/gpio/gpio_pwr.c | 70 +++++++++++++
119
hw/misc/npcm7xx_pwm.c | 23 ++++-
120
hw/misc/pvpanic-isa.c | 94 +++++++++++++++++
121
hw/misc/pvpanic-pci.c | 94 +++++++++++++++++
122
hw/misc/pvpanic.c | 85 ++--------------
123
hw/timer/cmsdk-apb-dualtimer.c | 53 +++++++---
124
hw/timer/cmsdk-apb-timer.c | 55 +++++-----
125
hw/watchdog/cmsdk-apb-watchdog.c | 29 ++++--
126
target/arm/helper.c | 27 +++--
127
target/arm/kvm64.c | 2 +
128
tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++
129
tests/qtest/cmsdk-apb-timer-test.c | 75 ++++++++++++++
130
tests/qtest/cmsdk-apb-watchdog-test.c | 131 ++++++++++++++++++++++++
131
tests/qtest/npcm7xx_pwm-test.c | 4 +-
132
tests/qtest/pvpanic-pci-test.c | 94 +++++++++++++++++
133
tests/qtest/xlnx-can-test.c | 30 +++---
134
MAINTAINERS | 3 +
135
accel/hvf/entitlements.plist | 8 ++
136
hw/arm/Kconfig | 1 +
137
hw/gpio/Kconfig | 3 +
138
hw/gpio/meson.build | 1 +
139
hw/i386/Kconfig | 2 +-
140
hw/misc/Kconfig | 12 ++-
141
hw/misc/meson.build | 4 +-
142
scripts/entitlement.sh | 13 +++
143
tests/qtest/meson.build | 6 +-
144
52 files changed, 1432 insertions(+), 319 deletions(-)
145
create mode 100644 hw/gpio/gpio_pwr.c
146
create mode 100644 hw/misc/pvpanic-isa.c
147
create mode 100644 hw/misc/pvpanic-pci.c
148
create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
149
create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
150
create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
151
create mode 100644 tests/qtest/pvpanic-pci-test.c
152
create mode 100644 accel/hvf/entitlements.plist
153
create mode 100755 scripts/entitlement.sh
63
154
diff view generated by jsdifflib
1
Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
1
From: Richard Henderson <richard.henderson@linaro.org>
2
sub-struct. We're going to want id_pfr1 for an isar_features
3
check, and moving both at the same time avoids an odd
4
inconsistency.
5
2
6
Changes other than the ones to cpu.h and kvm64.c made
3
This was defined at some point before ARMv8.4, and will
7
automatically with:
4
shortly be used by new processor descriptions.
8
perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c
9
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210120204400.1056582-1-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
13
---
10
---
14
target/arm/cpu.h | 4 ++--
11
target/arm/cpu.h | 1 +
15
hw/intc/armv7m_nvic.c | 4 ++--
12
target/arm/helper.c | 4 ++--
16
target/arm/cpu.c | 20 ++++++++++----------
13
target/arm/kvm64.c | 2 ++
17
target/arm/cpu64.c | 12 ++++++------
14
3 files changed, 5 insertions(+), 2 deletions(-)
18
target/arm/cpu_tcg.c | 36 ++++++++++++++++++------------------
19
target/arm/helper.c | 4 ++--
20
target/arm/kvm64.c | 4 ++++
21
7 files changed, 44 insertions(+), 40 deletions(-)
22
15
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
18
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
20
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
28
uint32_t id_mmfr2;
29
uint32_t id_mmfr3;
30
uint32_t id_mmfr4;
21
uint32_t id_mmfr4;
31
+ uint32_t id_pfr0;
22
uint32_t id_pfr0;
32
+ uint32_t id_pfr1;
23
uint32_t id_pfr1;
24
+ uint32_t id_pfr2;
33
uint32_t mvfr0;
25
uint32_t mvfr0;
34
uint32_t mvfr1;
26
uint32_t mvfr1;
35
uint32_t mvfr2;
27
uint32_t mvfr2;
36
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
37
uint32_t reset_fpsid;
38
uint32_t ctr;
39
uint32_t reset_sctlr;
40
- uint32_t id_pfr0;
41
- uint32_t id_pfr1;
42
uint64_t pmceid0;
43
uint64_t pmceid1;
44
uint32_t id_afr0;
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
46
index XXXXXXX..XXXXXXX 100644
47
--- a/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
49
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
50
"Aux Fault status registers unimplemented\n");
51
return 0;
52
case 0xd40: /* PFR0. */
53
- return cpu->id_pfr0;
54
+ return cpu->isar.id_pfr0;
55
case 0xd44: /* PFR1. */
56
- return cpu->id_pfr1;
57
+ return cpu->isar.id_pfr1;
58
case 0xd48: /* DFR0. */
59
return cpu->isar.id_dfr0;
60
case 0xd4c: /* AFR0. */
61
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/cpu.c
64
+++ b/target/arm/cpu.c
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
66
/* Disable the security extension feature bits in the processor feature
67
* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
68
*/
69
- cpu->id_pfr1 &= ~0xf0;
70
+ cpu->isar.id_pfr1 &= ~0xf0;
71
cpu->isar.id_aa64pfr0 &= ~0xf000;
72
}
73
74
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
75
* id_aa64pfr0_el1[11:8].
76
*/
77
cpu->isar.id_aa64pfr0 &= ~0xf00;
78
- cpu->id_pfr1 &= ~0xf000;
79
+ cpu->isar.id_pfr1 &= ~0xf000;
80
}
81
82
#ifndef CONFIG_USER_ONLY
83
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
84
cpu->isar.mvfr1 = 0x00011111;
85
cpu->ctr = 0x82048004;
86
cpu->reset_sctlr = 0x00c50078;
87
- cpu->id_pfr0 = 0x1031;
88
- cpu->id_pfr1 = 0x11;
89
+ cpu->isar.id_pfr0 = 0x1031;
90
+ cpu->isar.id_pfr1 = 0x11;
91
cpu->isar.id_dfr0 = 0x400;
92
cpu->id_afr0 = 0;
93
cpu->isar.id_mmfr0 = 0x31100003;
94
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
95
cpu->isar.mvfr1 = 0x01111111;
96
cpu->ctr = 0x80038003;
97
cpu->reset_sctlr = 0x00c50078;
98
- cpu->id_pfr0 = 0x1031;
99
- cpu->id_pfr1 = 0x11;
100
+ cpu->isar.id_pfr0 = 0x1031;
101
+ cpu->isar.id_pfr1 = 0x11;
102
cpu->isar.id_dfr0 = 0x000;
103
cpu->id_afr0 = 0;
104
cpu->isar.id_mmfr0 = 0x00100103;
105
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
106
cpu->isar.mvfr1 = 0x11111111;
107
cpu->ctr = 0x84448003;
108
cpu->reset_sctlr = 0x00c50078;
109
- cpu->id_pfr0 = 0x00001131;
110
- cpu->id_pfr1 = 0x00011011;
111
+ cpu->isar.id_pfr0 = 0x00001131;
112
+ cpu->isar.id_pfr1 = 0x00011011;
113
cpu->isar.id_dfr0 = 0x02010555;
114
cpu->id_afr0 = 0x00000000;
115
cpu->isar.id_mmfr0 = 0x10101105;
116
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
117
cpu->isar.mvfr1 = 0x11111111;
118
cpu->ctr = 0x8444c004;
119
cpu->reset_sctlr = 0x00c50078;
120
- cpu->id_pfr0 = 0x00001131;
121
- cpu->id_pfr1 = 0x00011011;
122
+ cpu->isar.id_pfr0 = 0x00001131;
123
+ cpu->isar.id_pfr1 = 0x00011011;
124
cpu->isar.id_dfr0 = 0x02010555;
125
cpu->id_afr0 = 0x00000000;
126
cpu->isar.id_mmfr0 = 0x10201105;
127
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
128
index XXXXXXX..XXXXXXX 100644
129
--- a/target/arm/cpu64.c
130
+++ b/target/arm/cpu64.c
131
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
132
cpu->isar.mvfr2 = 0x00000043;
133
cpu->ctr = 0x8444c004;
134
cpu->reset_sctlr = 0x00c50838;
135
- cpu->id_pfr0 = 0x00000131;
136
- cpu->id_pfr1 = 0x00011011;
137
+ cpu->isar.id_pfr0 = 0x00000131;
138
+ cpu->isar.id_pfr1 = 0x00011011;
139
cpu->isar.id_dfr0 = 0x03010066;
140
cpu->id_afr0 = 0x00000000;
141
cpu->isar.id_mmfr0 = 0x10101105;
142
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
143
cpu->isar.mvfr2 = 0x00000043;
144
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
145
cpu->reset_sctlr = 0x00c50838;
146
- cpu->id_pfr0 = 0x00000131;
147
- cpu->id_pfr1 = 0x00011011;
148
+ cpu->isar.id_pfr0 = 0x00000131;
149
+ cpu->isar.id_pfr1 = 0x00011011;
150
cpu->isar.id_dfr0 = 0x03010066;
151
cpu->id_afr0 = 0x00000000;
152
cpu->isar.id_mmfr0 = 0x10101105;
153
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
154
cpu->isar.mvfr2 = 0x00000043;
155
cpu->ctr = 0x8444c004;
156
cpu->reset_sctlr = 0x00c50838;
157
- cpu->id_pfr0 = 0x00000131;
158
- cpu->id_pfr1 = 0x00011011;
159
+ cpu->isar.id_pfr0 = 0x00000131;
160
+ cpu->isar.id_pfr1 = 0x00011011;
161
cpu->isar.id_dfr0 = 0x03010066;
162
cpu->id_afr0 = 0x00000000;
163
cpu->isar.id_mmfr0 = 0x10201105;
164
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
165
index XXXXXXX..XXXXXXX 100644
166
--- a/target/arm/cpu_tcg.c
167
+++ b/target/arm/cpu_tcg.c
168
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
169
cpu->isar.mvfr1 = 0x00000000;
170
cpu->ctr = 0x1dd20d2;
171
cpu->reset_sctlr = 0x00050078;
172
- cpu->id_pfr0 = 0x111;
173
- cpu->id_pfr1 = 0x1;
174
+ cpu->isar.id_pfr0 = 0x111;
175
+ cpu->isar.id_pfr1 = 0x1;
176
cpu->isar.id_dfr0 = 0x2;
177
cpu->id_afr0 = 0x3;
178
cpu->isar.id_mmfr0 = 0x01130003;
179
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
180
cpu->isar.mvfr1 = 0x00000000;
181
cpu->ctr = 0x1dd20d2;
182
cpu->reset_sctlr = 0x00050078;
183
- cpu->id_pfr0 = 0x111;
184
- cpu->id_pfr1 = 0x1;
185
+ cpu->isar.id_pfr0 = 0x111;
186
+ cpu->isar.id_pfr1 = 0x1;
187
cpu->isar.id_dfr0 = 0x2;
188
cpu->id_afr0 = 0x3;
189
cpu->isar.id_mmfr0 = 0x01130003;
190
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
191
cpu->isar.mvfr1 = 0x00000000;
192
cpu->ctr = 0x1dd20d2;
193
cpu->reset_sctlr = 0x00050078;
194
- cpu->id_pfr0 = 0x111;
195
- cpu->id_pfr1 = 0x11;
196
+ cpu->isar.id_pfr0 = 0x111;
197
+ cpu->isar.id_pfr1 = 0x11;
198
cpu->isar.id_dfr0 = 0x33;
199
cpu->id_afr0 = 0;
200
cpu->isar.id_mmfr0 = 0x01130003;
201
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
202
cpu->isar.mvfr0 = 0x11111111;
203
cpu->isar.mvfr1 = 0x00000000;
204
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
205
- cpu->id_pfr0 = 0x111;
206
- cpu->id_pfr1 = 0x1;
207
+ cpu->isar.id_pfr0 = 0x111;
208
+ cpu->isar.id_pfr1 = 0x1;
209
cpu->isar.id_dfr0 = 0;
210
cpu->id_afr0 = 0x2;
211
cpu->isar.id_mmfr0 = 0x01100103;
212
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
213
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
214
cpu->midr = 0x410fc231;
215
cpu->pmsav7_dregion = 8;
216
- cpu->id_pfr0 = 0x00000030;
217
- cpu->id_pfr1 = 0x00000200;
218
+ cpu->isar.id_pfr0 = 0x00000030;
219
+ cpu->isar.id_pfr1 = 0x00000200;
220
cpu->isar.id_dfr0 = 0x00100000;
221
cpu->id_afr0 = 0x00000000;
222
cpu->isar.id_mmfr0 = 0x00000030;
223
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
224
cpu->isar.mvfr0 = 0x10110021;
225
cpu->isar.mvfr1 = 0x11000011;
226
cpu->isar.mvfr2 = 0x00000000;
227
- cpu->id_pfr0 = 0x00000030;
228
- cpu->id_pfr1 = 0x00000200;
229
+ cpu->isar.id_pfr0 = 0x00000030;
230
+ cpu->isar.id_pfr1 = 0x00000200;
231
cpu->isar.id_dfr0 = 0x00100000;
232
cpu->id_afr0 = 0x00000000;
233
cpu->isar.id_mmfr0 = 0x00000030;
234
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
235
cpu->isar.mvfr0 = 0x10110221;
236
cpu->isar.mvfr1 = 0x12000011;
237
cpu->isar.mvfr2 = 0x00000040;
238
- cpu->id_pfr0 = 0x00000030;
239
- cpu->id_pfr1 = 0x00000200;
240
+ cpu->isar.id_pfr0 = 0x00000030;
241
+ cpu->isar.id_pfr1 = 0x00000200;
242
cpu->isar.id_dfr0 = 0x00100000;
243
cpu->id_afr0 = 0x00000000;
244
cpu->isar.id_mmfr0 = 0x00100030;
245
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
246
cpu->isar.mvfr0 = 0x10110021;
247
cpu->isar.mvfr1 = 0x11000011;
248
cpu->isar.mvfr2 = 0x00000040;
249
- cpu->id_pfr0 = 0x00000030;
250
- cpu->id_pfr1 = 0x00000210;
251
+ cpu->isar.id_pfr0 = 0x00000030;
252
+ cpu->isar.id_pfr1 = 0x00000210;
253
cpu->isar.id_dfr0 = 0x00200000;
254
cpu->id_afr0 = 0x00000000;
255
cpu->isar.id_mmfr0 = 0x00101F40;
256
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
257
set_feature(&cpu->env, ARM_FEATURE_PMSA);
258
set_feature(&cpu->env, ARM_FEATURE_PMU);
259
cpu->midr = 0x411fc153; /* r1p3 */
260
- cpu->id_pfr0 = 0x0131;
261
- cpu->id_pfr1 = 0x001;
262
+ cpu->isar.id_pfr0 = 0x0131;
263
+ cpu->isar.id_pfr1 = 0x001;
264
cpu->isar.id_dfr0 = 0x010400;
265
cpu->id_afr0 = 0x0;
266
cpu->isar.id_mmfr0 = 0x0210030;
267
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
268
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
269
--- a/target/arm/helper.c
30
--- a/target/arm/helper.c
270
+++ b/target/arm/helper.c
31
+++ b/target/arm/helper.c
271
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
272
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
273
{
274
ARMCPU *cpu = env_archcpu(env);
275
- uint64_t pfr1 = cpu->id_pfr1;
276
+ uint64_t pfr1 = cpu->isar.id_pfr1;
277
278
if (env->gicv3state) {
279
pfr1 |= 1 << 28;
280
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
32
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
282
.access = PL1_R, .type = ARM_CP_CONST,
33
.access = PL1_R, .type = ARM_CP_CONST,
283
.accessfn = access_aa32_tid3,
34
.accessfn = access_aa64_tid3,
284
- .resetvalue = cpu->id_pfr0 },
35
.resetvalue = 0 },
285
+ .resetvalue = cpu->isar.id_pfr0 },
36
- { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
286
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
37
+ { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
287
* the value of the GIC field until after we define these regs.
38
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
288
*/
39
.access = PL1_R, .type = ARM_CP_CONST,
40
.accessfn = access_aa64_tid3,
41
- .resetvalue = 0 },
42
+ .resetvalue = cpu->isar.id_pfr2 },
43
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
44
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
45
.access = PL1_R, .type = ARM_CP_CONST,
289
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
46
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
290
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
291
--- a/target/arm/kvm64.c
48
--- a/target/arm/kvm64.c
292
+++ b/target/arm/kvm64.c
49
+++ b/target/arm/kvm64.c
293
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
50
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
294
* than skipping the reads and leaving 0, as we must avoid
51
ARM64_SYS_REG(3, 0, 0, 1, 0));
295
* considering the values in every case.
52
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
296
*/
53
ARM64_SYS_REG(3, 0, 0, 1, 1));
297
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
54
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
298
+ ARM64_SYS_REG(3, 0, 0, 1, 0));
55
+ ARM64_SYS_REG(3, 0, 0, 3, 4));
299
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
300
+ ARM64_SYS_REG(3, 0, 0, 1, 1));
301
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
56
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
302
ARM64_SYS_REG(3, 0, 0, 1, 2));
57
ARM64_SYS_REG(3, 0, 0, 1, 2));
303
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
58
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
304
--
59
--
305
2.20.1
60
2.20.1
306
61
307
62
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
While converting to gen_gvec_ool_zzzp, we lost passing
3
Only define the register if it exists for the cpu.
4
a->esz as the data argument to the function.
5
4
6
Fixes: 36cbb7a8e71
7
Cc: qemu-stable@nongnu.org
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org
6
Message-id: 20210120031656.737646-1-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
target/arm/translate-sve.c | 2 +-
10
target/arm/helper.c | 21 +++++++++++++++------
14
1 file changed, 1 insertion(+), 1 deletion(-)
11
1 file changed, 15 insertions(+), 6 deletions(-)
15
12
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-sve.c
15
--- a/target/arm/helper.c
19
+++ b/target/arm/translate-sve.c
16
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
17
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
21
{
18
*/
22
if (sve_access_check(s)) {
19
int i;
23
gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
20
int wrps, brps, ctx_cmps;
24
- a->rd, a->rn, a->rm, a->pg, 0);
21
- ARMCPRegInfo dbgdidr = {
25
+ a->rd, a->rn, a->rm, a->pg, a->esz);
22
- .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
26
}
23
- .access = PL0_R, .accessfn = access_tda,
27
return true;
24
- .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
28
}
25
- };
26
+
27
+ /*
28
+ * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot
29
+ * use AArch32. Given that bit 15 is RES1, if the value is 0 then
30
+ * the register must not exist for this cpu.
31
+ */
32
+ if (cpu->isar.dbgdidr != 0) {
33
+ ARMCPRegInfo dbgdidr = {
34
+ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
35
+ .opc1 = 0, .opc2 = 0,
36
+ .access = PL0_R, .accessfn = access_tda,
37
+ .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
38
+ };
39
+ define_one_arm_cp_reg(cpu, &dbgdidr);
40
+ }
41
42
/* Note that all these register fields hold "number of Xs minus 1". */
43
brps = arm_num_brps(cpu);
44
@@ -XXX,XX +XXX,XX @@ static void define_debug_regs(ARMCPU *cpu)
45
46
assert(ctx_cmps <= brps);
47
48
- define_one_arm_cp_reg(cpu, &dbgdidr);
49
define_arm_cp_regs(cpu, debug_cp_reginfo);
50
51
if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
29
--
52
--
30
2.20.1
53
2.20.1
31
54
32
55
diff view generated by jsdifflib
New patch
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
2
3
The properties to attach a CANBUS object to the xlnx-zcu102 machine have
4
a period in them. We want to use periods in properties for compound QAPI types,
5
and besides the "xlnx-zcu102." prefix is both unnecessary and different
6
from any other machine property name. Remove it.
7
8
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
9
Message-id: 20210118162537.779542-1-pbonzini@redhat.com
10
Reviewed-by: Vikram Garhwal <fnu.vikram@xilinx.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/xlnx-zcu102.c | 4 ++--
14
tests/qtest/xlnx-can-test.c | 30 +++++++++++++++---------------
15
2 files changed, 17 insertions(+), 17 deletions(-)
16
17
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/xlnx-zcu102.c
20
+++ b/hw/arm/xlnx-zcu102.c
21
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
22
s->secure = false;
23
/* Default to virt (EL2) being disabled */
24
s->virt = false;
25
- object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
26
+ object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
27
(Object **)&s->canbus[0],
28
object_property_allow_set_link,
29
0);
30
31
- object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS,
32
+ object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
33
(Object **)&s->canbus[1],
34
object_property_allow_set_link,
35
0);
36
diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/qtest/xlnx-can-test.c
39
+++ b/tests/qtest/xlnx-can-test.c
40
@@ -XXX,XX +XXX,XX @@ static void test_can_bus(void)
41
uint8_t can_timestamp = 1;
42
43
QTestState *qts = qtest_init("-machine xlnx-zcu102"
44
- " -object can-bus,id=canbus0"
45
- " -machine xlnx-zcu102.canbus0=canbus0"
46
- " -machine xlnx-zcu102.canbus1=canbus0"
47
+ " -object can-bus,id=canbus"
48
+ " -machine canbus0=canbus"
49
+ " -machine canbus1=canbus"
50
);
51
52
/* Configure the CAN0 and CAN1. */
53
@@ -XXX,XX +XXX,XX @@ static void test_can_loopback(void)
54
uint32_t status = 0;
55
56
QTestState *qts = qtest_init("-machine xlnx-zcu102"
57
- " -object can-bus,id=canbus0"
58
- " -machine xlnx-zcu102.canbus0=canbus0"
59
- " -machine xlnx-zcu102.canbus1=canbus0"
60
+ " -object can-bus,id=canbus"
61
+ " -machine canbus0=canbus"
62
+ " -machine canbus1=canbus"
63
);
64
65
/* Configure the CAN0 in loopback mode. */
66
@@ -XXX,XX +XXX,XX @@ static void test_can_filter(void)
67
uint8_t can_timestamp = 1;
68
69
QTestState *qts = qtest_init("-machine xlnx-zcu102"
70
- " -object can-bus,id=canbus0"
71
- " -machine xlnx-zcu102.canbus0=canbus0"
72
- " -machine xlnx-zcu102.canbus1=canbus0"
73
+ " -object can-bus,id=canbus"
74
+ " -machine canbus0=canbus"
75
+ " -machine canbus1=canbus"
76
);
77
78
/* Configure the CAN0 and CAN1. */
79
@@ -XXX,XX +XXX,XX @@ static void test_can_sleepmode(void)
80
uint8_t can_timestamp = 1;
81
82
QTestState *qts = qtest_init("-machine xlnx-zcu102"
83
- " -object can-bus,id=canbus0"
84
- " -machine xlnx-zcu102.canbus0=canbus0"
85
- " -machine xlnx-zcu102.canbus1=canbus0"
86
+ " -object can-bus,id=canbus"
87
+ " -machine canbus0=canbus"
88
+ " -machine canbus1=canbus"
89
);
90
91
/* Configure the CAN0. */
92
@@ -XXX,XX +XXX,XX @@ static void test_can_snoopmode(void)
93
uint8_t can_timestamp = 1;
94
95
QTestState *qts = qtest_init("-machine xlnx-zcu102"
96
- " -object can-bus,id=canbus0"
97
- " -machine xlnx-zcu102.canbus0=canbus0"
98
- " -machine xlnx-zcu102.canbus1=canbus0"
99
+ " -object can-bus,id=canbus"
100
+ " -machine canbus0=canbus"
101
+ " -machine canbus1=canbus"
102
);
103
104
/* Configure the CAN0. */
105
--
106
2.20.1
107
108
diff view generated by jsdifflib
New patch
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
1
2
3
Implement gpio-pwr driver to allow reboot and poweroff machine.
4
This is simple driver with just 2 gpios lines. Current use case
5
is to reboot and poweroff virt machine in secure mode. Secure
6
pl066 gpio chip is needed for that.
7
8
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
9
Reviewed-by: Hao Wu <wuhaotsh@google.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/gpio/gpio_pwr.c | 70 +++++++++++++++++++++++++++++++++++++++++++++
14
hw/gpio/Kconfig | 3 ++
15
hw/gpio/meson.build | 1 +
16
3 files changed, 74 insertions(+)
17
create mode 100644 hw/gpio/gpio_pwr.c
18
19
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
20
new file mode 100644
21
index XXXXXXX..XXXXXXX
22
--- /dev/null
23
+++ b/hw/gpio/gpio_pwr.c
24
@@ -XXX,XX +XXX,XX @@
25
+/*
26
+ * GPIO qemu power controller
27
+ *
28
+ * Copyright (c) 2020 Linaro Limited
29
+ *
30
+ * Author: Maxim Uvarov <maxim.uvarov@linaro.org>
31
+ *
32
+ * Virtual gpio driver which can be used on top of pl061
33
+ * to reboot and shutdown qemu virtual machine. One of use
34
+ * case is gpio driver for secure world application (ARM
35
+ * Trusted Firmware.).
36
+ *
37
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
38
+ * See the COPYING file in the top-level directory.
39
+ * SPDX-License-Identifier: GPL-2.0-or-later
40
+ */
41
+
42
+/*
43
+ * QEMU interface:
44
+ * two named input GPIO lines:
45
+ * 'reset' : when asserted, trigger system reset
46
+ * 'shutdown' : when asserted, trigger system shutdown
47
+ */
48
+
49
+#include "qemu/osdep.h"
50
+#include "hw/sysbus.h"
51
+#include "sysemu/runstate.h"
52
+
53
+#define TYPE_GPIOPWR "gpio-pwr"
54
+OBJECT_DECLARE_SIMPLE_TYPE(GPIO_PWR_State, GPIOPWR)
55
+
56
+struct GPIO_PWR_State {
57
+ SysBusDevice parent_obj;
58
+};
59
+
60
+static void gpio_pwr_reset(void *opaque, int n, int level)
61
+{
62
+ if (level) {
63
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
64
+ }
65
+}
66
+
67
+static void gpio_pwr_shutdown(void *opaque, int n, int level)
68
+{
69
+ if (level) {
70
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
71
+ }
72
+}
73
+
74
+static void gpio_pwr_init(Object *obj)
75
+{
76
+ DeviceState *dev = DEVICE(obj);
77
+
78
+ qdev_init_gpio_in_named(dev, gpio_pwr_reset, "reset", 1);
79
+ qdev_init_gpio_in_named(dev, gpio_pwr_shutdown, "shutdown", 1);
80
+}
81
+
82
+static const TypeInfo gpio_pwr_info = {
83
+ .name = TYPE_GPIOPWR,
84
+ .parent = TYPE_SYS_BUS_DEVICE,
85
+ .instance_size = sizeof(GPIO_PWR_State),
86
+ .instance_init = gpio_pwr_init,
87
+};
88
+
89
+static void gpio_pwr_register_types(void)
90
+{
91
+ type_register_static(&gpio_pwr_info);
92
+}
93
+
94
+type_init(gpio_pwr_register_types)
95
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/gpio/Kconfig
98
+++ b/hw/gpio/Kconfig
99
@@ -XXX,XX +XXX,XX @@ config PL061
100
config GPIO_KEY
101
bool
102
103
+config GPIO_PWR
104
+ bool
105
+
106
config SIFIVE_GPIO
107
bool
108
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/gpio/meson.build
111
+++ b/hw/gpio/meson.build
112
@@ -XXX,XX +XXX,XX @@
113
softmmu_ss.add(when: 'CONFIG_E500', if_true: files('mpc8xxx.c'))
114
softmmu_ss.add(when: 'CONFIG_GPIO_KEY', if_true: files('gpio_key.c'))
115
+softmmu_ss.add(when: 'CONFIG_GPIO_PWR', if_true: files('gpio_pwr.c'))
116
softmmu_ss.add(when: 'CONFIG_MAX7310', if_true: files('max7310.c'))
117
softmmu_ss.add(when: 'CONFIG_PL061', if_true: files('pl061.c'))
118
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_gpio.c'))
119
--
120
2.20.1
121
122
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
The firmware load address depends on the SoC ("processor id") used,
3
No functional change. Just refactor code to better
4
not on the version of the board.
4
support secure and normal world gpios.
5
5
6
Suggested-by: Luc Michel <luc.michel@greensocs.com>
6
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200924111808.77168-8-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
hw/arm/raspi.c | 3 ++-
10
hw/arm/virt.c | 57 ++++++++++++++++++++++++++++++++-------------------
13
1 file changed, 2 insertions(+), 1 deletion(-)
11
1 file changed, 36 insertions(+), 21 deletions(-)
14
12
15
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
13
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/raspi.c
15
--- a/hw/arm/virt.c
18
+++ b/hw/arm/raspi.c
16
+++ b/hw/arm/virt.c
19
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
17
@@ -XXX,XX +XXX,XX @@ static void virt_powerdown_req(Notifier *n, void *opaque)
20
* the normal Linux boot process
18
}
21
*/
19
}
22
if (machine->firmware) {
20
23
- hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
21
-static void create_gpio(const VirtMachineState *vms)
24
+ hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836
22
+static void create_gpio_keys(const VirtMachineState *vms,
25
+ ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3;
23
+ DeviceState *pl061_dev,
26
/* load the firmware image (typically kernel.img) */
24
+ uint32_t phandle)
27
r = load_image_targphys(machine->firmware, firmware_addr,
25
+{
28
ram_size - firmware_addr);
26
+ gpio_key_dev = sysbus_create_simple("gpio-key", -1,
27
+ qdev_get_gpio_in(pl061_dev, 3));
28
+
29
+ qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
30
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
31
+ qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
32
+ qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
33
+
34
+ qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
35
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
36
+ "label", "GPIO Key Poweroff");
37
+ qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
38
+ KEY_POWER);
39
+ qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
40
+ "gpios", phandle, 3, 0);
41
+}
42
+
43
+static void create_gpio_devices(const VirtMachineState *vms, int gpio,
44
+ MemoryRegion *mem)
45
{
46
char *nodename;
47
DeviceState *pl061_dev;
48
- hwaddr base = vms->memmap[VIRT_GPIO].base;
49
- hwaddr size = vms->memmap[VIRT_GPIO].size;
50
- int irq = vms->irqmap[VIRT_GPIO];
51
+ hwaddr base = vms->memmap[gpio].base;
52
+ hwaddr size = vms->memmap[gpio].size;
53
+ int irq = vms->irqmap[gpio];
54
const char compat[] = "arm,pl061\0arm,primecell";
55
+ SysBusDevice *s;
56
57
- pl061_dev = sysbus_create_simple("pl061", base,
58
- qdev_get_gpio_in(vms->gic, irq));
59
+ pl061_dev = qdev_new("pl061");
60
+ s = SYS_BUS_DEVICE(pl061_dev);
61
+ sysbus_realize_and_unref(s, &error_fatal);
62
+ memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
63
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
64
65
uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
66
nodename = g_strdup_printf("/pl061@%" PRIx64, base);
67
@@ -XXX,XX +XXX,XX @@ static void create_gpio(const VirtMachineState *vms)
68
qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
69
qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
70
71
- gpio_key_dev = sysbus_create_simple("gpio-key", -1,
72
- qdev_get_gpio_in(pl061_dev, 3));
73
- qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
74
- qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
75
- qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
76
- qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
77
-
78
- qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
79
- qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
80
- "label", "GPIO Key Poweroff");
81
- qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
82
- KEY_POWER);
83
- qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
84
- "gpios", phandle, 3, 0);
85
g_free(nodename);
86
+
87
+ /* Child gpio devices */
88
+ create_gpio_keys(vms, pl061_dev, phandle);
89
}
90
91
static void create_virtio_devices(const VirtMachineState *vms)
92
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
93
if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
94
vms->acpi_dev = create_acpi_ged(vms);
95
} else {
96
- create_gpio(vms);
97
+ create_gpio_devices(vms, VIRT_GPIO, sysmem);
98
}
99
100
/* connect powerdown request */
29
--
101
--
30
2.20.1
102
2.20.1
31
103
32
104
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
Commit 1c3db49d39 added the raspi3, which uses the same peripherals
3
Add secure pl061 for reset/power down machine from
4
than the raspi2 (but with different ARM cores). The raspi3 was
4
the secure world (Arm Trusted Firmware). Connect it
5
introduced without the ignore_memory_transaction_failures flag.
5
with gpio-pwr driver.
6
Almost 2 years later, the machine is usable running U-Boot and
7
Linux.
8
In commit 00cbd5bd74 we mapped a lot of unimplemented devices,
9
commit d442d95f added thermal block and commit 0e5bbd7406 the
10
system timer.
11
As we are happy with the raspi3, let's remove this flag on the
12
raspi2.
13
6
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
15
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
8
Reviewed-by: Andrew Jones <drjones@redhat.com>
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
[PMM: Added mention of the new device to the documentation]
17
Message-id: 20200921034729.432931-4-f4bug@amsat.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
11
---
20
hw/arm/raspi.c | 3 ---
12
docs/system/arm/virt.rst | 2 ++
21
1 file changed, 3 deletions(-)
13
include/hw/arm/virt.h | 2 ++
14
hw/arm/virt.c | 56 +++++++++++++++++++++++++++++++++++++++-
15
hw/arm/Kconfig | 1 +
16
4 files changed, 60 insertions(+), 1 deletion(-)
22
17
23
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
18
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
24
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/raspi.c
20
--- a/docs/system/arm/virt.rst
26
+++ b/hw/arm/raspi.c
21
+++ b/docs/system/arm/virt.rst
27
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
22
@@ -XXX,XX +XXX,XX @@ The virt board supports:
28
mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
23
- Secure-World-only devices if the CPU has TrustZone:
29
mc->default_ram_size = board_ram_size(board_rev);
24
30
mc->default_ram_id = "ram";
25
- A second PL011 UART
31
- if (board_version(board_rev) == 2) {
26
+ - A second PL061 GPIO controller, with GPIO lines for triggering
32
- mc->ignore_memory_transaction_failures = true;
27
+ a system reset or system poweroff
33
- }
28
- A secure flash memory
29
- 16MB of secure RAM
30
31
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/virt.h
34
+++ b/include/hw/arm/virt.h
35
@@ -XXX,XX +XXX,XX @@ enum {
36
VIRT_GPIO,
37
VIRT_SECURE_UART,
38
VIRT_SECURE_MEM,
39
+ VIRT_SECURE_GPIO,
40
VIRT_PCDIMM_ACPI,
41
VIRT_ACPI_GED,
42
VIRT_NVDIMM_ACPI,
43
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
44
bool kvm_no_adjvtime;
45
bool no_kvm_steal_time;
46
bool acpi_expose_flash;
47
+ bool no_secure_gpio;
34
};
48
};
35
49
36
static const TypeInfo raspi_machine_types[] = {
50
struct VirtMachineState {
51
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/virt.c
54
+++ b/hw/arm/virt.c
55
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
56
[VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
57
[VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
58
[VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
59
+ [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
60
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
61
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
62
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
63
@@ -XXX,XX +XXX,XX @@ static void create_gpio_keys(const VirtMachineState *vms,
64
"gpios", phandle, 3, 0);
65
}
66
67
+#define SECURE_GPIO_POWEROFF 0
68
+#define SECURE_GPIO_RESET 1
69
+
70
+static void create_secure_gpio_pwr(const VirtMachineState *vms,
71
+ DeviceState *pl061_dev,
72
+ uint32_t phandle)
73
+{
74
+ DeviceState *gpio_pwr_dev;
75
+
76
+ /* gpio-pwr */
77
+ gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
78
+
79
+ /* connect secure pl061 to gpio-pwr */
80
+ qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
81
+ qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
82
+ qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
83
+ qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
84
+
85
+ qemu_fdt_add_subnode(vms->fdt, "/gpio-poweroff");
86
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "compatible",
87
+ "gpio-poweroff");
88
+ qemu_fdt_setprop_cells(vms->fdt, "/gpio-poweroff",
89
+ "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
90
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "status", "disabled");
91
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-poweroff", "secure-status",
92
+ "okay");
93
+
94
+ qemu_fdt_add_subnode(vms->fdt, "/gpio-restart");
95
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "compatible",
96
+ "gpio-restart");
97
+ qemu_fdt_setprop_cells(vms->fdt, "/gpio-restart",
98
+ "gpios", phandle, SECURE_GPIO_RESET, 0);
99
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "status", "disabled");
100
+ qemu_fdt_setprop_string(vms->fdt, "/gpio-restart", "secure-status",
101
+ "okay");
102
+}
103
+
104
static void create_gpio_devices(const VirtMachineState *vms, int gpio,
105
MemoryRegion *mem)
106
{
107
@@ -XXX,XX +XXX,XX @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
108
qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
109
qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
110
111
+ if (gpio != VIRT_GPIO) {
112
+ /* Mark as not usable by the normal world */
113
+ qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
114
+ qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
115
+ }
116
g_free(nodename);
117
118
/* Child gpio devices */
119
- create_gpio_keys(vms, pl061_dev, phandle);
120
+ if (gpio == VIRT_GPIO) {
121
+ create_gpio_keys(vms, pl061_dev, phandle);
122
+ } else {
123
+ create_secure_gpio_pwr(vms, pl061_dev, phandle);
124
+ }
125
}
126
127
static void create_virtio_devices(const VirtMachineState *vms)
128
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
129
create_gpio_devices(vms, VIRT_GPIO, sysmem);
130
}
131
132
+ if (vms->secure && !vmc->no_secure_gpio) {
133
+ create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
134
+ }
135
+
136
/* connect powerdown request */
137
vms->powerdown_notifier.notify = virt_powerdown_req;
138
qemu_register_powerdown_notifier(&vms->powerdown_notifier);
139
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 0)
140
141
static void virt_machine_5_2_options(MachineClass *mc)
142
{
143
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
144
+
145
virt_machine_6_0_options(mc);
146
compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
147
+ vmc->no_secure_gpio = true;
148
}
149
DEFINE_VIRT_MACHINE(5, 2)
150
151
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
152
index XXXXXXX..XXXXXXX 100644
153
--- a/hw/arm/Kconfig
154
+++ b/hw/arm/Kconfig
155
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
156
select PL011 # UART
157
select PL031 # RTC
158
select PL061 # GPIO
159
+ select GPIO_PWR
160
select PLATFORM_BUS
161
select SMBIOS
162
select VIRTIO_MMIO
37
--
163
--
38
2.20.1
164
2.20.1
39
165
40
166
diff view generated by jsdifflib
New patch
1
From: Hao Wu <wuhaotsh@google.com>
1
2
3
Fix potential overflow problem when calculating pwm_duty.
4
1. Ensure p->cmr and p->cnr to be from [0,65535], according to the
5
hardware specification.
6
2. Changed duty to uint32_t. However, since MAX_DUTY * (p->cmr+1)
7
can excceed UINT32_MAX, we convert them to uint64_t in computation
8
and converted them back to uint32_t.
9
(duty is guaranteed to be <= MAX_DUTY so it won't overflow.)
10
11
Fixes: CID 1442342
12
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Doug Evans <dje@google.com>
14
Signed-off-by: Hao Wu <wuhaotsh@google.com>
15
Message-id: 20210127011142.2122790-1-wuhaotsh@google.com
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
hw/misc/npcm7xx_pwm.c | 23 +++++++++++++++++++----
20
tests/qtest/npcm7xx_pwm-test.c | 4 ++--
21
2 files changed, 21 insertions(+), 6 deletions(-)
22
23
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/misc/npcm7xx_pwm.c
26
+++ b/hw/misc/npcm7xx_pwm.c
27
@@ -XXX,XX +XXX,XX @@ REG32(NPCM7XX_PWM_PWDR3, 0x50);
28
#define NPCM7XX_CH_INV BIT(2)
29
#define NPCM7XX_CH_MOD BIT(3)
30
31
+#define NPCM7XX_MAX_CMR 65535
32
+#define NPCM7XX_MAX_CNR 65535
33
+
34
/* Offset of each PWM channel's prescaler in the PPR register. */
35
static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
36
/* Offset of each PWM channel's clock selector in the CSR register. */
37
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
38
39
static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
40
{
41
- uint64_t duty;
42
+ uint32_t duty;
43
44
if (p->running) {
45
if (p->cnr == 0) {
46
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
47
} else if (p->cmr >= p->cnr) {
48
duty = NPCM7XX_PWM_MAX_DUTY;
49
} else {
50
- duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
51
+ duty = (uint64_t)NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
52
}
53
} else {
54
duty = 0;
55
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
56
case A_NPCM7XX_PWM_CNR2:
57
case A_NPCM7XX_PWM_CNR3:
58
p = &s->pwm[npcm7xx_cnr_index(offset)];
59
- p->cnr = value;
60
+ if (value > NPCM7XX_MAX_CNR) {
61
+ qemu_log_mask(LOG_GUEST_ERROR,
62
+ "%s: invalid cnr value: %u", __func__, value);
63
+ p->cnr = NPCM7XX_MAX_CNR;
64
+ } else {
65
+ p->cnr = value;
66
+ }
67
npcm7xx_pwm_update_output(p);
68
break;
69
70
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
71
case A_NPCM7XX_PWM_CMR2:
72
case A_NPCM7XX_PWM_CMR3:
73
p = &s->pwm[npcm7xx_cmr_index(offset)];
74
- p->cmr = value;
75
+ if (value > NPCM7XX_MAX_CMR) {
76
+ qemu_log_mask(LOG_GUEST_ERROR,
77
+ "%s: invalid cmr value: %u", __func__, value);
78
+ p->cmr = NPCM7XX_MAX_CMR;
79
+ } else {
80
+ p->cmr = value;
81
+ }
82
npcm7xx_pwm_update_output(p);
83
break;
84
85
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/tests/qtest/npcm7xx_pwm-test.c
88
+++ b/tests/qtest/npcm7xx_pwm-test.c
89
@@ -XXX,XX +XXX,XX @@ static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
90
91
static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
92
{
93
- uint64_t duty;
94
+ uint32_t duty;
95
96
if (cnr == 0) {
97
/* PWM is stopped. */
98
@@ -XXX,XX +XXX,XX @@ static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
99
} else if (cmr >= cnr) {
100
duty = MAX_DUTY;
101
} else {
102
- duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
103
+ duty = (uint64_t)MAX_DUTY * (cmr + 1) / (cnr + 1);
104
}
105
106
if (inverted) {
107
--
108
2.20.1
109
110
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Display the board revision in the machine description.
3
cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type.
4
4
5
Before:
6
7
$ qemu-system-aarch64 -M help | fgrep raspi
8
raspi2 Raspberry Pi 2B
9
raspi3 Raspberry Pi 3B
10
11
After:
12
13
raspi2 Raspberry Pi 2B (revision 1.1)
14
raspi3 Raspberry Pi 3B (revision 1.2)
15
16
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200924111808.77168-2-f4bug@amsat.org
6
Message-id: 20210127232822.3530782-1-f4bug@amsat.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
9
---
21
hw/arm/raspi.c | 4 +++-
10
target/arm/helper.c | 2 +-
22
1 file changed, 3 insertions(+), 1 deletion(-)
11
1 file changed, 1 insertion(+), 1 deletion(-)
23
12
24
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/raspi.c
15
--- a/target/arm/helper.c
27
+++ b/hw/arm/raspi.c
16
+++ b/target/arm/helper.c
28
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
17
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
29
uint32_t board_rev = (uint32_t)(uintptr_t)data;
18
30
19
*attrs = (MemTxAttrs) {};
31
rmc->board_rev = board_rev;
20
32
- mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
21
- ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr,
33
+ mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
22
+ ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr,
34
+ board_type(board_rev),
23
attrs, &prot, &page_size, &fi, &cacheattrs);
35
+ FIELD_EX32(board_rev, REV_CODE, REVISION));
24
36
mc->init = raspi_machine_init;
25
if (ret) {
37
mc->block_default_type = IF_SD;
38
mc->no_parallel = 1;
39
--
26
--
40
2.20.1
27
2.20.1
41
28
42
29
diff view generated by jsdifflib
New patch
1
Move the preadv availability check to meson.build. This is what we
2
want to be doing for host-OS-feature-checks anyway, but it also fixes
3
a problem with building for macOS with the most recent XCode SDK on a
4
Catalina host.
1
5
6
On that configuration, 'preadv()' is provided as a weak symbol, so
7
that programs can be built with optional support for it and make a
8
runtime availability check to see whether the preadv() they have is a
9
working one or one which they must not call because it will
10
runtime-assert. QEMU's configure test passes (unless you're building
11
with --enable-werror) because the test program using preadv()
12
compiles, but then QEMU crashes at runtime when preadv() is called,
13
with errors like:
14
15
dyld: lazy symbol binding failed: Symbol not found: _preadv
16
Referenced from: /Users/pm215/src/qemu/./build/x86/tests/test-replication
17
Expected in: /usr/lib/libSystem.B.dylib
18
19
dyld: Symbol not found: _preadv
20
Referenced from: /Users/pm215/src/qemu/./build/x86/tests/test-replication
21
Expected in: /usr/lib/libSystem.B.dylib
22
23
Meson's own function availability check has a special case for macOS
24
which adds '-Wl,-no_weak_imports' to the compiler flags, which forces
25
the test to require the real function, not the macOS-version-too-old
26
stub.
27
28
So this commit fixes the bug where macOS builds on Catalina currently
29
require --disable-werror.
30
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
33
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
34
Message-id: 20210126155846.17109-1-peter.maydell@linaro.org
35
---
36
configure | 16 ----------------
37
meson.build | 4 +++-
38
2 files changed, 3 insertions(+), 17 deletions(-)
39
40
diff --git a/configure b/configure
41
index XXXXXXX..XXXXXXX 100755
42
--- a/configure
43
+++ b/configure
44
@@ -XXX,XX +XXX,XX @@ if compile_prog "" "" ; then
45
iovec=yes
46
fi
47
48
-##########################################
49
-# preadv probe
50
-cat > $TMPC <<EOF
51
-#include <sys/types.h>
52
-#include <sys/uio.h>
53
-#include <unistd.h>
54
-int main(void) { return preadv(0, 0, 0, 0); }
55
-EOF
56
-preadv=no
57
-if compile_prog "" "" ; then
58
- preadv=yes
59
-fi
60
-
61
##########################################
62
# fdt probe
63
64
@@ -XXX,XX +XXX,XX @@ fi
65
if test "$iovec" = "yes" ; then
66
echo "CONFIG_IOVEC=y" >> $config_host_mak
67
fi
68
-if test "$preadv" = "yes" ; then
69
- echo "CONFIG_PREADV=y" >> $config_host_mak
70
-fi
71
if test "$membarrier" = "yes" ; then
72
echo "CONFIG_MEMBARRIER=y" >> $config_host_mak
73
fi
74
diff --git a/meson.build b/meson.build
75
index XXXXXXX..XXXXXXX 100644
76
--- a/meson.build
77
+++ b/meson.build
78
@@ -XXX,XX +XXX,XX @@ config_host_data.set('HAVE_PTY_H', cc.has_header('pty.h'))
79
config_host_data.set('HAVE_SYS_IOCCOM_H', cc.has_header('sys/ioccom.h'))
80
config_host_data.set('HAVE_SYS_KCOV_H', cc.has_header('sys/kcov.h'))
81
82
+config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))
83
+
84
ignored = ['CONFIG_QEMU_INTERP_PREFIX'] # actually per-target
85
arrays = ['CONFIG_AUDIO_DRIVERS', 'CONFIG_BDRV_RW_WHITELIST', 'CONFIG_BDRV_RO_WHITELIST']
86
strings = ['HOST_DSOSUF', 'CONFIG_IASL']
87
@@ -XXX,XX +XXX,XX @@ summary_info += {'PIE': get_option('b_pie')}
88
summary_info += {'static build': config_host.has_key('CONFIG_STATIC')}
89
summary_info += {'malloc trim support': has_malloc_trim}
90
summary_info += {'membarrier': config_host.has_key('CONFIG_MEMBARRIER')}
91
-summary_info += {'preadv support': config_host.has_key('CONFIG_PREADV')}
92
+summary_info += {'preadv support': config_host_data.get('CONFIG_PREADV')}
93
summary_info += {'fdatasync': config_host.has_key('CONFIG_FDATASYNC')}
94
summary_info += {'madvise': config_host.has_key('CONFIG_MADVISE')}
95
summary_info += {'posix_madvise': config_host.has_key('CONFIG_POSIX_MADVISE')}
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
New patch
1
From: Joelle van Dyne <j@getutm.app>
1
2
3
The iOS toolchain does not use the host prefix naming convention. So we
4
need to enable cross-compile options while allowing the PREFIX to be
5
blank.
6
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Signed-off-by: Joelle van Dyne <j@getutm.app>
9
Message-id: 20210126012457.39046-3-j@getutm.app
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
configure | 6 ++++--
13
1 file changed, 4 insertions(+), 2 deletions(-)
14
15
diff --git a/configure b/configure
16
index XXXXXXX..XXXXXXX 100755
17
--- a/configure
18
+++ b/configure
19
@@ -XXX,XX +XXX,XX @@ cpu=""
20
iasl="iasl"
21
interp_prefix="/usr/gnemul/qemu-%M"
22
static="no"
23
+cross_compile="no"
24
cross_prefix=""
25
audio_drv_list=""
26
block_drv_rw_whitelist=""
27
@@ -XXX,XX +XXX,XX @@ for opt do
28
optarg=$(expr "x$opt" : 'x[^=]*=\(.*\)')
29
case "$opt" in
30
--cross-prefix=*) cross_prefix="$optarg"
31
+ cross_compile="yes"
32
;;
33
--cc=*) CC="$optarg"
34
;;
35
@@ -XXX,XX +XXX,XX @@ $(echo Deprecated targets: $deprecated_targets_list | \
36
--target-list-exclude=LIST exclude a set of targets from the default target-list
37
38
Advanced options (experts only):
39
- --cross-prefix=PREFIX use PREFIX for compile tools [$cross_prefix]
40
+ --cross-prefix=PREFIX use PREFIX for compile tools, PREFIX can be blank [$cross_prefix]
41
--cc=CC use C compiler CC [$cc]
42
--iasl=IASL use ACPI compiler IASL [$iasl]
43
--host-cc=CC use C compiler CC [$host_cc] for code run at
44
@@ -XXX,XX +XXX,XX @@ if has $sdl2_config; then
45
fi
46
echo "strip = [$(meson_quote $strip)]" >> $cross
47
echo "windres = [$(meson_quote $windres)]" >> $cross
48
-if test -n "$cross_prefix"; then
49
+if test "$cross_compile" = "yes"; then
50
cross_arg="--cross-file config-meson.cross"
51
echo "[host_machine]" >> $cross
52
if test "$mingw32" = "yes" ; then
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Joelle van Dyne <j@getutm.app>
2
2
3
Now that we can instantiate different machines based on their
3
Build without error on hosts without a working system(). If system()
4
board_rev register value, we can have various raspi2 and raspi3.
4
is called, return -1 with ENOSYS.
5
5
6
In commit fc78a990ec103 we corrected the machine description.
6
Signed-off-by: Joelle van Dyne <j@getutm.app>
7
Correct the machine names too. For backward compatibility, add
7
Message-id: 20210126012457.39046-6-j@getutm.app
8
an alias to the previous generic name.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
10
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20200924111808.77168-6-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
hw/arm/raspi.c | 6 ++++--
11
meson.build | 1 +
16
1 file changed, 4 insertions(+), 2 deletions(-)
12
include/qemu/osdep.h | 12 ++++++++++++
13
2 files changed, 13 insertions(+)
17
14
18
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
15
diff --git a/meson.build b/meson.build
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/raspi.c
17
--- a/meson.build
21
+++ b/hw/arm/raspi.c
18
+++ b/meson.build
22
@@ -XXX,XX +XXX,XX @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
19
@@ -XXX,XX +XXX,XX @@ config_host_data.set('HAVE_DRM_H', cc.has_header('libdrm/drm.h'))
23
MachineClass *mc = MACHINE_CLASS(oc);
20
config_host_data.set('HAVE_PTY_H', cc.has_header('pty.h'))
24
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
21
config_host_data.set('HAVE_SYS_IOCCOM_H', cc.has_header('sys/ioccom.h'))
25
22
config_host_data.set('HAVE_SYS_KCOV_H', cc.has_header('sys/kcov.h'))
26
+ mc->alias = "raspi2";
23
+config_host_data.set('HAVE_SYSTEM_FUNCTION', cc.has_function('system', prefix: '#include <stdlib.h>'))
27
rmc->board_rev = 0xa21041;
24
28
raspi_machine_class_common_init(mc, rmc->board_rev);
25
config_host_data.set('CONFIG_PREADV', cc.has_function('preadv', prefix: '#include <sys/uio.h>'))
29
};
26
30
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
27
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
31
MachineClass *mc = MACHINE_CLASS(oc);
28
index XXXXXXX..XXXXXXX 100644
32
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
29
--- a/include/qemu/osdep.h
33
30
+++ b/include/qemu/osdep.h
34
+ mc->alias = "raspi3";
31
@@ -XXX,XX +XXX,XX @@ static inline void qemu_thread_jit_write(void) {}
35
rmc->board_rev = 0xa02082;
32
static inline void qemu_thread_jit_execute(void) {}
36
raspi_machine_class_common_init(mc, rmc->board_rev);
33
#endif
37
};
34
38
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
35
+/**
39
36
+ * Platforms which do not support system() return ENOSYS
40
static const TypeInfo raspi_machine_types[] = {
37
+ */
41
{
38
+#ifndef HAVE_SYSTEM_FUNCTION
42
- .name = MACHINE_TYPE_NAME("raspi2"),
39
+#define system platform_does_not_support_system
43
+ .name = MACHINE_TYPE_NAME("raspi2b"),
40
+static inline int platform_does_not_support_system(const char *command)
44
.parent = TYPE_RASPI_MACHINE,
41
+{
45
.class_init = raspi2b_machine_class_init,
42
+ errno = ENOSYS;
46
#ifdef TARGET_AARCH64
43
+ return -1;
47
}, {
44
+}
48
- .name = MACHINE_TYPE_NAME("raspi3"),
45
+#endif /* !HAVE_SYSTEM_FUNCTION */
49
+ .name = MACHINE_TYPE_NAME("raspi3b"),
46
+
50
.parent = TYPE_RASPI_MACHINE,
51
.class_init = raspi3b_machine_class_init,
52
#endif
47
#endif
53
--
48
--
54
2.20.1
49
2.20.1
55
50
56
51
diff view generated by jsdifflib
New patch
1
From: Joelle van Dyne <j@getutm.app>
1
2
3
Meson will find CoreFoundation, IOKit, and Cocoa as needed.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Joelle van Dyne <j@getutm.app>
7
Message-id: 20210126012457.39046-7-j@getutm.app
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
configure | 1 -
11
1 file changed, 1 deletion(-)
12
13
diff --git a/configure b/configure
14
index XXXXXXX..XXXXXXX 100755
15
--- a/configure
16
+++ b/configure
17
@@ -XXX,XX +XXX,XX @@ Darwin)
18
fi
19
audio_drv_list="coreaudio try-sdl"
20
audio_possible_drivers="coreaudio sdl"
21
- QEMU_LDFLAGS="-framework CoreFoundation -framework IOKit $QEMU_LDFLAGS"
22
# Disable attempts to use ObjectiveC features in os/object.h since they
23
# won't work when we're compiling with gcc as a C compiler.
24
QEMU_CFLAGS="-DOS_OBJECT_USE_OBJC=0 $QEMU_CFLAGS"
25
--
26
2.20.1
27
28
diff view generated by jsdifflib
New patch
1
From: Joelle van Dyne <j@getutm.app>
1
2
3
Add objc to the Meson cross file as well as detection of Darwin.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Joelle van Dyne <j@getutm.app>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210126012457.39046-8-j@getutm.app
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
configure | 4 ++++
12
1 file changed, 4 insertions(+)
13
14
diff --git a/configure b/configure
15
index XXXXXXX..XXXXXXX 100755
16
--- a/configure
17
+++ b/configure
18
@@ -XXX,XX +XXX,XX @@ echo "cpp_link_args = [${LDFLAGS:+$(meson_quote $LDFLAGS)}]" >> $cross
19
echo "[binaries]" >> $cross
20
echo "c = [$(meson_quote $cc)]" >> $cross
21
test -n "$cxx" && echo "cpp = [$(meson_quote $cxx)]" >> $cross
22
+test -n "$objcc" && echo "objc = [$(meson_quote $objcc)]" >> $cross
23
echo "ar = [$(meson_quote $ar)]" >> $cross
24
echo "nm = [$(meson_quote $nm)]" >> $cross
25
echo "pkgconfig = [$(meson_quote $pkg_config_exe)]" >> $cross
26
@@ -XXX,XX +XXX,XX @@ if test "$cross_compile" = "yes"; then
27
if test "$linux" = "yes" ; then
28
echo "system = 'linux'" >> $cross
29
fi
30
+ if test "$darwin" = "yes" ; then
31
+ echo "system = 'darwin'" >> $cross
32
+ fi
33
case "$ARCH" in
34
i386|x86_64)
35
echo "cpu_family = 'x86'" >> $cross
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
New patch
1
From: Joelle van Dyne <j@getutm.app>
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Signed-off-by: Joelle van Dyne <j@getutm.app>
5
Message-id: 20210126012457.39046-9-j@getutm.app
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
configure | 5 ++++-
9
1 file changed, 4 insertions(+), 1 deletion(-)
10
11
diff --git a/configure b/configure
12
index XXXXXXX..XXXXXXX 100755
13
--- a/configure
14
+++ b/configure
15
@@ -XXX,XX +XXX,XX @@ if test "$cross_compile" = "yes"; then
16
echo "system = 'darwin'" >> $cross
17
fi
18
case "$ARCH" in
19
- i386|x86_64)
20
+ i386)
21
echo "cpu_family = 'x86'" >> $cross
22
;;
23
+ x86_64)
24
+ echo "cpu_family = 'x86_64'" >> $cross
25
+ ;;
26
ppc64le)
27
echo "cpu_family = 'ppc64'" >> $cross
28
;;
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
New patch
1
From: Joelle van Dyne <j@getutm.app>
1
2
3
On iOS there is no CoreAudio, so we should not assume Darwin always
4
has it.
5
6
Signed-off-by: Joelle van Dyne <j@getutm.app>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210126012457.39046-11-j@getutm.app
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
configure | 35 +++++++++++++++++++++++++++++++++--
12
1 file changed, 33 insertions(+), 2 deletions(-)
13
14
diff --git a/configure b/configure
15
index XXXXXXX..XXXXXXX 100755
16
--- a/configure
17
+++ b/configure
18
@@ -XXX,XX +XXX,XX @@ fdt="auto"
19
netmap="no"
20
sdl="auto"
21
sdl_image="auto"
22
+coreaudio="auto"
23
virtiofsd="auto"
24
virtfs="auto"
25
libudev="auto"
26
@@ -XXX,XX +XXX,XX @@ Darwin)
27
QEMU_CFLAGS="-arch x86_64 $QEMU_CFLAGS"
28
QEMU_LDFLAGS="-arch x86_64 $QEMU_LDFLAGS"
29
fi
30
- audio_drv_list="coreaudio try-sdl"
31
+ audio_drv_list="try-coreaudio try-sdl"
32
audio_possible_drivers="coreaudio sdl"
33
# Disable attempts to use ObjectiveC features in os/object.h since they
34
# won't work when we're compiling with gcc as a C compiler.
35
@@ -XXX,XX +XXX,XX @@ EOF
36
fi
37
fi
38
39
+##########################################
40
+# detect CoreAudio
41
+if test "$coreaudio" != "no" ; then
42
+ coreaudio_libs="-framework CoreAudio"
43
+ cat > $TMPC << EOF
44
+#include <CoreAudio/CoreAudio.h>
45
+int main(void)
46
+{
47
+ return (int)AudioGetCurrentHostTime();
48
+}
49
+EOF
50
+ if compile_prog "" "$coreaudio_libs" ; then
51
+ coreaudio=yes
52
+ else
53
+ coreaudio=no
54
+ fi
55
+fi
56
+
57
##########################################
58
# Sound support libraries probe
59
60
@@ -XXX,XX +XXX,XX @@ for drv in $audio_drv_list; do
61
fi
62
;;
63
64
- coreaudio)
65
+ coreaudio | try-coreaudio)
66
+ if test "$coreaudio" = "no"; then
67
+ if test "$drv" = "try-coreaudio"; then
68
+ audio_drv_list=$(echo "$audio_drv_list" | sed -e 's/try-coreaudio//')
69
+ else
70
+ error_exit "$drv check failed" \
71
+ "Make sure to have the $drv is available."
72
+ fi
73
+ else
74
coreaudio_libs="-framework CoreAudio"
75
+ if test "$drv" = "try-coreaudio"; then
76
+ audio_drv_list=$(echo "$audio_drv_list" | sed -e 's/try-coreaudio/coreaudio/')
77
+ fi
78
+ fi
79
;;
80
81
dsound)
82
--
83
2.20.1
84
85
diff view generated by jsdifflib
New patch
1
From: Joelle van Dyne <j@getutm.app>
1
2
3
A workaround added in early days of 64-bit OSX forced x86_64 if the
4
host machine had 64-bit support. This creates issues when cross-
5
compiling for ARM64. Additionally, the user can always use --cpu=* to
6
manually set the host CPU and therefore this workaround should be
7
removed.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Joelle van Dyne <j@getutm.app>
11
Message-id: 20210126012457.39046-12-j@getutm.app
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
configure | 11 -----------
15
1 file changed, 11 deletions(-)
16
17
diff --git a/configure b/configure
18
index XXXXXXX..XXXXXXX 100755
19
--- a/configure
20
+++ b/configure
21
@@ -XXX,XX +XXX,XX @@ fi
22
# the correct CPU with the --cpu option.
23
case $targetos in
24
Darwin)
25
- # on Leopard most of the system is 32-bit, so we have to ask the kernel if we can
26
- # run 64-bit userspace code.
27
- # If the user didn't specify a CPU explicitly and the kernel says this is
28
- # 64 bit hw, then assume x86_64. Otherwise fall through to the usual detection code.
29
- if test -z "$cpu" && test "$(sysctl -n hw.optional.x86_64)" = "1"; then
30
- cpu="x86_64"
31
- fi
32
HOST_DSOSUF=".dylib"
33
;;
34
SunOS)
35
@@ -XXX,XX +XXX,XX @@ OpenBSD)
36
Darwin)
37
bsd="yes"
38
darwin="yes"
39
- if [ "$cpu" = "x86_64" ] ; then
40
- QEMU_CFLAGS="-arch x86_64 $QEMU_CFLAGS"
41
- QEMU_LDFLAGS="-arch x86_64 $QEMU_LDFLAGS"
42
- fi
43
audio_drv_list="try-coreaudio try-sdl"
44
audio_possible_drivers="coreaudio sdl"
45
# Disable attempts to use ObjectiveC features in os/object.h since they
46
--
47
2.20.1
48
49
diff view generated by jsdifflib
New patch
1
From: Alexander Graf <agraf@csgraf.de>
1
2
3
In macOS 11, QEMU only gets access to Hypervisor.framework if it has the
4
respective entitlement. Add an entitlement template and automatically self
5
sign and apply the entitlement in the build.
6
7
Signed-off-by: Alexander Graf <agraf@csgraf.de>
8
Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
9
Tested-by: Roman Bolshakov <r.bolshakov@yadro.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
meson.build | 29 +++++++++++++++++++++++++----
13
accel/hvf/entitlements.plist | 8 ++++++++
14
scripts/entitlement.sh | 13 +++++++++++++
15
3 files changed, 46 insertions(+), 4 deletions(-)
16
create mode 100644 accel/hvf/entitlements.plist
17
create mode 100755 scripts/entitlement.sh
18
19
diff --git a/meson.build b/meson.build
20
index XXXXXXX..XXXXXXX 100644
21
--- a/meson.build
22
+++ b/meson.build
23
@@ -XXX,XX +XXX,XX @@ foreach target : target_dirs
24
}]
25
endif
26
foreach exe: execs
27
- emulators += {exe['name']:
28
- executable(exe['name'], exe['sources'],
29
- install: true,
30
+ exe_name = exe['name']
31
+ exe_sign = 'CONFIG_HVF' in config_target
32
+ if exe_sign
33
+ exe_name += '-unsigned'
34
+ endif
35
+
36
+ emulator = executable(exe_name, exe['sources'],
37
+ install: not exe_sign,
38
c_args: c_args,
39
dependencies: arch_deps + deps + exe['dependencies'],
40
objects: lib.extract_all_objects(recursive: true),
41
@@ -XXX,XX +XXX,XX @@ foreach target : target_dirs
42
link_depends: [block_syms, qemu_syms] + exe.get('link_depends', []),
43
link_args: link_args,
44
gui_app: exe['gui'])
45
- }
46
+
47
+ if exe_sign
48
+ emulators += {exe['name'] : custom_target(exe['name'],
49
+ install: true,
50
+ install_dir: get_option('bindir'),
51
+ depends: emulator,
52
+ output: exe['name'],
53
+ command: [
54
+ meson.current_source_dir() / 'scripts/entitlement.sh',
55
+ meson.current_build_dir() / exe_name,
56
+ meson.current_build_dir() / exe['name'],
57
+ meson.current_source_dir() / 'accel/hvf/entitlements.plist'
58
+ ])
59
+ }
60
+ else
61
+ emulators += {exe['name']: emulator}
62
+ endif
63
64
if 'CONFIG_TRACE_SYSTEMTAP' in config_host
65
foreach stp: [
66
diff --git a/accel/hvf/entitlements.plist b/accel/hvf/entitlements.plist
67
new file mode 100644
68
index XXXXXXX..XXXXXXX
69
--- /dev/null
70
+++ b/accel/hvf/entitlements.plist
71
@@ -XXX,XX +XXX,XX @@
72
+<?xml version="1.0" encoding="UTF-8"?>
73
+<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
74
+<plist version="1.0">
75
+<dict>
76
+ <key>com.apple.security.hypervisor</key>
77
+ <true/>
78
+</dict>
79
+</plist>
80
diff --git a/scripts/entitlement.sh b/scripts/entitlement.sh
81
new file mode 100755
82
index XXXXXXX..XXXXXXX
83
--- /dev/null
84
+++ b/scripts/entitlement.sh
85
@@ -XXX,XX +XXX,XX @@
86
+#!/bin/sh -e
87
+#
88
+# Helper script for the build process to apply entitlements
89
+
90
+SRC="$1"
91
+DST="$2"
92
+ENTITLEMENT="$3"
93
+
94
+trap 'rm "$DST.tmp"' exit
95
+cp -af "$SRC" "$DST.tmp"
96
+codesign --entitlements "$ENTITLEMENT" --force -s - "$DST.tmp"
97
+mv "$DST.tmp" "$DST"
98
+trap '' exit
99
--
100
2.20.1
101
102
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Mihai Carabas <mihai.carabas@oracle.com>
2
2
3
Using class_data pointer to create a MachineClass is not
3
To ease the PCI device addition in next patches, split the code as follows:
4
the recommended way anymore. The correct way is to open-code
4
- generic code (read/write/setup) is being kept in pvpanic.c
5
the MachineClass::fields in the class_init() method.
5
- ISA dependent code moved to pvpanic-isa.c
6
6
7
We can not use TYPE_RASPI_MACHINE::class_base_init() because
7
Also, rename:
8
it is called *before* each machine class_init(), therefore the
8
- ISA_PVPANIC_DEVICE -> PVPANIC_ISA_DEVICE.
9
board_rev field is not populated. We have to manually call
9
- TYPE_PVPANIC -> TYPE_PVPANIC_ISA.
10
raspi_machine_class_common_init() for each machine.
10
- MemoryRegion io -> mr.
11
11
- pvpanic_ioport_* in pvpanic_*.
12
This partly reverts commit a03bde3674e.
12
13
13
Update the build system with the new files and config structure.
14
Suggested-by: Igor Mammedov <imammedo@redhat.com>
14
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
16
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200924111808.77168-5-f4bug@amsat.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
18
---
21
hw/arm/raspi.c | 34 ++++++++++++++++++++++++----------
19
include/hw/misc/pvpanic.h | 23 +++++++++-
22
1 file changed, 24 insertions(+), 10 deletions(-)
20
hw/misc/pvpanic-isa.c | 94 +++++++++++++++++++++++++++++++++++++++
23
21
hw/misc/pvpanic.c | 85 +++--------------------------------
24
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
22
hw/i386/Kconfig | 2 +-
25
index XXXXXXX..XXXXXXX 100644
23
hw/misc/Kconfig | 6 ++-
26
--- a/hw/arm/raspi.c
24
hw/misc/meson.build | 3 +-
27
+++ b/hw/arm/raspi.c
25
tests/qtest/meson.build | 2 +-
28
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
26
7 files changed, 130 insertions(+), 85 deletions(-)
29
setup_boot(machine, version, machine->ram_size - vcram_size);
27
create mode 100644 hw/misc/pvpanic-isa.c
28
29
diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/misc/pvpanic.h
32
+++ b/include/hw/misc/pvpanic.h
33
@@ -XXX,XX +XXX,XX @@
34
35
#include "qom/object.h"
36
37
-#define TYPE_PVPANIC "pvpanic"
38
+#define TYPE_PVPANIC_ISA_DEVICE "pvpanic"
39
40
#define PVPANIC_IOPORT_PROP "ioport"
41
42
+/* The bit of supported pv event, TODO: include uapi header and remove this */
43
+#define PVPANIC_F_PANICKED 0
44
+#define PVPANIC_F_CRASHLOADED 1
45
+
46
+/* The pv event value */
47
+#define PVPANIC_PANICKED (1 << PVPANIC_F_PANICKED)
48
+#define PVPANIC_CRASHLOADED (1 << PVPANIC_F_CRASHLOADED)
49
+
50
+/*
51
+ * PVPanicState for any device type
52
+ */
53
+typedef struct PVPanicState PVPanicState;
54
+struct PVPanicState {
55
+ MemoryRegion mr;
56
+ uint8_t events;
57
+};
58
+
59
+void pvpanic_setup_io(PVPanicState *s, DeviceState *dev, unsigned size);
60
+
61
static inline uint16_t pvpanic_port(void)
62
{
63
- Object *o = object_resolve_path_type("", TYPE_PVPANIC, NULL);
64
+ Object *o = object_resolve_path_type("", TYPE_PVPANIC_ISA_DEVICE, NULL);
65
if (!o) {
66
return 0;
67
}
68
diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c
69
new file mode 100644
70
index XXXXXXX..XXXXXXX
71
--- /dev/null
72
+++ b/hw/misc/pvpanic-isa.c
73
@@ -XXX,XX +XXX,XX @@
74
+/*
75
+ * QEMU simulated pvpanic device.
76
+ *
77
+ * Copyright Fujitsu, Corp. 2013
78
+ *
79
+ * Authors:
80
+ * Wen Congyang <wency@cn.fujitsu.com>
81
+ * Hu Tao <hutao@cn.fujitsu.com>
82
+ *
83
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
84
+ * See the COPYING file in the top-level directory.
85
+ *
86
+ */
87
+
88
+#include "qemu/osdep.h"
89
+#include "qemu/log.h"
90
+#include "qemu/module.h"
91
+#include "sysemu/runstate.h"
92
+
93
+#include "hw/nvram/fw_cfg.h"
94
+#include "hw/qdev-properties.h"
95
+#include "hw/misc/pvpanic.h"
96
+#include "qom/object.h"
97
+#include "hw/isa/isa.h"
98
+
99
+OBJECT_DECLARE_SIMPLE_TYPE(PVPanicISAState, PVPANIC_ISA_DEVICE)
100
+
101
+/*
102
+ * PVPanicISAState for ISA device and
103
+ * use ioport.
104
+ */
105
+struct PVPanicISAState {
106
+ ISADevice parent_obj;
107
+
108
+ uint16_t ioport;
109
+ PVPanicState pvpanic;
110
+};
111
+
112
+static void pvpanic_isa_initfn(Object *obj)
113
+{
114
+ PVPanicISAState *s = PVPANIC_ISA_DEVICE(obj);
115
+
116
+ pvpanic_setup_io(&s->pvpanic, DEVICE(s), 1);
117
+}
118
+
119
+static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
120
+{
121
+ ISADevice *d = ISA_DEVICE(dev);
122
+ PVPanicISAState *s = PVPANIC_ISA_DEVICE(dev);
123
+ PVPanicState *ps = &s->pvpanic;
124
+ FWCfgState *fw_cfg = fw_cfg_find();
125
+ uint16_t *pvpanic_port;
126
+
127
+ if (!fw_cfg) {
128
+ return;
129
+ }
130
+
131
+ pvpanic_port = g_malloc(sizeof(*pvpanic_port));
132
+ *pvpanic_port = cpu_to_le16(s->ioport);
133
+ fw_cfg_add_file(fw_cfg, "etc/pvpanic-port", pvpanic_port,
134
+ sizeof(*pvpanic_port));
135
+
136
+ isa_register_ioport(d, &ps->mr, s->ioport);
137
+}
138
+
139
+static Property pvpanic_isa_properties[] = {
140
+ DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicISAState, ioport, 0x505),
141
+ DEFINE_PROP_UINT8("events", PVPanicISAState, pvpanic.events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),
142
+ DEFINE_PROP_END_OF_LIST(),
143
+};
144
+
145
+static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
146
+{
147
+ DeviceClass *dc = DEVICE_CLASS(klass);
148
+
149
+ dc->realize = pvpanic_isa_realizefn;
150
+ device_class_set_props(dc, pvpanic_isa_properties);
151
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
152
+}
153
+
154
+static TypeInfo pvpanic_isa_info = {
155
+ .name = TYPE_PVPANIC_ISA_DEVICE,
156
+ .parent = TYPE_ISA_DEVICE,
157
+ .instance_size = sizeof(PVPanicISAState),
158
+ .instance_init = pvpanic_isa_initfn,
159
+ .class_init = pvpanic_isa_class_init,
160
+};
161
+
162
+static void pvpanic_register_types(void)
163
+{
164
+ type_register_static(&pvpanic_isa_info);
165
+}
166
+
167
+type_init(pvpanic_register_types)
168
diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/hw/misc/pvpanic.c
171
+++ b/hw/misc/pvpanic.c
172
@@ -XXX,XX +XXX,XX @@
173
#include "hw/misc/pvpanic.h"
174
#include "qom/object.h"
175
176
-/* The bit of supported pv event, TODO: include uapi header and remove this */
177
-#define PVPANIC_F_PANICKED 0
178
-#define PVPANIC_F_CRASHLOADED 1
179
-
180
-/* The pv event value */
181
-#define PVPANIC_PANICKED (1 << PVPANIC_F_PANICKED)
182
-#define PVPANIC_CRASHLOADED (1 << PVPANIC_F_CRASHLOADED)
183
-
184
-typedef struct PVPanicState PVPanicState;
185
-DECLARE_INSTANCE_CHECKER(PVPanicState, ISA_PVPANIC_DEVICE,
186
- TYPE_PVPANIC)
187
-
188
static void handle_event(int event)
189
{
190
static bool logged;
191
@@ -XXX,XX +XXX,XX @@ static void handle_event(int event)
192
}
30
}
193
}
31
194
32
-static void raspi_machine_class_init(ObjectClass *oc, void *data)
195
-#include "hw/isa/isa.h"
33
+static void raspi_machine_class_common_init(MachineClass *mc,
196
-
34
+ uint32_t board_rev)
197
-struct PVPanicState {
35
{
198
- ISADevice parent_obj;
36
- MachineClass *mc = MACHINE_CLASS(oc);
199
-
37
- RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
200
- MemoryRegion io;
38
- uint32_t board_rev = (uint32_t)(uintptr_t)data;
201
- uint16_t ioport;
39
-
202
- uint8_t events;
40
- rmc->board_rev = board_rev;
203
-};
41
mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
204
-
42
board_type(board_rev),
205
/* return supported events on read */
43
FIELD_EX32(board_rev, REV_CODE, REVISION));
206
-static uint64_t pvpanic_ioport_read(void *opaque, hwaddr addr, unsigned size)
44
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
207
+static uint64_t pvpanic_read(void *opaque, hwaddr addr, unsigned size)
45
mc->default_ram_id = "ram";
208
{
209
PVPanicState *pvp = opaque;
210
return pvp->events;
211
}
212
213
-static void pvpanic_ioport_write(void *opaque, hwaddr addr, uint64_t val,
214
+static void pvpanic_write(void *opaque, hwaddr addr, uint64_t val,
215
unsigned size)
216
{
217
handle_event(val);
218
}
219
220
static const MemoryRegionOps pvpanic_ops = {
221
- .read = pvpanic_ioport_read,
222
- .write = pvpanic_ioport_write,
223
+ .read = pvpanic_read,
224
+ .write = pvpanic_write,
225
.impl = {
226
.min_access_size = 1,
227
.max_access_size = 1,
228
},
46
};
229
};
47
230
48
+static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
231
-static void pvpanic_isa_initfn(Object *obj)
49
+{
232
+void pvpanic_setup_io(PVPanicState *s, DeviceState *dev, unsigned size)
50
+ MachineClass *mc = MACHINE_CLASS(oc);
233
{
51
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
234
- PVPanicState *s = ISA_PVPANIC_DEVICE(obj);
52
+
235
-
53
+ rmc->board_rev = 0xa21041;
236
- memory_region_init_io(&s->io, OBJECT(s), &pvpanic_ops, s, "pvpanic", 1);
54
+ raspi_machine_class_common_init(mc, rmc->board_rev);
237
+ memory_region_init_io(&s->mr, OBJECT(dev), &pvpanic_ops, s, "pvpanic", size);
55
+};
238
}
56
+
239
-
57
+#ifdef TARGET_AARCH64
240
-static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
58
+static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
241
-{
59
+{
242
- ISADevice *d = ISA_DEVICE(dev);
60
+ MachineClass *mc = MACHINE_CLASS(oc);
243
- PVPanicState *s = ISA_PVPANIC_DEVICE(dev);
61
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
244
- FWCfgState *fw_cfg = fw_cfg_find();
62
+
245
- uint16_t *pvpanic_port;
63
+ rmc->board_rev = 0xa02082;
246
-
64
+ raspi_machine_class_common_init(mc, rmc->board_rev);
247
- if (!fw_cfg) {
65
+};
248
- return;
66
+#endif /* TARGET_AARCH64 */
249
- }
67
+
250
-
68
static const TypeInfo raspi_machine_types[] = {
251
- pvpanic_port = g_malloc(sizeof(*pvpanic_port));
69
{
252
- *pvpanic_port = cpu_to_le16(s->ioport);
70
.name = MACHINE_TYPE_NAME("raspi2"),
253
- fw_cfg_add_file(fw_cfg, "etc/pvpanic-port", pvpanic_port,
71
.parent = TYPE_RASPI_MACHINE,
254
- sizeof(*pvpanic_port));
72
- .class_init = raspi_machine_class_init,
255
-
73
- .class_data = (void *)0xa21041,
256
- isa_register_ioport(d, &s->io, s->ioport);
74
+ .class_init = raspi2b_machine_class_init,
257
-}
75
#ifdef TARGET_AARCH64
258
-
76
}, {
259
-static Property pvpanic_isa_properties[] = {
77
.name = MACHINE_TYPE_NAME("raspi3"),
260
- DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505),
78
.parent = TYPE_RASPI_MACHINE,
261
- DEFINE_PROP_UINT8("events", PVPanicState, events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),
79
- .class_init = raspi_machine_class_init,
262
- DEFINE_PROP_END_OF_LIST(),
80
- .class_data = (void *)0xa02082,
263
-};
81
+ .class_init = raspi3b_machine_class_init,
264
-
82
#endif
265
-static void pvpanic_isa_class_init(ObjectClass *klass, void *data)
83
}, {
266
-{
84
.name = TYPE_RASPI_MACHINE,
267
- DeviceClass *dc = DEVICE_CLASS(klass);
268
-
269
- dc->realize = pvpanic_isa_realizefn;
270
- device_class_set_props(dc, pvpanic_isa_properties);
271
- set_bit(DEVICE_CATEGORY_MISC, dc->categories);
272
-}
273
-
274
-static TypeInfo pvpanic_isa_info = {
275
- .name = TYPE_PVPANIC,
276
- .parent = TYPE_ISA_DEVICE,
277
- .instance_size = sizeof(PVPanicState),
278
- .instance_init = pvpanic_isa_initfn,
279
- .class_init = pvpanic_isa_class_init,
280
-};
281
-
282
-static void pvpanic_register_types(void)
283
-{
284
- type_register_static(&pvpanic_isa_info);
285
-}
286
-
287
-type_init(pvpanic_register_types)
288
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
289
index XXXXXXX..XXXXXXX 100644
290
--- a/hw/i386/Kconfig
291
+++ b/hw/i386/Kconfig
292
@@ -XXX,XX +XXX,XX @@ config PC
293
imply ISA_DEBUG
294
imply PARALLEL
295
imply PCI_DEVICES
296
- imply PVPANIC
297
+ imply PVPANIC_ISA
298
imply QXL
299
imply SEV
300
imply SGA
301
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
302
index XXXXXXX..XXXXXXX 100644
303
--- a/hw/misc/Kconfig
304
+++ b/hw/misc/Kconfig
305
@@ -XXX,XX +XXX,XX @@ config IOTKIT_SYSCTL
306
config IOTKIT_SYSINFO
307
bool
308
309
-config PVPANIC
310
+config PVPANIC_COMMON
311
+ bool
312
+
313
+config PVPANIC_ISA
314
bool
315
depends on ISA_BUS
316
+ select PVPANIC_COMMON
317
318
config AUX
319
bool
320
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
321
index XXXXXXX..XXXXXXX 100644
322
--- a/hw/misc/meson.build
323
+++ b/hw/misc/meson.build
324
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_EMC141X', if_true: files('emc141x.c'))
325
softmmu_ss.add(when: 'CONFIG_UNIMP', if_true: files('unimp.c'))
326
softmmu_ss.add(when: 'CONFIG_EMPTY_SLOT', if_true: files('empty_slot.c'))
327
softmmu_ss.add(when: 'CONFIG_LED', if_true: files('led.c'))
328
+softmmu_ss.add(when: 'CONFIG_PVPANIC_COMMON', if_true: files('pvpanic.c'))
329
330
# ARM devices
331
softmmu_ss.add(when: 'CONFIG_PL310', if_true: files('arm_l2x0.c'))
332
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c')
333
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
334
softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c'))
335
336
-softmmu_ss.add(when: 'CONFIG_PVPANIC', if_true: files('pvpanic.c'))
337
+softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true: files('pvpanic-isa.c'))
338
softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
339
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_scu.c', 'aspeed_sdmc.c', 'aspeed_xdma.c'))
340
softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
341
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
342
index XXXXXXX..XXXXXXX 100644
343
--- a/tests/qtest/meson.build
344
+++ b/tests/qtest/meson.build
345
@@ -XXX,XX +XXX,XX @@ qtests_i386 = \
346
(config_host.has_key('CONFIG_LINUX') and \
347
config_all_devices.has_key('CONFIG_ISA_IPMI_BT') ? ['ipmi-bt-test'] : []) + \
348
(config_all_devices.has_key('CONFIG_WDT_IB700') ? ['wdt_ib700-test'] : []) + \
349
- (config_all_devices.has_key('CONFIG_PVPANIC') ? ['pvpanic-test'] : []) + \
350
+ (config_all_devices.has_key('CONFIG_PVPANIC_ISA') ? ['pvpanic-test'] : []) + \
351
(config_all_devices.has_key('CONFIG_HDA') ? ['intel-hda-test'] : []) + \
352
(config_all_devices.has_key('CONFIG_I82801B11') ? ['i82801b11-test'] : []) + \
353
(config_all_devices.has_key('CONFIG_IOH3420') ? ['ioh3420-test'] : []) + \
85
--
354
--
86
2.20.1
355
2.20.1
87
356
88
357
diff view generated by jsdifflib
New patch
1
From: Mihai Carabas <mihai.carabas@oracle.com>
1
2
3
Add PCI interface support for PVPANIC device. Create a new file pvpanic-pci.c
4
where the PCI specific routines reside and update the build system with the new
5
files and config structure.
6
7
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
8
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/specs/pci-ids.txt | 1 +
14
include/hw/misc/pvpanic.h | 1 +
15
include/hw/pci/pci.h | 1 +
16
hw/misc/pvpanic-pci.c | 94 +++++++++++++++++++++++++++++++++++++++
17
hw/misc/Kconfig | 6 +++
18
hw/misc/meson.build | 1 +
19
6 files changed, 104 insertions(+)
20
create mode 100644 hw/misc/pvpanic-pci.c
21
22
diff --git a/docs/specs/pci-ids.txt b/docs/specs/pci-ids.txt
23
index XXXXXXX..XXXXXXX 100644
24
--- a/docs/specs/pci-ids.txt
25
+++ b/docs/specs/pci-ids.txt
26
@@ -XXX,XX +XXX,XX @@ PCI devices (other than virtio):
27
1b36:000d PCI xhci usb host adapter
28
1b36:000f mdpy (mdev sample device), linux/samples/vfio-mdev/mdpy.c
29
1b36:0010 PCIe NVMe device (-device nvme)
30
+1b36:0011 PCI PVPanic device (-device pvpanic-pci)
31
32
All these devices are documented in docs/specs.
33
34
diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/misc/pvpanic.h
37
+++ b/include/hw/misc/pvpanic.h
38
@@ -XXX,XX +XXX,XX @@
39
#include "qom/object.h"
40
41
#define TYPE_PVPANIC_ISA_DEVICE "pvpanic"
42
+#define TYPE_PVPANIC_PCI_DEVICE "pvpanic-pci"
43
44
#define PVPANIC_IOPORT_PROP "ioport"
45
46
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/include/hw/pci/pci.h
49
+++ b/include/hw/pci/pci.h
50
@@ -XXX,XX +XXX,XX @@ extern bool pci_available;
51
#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
52
#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
53
#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
54
+#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
55
#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
56
57
#define FMT_PCIBUS PRIx64
58
diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c
59
new file mode 100644
60
index XXXXXXX..XXXXXXX
61
--- /dev/null
62
+++ b/hw/misc/pvpanic-pci.c
63
@@ -XXX,XX +XXX,XX @@
64
+/*
65
+ * QEMU simulated PCI pvpanic device.
66
+ *
67
+ * Copyright (C) 2020 Oracle
68
+ *
69
+ * Authors:
70
+ * Mihai Carabas <mihai.carabas@oracle.com>
71
+ *
72
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
73
+ * See the COPYING file in the top-level directory.
74
+ *
75
+ */
76
+
77
+#include "qemu/osdep.h"
78
+#include "qemu/log.h"
79
+#include "qemu/module.h"
80
+#include "sysemu/runstate.h"
81
+
82
+#include "hw/nvram/fw_cfg.h"
83
+#include "hw/qdev-properties.h"
84
+#include "migration/vmstate.h"
85
+#include "hw/misc/pvpanic.h"
86
+#include "qom/object.h"
87
+#include "hw/pci/pci.h"
88
+
89
+OBJECT_DECLARE_SIMPLE_TYPE(PVPanicPCIState, PVPANIC_PCI_DEVICE)
90
+
91
+/*
92
+ * PVPanicPCIState for PCI device
93
+ */
94
+typedef struct PVPanicPCIState {
95
+ PCIDevice dev;
96
+ PVPanicState pvpanic;
97
+} PVPanicPCIState;
98
+
99
+static const VMStateDescription vmstate_pvpanic_pci = {
100
+ .name = "pvpanic-pci",
101
+ .version_id = 1,
102
+ .minimum_version_id = 1,
103
+ .fields = (VMStateField[]) {
104
+ VMSTATE_PCI_DEVICE(dev, PVPanicPCIState),
105
+ VMSTATE_END_OF_LIST()
106
+ }
107
+};
108
+
109
+static void pvpanic_pci_realizefn(PCIDevice *dev, Error **errp)
110
+{
111
+ PVPanicPCIState *s = PVPANIC_PCI_DEVICE(dev);
112
+ PVPanicState *ps = &s->pvpanic;
113
+
114
+ pvpanic_setup_io(&s->pvpanic, DEVICE(s), 2);
115
+
116
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &ps->mr);
117
+}
118
+
119
+static Property pvpanic_pci_properties[] = {
120
+ DEFINE_PROP_UINT8("events", PVPanicPCIState, pvpanic.events, PVPANIC_PANICKED | PVPANIC_CRASHLOADED),
121
+ DEFINE_PROP_END_OF_LIST(),
122
+};
123
+
124
+static void pvpanic_pci_class_init(ObjectClass *klass, void *data)
125
+{
126
+ DeviceClass *dc = DEVICE_CLASS(klass);
127
+ PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
128
+
129
+ device_class_set_props(dc, pvpanic_pci_properties);
130
+
131
+ pc->realize = pvpanic_pci_realizefn;
132
+ pc->vendor_id = PCI_VENDOR_ID_REDHAT;
133
+ pc->device_id = PCI_DEVICE_ID_REDHAT_PVPANIC;
134
+ pc->revision = 1;
135
+ pc->class_id = PCI_CLASS_SYSTEM_OTHER;
136
+ dc->vmsd = &vmstate_pvpanic_pci;
137
+
138
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
139
+}
140
+
141
+static TypeInfo pvpanic_pci_info = {
142
+ .name = TYPE_PVPANIC_PCI_DEVICE,
143
+ .parent = TYPE_PCI_DEVICE,
144
+ .instance_size = sizeof(PVPanicPCIState),
145
+ .class_init = pvpanic_pci_class_init,
146
+ .interfaces = (InterfaceInfo[]) {
147
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
148
+ { }
149
+ }
150
+};
151
+
152
+static void pvpanic_register_types(void)
153
+{
154
+ type_register_static(&pvpanic_pci_info);
155
+}
156
+
157
+type_init(pvpanic_register_types);
158
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
159
index XXXXXXX..XXXXXXX 100644
160
--- a/hw/misc/Kconfig
161
+++ b/hw/misc/Kconfig
162
@@ -XXX,XX +XXX,XX @@ config IOTKIT_SYSINFO
163
config PVPANIC_COMMON
164
bool
165
166
+config PVPANIC_PCI
167
+ bool
168
+ default y if PCI_DEVICES
169
+ depends on PCI
170
+ select PVPANIC_COMMON
171
+
172
config PVPANIC_ISA
173
bool
174
depends on ISA_BUS
175
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
176
index XXXXXXX..XXXXXXX 100644
177
--- a/hw/misc/meson.build
178
+++ b/hw/misc/meson.build
179
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
180
softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c'))
181
182
softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true: files('pvpanic-isa.c'))
183
+softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c'))
184
softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
185
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_scu.c', 'aspeed_sdmc.c', 'aspeed_xdma.c'))
186
softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
187
--
188
2.20.1
189
190
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Mihai Carabas <mihai.carabas@oracle.com>
2
2
3
The mte update missed a bit when producing clean addresses.
3
Add pvpanic PCI device support details in docs/specs/pvpanic.txt.
4
4
5
Fixes: b2aa8879b88
5
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
target/arm/translate-sve.c | 4 ++--
9
docs/specs/pvpanic.txt | 13 ++++++++++++-
12
1 file changed, 2 insertions(+), 2 deletions(-)
10
1 file changed, 12 insertions(+), 1 deletion(-)
13
11
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
14
--- a/docs/specs/pvpanic.txt
17
+++ b/target/arm/translate-sve.c
15
+++ b/docs/specs/pvpanic.txt
18
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
16
@@ -XXX,XX +XXX,XX @@
19
for (i = 0; i < len_align; i += 8) {
17
PVPANIC DEVICE
20
tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ);
18
==============
21
tcg_gen_st_i64(t0, cpu_env, vofs + i);
19
22
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
20
-pvpanic device is a simulated ISA device, through which a guest panic
23
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
21
+pvpanic device is a simulated device, through which a guest panic
24
}
22
event is sent to qemu, and a QMP event is generated. This allows
25
tcg_temp_free_i64(t0);
23
management apps (e.g. libvirt) to be notified and respond to the event.
26
} else {
24
27
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
25
@@ -XXX,XX +XXX,XX @@ The management app has the option of waiting for GUEST_PANICKED events,
28
for (i = 0; i < len_align; i += 8) {
26
and/or polling for guest-panicked RunState, to learn when the pvpanic
29
tcg_gen_ld_i64(t0, cpu_env, vofs + i);
27
device has fired a panic event.
30
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
28
31
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
29
+The pvpanic device can be implemented as an ISA device (using IOPORT) or as a
32
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
30
+PCI device.
33
}
31
+
34
tcg_temp_free_i64(t0);
32
ISA Interface
35
} else {
33
-------------
34
35
@@ -XXX,XX +XXX,XX @@ bit 1: a guest panic has happened and will be handled by the guest;
36
the host should record it or report it, but should not affect
37
the execution of the guest.
38
39
+PCI Interface
40
+-------------
41
+
42
+The PCI interface is similar to the ISA interface except that it uses an MMIO
43
+address space provided by its BAR0, 1 byte long. Any machine with a PCI bus
44
+can enable a pvpanic device by adding '-device pvpanic-pci' to the command
45
+line.
46
+
47
ACPI Interface
48
--------------
49
36
--
50
--
37
2.20.1
51
2.20.1
38
52
39
53
diff view generated by jsdifflib
New patch
1
From: Mihai Carabas <mihai.carabas@oracle.com>
1
2
3
Add a test case for pvpanic-pci device. The scenario is the same as pvpanic
4
ISA device, but is using the PCI bus.
5
6
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
7
Acked-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
tests/qtest/pvpanic-pci-test.c | 94 ++++++++++++++++++++++++++++++++++
13
tests/qtest/meson.build | 1 +
14
2 files changed, 95 insertions(+)
15
create mode 100644 tests/qtest/pvpanic-pci-test.c
16
17
diff --git a/tests/qtest/pvpanic-pci-test.c b/tests/qtest/pvpanic-pci-test.c
18
new file mode 100644
19
index XXXXXXX..XXXXXXX
20
--- /dev/null
21
+++ b/tests/qtest/pvpanic-pci-test.c
22
@@ -XXX,XX +XXX,XX @@
23
+/*
24
+ * QTest testcase for PV Panic PCI device
25
+ *
26
+ * Copyright (C) 2020 Oracle
27
+ *
28
+ * Authors:
29
+ * Mihai Carabas <mihai.carabas@oracle.com>
30
+ *
31
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
32
+ * See the COPYING file in the top-level directory.
33
+ *
34
+ */
35
+
36
+#include "qemu/osdep.h"
37
+#include "libqos/libqtest.h"
38
+#include "qapi/qmp/qdict.h"
39
+#include "libqos/pci.h"
40
+#include "libqos/pci-pc.h"
41
+#include "hw/pci/pci_regs.h"
42
+
43
+static void test_panic_nopause(void)
44
+{
45
+ uint8_t val;
46
+ QDict *response, *data;
47
+ QTestState *qts;
48
+ QPCIBus *pcibus;
49
+ QPCIDevice *dev;
50
+ QPCIBar bar;
51
+
52
+ qts = qtest_init("-device pvpanic-pci,addr=04.0 -action panic=none");
53
+ pcibus = qpci_new_pc(qts, NULL);
54
+ dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0));
55
+ qpci_device_enable(dev);
56
+ bar = qpci_iomap(dev, 0, NULL);
57
+
58
+ qpci_memread(dev, bar, 0, &val, sizeof(val));
59
+ g_assert_cmpuint(val, ==, 3);
60
+
61
+ val = 1;
62
+ qpci_memwrite(dev, bar, 0, &val, sizeof(val));
63
+
64
+ response = qtest_qmp_eventwait_ref(qts, "GUEST_PANICKED");
65
+ g_assert(qdict_haskey(response, "data"));
66
+ data = qdict_get_qdict(response, "data");
67
+ g_assert(qdict_haskey(data, "action"));
68
+ g_assert_cmpstr(qdict_get_str(data, "action"), ==, "run");
69
+ qobject_unref(response);
70
+
71
+ qtest_quit(qts);
72
+}
73
+
74
+static void test_panic(void)
75
+{
76
+ uint8_t val;
77
+ QDict *response, *data;
78
+ QTestState *qts;
79
+ QPCIBus *pcibus;
80
+ QPCIDevice *dev;
81
+ QPCIBar bar;
82
+
83
+ qts = qtest_init("-device pvpanic-pci,addr=04.0 -action panic=pause");
84
+ pcibus = qpci_new_pc(qts, NULL);
85
+ dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0));
86
+ qpci_device_enable(dev);
87
+ bar = qpci_iomap(dev, 0, NULL);
88
+
89
+ qpci_memread(dev, bar, 0, &val, sizeof(val));
90
+ g_assert_cmpuint(val, ==, 3);
91
+
92
+ val = 1;
93
+ qpci_memwrite(dev, bar, 0, &val, sizeof(val));
94
+
95
+ response = qtest_qmp_eventwait_ref(qts, "GUEST_PANICKED");
96
+ g_assert(qdict_haskey(response, "data"));
97
+ data = qdict_get_qdict(response, "data");
98
+ g_assert(qdict_haskey(data, "action"));
99
+ g_assert_cmpstr(qdict_get_str(data, "action"), ==, "pause");
100
+ qobject_unref(response);
101
+
102
+ qtest_quit(qts);
103
+}
104
+
105
+int main(int argc, char **argv)
106
+{
107
+ int ret;
108
+
109
+ g_test_init(&argc, &argv, NULL);
110
+ qtest_add_func("/pvpanic-pci/panic", test_panic);
111
+ qtest_add_func("/pvpanic-pci/panic-nopause", test_panic_nopause);
112
+
113
+ ret = g_test_run();
114
+
115
+ return ret;
116
+}
117
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
118
index XXXXXXX..XXXXXXX 100644
119
--- a/tests/qtest/meson.build
120
+++ b/tests/qtest/meson.build
121
@@ -XXX,XX +XXX,XX @@ qtests_i386 = \
122
config_all_devices.has_key('CONFIG_ISA_IPMI_BT') ? ['ipmi-bt-test'] : []) + \
123
(config_all_devices.has_key('CONFIG_WDT_IB700') ? ['wdt_ib700-test'] : []) + \
124
(config_all_devices.has_key('CONFIG_PVPANIC_ISA') ? ['pvpanic-test'] : []) + \
125
+ (config_all_devices.has_key('CONFIG_PVPANIC_PCI') ? ['pvpanic-pci-test'] : []) + \
126
(config_all_devices.has_key('CONFIG_HDA') ? ['intel-hda-test'] : []) + \
127
(config_all_devices.has_key('CONFIG_I82801B11') ? ['i82801b11-test'] : []) + \
128
(config_all_devices.has_key('CONFIG_IOH3420') ? ['ioh3420-test'] : []) + \
129
--
130
2.20.1
131
132
diff view generated by jsdifflib
New patch
1
The ptimer API currently provides two methods for setting the period:
2
ptimer_set_period(), which takes a period in nanoseconds, and
3
ptimer_set_freq(), which takes a frequency in Hz. Neither of these
4
lines up nicely with the Clock API, because although both the Clock
5
and the ptimer track the frequency using a representation of whole
6
and fractional nanoseconds, conversion via either period-in-ns or
7
frequency-in-Hz will introduce a rounding error.
1
8
9
Add a new function ptimer_set_period_from_clock() which takes the
10
Clock object directly to avoid the rounding issues. This includes a
11
facility for the user to specify that there is a frequency divider
12
between the Clock proper and the timer, as some timer devices like
13
the CMSDK APB dualtimer need this.
14
15
To avoid having to drag in clock.h from ptimer.h we add the Clock
16
type to typedefs.h.
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Luc Michel <luc@lmichel.fr>
20
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Message-id: 20210128114145.20536-2-peter.maydell@linaro.org
23
Message-id: 20210121190622.22000-2-peter.maydell@linaro.org
24
---
25
include/hw/ptimer.h | 22 ++++++++++++++++++++++
26
include/qemu/typedefs.h | 1 +
27
hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++
28
3 files changed, 57 insertions(+)
29
30
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/ptimer.h
33
+++ b/include/hw/ptimer.h
34
@@ -XXX,XX +XXX,XX @@ void ptimer_transaction_commit(ptimer_state *s);
35
*/
36
void ptimer_set_period(ptimer_state *s, int64_t period);
37
38
+/**
39
+ * ptimer_set_period_from_clock - Set counter increment from a Clock
40
+ * @s: ptimer to configure
41
+ * @clk: pointer to Clock object to take period from
42
+ * @divisor: value to scale the clock frequency down by
43
+ *
44
+ * If the ptimer is being driven from a Clock, this is the preferred
45
+ * way to tell the ptimer about the period, because it avoids any
46
+ * possible rounding errors that might happen if the internal
47
+ * representation of the Clock period was converted to either a period
48
+ * in ns or a frequency in Hz.
49
+ *
50
+ * If the ptimer should run at the same frequency as the clock,
51
+ * pass 1 as the @divisor; if the ptimer should run at half the
52
+ * frequency, pass 2, and so on.
53
+ *
54
+ * This function will assert if it is called outside a
55
+ * ptimer_transaction_begin/commit block.
56
+ */
57
+void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clock,
58
+ unsigned int divisor);
59
+
60
/**
61
* ptimer_set_freq - Set counter frequency in Hz
62
* @s: ptimer to configure
63
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
64
index XXXXXXX..XXXXXXX 100644
65
--- a/include/qemu/typedefs.h
66
+++ b/include/qemu/typedefs.h
67
@@ -XXX,XX +XXX,XX @@ typedef struct BlockDriverState BlockDriverState;
68
typedef struct BusClass BusClass;
69
typedef struct BusState BusState;
70
typedef struct Chardev Chardev;
71
+typedef struct Clock Clock;
72
typedef struct CompatProperty CompatProperty;
73
typedef struct CoMutex CoMutex;
74
typedef struct CPUAddressSpace CPUAddressSpace;
75
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/hw/core/ptimer.c
78
+++ b/hw/core/ptimer.c
79
@@ -XXX,XX +XXX,XX @@
80
#include "sysemu/qtest.h"
81
#include "block/aio.h"
82
#include "sysemu/cpus.h"
83
+#include "hw/clock.h"
84
85
#define DELTA_ADJUST 1
86
#define DELTA_NO_ADJUST -1
87
@@ -XXX,XX +XXX,XX @@ void ptimer_set_period(ptimer_state *s, int64_t period)
88
}
89
}
90
91
+/* Set counter increment interval from a Clock */
92
+void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk,
93
+ unsigned int divisor)
94
+{
95
+ /*
96
+ * The raw clock period is a 64-bit value in units of 2^-32 ns;
97
+ * put another way it's a 32.32 fixed-point ns value. Our internal
98
+ * representation of the period is 64.32 fixed point ns, so
99
+ * the conversion is simple.
100
+ */
101
+ uint64_t raw_period = clock_get(clk);
102
+ uint64_t period_frac;
103
+
104
+ assert(s->in_transaction);
105
+ s->delta = ptimer_get_count(s);
106
+ s->period = extract64(raw_period, 32, 32);
107
+ period_frac = extract64(raw_period, 0, 32);
108
+ /*
109
+ * divisor specifies a possible frequency divisor between the
110
+ * clock and the timer, so it is a multiplier on the period.
111
+ * We do the multiply after splitting the raw period out into
112
+ * period and frac to avoid having to do a 32*64->96 multiply.
113
+ */
114
+ s->period *= divisor;
115
+ period_frac *= divisor;
116
+ s->period += extract64(period_frac, 32, 32);
117
+ s->period_frac = (uint32_t)period_frac;
118
+
119
+ if (s->enabled) {
120
+ s->need_reload = true;
121
+ }
122
+}
123
+
124
/* Set counter frequency in Hz. */
125
void ptimer_set_freq(ptimer_state *s, uint32_t freq)
126
{
127
--
128
2.20.1
129
130
diff view generated by jsdifflib
New patch
1
Add a function for checking whether a clock has a source. This is
2
useful for devices which have input clocks that must be wired up by
3
the board as it allows them to fail in realize rather than ploughing
4
on with a zero-period clock.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210128114145.20536-3-peter.maydell@linaro.org
11
Message-id: 20210121190622.22000-3-peter.maydell@linaro.org
12
---
13
docs/devel/clocks.rst | 16 ++++++++++++++++
14
include/hw/clock.h | 15 +++++++++++++++
15
2 files changed, 31 insertions(+)
16
17
diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
18
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/devel/clocks.rst
20
+++ b/docs/devel/clocks.rst
21
@@ -XXX,XX +XXX,XX @@ object during device instance init. For example:
22
/* set initial value to 10ns / 100MHz */
23
clock_set_ns(clk, 10);
24
25
+To enforce that the clock is wired up by the board code, you can
26
+call ``clock_has_source()`` in your device's realize method:
27
+
28
+.. code-block:: c
29
+
30
+ if (!clock_has_source(s->clk)) {
31
+ error_setg(errp, "MyDevice: clk input must be connected");
32
+ return;
33
+ }
34
+
35
+Note that this only checks that the clock has been wired up; it is
36
+still possible that the output clock connected to it is disabled
37
+or has not yet been configured, in which case the period will be
38
+zero. You should use the clock callback to find out when the clock
39
+period changes.
40
+
41
Fetching clock frequency/period
42
-------------------------------
43
44
diff --git a/include/hw/clock.h b/include/hw/clock.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/clock.h
47
+++ b/include/hw/clock.h
48
@@ -XXX,XX +XXX,XX @@ void clock_clear_callback(Clock *clk);
49
*/
50
void clock_set_source(Clock *clk, Clock *src);
51
52
+/**
53
+ * clock_has_source:
54
+ * @clk: the clock
55
+ *
56
+ * Returns true if the clock has a source clock connected to it.
57
+ * This is useful for devices which have input clocks which must
58
+ * be connected by the board/SoC code which creates them. The
59
+ * device code can use this to check in its realize method that
60
+ * the clock has been connected.
61
+ */
62
+static inline bool clock_has_source(const Clock *clk)
63
+{
64
+ return clk->source != NULL;
65
+}
66
+
67
/**
68
* clock_set:
69
* @clk: the clock to initialize.
70
--
71
2.20.1
72
73
diff view generated by jsdifflib
New patch
1
Add a simple test of the CMSDK APB timer, since we're about to do
2
some refactoring of how it is clocked.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Luc Michel <luc@lmichel.fr>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-4-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-4-peter.maydell@linaro.org
10
---
11
tests/qtest/cmsdk-apb-timer-test.c | 75 ++++++++++++++++++++++++++++++
12
MAINTAINERS | 1 +
13
tests/qtest/meson.build | 1 +
14
3 files changed, 77 insertions(+)
15
create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
16
17
diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c
18
new file mode 100644
19
index XXXXXXX..XXXXXXX
20
--- /dev/null
21
+++ b/tests/qtest/cmsdk-apb-timer-test.c
22
@@ -XXX,XX +XXX,XX @@
23
+/*
24
+ * QTest testcase for the CMSDK APB timer device
25
+ *
26
+ * Copyright (c) 2021 Linaro Limited
27
+ *
28
+ * This program is free software; you can redistribute it and/or modify it
29
+ * under the terms of the GNU General Public License as published by the
30
+ * Free Software Foundation; either version 2 of the License, or
31
+ * (at your option) any later version.
32
+ *
33
+ * This program is distributed in the hope that it will be useful, but WITHOUT
34
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
36
+ * for more details.
37
+ */
38
+
39
+#include "qemu/osdep.h"
40
+#include "libqtest-single.h"
41
+
42
+/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */
43
+#define TIMER_BASE 0x40000000
44
+
45
+#define CTRL 0
46
+#define VALUE 4
47
+#define RELOAD 8
48
+#define INTSTATUS 0xc
49
+
50
+static void test_timer(void)
51
+{
52
+ g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0);
53
+
54
+ /* Start timer: will fire after 40 * 1000 == 40000 ns */
55
+ writel(TIMER_BASE + RELOAD, 1000);
56
+ writel(TIMER_BASE + CTRL, 9);
57
+
58
+ /* Step to just past the 500th tick and check VALUE */
59
+ clock_step(40 * 500 + 1);
60
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0);
61
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500);
62
+
63
+ /* Just past the 1000th tick: timer should have fired */
64
+ clock_step(40 * 500);
65
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1);
66
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0);
67
+
68
+ /* VALUE reloads at the following tick */
69
+ clock_step(40);
70
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000);
71
+
72
+ /* Check write-1-to-clear behaviour of INTSTATUS */
73
+ writel(TIMER_BASE + INTSTATUS, 0);
74
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1);
75
+ writel(TIMER_BASE + INTSTATUS, 1);
76
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0);
77
+
78
+ /* Turn off the timer */
79
+ writel(TIMER_BASE + CTRL, 0);
80
+}
81
+
82
+int main(int argc, char **argv)
83
+{
84
+ int r;
85
+
86
+ g_test_init(&argc, &argv, NULL);
87
+
88
+ qtest_start("-machine mps2-an385");
89
+
90
+ qtest_add_func("/cmsdk-apb-timer/timer", test_timer);
91
+
92
+ r = g_test_run();
93
+
94
+ qtest_end();
95
+
96
+ return r;
97
+}
98
diff --git a/MAINTAINERS b/MAINTAINERS
99
index XXXXXXX..XXXXXXX 100644
100
--- a/MAINTAINERS
101
+++ b/MAINTAINERS
102
@@ -XXX,XX +XXX,XX @@ F: include/hw/rtc/pl031.h
103
F: include/hw/arm/primecell.h
104
F: hw/timer/cmsdk-apb-timer.c
105
F: include/hw/timer/cmsdk-apb-timer.h
106
+F: tests/qtest/cmsdk-apb-timer-test.c
107
F: hw/timer/cmsdk-apb-dualtimer.c
108
F: include/hw/timer/cmsdk-apb-dualtimer.h
109
F: hw/char/cmsdk-apb-uart.c
110
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
111
index XXXXXXX..XXXXXXX 100644
112
--- a/tests/qtest/meson.build
113
+++ b/tests/qtest/meson.build
114
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
115
'npcm7xx_timer-test',
116
'npcm7xx_watchdog_timer-test']
117
qtests_arm = \
118
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
119
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
120
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
121
['arm-cpu-features',
122
--
123
2.20.1
124
125
diff view generated by jsdifflib
New patch
1
Add a simple test of the CMSDK watchdog, since we're about to do some
2
refactoring of how it is clocked.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-5-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-5-peter.maydell@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
---
12
tests/qtest/cmsdk-apb-watchdog-test.c | 79 +++++++++++++++++++++++++++
13
MAINTAINERS | 1 +
14
tests/qtest/meson.build | 1 +
15
3 files changed, 81 insertions(+)
16
create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
17
18
diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c
19
new file mode 100644
20
index XXXXXXX..XXXXXXX
21
--- /dev/null
22
+++ b/tests/qtest/cmsdk-apb-watchdog-test.c
23
@@ -XXX,XX +XXX,XX @@
24
+/*
25
+ * QTest testcase for the CMSDK APB watchdog device
26
+ *
27
+ * Copyright (c) 2021 Linaro Limited
28
+ *
29
+ * This program is free software; you can redistribute it and/or modify it
30
+ * under the terms of the GNU General Public License as published by the
31
+ * Free Software Foundation; either version 2 of the License, or
32
+ * (at your option) any later version.
33
+ *
34
+ * This program is distributed in the hope that it will be useful, but WITHOUT
35
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
36
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
37
+ * for more details.
38
+ */
39
+
40
+#include "qemu/osdep.h"
41
+#include "libqtest-single.h"
42
+
43
+/*
44
+ * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz,
45
+ * which is 80ns per tick.
46
+ */
47
+#define WDOG_BASE 0x40000000
48
+
49
+#define WDOGLOAD 0
50
+#define WDOGVALUE 4
51
+#define WDOGCONTROL 8
52
+#define WDOGINTCLR 0xc
53
+#define WDOGRIS 0x10
54
+#define WDOGMIS 0x14
55
+#define WDOGLOCK 0xc00
56
+
57
+static void test_watchdog(void)
58
+{
59
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
60
+
61
+ writel(WDOG_BASE + WDOGCONTROL, 1);
62
+ writel(WDOG_BASE + WDOGLOAD, 1000);
63
+
64
+ /* Step to just past the 500th tick */
65
+ clock_step(500 * 80 + 1);
66
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
67
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
68
+
69
+ /* Just past the 1000th tick: timer should have fired */
70
+ clock_step(500 * 80);
71
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
72
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
73
+
74
+ /* VALUE reloads at following tick */
75
+ clock_step(80);
76
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
77
+
78
+ /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
79
+ clock_step(500 * 80);
80
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
81
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
82
+ writel(WDOG_BASE + WDOGINTCLR, 0);
83
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
84
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
85
+}
86
+
87
+int main(int argc, char **argv)
88
+{
89
+ int r;
90
+
91
+ g_test_init(&argc, &argv, NULL);
92
+
93
+ qtest_start("-machine lm3s811evb");
94
+
95
+ qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
96
+
97
+ r = g_test_run();
98
+
99
+ qtest_end();
100
+
101
+ return r;
102
+}
103
diff --git a/MAINTAINERS b/MAINTAINERS
104
index XXXXXXX..XXXXXXX 100644
105
--- a/MAINTAINERS
106
+++ b/MAINTAINERS
107
@@ -XXX,XX +XXX,XX @@ F: hw/char/cmsdk-apb-uart.c
108
F: include/hw/char/cmsdk-apb-uart.h
109
F: hw/watchdog/cmsdk-apb-watchdog.c
110
F: include/hw/watchdog/cmsdk-apb-watchdog.h
111
+F: tests/qtest/cmsdk-apb-watchdog-test.c
112
F: hw/misc/tz-ppc.c
113
F: include/hw/misc/tz-ppc.h
114
F: hw/misc/tz-mpc.c
115
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
116
index XXXXXXX..XXXXXXX 100644
117
--- a/tests/qtest/meson.build
118
+++ b/tests/qtest/meson.build
119
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
120
'npcm7xx_watchdog_timer-test']
121
qtests_arm = \
122
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
123
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
124
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
125
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
126
['arm-cpu-features',
127
--
128
2.20.1
129
130
diff view generated by jsdifflib
New patch
1
Add a simple test of the CMSDK dual timer, since we're about to do
2
some refactoring of how it is clocked.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Message-id: 20210128114145.20536-6-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-6-peter.maydell@linaro.org
10
---
11
tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++++
12
MAINTAINERS | 1 +
13
tests/qtest/meson.build | 1 +
14
3 files changed, 132 insertions(+)
15
create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
16
17
diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c
18
new file mode 100644
19
index XXXXXXX..XXXXXXX
20
--- /dev/null
21
+++ b/tests/qtest/cmsdk-apb-dualtimer-test.c
22
@@ -XXX,XX +XXX,XX @@
23
+/*
24
+ * QTest testcase for the CMSDK APB dualtimer device
25
+ *
26
+ * Copyright (c) 2021 Linaro Limited
27
+ *
28
+ * This program is free software; you can redistribute it and/or modify it
29
+ * under the terms of the GNU General Public License as published by the
30
+ * Free Software Foundation; either version 2 of the License, or
31
+ * (at your option) any later version.
32
+ *
33
+ * This program is distributed in the hope that it will be useful, but WITHOUT
34
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
36
+ * for more details.
37
+ */
38
+
39
+#include "qemu/osdep.h"
40
+#include "libqtest-single.h"
41
+
42
+/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */
43
+#define TIMER_BASE 0x40002000
44
+
45
+#define TIMER1LOAD 0
46
+#define TIMER1VALUE 4
47
+#define TIMER1CONTROL 8
48
+#define TIMER1INTCLR 0xc
49
+#define TIMER1RIS 0x10
50
+#define TIMER1MIS 0x14
51
+#define TIMER1BGLOAD 0x18
52
+
53
+#define TIMER2LOAD 0x20
54
+#define TIMER2VALUE 0x24
55
+#define TIMER2CONTROL 0x28
56
+#define TIMER2INTCLR 0x2c
57
+#define TIMER2RIS 0x30
58
+#define TIMER2MIS 0x34
59
+#define TIMER2BGLOAD 0x38
60
+
61
+#define CTRL_ENABLE (1 << 7)
62
+#define CTRL_PERIODIC (1 << 6)
63
+#define CTRL_INTEN (1 << 5)
64
+#define CTRL_PRESCALE_1 (0 << 2)
65
+#define CTRL_PRESCALE_16 (1 << 2)
66
+#define CTRL_PRESCALE_256 (2 << 2)
67
+#define CTRL_32BIT (1 << 1)
68
+#define CTRL_ONESHOT (1 << 0)
69
+
70
+static void test_dualtimer(void)
71
+{
72
+ g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0);
73
+
74
+ /* Start timer: will fire after 40000 ns */
75
+ writel(TIMER_BASE + TIMER1LOAD, 1000);
76
+ /* enable in free-running, wrapping, interrupt mode */
77
+ writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN);
78
+
79
+ /* Step to just past the 500th tick and check VALUE */
80
+ clock_step(500 * 40 + 1);
81
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
82
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500);
83
+
84
+ /* Just past the 1000th tick: timer should have fired */
85
+ clock_step(500 * 40);
86
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1);
87
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0);
88
+
89
+ /*
90
+ * We are in free-running wrapping 16-bit mode, so on the following
91
+ * tick VALUE should have wrapped round to 0xffff.
92
+ */
93
+ clock_step(40);
94
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff);
95
+
96
+ /* Check that any write to INTCLR clears interrupt */
97
+ writel(TIMER_BASE + TIMER1INTCLR, 1);
98
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
99
+
100
+ /* Turn off the timer */
101
+ writel(TIMER_BASE + TIMER1CONTROL, 0);
102
+}
103
+
104
+static void test_prescale(void)
105
+{
106
+ g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0);
107
+
108
+ /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */
109
+ writel(TIMER_BASE + TIMER2LOAD, 1000);
110
+ /* enable in periodic, wrapping, interrupt mode, prescale 256 */
111
+ writel(TIMER_BASE + TIMER2CONTROL,
112
+ CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256);
113
+
114
+ /* Step to just past the 500th tick and check VALUE */
115
+ clock_step(40 * 256 * 501);
116
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
117
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500);
118
+
119
+ /* Just past the 1000th tick: timer should have fired */
120
+ clock_step(40 * 256 * 500);
121
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1);
122
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0);
123
+
124
+ /* In periodic mode the tick VALUE now reloads */
125
+ clock_step(40 * 256);
126
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000);
127
+
128
+ /* Check that any write to INTCLR clears interrupt */
129
+ writel(TIMER_BASE + TIMER2INTCLR, 1);
130
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
131
+
132
+ /* Turn off the timer */
133
+ writel(TIMER_BASE + TIMER2CONTROL, 0);
134
+}
135
+
136
+int main(int argc, char **argv)
137
+{
138
+ int r;
139
+
140
+ g_test_init(&argc, &argv, NULL);
141
+
142
+ qtest_start("-machine mps2-an385");
143
+
144
+ qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer);
145
+ qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale);
146
+
147
+ r = g_test_run();
148
+
149
+ qtest_end();
150
+
151
+ return r;
152
+}
153
diff --git a/MAINTAINERS b/MAINTAINERS
154
index XXXXXXX..XXXXXXX 100644
155
--- a/MAINTAINERS
156
+++ b/MAINTAINERS
157
@@ -XXX,XX +XXX,XX @@ F: include/hw/timer/cmsdk-apb-timer.h
158
F: tests/qtest/cmsdk-apb-timer-test.c
159
F: hw/timer/cmsdk-apb-dualtimer.c
160
F: include/hw/timer/cmsdk-apb-dualtimer.h
161
+F: tests/qtest/cmsdk-apb-dualtimer-test.c
162
F: hw/char/cmsdk-apb-uart.c
163
F: include/hw/char/cmsdk-apb-uart.h
164
F: hw/watchdog/cmsdk-apb-watchdog.c
165
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
166
index XXXXXXX..XXXXXXX 100644
167
--- a/tests/qtest/meson.build
168
+++ b/tests/qtest/meson.build
169
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
170
'npcm7xx_timer-test',
171
'npcm7xx_watchdog_timer-test']
172
qtests_arm = \
173
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
174
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
175
(config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
176
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
177
--
178
2.20.1
179
180
diff view generated by jsdifflib
New patch
1
The state struct for the CMSDK APB timer device doesn't follow our
2
usual naming convention of camelcase -- "CMSDK" and "APB" are both
3
acronyms, but "TIMER" is not so should not be all-uppercase.
4
Globally rename the struct to "CMSDKAPBTimer" (bringing it into line
5
with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains
6
as-is because "UART" is an acronym).
1
7
8
Commit created with:
9
perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Luc Michel <luc@lmichel.fr>
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20210128114145.20536-7-peter.maydell@linaro.org
16
Message-id: 20210121190622.22000-7-peter.maydell@linaro.org
17
---
18
include/hw/arm/armsse.h | 6 +++---
19
include/hw/timer/cmsdk-apb-timer.h | 4 ++--
20
hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++--------------
21
3 files changed, 19 insertions(+), 19 deletions(-)
22
23
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/arm/armsse.h
26
+++ b/include/hw/arm/armsse.h
27
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
28
TZPPC apb_ppc0;
29
TZPPC apb_ppc1;
30
TZMPC mpc[IOTS_NUM_MPC];
31
- CMSDKAPBTIMER timer0;
32
- CMSDKAPBTIMER timer1;
33
- CMSDKAPBTIMER s32ktimer;
34
+ CMSDKAPBTimer timer0;
35
+ CMSDKAPBTimer timer1;
36
+ CMSDKAPBTimer s32ktimer;
37
qemu_or_irq ppc_irq_orgate;
38
SplitIRQ sec_resp_splitter;
39
SplitIRQ ppc_irq_splitter[NUM_PPCS];
40
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/include/hw/timer/cmsdk-apb-timer.h
43
+++ b/include/hw/timer/cmsdk-apb-timer.h
44
@@ -XXX,XX +XXX,XX @@
45
#include "qom/object.h"
46
47
#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
48
-OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER)
49
+OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
50
51
-struct CMSDKAPBTIMER {
52
+struct CMSDKAPBTimer {
53
/*< private >*/
54
SysBusDevice parent_obj;
55
56
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/timer/cmsdk-apb-timer.c
59
+++ b/hw/timer/cmsdk-apb-timer.c
60
@@ -XXX,XX +XXX,XX @@ static const int timer_id[] = {
61
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
62
};
63
64
-static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s)
65
+static void cmsdk_apb_timer_update(CMSDKAPBTimer *s)
66
{
67
qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK));
68
}
69
70
static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
71
{
72
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
73
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
74
uint64_t r;
75
76
switch (offset) {
77
@@ -XXX,XX +XXX,XX @@ static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
78
static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
79
unsigned size)
80
{
81
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
82
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
83
84
trace_cmsdk_apb_timer_write(offset, value, size);
85
86
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps cmsdk_apb_timer_ops = {
87
88
static void cmsdk_apb_timer_tick(void *opaque)
89
{
90
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
91
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
92
93
if (s->ctrl & R_CTRL_IRQEN_MASK) {
94
s->intstatus |= R_INTSTATUS_IRQ_MASK;
95
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_tick(void *opaque)
96
97
static void cmsdk_apb_timer_reset(DeviceState *dev)
98
{
99
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
100
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
101
102
trace_cmsdk_apb_timer_reset();
103
s->ctrl = 0;
104
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
105
static void cmsdk_apb_timer_init(Object *obj)
106
{
107
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
108
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj);
109
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(obj);
110
111
memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops,
112
s, "cmsdk-apb-timer", 0x1000);
113
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_init(Object *obj)
114
115
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
116
{
117
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
118
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
119
120
if (s->pclk_frq == 0) {
121
error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
122
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
123
.version_id = 1,
124
.minimum_version_id = 1,
125
.fields = (VMStateField[]) {
126
- VMSTATE_PTIMER(timer, CMSDKAPBTIMER),
127
- VMSTATE_UINT32(ctrl, CMSDKAPBTIMER),
128
- VMSTATE_UINT32(value, CMSDKAPBTIMER),
129
- VMSTATE_UINT32(reload, CMSDKAPBTIMER),
130
- VMSTATE_UINT32(intstatus, CMSDKAPBTIMER),
131
+ VMSTATE_PTIMER(timer, CMSDKAPBTimer),
132
+ VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
133
+ VMSTATE_UINT32(value, CMSDKAPBTimer),
134
+ VMSTATE_UINT32(reload, CMSDKAPBTimer),
135
+ VMSTATE_UINT32(intstatus, CMSDKAPBTimer),
136
VMSTATE_END_OF_LIST()
137
}
138
};
139
140
static Property cmsdk_apb_timer_properties[] = {
141
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0),
142
+ DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
143
DEFINE_PROP_END_OF_LIST(),
144
};
145
146
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
147
static const TypeInfo cmsdk_apb_timer_info = {
148
.name = TYPE_CMSDK_APB_TIMER,
149
.parent = TYPE_SYS_BUS_DEVICE,
150
- .instance_size = sizeof(CMSDKAPBTIMER),
151
+ .instance_size = sizeof(CMSDKAPBTimer),
152
.instance_init = cmsdk_apb_timer_init,
153
.class_init = cmsdk_apb_timer_class_init,
154
};
155
--
156
2.20.1
157
158
diff view generated by jsdifflib
New patch
1
As the first step in converting the CMSDK_APB_TIMER device to the
2
Clock framework, add a Clock input. For the moment we do nothing
3
with this clock; we will change the behaviour from using the pclk-frq
4
property to using the Clock once all the users of this device have
5
been converted to wire up the Clock.
1
6
7
Since the device doesn't already have a doc comment for its "QEMU
8
interface", we add one including the new Clock.
9
10
This is a migration compatibility break for machines mps2-an505,
11
mps2-an521, musca-a, musca-b1.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
16
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20210128114145.20536-8-peter.maydell@linaro.org
18
Message-id: 20210121190622.22000-8-peter.maydell@linaro.org
19
---
20
include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++
21
hw/timer/cmsdk-apb-timer.c | 7 +++++--
22
2 files changed, 14 insertions(+), 2 deletions(-)
23
24
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/timer/cmsdk-apb-timer.h
27
+++ b/include/hw/timer/cmsdk-apb-timer.h
28
@@ -XXX,XX +XXX,XX @@
29
#include "hw/qdev-properties.h"
30
#include "hw/sysbus.h"
31
#include "hw/ptimer.h"
32
+#include "hw/clock.h"
33
#include "qom/object.h"
34
35
#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
36
OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
37
38
+/*
39
+ * QEMU interface:
40
+ * + QOM property "pclk-frq": frequency at which the timer is clocked
41
+ * + Clock input "pclk": clock for the timer
42
+ * + sysbus MMIO region 0: the register bank
43
+ * + sysbus IRQ 0: timer interrupt TIMERINT
44
+ */
45
struct CMSDKAPBTimer {
46
/*< private >*/
47
SysBusDevice parent_obj;
48
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBTimer {
49
qemu_irq timerint;
50
uint32_t pclk_frq;
51
struct ptimer_state *timer;
52
+ Clock *pclk;
53
54
uint32_t ctrl;
55
uint32_t value;
56
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/timer/cmsdk-apb-timer.c
59
+++ b/hw/timer/cmsdk-apb-timer.c
60
@@ -XXX,XX +XXX,XX @@
61
#include "hw/sysbus.h"
62
#include "hw/irq.h"
63
#include "hw/registerfields.h"
64
+#include "hw/qdev-clock.h"
65
#include "hw/timer/cmsdk-apb-timer.h"
66
#include "migration/vmstate.h"
67
68
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_init(Object *obj)
69
s, "cmsdk-apb-timer", 0x1000);
70
sysbus_init_mmio(sbd, &s->iomem);
71
sysbus_init_irq(sbd, &s->timerint);
72
+ s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
73
}
74
75
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
76
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
77
78
static const VMStateDescription cmsdk_apb_timer_vmstate = {
79
.name = "cmsdk-apb-timer",
80
- .version_id = 1,
81
- .minimum_version_id = 1,
82
+ .version_id = 2,
83
+ .minimum_version_id = 2,
84
.fields = (VMStateField[]) {
85
VMSTATE_PTIMER(timer, CMSDKAPBTimer),
86
+ VMSTATE_CLOCK(pclk, CMSDKAPBTimer),
87
VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
88
VMSTATE_UINT32(value, CMSDKAPBTimer),
89
VMSTATE_UINT32(reload, CMSDKAPBTimer),
90
--
91
2.20.1
92
93
diff view generated by jsdifflib
New patch
1
As the first step in converting the CMSDK_APB_DUALTIMER device to the
2
Clock framework, add a Clock input. For the moment we do nothing
3
with this clock; we will change the behaviour from using the pclk-frq
4
property to using the Clock once all the users of this device have
5
been converted to wire up the Clock.
1
6
7
We take the opportunity to correct the name of the clock input to
8
match the hardware -- the dual timer names the clock which drives the
9
timers TIMCLK. (It does also have a 'pclk' input, which is used only
10
for the register and APB bus logic; on the SSE-200 these clocks are
11
both connected together.)
12
13
This is a migration compatibility break for machines mps2-an385,
14
mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
15
musca-b1.
16
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Reviewed-by: Luc Michel <luc@lmichel.fr>
20
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Message-id: 20210128114145.20536-9-peter.maydell@linaro.org
22
Message-id: 20210121190622.22000-9-peter.maydell@linaro.org
23
---
24
include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++
25
hw/timer/cmsdk-apb-dualtimer.c | 7 +++++--
26
2 files changed, 8 insertions(+), 2 deletions(-)
27
28
diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/timer/cmsdk-apb-dualtimer.h
31
+++ b/include/hw/timer/cmsdk-apb-dualtimer.h
32
@@ -XXX,XX +XXX,XX @@
33
*
34
* QEMU interface:
35
* + QOM property "pclk-frq": frequency at which the timer is clocked
36
+ * + Clock input "TIMCLK": clock (for both timers)
37
* + sysbus MMIO region 0: the register bank
38
* + sysbus IRQ 0: combined timer interrupt TIMINTC
39
* + sysbus IRO 1: timer block 1 interrupt TIMINT1
40
@@ -XXX,XX +XXX,XX @@
41
42
#include "hw/sysbus.h"
43
#include "hw/ptimer.h"
44
+#include "hw/clock.h"
45
#include "qom/object.h"
46
47
#define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
48
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBDualTimer {
49
MemoryRegion iomem;
50
qemu_irq timerintc;
51
uint32_t pclk_frq;
52
+ Clock *timclk;
53
54
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
55
uint32_t timeritcr;
56
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/timer/cmsdk-apb-dualtimer.c
59
+++ b/hw/timer/cmsdk-apb-dualtimer.c
60
@@ -XXX,XX +XXX,XX @@
61
#include "hw/irq.h"
62
#include "hw/qdev-properties.h"
63
#include "hw/registerfields.h"
64
+#include "hw/qdev-clock.h"
65
#include "hw/timer/cmsdk-apb-dualtimer.h"
66
#include "migration/vmstate.h"
67
68
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_init(Object *obj)
69
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
70
sysbus_init_irq(sbd, &s->timermod[i].timerint);
71
}
72
+ s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL);
73
}
74
75
static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
76
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_dualtimermod_vmstate = {
77
78
static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
79
.name = "cmsdk-apb-dualtimer",
80
- .version_id = 1,
81
- .minimum_version_id = 1,
82
+ .version_id = 2,
83
+ .minimum_version_id = 2,
84
.fields = (VMStateField[]) {
85
+ VMSTATE_CLOCK(timclk, CMSDKAPBDualTimer),
86
VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer,
87
CMSDK_APB_DUALTIMER_NUM_MODULES,
88
1, cmsdk_dualtimermod_vmstate,
89
--
90
2.20.1
91
92
diff view generated by jsdifflib
New patch
1
As the first step in converting the CMSDK_APB_TIMER device to the
2
Clock framework, add a Clock input. For the moment we do nothing
3
with this clock; we will change the behaviour from using the
4
wdogclk-frq property to using the Clock once all the users of this
5
device have been converted to wire up the Clock.
1
6
7
This is a migration compatibility break for machines mps2-an385,
8
mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
9
musca-b1, lm3s811evb, lm3s6965evb.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Luc Michel <luc@lmichel.fr>
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 20210128114145.20536-10-peter.maydell@linaro.org
16
Message-id: 20210121190622.22000-10-peter.maydell@linaro.org
17
---
18
include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++
19
hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++--
20
2 files changed, 8 insertions(+), 2 deletions(-)
21
22
diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
23
index XXXXXXX..XXXXXXX 100644
24
--- a/include/hw/watchdog/cmsdk-apb-watchdog.h
25
+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
26
@@ -XXX,XX +XXX,XX @@
27
*
28
* QEMU interface:
29
* + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
30
+ * + Clock input "WDOGCLK": clock for the watchdog's timer
31
* + sysbus MMIO region 0: the register bank
32
* + sysbus IRQ 0: watchdog interrupt
33
*
34
@@ -XXX,XX +XXX,XX @@
35
36
#include "hw/sysbus.h"
37
#include "hw/ptimer.h"
38
+#include "hw/clock.h"
39
#include "qom/object.h"
40
41
#define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
42
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBWatchdog {
43
uint32_t wdogclk_frq;
44
bool is_luminary;
45
struct ptimer_state *timer;
46
+ Clock *wdogclk;
47
48
uint32_t control;
49
uint32_t intstatus;
50
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/hw/watchdog/cmsdk-apb-watchdog.c
53
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
54
@@ -XXX,XX +XXX,XX @@
55
#include "hw/irq.h"
56
#include "hw/qdev-properties.h"
57
#include "hw/registerfields.h"
58
+#include "hw/qdev-clock.h"
59
#include "hw/watchdog/cmsdk-apb-watchdog.h"
60
#include "migration/vmstate.h"
61
62
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj)
63
s, "cmsdk-apb-watchdog", 0x1000);
64
sysbus_init_mmio(sbd, &s->iomem);
65
sysbus_init_irq(sbd, &s->wdogint);
66
+ s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL);
67
68
s->is_luminary = false;
69
s->id = cmsdk_apb_watchdog_id;
70
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
71
72
static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
73
.name = "cmsdk-apb-watchdog",
74
- .version_id = 1,
75
- .minimum_version_id = 1,
76
+ .version_id = 2,
77
+ .minimum_version_id = 2,
78
.fields = (VMStateField[]) {
79
+ VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog),
80
VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
81
VMSTATE_UINT32(control, CMSDKAPBWatchdog),
82
VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
83
--
84
2.20.1
85
86
diff view generated by jsdifflib
New patch
1
While we transition the ARMSSE code from integer properties
2
specifying clock frequencies to Clock objects, we want to have the
3
device provide both at once. We want the final name of the main
4
input Clock to be "MAINCLK", following the hardware name.
5
Unfortunately creating an input Clock with a name X creates an
6
under-the-hood QOM property X; for "MAINCLK" this clashes with the
7
existing UINT32 property of that name.
1
8
9
Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the
10
MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be
11
deleted.
12
13
Commit created with:
14
perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Reviewed-by: Luc Michel <luc@lmichel.fr>
19
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20210128114145.20536-11-peter.maydell@linaro.org
21
Message-id: 20210121190622.22000-11-peter.maydell@linaro.org
22
---
23
include/hw/arm/armsse.h | 2 +-
24
hw/arm/armsse.c | 6 +++---
25
hw/arm/mps2-tz.c | 2 +-
26
hw/arm/musca.c | 2 +-
27
4 files changed, 6 insertions(+), 6 deletions(-)
28
29
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/hw/arm/armsse.h
32
+++ b/include/hw/arm/armsse.h
33
@@ -XXX,XX +XXX,XX @@
34
* QEMU interface:
35
* + QOM property "memory" is a MemoryRegion containing the devices provided
36
* by the board model.
37
- * + QOM property "MAINCLK" is the frequency of the main system clock
38
+ * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
39
* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
40
* (In hardware, the SSE-200 permits the number of expansion interrupts
41
* for the two CPUs to be configured separately, but we restrict it to
42
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/armsse.c
45
+++ b/hw/arm/armsse.c
46
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
47
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
48
MemoryRegion *),
49
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
50
- DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
51
+ DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
52
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
53
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
54
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
55
@@ -XXX,XX +XXX,XX @@ static Property armsse_properties[] = {
56
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
57
MemoryRegion *),
58
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
59
- DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
60
+ DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
61
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
62
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
63
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
64
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
65
}
66
67
if (!s->mainclk_frq) {
68
- error_setg(errp, "MAINCLK property was not set");
69
+ error_setg(errp, "MAINCLK_FRQ property was not set");
70
return;
71
}
72
73
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/arm/mps2-tz.c
76
+++ b/hw/arm/mps2-tz.c
77
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
78
object_property_set_link(OBJECT(&mms->iotkit), "memory",
79
OBJECT(system_memory), &error_abort);
80
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
81
- qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
82
+ qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
83
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
84
85
/*
86
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/arm/musca.c
89
+++ b/hw/arm/musca.c
90
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
91
qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
92
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
93
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
94
- qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ);
95
+ qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
96
/*
97
* Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
98
* CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
99
--
100
2.20.1
101
102
diff view generated by jsdifflib
New patch
1
Create two input clocks on the ARMSSE devices, one for the normal
2
MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the
3
appropriate devices. The old property-based clock frequency setting
4
will remain in place until conversion is complete.
1
5
6
This is a migration compatibility break for machines mps2-an505,
7
mps2-an521, musca-a, musca-b1.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Luc Michel <luc@lmichel.fr>
12
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20210128114145.20536-12-peter.maydell@linaro.org
14
Message-id: 20210121190622.22000-12-peter.maydell@linaro.org
15
---
16
include/hw/arm/armsse.h | 6 ++++++
17
hw/arm/armsse.c | 17 +++++++++++++++--
18
2 files changed, 21 insertions(+), 2 deletions(-)
19
20
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/armsse.h
23
+++ b/include/hw/arm/armsse.h
24
@@ -XXX,XX +XXX,XX @@
25
* per-CPU identity and control register blocks
26
*
27
* QEMU interface:
28
+ * + Clock input "MAINCLK": clock for CPUs and most peripherals
29
+ * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
30
* + QOM property "memory" is a MemoryRegion containing the devices provided
31
* by the board model.
32
* + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
33
@@ -XXX,XX +XXX,XX @@
34
#include "hw/misc/armsse-mhu.h"
35
#include "hw/misc/unimp.h"
36
#include "hw/or-irq.h"
37
+#include "hw/clock.h"
38
#include "hw/core/split-irq.h"
39
#include "hw/cpu/cluster.h"
40
#include "qom/object.h"
41
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
42
43
uint32_t nsccfg;
44
45
+ Clock *mainclk;
46
+ Clock *s32kclk;
47
+
48
/* Properties */
49
MemoryRegion *board_memory;
50
uint32_t exp_numirq;
51
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/armsse.c
54
+++ b/hw/arm/armsse.c
55
@@ -XXX,XX +XXX,XX @@
56
#include "hw/arm/armsse.h"
57
#include "hw/arm/boot.h"
58
#include "hw/irq.h"
59
+#include "hw/qdev-clock.h"
60
61
/* Format of the System Information block SYS_CONFIG register */
62
typedef enum SysConfigFormat {
63
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
64
assert(info->sram_banks <= MAX_SRAM_BANKS);
65
assert(info->num_cpus <= SSE_MAX_CPUS);
66
67
+ s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL);
68
+ s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL);
69
+
70
memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
71
72
for (i = 0; i < info->num_cpus; i++) {
73
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
74
* map its upstream ends to the right place in the container.
75
*/
76
qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
77
+ qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk);
78
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) {
79
return;
80
}
81
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
82
&error_abort);
83
84
qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
85
+ qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk);
86
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) {
87
return;
88
}
89
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
90
&error_abort);
91
92
qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
93
+ qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk);
94
if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) {
95
return;
96
}
97
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
98
* 0x4002f000: S32K timer
99
*/
100
qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
101
+ qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk);
102
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) {
103
return;
104
}
105
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
106
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
107
108
qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
109
+ qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
110
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
111
return;
112
}
113
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
114
/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
115
116
qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
117
+ qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
118
if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
119
return;
120
}
121
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
122
sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
123
124
qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
125
+ qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
126
if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
127
return;
128
}
129
@@ -XXX,XX +XXX,XX @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
130
131
static const VMStateDescription armsse_vmstate = {
132
.name = "iotkit",
133
- .version_id = 1,
134
- .minimum_version_id = 1,
135
+ .version_id = 2,
136
+ .minimum_version_id = 2,
137
.fields = (VMStateField[]) {
138
+ VMSTATE_CLOCK(mainclk, ARMSSE),
139
+ VMSTATE_CLOCK(s32kclk, ARMSSE),
140
VMSTATE_UINT32(nsccfg, ARMSSE),
141
VMSTATE_END_OF_LIST()
142
}
143
--
144
2.20.1
145
146
diff view generated by jsdifflib
New patch
1
The old-style convenience function cmsdk_apb_timer_create() for
2
creating CMSDK_APB_TIMER objects is used in only two places in
3
mps2.c. Most of the rest of the code in that file uses the new
4
"initialize in place" coding style.
1
5
6
We want to connect up a Clock object which should be done between the
7
object creation and realization; rather than adding a Clock* argument
8
to the convenience function, convert the timer creation code in
9
mps2.c to the same style as is used already for the watchdog,
10
dualtimer and other devices, and delete the now-unused convenience
11
function.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Luc Michel <luc@lmichel.fr>
16
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20210128114145.20536-13-peter.maydell@linaro.org
18
Message-id: 20210121190622.22000-13-peter.maydell@linaro.org
19
---
20
include/hw/timer/cmsdk-apb-timer.h | 21 ---------------------
21
hw/arm/mps2.c | 18 ++++++++++++++++--
22
2 files changed, 16 insertions(+), 23 deletions(-)
23
24
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/timer/cmsdk-apb-timer.h
27
+++ b/include/hw/timer/cmsdk-apb-timer.h
28
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBTimer {
29
uint32_t intstatus;
30
};
31
32
-/**
33
- * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER
34
- * @addr: location in system memory to map registers
35
- * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
36
- */
37
-static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr,
38
- qemu_irq timerint,
39
- uint32_t pclk_frq)
40
-{
41
- DeviceState *dev;
42
- SysBusDevice *s;
43
-
44
- dev = qdev_new(TYPE_CMSDK_APB_TIMER);
45
- s = SYS_BUS_DEVICE(dev);
46
- qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
47
- sysbus_realize_and_unref(s, &error_fatal);
48
- sysbus_mmio_map(s, 0, addr);
49
- sysbus_connect_irq(s, 0, timerint);
50
- return dev;
51
-}
52
-
53
#endif
54
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/mps2.c
57
+++ b/hw/arm/mps2.c
58
@@ -XXX,XX +XXX,XX @@ struct MPS2MachineState {
59
/* CMSDK APB subsystem */
60
CMSDKAPBDualTimer dualtimer;
61
CMSDKAPBWatchdog watchdog;
62
+ CMSDKAPBTimer timer[2];
63
};
64
65
#define TYPE_MPS2_MACHINE "mps2"
66
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
67
}
68
69
/* CMSDK APB subsystem */
70
- cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
71
- cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
72
+ for (i = 0; i < ARRAY_SIZE(mms->timer); i++) {
73
+ g_autofree char *name = g_strdup_printf("timer%d", i);
74
+ hwaddr base = 0x40000000 + i * 0x1000;
75
+ int irqno = 8 + i;
76
+ SysBusDevice *sbd;
77
+
78
+ object_initialize_child(OBJECT(mms), name, &mms->timer[i],
79
+ TYPE_CMSDK_APB_TIMER);
80
+ sbd = SYS_BUS_DEVICE(&mms->timer[i]);
81
+ qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
82
+ sysbus_realize_and_unref(sbd, &error_fatal);
83
+ sysbus_mmio_map(sbd, 0, base);
84
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
85
+ }
86
+
87
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
88
TYPE_CMSDK_APB_DUALTIMER);
89
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
90
--
91
2.20.1
92
93
diff view generated by jsdifflib
New patch
1
Create a fixed-frequency Clock object to be the SYSCLK, and wire it
2
up to the devices that require it.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Luc Michel <luc@lmichel.fr>
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-14-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-14-peter.maydell@linaro.org
10
---
11
hw/arm/mps2.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/mps2.c
17
+++ b/hw/arm/mps2.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/net/lan9118.h"
20
#include "net/net.h"
21
#include "hw/watchdog/cmsdk-apb-watchdog.h"
22
+#include "hw/qdev-clock.h"
23
#include "qom/object.h"
24
25
typedef enum MPS2FPGAType {
26
@@ -XXX,XX +XXX,XX @@ struct MPS2MachineState {
27
CMSDKAPBDualTimer dualtimer;
28
CMSDKAPBWatchdog watchdog;
29
CMSDKAPBTimer timer[2];
30
+ Clock *sysclk;
31
};
32
33
#define TYPE_MPS2_MACHINE "mps2"
34
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
35
exit(EXIT_FAILURE);
36
}
37
38
+ /* This clock doesn't need migration because it is fixed-frequency */
39
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
40
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
41
+
42
/* The FPGA images have an odd combination of different RAMs,
43
* because in hardware they are different implementations and
44
* connected to different buses, giving varying performance/size
45
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
46
TYPE_CMSDK_APB_TIMER);
47
sbd = SYS_BUS_DEVICE(&mms->timer[i]);
48
qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
49
+ qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
50
sysbus_realize_and_unref(sbd, &error_fatal);
51
sysbus_mmio_map(sbd, 0, base);
52
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
53
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
54
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
55
TYPE_CMSDK_APB_DUALTIMER);
56
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
57
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
58
sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
59
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
60
qdev_get_gpio_in(armv7m, 10));
61
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
62
object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
63
TYPE_CMSDK_APB_WATCHDOG);
64
qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
65
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
66
sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
67
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
68
qdev_get_gpio_in_named(armv7m, "NMI", 0));
69
--
70
2.20.1
71
72
diff view generated by jsdifflib
New patch
1
Create and connect the two clocks needed by the ARMSSE.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210128114145.20536-15-peter.maydell@linaro.org
8
Message-id: 20210121190622.22000-15-peter.maydell@linaro.org
9
---
10
hw/arm/mps2-tz.c | 13 +++++++++++++
11
1 file changed, 13 insertions(+)
12
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/mps2-tz.c
16
+++ b/hw/arm/mps2-tz.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/net/lan9118.h"
19
#include "net/net.h"
20
#include "hw/core/split-irq.h"
21
+#include "hw/qdev-clock.h"
22
#include "qom/object.h"
23
24
#define MPS2TZ_NUMIRQ 92
25
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState {
26
qemu_or_irq uart_irq_orgate;
27
DeviceState *lan9118;
28
SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ];
29
+ Clock *sysclk;
30
+ Clock *s32kclk;
31
};
32
33
#define TYPE_MPS2TZ_MACHINE "mps2tz"
34
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
35
36
/* Main SYSCLK frequency in Hz */
37
#define SYSCLK_FRQ 20000000
38
+/* Slow 32Khz S32KCLK frequency in Hz */
39
+#define S32KCLK_FRQ (32 * 1000)
40
41
/* Create an alias of an entire original MemoryRegion @orig
42
* located at @base in the memory map.
43
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
44
exit(EXIT_FAILURE);
45
}
46
47
+ /* These clocks don't need migration because they are fixed-frequency */
48
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
49
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
50
+ mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
51
+ clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
52
+
53
object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
54
mmc->armsse_type);
55
iotkitdev = DEVICE(&mms->iotkit);
56
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
57
OBJECT(system_memory), &error_abort);
58
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
59
qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
60
+ qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
61
+ qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
62
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
63
64
/*
65
--
66
2.20.1
67
68
diff view generated by jsdifflib
New patch
1
Create and connect the two clocks needed by the ARMSSE.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20210128114145.20536-16-peter.maydell@linaro.org
8
Message-id: 20210121190622.22000-16-peter.maydell@linaro.org
9
---
10
hw/arm/musca.c | 12 ++++++++++++
11
1 file changed, 12 insertions(+)
12
13
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/musca.c
16
+++ b/hw/arm/musca.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/misc/tz-ppc.h"
19
#include "hw/misc/unimp.h"
20
#include "hw/rtc/pl031.h"
21
+#include "hw/qdev-clock.h"
22
#include "qom/object.h"
23
24
#define MUSCA_NUMIRQ_MAX 96
25
@@ -XXX,XX +XXX,XX @@ struct MuscaMachineState {
26
UnimplementedDeviceState sdio;
27
UnimplementedDeviceState gpio;
28
UnimplementedDeviceState cryptoisland;
29
+ Clock *sysclk;
30
+ Clock *s32kclk;
31
};
32
33
#define TYPE_MUSCA_MACHINE "musca"
34
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE)
35
* don't model that in our SSE-200 model yet.
36
*/
37
#define SYSCLK_FRQ 40000000
38
+/* Slow 32Khz S32KCLK frequency in Hz */
39
+#define S32KCLK_FRQ (32 * 1000)
40
41
static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
42
{
43
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
44
exit(1);
45
}
46
47
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
48
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
49
+ mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
50
+ clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
51
+
52
object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
53
TYPE_SSE200);
54
ssedev = DEVICE(&mms->sse);
55
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
56
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
57
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
58
qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
59
+ qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
60
+ qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
61
/*
62
* Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
63
* CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
64
--
65
2.20.1
66
67
diff view generated by jsdifflib
1
Give the Cortex-M0 ID register values corresponding to its
1
Convert the SSYS code in the Stellaris boards (which encapsulates the
2
implemented behaviour. These will not be guest-visible but will be
2
system registers) to a proper QOM device. This will provide us with
3
used to govern the behaviour of QEMU's emulation. We use the same
3
somewhere to put the output Clock whose frequency depends on the
4
values that the Cortex-M3 does.
4
setting of the PLL configuration registers.
5
6
This is a migration compatibility break for lm3s811evb, lm3s6965evb.
7
8
We use 3-phase reset here because the Clock will need to propagate
9
its value in the hold phase.
10
11
For the moment we reset the device during the board creation so that
12
the system_clock_scale global gets set; this will be removed in a
13
subsequent commit.
5
14
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
17
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Message-id: 20210128114145.20536-17-peter.maydell@linaro.org
20
Message-id: 20210121190622.22000-17-peter.maydell@linaro.org
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
---
22
---
10
target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++
23
hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++---------
11
1 file changed, 24 insertions(+)
24
1 file changed, 107 insertions(+), 25 deletions(-)
12
25
13
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
26
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
14
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu_tcg.c
28
--- a/hw/arm/stellaris.c
16
+++ b/target/arm/cpu_tcg.c
29
+++ b/hw/arm/stellaris.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_m0_initfn(Object *obj)
30
@@ -XXX,XX +XXX,XX @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
18
set_feature(&cpu->env, ARM_FEATURE_M);
31
19
32
/* System controller. */
20
cpu->midr = 0x410cc200;
33
34
-typedef struct {
35
+#define TYPE_STELLARIS_SYS "stellaris-sys"
36
+OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
37
+
38
+struct ssys_state {
39
+ SysBusDevice parent_obj;
40
+
41
MemoryRegion iomem;
42
uint32_t pborctl;
43
uint32_t ldopctl;
44
@@ -XXX,XX +XXX,XX @@ typedef struct {
45
uint32_t dcgc[3];
46
uint32_t clkvclr;
47
uint32_t ldoarst;
48
+ qemu_irq irq;
49
+ /* Properties (all read-only registers) */
50
uint32_t user0;
51
uint32_t user1;
52
- qemu_irq irq;
53
- stellaris_board_info *board;
54
-} ssys_state;
55
+ uint32_t did0;
56
+ uint32_t did1;
57
+ uint32_t dc0;
58
+ uint32_t dc1;
59
+ uint32_t dc2;
60
+ uint32_t dc3;
61
+ uint32_t dc4;
62
+};
63
64
static void ssys_update(ssys_state *s)
65
{
66
@@ -XXX,XX +XXX,XX @@ static uint32_t pllcfg_fury[16] = {
67
68
static int ssys_board_class(const ssys_state *s)
69
{
70
- uint32_t did0 = s->board->did0;
71
+ uint32_t did0 = s->did0;
72
switch (did0 & DID0_VER_MASK) {
73
case DID0_VER_0:
74
return DID0_CLASS_SANDSTORM;
75
@@ -XXX,XX +XXX,XX @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
76
77
switch (offset) {
78
case 0x000: /* DID0 */
79
- return s->board->did0;
80
+ return s->did0;
81
case 0x004: /* DID1 */
82
- return s->board->did1;
83
+ return s->did1;
84
case 0x008: /* DC0 */
85
- return s->board->dc0;
86
+ return s->dc0;
87
case 0x010: /* DC1 */
88
- return s->board->dc1;
89
+ return s->dc1;
90
case 0x014: /* DC2 */
91
- return s->board->dc2;
92
+ return s->dc2;
93
case 0x018: /* DC3 */
94
- return s->board->dc3;
95
+ return s->dc3;
96
case 0x01c: /* DC4 */
97
- return s->board->dc4;
98
+ return s->dc4;
99
case 0x030: /* PBORCTL */
100
return s->pborctl;
101
case 0x034: /* LDOPCTL */
102
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ssys_ops = {
103
.endianness = DEVICE_NATIVE_ENDIAN,
104
};
105
106
-static void ssys_reset(void *opaque)
107
+static void stellaris_sys_reset_enter(Object *obj, ResetType type)
108
{
109
- ssys_state *s = (ssys_state *)opaque;
110
+ ssys_state *s = STELLARIS_SYS(obj);
111
112
s->pborctl = 0x7ffd;
113
s->rcc = 0x078e3ac0;
114
@@ -XXX,XX +XXX,XX @@ static void ssys_reset(void *opaque)
115
s->rcgc[0] = 1;
116
s->scgc[0] = 1;
117
s->dcgc[0] = 1;
118
+}
119
+
120
+static void stellaris_sys_reset_hold(Object *obj)
121
+{
122
+ ssys_state *s = STELLARIS_SYS(obj);
123
+
124
ssys_calculate_system_clock(s);
125
}
126
127
+static void stellaris_sys_reset_exit(Object *obj)
128
+{
129
+}
130
+
131
static int stellaris_sys_post_load(void *opaque, int version_id)
132
{
133
ssys_state *s = opaque;
134
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_sys = {
135
}
136
};
137
138
+static Property stellaris_sys_properties[] = {
139
+ DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
140
+ DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
141
+ DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
142
+ DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
143
+ DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
144
+ DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
145
+ DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
146
+ DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
147
+ DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
148
+ DEFINE_PROP_END_OF_LIST()
149
+};
150
+
151
+static void stellaris_sys_instance_init(Object *obj)
152
+{
153
+ ssys_state *s = STELLARIS_SYS(obj);
154
+ SysBusDevice *sbd = SYS_BUS_DEVICE(s);
155
+
156
+ memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
157
+ sysbus_init_mmio(sbd, &s->iomem);
158
+ sysbus_init_irq(sbd, &s->irq);
159
+}
160
+
161
static int stellaris_sys_init(uint32_t base, qemu_irq irq,
162
stellaris_board_info * board,
163
uint8_t *macaddr)
164
{
165
- ssys_state *s;
166
+ DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
167
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
168
169
- s = g_new0(ssys_state, 1);
170
- s->irq = irq;
171
- s->board = board;
172
/* Most devices come preprogrammed with a MAC address in the user data. */
173
- s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
174
- s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
175
+ qdev_prop_set_uint32(dev, "user0",
176
+ macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
177
+ qdev_prop_set_uint32(dev, "user1",
178
+ macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
179
+ qdev_prop_set_uint32(dev, "did0", board->did0);
180
+ qdev_prop_set_uint32(dev, "did1", board->did1);
181
+ qdev_prop_set_uint32(dev, "dc0", board->dc0);
182
+ qdev_prop_set_uint32(dev, "dc1", board->dc1);
183
+ qdev_prop_set_uint32(dev, "dc2", board->dc2);
184
+ qdev_prop_set_uint32(dev, "dc3", board->dc3);
185
+ qdev_prop_set_uint32(dev, "dc4", board->dc4);
186
+
187
+ sysbus_realize_and_unref(sbd, &error_fatal);
188
+ sysbus_mmio_map(sbd, 0, base);
189
+ sysbus_connect_irq(sbd, 0, irq);
21
+
190
+
22
+ /*
191
+ /*
23
+ * These ID register values are not guest visible, because
192
+ * Normally we should not be resetting devices like this during
24
+ * we do not implement the Main Extension. They must be set
193
+ * board creation. For the moment we need to do so, because
25
+ * to values corresponding to the Cortex-M0's implemented
194
+ * system_clock_scale will only get set when the STELLARIS_SYS
26
+ * features, because QEMU generally controls its emulation
195
+ * device is reset, and we need its initial value to pass to
27
+ * by looking at ID register fields. We use the same values as
196
+ * the watchdog device. This hack can be removed once the
28
+ * for the M3.
197
+ * watchdog has been converted to use a Clock input instead.
29
+ */
198
+ */
30
+ cpu->isar.id_pfr0 = 0x00000030;
199
+ device_cold_reset(dev);
31
+ cpu->isar.id_pfr1 = 0x00000200;
200
32
+ cpu->isar.id_dfr0 = 0x00100000;
201
- memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
33
+ cpu->id_afr0 = 0x00000000;
202
- memory_region_add_subregion(get_system_memory(), base, &s->iomem);
34
+ cpu->isar.id_mmfr0 = 0x00000030;
203
- ssys_reset(s);
35
+ cpu->isar.id_mmfr1 = 0x00000000;
204
- vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s);
36
+ cpu->isar.id_mmfr2 = 0x00000000;
205
return 0;
37
+ cpu->isar.id_mmfr3 = 0x00000000;
38
+ cpu->isar.id_isar0 = 0x01141110;
39
+ cpu->isar.id_isar1 = 0x02111000;
40
+ cpu->isar.id_isar2 = 0x21112231;
41
+ cpu->isar.id_isar3 = 0x01111110;
42
+ cpu->isar.id_isar4 = 0x01310102;
43
+ cpu->isar.id_isar5 = 0x00000000;
44
+ cpu->isar.id_isar6 = 0x00000000;
45
}
206
}
46
207
47
static void cortex_m3_initfn(Object *obj)
208
-
209
/* I2C controller. */
210
211
#define TYPE_STELLARIS_I2C "stellaris-i2c"
212
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_adc_info = {
213
.class_init = stellaris_adc_class_init,
214
};
215
216
+static void stellaris_sys_class_init(ObjectClass *klass, void *data)
217
+{
218
+ DeviceClass *dc = DEVICE_CLASS(klass);
219
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
220
+
221
+ dc->vmsd = &vmstate_stellaris_sys;
222
+ rc->phases.enter = stellaris_sys_reset_enter;
223
+ rc->phases.hold = stellaris_sys_reset_hold;
224
+ rc->phases.exit = stellaris_sys_reset_exit;
225
+ device_class_set_props(dc, stellaris_sys_properties);
226
+}
227
+
228
+static const TypeInfo stellaris_sys_info = {
229
+ .name = TYPE_STELLARIS_SYS,
230
+ .parent = TYPE_SYS_BUS_DEVICE,
231
+ .instance_size = sizeof(ssys_state),
232
+ .instance_init = stellaris_sys_instance_init,
233
+ .class_init = stellaris_sys_class_init,
234
+};
235
+
236
static void stellaris_register_types(void)
237
{
238
type_register_static(&stellaris_i2c_info);
239
type_register_static(&stellaris_gptm_info);
240
type_register_static(&stellaris_adc_info);
241
+ type_register_static(&stellaris_sys_info);
242
}
243
244
type_init(stellaris_register_types)
48
--
245
--
49
2.20.1
246
2.20.1
50
247
51
248
diff view generated by jsdifflib
1
The M-profile definition of the MVFR1 ID register differs slightly
1
Create and connect the Clock input for the watchdog device on the
2
from the A-profile one, and in particular the check for "does the CPU
2
Stellaris boards. Because the Stellaris boards model the ability to
3
support fp16 arithmetic" is not the same.
3
change the clock rate by programming PLL registers, we have to create
4
an output Clock on the ssys_state device and wire it up to the
5
watchdog.
4
6
5
We don't currently implement any M-profile CPUs with fp16 arithmetic,
7
Note that the old comment on ssys_calculate_system_clock() got the
6
so this is not yet a visible bug, but correcting the logic now
8
units wrong -- system_clock_scale is in nanoseconds, not
7
disarms this beartrap for when we eventually do.
9
milliseconds. Improve the commentary to clarify how we are
10
calculating the period.
8
11
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Luc Michel <luc@lmichel.fr>
11
Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20210128114145.20536-18-peter.maydell@linaro.org
17
Message-id: 20210121190622.22000-18-peter.maydell@linaro.org
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
---
19
---
13
target/arm/cpu.h | 31 ++++++++++++++++++++++++++-----
20
hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------
14
1 file changed, 26 insertions(+), 5 deletions(-)
21
1 file changed, 31 insertions(+), 12 deletions(-)
15
22
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
17
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
25
--- a/hw/arm/stellaris.c
19
+++ b/target/arm/cpu.h
26
+++ b/hw/arm/stellaris.c
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
27
@@ -XXX,XX +XXX,XX @@
21
FIELD(ID_MMFR4, CCIDX, 24, 4)
28
#include "hw/watchdog/cmsdk-apb-watchdog.h"
22
FIELD(ID_MMFR4, EVT, 28, 4)
29
#include "migration/vmstate.h"
23
30
#include "hw/misc/unimp.h"
24
+FIELD(ID_PFR1, PROGMOD, 0, 4)
31
+#include "hw/qdev-clock.h"
25
+FIELD(ID_PFR1, SECURITY, 4, 4)
32
#include "cpu.h"
26
+FIELD(ID_PFR1, MPROGMOD, 8, 4)
33
#include "qom/object.h"
27
+FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
34
28
+FIELD(ID_PFR1, GENTIMER, 16, 4)
35
@@ -XXX,XX +XXX,XX @@ struct ssys_state {
29
+FIELD(ID_PFR1, SEC_FRAC, 20, 4)
36
uint32_t clkvclr;
30
+FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
37
uint32_t ldoarst;
31
+FIELD(ID_PFR1, GIC, 28, 4)
38
qemu_irq irq;
32
+
39
+ Clock *sysclk;
33
FIELD(ID_AA64ISAR0, AES, 4, 4)
40
/* Properties (all read-only registers) */
34
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
41
uint32_t user0;
35
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
42
uint32_t user1;
36
@@ -XXX,XX +XXX,XX @@ FIELD(MVFR0, FPROUND, 28, 4)
43
@@ -XXX,XX +XXX,XX @@ static bool ssys_use_rcc2(ssys_state *s)
37
38
FIELD(MVFR1, FPFTZ, 0, 4)
39
FIELD(MVFR1, FPDNAN, 4, 4)
40
-FIELD(MVFR1, SIMDLS, 8, 4)
41
-FIELD(MVFR1, SIMDINT, 12, 4)
42
-FIELD(MVFR1, SIMDSP, 16, 4)
43
-FIELD(MVFR1, SIMDHP, 20, 4)
44
+FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
45
+FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
46
+FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
47
+FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
48
+FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
49
+FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
50
FIELD(MVFR1, FPHP, 24, 4)
51
FIELD(MVFR1, SIMDFMAC, 28, 4)
52
53
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
54
return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
55
}
44
}
56
45
57
+static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
46
/*
58
+{
47
- * Caculate the sys. clock period in ms.
59
+ return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
48
+ * Calculate the system clock period. We only want to propagate
60
+}
49
+ * this change to the rest of the system if we're not being called
61
+
50
+ * from migration post-load.
62
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
51
*/
52
-static void ssys_calculate_system_clock(ssys_state *s)
53
+static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
63
{
54
{
64
- return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
55
+ /*
65
+ /* Sadly this is encoded differently for A-profile and M-profile */
56
+ * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
66
+ if (isar_feature_aa32_mprofile(id)) {
57
+ * clock is 200MHz, which is a period of 5 ns. Dividing the clock
67
+ return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
58
+ * frequency by X is the same as multiplying the period by X.
68
+ } else {
59
+ */
69
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
60
if (ssys_use_rcc2(s)) {
61
system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
62
} else {
63
system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
64
}
65
+ clock_set_ns(s->sysclk, system_clock_scale);
66
+ if (propagate_clock) {
67
+ clock_propagate(s->sysclk);
70
+ }
68
+ }
71
}
69
}
72
70
73
static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
71
static void ssys_write(void *opaque, hwaddr offset,
72
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
73
s->int_status |= (1 << 6);
74
}
75
s->rcc = value;
76
- ssys_calculate_system_clock(s);
77
+ ssys_calculate_system_clock(s, true);
78
break;
79
case 0x070: /* RCC2 */
80
if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
81
@@ -XXX,XX +XXX,XX @@ static void ssys_write(void *opaque, hwaddr offset,
82
s->int_status |= (1 << 6);
83
}
84
s->rcc2 = value;
85
- ssys_calculate_system_clock(s);
86
+ ssys_calculate_system_clock(s, true);
87
break;
88
case 0x100: /* RCGC0 */
89
s->rcgc[0] = value;
90
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_reset_hold(Object *obj)
91
{
92
ssys_state *s = STELLARIS_SYS(obj);
93
94
- ssys_calculate_system_clock(s);
95
+ /* OK to propagate clocks from the hold phase */
96
+ ssys_calculate_system_clock(s, true);
97
}
98
99
static void stellaris_sys_reset_exit(Object *obj)
100
@@ -XXX,XX +XXX,XX @@ static int stellaris_sys_post_load(void *opaque, int version_id)
101
{
102
ssys_state *s = opaque;
103
104
- ssys_calculate_system_clock(s);
105
+ ssys_calculate_system_clock(s, false);
106
107
return 0;
108
}
109
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_sys = {
110
VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
111
VMSTATE_UINT32(clkvclr, ssys_state),
112
VMSTATE_UINT32(ldoarst, ssys_state),
113
+ /* No field for sysclk -- handled in post-load instead */
114
VMSTATE_END_OF_LIST()
115
}
116
};
117
@@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj)
118
memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
119
sysbus_init_mmio(sbd, &s->iomem);
120
sysbus_init_irq(sbd, &s->irq);
121
+ s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
122
}
123
124
-static int stellaris_sys_init(uint32_t base, qemu_irq irq,
125
- stellaris_board_info * board,
126
- uint8_t *macaddr)
127
+static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
128
+ stellaris_board_info *board,
129
+ uint8_t *macaddr)
130
{
131
DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
132
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
133
@@ -XXX,XX +XXX,XX @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
134
*/
135
device_cold_reset(dev);
136
137
- return 0;
138
+ return dev;
139
}
140
141
/* I2C controller. */
142
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
143
int flash_size;
144
I2CBus *i2c;
145
DeviceState *dev;
146
+ DeviceState *ssys_dev;
147
int i;
148
int j;
149
150
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
151
}
152
}
153
154
- stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
155
- board, nd_table[0].macaddr.a);
156
+ ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
157
+ board, nd_table[0].macaddr.a);
158
159
160
if (board->dc1 & (1 << 3)) { /* watchdog present */
161
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
162
/* system_clock_scale is valid now */
163
uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
164
qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
165
+ qdev_connect_clock_in(dev, "WDOGCLK",
166
+ qdev_get_clock_out(ssys_dev, "SYSCLK"));
167
168
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
169
sysbus_mmio_map(SYS_BUS_DEVICE(dev),
74
--
170
--
75
2.20.1
171
2.20.1
76
172
77
173
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Switch the CMSDK APB timer device over to using its Clock input; the
2
pclk-frq property is now ignored.
2
3
3
We expected the 'version' ID to match the board processor ID,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
but this is not always true (for example boards with revision
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
id 0xa02042/0xa22042 are Raspberry Pi 2 with a BCM2837 SoC).
6
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
This was not important because we were not modelling them, but
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
since the recent refactor now allow to model these boards, it
8
Message-id: 20210128114145.20536-19-peter.maydell@linaro.org
8
is safer to check the processor id directly. Remove the version
9
Message-id: 20210121190622.22000-19-peter.maydell@linaro.org
9
check.
10
---
11
hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++----
12
1 file changed, 14 insertions(+), 4 deletions(-)
10
13
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
14
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
12
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200924111808.77168-9-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/raspi.c | 29 +++++++++++++----------------
18
1 file changed, 13 insertions(+), 16 deletions(-)
19
20
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/raspi.c
16
--- a/hw/timer/cmsdk-apb-timer.c
23
+++ b/hw/arm/raspi.c
17
+++ b/hw/timer/cmsdk-apb-timer.c
24
@@ -XXX,XX +XXX,XX @@ static RaspiProcessorId board_processor_id(uint32_t board_rev)
18
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
25
return proc_id;
19
ptimer_transaction_commit(s->timer);
26
}
20
}
27
21
28
-static int board_version(uint32_t board_rev)
22
+static void cmsdk_apb_timer_clk_update(void *opaque)
29
-{
23
+{
30
- return board_processor_id(board_rev) + 1;
24
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
31
-}
25
+
32
-
26
+ ptimer_transaction_begin(s->timer);
33
static const char *board_soc_type(uint32_t board_rev)
27
+ ptimer_set_period_from_clock(s->timer, s->pclk, 1);
28
+ ptimer_transaction_commit(s->timer);
29
+}
30
+
31
static void cmsdk_apb_timer_init(Object *obj)
34
{
32
{
35
return soc_property[board_processor_id(board_rev)].type;
33
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
36
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
34
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_init(Object *obj)
37
cpu_set_pc(cs, info->smp_loader_start);
35
s, "cmsdk-apb-timer", 0x1000);
36
sysbus_init_mmio(sbd, &s->iomem);
37
sysbus_init_irq(sbd, &s->timerint);
38
- s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
39
+ s->pclk = qdev_init_clock_in(DEVICE(s), "pclk",
40
+ cmsdk_apb_timer_clk_update, s);
38
}
41
}
39
42
40
-static void setup_boot(MachineState *machine, int version, size_t ram_size)
43
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
41
+static void setup_boot(MachineState *machine, RaspiProcessorId processor_id,
42
+ size_t ram_size)
43
{
44
{
44
RaspiMachineState *s = RASPI_MACHINE(machine);
45
CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
45
int r;
46
46
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
47
- if (s->pclk_frq == 0) {
47
s->binfo.ram_size = ram_size;
48
- error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
48
s->binfo.nb_cpus = machine->smp.cpus;
49
+ if (!clock_has_source(s->pclk)) {
49
50
+ error_setg(errp, "CMSDK APB timer: pclk clock must be connected");
50
- if (version <= 2) {
51
return;
51
- /* The rpi1 and 2 require some custom setup code to run in Secure
52
- * mode before booting a kernel (to set up the SMC vectors so
53
- * that we get a no-op SMC; this is used by Linux to call the
54
+ if (processor_id <= PROCESSOR_ID_BCM2836) {
55
+ /*
56
+ * The BCM2835 and BCM2836 require some custom setup code to run
57
+ * in Secure mode before booting a kernel (to set up the SMC vectors
58
+ * so that we get a no-op SMC; this is used by Linux to call the
59
* firmware for some cache maintenance operations.
60
- * The rpi3 doesn't need this.
61
+ * The BCM2837 doesn't need this.
62
*/
63
s->binfo.board_setup_addr = BOARDSETUP_ADDR;
64
s->binfo.write_board_setup = write_board_setup;
65
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
66
s->binfo.secure_boot = true;
67
}
52
}
68
53
69
- /* Pi2 and Pi3 requires SMP setup */
54
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
70
- if (version >= 2) {
55
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
71
+ /* BCM2836 and BCM2837 requires SMP setup */
56
72
+ if (processor_id >= PROCESSOR_ID_BCM2836) {
57
ptimer_transaction_begin(s->timer);
73
s->binfo.smp_loader_start = SMPBOOT_ADDR;
58
- ptimer_set_freq(s->timer, s->pclk_frq);
74
- if (version == 2) {
59
+ ptimer_set_period_from_clock(s->timer, s->pclk, 1);
75
+ if (processor_id == PROCESSOR_ID_BCM2836) {
60
ptimer_transaction_commit(s->timer);
76
s->binfo.write_secondary_boot = write_smpboot;
77
} else {
78
s->binfo.write_secondary_boot = write_smpboot64;
79
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
80
RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
81
RaspiMachineState *s = RASPI_MACHINE(machine);
82
uint32_t board_rev = mc->board_rev;
83
- int version = board_version(board_rev);
84
uint64_t ram_size = board_ram_size(board_rev);
85
uint32_t vcram_size;
86
DriveInfo *di;
87
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
88
89
vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
90
&error_abort);
91
- setup_boot(machine, version, machine->ram_size - vcram_size);
92
+ setup_boot(machine, board_processor_id(mc->board_rev),
93
+ machine->ram_size - vcram_size);
94
}
61
}
95
62
96
static void raspi_machine_class_common_init(MachineClass *mc,
97
--
63
--
98
2.20.1
64
2.20.1
99
65
100
66
diff view generated by jsdifflib
1
The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN
1
Switch the CMSDK APB dualtimer device over to using its Clock input;
2
bit in short-descriptor translation table format descriptors. This
2
the pclk-frq property is now ignored.
3
is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the
4
feature bit with an ID register check, in line with our preference
5
for ID register checks over feature bits.
6
3
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
9
Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-20-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-20-peter.maydell@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
---
11
---
11
target/arm/cpu.h | 15 ++++++++++++++-
12
hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++----
12
target/arm/cpu.c | 1 -
13
1 file changed, 37 insertions(+), 5 deletions(-)
13
target/arm/helper.c | 5 +++--
14
3 files changed, 17 insertions(+), 4 deletions(-)
15
14
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
17
--- a/hw/timer/cmsdk-apb-dualtimer.c
19
+++ b/target/arm/cpu.h
18
+++ b/hw/timer/cmsdk-apb-dualtimer.c
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4)
19
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s)
21
FIELD(ID_ISAR6, SB, 12, 4)
20
qemu_set_irq(s->timerintc, timintc);
22
FIELD(ID_ISAR6, SPECRES, 16, 4)
23
24
+FIELD(ID_MMFR0, VMSA, 0, 4)
25
+FIELD(ID_MMFR0, PMSA, 4, 4)
26
+FIELD(ID_MMFR0, OUTERSHR, 8, 4)
27
+FIELD(ID_MMFR0, SHARELVL, 12, 4)
28
+FIELD(ID_MMFR0, TCM, 16, 4)
29
+FIELD(ID_MMFR0, AUXREG, 20, 4)
30
+FIELD(ID_MMFR0, FCSE, 24, 4)
31
+FIELD(ID_MMFR0, INNERSHR, 28, 4)
32
+
33
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
34
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
35
FIELD(ID_MMFR3, BPMAINT, 8, 4)
36
@@ -XXX,XX +XXX,XX @@ enum arm_features {
37
ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
38
ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
39
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
40
- ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
41
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
42
ARM_FEATURE_V8,
43
ARM_FEATURE_AARCH64, /* supports 64 bit mode */
44
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
45
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
46
}
21
}
47
22
48
+static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
23
+static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m)
49
+{
24
+{
50
+ return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
25
+ /* Return the divisor set by the current CONTROL.PRESCALE value */
26
+ switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) {
27
+ case 0:
28
+ return 1;
29
+ case 1:
30
+ return 16;
31
+ case 2:
32
+ case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */
33
+ return 256;
34
+ default:
35
+ g_assert_not_reached();
36
+ }
51
+}
37
+}
52
+
38
+
53
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
39
static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
40
uint32_t newctrl)
54
{
41
{
55
return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
42
@@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
56
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
43
default:
57
index XXXXXXX..XXXXXXX 100644
44
g_assert_not_reached();
58
--- a/target/arm/cpu.c
45
}
59
+++ b/target/arm/cpu.c
46
- ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor);
60
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
47
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor);
61
}
48
}
62
if (arm_feature(env, ARM_FEATURE_LPAE)) {
49
63
set_feature(env, ARM_FEATURE_V7MP);
50
if (changed & R_CONTROL_MODE_MASK) {
64
- set_feature(env, ARM_FEATURE_PXN);
51
@@ -XXX,XX +XXX,XX @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m)
52
* limit must both be set to 0xffff, so we wrap at 16 bits.
53
*/
54
ptimer_set_limit(m->timer, 0xffff, 1);
55
- ptimer_set_freq(m->timer, m->parent->pclk_frq);
56
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk,
57
+ cmsdk_dualtimermod_divisor(m));
58
ptimer_transaction_commit(m->timer);
59
}
60
61
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev)
62
s->timeritop = 0;
63
}
64
65
+static void cmsdk_apb_dualtimer_clk_update(void *opaque)
66
+{
67
+ CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque);
68
+ int i;
69
+
70
+ for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
71
+ CMSDKAPBDualTimerModule *m = &s->timermod[i];
72
+ ptimer_transaction_begin(m->timer);
73
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk,
74
+ cmsdk_dualtimermod_divisor(m));
75
+ ptimer_transaction_commit(m->timer);
76
+ }
77
+}
78
+
79
static void cmsdk_apb_dualtimer_init(Object *obj)
80
{
81
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
82
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_init(Object *obj)
83
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
84
sysbus_init_irq(sbd, &s->timermod[i].timerint);
65
}
85
}
66
if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
86
- s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL);
67
set_feature(env, ARM_FEATURE_CBAR);
87
+ s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK",
68
diff --git a/target/arm/helper.c b/target/arm/helper.c
88
+ cmsdk_apb_dualtimer_clk_update, s);
69
index XXXXXXX..XXXXXXX 100644
89
}
70
--- a/target/arm/helper.c
90
71
+++ b/target/arm/helper.c
91
static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
72
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
92
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
73
target_ulong *page_size, ARMMMUFaultInfo *fi)
93
CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev);
74
{
94
int i;
75
CPUState *cs = env_cpu(env);
95
76
+ ARMCPU *cpu = env_archcpu(env);
96
- if (s->pclk_frq == 0) {
77
int level = 1;
97
- error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
78
uint32_t table;
98
+ if (!clock_has_source(s->timclk)) {
79
uint32_t desc;
99
+ error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected");
80
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
100
return;
81
goto do_fault;
82
}
101
}
83
type = (desc & 3);
102
84
- if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
85
+ if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
86
/* Section translation fault, or attempt to use the encoding
87
* which is Reserved on implementations without PXN.
88
*/
89
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
90
pxn = desc & 1;
91
ns = extract32(desc, 19, 1);
92
} else {
93
- if (arm_feature(env, ARM_FEATURE_PXN)) {
94
+ if (cpu_isar_feature(aa32_pxn, cpu)) {
95
pxn = (desc >> 2) & 1;
96
}
97
ns = extract32(desc, 3, 1);
98
--
103
--
99
2.20.1
104
2.20.1
100
105
101
106
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Switch the CMSDK APB watchdog device over to using its Clock input;
2
the wdogclk_frq property is now ignored.
2
3
3
The 'first_cpu' is more a QEMU accelerator-related concept
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
than a variable the machine requires to use.
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Since the machine is aware of its CPUs, directly use the
6
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
first one to load the firmware.
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20210128114145.20536-21-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-21-peter.maydell@linaro.org
10
---
11
hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++----
12
1 file changed, 14 insertions(+), 4 deletions(-)
7
13
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
14
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200924111808.77168-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/raspi.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
16
--- a/hw/watchdog/cmsdk-apb-watchdog.c
19
+++ b/hw/arm/raspi.c
17
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
20
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
18
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev)
21
19
ptimer_transaction_commit(s->timer);
22
static void setup_boot(MachineState *machine, int version, size_t ram_size)
20
}
21
22
+static void cmsdk_apb_watchdog_clk_update(void *opaque)
23
+{
24
+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
25
+
26
+ ptimer_transaction_begin(s->timer);
27
+ ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
28
+ ptimer_transaction_commit(s->timer);
29
+}
30
+
31
static void cmsdk_apb_watchdog_init(Object *obj)
23
{
32
{
24
+ RaspiMachineState *s = RASPI_MACHINE(machine);
33
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
25
static struct arm_boot_info binfo;
34
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj)
26
int r;
35
s, "cmsdk-apb-watchdog", 0x1000);
27
36
sysbus_init_mmio(sbd, &s->iomem);
28
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
37
sysbus_init_irq(sbd, &s->wdogint);
29
binfo.firmware_loaded = true;
38
- s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL);
39
+ s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK",
40
+ cmsdk_apb_watchdog_clk_update, s);
41
42
s->is_luminary = false;
43
s->id = cmsdk_apb_watchdog_id;
44
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
45
{
46
CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
47
48
- if (s->wdogclk_frq == 0) {
49
+ if (!clock_has_source(s->wdogclk)) {
50
error_setg(errp,
51
- "CMSDK APB watchdog: wdogclk-frq property must be set");
52
+ "CMSDK APB watchdog: WDOGCLK clock must be connected");
53
return;
30
}
54
}
31
55
32
- arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
56
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
33
+ arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
57
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
58
59
ptimer_transaction_begin(s->timer);
60
- ptimer_set_freq(s->timer, s->wdogclk_frq);
61
+ ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
62
ptimer_transaction_commit(s->timer);
34
}
63
}
35
64
36
static void raspi_machine_init(MachineState *machine)
37
--
65
--
38
2.20.1
66
2.20.1
39
67
40
68
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Now that the CMSDK APB watchdog uses its Clock input, it will
2
correctly respond when the system clock frequency is changed using
3
the RCC register on in the Stellaris board system registers. Test
4
that when the RCC register is written it causes the watchdog timer to
5
change speed.
2
6
3
The Raspberry firmware is closed-source. While running it, it
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
accesses various I/O registers. Logging these accesses as UNIMP
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
(unimplemented) help to understand what the firmware is doing
9
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
(ideally we want it able to boot a Linux kernel).
10
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20210128114145.20536-22-peter.maydell@linaro.org
12
Message-id: 20210121190622.22000-22-peter.maydell@linaro.org
13
---
14
tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++
15
1 file changed, 52 insertions(+)
7
16
8
Document various blocks we might use later.
17
diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c
9
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
13
Message-id: 20200921034729.432931-2-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/raspi_platform.h | 51 +++++++++++++++++++++++++++------
17
1 file changed, 43 insertions(+), 8 deletions(-)
18
19
diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/raspi_platform.h
19
--- a/tests/qtest/cmsdk-apb-watchdog-test.c
22
+++ b/include/hw/arm/raspi_platform.h
20
+++ b/tests/qtest/cmsdk-apb-watchdog-test.c
23
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
24
* You should have received a copy of the GNU General Public License
25
* along with this program; if not, write to the Free Software
26
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27
+ *
28
+ * Various undocumented addresses and names come from Herman Hermitage's VC4
29
+ * documentation:
30
+ * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
31
*/
22
*/
32
23
33
#ifndef HW_ARM_RASPI_PLATFORM_H
24
#include "qemu/osdep.h"
34
#define HW_ARM_RASPI_PLATFORM_H
25
+#include "qemu/bitops.h"
35
26
#include "libqtest-single.h"
36
#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
27
37
-#define IC0_OFFSET 0x2000
28
/*
38
+#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
39
+#define INTE_OFFSET 0x2000 /* VC Interrupt controller */
40
#define ST_OFFSET 0x3000 /* System Timer */
41
+#define TXP_OFFSET 0x4000 /* Transposer */
42
+#define JPEG_OFFSET 0x5000
43
#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
44
#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
45
-#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
46
+#define ARBA_OFFSET 0x9000
47
+#define BRDG_OFFSET 0xa000
48
+#define ARM_OFFSET 0xB000 /* ARM control block */
49
#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
50
#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
51
-#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
52
+#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
53
#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
54
* Doorbells & Mailboxes */
55
#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
56
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@
57
#define AVS_OFFSET 0x103000 /* Audio Video Standard */
30
#define WDOGMIS 0x14
58
#define RNG_OFFSET 0x104000
31
#define WDOGLOCK 0xc00
59
#define GPIO_OFFSET 0x200000
32
60
-#define UART0_OFFSET 0x201000
33
+#define SSYS_BASE 0x400fe000
61
-#define MMCI0_OFFSET 0x202000
34
+#define RCC 0x60
62
-#define I2S_OFFSET 0x203000
35
+#define SYSDIV_SHIFT 23
63
-#define SPI0_OFFSET 0x204000
36
+#define SYSDIV_LENGTH 4
64
+#define UART0_OFFSET 0x201000 /* PL011 */
37
+
65
+#define MMCI0_OFFSET 0x202000 /* Legacy MMC */
38
static void test_watchdog(void)
66
+#define I2S_OFFSET 0x203000 /* PCM */
39
{
67
+#define SPI0_OFFSET 0x204000 /* SPI master */
40
g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
68
#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
41
@@ -XXX,XX +XXX,XX @@ static void test_watchdog(void)
69
+#define PIXV0_OFFSET 0x206000
42
g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
70
+#define PIXV1_OFFSET 0x207000
43
}
71
+#define DPI_OFFSET 0x208000
44
72
+#define DSI0_OFFSET 0x209000 /* Display Serial Interface */
45
+static void test_clock_change(void)
73
+#define PWM_OFFSET 0x20c000
46
+{
74
+#define PERM_OFFSET 0x20d000
47
+ uint32_t rcc;
75
+#define TEC_OFFSET 0x20e000
48
+
76
#define OTP_OFFSET 0x20f000
49
+ /*
77
+#define SLIM_OFFSET 0x210000 /* SLIMbus */
50
+ * Test that writing to the stellaris board's RCC register to
78
+#define CPG_OFFSET 0x211000
51
+ * change the system clock frequency causes the watchdog
79
#define THERMAL_OFFSET 0x212000
52
+ * to change the speed it counts at.
80
-#define BSC_SL_OFFSET 0x214000 /* SPI slave */
53
+ */
81
+#define AVSP_OFFSET 0x213000
54
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
82
+#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */
55
+
83
#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */
56
+ writel(WDOG_BASE + WDOGCONTROL, 1);
84
#define EMMC1_OFFSET 0x300000
57
+ writel(WDOG_BASE + WDOGLOAD, 1000);
85
+#define EMMC2_OFFSET 0x340000
58
+
86
+#define HVS_OFFSET 0x400000
59
+ /* Step to just past the 500th tick */
87
#define SMI_OFFSET 0x600000
60
+ clock_step(80 * 500 + 1);
88
+#define DSI1_OFFSET 0x700000
61
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
89
+#define UCAM_OFFSET 0x800000
62
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
90
+#define CMI_OFFSET 0x802000
63
+
91
#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
64
+ /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */
92
#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */
65
+ rcc = readl(SSYS_BASE + RCC);
93
+#define VECA_OFFSET 0x806000
66
+ g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf);
94
+#define PIXV2_OFFSET 0x807000
67
+ rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7);
95
+#define HDMI_OFFSET 0x808000
68
+ writel(SSYS_BASE + RCC, rcc);
96
+#define HDCP_OFFSET 0x809000
69
+
97
+#define ARBR0_OFFSET 0x80a000
70
+ /* Just past the 1000th tick: timer should have fired */
98
#define DBUS_OFFSET 0x900000
71
+ clock_step(40 * 500);
99
#define AVE0_OFFSET 0x910000
72
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
100
#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */
73
+
101
+#define V3D_OFFSET 0xc00000
74
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
102
#define SDRAMC_OFFSET 0xe00000
75
+
103
+#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */
76
+ /* VALUE reloads at following tick */
104
+#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */
77
+ clock_step(41);
105
+#define ARBR1_OFFSET 0xe04000
78
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
106
#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
79
+
107
+#define DCRC_OFFSET 0xe07000
80
+ /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
108
+#define AXIP_OFFSET 0xe08000
81
+ clock_step(40 * 500);
109
82
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
110
/* GPU interrupts */
83
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
111
#define INTERRUPT_TIMER0 0
84
+ writel(WDOG_BASE + WDOGINTCLR, 0);
85
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
86
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
87
+}
88
+
89
int main(int argc, char **argv)
90
{
91
int r;
92
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
93
qtest_start("-machine lm3s811evb");
94
95
qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
96
+ qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change",
97
+ test_clock_change);
98
99
r = g_test_run();
100
112
--
101
--
113
2.20.1
102
2.20.1
114
103
115
104
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Use the MAINCLK Clock input to set the system_clock_scale variable
2
rather than using the mainclk_frq property.
2
3
3
The arm_boot_info structure belong to the machine,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
move it to RaspiMachineState.
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Message-id: 20210128114145.20536-23-peter.maydell@linaro.org
9
Message-id: 20210121190622.22000-23-peter.maydell@linaro.org
10
---
11
hw/arm/armsse.c | 24 +++++++++++++++++++-----
12
1 file changed, 19 insertions(+), 5 deletions(-)
5
13
6
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
14
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200924111808.77168-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/raspi.c | 30 +++++++++++++++---------------
12
1 file changed, 15 insertions(+), 15 deletions(-)
13
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/raspi.c
16
--- a/hw/arm/armsse.c
17
+++ b/hw/arm/raspi.c
17
+++ b/hw/arm/armsse.c
18
@@ -XXX,XX +XXX,XX @@ struct RaspiMachineState {
18
@@ -XXX,XX +XXX,XX @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
19
MachineState parent_obj;
19
qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
20
/*< public >*/
20
}
21
BCM283XState soc;
21
22
+ struct arm_boot_info binfo;
22
+static void armsse_mainclk_update(void *opaque)
23
};
23
+{
24
typedef struct RaspiMachineState RaspiMachineState;
24
+ ARMSSE *s = ARM_SSE(opaque);
25
25
+ /*
26
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
26
+ * Set system_clock_scale from our Clock input; this is what
27
static void setup_boot(MachineState *machine, int version, size_t ram_size)
27
+ * controls the tick rate of the CPU SysTick timer.
28
+ */
29
+ system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
30
+}
31
+
32
static void armsse_init(Object *obj)
28
{
33
{
29
RaspiMachineState *s = RASPI_MACHINE(machine);
34
ARMSSE *s = ARM_SSE(obj);
30
- static struct arm_boot_info binfo;
35
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
31
int r;
36
assert(info->sram_banks <= MAX_SRAM_BANKS);
32
37
assert(info->num_cpus <= SSE_MAX_CPUS);
33
- binfo.board_id = MACH_TYPE_BCM2708;
38
34
- binfo.ram_size = ram_size;
39
- s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL);
35
- binfo.nb_cpus = machine->smp.cpus;
40
+ s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK",
36
+ s->binfo.board_id = MACH_TYPE_BCM2708;
41
+ armsse_mainclk_update, s);
37
+ s->binfo.ram_size = ram_size;
42
s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL);
38
+ s->binfo.nb_cpus = machine->smp.cpus;
43
39
44
memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
40
if (version <= 2) {
45
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
41
/* The rpi1 and 2 require some custom setup code to run in Secure
46
return;
42
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
43
* firmware for some cache maintenance operations.
44
* The rpi3 doesn't need this.
45
*/
46
- binfo.board_setup_addr = BOARDSETUP_ADDR;
47
- binfo.write_board_setup = write_board_setup;
48
- binfo.secure_board_setup = true;
49
- binfo.secure_boot = true;
50
+ s->binfo.board_setup_addr = BOARDSETUP_ADDR;
51
+ s->binfo.write_board_setup = write_board_setup;
52
+ s->binfo.secure_board_setup = true;
53
+ s->binfo.secure_boot = true;
54
}
47
}
55
48
56
/* Pi2 and Pi3 requires SMP setup */
49
- if (!s->mainclk_frq) {
57
if (version >= 2) {
50
- error_setg(errp, "MAINCLK_FRQ property was not set");
58
- binfo.smp_loader_start = SMPBOOT_ADDR;
51
- return;
59
+ s->binfo.smp_loader_start = SMPBOOT_ADDR;
52
+ if (!clock_has_source(s->mainclk)) {
60
if (version == 2) {
53
+ error_setg(errp, "MAINCLK clock was not connected");
61
- binfo.write_secondary_boot = write_smpboot;
54
+ }
62
+ s->binfo.write_secondary_boot = write_smpboot;
55
+ if (!clock_has_source(s->s32kclk)) {
63
} else {
56
+ error_setg(errp, "S32KCLK clock was not connected");
64
- binfo.write_secondary_boot = write_smpboot64;
65
+ s->binfo.write_secondary_boot = write_smpboot64;
66
}
67
- binfo.secondary_cpu_reset_hook = reset_secondary;
68
+ s->binfo.secondary_cpu_reset_hook = reset_secondary;
69
}
57
}
70
58
71
/* If the user specified a "firmware" image (e.g. UEFI), we bypass
59
assert(info->num_cpus <= SSE_MAX_CPUS);
72
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
60
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
73
exit(1);
61
*/
74
}
62
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
75
63
76
- binfo.entry = firmware_addr;
64
- system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq;
77
- binfo.firmware_loaded = true;
65
+ /* Set initial system_clock_scale from MAINCLK */
78
+ s->binfo.entry = firmware_addr;
66
+ armsse_mainclk_update(s);
79
+ s->binfo.firmware_loaded = true;
80
}
81
82
- arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
83
+ arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo);
84
}
67
}
85
68
86
static void raspi_machine_init(MachineState *machine)
69
static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
87
--
70
--
88
2.20.1
71
2.20.1
89
72
90
73
diff view generated by jsdifflib
1
M-profile CPUs only implement the ID registers as guest-visible if
1
Remove all the code that sets frequency properties on the CMSDK
2
the CPU implements the Main Extension (all our current CPUs except
2
timer, dualtimer and watchdog devices and on the ARMSSE SoC device:
3
the Cortex-M0 do).
3
these properties are unused now that the devices rely on their Clock
4
4
inputs instead.
5
Currently we handle this by having the Cortex-M0 leave the ID
6
register values in the ARMCPU struct as zero, but this conflicts with
7
our design decision to make QEMU behaviour be keyed off ID register
8
fields wherever possible.
9
10
Explicitly code the ID registers in the NVIC to return 0 if the Main
11
Extension is not implemented, so we can make the M0 model set the
12
ARMCPU struct fields to obtain the correct behaviour without those
13
values becoming guest-visible.
14
5
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20200910173855.4068-4-peter.maydell@linaro.org
8
Reviewed-by: Luc Michel <luc@lmichel.fr>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210128114145.20536-24-peter.maydell@linaro.org
11
Message-id: 20210121190622.22000-24-peter.maydell@linaro.org
18
---
12
---
19
hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++
13
hw/arm/armsse.c | 7 -------
20
1 file changed, 42 insertions(+)
14
hw/arm/mps2-tz.c | 1 -
15
hw/arm/mps2.c | 3 ---
16
hw/arm/musca.c | 1 -
17
hw/arm/stellaris.c | 3 ---
18
5 files changed, 15 deletions(-)
21
19
22
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
20
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
23
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/intc/armv7m_nvic.c
22
--- a/hw/arm/armsse.c
25
+++ b/hw/intc/armv7m_nvic.c
23
+++ b/hw/arm/armsse.c
26
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
24
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
27
"Aux Fault status registers unimplemented\n");
25
* it to the appropriate PPC port; then we can realize the PPC and
28
return 0;
26
* map its upstream ends to the right place in the container.
29
case 0xd40: /* PFR0. */
27
*/
30
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
28
- qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
31
+ goto bad_offset;
29
qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk);
32
+ }
30
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) {
33
return cpu->isar.id_pfr0;
31
return;
34
case 0xd44: /* PFR1. */
32
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
35
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
33
object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr),
36
+ goto bad_offset;
34
&error_abort);
37
+ }
35
38
return cpu->isar.id_pfr1;
36
- qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
39
case 0xd48: /* DFR0. */
37
qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk);
40
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
38
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) {
41
+ goto bad_offset;
39
return;
42
+ }
40
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
43
return cpu->isar.id_dfr0;
41
object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr),
44
case 0xd4c: /* AFR0. */
42
&error_abort);
45
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
43
46
+ goto bad_offset;
44
- qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
47
+ }
45
qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk);
48
return cpu->id_afr0;
46
if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) {
49
case 0xd50: /* MMFR0. */
47
return;
50
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
48
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
51
+ goto bad_offset;
49
/* Devices behind APB PPC1:
52
+ }
50
* 0x4002f000: S32K timer
53
return cpu->isar.id_mmfr0;
51
*/
54
case 0xd54: /* MMFR1. */
52
- qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
55
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
53
qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk);
56
+ goto bad_offset;
54
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) {
57
+ }
55
return;
58
return cpu->isar.id_mmfr1;
56
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
59
case 0xd58: /* MMFR2. */
57
qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
60
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
58
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
61
+ goto bad_offset;
59
62
+ }
60
- qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
63
return cpu->isar.id_mmfr2;
61
qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
64
case 0xd5c: /* MMFR3. */
62
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
65
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
63
return;
66
+ goto bad_offset;
64
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
67
+ }
65
68
return cpu->isar.id_mmfr3;
66
/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
69
case 0xd60: /* ISAR0. */
67
70
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
68
- qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
71
+ goto bad_offset;
69
qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
72
+ }
70
if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
73
return cpu->isar.id_isar0;
71
return;
74
case 0xd64: /* ISAR1. */
72
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
75
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
73
armsse_get_common_irq_in(s, 1));
76
+ goto bad_offset;
74
sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
77
+ }
75
78
return cpu->isar.id_isar1;
76
- qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
79
case 0xd68: /* ISAR2. */
77
qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
80
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
78
if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
81
+ goto bad_offset;
79
return;
82
+ }
80
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
83
return cpu->isar.id_isar2;
81
index XXXXXXX..XXXXXXX 100644
84
case 0xd6c: /* ISAR3. */
82
--- a/hw/arm/mps2-tz.c
85
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
83
+++ b/hw/arm/mps2-tz.c
86
+ goto bad_offset;
84
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
87
+ }
85
object_property_set_link(OBJECT(&mms->iotkit), "memory",
88
return cpu->isar.id_isar3;
86
OBJECT(system_memory), &error_abort);
89
case 0xd70: /* ISAR4. */
87
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
90
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
88
- qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
91
+ goto bad_offset;
89
qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
92
+ }
90
qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
93
return cpu->isar.id_isar4;
91
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
94
case 0xd74: /* ISAR5. */
92
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
95
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
93
index XXXXXXX..XXXXXXX 100644
96
+ goto bad_offset;
94
--- a/hw/arm/mps2.c
97
+ }
95
+++ b/hw/arm/mps2.c
98
return cpu->isar.id_isar5;
96
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
99
case 0xd78: /* CLIDR */
97
object_initialize_child(OBJECT(mms), name, &mms->timer[i],
100
return cpu->clidr;
98
TYPE_CMSDK_APB_TIMER);
99
sbd = SYS_BUS_DEVICE(&mms->timer[i]);
100
- qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
101
qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
102
sysbus_realize_and_unref(sbd, &error_fatal);
103
sysbus_mmio_map(sbd, 0, base);
104
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
105
106
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
107
TYPE_CMSDK_APB_DUALTIMER);
108
- qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
109
qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
110
sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
111
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
112
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
113
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
114
object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
115
TYPE_CMSDK_APB_WATCHDOG);
116
- qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
117
qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
118
sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
119
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
120
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
121
index XXXXXXX..XXXXXXX 100644
122
--- a/hw/arm/musca.c
123
+++ b/hw/arm/musca.c
124
@@ -XXX,XX +XXX,XX @@ static void musca_init(MachineState *machine)
125
qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
126
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
127
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
128
- qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
129
qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
130
qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
131
/*
132
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
133
index XXXXXXX..XXXXXXX 100644
134
--- a/hw/arm/stellaris.c
135
+++ b/hw/arm/stellaris.c
136
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
137
if (board->dc1 & (1 << 3)) { /* watchdog present */
138
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
139
140
- /* system_clock_scale is valid now */
141
- uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
142
- qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
143
qdev_connect_clock_in(dev, "WDOGCLK",
144
qdev_get_clock_out(ssys_dev, "SYSCLK"));
145
101
--
146
--
102
2.20.1
147
2.20.1
103
148
104
149
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Now no users are setting the frq properties on the CMSDK timer,
2
dualtimer, watchdog or ARMSSE SoC devices, we can remove the
3
properties and the struct fields that back them.
2
4
3
As we only support a reduced set of the REV_CODE_PROCESSOR id
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
encoded in the board revision, define the PROCESSOR_ID values
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
as an enum. We can simplify the board_soc_type and cores_count
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
methods.
8
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210128114145.20536-25-peter.maydell@linaro.org
10
Message-id: 20210121190622.22000-25-peter.maydell@linaro.org
11
---
12
include/hw/arm/armsse.h | 2 --
13
include/hw/timer/cmsdk-apb-dualtimer.h | 2 --
14
include/hw/timer/cmsdk-apb-timer.h | 2 --
15
include/hw/watchdog/cmsdk-apb-watchdog.h | 2 --
16
hw/arm/armsse.c | 2 --
17
hw/timer/cmsdk-apb-dualtimer.c | 6 ------
18
hw/timer/cmsdk-apb-timer.c | 6 ------
19
hw/watchdog/cmsdk-apb-watchdog.c | 6 ------
20
8 files changed, 28 deletions(-)
7
21
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
22
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200924111808.77168-7-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/raspi.c | 45 +++++++++++++++++++++------------------------
14
1 file changed, 21 insertions(+), 24 deletions(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
24
--- a/include/hw/arm/armsse.h
19
+++ b/hw/arm/raspi.c
25
+++ b/include/hw/arm/armsse.h
20
@@ -XXX,XX +XXX,XX @@ FIELD(REV_CODE, MANUFACTURER, 16, 4);
26
@@ -XXX,XX +XXX,XX @@
21
FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
27
* + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
22
FIELD(REV_CODE, STYLE, 23, 1);
28
* + QOM property "memory" is a MemoryRegion containing the devices provided
23
29
* by the board model.
24
+typedef enum RaspiProcessorId {
30
- * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
25
+ PROCESSOR_ID_BCM2836 = 1,
31
* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
26
+ PROCESSOR_ID_BCM2837 = 2,
32
* (In hardware, the SSE-200 permits the number of expansion interrupts
27
+} RaspiProcessorId;
33
* for the two CPUs to be configured separately, but we restrict it to
28
+
34
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
29
+static const struct {
35
/* Properties */
30
+ const char *type;
36
MemoryRegion *board_memory;
31
+ int cores_count;
37
uint32_t exp_numirq;
32
+} soc_property[] = {
38
- uint32_t mainclk_frq;
33
+ [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
39
uint32_t sram_addr_width;
34
+ [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
40
uint32_t init_svtor;
35
+};
41
bool cpu_fpu[SSE_MAX_CPUS];
36
+
42
diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h
37
static uint64_t board_ram_size(uint32_t board_rev)
43
index XXXXXXX..XXXXXXX 100644
44
--- a/include/hw/timer/cmsdk-apb-dualtimer.h
45
+++ b/include/hw/timer/cmsdk-apb-dualtimer.h
46
@@ -XXX,XX +XXX,XX @@
47
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
48
*
49
* QEMU interface:
50
- * + QOM property "pclk-frq": frequency at which the timer is clocked
51
* + Clock input "TIMCLK": clock (for both timers)
52
* + sysbus MMIO region 0: the register bank
53
* + sysbus IRQ 0: combined timer interrupt TIMINTC
54
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBDualTimer {
55
/*< public >*/
56
MemoryRegion iomem;
57
qemu_irq timerintc;
58
- uint32_t pclk_frq;
59
Clock *timclk;
60
61
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
62
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/hw/timer/cmsdk-apb-timer.h
65
+++ b/include/hw/timer/cmsdk-apb-timer.h
66
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
67
68
/*
69
* QEMU interface:
70
- * + QOM property "pclk-frq": frequency at which the timer is clocked
71
* + Clock input "pclk": clock for the timer
72
* + sysbus MMIO region 0: the register bank
73
* + sysbus IRQ 0: timer interrupt TIMERINT
74
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBTimer {
75
/*< public >*/
76
MemoryRegion iomem;
77
qemu_irq timerint;
78
- uint32_t pclk_frq;
79
struct ptimer_state *timer;
80
Clock *pclk;
81
82
diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/watchdog/cmsdk-apb-watchdog.h
85
+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
86
@@ -XXX,XX +XXX,XX @@
87
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
88
*
89
* QEMU interface:
90
- * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
91
* + Clock input "WDOGCLK": clock for the watchdog's timer
92
* + sysbus MMIO region 0: the register bank
93
* + sysbus IRQ 0: watchdog interrupt
94
@@ -XXX,XX +XXX,XX @@ struct CMSDKAPBWatchdog {
95
/*< public >*/
96
MemoryRegion iomem;
97
qemu_irq wdogint;
98
- uint32_t wdogclk_frq;
99
bool is_luminary;
100
struct ptimer_state *timer;
101
Clock *wdogclk;
102
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/arm/armsse.c
105
+++ b/hw/arm/armsse.c
106
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
107
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
108
MemoryRegion *),
109
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
110
- DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
111
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
112
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
113
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
114
@@ -XXX,XX +XXX,XX @@ static Property armsse_properties[] = {
115
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
116
MemoryRegion *),
117
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
118
- DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
119
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
120
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
121
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
122
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
123
index XXXXXXX..XXXXXXX 100644
124
--- a/hw/timer/cmsdk-apb-dualtimer.c
125
+++ b/hw/timer/cmsdk-apb-dualtimer.c
126
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
127
}
128
};
129
130
-static Property cmsdk_apb_dualtimer_properties[] = {
131
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0),
132
- DEFINE_PROP_END_OF_LIST(),
133
-};
134
-
135
static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
38
{
136
{
39
assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
137
DeviceClass *dc = DEVICE_CLASS(klass);
40
return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
138
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
139
dc->realize = cmsdk_apb_dualtimer_realize;
140
dc->vmsd = &cmsdk_apb_dualtimer_vmstate;
141
dc->reset = cmsdk_apb_dualtimer_reset;
142
- device_class_set_props(dc, cmsdk_apb_dualtimer_properties);
41
}
143
}
42
144
43
-static int board_processor_id(uint32_t board_rev)
145
static const TypeInfo cmsdk_apb_dualtimer_info = {
44
+static RaspiProcessorId board_processor_id(uint32_t board_rev)
146
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/hw/timer/cmsdk-apb-timer.c
149
+++ b/hw/timer/cmsdk-apb-timer.c
150
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
151
}
152
};
153
154
-static Property cmsdk_apb_timer_properties[] = {
155
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
156
- DEFINE_PROP_END_OF_LIST(),
157
-};
158
-
159
static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
45
{
160
{
46
+ int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
161
DeviceClass *dc = DEVICE_CLASS(klass);
47
+
162
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
48
assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
163
dc->realize = cmsdk_apb_timer_realize;
49
- return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
164
dc->vmsd = &cmsdk_apb_timer_vmstate;
50
+ assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type);
165
dc->reset = cmsdk_apb_timer_reset;
51
+
166
- device_class_set_props(dc, cmsdk_apb_timer_properties);
52
+ return proc_id;
53
}
167
}
54
168
55
static int board_version(uint32_t board_rev)
169
static const TypeInfo cmsdk_apb_timer_info = {
56
@@ -XXX,XX +XXX,XX @@ static int board_version(uint32_t board_rev)
170
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
57
171
index XXXXXXX..XXXXXXX 100644
58
static const char *board_soc_type(uint32_t board_rev)
172
--- a/hw/watchdog/cmsdk-apb-watchdog.c
173
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
174
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
175
}
176
};
177
178
-static Property cmsdk_apb_watchdog_properties[] = {
179
- DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
180
- DEFINE_PROP_END_OF_LIST(),
181
-};
182
-
183
static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
59
{
184
{
60
- static const char *soc_types[] = {
185
DeviceClass *dc = DEVICE_CLASS(klass);
61
- NULL, TYPE_BCM2836, TYPE_BCM2837,
186
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
62
- };
187
dc->realize = cmsdk_apb_watchdog_realize;
63
- int proc_id = board_processor_id(board_rev);
188
dc->vmsd = &cmsdk_apb_watchdog_vmstate;
64
-
189
dc->reset = cmsdk_apb_watchdog_reset;
65
- if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
190
- device_class_set_props(dc, cmsdk_apb_watchdog_properties);
66
- error_report("Unsupported processor id '%d' (board revision: 0x%x)",
67
- proc_id, board_rev);
68
- exit(1);
69
- }
70
- return soc_types[proc_id];
71
+ return soc_property[board_processor_id(board_rev)].type;
72
}
191
}
73
192
74
static int cores_count(uint32_t board_rev)
193
static const TypeInfo cmsdk_apb_watchdog_info = {
75
{
76
- static const int soc_cores_count[] = {
77
- 0, BCM283X_NCPUS, BCM283X_NCPUS,
78
- };
79
- int proc_id = board_processor_id(board_rev);
80
-
81
- if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
82
- error_report("Unsupported processor id '%d' (board revision: 0x%x)",
83
- proc_id, board_rev);
84
- exit(1);
85
- }
86
- return soc_cores_count[proc_id];
87
+ return soc_property[board_processor_id(board_rev)].cores_count;
88
}
89
90
static const char *board_type(uint32_t board_rev)
91
--
194
--
92
2.20.1
195
2.20.1
93
196
94
197
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Now that the watchdog device uses its Clock input rather than being
2
passed the value of system_clock_scale at creation time, we can
3
remove the hack where we reset the STELLARIS_SYS at board creation
4
time to force it to set system_clock_scale. Instead it will be reset
5
at the usual point in startup and will inform the watchdog of the
6
clock frequency at that point.
2
7
3
The bcm2835-v3d is used since Linux 4.7, see commit
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
49ac67e0c39c ("ARM: bcm2835: Add VC4 to the device tree"),
9
Reviewed-by: Luc Michel <luc@lmichel.fr>
5
and the bcm2835-txp since Linux 4.19, see commit
10
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
b7dd29b401f5 ("ARM: dts: bcm283x: Add Transposer block").
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20210128114145.20536-26-peter.maydell@linaro.org
13
Message-id: 20210121190622.22000-26-peter.maydell@linaro.org
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
---
16
hw/arm/stellaris.c | 10 ----------
17
1 file changed, 10 deletions(-)
7
18
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Message-id: 20200921034729.432931-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/bcm2835_peripherals.h | 2 ++
14
hw/arm/bcm2835_peripherals.c | 2 ++
15
2 files changed, 4 insertions(+)
16
17
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/bcm2835_peripherals.h
21
--- a/hw/arm/stellaris.c
20
+++ b/include/hw/arm/bcm2835_peripherals.h
22
+++ b/hw/arm/stellaris.c
21
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
23
@@ -XXX,XX +XXX,XX @@ static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
22
24
sysbus_mmio_map(sbd, 0, base);
23
BCM2835SystemTimerState systmr;
25
sysbus_connect_irq(sbd, 0, irq);
24
BCM2835MphiState mphi;
26
25
+ UnimplementedDeviceState txp;
27
- /*
26
UnimplementedDeviceState armtmr;
28
- * Normally we should not be resetting devices like this during
27
UnimplementedDeviceState cprman;
29
- * board creation. For the moment we need to do so, because
28
UnimplementedDeviceState a2w;
30
- * system_clock_scale will only get set when the STELLARIS_SYS
29
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
31
- * device is reset, and we need its initial value to pass to
30
UnimplementedDeviceState otp;
32
- * the watchdog device. This hack can be removed once the
31
UnimplementedDeviceState dbus;
33
- * watchdog has been converted to use a Clock input instead.
32
UnimplementedDeviceState ave0;
34
- */
33
+ UnimplementedDeviceState v3d;
35
- device_cold_reset(dev);
34
UnimplementedDeviceState bscsl;
36
-
35
UnimplementedDeviceState smi;
37
return dev;
36
DWC2State dwc2;
37
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/arm/bcm2835_peripherals.c
40
+++ b/hw/arm/bcm2835_peripherals.c
41
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
42
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
43
INTERRUPT_USB));
44
45
+ create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
46
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
47
create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
48
create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
50
create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
51
create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
52
create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
53
+ create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000);
54
create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
55
}
38
}
56
39
57
--
40
--
58
2.20.1
41
2.20.1
59
42
60
43
diff view generated by jsdifflib