From: Frank Chang <frank.chang@sifive.com>
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cf9718908e..21eeb4b791 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -56,6 +56,11 @@ static int fs(CPURISCVState *env, int csrno)
static int vs(CPURISCVState *env, int csrno)
{
if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -1;
+ }
+#endif
return 0;
}
return -1;
--
2.17.1