This is the first revision that has been fully tested vs ArmIE,
although only with 128-bit vectors.
Since ArmIE does not produce an SVE signal frame, I have a small
hack in RISU to pull the vector data from the FP frame. I may try
an assembly wrapper to capture the larger vector data before it
gets clobbered by AdvSIMD usage within libc (especially memset),
but it wasn't especially urgent.
r~
Richard Henderson (63):
target/arm: Fix sve_uzp_p vs odd vector lengths
target/arm: Fix sve_zip_p vs odd vector lengths
target/arm: Fix sve_punpk_p vs odd vector lengths
target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2
target/arm: Implement SVE2 Integer Multiply - Unpredicated
target/arm: Implement SVE2 integer pairwise add and accumulate long
target/arm: Implement SVE2 integer unary operations (predicated)
target/arm: Split out saturating/rounding shifts from neon
target/arm: Implement SVE2 saturating/rounding bitwise shift left
(predicated)
target/arm: Implement SVE2 integer halving add/subtract (predicated)
target/arm: Implement SVE2 integer pairwise arithmetic
target/arm: Implement SVE2 saturating add/subtract (predicated)
target/arm: Implement SVE2 integer add/subtract long
target/arm: Implement SVE2 integer add/subtract interleaved long
target/arm: Implement SVE2 integer add/subtract wide
target/arm: Implement SVE2 integer multiply long
target/arm: Implement PMULLB and PMULLT
target/arm: Implement SVE2 bitwise shift left long
target/arm: Implement SVE2 bitwise exclusive-or interleaved
target/arm: Implement SVE2 bitwise permute
target/arm: Implement SVE2 complex integer add
target/arm: Implement SVE2 integer absolute difference and accumulate
long
target/arm: Implement SVE2 integer add/subtract long with carry
target/arm: Implement SVE2 bitwise shift right and accumulate
target/arm: Implement SVE2 bitwise shift and insert
target/arm: Implement SVE2 integer absolute difference and accumulate
target/arm: Implement SVE2 saturating extract narrow
target/arm: Implement SVE2 SHRN, RSHRN
target/arm: Implement SVE2 SQSHRUN, SQRSHRUN
target/arm: Implement SVE2 UQSHRN, UQRSHRN
target/arm: Implement SVE2 SQSHRN, SQRSHRN
target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
target/arm: Implement SVE2 WHILERW, WHILEWR
target/arm: Implement SVE2 bitwise ternary operations
target/arm: Implement SVE2 saturating multiply-add long
target/arm: Implement SVE2 saturating multiply-add high
target/arm: Implement SVE2 integer multiply-add long
target/arm: Implement SVE2 complex integer multiply-add
target/arm: Implement SVE2 XAR
target/arm: Pass separate addend to {U,S}DOT helpers
target/arm: Pass separate addend to FCMLA helpers
target/arm: Split out formats for 2 vectors + 1 index
target/arm: Split out formats for 3 vectors + 1 index
target/arm: Implement SVE2 integer multiply (indexed)
target/arm: Implement SVE2 integer multiply-add (indexed)
target/arm: Implement SVE2 saturating multiply-add high (indexed)
target/arm: Implement SVE2 saturating multiply-add (indexed)
target/arm: Implement SVE2 integer multiply long (indexed)
target/arm: Implement SVE2 saturating multiply (indexed)
target/arm: Implement SVE2 signed saturating doubling multiply high
target/arm: Implement SVE2 saturating multiply high (indexed)
target/arm: Implement SVE2 multiply-add long (indexed)
target/arm: Implement SVE2 complex integer multiply-add (indexed)
target/arm: Implement SVE mixed sign dot product (indexed)
target/arm: Implement SVE mixed sign dot product
target/arm: Implement SVE2 crypto unary operations
target/arm: Implement SVE2 crypto destructive binary operations
target/arm: Implement SVE2 crypto constructive binary operations
target/arm: Share table of sve load functions
target/arm: Implement SVE2 LD1RO
target/arm: Implement 128-bit ZIP, UZP, TRN
target/arm: Implement SVE2 complex integer dot product
target/arm: Enable SVE2 and some extensions
Stephen Long (18):
target/arm: Implement SVE2 floating-point pairwise
target/arm: Implement SVE2 MATCH, NMATCH
target/arm: Implement SVE2 ADDHNB, ADDHNT
target/arm: Implement SVE2 RADDHNB, RADDHNT
target/arm: Implement SVE2 SUBHNB, SUBHNT
target/arm: Implement SVE2 RSUBHNB, RSUBHNT
target/arm: Implement SVE2 HISTCNT, HISTSEG
target/arm: Implement SVE2 scatter store insns
target/arm: Implement SVE2 gather load insns
target/arm: Implement SVE2 FMMLA
target/arm: Implement SVE2 SPLICE, EXT
target/arm: Implement SVE2 TBL, TBX
target/arm: Implement SVE2 FCVTNT
target/arm: Implement SVE2 FCVTLT
target/arm: Implement SVE2 FCVTXNT, FCVTX
target/arm: Implement SVE2 FLOGB
target/arm: Implement SVE2 bitwise shift immediate
target/arm: Implement SVE2 fp multiply-add long
target/arm/cpu.h | 56 +
target/arm/helper-sve.h | 722 ++++++-
target/arm/helper.h | 104 +-
target/arm/translate-a64.h | 3 +
target/arm/vec_internal.h | 143 ++
target/arm/sve.decode | 568 +++++-
target/arm/cpu64.c | 11 +
target/arm/helper.c | 3 +-
target/arm/kvm64.c | 11 +
target/arm/neon_helper.c | 507 +----
target/arm/sve_helper.c | 2175 +++++++++++++++++++--
target/arm/translate-a64.c | 67 +-
target/arm/translate-sve.c | 3152 +++++++++++++++++++++++++++++--
target/arm/vec_helper.c | 767 +++++++-
target/arm/translate-neon.c.inc | 20 +-
15 files changed, 7443 insertions(+), 866 deletions(-)
--
2.25.1