Series comparison

 [PULL 00/36] target-arm queue
-Nuvoton new board models, and some more minor stuff. I also put
+First pullreq for 6.0: mostly my v8.1M work, plus some other
-in the deprecation patches for unicore32 and lm32.
+bits and pieces. (I still have a lot of stuff in my to-review
 folder, which I may or may not get to before the Christmas break...)
 thanks
 -- PMM
-The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
+The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:
-  Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
+  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210
-for you to fetch changes up to dd44ae00fc5342ed99acb68ec3508f76a71d523a:
+for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:
-  MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller (2020-09-14 14:27:08 +0100)
+  hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * hw/misc/a9scu: Do not allow invalid CPU count
+ * hw/arm/smmuv3: Fix up L1STD_SPAN decoding
- * hw/misc/a9scu: Minor cleanups
+ * xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
- * hw/timer/armv7m_systick: assert that board code set system_clock_scale
+ * sbsa-ref: allow to use Cortex-A53/57/72 cpus
- * decodetree: Improve identifier matching
+ * Various minor code cleanups
- * target/arm: Clean up neon fp insn size field decode
+ * hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
- * target/arm: Remove KVM support for 32-bit Arm hosts
+ * Implement more pieces of ARMv8.1M support
  * hw/arm/mps2: New board models mps2-an386, mps2-an500
  * Deprecate Unicore32 port
  * Deprecate lm32 port
  * target/arm: Count PMU events when MDCR.SPME is set
  * hw/arm: versal-virt: Correct the tx/rx GEM clocks
  * New Nuvoton iBMC board models npcm750-evb, quanta-gsj
  * xlnx-zynqmp: implement ZynqMP CAN controllers
 ----------------------------------------------------------------
-Aaron Lindsay (1):
+Alex Chen (4):
-      target/arm: Count PMU events when MDCR.SPME is set
+      i.MX25: Fix bad printf format specifiers
       i.MX31: Fix bad printf format specifiers
       i.MX6: Fix bad printf format specifiers
       i.MX6ul: Fix bad printf format specifiers
-Edgar E. Iglesias (1):
+Havard Skinnemoen (1):
-      hw/arm: versal-virt: Correct the tx/rx GEM clocks
+      tests/qtest/npcm7xx_rng-test: dump random data on failure
-Havard Skinnemoen (14):
+Kunkun Jiang (1):
-      hw/misc: Add NPCM7xx System Global Control Registers device model
+      hw/arm/smmuv3: Fix up L1STD_SPAN decoding
       hw/misc: Add NPCM7xx Clock Controller device model
       hw/timer: Add NPCM7xx Timer device model
       hw/arm: Add NPCM730 and NPCM750 SoC models
       hw/arm: Add two NPCM7xx-based machines
       roms: Add virtual Boot ROM for NPCM7xx SoCs
       hw/arm: Load -bios image as a boot ROM for npcm7xx
       hw/nvram: NPCM7xx OTP device model
       hw/mem: Stubbed out NPCM7xx Memory Controller model
       hw/ssi: NPCM7xx Flash Interface Unit device model
       hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
       hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
       docs/system: Add Nuvoton machine documentation
       tests/acceptance: console boot tests for quanta-gsj
-Peter Maydell (11):
+Marcin Juszkiewicz (1):
-      hw/timer/armv7m_systick: assert that board code set system_clock_scale
+      sbsa-ref: allow to use Cortex-A53/57/72 cpus
       target/arm: Convert Neon 3-same-fp size field to MO_* in decode
       target/arm: Convert Neon VCVT fp size field to MO_* in decode
       target/arm: Convert VCMLA, VCADD size field to MO_* in decode
       target/arm: Remove KVM support for 32-bit Arm hosts
       target/arm: Remove no-longer-reachable 32-bit KVM code
       hw/arm/mps2: New board model mps2-an386
       hw/arm/mps2: New board model mps2-an500
       docs/system/arm/mps2.rst: Make board list consistent
       Deprecate Unicore32 port
       Deprecate lm32 port
-Philippe Mathieu-Daudé (4):
+Peter Maydell (25):
-      hw/misc/a9scu: Do not allow invalid CPU count
+      hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
-      hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
+      target/arm: Implement v8.1M PXN extension
-      hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
+      target/arm: Don't clobber ID_PFR1.Security on M-profile cores
-      hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
+      target/arm: Implement VSCCLRM insn
+      target/arm: Implement CLRM instruction
-Richard Henderson (1):
+      target/arm: Enforce M-profile VMRS/VMSR register restrictions
-      decodetree: Improve identifier matching
+      target/arm: Refactor M-profile VMSR/VMRS handling
       target/arm: Move general-use constant expanders up in translate.c
       target/arm: Implement VLDR/VSTR system register
       target/arm: Implement M-profile FPSCR_nzcvqc
       target/arm: Use new FPCR_NZCV_MASK constant
       target/arm: Factor out preserve-fp-state from full_vfp_access_check()
       target/arm: Implement FPCXT_S fp system register
       hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
       target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
       target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
       target/arm: Implement v8.1M REVIDR register
       target/arm: Implement new v8.1M NOCP check for exception return
       target/arm: Implement new v8.1M VLLDM and VLSTM encodings
       hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
       target/arm: Implement CCR_S.TRD behaviour for SG insns
       hw/intc/armv7m_nvic: Fix "return from inactive handler" check
       target/arm: Implement M-profile "minimal RAS implementation"
       hw/intc/armv7m_nvic: Implement read/write for RAS register block
       hw/arm/armv7m: Correct typo in QOM object name
 Vikram Garhwal (4):
       hw/net/can: Introduce Xilinx ZynqMP CAN controller
       xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
       tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
       MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
- docs/system/arm/mps2.rst               |   20 +-
+ meson.build                      |    1 +
- docs/system/arm/nuvoton.rst            |   92 +++
+ hw/arm/smmuv3-internal.h         |    2 +-
- docs/system/deprecated.rst             |   32 +-
+ hw/net/can/trace.h               |    1 +
- docs/system/target-arm.rst             |    1 +
+ include/hw/arm/xlnx-zynqmp.h     |    8 +
- configure                              |    2 +-
+ include/hw/intc/armv7m_nvic.h    |    2 +
- default-configs/arm-softmmu.mak        |    1 +
+ include/hw/net/xlnx-zynqmp-can.h |   78 +++
- include/hw/arm/npcm7xx.h               |  112 +++
+ target/arm/cpu.h                 |   46 ++
- include/hw/arm/xlnx-zynqmp.h           |    8 +
+ target/arm/m-nocp.decode         |   10 +-
- include/hw/mem/npcm7xx_mc.h            |   36 +
+ target/arm/t32.decode            |   10 +-
- include/hw/misc/npcm7xx_clk.h          |   48 ++
+ target/arm/vfp.decode            |   14 +
- include/hw/misc/npcm7xx_gcr.h          |   43 ++
+ hw/arm/armv7m.c                  |    4 +-
- include/hw/net/xlnx-zynqmp-can.h       |   78 +++
+ hw/arm/sbsa-ref.c                |   23 +-
- include/hw/nvram/npcm7xx_otp.h         |   79 +++
+ hw/arm/xlnx-zcu102.c             |   20 +
- include/hw/ssi/npcm7xx_fiu.h           |   73 ++
+ hw/arm/xlnx-zynqmp.c             |   34 ++
- include/hw/timer/npcm7xx_timer.h       |   78 +++
+ hw/intc/armv7m_nvic.c            |  246 ++++++--
- target/arm/kvm-consts.h                |    7 -
+ hw/misc/imx25_ccm.c              |   12 +-
- target/arm/kvm_arm.h                   |    6 -
+ hw/misc/imx31_ccm.c              |   14 +-
- target/arm/neon-dp.decode              |   18 +-
+ hw/misc/imx6_ccm.c               |   20 +-
- target/arm/neon-shared.decode          |   18 +-
+ hw/misc/imx6_src.c               |    2 +-
- tests/decode/succ_ident1.decode        |    7 +
+ hw/misc/imx6ul_ccm.c             |    4 +-
- hw/arm/mps2.c                          |   97 ++-
+ hw/misc/imx_ccm.c                |    4 +-
- hw/arm/npcm7xx.c                       |  532 +++++++++++++++
+ hw/net/can/xlnx-zynqmp-can.c     | 1161 ++++++++++++++++++++++++++++++++++++++
- hw/arm/npcm7xx_boards.c                |  197 ++++++
+ target/arm/cpu.c                 |    5 +-
- hw/arm/xlnx-versal-virt.c              |    2 +-
+ target/arm/helper.c              |    7 +-
- hw/arm/xlnx-zcu102.c                   |   20 +
+ target/arm/m_helper.c            |  130 ++++-
- hw/arm/xlnx-zynqmp.c                   |   34 +
+ target/arm/translate.c           |  105 +++-
- hw/mem/npcm7xx_mc.c                    |   84 +++
+ tests/qtest/npcm7xx_rng-test.c   |   12 +
- hw/misc/a9scu.c                        |   59 +-
+ tests/qtest/xlnx-can-test.c      |  360 ++++++++++++
- hw/misc/npcm7xx_clk.c                  |  266 ++++++++
+ MAINTAINERS                      |    8 +
- hw/misc/npcm7xx_gcr.c                  |  269 ++++++++
+ hw/Kconfig                       |    1 +
- hw/net/can/xlnx-zynqmp-can.c           | 1165 ++++++++++++++++++++++++++++++++
+ hw/net/can/meson.build           |    1 +
- hw/nvram/npcm7xx_otp.c                 |  440 ++++++++++++
+ hw/net/can/trace-events          |    9 +
- hw/ssi/npcm7xx_fiu.c                   |  572 ++++++++++++++++
+ target/arm/translate-vfp.c.inc   |  511 ++++++++++++++++-
- hw/timer/armv7m_systick.c              |    8 +
+ tests/qtest/meson.build          |    1 +
- hw/timer/npcm7xx_timer.c               |  543 +++++++++++++++
+files changed, 2713 insertions(+), 153 deletions(-)
- target/arm/cpu.c                       |  101 ++-
+ create mode 100644 hw/net/can/trace.h
  target/arm/helper.c                    |    2 +-
  target/arm/kvm.c                       |    7 -
  target/arm/kvm32.c                     |  595 ----------------
  tests/qtest/xlnx-can-test.c            |  359 ++++++++++
  .gitmodules                            |    3 +
  MAINTAINERS                            |   18 +
  hw/arm/Kconfig                         |    9 +
  hw/arm/meson.build                     |    1 +
  hw/mem/meson.build                     |    1 +
  hw/misc/meson.build                    |    4 +
  hw/misc/trace-events                   |    8 +
  hw/net/can/meson.build                 |    1 +
  hw/nvram/meson.build                   |    1 +
  hw/ssi/meson.build                     |    1 +
  hw/ssi/trace-events                    |   11 +
  hw/timer/meson.build                   |    1 +
  hw/timer/trace-events                  |    5 +
  pc-bios/README                         |    6 +
  pc-bios/meson.build                    |    1 +
  pc-bios/npcm7xx_bootrom.bin            |  Bin 0 -> 768 bytes
  roms/Makefile                          |    7 +
  roms/vbootrom                          |    1 +
  scripts/decodetree.py                  |   46 +-
  target/arm/meson.build                 |    5 +-
  target/arm/translate-neon.c.inc        |   42 +-
  tests/acceptance/boot_linux_console.py |   83 +++
  tests/qtest/meson.build                |    1 +
 files changed, 5584 insertions(+), 783 deletions(-)
  create mode 100644 docs/system/arm/nuvoton.rst
  create mode 100644 include/hw/arm/npcm7xx.h
  create mode 100644 include/hw/mem/npcm7xx_mc.h
  create mode 100644 include/hw/misc/npcm7xx_clk.h
  create mode 100644 include/hw/misc/npcm7xx_gcr.h
  create mode 100644 include/hw/net/xlnx-zynqmp-can.h
- create mode 100644 include/hw/nvram/npcm7xx_otp.h
- create mode 100644 include/hw/ssi/npcm7xx_fiu.h
- create mode 100644 include/hw/timer/npcm7xx_timer.h
- create mode 100644 tests/decode/succ_ident1.decode
- create mode 100644 hw/arm/npcm7xx.c
- create mode 100644 hw/arm/npcm7xx_boards.c
- create mode 100644 hw/mem/npcm7xx_mc.c
- create mode 100644 hw/misc/npcm7xx_clk.c
- create mode 100644 hw/misc/npcm7xx_gcr.c
  create mode 100644 hw/net/can/xlnx-zynqmp-can.c
- create mode 100644 hw/nvram/npcm7xx_otp.c
- create mode 100644 hw/ssi/npcm7xx_fiu.c
- create mode 100644 hw/timer/npcm7xx_timer.c
- delete mode 100644 target/arm/kvm32.c
  create mode 100644 tests/qtest/xlnx-can-test.c
- create mode 100644 pc-bios/npcm7xx_bootrom.bin
+ create mode 100644 hw/net/can/trace-events
  create mode 160000 roms/vbootrom

-[PULL 01/36] hw/misc/a9scu: Do not allow invalid CPU count
+[PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Kunkun Jiang <jiangkunkun@huawei.com>
-Per the datasheet (DDI0407 r2p0):
+Accroding to the SMMUv3 spec, the SPAN field of Level1 Stream Table
 Descriptor is 5 bits([4:0]).
-  "The SCU connects one to four Cortex-A9 processors to
+Fixes: 9bde7f0674f(hw/arm/smmuv3: Implement translate callback)
-   the memory system through the AXI interfaces."
+Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
+Message-id: 20201124023711.1184-1-jiangkunkun@huawei.com
-Change the instance_init() handler to a device_realize()
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-one so we can verify the property is in range, and return
+Acked-by: Eric Auger <eric.auger@redhat.com>
 an error to the caller if not.
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200901144100.116742-2-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/misc/a9scu.c | 18 +++++++++++++-----
+ hw/arm/smmuv3-internal.h | 2 +-
-file changed, 13 insertions(+), 5 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
+diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/a9scu.c
+--- a/hw/arm/smmuv3-internal.h
-+++ b/hw/misc/a9scu.c
++++ b/hw/arm/smmuv3-internal.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline uint64_t l1std_l2ptr(STEDesc *desc)
- #include "hw/misc/a9scu.h"
+     return hi << 32 | lo;
  #include "hw/qdev-properties.h"
  #include "migration/vmstate.h"
 +#include "qapi/error.h"
  #include "qemu/module.h"
 +#define A9_SCU_CPU_MAX  4
 +
  static uint64_t a9_scu_read(void *opaque, hwaddr offset,
                              unsigned size)
  {
@@ -XXX,XX +XXX,XX @@ static void a9_scu_reset(DeviceState *dev)
      s->control = 0;
  }
--static void a9_scu_init(Object *obj)
+-#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4))
-+static void a9_scu_realize(DeviceState *dev, Error **errp)
++#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))
- {
--    A9SCUState *s = A9_SCU(obj);
+ #endif
 -    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    A9SCUState *s = A9_SCU(dev);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 -    memory_region_init_io(&s->iomem, obj, &a9_scu_ops, s,
 +    if (!s->num_cpu || s->num_cpu > A9_SCU_CPU_MAX) {
 +        error_setg(errp, "Illegal CPU count: %u", s->num_cpu);
 +        return;
 +    }
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &a9_scu_ops, s,
                            "a9-scu", 0x100);
      sysbus_init_mmio(sbd, &s->iomem);
  }
@@ -XXX,XX +XXX,XX @@ static void a9_scu_class_init(ObjectClass *klass, void *data)
      device_class_set_props(dc, a9_scu_properties);
      dc->vmsd = &vmstate_a9_scu;
      dc->reset = a9_scu_reset;
 +    dc->realize = a9_scu_realize;
  }
  static const TypeInfo a9_scu_info = {
      .name          = TYPE_A9_SCU,
      .parent        = TYPE_SYS_BUS_DEVICE,
      .instance_size = sizeof(A9SCUState),
 -    .instance_init = a9_scu_init,
      .class_init    = a9_scu_class_init,
  };
 --
 .20.1

-[PULL 33/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller
+[PULL 02/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller
 ...
 To create virtual CAN on the host machine, please check the QEMU CAN docs:
 https://github.com/qemu/qemu/blob/master/docs/can.txt
 Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
-Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
+Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 1597278668-339715-2-git-send-email-fnu.vikram@xilinx.com
 [PMM: updated to meson build system]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
+ meson.build                      |    1 +
+ hw/net/can/trace.h               |    1 +
  include/hw/net/xlnx-zynqmp-can.h |   78 ++
- hw/net/can/xlnx-zynqmp-can.c     | 1165 ++++++++++++++++++++++++++++++
+ hw/net/can/xlnx-zynqmp-can.c     | 1161 ++++++++++++++++++++++++++++++
  hw/Kconfig                       |    1 +
  hw/net/can/meson.build           |    1 +
-files changed, 1244 insertions(+)
+ hw/net/can/trace-events          |    9 +
 files changed, 1252 insertions(+)
  create mode 100644 hw/net/can/trace.h
  create mode 100644 include/hw/net/xlnx-zynqmp-can.h
  create mode 100644 hw/net/can/xlnx-zynqmp-can.c
+ create mode 100644 hw/net/can/trace-events
+diff --git a/meson.build b/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/meson.build
++++ b/meson.build
+@@ -XXX,XX +XXX,XX @@ if have_system
+     'hw/misc',
+     'hw/misc/macio',
+     'hw/net',
++    'hw/net/can',
+     'hw/nvram',
+     'hw/pci',
+     'hw/pci-host',
+diff --git a/hw/net/can/trace.h b/hw/net/can/trace.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/net/can/trace.h
+@@ -0,0 +1 @@
++#include "trace/trace-hw_net_can.h"
 diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-can.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/net/xlnx-zynqmp-can.h
 ...
 +#include "net/can_emu.h"
 +#include "net/can_host.h"
 +#include "qemu/event_notifier.h"
 +#include "qom/object_interfaces.h"
 +#include "hw/net/xlnx-zynqmp-can.h"
++#include "trace.h"
 +
 +#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG
 +#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0
 +#endif
-+
-+#define DB_PRINT(dev, ...) do { \
-+    if (XLNX_ZYNQMP_CAN_ERR_DEBUG) { \
-+        g_autofree char *path = object_get_canonical_path(OBJECT(dev)); \
-+        qemu_log("%s: %s", path, ## __VA_ARGS__); \
-+    } \
-+} while (0)
 +
 +#define MAX_DLC            8
 +#undef ERROR
 +
 +REG32(SOFTWARE_RESET_REGISTER, 0x0)
 ...
 +    }
 +
 +    irq = s->regs[R_INTERRUPT_STATUS_REGISTER];
 +    irq &= s->regs[R_INTERRUPT_ENABLE_REGISTER];
 +
++    trace_xlnx_can_update_irq(s->regs[R_INTERRUPT_STATUS_REGISTER],
++                              s->regs[R_INTERRUPT_ENABLE_REGISTER], irq);
 +    qemu_set_irq(s->irq, irq);
 +}
 +
-+static void can_ier_post_write(RegisterInfo *reg, uint64_t val64)
++static void can_ier_post_write(RegisterInfo *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
 +
 +    can_update_irq(s);
 +}
 +
-+static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val64)
++static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
-+    uint32_t val = val64;
 +
 +    s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val;
 +    can_update_irq(s);
 +
 +    return 0;
 ...
 +    qemu_can_frame frame;
 +    uint32_t data[CAN_FRAME_SIZE];
 +    int i;
 +    bool can_tx = tx_ready_check(s);
 +
-+    if (can_tx) {
++    if (!can_tx) {
-+        while (!fifo32_is_empty(fifo)) {
++        g_autofree char *path = object_get_canonical_path(OBJECT(s));
-+            for (i = 0; i < CAN_FRAME_SIZE; i++) {
++
-+                data[i] = fifo32_pop(fifo);
++        qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is not enabled for data"
 +                      " transfer.\n", path);
 +        can_update_irq(s);
 +        return;
 +    }
 +
 +    while (!fifo32_is_empty(fifo)) {
 +        for (i = 0; i < CAN_FRAME_SIZE; i++) {
 +            data[i] = fifo32_pop(fifo);
 +        }
 +
 +        if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
 +            /*
 +             * Controller is in loopback. In Loopback mode, the CAN core
 +             * transmits a recessive bitstream on to the XlnxZynqMPCAN Bus.
 +             * Any message transmitted is looped back to the RX line and
 +             * acknowledged. The XlnxZynqMPCAN core receives any message
 +             * that it transmits.
 +             */
 +            if (fifo32_is_full(&s->rx_fifo)) {
 +                ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
 +            } else {
 +                for (i = 0; i < CAN_FRAME_SIZE; i++) {
 +                    fifo32_push(&s->rx_fifo, data[i]);
 +                }
 +
 +                ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
 +            }
-+
++        } else {
-+            if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
++            /* Normal mode Tx. */
-+                /*
++            generate_frame(&frame, data);
-+                 * Controller is in loopback. In Loopback mode, the CAN core
++
-+                 * transmits a recessive bitstream on to the XlnxZynqMPCAN Bus.
++            trace_xlnx_can_tx_data(frame.can_id, frame.can_dlc,
-+                 * Any message transmitted is looped back to the RX line and
++                                   frame.data[0], frame.data[1],
-+                 * acknowledged. The XlnxZynqMPCAN core receives any message
++                                   frame.data[2], frame.data[3],
-+                 * that it transmits.
++                                   frame.data[4], frame.data[5],
-+                 */
++                                   frame.data[6], frame.data[7]);
-+                if (fifo32_is_full(&s->rx_fifo)) {
++            can_bus_client_send(&s->bus_client, &frame, 1);
 +                    DB_PRINT(s, "Loopback: RX FIFO is full."
 +                             " TX FIFO will be flushed.\n");
 +
 +                    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER,
 +                                     RXOFLW, 1);
 +                } else {
 +                    for (i = 0; i < CAN_FRAME_SIZE; i++) {
 +                        fifo32_push(&s->rx_fifo, data[i]);
 +                    }
 +
 +                    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER,
 +                                     RXOK, 1);
 +                }
 +            } else {
 +                /* Normal mode Tx. */
 +                generate_frame(&frame, data);
 +
 +                can_bus_client_send(&s->bus_client, &frame, 1);
 +            }
 +        }
-+
++    }
-+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
++
-+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0);
++    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
-+
++    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0);
-+        if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
++
-+            can_exit_sleep_mode(s);
++    if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
-+        }
++        can_exit_sleep_mode(s);
 +    } else {
 +        DB_PRINT(s, "Not enabled for data transfer.\n");
 +    }
 +
 +    can_update_irq(s);
 +}
 +
-+static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val64)
++static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
-+    uint32_t val = val64;
 +
 +    ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN,
 +                     FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN));
 +
 +    if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) {
-+        DB_PRINT(s, "Resetting controller.\n");
++        trace_xlnx_can_reset(val);
 +
 +        /* First, core will do software reset then will enter in config mode. */
 +        can_config_reset(s);
 +    }
 +
 ...
 +    update_status_register_mode_bits(s);
 +
 +    return s->regs[R_SOFTWARE_RESET_REGISTER];
 +}
 +
-+static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val64)
++static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
-+    uint32_t val = val64;
 +    uint8_t multi_mode;
 +
 +    /*
 +     * Multiple mode set check. This is done to make sure user doesn't set
 +     * multiple modes.
 ...
 +    }
 +
 +    return s->regs[R_MODE_SELECT_REGISTER];
 +}
 +
-+static uint64_t can_brpr_pre_write(RegisterInfo  *reg, uint64_t val64)
++static uint64_t can_brpr_pre_write(RegisterInfo  *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
-+    uint32_t val = val64;
 +
 +    /* Only allow writes when in config mode. */
 +    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
-+        val = s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER];
++        return s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER];
 +    }
 +
 +    return val;
 +}
 +
-+static uint64_t can_btr_pre_write(RegisterInfo  *reg, uint64_t val64)
++static uint64_t can_btr_pre_write(RegisterInfo  *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
-+    uint32_t val = val64;
 +
 +    /* Only allow writes when in config mode. */
 +    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
-+        val = s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER];
++        return s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER];
 +    }
 +
 +    return val;
 +}
 +
-+static uint64_t can_tcr_pre_write(RegisterInfo  *reg, uint64_t val64)
++static uint64_t can_tcr_pre_write(RegisterInfo  *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
-+    uint32_t val = val64;
 +
 +    if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) {
 +        ptimer_transaction_begin(s->can_timer);
 +        ptimer_set_count(s->can_timer, 0);
 +        ptimer_transaction_commit(s->can_timer);
 ...
 +        if (filter_id_masked == id_masked) {
 +            filter_pass = true;
 +        }
 +    }
 +
++    if (!filter_pass) {
++        trace_xlnx_can_rx_fifo_filter_reject(frame->can_id, frame->can_dlc);
++        return;
++    }
++
 +    /* Store the message in fifo if it passed through any of the filters. */
 +    if (filter_pass && frame->can_dlc <= MAX_DLC) {
 +
 +        if (fifo32_is_full(&s->rx_fifo)) {
-+            DB_PRINT(s, "RX FIFO is full.\n");
-+
 +            ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
 +        } else {
 +            timestamp = CAN_TIMER_MAX - ptimer_get_count(s->can_timer);
 +
 +            fifo32_push(&s->rx_fifo, frame->can_id);
 ...
 +                                     deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
 +                                               R_TXFIFO_DATA2_DB4_LENGTH,
 +                                               frame->data[7]));
 +
 +            ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
++            trace_xlnx_can_rx_data(frame->can_id, frame->can_dlc,
++                                   frame->data[0], frame->data[1],
++                                   frame->data[2], frame->data[3],
++                                   frame->data[4], frame->data[5],
++                                   frame->data[6], frame->data[7]);
 +        }
 +
 +        can_update_irq(s);
++    }
++}
++
++static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val)
++{
++    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
++
++    if (!fifo32_is_empty(&s->rx_fifo)) {
++        val = fifo32_pop(&s->rx_fifo);
 +    } else {
-+        DB_PRINT(s, "Message didn't pass through any filter or dlc"
-+                 " is not in range.\n");
-+    }
-+}
-+
-+static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val64)
-+{
-+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
-+    uint32_t r = 0;
-+
-+    if (!fifo32_is_empty(&s->rx_fifo)) {
-+        r = fifo32_pop(&s->rx_fifo);
-+    } else {
-+        DB_PRINT(s, "No message in RXFIFO.\n");
-+
 +        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1);
 +    }
 +
 +    can_update_irq(s);
-+    return r;
++    return val;
 +}
 +
-+static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val64)
++static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
 +
 +    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) &&
 +        ARRAY_FIELD_EX32(s->regs, AFR, UAF2) &&
 ...
 +    } else {
 +        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0);
 +    }
 +}
 +
-+static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val64)
++static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
 +    uint32_t reg_idx = (reg->access->addr) / 4;
-+    uint32_t val = val64;
 +    uint32_t filter_number = (reg_idx - R_AFMR1) / 2;
 +
-+    /* modify an acceptance filter, the corresponding UAF bit should be '0.' */
++    /* modify an acceptance filter, the corresponding UAF bit should be '0'. */
 +    if (!(s->regs[R_AFR] & (1 << filter_number))) {
 +        s->regs[reg_idx] = val;
++
++        trace_xlnx_can_filter_mask_pre_write(filter_number, s->regs[reg_idx]);
 +    } else {
 +        g_autofree char *path = object_get_canonical_path(OBJECT(s));
 +
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
 +                      " mask is not set as corresponding UAF bit is not 0.\n",
 +                      path, filter_number + 1);
 +    }
 +
 +    return s->regs[reg_idx];
 +}
 +
-+static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val64)
++static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
 +    uint32_t reg_idx = (reg->access->addr) / 4;
-+    uint32_t val = val64;
 +    uint32_t filter_number = (reg_idx - R_AFIR1) / 2;
 +
 +    if (!(s->regs[R_AFR] & (1 << filter_number))) {
 +        s->regs[reg_idx] = val;
++
++        trace_xlnx_can_filter_id_pre_write(filter_number, s->regs[reg_idx]);
 +    } else {
 +        g_autofree char *path = object_get_canonical_path(OBJECT(s));
 +
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
 +                      " id is not set as corresponding UAF bit is not 0.\n",
 +                      path, filter_number + 1);
 +    }
 +
 +    return s->regs[reg_idx];
 +}
 +
-+static void can_tx_post_write(RegisterInfo *reg, uint64_t val64)
++static void can_tx_post_write(RegisterInfo *reg, uint64_t val)
 +{
 +    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
-+    uint32_t val = val64;
 +
 +    bool is_txhpb = reg->access->addr > A_TXFIFO_DATA2;
 +
 +    bool initiate_transfer = (reg->access->addr == A_TXFIFO_DATA2) ||
 +                             (reg->access->addr == A_TXHPB_DATA2);
 +
 +    Fifo32 *f = is_txhpb ? &s->txhpb_fifo : &s->tx_fifo;
-+
-+    DB_PRINT(s, "TX FIFO write.\n");
 +
 +    if (!fifo32_is_full(f)) {
 +        fifo32_push(f, val);
 +    } else {
 +        g_autofree char *path = object_get_canonical_path(OBJECT(s));
 ...
 +{
 +    XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
 +                                         bus_client);
 +
 +    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
-+        DB_PRINT(s, "Controller is in reset.\n");
++        g_autofree char *path = object_get_canonical_path(OBJECT(s));
 +
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in reset state.\n",
 +                      path);
 +        return false;
-+    } else if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) == 0) {
++    }
-+        DB_PRINT(s, "Controller is disabled. Incoming messages"
++
-+                 " will be discarded.\n");
++    if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) == 0) {
 +        g_autofree char *path = object_get_canonical_path(OBJECT(s));
 +
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is disabled. Incoming"
 +                      " messages will be discarded.\n", path);
 +        return false;
-+    } else {
++    }
-+        return true;
++
-+    }
++    return true;
 +}
 +
 +static ssize_t xlnx_zynqmp_can_receive(CanBusClientState *client,
 +                               const qemu_can_frame *buf, size_t buf_size) {
 +    XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
-+                                        bus_client);
++                                         bus_client);
 +    const qemu_can_frame *frame = buf;
 +
-+    DB_PRINT(s, "Incoming data.\n");
-+
 +    if (buf_size <= 0) {
-+        DB_PRINT(s, "Junk data received.\n");
++        g_autofree char *path = object_get_canonical_path(OBJECT(s));
 +
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Error in the data received.\n",
 +                      path);
 +        return 0;
 +    }
-+    if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
++
-+        /*
++    if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
 +         * XlnxZynqMPCAN will not participate in normal bus communication
 +         * and will not receive any messages transmitted by other CAN nodes.
 +         */
 +        DB_PRINT(s, "Controller is in loopback mode. It will not"
 +                 " receive data.\n");
 +
 +    } else if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
 +        /* Snoop Mode: Just keep the data. no response back. */
 +        update_rx_fifo(s, frame);
 +    } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) {
 +        /*
 +         * XlnxZynqMPCAN is in sleep mode. Any data on bus will bring it to wake
 ...
 +        can_exit_sleep_mode(s);
 +        update_rx_fifo(s, frame);
 +    } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) == 0) {
 +        update_rx_fifo(s, frame);
 +    } else {
-+        DB_PRINT(s, "Cannot receive data as controller is not configured"
++        /*
-+                 " correctly.\n");
++         * XlnxZynqMPCAN will not participate in normal bus communication
 +         * and will not receive any messages transmitted by other CAN nodes.
 +         */
 +        trace_xlnx_can_rx_discard(s->regs[R_STATUS_REGISTER]);
 +    }
 +
 +    return 1;
 +}
 +
 ...
 +
 +            error_setg(errp, "%s: xlnx_zynqmp_can_connect_to_bus"
 +                       " failed.", path);
 +            return;
 +        }
-+
-+    } else {
-+        /* If no bus is set. */
-+        DB_PRINT(s, "Canbus property is not set.\n");
 +    }
 +
 +    /* Create RX FIFO, TXFIFO, TXHPB storage. */
 +    fifo32_create(&s->rx_fifo, RXFIFO_SIZE);
 +    fifo32_create(&s->tx_fifo, RXFIFO_SIZE);
 ...
 +{
 +    type_register_static(&can_info);
 +}
 +
 +type_init(can_register_types)
+diff --git a/hw/Kconfig b/hw/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/Kconfig
++++ b/hw/Kconfig
+@@ -XXX,XX +XXX,XX @@ config XILINX_AXI
+ config XLNX_ZYNQMP
+     bool
+     select REGISTER
++    select CAN_BUS
 diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/can/meson.build
 +++ b/hw/net/can/meson.build
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_CAN_SJA1000', if_true: files('can_sja1000.c'))
+@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c'))
  softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_kvaser_pci.c'))
  softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c'))
  softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'))
+ softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_core.c'))
+ softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci.c'))
 +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.c'))
+diff --git a/hw/net/can/trace-events b/hw/net/can/trace-events
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/net/can/trace-events
+@@ -XXX,XX +XXX,XX @@
++# xlnx-zynqmp-can.c
++xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
++xlnx_can_reset(uint32_t val) "Resetting controller with value = 0x%08x"
++xlnx_can_rx_fifo_filter_reject(uint32_t id, uint8_t dlc) "Frame: ID: 0x%08x DLC: 0x%02x"
++xlnx_can_filter_id_pre_write(uint8_t filter_num, uint32_t value) "Filter%d ID: 0x%08x"
++xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter%d MASK: 0x%08x"
++xlnx_can_tx_data(uint32_t id, uint8_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
++xlnx_can_rx_data(uint32_t id, uint32_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
++xlnx_can_rx_discard(uint32_t status) "Controller is not enabled for bus communication. Status Register: 0x%08x"
 --
 .20.1

-[PULL 34/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
+[PULL 03/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
 ...
 Connect CAN0 and CAN1 on the ZynqMP.
 Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
 Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
-Message-id: 1597278668-339715-3-git-send-email-fnu.vikram@xilinx.com
+Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/xlnx-zynqmp.h |  8 ++++++++
  hw/arm/xlnx-zcu102.c         | 20 ++++++++++++++++++++
  hw/arm/xlnx-zynqmp.c         | 34 ++++++++++++++++++++++++++++++++++
 ...
  #include "target/arm/cpu.h"
  #include "qom/object.h"
 +#include "net/can_emu.h"
  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
- typedef struct XlnxZynqMPState XlnxZynqMPState;
+ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
-@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(XlnxZynqMPState, XLNX_ZYNQMP,
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
  #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
  #define XLNX_ZYNQMP_NUM_GEMS 4
  #define XLNX_ZYNQMP_NUM_UARTS 2
 +#define XLNX_ZYNQMP_NUM_CAN 2
 +#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
 ...
 +    CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
 +
      struct arm_boot_info binfo;
  };
- typedef struct XlnxZCU102 XlnxZCU102;
 @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
      object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
                               &error_fatal);
 +    for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
 ...
 +
      qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
      /* Create and plug in the SD cards */
 @@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
-                                     "Set on/off to enable/disable emulating a "
+     s->secure = false;
-                                     "guest CPU which implements the ARM "
+     /* Default to virt (EL2) being disabled */
-                                     "Virtualization Extensions");
+     s->virt = false;
 +    object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
 +                             (Object **)&s->canbus[0],
 +                             object_property_allow_set_link,
 +                             0);
 +
 ...

-[PULL 35/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
+[PULL 04/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
 From: Vikram Garhwal <fnu.vikram@xilinx.com>
 The QTests perform five tests on the Xilinx ZynqMP CAN controller:
     Tests the CAN controller in loopback, sleep and snoop mode.
     Tests filtering of incoming CAN messages.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
 Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
-Message-id: 1597278668-339715-4-git-send-email-fnu.vikram@xilinx.com
+Message-id: 1605728926-352690-4-git-send-email-fnu.vikram@xilinx.com
 [PMM: updated to meson build system]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/qtest/xlnx-can-test.c | 359 ++++++++++++++++++++++++++++++++++++
+ tests/qtest/xlnx-can-test.c | 360 ++++++++++++++++++++++++++++++++++++
  tests/qtest/meson.build     |   1 +
-files changed, 360 insertions(+)
+files changed, 361 insertions(+)
  create mode 100644 tests/qtest/xlnx-can-test.c
 diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 ...
 +#define STATUS_SNOOP_MODE       (1 << 12)
 +#define STATUS_SLEEP_MODE       (1 << 2)
 +#define ISR_TXOK                (1 << 1)
 +#define ISR_RXOK                (1 << 4)
 +
-+static void match_rx_tx_data(uint32_t *buf_tx, uint32_t *buf_rx,
++static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
 +                             uint8_t can_timestamp)
 +{
 +    uint16_t size = 0;
 +    uint8_t len = 4;
 +
 ...
 +
 +    /* Clear the RX interrupt. */
 +    qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK);
 +}
 +
-+static void send_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_tx)
++static void send_data(QTestState *qts, uint64_t can_base_addr,
 +                      const uint32_t *buf_tx)
 +{
 +    uint32_t int_status;
 +
 +    /* Write the TX register data for CAN. */
 +    qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]);
 ...
 + * initiate the data transfer to can-bus, CAN1 receives the data. Test compares
 + * the data sent from CAN0 with received on CAN1.
 + */
 +static void test_can_bus(void)
 +{
-+    uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
++    const uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
 +    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
 +    uint32_t status = 0;
 +    uint8_t can_timestamp = 1;
 +
 +    QTestState *qts = qtest_init("-machine xlnx-zcu102"
 ...
 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/meson.build
 +++ b/tests/qtest/meson.build
 @@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
-   (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
+   ['arm-cpu-features',
-   ['numa-test',
+    'numa-test',
     'boot-serial-test',
 +   'xlnx-can-test',
     'migration-test']
  qtests_s390x = \
 --
 .20.1

-[PULL 36/36] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
+[PULL 05/36] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
 From: Vikram Garhwal <fnu.vikram@xilinx.com>
 Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
 Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
-Message-id: 1597278668-339715-5-git-send-email-fnu.vikram@xilinx.com
+Message-id: 1605728926-352690-5-git-send-email-fnu.vikram@xilinx.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  MAINTAINERS | 8 ++++++++
 file changed, 8 insertions(+)
 ...

-[PULL 21/36] hw/timer: Add NPCM7xx Timer device model
+[PULL 06/36] sbsa-ref: allow to use Cortex-A53/57/72 cpus
-From: Havard Skinnemoen <hskinnemoen@google.com>
+From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-The NPCM730 and NPCM750 SoCs have three timer modules each holding five
+Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable
-timers and some shared registers (e.g. interrupt status).
+it for QEMU as well. A53 was already enabled there.
-Each timer runs at 25 MHz divided by a prescaler, and counts down from a
+. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117
 configurable initial value to zero. When zero is reached, the interrupt
 flag for the timer is set, and the timer is disabled (one-shot mode) or
 reloaded from its initial value (periodic mode).
-This implementation is sufficient to boot a Linux kernel configured for
+Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
-NPCM750. Note that the kernel does not seem to actually turn on the
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-interrupts.
+Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Reviewed-by: Joel Stanley <joel@jms.id.au>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Alexander Bulekov <alxndr@bu.edu>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-4-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/timer/npcm7xx_timer.h |  78 +++++
+ hw/arm/sbsa-ref.c | 23 ++++++++++++++++++++---
- hw/timer/npcm7xx_timer.c         | 543 +++++++++++++++++++++++++++++++
+file changed, 20 insertions(+), 3 deletions(-)
  hw/timer/meson.build             |   1 +
  hw/timer/trace-events            |   5 +
 files changed, 627 insertions(+)
  create mode 100644 include/hw/timer/npcm7xx_timer.h
  create mode 100644 hw/timer/npcm7xx_timer.c
-diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/hw/arm/sbsa-ref.c
---- /dev/null
++++ b/hw/arm/sbsa-ref.c
-+++ b/include/hw/timer/npcm7xx_timer.h
+@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
-@@ -XXX,XX +XXX,XX @@
+     [SBSA_GWDT] = 16,
-+/*
+ };
-+ * Nuvoton NPCM7xx Timer Controller
-+ *
++static const char * const valid_cpus[] = {
-+ * Copyright 2020 Google LLC
++    ARM_CPU_TYPE_NAME("cortex-a53"),
-+ *
++    ARM_CPU_TYPE_NAME("cortex-a57"),
-+ * This program is free software; you can redistribute it and/or modify it
++    ARM_CPU_TYPE_NAME("cortex-a72"),
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +#ifndef NPCM7XX_TIMER_H
 +#define NPCM7XX_TIMER_H
 +
 +#include "exec/memory.h"
 +#include "hw/sysbus.h"
 +#include "qemu/timer.h"
 +
 +/* Each Timer Module (TIM) instance holds five 25 MHz timers. */
 +#define NPCM7XX_TIMERS_PER_CTRL (5)
 +
 +/*
 + * Number of registers in our device state structure. Don't change this without
 + * incrementing the version_id in the vmstate.
 + */
 +#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
 +
 +typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
 +
 +/**
 + * struct NPCM7xxTimer - Individual timer state.
 + * @irq: GIC interrupt line to fire on expiration (if enabled).
 + * @qtimer: QEMU timer that notifies us on expiration.
 + * @expires_ns: Absolute virtual expiration time.
 + * @remaining_ns: Remaining time until expiration if timer is paused.
 + * @tcsr: The Timer Control and Status Register.
 + * @ticr: The Timer Initial Count Register.
 + */
 +typedef struct NPCM7xxTimer {
 +    NPCM7xxTimerCtrlState *ctrl;
 +
 +    qemu_irq    irq;
 +    QEMUTimer   qtimer;
 +    int64_t     expires_ns;
 +    int64_t     remaining_ns;
 +
 +    uint32_t    tcsr;
 +    uint32_t    ticr;
 +} NPCM7xxTimer;
 +
 +/**
 + * struct NPCM7xxTimerCtrlState - Timer Module device state.
 + * @parent: System bus device.
 + * @iomem: Memory region through which registers are accessed.
 + * @tisr: The Timer Interrupt Status Register.
 + * @wtcr: The Watchdog Timer Control Register.
 + * @timer: The five individual timers managed by this module.
 + */
 +struct NPCM7xxTimerCtrlState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    uint32_t    tisr;
 +    uint32_t    wtcr;
 +
 +    NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
 +};
 +
-+#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
++static bool cpu_type_valid(const char *cpu)
 +#define NPCM7XX_TIMER(obj)                                              \
 +    OBJECT_CHECK(NPCM7xxTimerCtrlState, (obj), TYPE_NPCM7XX_TIMER)
 +
 +#endif /* NPCM7XX_TIMER_H */
 diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx Timer Controller
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +
 +#include "hw/irq.h"
 +#include "hw/misc/npcm7xx_clk.h"
 +#include "hw/timer/npcm7xx_timer.h"
 +#include "migration/vmstate.h"
 +#include "qemu/bitops.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/timer.h"
 +#include "qemu/units.h"
 +#include "trace.h"
 +
 +/* 32-bit register indices. */
 +enum NPCM7xxTimerRegisters {
 +    NPCM7XX_TIMER_TCSR0,
 +    NPCM7XX_TIMER_TCSR1,
 +    NPCM7XX_TIMER_TICR0,
 +    NPCM7XX_TIMER_TICR1,
 +    NPCM7XX_TIMER_TDR0,
 +    NPCM7XX_TIMER_TDR1,
 +    NPCM7XX_TIMER_TISR,
 +    NPCM7XX_TIMER_WTCR,
 +    NPCM7XX_TIMER_TCSR2,
 +    NPCM7XX_TIMER_TCSR3,
 +    NPCM7XX_TIMER_TICR2,
 +    NPCM7XX_TIMER_TICR3,
 +    NPCM7XX_TIMER_TDR2,
 +    NPCM7XX_TIMER_TDR3,
 +    NPCM7XX_TIMER_TCSR4         = 0x0040 / sizeof(uint32_t),
 +    NPCM7XX_TIMER_TICR4         = 0x0048 / sizeof(uint32_t),
 +    NPCM7XX_TIMER_TDR4          = 0x0050 / sizeof(uint32_t),
 +    NPCM7XX_TIMER_REGS_END,
 +};
 +
 +/* Register field definitions. */
 +#define NPCM7XX_TCSR_CEN                BIT(30)
 +#define NPCM7XX_TCSR_IE                 BIT(29)
 +#define NPCM7XX_TCSR_PERIODIC           BIT(27)
 +#define NPCM7XX_TCSR_CRST               BIT(26)
 +#define NPCM7XX_TCSR_CACT               BIT(25)
 +#define NPCM7XX_TCSR_RSVD               0x01ffff00
 +#define NPCM7XX_TCSR_PRESCALE_START     0
 +#define NPCM7XX_TCSR_PRESCALE_LEN       8
 +
 +/*
 + * Returns the index of timer in the tc->timer array. This can be used to
 + * locate the registers that belong to this timer.
 + */
 +static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer)
 +{
 +    int index = timer - tc->timer;
 +
 +    g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);
 +
 +    return index;
 +}
 +
 +/* Return the value by which to divide the reference clock rate. */
 +static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
 +{
 +    return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START,
 +                     NPCM7XX_TCSR_PRESCALE_LEN) + 1;
 +}
 +
 +/* Convert a timer cycle count to a time interval in nanoseconds. */
 +static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
 +{
 +    int64_t ns = count;
 +
 +    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
 +    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
 +
 +    return ns;
 +}
 +
 +/* Convert a time interval in nanoseconds to a timer cycle count. */
 +static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
 +{
 +    int64_t count;
 +
 +    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
 +    count /= npcm7xx_tcsr_prescaler(t->tcsr);
 +
 +    return count;
 +}
 +
 +/*
 + * Raise the interrupt line if there's a pending interrupt and interrupts are
 + * enabled for this timer. If not, lower it.
 + */
 +static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
 +{
 +    NPCM7xxTimerCtrlState *tc = t->ctrl;
 +    int index = npcm7xx_timer_index(tc, t);
 +    bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index));
 +
 +    qemu_set_irq(t->irq, pending);
 +    trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
 +}
 +
 +/* Start or resume the timer. */
 +static void npcm7xx_timer_start(NPCM7xxTimer *t)
 +{
 +    int64_t now;
 +
 +    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    t->expires_ns = now + t->remaining_ns;
 +    timer_mod(&t->qtimer, t->expires_ns);
 +}
 +
 +/*
 + * Called when the counter reaches zero. Sets the interrupt flag, and either
 + * restarts or disables the timer.
 + */
 +static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
 +{
 +    NPCM7xxTimerCtrlState *tc = t->ctrl;
 +    int index = npcm7xx_timer_index(tc, t);
 +
 +    tc->tisr |= BIT(index);
 +
 +    if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
 +        t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
 +        if (t->tcsr & NPCM7XX_TCSR_CEN) {
 +            npcm7xx_timer_start(t);
 +        }
 +    } else {
 +        t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
 +    }
 +
 +    npcm7xx_timer_check_interrupt(t);
 +}
 +
 +/* Stop counting. Record the time remaining so we can continue later. */
 +static void npcm7xx_timer_pause(NPCM7xxTimer *t)
 +{
 +    int64_t now;
 +
 +    timer_del(&t->qtimer);
 +    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +    t->remaining_ns = t->expires_ns - now;
 +    if (t->remaining_ns <= 0) {
 +        npcm7xx_timer_reached_zero(t);
 +    }
 +}
 +
 +/*
 + * Restart the timer from its initial value. If the timer was enabled and stays
 + * enabled, adjust the QEMU timer according to the new count. If the timer is
 + * transitioning from disabled to enabled, the caller is expected to start the
 + * timer later.
 + */
 +static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
 +{
 +    t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
 +
 +    if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
 +        npcm7xx_timer_start(t);
 +    }
 +}
 +
 +/* Register read and write handlers */
 +
 +static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
 +{
 +    if (t->tcsr & NPCM7XX_TCSR_CEN) {
 +        int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +
 +        return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
 +    }
 +
 +    return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
 +}
 +
 +static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
 +{
 +    uint32_t old_tcsr = t->tcsr;
 +    uint32_t tdr;
 +
 +    if (new_tcsr & NPCM7XX_TCSR_RSVD) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits in 0x%08x ignored\n",
 +                      __func__, new_tcsr);
 +        new_tcsr &= ~NPCM7XX_TCSR_RSVD;
 +    }
 +    if (new_tcsr & NPCM7XX_TCSR_CACT) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only bits in 0x%08x ignored\n",
 +                      __func__, new_tcsr);
 +        new_tcsr &= ~NPCM7XX_TCSR_CACT;
 +    }
 +    if ((new_tcsr & NPCM7XX_TCSR_CRST) && (new_tcsr & NPCM7XX_TCSR_CEN)) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: both CRST and CEN set; ignoring CEN.\n",
 +                      __func__);
 +        new_tcsr &= ~NPCM7XX_TCSR_CEN;
 +    }
 +
 +    /* Calculate the value of TDR before potentially changing the prescaler. */
 +    tdr = npcm7xx_timer_read_tdr(t);
 +
 +    t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr;
 +
 +    if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
 +        /* Recalculate time remaining based on the current TDR value. */
 +        t->remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
 +        if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
 +            npcm7xx_timer_start(t);
 +        }
 +    }
 +
 +    if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) {
 +        npcm7xx_timer_check_interrupt(t);
 +    }
 +    if (new_tcsr & NPCM7XX_TCSR_CRST) {
 +        npcm7xx_timer_restart(t, old_tcsr);
 +        t->tcsr &= ~NPCM7XX_TCSR_CRST;
 +    }
 +    if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
 +        if (new_tcsr & NPCM7XX_TCSR_CEN) {
 +            t->tcsr |= NPCM7XX_TCSR_CACT;
 +            npcm7xx_timer_start(t);
 +        } else {
 +            t->tcsr &= ~NPCM7XX_TCSR_CACT;
 +            npcm7xx_timer_pause(t);
 +        }
 +    }
 +}
 +
 +static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr)
 +{
 +    t->ticr = new_ticr;
 +
 +    npcm7xx_timer_restart(t, t->tcsr);
 +}
 +
 +static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value)
 +{
 +    int i;
 +
-+    s->tisr &= ~value;
++    for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
-+    for (i = 0; i < ARRAY_SIZE(s->timer); i++) {
++        if (strcmp(cpu, valid_cpus[i]) == 0) {
-+        if (value & (1U << i)) {
++            return true;
 +            npcm7xx_timer_check_interrupt(&s->timer[i]);
 +        }
 +    }
++    return false;
 +}
 +
-+static hwaddr npcm7xx_tcsr_index(hwaddr reg)
+ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
-+{
+ {
-+    switch (reg) {
+     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
-+    case NPCM7XX_TIMER_TCSR0:
+@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
-+        return 0;
+     const CPUArchIdList *possible_cpus;
-+    case NPCM7XX_TIMER_TCSR1:
+     int n, sbsa_max_cpus;
-+        return 1;
-+    case NPCM7XX_TIMER_TCSR2:
+-    if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
-+        return 2;
+-        error_report("sbsa-ref: CPU type other than the built-in "
-+    case NPCM7XX_TIMER_TCSR3:
+-                     "cortex-a57 not supported");
-+        return 3;
++    if (!cpu_type_valid(machine->cpu_type)) {
-+    case NPCM7XX_TIMER_TCSR4:
++        error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
-+        return 4;
+         exit(1);
-+    default:
+     }
-+        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_ticr_index(hwaddr reg)
 +{
 +    switch (reg) {
 +    case NPCM7XX_TIMER_TICR0:
 +        return 0;
 +    case NPCM7XX_TIMER_TICR1:
 +        return 1;
 +    case NPCM7XX_TIMER_TICR2:
 +        return 2;
 +    case NPCM7XX_TIMER_TICR3:
 +        return 3;
 +    case NPCM7XX_TIMER_TICR4:
 +        return 4;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static hwaddr npcm7xx_tdr_index(hwaddr reg)
 +{
 +    switch (reg) {
 +    case NPCM7XX_TIMER_TDR0:
 +        return 0;
 +    case NPCM7XX_TIMER_TDR1:
 +        return 1;
 +    case NPCM7XX_TIMER_TDR2:
 +        return 2;
 +    case NPCM7XX_TIMER_TDR3:
 +        return 3;
 +    case NPCM7XX_TIMER_TDR4:
 +        return 4;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
 +static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    NPCM7xxTimerCtrlState *s = opaque;
 +    uint64_t value = 0;
 +    hwaddr reg;
 +
 +    reg = offset / sizeof(uint32_t);
 +    switch (reg) {
 +    case NPCM7XX_TIMER_TCSR0:
 +    case NPCM7XX_TIMER_TCSR1:
 +    case NPCM7XX_TIMER_TCSR2:
 +    case NPCM7XX_TIMER_TCSR3:
 +    case NPCM7XX_TIMER_TCSR4:
 +        value = s->timer[npcm7xx_tcsr_index(reg)].tcsr;
 +        break;
 +
 +    case NPCM7XX_TIMER_TICR0:
 +    case NPCM7XX_TIMER_TICR1:
 +    case NPCM7XX_TIMER_TICR2:
 +    case NPCM7XX_TIMER_TICR3:
 +    case NPCM7XX_TIMER_TICR4:
 +        value = s->timer[npcm7xx_ticr_index(reg)].ticr;
 +        break;
 +
 +    case NPCM7XX_TIMER_TDR0:
 +    case NPCM7XX_TIMER_TDR1:
 +    case NPCM7XX_TIMER_TDR2:
 +    case NPCM7XX_TIMER_TDR3:
 +    case NPCM7XX_TIMER_TDR4:
 +        value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]);
 +        break;
 +
 +    case NPCM7XX_TIMER_TISR:
 +        value = s->tisr;
 +        break;
 +
 +    case NPCM7XX_TIMER_WTCR:
 +        value = s->wtcr;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    trace_npcm7xx_timer_read(DEVICE(s)->canonical_path, offset, value);
 +
 +    return value;
 +}
 +
 +static void npcm7xx_timer_write(void *opaque, hwaddr offset,
 +                                uint64_t v, unsigned size)
 +{
 +    uint32_t reg = offset / sizeof(uint32_t);
 +    NPCM7xxTimerCtrlState *s = opaque;
 +    uint32_t value = v;
 +
 +    trace_npcm7xx_timer_write(DEVICE(s)->canonical_path, offset, value);
 +
 +    switch (reg) {
 +    case NPCM7XX_TIMER_TCSR0:
 +    case NPCM7XX_TIMER_TCSR1:
 +    case NPCM7XX_TIMER_TCSR2:
 +    case NPCM7XX_TIMER_TCSR3:
 +    case NPCM7XX_TIMER_TCSR4:
 +        npcm7xx_timer_write_tcsr(&s->timer[npcm7xx_tcsr_index(reg)], value);
 +        return;
 +
 +    case NPCM7XX_TIMER_TICR0:
 +    case NPCM7XX_TIMER_TICR1:
 +    case NPCM7XX_TIMER_TICR2:
 +    case NPCM7XX_TIMER_TICR3:
 +    case NPCM7XX_TIMER_TICR4:
 +        npcm7xx_timer_write_ticr(&s->timer[npcm7xx_ticr_index(reg)], value);
 +        return;
 +
 +    case NPCM7XX_TIMER_TDR0:
 +    case NPCM7XX_TIMER_TDR1:
 +    case NPCM7XX_TIMER_TDR2:
 +    case NPCM7XX_TIMER_TDR3:
 +    case NPCM7XX_TIMER_TDR4:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        return;
 +
 +    case NPCM7XX_TIMER_TISR:
 +        npcm7xx_timer_write_tisr(s, value);
 +        return;
 +
 +    case NPCM7XX_TIMER_WTCR:
 +        qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
 +                      __func__, value);
 +        return;
 +    }
 +
 +    qemu_log_mask(LOG_GUEST_ERROR,
 +                  "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
 +                  __func__, offset);
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_timer_ops = {
 +    .read       = npcm7xx_timer_read,
 +    .write      = npcm7xx_timer_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +/* Called when the QEMU timer expires. */
 +static void npcm7xx_timer_expired(void *opaque)
 +{
 +    NPCM7xxTimer *t = opaque;
 +
 +    if (t->tcsr & NPCM7XX_TCSR_CEN) {
 +        npcm7xx_timer_reached_zero(t);
 +    }
 +}
 +
 +static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
 +        NPCM7xxTimer *t = &s->timer[i];
 +
 +        timer_del(&t->qtimer);
 +        t->expires_ns = 0;
 +        t->remaining_ns = 0;
 +        t->tcsr = 0x00000005;
 +        t->ticr = 0x00000000;
 +    }
 +
 +    s->tisr = 0x00000000;
 +    s->wtcr = 0x00000400;
 +}
 +
 +static void npcm7xx_timer_hold_reset(Object *obj)
 +{
 +    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
 +        qemu_irq_lower(s->timer[i].irq);
 +    }
 +}
 +
 +static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
 +{
 +    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
 +    SysBusDevice *sbd = &s->parent;
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
 +        NPCM7xxTimer *t = &s->timer[i];
 +        t->ctrl = s;
 +        timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
 +        sysbus_init_irq(sbd, &t->irq);
 +    }
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
 +                          TYPE_NPCM7XX_TIMER, 4 * KiB);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_timer = {
 +    .name = "npcm7xx-timer",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_TIMER(qtimer, NPCM7xxTimer),
 +        VMSTATE_INT64(expires_ns, NPCM7xxTimer),
 +        VMSTATE_INT64(remaining_ns, NPCM7xxTimer),
 +        VMSTATE_UINT32(tcsr, NPCM7xxTimer),
 +        VMSTATE_UINT32(ticr, NPCM7xxTimer),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
 +    .name = "npcm7xx-timer-ctrl",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
 +        VMSTATE_UINT32(wtcr, NPCM7xxTimerCtrlState),
 +        VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
 +                             NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
 +                             NPCM7xxTimer),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
 +
 +    dc->desc = "NPCM7xx Timer Controller";
 +    dc->realize = npcm7xx_timer_realize;
 +    dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
 +    rc->phases.enter = npcm7xx_timer_enter_reset;
 +    rc->phases.hold = npcm7xx_timer_hold_reset;
 +}
 +
 +static const TypeInfo npcm7xx_timer_info = {
 +    .name               = TYPE_NPCM7XX_TIMER,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxTimerCtrlState),
 +    .class_init         = npcm7xx_timer_class_init,
 +};
 +
 +static void npcm7xx_timer_register_type(void)
 +{
 +    type_register_static(&npcm7xx_timer_info);
 +}
 +type_init(npcm7xx_timer_register_type);
 diff --git a/hw/timer/meson.build b/hw/timer/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/meson.build
 +++ b/hw/timer/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_timer.c'))
  softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-sysctl.c'))
  softmmu_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gictimer.c'))
  softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-timer.c'))
 +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_timer.c'))
  softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_timer.c'))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gptimer.c'))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_synctimer.c'))
 diff --git a/hw/timer/trace-events b/hw/timer/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/timer/trace-events
 +++ b/hw/timer/trace-events
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK A
  cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
  cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
 +# npcm7xx_timer.c
 +npcm7xx_timer_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
 +npcm7xx_timer_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
 +npcm7xx_timer_irq(const char *id, int timer, int state) "%s timer %d state %d"
 +
  # nrf51_timer.c
  nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
  nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
 --
 .20.1

-[PULL 25/36] hw/arm: Load -bios image as a boot ROM for npcm7xx
+[PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure
 From: Havard Skinnemoen <hskinnemoen@google.com>
-If a -bios option is specified on the command line, load the image into
+Dump the collected random data after a randomness test failure.
 the internal ROM memory region, which contains the first instructions
 run by the CPU after reset.
-If -bios is not specified, the vbootrom included with qemu is loaded by
+Note that this relies on the test having called
-default.
+g_test_set_nonfatal_assertions() so we don't abort immediately on the
 assertion failure.
-Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
-Message-id: 20200911052101.2602693-8-hskinnemoen@google.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 [PMM: minor commit message tweak]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/npcm7xx_boards.c | 32 ++++++++++++++++++++++++++++++++
+ tests/qtest/npcm7xx_rng-test.c | 12 ++++++++++++
-file changed, 32 insertions(+)
+file changed, 12 insertions(+)
-diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
+diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/npcm7xx_boards.c
+--- a/tests/qtest/npcm7xx_rng-test.c
-+++ b/hw/arm/npcm7xx_boards.c
++++ b/tests/qtest/npcm7xx_rng-test.c
 @@ -XXX,XX +XXX,XX @@
- #include "exec/address-spaces.h"
- #include "hw/arm/npcm7xx.h"
+ #include "libqtest-single.h"
- #include "hw/core/cpu.h"
+ #include "qemu/bitops.h"
 +#include "hw/loader.h"
  #include "qapi/error.h"
 +#include "qemu-common.h"
- #include "qemu/units.h"
-+#include "sysemu/sysemu.h"
+ #define RNG_BASE_ADDR   0xf000b000
- #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
+@@ -XXX,XX +XXX,XX @@
- #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
+ /* Number of bits to collect for randomness tests. */
+ #define TEST_INPUT_BITS  (128)
-+static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
-+
++static void dump_buf_if_failed(const uint8_t *buf, size_t size)
 +static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
 +{
-+    g_autofree char *filename = NULL;
++    if (g_test_failed()) {
-+    int ret;
++        qemu_hexdump(stderr, "", buf, size);
 +
 +    if (!bios_name) {
 +        bios_name = npcm7xx_default_bootrom;
 +    }
 +
 +    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 +    if (!filename) {
 +        error_report("Could not find ROM image '%s'", bios_name);
 +        if (!machine->kernel_filename) {
 +            /* We can't boot without a bootrom or a kernel image. */
 +            exit(1);
 +        }
 +        return;
 +    }
 +    ret = load_image_mr(filename, &soc->irom);
 +    if (ret < 0) {
 +        error_report("Failed to load ROM image '%s'", filename);
 +        exit(1);
 +    }
 +}
 +
- static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
+ static void rng_writeb(unsigned int offset, uint8_t value)
  {
-     memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
+     writeb(RNG_BASE_ADDR + offset, value);
-@@ -XXX,XX +XXX,XX @@ static void npcm750_evb_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void test_continuous_monobit(void)
-     npcm7xx_connect_dram(soc, machine->ram);
+     }
-     qdev_realize(DEVICE(soc), NULL, &error_fatal);
+     g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
-+    npcm7xx_load_bootrom(machine, soc);
++    dump_buf_if_failed(buf, sizeof(buf));
      npcm7xx_load_kernel(machine, soc);
  }
-@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_init(MachineState *machine)
+ /*
-     npcm7xx_connect_dram(soc, machine->ram);
+@@ -XXX,XX +XXX,XX @@ static void test_continuous_runs(void)
-     qdev_realize(DEVICE(soc), NULL, &error_fatal);
+     }
-+    npcm7xx_load_bootrom(machine, soc);
+     g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
-     npcm7xx_load_kernel(machine, soc);
++    dump_buf_if_failed(buf.c, sizeof(buf));
  }
+ /*
+@@ -XXX,XX +XXX,XX @@ static void test_first_byte_monobit(void)
+     }
+     g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
++    dump_buf_if_failed(buf, sizeof(buf));
+ }
+ /*
+@@ -XXX,XX +XXX,XX @@ static void test_first_byte_runs(void)
+     }
+     g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
++    dump_buf_if_failed(buf.c, sizeof(buf));
+ }
+ int main(int argc, char **argv)
 --
 .20.1

-[PULL 03/36] hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
+[PULL 08/36] i.MX25: Fix bad printf format specifiers
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Alex Chen <alex.chen@huawei.com>
-This model implementation is designed for 32-bit accesses.
+We should use printf format specifier "%u" instead of "%d" for
-We can simplify setting the MemoryRegionOps::impl min/max
+argument of type "unsigned int".
 fields to 32-bit (memory::access_with_adjusted_size() will
 take care of the 8/16-bit accesses).
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reported-by: Euler Robot <euler.robot@huawei.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Alex Chen <alex.chen@huawei.com>
-Message-id: 20200901144100.116742-4-f4bug@amsat.org
+Message-id: 20201126111109.112238-2-alex.chen@huawei.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/misc/a9scu.c | 16 +++++-----------
+ hw/misc/imx25_ccm.c | 12 ++++++------
-file changed, 5 insertions(+), 11 deletions(-)
+file changed, 6 insertions(+), 6 deletions(-)
-diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
+diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/a9scu.c
+--- a/hw/misc/imx25_ccm.c
-+++ b/hw/misc/a9scu.c
++++ b/hw/misc/imx25_ccm.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ static const char *imx25_ccm_reg_name(uint32_t reg)
-         return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
+     case IMX25_CCM_LPIMR1_REG:
-     case 0x08: /* CPU Power Status */
+         return "lpimr1";
-         return s->status;
+     default:
--    case 0x09: /* CPU status.  */
+-        sprintf(unknown, "[%d ?]", reg);
--        return s->status >> 8;
++        sprintf(unknown, "[%u ?]", reg);
--    case 0x0a: /* CPU status.  */
+         return unknown;
--        return s->status >> 16;
+     }
--    case 0x0b: /* CPU status.  */
+ }
--        return s->status >> 24;
+@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev)
-     case 0x0c: /* Invalidate All Registers In Secure State */
+         freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ);
-         return 0;
+     }
-     case 0x40: /* Filtering Start Address Register */
-@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
+-    DPRINTF("freq = %d\n", freq);
-                          uint64_t value, unsigned size)
++    DPRINTF("freq = %u\n", freq);
- {
-     A9SCUState *s = (A9SCUState *)opaque;
+     return freq;
--    uint32_t mask = MAKE_64BIT_MASK(0, size * 8);
+ }
--    uint32_t shift;
+@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev)
-     switch (offset) {
+     freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV));
-     case 0x00: /* Control */
-@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
+-    DPRINTF("freq = %d\n", freq);
-     case 0x4: /* Configuration: RO */
++    DPRINTF("freq = %u\n", freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev)
      freq = imx25_ccm_get_mcu_clk(dev)
             / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV));
 -    DPRINTF("freq = %d\n", freq);
 +    DPRINTF("freq = %u\n", freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev)
      freq = imx25_ccm_get_ahb_clk(dev) / 2;
 -    DPRINTF("freq = %d\n", freq);
 +    DPRINTF("freq = %u\n", freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
          break;
-     case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
+     }
--        shift = (offset - 0x8) * 8;
--        s->status &= ~(mask << shift);
+-    DPRINTF("Clock = %d) = %d\n", clock, freq);
--        s->status |= ((value & mask) << shift);
++    DPRINTF("Clock = %d) = %u\n", clock, freq);
-+        s->status = value;
-         break;
+     return freq;
-     case 0x0c: /* Invalidate All Registers In Secure State */
+ }
          /* no-op as we do not implement caches */
@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
  static const MemoryRegionOps a9_scu_ops = {
      .read = a9_scu_read,
      .write = a9_scu_write,
 +    .impl = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
      .valid = {
          .min_access_size = 1,
          .max_access_size = 4,
 --
 .20.1

-[PULL 29/36] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
+[PULL 09/36] i.MX31: Fix bad printf format specifiers
-From: Havard Skinnemoen <hskinnemoen@google.com>
+From: Alex Chen <alex.chen@huawei.com>
-This allows these NPCM7xx-based boards to boot from a flash image, e.g.
+We should use printf format specifier "%u" instead of "%d" for
-one built with OpenBMC. For example like this:
+argument of type "unsigned int".
-IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc
+Reported-by: Euler Robot <euler.robot@huawei.com>
-qemu-system-arm -machine quanta-gsj -nographic \
+Signed-off-by: Alex Chen <alex.chen@huawei.com>
-    -drive file=${IMAGE},if=mtd,bus=0,unit=0,format=raw,snapshot=on
+Message-id: 20201126111109.112238-3-alex.chen@huawei.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Tested-by: Cédric Le Goater <clg@kaod.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200911052101.2602693-12-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/npcm7xx_boards.c | 20 ++++++++++++++++++++
+ hw/misc/imx31_ccm.c | 14 +++++++-------
-file changed, 20 insertions(+)
+ hw/misc/imx_ccm.c   |  4 ++--
 files changed, 9 insertions(+), 9 deletions(-)
-diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
+diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/npcm7xx_boards.c
+--- a/hw/misc/imx31_ccm.c
-+++ b/hw/arm/npcm7xx_boards.c
++++ b/hw/misc/imx31_ccm.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const char *imx31_ccm_reg_name(uint32_t reg)
- #include "hw/arm/npcm7xx.h"
+     case IMX31_CCM_PDR2_REG:
- #include "hw/core/cpu.h"
+         return "PDR2";
- #include "hw/loader.h"
+     default:
-+#include "hw/qdev-properties.h"
+-        sprintf(unknown, "[%d ?]", reg);
- #include "qapi/error.h"
++        sprintf(unknown, "[%u ?]", reg);
- #include "qemu-common.h"
+         return unknown;
  #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
      }
  }
+@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
-+static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
+         freq = CKIH_FREQ;
-+                                  const char *flash_type, DriveInfo *dinfo)
+     }
-+{
-+    DeviceState *flash;
+-    DPRINTF("freq = %d\n", freq);
-+    qemu_irq flash_cs;
++    DPRINTF("freq = %u\n", freq);
-+
-+    flash = qdev_new(flash_type);
+     return freq;
 +    if (dinfo) {
 +        qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
 +    }
 +    qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
 +
 +    flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
 +    qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
 +}
 +
  static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
  {
      memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
@@ -XXX,XX +XXX,XX @@ static void npcm750_evb_init(MachineState *machine)
      qdev_realize(DEVICE(soc), NULL, &error_fatal);
      npcm7xx_load_bootrom(machine, soc);
 +    npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
      npcm7xx_load_kernel(machine, soc);
  }
+@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
-@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_init(MachineState *machine)
+     freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
-     qdev_realize(DEVICE(soc), NULL, &error_fatal);
+                             imx31_ccm_get_pll_ref_clk(dev));
-     npcm7xx_load_bootrom(machine, soc);
+-    DPRINTF("freq = %d\n", freq);
-+    npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
++    DPRINTF("freq = %u\n", freq);
-+                          drive_get(IF_MTD, 0, 0));
-     npcm7xx_load_kernel(machine, soc);
+     return freq;
  }
+@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
          freq = imx31_ccm_get_mpll_clk(dev);
      }
 -    DPRINTF("freq = %d\n", freq);
 +    DPRINTF("freq = %u\n", freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
      freq = imx31_ccm_get_mcu_main_clk(dev)
             / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
 -    DPRINTF("freq = %d\n", freq);
 +    DPRINTF("freq = %u\n", freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
      freq = imx31_ccm_get_hclk_clk(dev)
             / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
 -    DPRINTF("freq = %d\n", freq);
 +    DPRINTF("freq = %u\n", freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
          break;
      }
 -    DPRINTF("Clock = %d) = %d\n", clock, freq);
 +    DPRINTF("Clock = %d) = %u\n", clock, freq);
      return freq;
  }
 diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/imx_ccm.c
 +++ b/hw/misc/imx_ccm.c
@@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
          freq = klass->get_clock_frequency(dev, clock);
      }
 -    DPRINTF("(clock = %d) = %d\n", clock, freq);
 +    DPRINTF("(clock = %d) = %u\n", clock, freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq)
      freq = ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) /
              (mfd * pd)) << 10;
 -    DPRINTF("(pllreg = 0x%08x, base_freq = %d) = %d\n", pllreg, base_freq,
 +    DPRINTF("(pllreg = 0x%08x, base_freq = %u) = %d\n", pllreg, base_freq,
              freq);
      return freq;
 --
 .20.1

-[PULL 02/36] hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
+[PULL 10/36] i.MX6: Fix bad printf format specifiers
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Alex Chen <alex.chen@huawei.com>
-Per the datasheet (DDI0407 r2p0):
+We should use printf format specifier "%u" instead of "%d" for
 argument of type "unsigned int".
-  "All SCU registers are byte accessible" and are 32-bit aligned.
+Reported-by: Euler Robot <euler.robot@huawei.com>
+Signed-off-by: Alex Chen <alex.chen@huawei.com>
-Set MemoryRegionOps::valid min/max fields and simplify the write()
+Message-id: 20201126111109.112238-4-alex.chen@huawei.com
-handler.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200901144100.116742-3-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/misc/a9scu.c | 21 +++++----------------
+ hw/misc/imx6_ccm.c | 20 ++++++++++----------
-file changed, 5 insertions(+), 16 deletions(-)
+ hw/misc/imx6_src.c |  2 +-
 files changed, 11 insertions(+), 11 deletions(-)
-diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
+diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/a9scu.c
+--- a/hw/misc/imx6_ccm.c
-+++ b/hw/misc/a9scu.c
++++ b/hw/misc/imx6_ccm.c
-@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ static const char *imx6_ccm_reg_name(uint32_t reg)
-                          uint64_t value, unsigned size)
+     case CCM_CMEOR:
- {
+         return "CMEOR";
-     A9SCUState *s = (A9SCUState *)opaque;
+     default:
--    uint32_t mask;
+-        sprintf(unknown, "%d ?", reg);
-+    uint32_t mask = MAKE_64BIT_MASK(0, size * 8);
++        sprintf(unknown, "%u ?", reg);
-     uint32_t shift;
+         return unknown;
--    switch (size) {
+     }
--    case 1:
+ }
--        mask = 0xff;
+@@ -XXX,XX +XXX,XX @@ static const char *imx6_analog_reg_name(uint32_t reg)
--        break;
+     case USB_ANALOG_DIGPROG:
--    case 2:
+         return "USB_ANALOG_DIGPROG";
--        mask = 0xffff;
+     default:
--        break;
+-        sprintf(unknown, "%d ?", reg);
--    case 4:
++        sprintf(unknown, "%u ?", reg);
--        mask = 0xffffffff;
+         return unknown;
--        break;
+     }
--    default:
+ }
--        fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
+@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState *dev)
--                size, (unsigned)offset);
+         freq *= 20;
--        return;
+     }
--    }
+-    DPRINTF("freq = %d\n", (uint32_t)freq);
-     switch (offset) {
++    DPRINTF("freq = %u\n", (uint32_t)freq);
-     case 0x00: /* Control */
-@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
+     return freq;
- static const MemoryRegionOps a9_scu_ops = {
+ }
-     .read = a9_scu_read,
+@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMState *dev)
-     .write = a9_scu_write,
+     freq = imx6_analog_get_pll2_clk(dev) * 18
-+    .valid = {
+            / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD0_FRAC);
-+        .min_access_size = 1,
-+        .max_access_size = 4,
+-    DPRINTF("freq = %d\n", (uint32_t)freq);
-+    },
++    DPRINTF("freq = %u\n", (uint32_t)freq);
-     .endianness = DEVICE_NATIVE_ENDIAN,
- };
+     return freq;
+ }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd2_clk(IMX6CCMState *dev)
      freq = imx6_analog_get_pll2_clk(dev) * 18
             / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD2_FRAC);
 -    DPRINTF("freq = %d\n", (uint32_t)freq);
 +    DPRINTF("freq = %u\n", (uint32_t)freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_periph_clk(IMX6CCMState *dev)
          break;
      }
 -    DPRINTF("freq = %d\n", (uint32_t)freq);
 +    DPRINTF("freq = %u\n", (uint32_t)freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ahb_clk(IMX6CCMState *dev)
      freq = imx6_analog_get_periph_clk(dev)
             / (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF));
 -    DPRINTF("freq = %d\n", (uint32_t)freq);
 +    DPRINTF("freq = %u\n", (uint32_t)freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ipg_clk(IMX6CCMState *dev)
      freq = imx6_ccm_get_ahb_clk(dev)
             / (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF));
 -    DPRINTF("freq = %d\n", (uint32_t)freq);
 +    DPRINTF("freq = %u\n", (uint32_t)freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev)
      freq = imx6_ccm_get_ipg_clk(dev)
             / (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF));
 -    DPRINTF("freq = %d\n", (uint32_t)freq);
 +    DPRINTF("freq = %u\n", (uint32_t)freq);
      return freq;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
          break;
      }
 -    DPRINTF("Clock = %d) = %d\n", clock, freq);
 +    DPRINTF("Clock = %d) = %u\n", clock, freq);
      return freq;
  }
 diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/imx6_src.c
 +++ b/hw/misc/imx6_src.c
@@ -XXX,XX +XXX,XX @@ static const char *imx6_src_reg_name(uint32_t reg)
      case SRC_GPR10:
          return "SRC_GPR10";
      default:
 -        sprintf(unknown, "%d ?", reg);
 +        sprintf(unknown, "%u ?", reg);
          return unknown;
      }
  }
 --
 .20.1

-[PULL 04/36] hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
+[PULL 11/36] i.MX6ul: Fix bad printf format specifiers
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Alex Chen <alex.chen@huawei.com>
-Report unimplemented register accesses using qemu_log_mask(UNIMP).
+We should use printf format specifier "%u" instead of "%d" for
 argument of type "unsigned int".
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reported-by: Euler Robot <euler.robot@huawei.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Alex Chen <alex.chen@huawei.com>
-Message-id: 20200901144100.116742-5-f4bug@amsat.org
+Message-id: 20201126111109.112238-5-alex.chen@huawei.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/misc/a9scu.c | 6 ++++++
+ hw/misc/imx6ul_ccm.c | 4 ++--
-file changed, 6 insertions(+)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
+diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/a9scu.c
+--- a/hw/misc/imx6ul_ccm.c
-+++ b/hw/misc/a9scu.c
++++ b/hw/misc/imx6ul_ccm.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const char *imx6ul_ccm_reg_name(uint32_t reg)
- #include "hw/qdev-properties.h"
+     case CCM_CMEOR:
- #include "migration/vmstate.h"
+         return "CMEOR";
  #include "qapi/error.h"
 +#include "qemu/log.h"
  #include "qemu/module.h"
  #define A9_SCU_CPU_MAX  4
@@ -XXX,XX +XXX,XX @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset,
      case 0x54: /* SCU Non-secure Access Control Register */
          /* unimplemented, fall through */
      default:
-+        qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n",
+-        sprintf(unknown, "%d ?", reg);
-+                      __func__, offset);
++        sprintf(unknown, "%u ?", reg);
-         return 0;
+         return unknown;
      }
  }
-@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ static const char *imx6ul_analog_reg_name(uint32_t reg)
-     case 0x54: /* SCU Non-secure Access Control Register */
+     case USB_ANALOG_DIGPROG:
-         /* unimplemented, fall through */
+         return "USB_ANALOG_DIGPROG";
      default:
-+        qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx
+-        sprintf(unknown, "%d ?", reg);
-+                                 " value 0x%"PRIx64"\n",
++        sprintf(unknown, "%u ?", reg);
-+                      __func__, offset, value);
+         return unknown;
          break;
      }
  }
 --
 .20.1

-[PULL 23/36] hw/arm: Add two NPCM7xx-based machines
+[PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
-From: Havard Skinnemoen <hskinnemoen@google.com>
+For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the
 Private Peripheral Bus range, which includes all of the memory mapped
 devices and registers that are part of the CPU itself, including the
 NVIC, systick timer, and debug and trace components like the Data
 Watchpoint and Trace unit (DWT).  Within this large region, the range
 xe000e000 to 0xe000efff is the System Control Space (NVIC, system
 registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure
 alias.
-This adds two new machines, both supported by OpenBMC:
+The architecture is clear that within the SCS unimplemented registers
 should be RES0 for privileged accesses and generate BusFault for
 unprivileged accesses, and we currently implement this.
-  - npcm750-evb: Nuvoton NPCM750 Evaluation Board.
+It is less clear about how to handle accesses to unimplemented
-  - quanta-gsj: A board with a NPCM730 chip.
+regions of the wider PPB.  Unprivileged accesses should definitely
 cause BusFaults (R_DQQS), but the behaviour of privileged accesses is
 not given as a general rule.  However, the register definitions of
 individual registers for components like the DWT all state that they
 are RES0 if the relevant component is not implemented, so the
 simplest way to provide that is to provide RAZ/WI for the whole range
 for privileged accesses.  (The v7M Arm ARM does say that reserved
 registers should be UNK/SBZP.)
-They rely on the NPCM7xx SoC device to do the heavy lifting. They are
+Expand the container MemoryRegion that the NVIC exposes so that
-almost completely identical at the moment, apart from the SoC type,
+it covers the whole PPB space. This means:
-which currently only changes the reset contents of one register
+ * moving the address that the ARMV7M device maps it to down by
-(GCR.MDLR), but they might grow apart a bit more as more functionality
+xe000 bytes
-is added.
+ * moving the off and the offsets within the container of all the
    subregions forward by 0xe000 bytes
  * adding a new default MemoryRegion that covers the whole container
    at a lower priority than anything else and which provides the
    RAZWI/BusFault behaviour
-Both machines can boot the Linux kernel into /bin/sh.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20201119215617.29887-2-peter.maydell@linaro.org
 ---
  include/hw/intc/armv7m_nvic.h |  1 +
  hw/arm/armv7m.c               |  2 +-
  hw/intc/armv7m_nvic.c         | 78 ++++++++++++++++++++++++++++++-----
 files changed, 69 insertions(+), 12 deletions(-)
-Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
 Reviewed-by: Joel Stanley <joel@jms.id.au>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Alexander Bulekov <alxndr@bu.edu>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-6-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  default-configs/arm-softmmu.mak |   1 +
  include/hw/arm/npcm7xx.h        |  19 +++++
  hw/arm/npcm7xx_boards.c         | 145 ++++++++++++++++++++++++++++++++
  hw/arm/meson.build              |   2 +-
 files changed, 166 insertions(+), 1 deletion(-)
  create mode 100644 hw/arm/npcm7xx_boards.c
 diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
---- a/default-configs/arm-softmmu.mak
+--- a/include/hw/intc/armv7m_nvic.h
-+++ b/default-configs/arm-softmmu.mak
++++ b/include/hw/intc/armv7m_nvic.h
-@@ -XXX,XX +XXX,XX @@ CONFIG_GUMSTIX=y
+@@ -XXX,XX +XXX,XX @@ struct NVICState {
- CONFIG_SPITZ=y
+     MemoryRegion systickmem;
- CONFIG_TOSA=y
+     MemoryRegion systick_ns_mem;
- CONFIG_Z2=y
+     MemoryRegion container;
-+CONFIG_NPCM7XX=y
++    MemoryRegion defaultmem;
- CONFIG_COLLIE=y
- CONFIG_ASPEED_SOC=y
+     uint32_t num_irq;
- CONFIG_NETDUINO2=y
+     qemu_irq excpout;
-diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
+diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/npcm7xx.h
+--- a/hw/arm/armv7m.c
-+++ b/include/hw/arm/npcm7xx.h
++++ b/hw/arm/armv7m.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
- #define NPCM7XX_SMP_BOOTREG_ADDR        (0xf080013c)  /* GCR.SCRPAD */
+     sysbus_connect_irq(sbd, 0,
- #define NPCM7XX_GIC_CPU_IF_ADDR         (0xf03fe100)  /* GIC within A9 */
+                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
-+typedef struct NPCM7xxMachine {
+-    memory_region_add_subregion(&s->container, 0xe000e000,
-+    MachineState        parent;
++    memory_region_add_subregion(&s->container, 0xe0000000,
-+} NPCM7xxMachine;
+                                 sysbus_mmio_get_region(sbd, 0));
-+
-+#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
+     for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
-+#define NPCM7XX_MACHINE(obj)                                            \
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
-+    OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
+index XXXXXXX..XXXXXXX 100644
-+
+--- a/hw/intc/armv7m_nvic.c
-+typedef struct NPCM7xxMachineClass {
++++ b/hw/intc/armv7m_nvic.c
-+    MachineClass        parent;
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = {
-+
+     .endianness = DEVICE_NATIVE_ENDIAN,
-+    const char          *soc_type;
+ };
-+} NPCM7xxMachineClass;
 +
 +#define NPCM7XX_MACHINE_CLASS(klass)                                    \
 +    OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE)
 +#define NPCM7XX_MACHINE_GET_CLASS(obj)                                  \
 +    OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
 +
  typedef struct NPCM7xxState {
      DeviceState         parent;
 diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@
 +/*
-+ * Machine definitions for boards featuring an NPCM7xx SoC.
++ * Unassigned portions of the PPB space are RAZ/WI for privileged
-+ *
++ * accesses, and fault for non-privileged accesses.
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
-+
++static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
-+#include "qemu/osdep.h"
++                                    uint64_t *data, unsigned size,
-+
++                                    MemTxAttrs attrs)
 +#include "exec/address-spaces.h"
 +#include "hw/arm/npcm7xx.h"
 +#include "hw/core/cpu.h"
 +#include "qapi/error.h"
 +#include "qemu/units.h"
 +
 +#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
 +#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
 +
 +static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
 +{
-+    memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
++    qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
-+
++                  (uint32_t)addr);
-+    object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
++    if (attrs.user) {
-+                             &error_abort);
++        return MEMTX_ERROR;
 +    }
 +    *data = 0;
 +    return MEMTX_OK;
 +}
 +
-+static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
++static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
-+                                        uint32_t hw_straps)
++                                     uint64_t value, unsigned size,
 +                                     MemTxAttrs attrs)
 +{
-+    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
++    qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
-+    MachineClass *mc = &nmc->parent;
++                  (uint32_t)addr);
-+    Object *obj;
++    if (attrs.user) {
-+
++        return MEMTX_ERROR;
 +    if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
 +        error_report("This board can only be used with %s",
 +                     mc->default_cpu_type);
 +        exit(1);
 +    }
-+
++    return MEMTX_OK;
 +    obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
 +                                &error_abort, NULL);
 +    object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
 +
 +    return NPCM7XX(obj);
 +}
 +
-+static void npcm750_evb_init(MachineState *machine)
++static const MemoryRegionOps ppb_default_ops = {
-+{
++    .read_with_attrs = ppb_default_read,
-+    NPCM7xxState *soc;
++    .write_with_attrs = ppb_default_write,
-+
++    .endianness = DEVICE_NATIVE_ENDIAN,
-+    soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
++    .valid.min_access_size = 1,
-+    npcm7xx_connect_dram(soc, machine->ram);
++    .valid.max_access_size = 8,
 +    qdev_realize(DEVICE(soc), NULL, &error_fatal);
 +
 +    npcm7xx_load_kernel(machine, soc);
 +}
 +
 +static void quanta_gsj_init(MachineState *machine)
 +{
 +    NPCM7xxState *soc;
 +
 +    soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
 +    npcm7xx_connect_dram(soc, machine->ram);
 +    qdev_realize(DEVICE(soc), NULL, &error_fatal);
 +
 +    npcm7xx_load_kernel(machine, soc);
 +}
 +
 +static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
 +{
 +    NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
 +    MachineClass *mc = MACHINE_CLASS(nmc);
 +
 +    nmc->soc_type = type;
 +    mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
 +}
 +
 +static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
 +{
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +
 +    mc->no_floppy = 1;
 +    mc->no_cdrom = 1;
 +    mc->no_parallel = 1;
 +    mc->default_ram_id = "ram";
 +    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 +}
 +
 +/*
 + * Schematics:
 + * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
 + */
 +static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
 +{
 +    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +
 +    npcm7xx_set_soc_type(nmc, TYPE_NPCM750);
 +
 +    mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)";
 +    mc->init = npcm750_evb_init;
 +    mc->default_ram_size = 512 * MiB;
 +};
 +
-+static void gsj_machine_class_init(ObjectClass *oc, void *data)
+ static int nvic_post_load(void *opaque, int version_id)
-+{
+ {
-+    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
+     NVICState *s = opaque;
-+    MachineClass *mc = MACHINE_CLASS(oc);
+@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
-+
+ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
-+    npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
+ {
-+
+     NVICState *s = NVIC(dev);
-+    mc->desc = "Quanta GSJ (Cortex A9)";
+-    int regionlen;
-+    mc->init = quanta_gsj_init;
-+    mc->default_ram_size = 512 * MiB;
+     /* The armv7m container object will have set our CPU pointer */
-+};
+     if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) {
-+
+@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
-+static const TypeInfo npcm7xx_machine_types[] = {
+                                                   M_REG_S));
-+    {
+     }
-+        .name           = TYPE_NPCM7XX_MACHINE,
-+        .parent         = TYPE_MACHINE,
+-    /* The NVIC and System Control Space (SCS) starts at 0xe000e000
-+        .instance_size  = sizeof(NPCM7xxMachine),
++    /*
-+        .class_size     = sizeof(NPCM7xxMachineClass),
++     * This device provides a single sysbus memory region which
-+        .class_init     = npcm7xx_machine_class_init,
++     * represents the whole of the "System PPB" space. This is the
-+        .abstract       = true,
++     * range from 0xe0000000 to 0xe00fffff and includes the NVIC,
-+    }, {
++     * the System Control Space (system registers), the systick timer,
-+        .name           = MACHINE_TYPE_NAME("npcm750-evb"),
++     * and for CPUs with the Security extension an NS banked version
-+        .parent         = TYPE_NPCM7XX_MACHINE,
++     * of all of these.
-+        .class_init     = npcm750_evb_machine_class_init,
++     *
-+    }, {
++     * The default behaviour for unimplemented registers/ranges
-+        .name           = MACHINE_TYPE_NAME("quanta-gsj"),
++     * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
-+        .parent         = TYPE_NPCM7XX_MACHINE,
++     * is to RAZ/WI for privileged access and BusFault for non-privileged
-+        .class_init     = gsj_machine_class_init,
++     * access.
-+    },
++     *
-+};
++     * The NVIC and System Control Space (SCS) starts at 0xe000e000
-+
+      * and looks like this:
-+DEFINE_TYPES(npcm7xx_machine_types)
+      *  0x004 - ICTR
-diff --git a/hw/arm/meson.build b/hw/arm/meson.build
+      *  0x010 - 0xff - systick
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
---- a/hw/arm/meson.build
+      * generally code determining which banked register to use should
-+++ b/hw/arm/meson.build
+      * use attrs.secure; code determining actual behaviour of the system
-@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
+      * should use env->v7m.secure.
- arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
++     *
- arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
++     * The container covers the whole PPB space. Within it the priority
- arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
++     * of overlapping regions is:
--arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c'))
++     *  - default region (for RAZ/WI and BusFault) : -1
-+arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
++     *  - system register regions : 0
- arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
++     *  - systick : 1
- arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
++     * This is because the systick device is a small block of registers
- arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
++     * in the middle of the other system control registers.
       */
 -    regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000;
 -    memory_region_init(&s->container, OBJECT(s), "nvic", regionlen);
 -    /* The system register region goes at the bottom of the priority
 -     * stack as it covers the whole page.
 -     */
 +    memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000);
 +    memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
 +                          "nvic-default", 0x100000);
 +    memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1);
      memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
                            "nvic_sysregs", 0x1000);
 -    memory_region_add_subregion(&s->container, 0, &s->sysregmem);
 +    memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
      memory_region_init_io(&s->systickmem, OBJECT(s),
                            &nvic_systick_ops, s,
                            "nvic_systick", 0xe0);
 -    memory_region_add_subregion_overlap(&s->container, 0x10,
 +    memory_region_add_subregion_overlap(&s->container, 0xe010,
                                          &s->systickmem, 1);
      if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
          memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
                                &nvic_sysreg_ns_ops, &s->sysregmem,
                                "nvic_sysregs_ns", 0x1000);
 -        memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem);
 +        memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
          memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
                                &nvic_sysreg_ns_ops, &s->systickmem,
                                "nvic_systick_ns", 0xe0);
 -        memory_region_add_subregion_overlap(&s->container, 0x20010,
 +        memory_region_add_subregion_overlap(&s->container, 0x2e010,
                                              &s->systick_ns_mem, 1);
      }
 --
 .20.1

-[PULL 17/36] target/arm: Count PMU events when MDCR.SPME is set
+[PULL 13/36] target/arm: Implement v8.1M PXN extension
-From: Aaron Lindsay <aaron@os.amperecomputing.com>
+In v8.1M the PXN architecture extension adds a new PXN bit to the
 MPU_RLAR registers, which forbids execution of code in the region
 from a privileged mode.
-This check was backwards when introduced in commit
+This is another feature which is just in the generic "in v8.1M" set
-c47de78409ad3fb39bb7bd1483b71c6789:
+and has no ID register field indicating its presence.
-    target/arm: Filter cycle counter based on PMCCFILTR_EL0
-Cc: qemu-stable@nongnu.org
-Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20201119215617.29887-3-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 2 +-
+ target/arm/helper.c | 7 ++++++-
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 6 insertions(+), 1 deletion(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
+@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
      } else {
          uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
          uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
 +        bool pxn = false;
 +
 +        if (arm_feature(env, ARM_FEATURE_V8_1M)) {
 +            pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
 +        }
          if (m_is_system_region(env, address)) {
              /* System space is always execute never */
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
          }
-     } else {
-         prohibited = arm_feature(env, ARM_FEATURE_EL3) &&
+         *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
--           (env->cp15.mdcr_el3 & MDCR_SPME);
+-        if (*prot && !xn) {
-+           !(env->cp15.mdcr_el3 & MDCR_SPME);
++        if (*prot && !xn && !(pxn && !is_user)) {
-     }
+             *prot |= PAGE_EXEC;
+         }
-     if (prohibited && counter == 31) {
+         /* We don't need to look the attribute up in the MAIR0/MAIR1
 --
 .20.1

-[PULL 18/36] hw/arm: versal-virt: Correct the tx/rx GEM clocks
+[PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+In arm_cpu_realizefn() we check whether the board code disabled EL3
 via the has_el3 CPU object property, which we create if the CPU
 starts with the ARM_FEATURE_EL3 feature bit.  If it is disabled, then
 we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in
 the ID_PFR1 and ID_AA64PFR0 registers.
-Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock.
+This codepath was incorrectly being taken for M-profile CPUs, which
-This matches the setup with the fixed-link 100Mbit PHY.
+do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have
-It also avoids the following warnings from the Linux kernel
+the M-profile Security extension and so should have non-zero values
-driver:
+in the ID_PFR1.Security field.
-eth0: unable to generate target frequency: 125000000 Hz
+Restrict the handling of the feature flag to A/R-profile cores.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Message-id: 20200909174647.662864-2-edgar.iglesias@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20201119215617.29887-4-peter.maydell@linaro.org
 ---
- hw/arm/xlnx-versal-virt.c | 2 +-
+ target/arm/cpu.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal-virt.c
+--- a/target/arm/cpu.c
-+++ b/hw/arm/xlnx-versal-virt.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_gem_nodes(VersalVirt *s)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-                               s->phandle.ethernet_phy[i]);
+         }
-         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
+     }
-                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
--                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
+-    if (!cpu->has_el3) {
-+                               s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
++    if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
-         qemu_fdt_setprop(s->fdt, name, "clock-names",
+         /* If the has_el3 CPU property is disabled then we need to disable the
-                          clocknames, sizeof(clocknames));
+          * feature.
-         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+          */
 --
 .20.1

-[PULL 27/36] hw/mem: Stubbed out NPCM7xx Memory Controller model
+[PULL 15/36] target/arm: Implement VSCCLRM insn
-From: Havard Skinnemoen <hskinnemoen@google.com>
+Implement the v8.1M VSCCLRM insn, which zeros floating point
+registers if there is an active floating point context.
-This just implements the bare minimum to cause the boot block to skip
+This requires support in write_neon_element32() for the MO_32
-memory initialization.
+element size, so add it.
-Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
+Because we want to use arm_gen_condlabel(), we need to move
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
+the definition of that function up in translate.c so it is
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+before the #include of translate-vfp.c.inc.
-Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Alexander Bulekov <alxndr@bu.edu>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-10-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20201119215617.29887-5-peter.maydell@linaro.org
 ---
- include/hw/arm/npcm7xx.h    |  2 +
+ target/arm/cpu.h               |  9 ++++
- include/hw/mem/npcm7xx_mc.h | 36 ++++++++++++++++
+ target/arm/m-nocp.decode       |  8 +++-
- hw/arm/npcm7xx.c            |  6 +++
+ target/arm/translate.c         | 21 +++++----
- hw/mem/npcm7xx_mc.c         | 84 +++++++++++++++++++++++++++++++++++++
+ target/arm/translate-vfp.c.inc | 84 ++++++++++++++++++++++++++++++++++
- hw/mem/meson.build          |  1 +
+files changed, 111 insertions(+), 11 deletions(-)
-files changed, 129 insertions(+)
- create mode 100644 include/hw/mem/npcm7xx_mc.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
- create mode 100644 hw/mem/npcm7xx_mc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
-diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
++++ b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
---- a/include/hw/arm/npcm7xx.h
+     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
-+++ b/include/hw/arm/npcm7xx.h
+ }
-@@ -XXX,XX +XXX,XX @@
++static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
  #include "hw/boards.h"
  #include "hw/cpu/a9mpcore.h"
 +#include "hw/mem/npcm7xx_mc.h"
  #include "hw/misc/npcm7xx_clk.h"
  #include "hw/misc/npcm7xx_gcr.h"
  #include "hw/nvram/npcm7xx_otp.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
      NPCM7xxTimerCtrlState tim[3];
      NPCM7xxOTPState     key_storage;
      NPCM7xxOTPState     fuse_array;
 +    NPCM7xxMCState      mc;
  } NPCM7xxState;
  #define TYPE_NPCM7XX    "npcm7xx"
 diff --git a/include/hw/mem/npcm7xx_mc.h b/include/hw/mem/npcm7xx_mc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/mem/npcm7xx_mc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx Memory Controller stub
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +#ifndef NPCM7XX_MC_H
 +#define NPCM7XX_MC_H
 +
 +#include "exec/memory.h"
 +#include "hw/sysbus.h"
 +
 +/**
 + * struct NPCM7xxMCState - Device state for the memory controller.
 + * @parent: System bus device.
 + * @mmio: Memory region through which registers are accessed.
 + */
 +typedef struct NPCM7xxMCState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion mmio;
 +} NPCM7xxMCState;
 +
 +#define TYPE_NPCM7XX_MC "npcm7xx-mc"
 +#define NPCM7XX_MC(obj) OBJECT_CHECK(NPCM7xxMCState, (obj), TYPE_NPCM7XX_MC)
 +
 +#endif /* NPCM7XX_MC_H */
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_CPUP_BA         (0xf03fe000)
  #define NPCM7XX_GCR_BA          (0xf0800000)
  #define NPCM7XX_CLK_BA          (0xf0801000)
 +#define NPCM7XX_MC_BA           (0xf0824000)
  /* Internal AHB SRAM */
  #define NPCM7XX_RAM3_BA         (0xc0008000)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
                              TYPE_NPCM7XX_KEY_STORAGE);
      object_initialize_child(obj, "otp2", &s->fuse_array,
                              TYPE_NPCM7XX_FUSE_ARRAY);
 +    object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
          object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
      npcm7xx_init_fuses(s);
 +    /* Fake Memory Controller (MC). Cannot fail. */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 +
      /* Timer Modules (TIM). Cannot fail. */
      QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
 diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/mem/npcm7xx_mc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx Memory Controller stub
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +
 +#include "hw/mem/npcm7xx_mc.h"
 +#include "qapi/error.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/units.h"
 +
 +#define NPCM7XX_MC_REGS_SIZE (4 * KiB)
 +
 +static uint64_t npcm7xx_mc_read(void *opaque, hwaddr addr, unsigned int size)
 +{
 +    /*
-+     * If bits 8..11 @ offset 0 are not zero, the boot block thinks the memory
++     * Return true if M-profile state handling insns
-+     * controller has already been initialized and will skip DDR training.
++     * (VSCCLRM, CLRM, FPCTX access insns) are implemented
 +     */
-+    if (addr == 0) {
++    return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
 +        return 0x100;
 +    }
 +
 +    qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
 +
 +    return 0;
 +}
 +
-+static void npcm7xx_mc_write(void *opaque, hwaddr addr, uint64_t v,
+ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
-+                             unsigned int size)
+ {
      /* Sadly this is encoded differently for A-profile and M-profile */
 diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m-nocp.decode
 +++ b/target/arm/m-nocp.decode
@@ -XXX,XX +XXX,XX @@
  # If the coprocessor is not present or disabled then we will generate
  # the NOCP exception; otherwise we let the insn through to the main decode.
 +%vd_dp  22:1 12:4
 +%vd_sp  12:4 22:1
 +
  &nocp cp
  {
    # Special cases which do not take an early NOCP: VLLDM and VLSTM
    VLLDM_VLSTM  1110 1100 001 l:1 rn:4 0000 1010 0000 0000
 -  # TODO: VSCCLRM (new in v8.1M) is similar:
 -  #VSCCLRM      1110 1100 1-01 1111 ---- 1011 ---- ---0
 +  # VSCCLRM (new in v8.1M) is similar:
 +  VSCCLRM      1110 1100 1.01 1111 .... 1011 imm:7 0   vd=%vd_dp size=3
 +  VSCCLRM      1110 1100 1.01 1111 .... 1010 imm:8     vd=%vd_sp size=2
    NOCP         111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp
    NOCP         111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
      a64_translate_init();
  }
 +/* Generate a label used for skipping this instruction */
 +static void arm_gen_condlabel(DisasContext *s)
 +{
-+    qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
++    if (!s->condjmp) {
 +        s->condlabel = gen_new_label();
 +        s->condjmp = 1;
 +    }
 +}
 +
-+static const MemoryRegionOps npcm7xx_mc_ops = {
+ /* Flags for the disas_set_da_iss info argument:
-+    .read = npcm7xx_mc_read,
+  * lower bits hold the Rt register number, higher bits are flags.
-+    .write = npcm7xx_mc_write,
+  */
-+    .endianness = DEVICE_LITTLE_ENDIAN,
+@@ -XXX,XX +XXX,XX @@ static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
-+    .valid = {
+     long off = neon_element_offset(reg, ele, memop);
-+        .min_access_size = 4,
-+        .max_access_size = 4,
+     switch (memop) {
-+        .unaligned = false,
++    case MO_32:
-+    },
++        tcg_gen_st32_i64(src, cpu_env, off);
-+};
++        break;
-+
+     case MO_64:
-+static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
+         tcg_gen_st_i64(src, cpu_env, off);
          break;
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
      s->base.is_jmp = DISAS_UPDATE_EXIT;
  }
 -/* Generate a label used for skipping this instruction */
 -static void arm_gen_condlabel(DisasContext *s)
 -{
 -    if (!s->condjmp) {
 -        s->condlabel = gen_new_label();
 -        s->condjmp = 1;
 -    }
 -}
 -
  /* Skip this instruction if the ARM condition is false */
  static void arm_skip_unless(DisasContext *s, uint32_t cond)
  {
 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-vfp.c.inc
 +++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
      return true;
  }
 +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
 +{
-+    NPCM7xxMCState *s = NPCM7XX_MC(dev);
++    int btmreg, topreg;
-+
++    TCGv_i64 zero;
-+    memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
++    TCGv_i32 aspen, sfpa;
-+                          NPCM7XX_MC_REGS_SIZE);
++
-+    sysbus_init_mmio(&s->parent, &s->mmio);
++    if (!dc_isar_feature(aa32_m_sec_state, s)) {
 +        /* Before v8.1M, fall through in decode to NOCP check */
 +        return false;
 +    }
 +
 +    /* Explicitly UNDEF because this takes precedence over NOCP */
 +    if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    if (!dc_isar_feature(aa32_vfp_simd, s)) {
 +        /* NOP if we have neither FP nor MVE */
 +        return true;
 +    }
 +
 +    /*
 +     * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
 +     * active floating point context so we must NOP (without doing
 +     * any lazy state preservation or the NOCP check).
 +     */
 +    aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
 +    sfpa = load_cpu_field(v7m.control[M_REG_S]);
 +    tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
 +    tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
 +    tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
 +    tcg_gen_or_i32(sfpa, sfpa, aspen);
 +    arm_gen_condlabel(s);
 +    tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
 +
 +    if (s->fp_excp_el != 0) {
 +        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
 +                           syn_uncategorized(), s->fp_excp_el);
 +        return true;
 +    }
 +
 +    topreg = a->vd + a->imm - 1;
 +    btmreg = a->vd;
 +
 +    /* Convert to Sreg numbers if the insn specified in Dregs */
 +    if (a->size == 3) {
 +        topreg = topreg * 2 + 1;
 +        btmreg *= 2;
 +    }
 +
 +    if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
 +        /* UNPREDICTABLE: we choose to undef */
 +        unallocated_encoding(s);
 +        return true;
 +    }
 +
 +    /* Silently ignore requests to clear D16-D31 if they don't exist */
 +    if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
 +        topreg = 31;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /* Zero the Sregs from btmreg to topreg inclusive. */
 +    zero = tcg_const_i64(0);
 +    if (btmreg & 1) {
 +        write_neon_element64(zero, btmreg >> 1, 1, MO_32);
 +        btmreg++;
 +    }
 +    for (; btmreg + 1 <= topreg; btmreg += 2) {
 +        write_neon_element64(zero, btmreg >> 1, 0, MO_64);
 +    }
 +    if (btmreg == topreg) {
 +        write_neon_element64(zero, btmreg >> 1, 0, MO_32);
 +        btmreg++;
 +    }
 +    assert(btmreg == topreg + 1);
 +    /* TODO: when MVE is implemented, zero VPR here */
 +    return true;
 +}
 +
-+static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
+ static bool trans_NOCP(DisasContext *s, arg_nocp *a)
-+{
+ {
-+    DeviceClass *dc = DEVICE_CLASS(klass);
+     /*
 +
 +    dc->desc = "NPCM7xx Memory Controller stub";
 +    dc->realize = npcm7xx_mc_realize;
 +}
 +
 +static const TypeInfo npcm7xx_mc_types[] = {
 +    {
 +        .name = TYPE_NPCM7XX_MC,
 +        .parent = TYPE_SYS_BUS_DEVICE,
 +        .instance_size = sizeof(NPCM7xxMCState),
 +        .class_init = npcm7xx_mc_class_init,
 +    },
 +};
 +DEFINE_TYPES(npcm7xx_mc_types);
 diff --git a/hw/mem/meson.build b/hw/mem/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/mem/meson.build
 +++ b/hw/mem/meson.build
@@ -XXX,XX +XXX,XX @@
  mem_ss = ss.source_set()
  mem_ss.add(files('memory-device.c'))
  mem_ss.add(when: 'CONFIG_DIMM', if_true: files('pc-dimm.c'))
 +mem_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_mc.c'))
  mem_ss.add(when: 'CONFIG_NVDIMM', if_true: files('nvdimm.c'))
  softmmu_ss.add_all(when: 'CONFIG_MEM_DEVICE', if_true: mem_ss)
 --
 .20.1

-[PULL 20/36] hw/misc: Add NPCM7xx Clock Controller device model
+[PULL 16/36] target/arm: Implement CLRM instruction
-From: Havard Skinnemoen <hskinnemoen@google.com>
+In v8.1M the new CLRM instruction allows zeroing an arbitrary set of
 the general-purpose registers and APSR.  Implement this.
-Enough functionality to boot the Linux kernel has been implemented. This
+The encoding is a subset of the LDMIA T2 encoding, using what would
-includes:
+be Rn=0b1111 (which UNDEFs for LDMIA).
-  - Correct power-on reset values so the various clock rates can be
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-    accurately calculated.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-  - Clock enables stick around when written.
+Message-id: 20201119215617.29887-6-peter.maydell@linaro.org
 ---
  target/arm/t32.decode  |  6 +++++-
  target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
 files changed, 43 insertions(+), 1 deletion(-)
-In addition, a best effort attempt to implement SECCNT and CNTR25M was
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-made even though I don't think the kernel needs them.
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/t32.decode
-Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
++++ b/target/arm/t32.decode
-Reviewed-by: Joel Stanley <joel@jms.id.au>
+@@ -XXX,XX +XXX,XX @@ UXTAB            1111 1010 0101 .... 1111 .... 10.. ....      @rrr_rot
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+ STM_t32          1110 1000 10.0 .... ................         @ldstm i=1 b=0
-Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+ STM_t32          1110 1001 00.0 .... ................         @ldstm i=0 b=1
-Tested-by: Alexander Bulekov <alxndr@bu.edu>
+-LDM_t32          1110 1000 10.1 .... ................         @ldstm i=1 b=0
-Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
++{
-Message-id: 20200911052101.2602693-3-hskinnemoen@google.com
++  # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
++  CLRM           1110 1000 1001 1111 list:16
----
++  LDM_t32        1110 1000 10.1 .... ................         @ldstm i=1 b=0
- include/hw/misc/npcm7xx_clk.h |  48 ++++++
++}
- hw/misc/npcm7xx_clk.c         | 266 ++++++++++++++++++++++++++++++++++
+ LDM_t32          1110 1001 00.1 .... ................         @ldstm i=0 b=1
- hw/misc/meson.build           |   1 +
- hw/misc/trace-events          |   4 +
+ &rfe             !extern rn w pu
-files changed, 319 insertions(+)
+diff --git a/target/arm/translate.c b/target/arm/translate.c
- create mode 100644 include/hw/misc/npcm7xx_clk.h
+index XXXXXXX..XXXXXXX 100644
- create mode 100644 hw/misc/npcm7xx_clk.c
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
-diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
-new file mode 100644
+     return do_ldm(s, a, 1);
-index XXXXXXX..XXXXXXX
+ }
---- /dev/null
-+++ b/include/hw/misc/npcm7xx_clk.h
++static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
-@@ -XXX,XX +XXX,XX @@
++{
-+/*
++    int i;
-+ * Nuvoton NPCM7xx Clock Control Registers.
++    TCGv_i32 zero;
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +#ifndef NPCM7XX_CLK_H
 +#define NPCM7XX_CLK_H
 +
-+#include "exec/memory.h"
++    if (!dc_isar_feature(aa32_m_sec_state, s)) {
-+#include "hw/sysbus.h"
++        return false;
 +
 +/*
 + * The reference clock frequency for the timer modules, and the SECCNT and
 + * CNTR25M registers in this module, is always 25 MHz.
 + */
 +#define NPCM7XX_TIMER_REF_HZ            (25000000)
 +
 +/*
 + * Number of registers in our device state structure. Don't change this without
 + * incrementing the version_id in the vmstate.
 + */
 +#define NPCM7XX_CLK_NR_REGS             (0x70 / sizeof(uint32_t))
 +
 +typedef struct NPCM7xxCLKState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    uint32_t regs[NPCM7XX_CLK_NR_REGS];
 +
 +    /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
 +    int64_t ref_ns;
 +} NPCM7xxCLKState;
 +
 +#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
 +#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
 +
 +#endif /* NPCM7XX_CLK_H */
 diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx Clock Control Registers.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +
 +#include "hw/misc/npcm7xx_clk.h"
 +#include "migration/vmstate.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/timer.h"
 +#include "qemu/units.h"
 +#include "trace.h"
 +
 +#define PLLCON_LOKI     BIT(31)
 +#define PLLCON_LOKS     BIT(30)
 +#define PLLCON_PWDEN    BIT(12)
 +
 +enum NPCM7xxCLKRegisters {
 +    NPCM7XX_CLK_CLKEN1,
 +    NPCM7XX_CLK_CLKSEL,
 +    NPCM7XX_CLK_CLKDIV1,
 +    NPCM7XX_CLK_PLLCON0,
 +    NPCM7XX_CLK_PLLCON1,
 +    NPCM7XX_CLK_SWRSTR,
 +    NPCM7XX_CLK_IPSRST1         = 0x20 / sizeof(uint32_t),
 +    NPCM7XX_CLK_IPSRST2,
 +    NPCM7XX_CLK_CLKEN2,
 +    NPCM7XX_CLK_CLKDIV2,
 +    NPCM7XX_CLK_CLKEN3,
 +    NPCM7XX_CLK_IPSRST3,
 +    NPCM7XX_CLK_WD0RCR,
 +    NPCM7XX_CLK_WD1RCR,
 +    NPCM7XX_CLK_WD2RCR,
 +    NPCM7XX_CLK_SWRSTC1,
 +    NPCM7XX_CLK_SWRSTC2,
 +    NPCM7XX_CLK_SWRSTC3,
 +    NPCM7XX_CLK_SWRSTC4,
 +    NPCM7XX_CLK_PLLCON2,
 +    NPCM7XX_CLK_CLKDIV3,
 +    NPCM7XX_CLK_CORSTC,
 +    NPCM7XX_CLK_PLLCONG,
 +    NPCM7XX_CLK_AHBCKFI,
 +    NPCM7XX_CLK_SECCNT,
 +    NPCM7XX_CLK_CNTR25M,
 +    NPCM7XX_CLK_REGS_END,
 +};
 +
 +/*
 + * These reset values were taken from version 0.91 of the NPCM750R data sheet.
 + *
 + * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
 + * core domain reset, but this reset type is not yet supported by QEMU.
 + */
 +static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
 +    [NPCM7XX_CLK_CLKEN1]        = 0xffffffff,
 +    [NPCM7XX_CLK_CLKSEL]        = 0x004aaaaa,
 +    [NPCM7XX_CLK_CLKDIV1]       = 0x5413f855,
 +    [NPCM7XX_CLK_PLLCON0]       = 0x00222101 | PLLCON_LOKI,
 +    [NPCM7XX_CLK_PLLCON1]       = 0x00202101 | PLLCON_LOKI,
 +    [NPCM7XX_CLK_IPSRST1]       = 0x00001000,
 +    [NPCM7XX_CLK_IPSRST2]       = 0x80000000,
 +    [NPCM7XX_CLK_CLKEN2]        = 0xffffffff,
 +    [NPCM7XX_CLK_CLKDIV2]       = 0xaa4f8f9f,
 +    [NPCM7XX_CLK_CLKEN3]        = 0xffffffff,
 +    [NPCM7XX_CLK_IPSRST3]       = 0x03000000,
 +    [NPCM7XX_CLK_WD0RCR]        = 0xffffffff,
 +    [NPCM7XX_CLK_WD1RCR]        = 0xffffffff,
 +    [NPCM7XX_CLK_WD2RCR]        = 0xffffffff,
 +    [NPCM7XX_CLK_SWRSTC1]       = 0x00000003,
 +    [NPCM7XX_CLK_PLLCON2]       = 0x00c02105 | PLLCON_LOKI,
 +    [NPCM7XX_CLK_CORSTC]        = 0x04000003,
 +    [NPCM7XX_CLK_PLLCONG]       = 0x01228606 | PLLCON_LOKI,
 +    [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
 +};
 +
 +static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint32_t reg = offset / sizeof(uint32_t);
 +    NPCM7xxCLKState *s = opaque;
 +    int64_t now_ns;
 +    uint32_t value = 0;
 +
 +    if (reg >= NPCM7XX_CLK_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
 +                      __func__, offset);
 +        return 0;
 +    }
 +
-+    switch (reg) {
++    if (extract32(a->list, 13, 1)) {
-+    case NPCM7XX_CLK_SWRSTR:
++        return false;
-+        qemu_log_mask(LOG_GUEST_ERROR,
++    }
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is write-only\n",
 +                      __func__, offset);
 +        break;
 +
-+    case NPCM7XX_CLK_SECCNT:
++    if (!a->list) {
-+        now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
++        /* UNPREDICTABLE; we choose to UNDEF */
-+        value = (now_ns - s->ref_ns) / NANOSECONDS_PER_SECOND;
++        return false;
-+        break;
++    }
 +
-+    case NPCM7XX_CLK_CNTR25M:
++    zero = tcg_const_i32(0);
-+        now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
++    for (i = 0; i < 15; i++) {
 +        if (extract32(a->list, i, 1)) {
 +            /* Clear R[i] */
 +            tcg_gen_mov_i32(cpu_R[i], zero);
 +        }
 +    }
 +    if (extract32(a->list, 15, 1)) {
 +        /*
-+         * This register counts 25 MHz cycles, updating every 640 ns. It rolls
++         * Clear APSR (by calling the MSR helper with the same argument
-+         * over to zero every second.
++         * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
 +         *
 +         * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
 +         */
-+        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
++        TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
-+        break;
++        gen_helper_v7m_msr(cpu_env, maskreg, zero);
-+
++        tcg_temp_free_i32(maskreg);
-+    default:
++    }
-+        value = s->regs[reg];
++    tcg_temp_free_i32(zero);
-+        break;
++    return true;
 +    };
 +
 +    trace_npcm7xx_clk_read(offset, value);
 +
 +    return value;
 +}
 +
-+static void npcm7xx_clk_write(void *opaque, hwaddr offset,
+ /*
-+                              uint64_t v, unsigned size)
+  * Branch, branch with link
-+{
+  */
 +    uint32_t reg = offset / sizeof(uint32_t);
 +    NPCM7xxCLKState *s = opaque;
 +    uint32_t value = v;
 +
 +    trace_npcm7xx_clk_write(offset, value);
 +
 +    if (reg >= NPCM7XX_CLK_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
 +                      __func__, offset);
 +        return;
 +    }
 +
 +    switch (reg) {
 +    case NPCM7XX_CLK_SWRSTR:
 +        qemu_log_mask(LOG_UNIMP, "%s: SW reset not implemented: 0x%02x\n",
 +                      __func__, value);
 +        value = 0;
 +        break;
 +
 +    case NPCM7XX_CLK_PLLCON0:
 +    case NPCM7XX_CLK_PLLCON1:
 +    case NPCM7XX_CLK_PLLCON2:
 +    case NPCM7XX_CLK_PLLCONG:
 +        if (value & PLLCON_PWDEN) {
 +            /* Power down -- clear lock and indicate loss of lock */
 +            value &= ~PLLCON_LOKI;
 +            value |= PLLCON_LOKS;
 +        } else {
 +            /* Normal mode -- assume always locked */
 +            value |= PLLCON_LOKI;
 +            /* Keep LOKS unchanged unless cleared by writing 1 */
 +            if (value & PLLCON_LOKS) {
 +                value &= ~PLLCON_LOKS;
 +            } else {
 +                value |= (value & PLLCON_LOKS);
 +            }
 +        }
 +        break;
 +
 +    case NPCM7XX_CLK_CNTR25M:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        return;
 +    }
 +
 +    s->regs[reg] = value;
 +}
 +
 +static const struct MemoryRegionOps npcm7xx_clk_ops = {
 +    .read       = npcm7xx_clk_read,
 +    .write      = npcm7xx_clk_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
 +
 +    QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
 +
 +    switch (type) {
 +    case RESET_TYPE_COLD:
 +        memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
 +        s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 +        return;
 +    }
 +
 +    /*
 +     * A small number of registers need to be reset on a core domain reset,
 +     * but no such reset type exists yet.
 +     */
 +    qemu_log_mask(LOG_UNIMP, "%s: reset type %d not implemented.",
 +                  __func__, type);
 +}
 +
 +static void npcm7xx_clk_init(Object *obj)
 +{
 +    NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
 +                          TYPE_NPCM7XX_CLK, 4 * KiB);
 +    sysbus_init_mmio(&s->parent, &s->iomem);
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_clk = {
 +    .name = "npcm7xx-clk",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
 +        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM7XX_CLK_NR_REGS);
 +
 +    dc->desc = "NPCM7xx Clock Control Registers";
 +    dc->vmsd = &vmstate_npcm7xx_clk;
 +    rc->phases.enter = npcm7xx_clk_enter_reset;
 +}
 +
 +static const TypeInfo npcm7xx_clk_info = {
 +    .name               = TYPE_NPCM7XX_CLK,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxCLKState),
 +    .instance_init      = npcm7xx_clk_init,
 +    .class_init         = npcm7xx_clk_class_init,
 +};
 +
 +static void npcm7xx_clk_register_type(void)
 +{
 +    type_register_static(&npcm7xx_clk_info);
 +}
 +type_init(npcm7xx_clk_register_type);
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
  softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-hpdmc.c', 'milkymist-pfpu.c'))
  softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
  softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
 +  'npcm7xx_clk.c',
    'npcm7xx_gcr.c',
  ))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
  mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
  mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
 +# npcm7xx_clk.c
 +npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +
  # npcm7xx_gcr.c
  npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
  npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 --
 .20.1

-[PULL 16/36] Deprecate lm32 port
+[PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions
-Deprecate our lm32 target support. Michael Walle (former lm32 maintainer)
+For M-profile before v8.1M, the only valid register for VMSR/VMRS is
-suggested that we do this in 2019:
+the FPSCR.  We have a comment that states this, but the actual logic
- https://www.mail-archive.com/qemu-devel@nongnu.org/msg605024.html
+to forbid accesses for any other register value is missing, so we
-because the only public user of the architecture is the many-years-dead
+would end up with A-profile style behaviour.  Add the missing check.
 milkymist project. (The Linux port to lm32 was never merged upstream.)
 In commit 4b4d96c776f552e (March 2020) we marked it as 'orphan' in
 the MAINTAINERS file, but didn't officially deprecate it. Mark it
 deprecated now, with the intention of removing it from QEMU in
 mid-2021 before the 6.1 release.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20201119215617.29887-7-peter.maydell@linaro.org
 Reviewed-by: Thomas Huth <thuth@redhat.com>
 Acked-by: Michael Walle <michael@walle.cc>
 Message-id: 20200827113259.25064-1-peter.maydell@linaro.org
 ---
- docs/system/deprecated.rst | 8 ++++++++
+ target/arm/translate-vfp.c.inc | 5 ++++-
-file changed, 8 insertions(+)
+file changed, 4 insertions(+), 1 deletion(-)
-diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
+diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/deprecated.rst
+--- a/target/arm/translate-vfp.c.inc
-+++ b/docs/system/deprecated.rst
++++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
+@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
- linux-user mode CPUs
+          * Accesses to R15 are UNPREDICTABLE; we choose to undef.
- --------------------
+          * (FPSCR -> r15 is a special case which writes to the PSR flags.)
+          */
-+``lm32`` CPUs (since 5.2.0)
+-        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
-+'''''''''''''''''''''''''''
++        if (a->reg != ARM_VFP_FPSCR) {
-+
++            return false;
-+The ``lm32`` guest CPU support is deprecated and will be removed in
++        }
-+a future version of QEMU. The only public user of this architecture
++        if (a->rt == 15 && !a->l) {
-+was the milkymist project, which has been dead for years; there was
+             return false;
-+never an upstream Linux port.
+         }
-+
+     }
  ``unicore32`` CPUs (since 5.2.0)
  ''''''''''''''''''''''''''''''''
 --
 .20.1

-[PULL 09/36] target/arm: Convert VCMLA, VCADD size field to MO_* in decode
+[PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling
-The VCMLA and VCADD insns have a size field which is 0 for fp16
+Currently M-profile borrows the A-profile code for VMSR and VMRS
-and 1 for fp32 (note that this is the reverse of the Neon 3-same
+(access to the FP system registers), because all it needs to support
-encoding!). Convert it to MO_* values in decode for consistency.
+is the FPSCR.  In v8.1M things become significantly more complicated
 in two ways:
  * there are several new FP system registers; some have side effects
    on read, and one (FPCXT_NS) needs to avoid the usual
    vfp_access_check() and the "only if FPU implemented" check
  * all sysregs are now accessible both by VMRS/VMSR (which
    reads/writes a general purpose register) and also by VLDR/VSTR
    (which reads/writes them directly to memory)
 Refactor the structure of how we handle VMSR/VMRS to cope with this:
  * keep the M-profile code entirely separate from the A-profile code
  * abstract out the "read or write the general purpose register" part
    of the code into a loadfn or storefn function pointer, so we can
    reuse it for VLDR/VSTR.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200903133209.5141-4-peter.maydell@linaro.org
+Message-id: 20201119215617.29887-8-peter.maydell@linaro.org
 ---
- target/arm/neon-shared.decode   | 18 ++++++++++++------
+ target/arm/cpu.h               |   3 +
- target/arm/translate-neon.c.inc | 22 ++++++++++++----------
+ target/arm/translate-vfp.c.inc | 182 ++++++++++++++++++++++++++++++---
-files changed, 24 insertions(+), 16 deletions(-)
+files changed, 171 insertions(+), 14 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
+--- a/target/arm/cpu.h
-+++ b/target/arm/neon-shared.decode
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode {
- %vd_dp  22:1 12:4
+ #define ARM_VFP_FPINST  9
- %vd_sp  12:4 22:1
+ #define ARM_VFP_FPINST2 10
--VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
++/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
--               vm=%vm_dp vn=%vn_dp vd=%vd_dp
++#define QEMU_VFP_FPSCR_NZCV 0xffff
-+# For VCMLA/VCADD insns, convert the single-bit size field
++
-+# which is 0 for fp16 and 1 for fp32 into a MO_* constant.
+ /* iwMMXt coprocessor control registers.  */
-+# (Note that this is the reverse of the sense of the 1-bit size
+ #define ARM_IWMMXT_wCID  0
-+# field in the 3same_fp Neon insns.)
+ #define ARM_IWMMXT_wCon  1
-+%vcadd_size    20:1 !function=plus1
+diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 -VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
 -               vm=%vm_dp vn=%vn_dp vd=%vd_dp
 +VCMLA          1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \
 +               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
 +
 +VCADD          1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \
 +               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
  # VUDOT and VSDOT
  VDOT           1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
@@ -XXX,XX +XXX,XX @@ VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
                 vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
  VCMLA_scalar   1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
 -               vn=%vn_dp vd=%vd_dp size=0
 +               vn=%vn_dp vd=%vd_dp size=1
  VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
 -               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
 +               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=2 index=0
  VDOT_scalar    1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
                 vm=%vm_dp vn=%vn_dp vd=%vd_dp
 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.c.inc
+--- a/target/arm/translate-vfp.c.inc
-+++ b/target/arm/translate-neon.c.inc
++++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
+@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
-     gen_helper_gvec_3_ptr *fn_gvec_ptr;
+     return true;
+ }
-     if (!dc_isar_feature(aa32_vcma, s)
--        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
++/*
-+        || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) {
++ * M-profile provides two different sets of instructions that can
-         return false;
++ * access floating point system registers: VMSR/VMRS (which move
 + * to/from a general purpose register) and VLDR/VSTR sysreg (which
 + * move directly to/from memory). In some cases there are also side
 + * effects which must happen after any write to memory (which could
 + * cause an exception). So we implement the common logic for the
 + * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(),
 + * which take pointers to callback functions which will perform the
 + * actual "read/write general purpose register" and "read/write
 + * memory" operations.
 + */
 +
 +/*
 + * Emit code to store the sysreg to its final destination; frees the
 + * TCG temp 'value' it is passed.
 + */
 +typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value);
 +/*
 + * Emit code to load the value to be copied to the sysreg; returns
 + * a new TCG temporary
 + */
 +typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque);
 +
 +/* Common decode/access checks for fp sysreg read/write */
 +typedef enum FPSysRegCheckResult {
 +    FPSysRegCheckFailed, /* caller should return false */
 +    FPSysRegCheckDone, /* caller should return true */
 +    FPSysRegCheckContinue, /* caller should continue generating code */
 +} FPSysRegCheckResult;
 +
 +static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
 +{
 +    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
 +        return FPSysRegCheckFailed;
 +    }
 +
 +    switch (regno) {
 +    case ARM_VFP_FPSCR:
 +    case QEMU_VFP_FPSCR_NZCV:
 +        break;
 +    default:
 +        return FPSysRegCheckFailed;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return FPSysRegCheckDone;
 +    }
 +
 +    return FPSysRegCheckContinue;
 +}
 +
 +static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
 +
 +                                  fp_sysreg_loadfn *loadfn,
 +                                 void *opaque)
 +{
 +    /* Do a write to an M-profile floating point system register */
 +    TCGv_i32 tmp;
 +
 +    switch (fp_sysreg_checks(s, regno)) {
 +    case FPSysRegCheckFailed:
 +        return false;
 +    case FPSysRegCheckDone:
 +        return true;
 +    case FPSysRegCheckContinue:
 +        break;
 +    }
 +
 +    switch (regno) {
 +    case ARM_VFP_FPSCR:
 +        tmp = loadfn(s, opaque);
 +        gen_helper_vfp_set_fpscr(cpu_env, tmp);
 +        tcg_temp_free_i32(tmp);
 +        gen_lookup_tb(s);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +    return true;
 +}
 +
 +static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
 +                                fp_sysreg_storefn *storefn,
 +                                void *opaque)
 +{
 +    /* Do a read from an M-profile floating point system register */
 +    TCGv_i32 tmp;
 +
 +    switch (fp_sysreg_checks(s, regno)) {
 +    case FPSysRegCheckFailed:
 +        return false;
 +    case FPSysRegCheckDone:
 +        return true;
 +    case FPSysRegCheckContinue:
 +        break;
 +    }
 +
 +    switch (regno) {
 +    case ARM_VFP_FPSCR:
 +        tmp = tcg_temp_new_i32();
 +        gen_helper_vfp_get_fpscr(tmp, cpu_env);
 +        storefn(s, opaque, tmp);
 +        break;
 +    case QEMU_VFP_FPSCR_NZCV:
 +        /*
 +         * Read just NZCV; this is a special case to avoid the
 +         * helper call for the "VMRS to CPSR.NZCV" insn.
 +         */
 +        tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
 +        tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
 +        storefn(s, opaque, tmp);
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +    return true;
 +}
 +
 +static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value)
 +{
 +    arg_VMSR_VMRS *a = opaque;
 +
 +    if (a->rt == 15) {
 +        /* Set the 4 flag bits in the CPSR */
 +        gen_set_nzcv(value);
 +        tcg_temp_free_i32(value);
 +    } else {
 +        store_reg(s, a->rt, value);
 +    }
 +}
 +
 +static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque)
 +{
 +    arg_VMSR_VMRS *a = opaque;
 +
 +    return load_reg(s, a->rt);
 +}
 +
 +static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
 +{
 +    /*
 +     * Accesses to R15 are UNPREDICTABLE; we choose to undef.
 +     * FPSCR -> r15 is a special case which writes to the PSR flags;
 +     * set a->reg to a special value to tell gen_M_fp_sysreg_read()
 +     * we only care about the top 4 bits of FPSCR there.
 +     */
 +    if (a->rt == 15) {
 +        if (a->l && a->reg == ARM_VFP_FPSCR) {
 +            a->reg = QEMU_VFP_FPSCR_NZCV;
 +        } else {
 +            return false;
 +        }
 +    }
 +
 +    if (a->l) {
 +        /* VMRS, move FP system register to gp register */
 +        return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a);
 +    } else {
 +        /* VMSR, move gp register to FP system register */
 +        return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a);
 +    }
 +}
 +
  static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
  {
      TCGv_i32 tmp;
      bool ignore_vfp_enabled = false;
 -    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
 -        return false;
 +    if (arm_dc_feature(s, ARM_FEATURE_M)) {
 +        return gen_M_VMSR_VMRS(s, a);
      }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
+-    if (arm_dc_feature(s, ARM_FEATURE_M)) {
 -        /*
 -         * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
 -         * Accesses to R15 are UNPREDICTABLE; we choose to undef.
 -         * (FPSCR -> r15 is a special case which writes to the PSR flags.)
 -         */
 -        if (a->reg != ARM_VFP_FPSCR) {
 -            return false;
 -        }
 -        if (a->rt == 15 && !a->l) {
 -            return false;
 -        }
 +    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
 +        return false;
      }
-     opr_sz = (1 + a->q) * 8;
+     switch (a->reg) {
 -    fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD);
 -    fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
 +    fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
 +    fn_gvec_ptr = (a->size == MO_16) ?
 +        gen_helper_gvec_fcmlah : gen_helper_gvec_fcmlas;
      tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
                         vfp_reg_offset(1, a->vn),
                         vfp_reg_offset(1, a->vm),
@@ -XXX,XX +XXX,XX @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
      gen_helper_gvec_3_ptr *fn_gvec_ptr;
      if (!dc_isar_feature(aa32_vcma, s)
 -        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
 +        || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
      }
      opr_sz = (1 + a->q) * 8;
 -    fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD);
 -    fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
 +    fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
 +    fn_gvec_ptr = (a->size == MO_16) ?
 +        gen_helper_gvec_fcaddh : gen_helper_gvec_fcadds;
      tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
                         vfp_reg_offset(1, a->vn),
                         vfp_reg_offset(1, a->vm),
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
      if (!dc_isar_feature(aa32_vcma, s)) {
          return false;
      }
 -    if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
 +    if (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s)) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
          return true;
      }
 -    fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
 -                   : gen_helper_gvec_fcmlah_idx);
 +    fn_gvec_ptr = (a->size == MO_16) ?
 +        gen_helper_gvec_fcmlah_idx : gen_helper_gvec_fcmlas_idx;
      opr_sz = (1 + a->q) * 8;
 -    fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD);
 +    fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
      tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
                         vfp_reg_offset(1, a->vn),
                         vfp_reg_offset(1, a->vm),
 --
 .20.1

-[PULL 19/36] hw/misc: Add NPCM7xx System Global Control Registers device model
+[PULL 19/36] target/arm: Move general-use constant expanders up in translate.c
-From: Havard Skinnemoen <hskinnemoen@google.com>
+The constant-expander functions like negate, plus_2, etc, are
 generally useful; move them up in translate.c so we can use them in
 the VFP/Neon decoders as well as in the A32/T32/T16 decoders.
-Implement a device model for the System Global Control Registers in the
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-NPCM730 and NPCM750 BMC SoCs.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20201119215617.29887-9-peter.maydell@linaro.org
 ---
  target/arm/translate.c | 46 +++++++++++++++++++++++-------------------
 file changed, 25 insertions(+), 21 deletions(-)
-This is primarily used to enable SMP boot (the boot ROM spins reading
+diff --git a/target/arm/translate.c b/target/arm/translate.c
-the SCRPAD register) and DDR memory initialization; other registers are
+index XXXXXXX..XXXXXXX 100644
-best effort for now.
+--- a/target/arm/translate.c
++++ b/target/arm/translate.c
-The reset values of the MDLR and PWRON registers are determined by the
+@@ -XXX,XX +XXX,XX @@ static void arm_gen_condlabel(DisasContext *s)
-SoC variant (730 vs 750) and board straps respectively.
+     }
+ }
-Reviewed-by: Joel Stanley <joel@jms.id.au>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Alexander Bulekov <alxndr@bu.edu>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-2-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/misc/npcm7xx_gcr.h |  43 ++++++
  hw/misc/npcm7xx_gcr.c         | 269 ++++++++++++++++++++++++++++++++++
  MAINTAINERS                   |   8 +
  hw/arm/Kconfig                |   3 +
  hw/misc/meson.build           |   3 +
  hw/misc/trace-events          |   4 +
 files changed, 330 insertions(+)
  create mode 100644 include/hw/misc/npcm7xx_gcr.h
  create mode 100644 hw/misc/npcm7xx_gcr.c
 diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/npcm7xx_gcr.h
@@ -XXX,XX +XXX,XX @@
 +/*
-+ * Nuvoton NPCM7xx System Global Control Registers.
++ * Constant expanders for the decoders.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +#ifndef NPCM7XX_GCR_H
 +#define NPCM7XX_GCR_H
 +
 +#include "exec/memory.h"
 +#include "hw/sysbus.h"
 +
 +/*
 + * Number of registers in our device state structure. Don't change this without
 + * incrementing the version_id in the vmstate.
 + */
 +#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
 +
 +typedef struct NPCM7xxGCRState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion iomem;
 +
 +    uint32_t regs[NPCM7XX_GCR_NR_REGS];
 +
 +    uint32_t reset_pwron;
 +    uint32_t reset_mdlr;
 +    uint32_t reset_intcr3;
 +} NPCM7xxGCRState;
 +
 +#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
 +#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
 +
 +#endif /* NPCM7XX_GCR_H */
 diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx System Global Control Registers.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
-+#include "qemu/osdep.h"
++static int negate(DisasContext *s, int x)
 +
 +#include "hw/misc/npcm7xx_gcr.h"
 +#include "hw/qdev-properties.h"
 +#include "migration/vmstate.h"
 +#include "qapi/error.h"
 +#include "qemu/cutils.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/units.h"
 +
 +#include "trace.h"
 +
 +#define NPCM7XX_GCR_MIN_DRAM_SIZE   (128 * MiB)
 +#define NPCM7XX_GCR_MAX_DRAM_SIZE   (2 * GiB)
 +
 +enum NPCM7xxGCRRegisters {
 +    NPCM7XX_GCR_PDID,
 +    NPCM7XX_GCR_PWRON,
 +    NPCM7XX_GCR_MFSEL1          = 0x0c / sizeof(uint32_t),
 +    NPCM7XX_GCR_MFSEL2,
 +    NPCM7XX_GCR_MISCPE,
 +    NPCM7XX_GCR_SPSWC           = 0x038 / sizeof(uint32_t),
 +    NPCM7XX_GCR_INTCR,
 +    NPCM7XX_GCR_INTSR,
 +    NPCM7XX_GCR_HIFCR           = 0x050 / sizeof(uint32_t),
 +    NPCM7XX_GCR_INTCR2          = 0x060 / sizeof(uint32_t),
 +    NPCM7XX_GCR_MFSEL3,
 +    NPCM7XX_GCR_SRCNT,
 +    NPCM7XX_GCR_RESSR,
 +    NPCM7XX_GCR_RLOCKR1,
 +    NPCM7XX_GCR_FLOCKR1,
 +    NPCM7XX_GCR_DSCNT,
 +    NPCM7XX_GCR_MDLR,
 +    NPCM7XX_GCR_SCRPAD3,
 +    NPCM7XX_GCR_SCRPAD2,
 +    NPCM7XX_GCR_DAVCLVLR        = 0x098 / sizeof(uint32_t),
 +    NPCM7XX_GCR_INTCR3,
 +    NPCM7XX_GCR_VSINTR          = 0x0ac / sizeof(uint32_t),
 +    NPCM7XX_GCR_MFSEL4,
 +    NPCM7XX_GCR_CPBPNTR         = 0x0c4 / sizeof(uint32_t),
 +    NPCM7XX_GCR_CPCTL           = 0x0d0 / sizeof(uint32_t),
 +    NPCM7XX_GCR_CP2BST,
 +    NPCM7XX_GCR_B2CPNT,
 +    NPCM7XX_GCR_CPPCTL,
 +    NPCM7XX_GCR_I2CSEGSEL,
 +    NPCM7XX_GCR_I2CSEGCTL,
 +    NPCM7XX_GCR_VSRCR,
 +    NPCM7XX_GCR_MLOCKR,
 +    NPCM7XX_GCR_SCRPAD          = 0x013c / sizeof(uint32_t),
 +    NPCM7XX_GCR_USB1PHYCTL,
 +    NPCM7XX_GCR_USB2PHYCTL,
 +    NPCM7XX_GCR_REGS_END,
 +};
 +
 +static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
 +    [NPCM7XX_GCR_PDID]          = 0x04a92750,   /* Poleg A1 */
 +    [NPCM7XX_GCR_MISCPE]        = 0x0000ffff,
 +    [NPCM7XX_GCR_SPSWC]         = 0x00000003,
 +    [NPCM7XX_GCR_INTCR]         = 0x0000035e,
 +    [NPCM7XX_GCR_HIFCR]         = 0x0000004e,
 +    [NPCM7XX_GCR_INTCR2]        = (1U << 19),   /* DDR initialized */
 +    [NPCM7XX_GCR_RESSR]         = 0x80000000,
 +    [NPCM7XX_GCR_DSCNT]         = 0x000000c0,
 +    [NPCM7XX_GCR_DAVCLVLR]      = 0x5a00f3cf,
 +    [NPCM7XX_GCR_SCRPAD]        = 0x00000008,
 +    [NPCM7XX_GCR_USB1PHYCTL]    = 0x034730e4,
 +    [NPCM7XX_GCR_USB2PHYCTL]    = 0x034730e4,
 +};
 +
 +static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size)
 +{
-+    uint32_t reg = offset / sizeof(uint32_t);
++    return -x;
 +    NPCM7xxGCRState *s = opaque;
 +
 +    if (reg >= NPCM7XX_GCR_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
 +                      __func__, offset);
 +        return 0;
 +    }
 +
 +    trace_npcm7xx_gcr_read(offset, s->regs[reg]);
 +
 +    return s->regs[reg];
 +}
 +
-+static void npcm7xx_gcr_write(void *opaque, hwaddr offset,
++static int plus_2(DisasContext *s, int x)
 +                              uint64_t v, unsigned size)
 +{
-+    uint32_t reg = offset / sizeof(uint32_t);
++    return x + 2;
 +    NPCM7xxGCRState *s = opaque;
 +    uint32_t value = v;
 +
 +    trace_npcm7xx_gcr_write(offset, value);
 +
 +    if (reg >= NPCM7XX_GCR_NR_REGS) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
 +                      __func__, offset);
 +        return;
 +    }
 +
 +    switch (reg) {
 +    case NPCM7XX_GCR_PDID:
 +    case NPCM7XX_GCR_PWRON:
 +    case NPCM7XX_GCR_INTSR:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
 +                      __func__, offset);
 +        return;
 +
 +    case NPCM7XX_GCR_RESSR:
 +    case NPCM7XX_GCR_CP2BST:
 +        /* Write 1 to clear */
 +        value = s->regs[reg] & ~value;
 +        break;
 +
 +    case NPCM7XX_GCR_RLOCKR1:
 +    case NPCM7XX_GCR_MDLR:
 +        /* Write 1 to set */
 +        value |= s->regs[reg];
 +        break;
 +    };
 +
 +    s->regs[reg] = value;
 +}
 +
-+static const struct MemoryRegionOps npcm7xx_gcr_ops = {
++static int times_2(DisasContext *s, int x)
 +    .read       = npcm7xx_gcr_read,
 +    .write      = npcm7xx_gcr_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
 +{
-+    NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
++    return x * 2;
 +
 +    QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
 +
 +    switch (type) {
 +    case RESET_TYPE_COLD:
 +        memcpy(s->regs, cold_reset_values, sizeof(s->regs));
 +        s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron;
 +        s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr;
 +        s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
 +        break;
 +    }
 +}
 +
-+static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
++static int times_4(DisasContext *s, int x)
 +{
-+    ERRP_GUARD();
++    return x * 4;
 +    NPCM7xxGCRState *s = NPCM7XX_GCR(dev);
 +    uint64_t dram_size;
 +    Object *obj;
 +
 +    obj = object_property_get_link(OBJECT(dev), "dram-mr", errp);
 +    if (!obj) {
 +        error_prepend(errp, "%s: required dram-mr link not found: ", __func__);
 +        return;
 +    }
 +    dram_size = memory_region_size(MEMORY_REGION(obj));
 +    if (!is_power_of_2(dram_size) ||
 +        dram_size < NPCM7XX_GCR_MIN_DRAM_SIZE ||
 +        dram_size > NPCM7XX_GCR_MAX_DRAM_SIZE) {
 +        g_autofree char *sz = size_to_str(dram_size);
 +        g_autofree char *min_sz = size_to_str(NPCM7XX_GCR_MIN_DRAM_SIZE);
 +        g_autofree char *max_sz = size_to_str(NPCM7XX_GCR_MAX_DRAM_SIZE);
 +        error_setg(errp, "%s: unsupported DRAM size %s", __func__, sz);
 +        error_append_hint(errp,
 +                          "DRAM size must be a power of two between %s and %s,"
 +                          " inclusive.\n", min_sz, max_sz);
 +        return;
 +    }
 +
 +    /* Power-on reset value */
 +    s->reset_intcr3 = 0x00001002;
 +
 +    /*
 +     * The GMMAP (Graphics Memory Map) field is used by u-boot to detect the
 +     * DRAM size, and is normally initialized by the boot block as part of DRAM
 +     * training. However, since we don't have a complete emulation of the
 +     * memory controller and try to make it look like it has already been
 +     * initialized, the boot block will skip this initialization, and we need
 +     * to make sure this field is set correctly up front.
 +     *
 +     * WARNING: some versions of u-boot only looks at bits 8 and 9, so 2 GiB of
 +     * DRAM will be interpreted as 128 MiB.
 +     *
 +     * https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408dbaad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244
 +     */
 +    s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8;
 +}
 +
-+static void npcm7xx_gcr_init(Object *obj)
+ /* Flags for the disas_set_da_iss info argument:
-+{
+  * lower bits hold the Rt register number, higher bits are flags.
-+    NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
+  */
-+
+@@ -XXX,XX +XXX,XX @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
-+    memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
-+                          TYPE_NPCM7XX_GCR, 4 * KiB);
-+    sysbus_init_mmio(&s->parent, &s->iomem);
+ /*
-+}
+- * Constant expanders for the decoders.
-+
++ * Constant expanders used by T16/T32 decode
-+static const VMStateDescription vmstate_npcm7xx_gcr = {
+  */
-+    .name = "npcm7xx-gcr",
-+    .version_id = 0,
+-static int negate(DisasContext *s, int x)
-+    .minimum_version_id = 0,
+-{
-+    .fields = (VMStateField[]) {
+-    return -x;
-+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxGCRState, NPCM7XX_GCR_NR_REGS),
+-}
-+        VMSTATE_END_OF_LIST(),
+-
-+    },
+-static int plus_2(DisasContext *s, int x)
-+};
+-{
-+
+-    return x + 2;
-+static Property npcm7xx_gcr_properties[] = {
+-}
-+    DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState, reset_mdlr, 0),
+-
-+    DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState, reset_pwron, 0),
+-static int times_2(DisasContext *s, int x)
-+    DEFINE_PROP_END_OF_LIST(),
+-{
-+};
+-    return x * 2;
-+
+-}
-+static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
+-
-+{
+-static int times_4(DisasContext *s, int x)
-+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+-{
-+    DeviceClass *dc = DEVICE_CLASS(klass);
+-    return x * 4;
-+
+-}
-+    QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS);
+-
-+
+ /* Return only the rotation part of T32ExpandImm.  */
-+    dc->desc = "NPCM7xx System Global Control Registers";
+ static int t32_expandimm_rot(DisasContext *s, int x)
-+    dc->realize = npcm7xx_gcr_realize;
+ {
 +    dc->vmsd = &vmstate_npcm7xx_gcr;
 +    rc->phases.enter = npcm7xx_gcr_enter_reset;
 +
 +    device_class_set_props(dc, npcm7xx_gcr_properties);
 +}
 +
 +static const TypeInfo npcm7xx_gcr_info = {
 +    .name               = TYPE_NPCM7XX_GCR,
 +    .parent             = TYPE_SYS_BUS_DEVICE,
 +    .instance_size      = sizeof(NPCM7xxGCRState),
 +    .instance_init      = npcm7xx_gcr_init,
 +    .class_init         = npcm7xx_gcr_class_init,
 +};
 +
 +static void npcm7xx_gcr_register_type(void)
 +{
 +    type_register_static(&npcm7xx_gcr_info);
 +}
 +type_init(npcm7xx_gcr_register_type);
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
  F: hw/arm/musicpal.c
  F: docs/system/arm/musicpal.rst
 +Nuvoton NPCM7xx
 +M: Havard Skinnemoen <hskinnemoen@google.com>
 +M: Tyrone Ting <kfting@nuvoton.com>
 +L: qemu-arm@nongnu.org
 +S: Supported
 +F: hw/*/npcm7xx*
 +F: include/hw/*/npcm7xx*
 +
  nSeries
  M: Andrzej Zaborowski <balrogg@gmail.com>
  M: Peter Maydell <peter.maydell@linaro.org>
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
      select VIRTIO_MMIO
      select UNIMP
 +config NPCM7XX
 +    bool
 +
  config FSL_IMX25
      bool
      select IMX
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
  ))
  softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-hpdmc.c', 'milkymist-pfpu.c'))
  softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
 +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
 +  'npcm7xx_gcr.c',
 +))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
    'omap_clk.c',
    'omap_gpmc.c',
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
  mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
  mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
 +# npcm7xx_gcr.c
 +npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +
  # stm32f4xx_syscfg.c
  stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
  stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
 --
 .20.1

-[PULL 22/36] hw/arm: Add NPCM730 and NPCM750 SoC models
+[PULL 20/36] target/arm: Implement VLDR/VSTR system register
-From: Havard Skinnemoen <hskinnemoen@google.com>
+Implement the new-in-v8.1M VLDR/VSTR variants which directly
 read or write FP system registers to memory.
-The Nuvoton NPCM7xx SoC family are used to implement Baseboard
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Management Controllers in servers. While the family includes four SoCs,
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-this patch implements limited support for two of them: NPCM730 (targeted
+Message-id: 20201119215617.29887-10-peter.maydell@linaro.org
-for Data Center applications) and NPCM750 (targeted for Enterprise
+---
-applications).
+ target/arm/vfp.decode          | 14 ++++++
  target/arm/translate-vfp.c.inc | 91 ++++++++++++++++++++++++++++++++++
 files changed, 105 insertions(+)
-This patch includes little more than the bare minimum needed to boot a
+diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
-Linux kernel built with NPCM7xx support in direct-kernel mode:
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/vfp.decode
-  - Two Cortex-A9 CPU cores with built-in periperhals.
++++ b/target/arm/vfp.decode
-  - Global Configuration Registers.
+@@ -XXX,XX +XXX,XX @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8      vd=%vd_sp
-  - Clock Management.
+ VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8      vd=%vd_sp
-  - 3 Timer Modules with 5 timers each.
+ VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8      vd=%vd_dp
-  - 4 serial ports.
++# M-profile VLDR/VSTR to sysreg
-The chips themselves have a lot more features, some of which will be
++%vldr_sysreg 22:1 13:3
-added to the model at a later stage.
++%imm7_0x4 0:7 !function=times_4
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Reviewed-by: Joel Stanley <joel@jms.id.au>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Alexander Bulekov <alxndr@bu.edu>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-5-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/npcm7xx.h |  85 ++++++++
  hw/arm/npcm7xx.c         | 407 +++++++++++++++++++++++++++++++++++++++
  hw/arm/Kconfig           |   5 +
  hw/arm/meson.build       |   1 +
 files changed, 498 insertions(+)
  create mode 100644 include/hw/arm/npcm7xx.h
  create mode 100644 hw/arm/npcm7xx.c
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx SoC family.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +#ifndef NPCM7XX_H
 +#define NPCM7XX_H
 +
-+#include "hw/boards.h"
++&vldr_sysreg rn reg imm a w p
-+#include "hw/cpu/a9mpcore.h"
++@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \
-+#include "hw/misc/npcm7xx_clk.h"
++             reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg
 +#include "hw/misc/npcm7xx_gcr.h"
 +#include "hw/timer/npcm7xx_timer.h"
 +#include "target/arm/cpu.h"
 +
-+#define NPCM7XX_MAX_NUM_CPUS    (2)
++# P=0 W=0 is SEE "Related encodings", so split into two patterns
 +VLDR_sysreg  ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1
 +VLDR_sysreg  ---- 110 0 . . 1   1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
 +VSTR_sysreg  ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1
 +VSTR_sysreg  ---- 110 0 . . 1   0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
 +
-+/* The first half of the address space is reserved for DDR4 DRAM. */
+ # We split the load/store multiple up into two patterns to avoid
-+#define NPCM7XX_DRAM_BA         (0x00000000)
+ # overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
-+#define NPCM7XX_DRAM_SZ         (2 * GiB)
+ # grouping:
 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-vfp.c.inc
 +++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
      return true;
  }
 +static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value)
 +{
 +    arg_vldr_sysreg *a = opaque;
 +    uint32_t offset = a->imm;
 +    TCGv_i32 addr;
 +
-+/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
++    if (!a->a) {
-+#define NPCM7XX_LOADER_START            (0x00000000)  /* Start of SDRAM */
++        offset = - offset;
 +#define NPCM7XX_SMP_LOADER_START        (0xffff0000)  /* Boot ROM */
 +#define NPCM7XX_SMP_BOOTREG_ADDR        (0xf080013c)  /* GCR.SCRPAD */
 +#define NPCM7XX_GIC_CPU_IF_ADDR         (0xf03fe100)  /* GIC within A9 */
 +
 +typedef struct NPCM7xxState {
 +    DeviceState         parent;
 +
 +    ARMCPU              cpu[NPCM7XX_MAX_NUM_CPUS];
 +    A9MPPrivState       a9mpcore;
 +
 +    MemoryRegion        sram;
 +    MemoryRegion        irom;
 +    MemoryRegion        ram3;
 +    MemoryRegion        *dram;
 +
 +    NPCM7xxGCRState     gcr;
 +    NPCM7xxCLKState     clk;
 +    NPCM7xxTimerCtrlState tim[3];
 +} NPCM7xxState;
 +
 +#define TYPE_NPCM7XX    "npcm7xx"
 +#define NPCM7XX(obj)    OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
 +
 +#define TYPE_NPCM730    "npcm730"
 +#define TYPE_NPCM750    "npcm750"
 +
 +typedef struct NPCM7xxClass {
 +    DeviceClass         parent;
 +
 +    /* Bitmask of modules that are permanently disabled on this chip. */
 +    uint32_t            disabled_modules;
 +    /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
 +    uint32_t            num_cpus;
 +} NPCM7xxClass;
 +
 +#define NPCM7XX_CLASS(klass)                                            \
 +    OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
 +#define NPCM7XX_GET_CLASS(obj)                                          \
 +    OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
 +
 +/**
 + * npcm7xx_load_kernel - Loads memory with everything needed to boot
 + * @machine - The machine containing the SoC to be booted.
 + * @soc - The SoC containing the CPU to be booted.
 + *
 + * This will set up the ARM boot info structure for the specific NPCM7xx
 + * derivative and call arm_load_kernel() to set up loading of the kernel, etc.
 + * into memory, if requested by the user.
 + */
 +void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc);
 +
 +#endif /* NPCM7XX_H */
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx SoC family.
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +
 +#include "exec/address-spaces.h"
 +#include "hw/arm/boot.h"
 +#include "hw/arm/npcm7xx.h"
 +#include "hw/char/serial.h"
 +#include "hw/loader.h"
 +#include "hw/misc/unimp.h"
 +#include "hw/qdev-properties.h"
 +#include "qapi/error.h"
 +#include "qemu/units.h"
 +#include "sysemu/sysemu.h"
 +
 +/*
 + * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
 + * that aren't handled by any device.
 + */
 +#define NPCM7XX_MMIO_BA         (0x80000000)
 +#define NPCM7XX_MMIO_SZ         (0x7ffd0000)
 +
 +/* Core system modules. */
 +#define NPCM7XX_L2C_BA          (0xf03fc000)
 +#define NPCM7XX_CPUP_BA         (0xf03fe000)
 +#define NPCM7XX_GCR_BA          (0xf0800000)
 +#define NPCM7XX_CLK_BA          (0xf0801000)
 +
 +/* Internal AHB SRAM */
 +#define NPCM7XX_RAM3_BA         (0xc0008000)
 +#define NPCM7XX_RAM3_SZ         (4 * KiB)
 +
 +/* Memory blocks at the end of the address space */
 +#define NPCM7XX_RAM2_BA         (0xfffd0000)
 +#define NPCM7XX_RAM2_SZ         (128 * KiB)
 +#define NPCM7XX_ROM_BA          (0xffff0000)
 +#define NPCM7XX_ROM_SZ          (64 * KiB)
 +
 +/*
 + * Interrupt lines going into the GIC. This does not include internal Cortex-A9
 + * interrupts.
 + */
 +enum NPCM7xxInterrupt {
 +    NPCM7XX_UART0_IRQ           = 2,
 +    NPCM7XX_UART1_IRQ,
 +    NPCM7XX_UART2_IRQ,
 +    NPCM7XX_UART3_IRQ,
 +    NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
 +    NPCM7XX_TIMER1_IRQ,
 +    NPCM7XX_TIMER2_IRQ,
 +    NPCM7XX_TIMER3_IRQ,
 +    NPCM7XX_TIMER4_IRQ,
 +    NPCM7XX_TIMER5_IRQ,                 /* Timer Module 1 */
 +    NPCM7XX_TIMER6_IRQ,
 +    NPCM7XX_TIMER7_IRQ,
 +    NPCM7XX_TIMER8_IRQ,
 +    NPCM7XX_TIMER9_IRQ,
 +    NPCM7XX_TIMER10_IRQ,                /* Timer Module 2 */
 +    NPCM7XX_TIMER11_IRQ,
 +    NPCM7XX_TIMER12_IRQ,
 +    NPCM7XX_TIMER13_IRQ,
 +    NPCM7XX_TIMER14_IRQ,
 +};
 +
 +/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
 +#define NPCM7XX_NUM_IRQ         (160)
 +
 +/* Register base address for each Timer Module */
 +static const hwaddr npcm7xx_tim_addr[] = {
 +    0xf0008000,
 +    0xf0009000,
 +    0xf000a000,
 +};
 +
 +/* Register base address for each 16550 UART */
 +static const hwaddr npcm7xx_uart_addr[] = {
 +    0xf0001000,
 +    0xf0002000,
 +    0xf0003000,
 +    0xf0004000,
 +};
 +
 +static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
 +                                         const struct arm_boot_info *info)
 +{
 +    /*
 +     * The default smpboot stub halts the secondary CPU with a 'wfi'
 +     * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
 +     * does not send an IPI to wake it up, so the second CPU fails to boot. So
 +     * we need to provide our own smpboot stub that can not use 'wfi', it has
 +     * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
 +     */
 +    uint32_t smpboot[] = {
 +        0xe59f2018,     /* ldr r2, bootreg_addr */
 +        0xe3a00000,     /* mov r0, #0 */
 +        0xe5820000,     /* str r0, [r2] */
 +        0xe320f002,     /* wfe */
 +        0xe5921000,     /* ldr r1, [r2] */
 +        0xe1110001,     /* tst r1, r1 */
 +        0x0afffffb,     /* beq <wfe> */
 +        0xe12fff11,     /* bx r1 */
 +        NPCM7XX_SMP_BOOTREG_ADDR,
 +    };
 +    int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
 +        smpboot[i] = tswap32(smpboot[i]);
 +    }
 +
-+    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
++    addr = load_reg(s, a->rn);
-+                       NPCM7XX_SMP_LOADER_START);
++    if (a->p) {
-+}
++        tcg_gen_addi_i32(addr, addr, offset);
 +
 +static struct arm_boot_info npcm7xx_binfo = {
 +    .loader_start           = NPCM7XX_LOADER_START,
 +    .smp_loader_start       = NPCM7XX_SMP_LOADER_START,
 +    .smp_bootreg_addr       = NPCM7XX_SMP_BOOTREG_ADDR,
 +    .gic_cpu_if_addr        = NPCM7XX_GIC_CPU_IF_ADDR,
 +    .write_secondary_boot   = npcm7xx_write_secondary_boot,
 +    .board_id               = -1,
 +};
 +
 +void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
 +{
 +    NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc);
 +
 +    npcm7xx_binfo.ram_size = machine->ram_size;
 +    npcm7xx_binfo.nb_cpus = sc->num_cpus;
 +
 +    arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
 +}
 +
 +static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
 +{
 +    return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
 +}
 +
 +static void npcm7xx_init(Object *obj)
 +{
 +    NPCM7xxState *s = NPCM7XX(obj);
 +    int i;
 +
 +    for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
 +        object_initialize_child(obj, "cpu[*]", &s->cpu[i],
 +                                ARM_CPU_TYPE_NAME("cortex-a9"));
 +    }
 +
-+    object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
++    if (s->v8m_stackcheck && a->rn == 13 && a->w) {
-+    object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
++        gen_helper_v8m_stackcheck(cpu_env, addr);
-+    object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
++    }
 +                              "power-on-straps");
 +    object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
 +
-+    for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
++    gen_aa32_st_i32(s, value, addr, get_mem_index(s),
-+        object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
++                    MO_UL | MO_ALIGN | s->be_data);
 +    tcg_temp_free_i32(value);
 +
 +    if (a->w) {
 +        /* writeback */
 +        if (!a->p) {
 +            tcg_gen_addi_i32(addr, addr, offset);
 +        }
 +        store_reg(s, a->rn, addr);
 +    } else {
 +        tcg_temp_free_i32(addr);
 +    }
 +}
 +
-+static void npcm7xx_realize(DeviceState *dev, Error **errp)
++static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque)
 +{
-+    NPCM7xxState *s = NPCM7XX(dev);
++    arg_vldr_sysreg *a = opaque;
-+    NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
++    uint32_t offset = a->imm;
-+    int i;
++    TCGv_i32 addr;
 +    TCGv_i32 value = tcg_temp_new_i32();
 +
-+    if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) {
++    if (!a->a) {
-+        error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64
++        offset = - offset;
 +                   " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB);
 +        return;
 +    }
 +
-+    /* CPUs */
++    addr = load_reg(s, a->rn);
-+    for (i = 0; i < nc->num_cpus; i++) {
++    if (a->p) {
-+        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
++        tcg_gen_addi_i32(addr, addr, offset);
 +                                arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
 +                                &error_abort);
 +        object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
 +                                NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
 +        object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
 +                                 &error_abort);
 +
 +        /* Disable security extensions. */
 +        object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
 +                                 &error_abort);
 +
 +        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
 +            return;
 +        }
 +    }
 +
-+    /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */
++    if (s->v8m_stackcheck && a->rn == 13 && a->w) {
-+    object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus,
++        gen_helper_v8m_stackcheck(cpu_env, addr);
 +                            &error_abort);
 +    object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ,
 +                            &error_abort);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
 +
 +    for (i = 0; i < nc->num_cpus; i++) {
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
 +                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
 +                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
 +    }
 +
-+    /* L2 cache controller */
++    gen_aa32_ld_i32(s, value, addr, get_mem_index(s),
-+    sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
++                    MO_UL | MO_ALIGN | s->be_data);
 +
-+    /* System Global Control Registers (GCR). Can fail due to user input. */
++    if (a->w) {
-+    object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
++        /* writeback */
-+                            nc->disabled_modules, &error_abort);
++        if (!a->p) {
-+    object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
++            tcg_gen_addi_i32(addr, addr, offset);
-+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
++        }
-+        return;
++        store_reg(s, a->rn, addr);
 +    } else {
 +        tcg_temp_free_i32(addr);
 +    }
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
++    return value;
 +
 +    /* Clock Control Registers (CLK). Cannot fail. */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
 +
 +    /* Timer Modules (TIM). Cannot fail. */
 +    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
 +    for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
 +        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
 +        int first_irq;
 +        int j;
 +
 +        sysbus_realize(sbd, &error_abort);
 +        sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 +
 +        first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
 +        for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
 +            qemu_irq irq = npcm7xx_irq(s, first_irq + j);
 +            sysbus_connect_irq(sbd, j, irq);
 +        }
 +    }
 +
 +    /* UART0..3 (16550 compatible) */
 +    for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
 +        serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
 +                       npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
 +                       serial_hd(i), DEVICE_LITTLE_ENDIAN);
 +    }
 +
 +    /* RAM2 (SRAM) */
 +    memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
 +                           NPCM7XX_RAM2_SZ, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
 +
 +    /* RAM3 (SRAM) */
 +    memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
 +                           NPCM7XX_RAM3_SZ, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3);
 +
 +    /* Internal ROM */
 +    memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
 +
 +    create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
 +    create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.rng",          0xf000b000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gpio[2]",      0xf0012000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gpio[3]",      0xf0013000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gpio[4]",      0xf0014000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gpio[5]",      0xf0015000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gpio[6]",      0xf0016000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.gpio[7]",      0xf0017000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[0]",     0xf0080000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[1]",     0xf0081000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[2]",     0xf0082000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[3]",     0xf0083000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[4]",     0xf0084000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[5]",     0xf0085000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[6]",     0xf0086000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[7]",     0xf0087000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[8]",     0xf0088000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[9]",     0xf0089000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[10]",    0xf008a000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[11]",    0xf008b000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[12]",    0xf008c000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[13]",    0xf008d000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[14]",    0xf008e000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.smbus[15]",    0xf008f000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.espi",         0xf009f000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.mft[3]",       0xf0183000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.mft[4]",       0xf0184000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.mft[5]",       0xf0185000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.mft[6]",       0xf0186000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.mft[7]",       0xf0187000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
 +    create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
 +    create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
 +    create_unimplemented_device("npcm7xx.gmac2",        0xf0804000,   8 * KiB);
 +    create_unimplemented_device("npcm7xx.ehci",         0xf0806000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.ohci",         0xf0807000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.vcd",          0xf0810000,  64 * KiB);
 +    create_unimplemented_device("npcm7xx.ece",          0xf0820000,   8 * KiB);
 +    create_unimplemented_device("npcm7xx.vdma",         0xf0822000,   8 * KiB);
 +    create_unimplemented_device("npcm7xx.emc1",         0xf0825000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.emc2",         0xf0826000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[0]",      0xf0830000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[1]",      0xf0831000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[2]",      0xf0832000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[3]",      0xf0833000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[4]",      0xf0834000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[5]",      0xf0835000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[6]",      0xf0836000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[7]",      0xf0837000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[8]",      0xf0838000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.usbd[9]",      0xf0839000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.sd",           0xf0840000,   8 * KiB);
 +    create_unimplemented_device("npcm7xx.mmc",          0xf0842000,   8 * KiB);
 +    create_unimplemented_device("npcm7xx.pcimbx",       0xf0848000, 512 * KiB);
 +    create_unimplemented_device("npcm7xx.aes",          0xf0858000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.des",          0xf0859000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.sha",          0xf085a000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.secacc",       0xf085b000,   4 * KiB);
 +    create_unimplemented_device("npcm7xx.spixcs0",      0xf8000000,  16 * MiB);
 +    create_unimplemented_device("npcm7xx.spixcs1",      0xf9000000,  16 * MiB);
 +    create_unimplemented_device("npcm7xx.spix",         0xfb001000,   4 * KiB);
 +}
 +
-+static Property npcm7xx_properties[] = {
++static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
 +    DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION,
 +                     MemoryRegion *),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void npcm7xx_class_init(ObjectClass *oc, void *data)
 +{
-+    DeviceClass *dc = DEVICE_CLASS(oc);
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-+
++        return false;
-+    dc->realize = npcm7xx_realize;
++    }
-+    dc->user_creatable = false;
++    if (a->rn == 15) {
-+    device_class_set_props(dc, npcm7xx_properties);
++        return false;
 +    }
 +    return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a);
 +}
 +
-+static void npcm730_class_init(ObjectClass *oc, void *data)
++static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
 +{
-+    NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
++    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-+
++        return false;
-+    /* NPCM730 is optimized for data center use, so no graphics, etc. */
++    }
-+    nc->disabled_modules = 0x00300395;
++    if (a->rn == 15) {
-+    nc->num_cpus = 2;
++        return false;
 +    }
 +    return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a);
 +}
 +
-+static void npcm750_class_init(ObjectClass *oc, void *data)
+ static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
-+{
+ {
-+    NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
+     TCGv_i32 tmp;
 +
 +    /* NPCM750 has 2 cores and a full set of peripherals */
 +    nc->disabled_modules = 0x00000000;
 +    nc->num_cpus = 2;
 +}
 +
 +static const TypeInfo npcm7xx_soc_types[] = {
 +    {
 +        .name           = TYPE_NPCM7XX,
 +        .parent         = TYPE_DEVICE,
 +        .instance_size  = sizeof(NPCM7xxState),
 +        .instance_init  = npcm7xx_init,
 +        .class_size     = sizeof(NPCM7xxClass),
 +        .class_init     = npcm7xx_class_init,
 +        .abstract       = true,
 +    }, {
 +        .name           = TYPE_NPCM730,
 +        .parent         = TYPE_NPCM7XX,
 +        .class_init     = npcm730_class_init,
 +    }, {
 +        .name           = TYPE_NPCM750,
 +        .parent         = TYPE_NPCM7XX,
 +        .class_init     = npcm750_class_init,
 +    },
 +};
 +
 +DEFINE_TYPES(npcm7xx_soc_types);
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
  config NPCM7XX
      bool
 +    select A9MPCORE
 +    select ARM_GIC
 +    select PL310  # cache controller
 +    select SERIAL
 +    select UNIMP
  config FSL_IMX25
      bool
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
  arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
  arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
  arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
 +arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c'))
  arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
  arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
  arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
 --
 .20.1

-[PULL 15/36] Deprecate Unicore32 port
+[PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc
-Deprecate our Unicore32 target support:
+v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves
- * the Linux kernel dropped support for unicore32 in commit
+like the existing FPSCR, except that it reads and writes only bits
-   05119217a9bd199c for its 5.9 release (with rationale in the
+[31:27] of the FPSCR (the N, Z, C, V and QC flag bits).  (Unlike the
-   cover letter: https://lkml.org/lkml/2020/8/3/232 )
+FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not
- * there is apparently no upstream toolchain that can create unicore32
+permitted.)
-   binaries
- * the maintainer doesn't seem to have made any contributions to
+Implement the register.  Since we don't yet implement MVE, we handle
-   QEMU since the port first landed in 2012
+the QC bit as RES0, with todo comments for where we will need to add
- * nobody else seems to have made changes to the unicore code except
+support later.
    for generic cleanups either
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200825172719.19422-1-peter.maydell@linaro.org
+Message-id: 20201119215617.29887-11-peter.maydell@linaro.org
 ---
- docs/system/deprecated.rst | 8 ++++++++
+ target/arm/cpu.h               | 13 +++++++++++++
-file changed, 8 insertions(+)
+ target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++
 files changed, 40 insertions(+)
-diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/deprecated.rst
+--- a/target/arm/cpu.h
-+++ b/docs/system/deprecated.rst
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
+@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
- linux-user mode CPUs
+ #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
- --------------------
+ #define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
+ #define FPCR_QC     (1 << 27)   /* Cumulative saturation bit */
-+``unicore32`` CPUs (since 5.2.0)
++#define FPCR_V      (1 << 28)   /* FP overflow flag */
-+''''''''''''''''''''''''''''''''
++#define FPCR_C      (1 << 29)   /* FP carry flag */
 +#define FPCR_Z      (1 << 30)   /* FP zero flag */
 +#define FPCR_N      (1 << 31)   /* FP negative flag */
 +
-+The ``unicore32`` guest CPU support is deprecated and will be removed in
++#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
-+a future version of QEMU. Support for this CPU was removed from the
++#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
-+upstream Linux kernel, and there is no available upstream toolchain
-+to build binaries for it.
+ static inline uint32_t vfp_get_fpsr(CPUARMState *env)
-+
+ {
- ``tilegx`` CPUs (since 5.1.0)
+@@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode {
- '''''''''''''''''''''''''''''
+ #define ARM_VFP_FPEXC   8
+ #define ARM_VFP_FPINST  9
  #define ARM_VFP_FPINST2 10
 +/* These ones are M-profile only */
 +#define ARM_VFP_FPSCR_NZCVQC 2
 +#define ARM_VFP_VPR 12
 +#define ARM_VFP_P0 13
 +#define ARM_VFP_FPCXT_NS 14
 +#define ARM_VFP_FPCXT_S 15
  /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
  #define QEMU_VFP_FPSCR_NZCV 0xffff
 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-vfp.c.inc
 +++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
      case ARM_VFP_FPSCR:
      case QEMU_VFP_FPSCR_NZCV:
          break;
 +    case ARM_VFP_FPSCR_NZCVQC:
 +        if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +            return false;
 +        }
 +        break;
      default:
          return FPSysRegCheckFailed;
      }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
          tcg_temp_free_i32(tmp);
          gen_lookup_tb(s);
          break;
 +    case ARM_VFP_FPSCR_NZCVQC:
 +    {
 +        TCGv_i32 fpscr;
 +        tmp = loadfn(s, opaque);
 +        /*
 +         * TODO: when we implement MVE, write the QC bit.
 +         * For non-MVE, QC is RES0.
 +         */
 +        tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
 +        fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
 +        tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
 +        tcg_gen_or_i32(fpscr, fpscr, tmp);
 +        store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
 +        tcg_temp_free_i32(tmp);
 +        break;
 +    }
      default:
          g_assert_not_reached();
      }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
          gen_helper_vfp_get_fpscr(tmp, cpu_env);
          storefn(s, opaque, tmp);
          break;
 +    case ARM_VFP_FPSCR_NZCVQC:
 +        /*
 +         * TODO: MVE has a QC bit, which we probably won't store
 +         * in the xregs[] field. For non-MVE, where QC is RES0,
 +         * we can just fall through to the FPSCR_NZCV case.
 +         */
      case QEMU_VFP_FPSCR_NZCV:
          /*
           * Read just NZCV; this is a special case to avoid the
 --
 .20.1

-[PULL 32/36] tests/acceptance: console boot tests for quanta-gsj
+[PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant
-From: Havard Skinnemoen <hskinnemoen@google.com>
+We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
 in the previous commit; use it in a couple of places in existing code,
 where we're masking out everything except NZCV for the "load to Rt=15
 sets CPSR.NZCV" special case.
-This adds two acceptance tests for the quanta-gsj machine.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20201119215617.29887-12-peter.maydell@linaro.org
 ---
  target/arm/translate-vfp.c.inc | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
-One test downloads a lightly patched openbmc flash image from github and
+diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 verifies that it boots all the way to the login prompt.
 The other test downloads a kernel, initrd and dtb built from the same
 openbmc source and verifies that the kernel detects all CPUs and boots
 to the point where it can't find the root filesystem (because we have no
 flash image in this case).
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-15-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/acceptance/boot_linux_console.py | 83 ++++++++++++++++++++++++++
 file changed, 83 insertions(+)
 diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/tests/acceptance/boot_linux_console.py
+--- a/target/arm/translate-vfp.c.inc
-+++ b/tests/acceptance/boot_linux_console.py
++++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
+@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
-                                                 'sda')
+          * helper call for the "VMRS to CPSR.NZCV" insn.
-         # cubieboard's reboot is not functioning; omit reboot test.
+          */
+         tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
-+    def test_arm_quanta_gsj(self):
+-        tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
-+        """
++        tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
-+        :avocado: tags=arch:arm
+         storefn(s, opaque, tmp);
-+        :avocado: tags=machine:quanta-gsj
+         break;
-+        """
+     default:
-+        # 25 MiB compressed, 32 MiB uncompressed.
+@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
-+        image_url = (
+         case ARM_VFP_FPSCR:
-+                'https://github.com/hskinnemoen/openbmc/releases/download/'
+             if (a->rt == 15) {
-+                '20200711-gsj-qemu-0/obmc-phosphor-image-gsj.static.mtd.gz')
+                 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
-+        image_hash = '14895e634923345cb5c8776037ff7876df96f6b1'
+-                tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
-+        image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash)
++                tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
-+        image_name = 'obmc.mtd'
+             } else {
-+        image_path = os.path.join(self.workdir, image_name)
+                 tmp = tcg_temp_new_i32();
-+        archive.gzip_uncompress(image_path_gz, image_path)
+                 gen_helper_vfp_get_fpscr(tmp, cpu_env);
 +
 +        self.vm.set_console()
 +        drive_args = 'file=' + image_path + ',if=mtd,bus=0,unit=0'
 +        self.vm.add_args('-drive', drive_args)
 +        self.vm.launch()
 +
 +        # Disable drivers and services that stall for a long time during boot,
 +        # to avoid running past the 90-second timeout. These may be removed
 +        # as the corresponding device support is added.
 +        kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + (
 +                'console=${console} '
 +                'mem=${mem} '
 +                'initcall_blacklist=npcm_i2c_bus_driver_init '
 +                'systemd.mask=systemd-random-seed.service '
 +                'systemd.mask=dropbearkey.service '
 +        )
 +
 +        self.wait_for_console_pattern('> BootBlock by Nuvoton')
 +        self.wait_for_console_pattern('>Device: Poleg BMC NPCM730')
 +        self.wait_for_console_pattern('>Skip DDR init.')
 +        self.wait_for_console_pattern('U-Boot ')
 +        interrupt_interactive_console_until_pattern(
 +                self, 'Hit any key to stop autoboot:', 'U-Boot>')
 +        exec_command_and_wait_for_pattern(
 +                self, "setenv bootargs ${bootargs} " + kernel_command_line,
 +                'U-Boot>')
 +        exec_command_and_wait_for_pattern(
 +                self, 'run romboot', 'Booting Kernel from flash')
 +        self.wait_for_console_pattern('Booting Linux on physical CPU 0x0')
 +        self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0')
 +        self.wait_for_console_pattern('OpenBMC Project Reference Distro')
 +        self.wait_for_console_pattern('gsj login:')
 +
 +    def test_arm_quanta_gsj_initrd(self):
 +        """
 +        :avocado: tags=arch:arm
 +        :avocado: tags=machine:quanta-gsj
 +        """
 +        initrd_url = (
 +                'https://github.com/hskinnemoen/openbmc/releases/download/'
 +                '20200711-gsj-qemu-0/obmc-phosphor-initramfs-gsj.cpio.xz')
 +        initrd_hash = '98fefe5d7e56727b1eb17d5c00311b1b5c945300'
 +        initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
 +        kernel_url = (
 +                'https://github.com/hskinnemoen/openbmc/releases/download/'
 +                '20200711-gsj-qemu-0/uImage-gsj.bin')
 +        kernel_hash = 'fa67b2f141d56d39b3c54305c0e8a899c99eb2c7'
 +        kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
 +        dtb_url = (
 +                'https://github.com/hskinnemoen/openbmc/releases/download/'
 +                '20200711-gsj-qemu-0/nuvoton-npcm730-gsj.dtb')
 +        dtb_hash = '18315f7006d7b688d8312d5c727eecd819aa36a4'
 +        dtb_path = self.fetch_asset(dtb_url, asset_hash=dtb_hash)
 +
 +        self.vm.set_console()
 +        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
 +                               'console=ttyS0,115200n8 '
 +                               'earlycon=uart8250,mmio32,0xf0001000')
 +        self.vm.add_args('-kernel', kernel_path,
 +                         '-initrd', initrd_path,
 +                         '-dtb', dtb_path,
 +                         '-append', kernel_command_line)
 +        self.vm.launch()
 +
 +        self.wait_for_console_pattern('Booting Linux on physical CPU 0x0')
 +        self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0')
 +        self.wait_for_console_pattern(
 +                'Give root password for system maintenance')
 +
      def test_arm_orangepi(self):
          """
          :avocado: tags=arch:arm
 --
 .20.1

-[PULL 12/36] hw/arm/mps2: New board model mps2-an386
+[PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check()
-Implement a model of the MPS2 with the AN386 firmware. This is
+Factor out the code which handles M-profile lazy FP state preservation
-essentially identical to the AN385 firmware, but it has a
+from full_vfp_access_check(); accesses to the FPCXT_NS register are
-Cortex-M4 rather than a Cortex-M3.
+a special case which need to do just this part (corresponding in the
 pseudocode to the PreserveFPState() function), and not the full
 set of actions matching the pseudocode ExecuteFPCheck() which
 normal FP instructions need to do.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200903202048.15370-2-peter.maydell@linaro.org
+Message-id: 20201119215617.29887-13-peter.maydell@linaro.org
 ---
- docs/system/arm/mps2.rst |  8 +++++---
+ target/arm/translate-vfp.c.inc | 45 ++++++++++++++++++++--------------
- hw/arm/mps2.c            | 34 +++++++++++++++++++++++++++++-----
+file changed, 27 insertions(+), 18 deletions(-)
 files changed, 34 insertions(+), 8 deletions(-)
-diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
+diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/mps2.rst
+--- a/target/arm/translate-vfp.c.inc
-+++ b/docs/system/arm/mps2.rst
++++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top)
--Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
+     return offs;
 -================================================================================
 +Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
 +================================================================================================
  These board models all use Arm M-profile CPUs.
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
  ``mps2-an385``
    Cortex-M3 as documented in ARM Application Note AN385
 +``mps2-an386``
 +  Cortex-M4 as documented in ARM Application Note AN386
  ``mps2-an511``
    Cortex-M3 'DesignStart' as documented in AN511
  ``mps2-an505``
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
  Differences between QEMU and real hardware:
 -- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to
 +- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
    block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
    if zbt_boot_ctrl is always zero)
  - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
 diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/mps2.c
 +++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
   * as seen by the guest depend significantly on the FPGA image.
   * We model the following FPGA images:
   *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
 + *  "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
   *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
   *
   * Links to the TRM for the board itself and to the various Application
@@ -XXX,XX +XXX,XX @@
  typedef enum MPS2FPGAType {
      FPGA_AN385,
 +    FPGA_AN386,
      FPGA_AN511,
  } MPS2FPGAType;
@@ -XXX,XX +XXX,XX @@ typedef struct MPS2MachineState MPS2MachineState;
  #define TYPE_MPS2_MACHINE "mps2"
  #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
 +#define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
  #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
  DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass,
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
       * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
       * call the 16MB our "system memory", as it's the largest lump.
       *
 -     * Common to both boards:
 -     *  0x21000000..0x21ffffff : PSRAM (16MB)
 -     * AN385 only:
 +     * AN385/AN386/AN511:
 +     *  0x21000000 .. 0x21ffffff : PSRAM (16MB)
 +     * AN385/AN386 only:
       *  0x00000000 .. 0x003fffff : ZBT SSRAM1
       *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
       *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
       *  0x20000000 .. 0x2001ffff : SRAM
       *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
       *
 -     * The AN385 has a feature where the lowest 16K can be mapped
 +     * The AN385/AN386 has a feature where the lowest 16K can be mapped
       * either to the bottom of the ZBT SSRAM1 or to the block RAM.
       * This is of no use for QEMU so we don't implement it (as if
       * zbt_boot_ctrl is always zero).
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      switch (mmc->fpga_type) {
      case FPGA_AN385:
 +    case FPGA_AN386:
          make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
          make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
          make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      armv7m = DEVICE(&mms->armv7m);
      switch (mmc->fpga_type) {
      case FPGA_AN385:
 +    case FPGA_AN386:
          qdev_prop_set_uint32(armv7m, "num-irq", 32);
          break;
      case FPGA_AN511:
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      switch (mmc->fpga_type) {
      case FPGA_AN385:
 +    case FPGA_AN386:
      {
          /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
           * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
       */
      lan9118_init(&nd_table[0], 0x40200000,
                   qdev_get_gpio_in(armv7m,
 -                                  mmc->fpga_type == FPGA_AN385 ? 13 : 47));
 +                                  mmc->fpga_type == FPGA_AN511 ? 47 : 13));
      system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
@@ -XXX,XX +XXX,XX @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
      mmc->scc_id = 0x41043850;
  }
-+static void mps2_an386_class_init(ObjectClass *oc, void *data)
++/*
 + * Generate code for M-profile lazy FP state preservation if needed;
 + * this corresponds to the pseudocode PreserveFPState() function.
 + */
 +static void gen_preserve_fp_state(DisasContext *s)
 +{
-+    MachineClass *mc = MACHINE_CLASS(oc);
++    if (s->v7m_lspact) {
-+    MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
++        /*
-+
++         * Lazy state saving affects external memory and also the NVIC,
-+    mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
++         * so we must mark it as an IO operation for icount (and cause
-+    mmc->fpga_type = FPGA_AN386;
++         * this to be the last insn in the TB).
-+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
++         */
-+    mmc->scc_id = 0x41043860;
++        if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
 +            s->base.is_jmp = DISAS_UPDATE_EXIT;
 +            gen_io_start();
 +        }
 +        gen_helper_v7m_preserve_fp_state(cpu_env);
 +        /*
 +         * If the preserve_fp_state helper doesn't throw an exception
 +         * then it will clear LSPACT; we don't need to repeat this for
 +         * any further FP insns in this TB.
 +         */
 +        s->v7m_lspact = false;
 +    }
 +}
 +
- static void mps2_an511_class_init(ObjectClass *oc, void *data)
+ /*
- {
+  * Check that VFP access is enabled. If it is, do the necessary
-     MachineClass *mc = MACHINE_CLASS(oc);
+  * M-profile lazy-FP handling and then return true.
-@@ -XXX,XX +XXX,XX @@ static const TypeInfo mps2_an385_info = {
+@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
-     .class_init = mps2_an385_class_init,
+         /* Handle M-profile lazy FP state mechanics */
- };
+         /* Trigger lazy-state preservation if necessary */
-+static const TypeInfo mps2_an386_info = {
+-        if (s->v7m_lspact) {
-+    .name = TYPE_MPS2_AN386_MACHINE,
+-            /*
-+    .parent = TYPE_MPS2_MACHINE,
+-             * Lazy state saving affects external memory and also the NVIC,
-+    .class_init = mps2_an386_class_init,
+-             * so we must mark it as an IO operation for icount (and cause
-+};
+-             * this to be the last insn in the TB).
-+
+-             */
- static const TypeInfo mps2_an511_info = {
+-            if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
-     .name = TYPE_MPS2_AN511_MACHINE,
+-                s->base.is_jmp = DISAS_UPDATE_EXIT;
-     .parent = TYPE_MPS2_MACHINE,
+-                gen_io_start();
-@@ -XXX,XX +XXX,XX @@ static void mps2_machine_init(void)
+-            }
- {
+-            gen_helper_v7m_preserve_fp_state(cpu_env);
-     type_register_static(&mps2_info);
+-            /*
-     type_register_static(&mps2_an385_info);
+-             * If the preserve_fp_state helper doesn't throw an exception
-+    type_register_static(&mps2_an386_info);
+-             * then it will clear LSPACT; we don't need to repeat this for
-     type_register_static(&mps2_an511_info);
+-             * any further FP insns in this TB.
- }
+-             */
+-            s->v7m_lspact = false;
 -        }
 +        gen_preserve_fp_state(s);
          /* Update ownership of FP context: set FPCCR.S to match current state */
          if (s->v8m_fpccr_s_wrong) {
 --
 .20.1

-[PULL 08/36] target/arm: Convert Neon VCVT fp size field to MO_* in decode
+[PULL 24/36] target/arm: Implement FPCXT_S fp system register
-Convert the insns using the 2reg_vcvt and 2reg_vcvt_f16 formats
+Implement the new-in-v8.1M FPCXT_S floating point system register.
-to pass the size through to the trans function as a MO_* value
+This is for saving and restoring the secure floating point context,
-rather than the '0==f32, 1==f16' used in the fp 3-same encodings.
+and it reads and writes bits [27:0] from the FPSCR and the
 CONTROL.SFPA bit in bit [31].
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200903133209.5141-3-peter.maydell@linaro.org
+Message-id: 20201119215617.29887-14-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 3 +--
+ target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++
- target/arm/translate-neon.c.inc | 4 ++--
+file changed, 58 insertions(+)
 files changed, 3 insertions(+), 4 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/target/arm/translate-vfp.c.inc
-+++ b/target/arm/neon-dp.decode
++++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
+@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
  @2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
                   &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
 -# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
  @2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
 -                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
 +                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
  @2reg_vcvt_f16   .... ... . . . 11 .... .... .... . q:1 . . .... \
                   &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c.inc
 +++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
          return false;
      }
 -    if (a->size != 0) {
 +    if (a->size == MO_16) {
          if (!dc_isar_feature(aa32_fp16_arith, s)) {
              return false;
          }
-@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
+         break;
-         return true;
++    case ARM_VFP_FPCXT_S:
 +        if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
 +            return false;
 +        }
 +        if (!s->v8m_secure) {
 +            return false;
 +        }
 +        break;
      default:
          return FPSysRegCheckFailed;
      }
+@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
--    fpst = fpstatus_ptr(a->size ? FPST_STD_F16 : FPST_STD);
+         tcg_temp_free_i32(tmp);
-+    fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
+         break;
-     tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, vec_size, vec_size, a->shift, fn);
+     }
-     tcg_temp_free_ptr(fpst);
++    case ARM_VFP_FPCXT_S:
-     return true;
++    {
 +        TCGv_i32 sfpa, control, fpscr;
 +        /* Set FPSCR[27:0] and CONTROL.SFPA from value */
 +        tmp = loadfn(s, opaque);
 +        sfpa = tcg_temp_new_i32();
 +        tcg_gen_shri_i32(sfpa, tmp, 31);
 +        control = load_cpu_field(v7m.control[M_REG_S]);
 +        tcg_gen_deposit_i32(control, control, sfpa,
 +                            R_V7M_CONTROL_SFPA_SHIFT, 1);
 +        store_cpu_field(control, v7m.control[M_REG_S]);
 +        fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
 +        tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK);
 +        tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
 +        tcg_gen_or_i32(fpscr, fpscr, tmp);
 +        store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
 +        tcg_temp_free_i32(tmp);
 +        tcg_temp_free_i32(sfpa);
 +        break;
 +    }
      default:
          g_assert_not_reached();
      }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
          tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
          storefn(s, opaque, tmp);
          break;
 +    case ARM_VFP_FPCXT_S:
 +    {
 +        TCGv_i32 control, sfpa, fpscr;
 +        /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
 +        tmp = tcg_temp_new_i32();
 +        sfpa = tcg_temp_new_i32();
 +        gen_helper_vfp_get_fpscr(tmp, cpu_env);
 +        tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
 +        control = load_cpu_field(v7m.control[M_REG_S]);
 +        tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
 +        tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
 +        tcg_gen_or_i32(tmp, tmp, sfpa);
 +        tcg_temp_free_i32(sfpa);
 +        /*
 +         * Store result before updating FPSCR etc, in case
 +         * it is a memory write which causes an exception.
 +         */
 +        storefn(s, opaque, tmp);
 +        /*
 +         * Now we must reset FPSCR from FPDSCR_NS, and clear
 +         * CONTROL.SFPA; so we'll end the TB here.
 +         */
 +        tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
 +        store_cpu_field(control, v7m.control[M_REG_S]);
 +        fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
 +        gen_helper_vfp_set_fpscr(cpu_env, fpscr);
 +        tcg_temp_free_i32(fpscr);
 +        gen_lookup_tb(s);
 +        break;
 +    }
      default:
          g_assert_not_reached();
      }
 --
 .20.1

-[PULL 11/36] target/arm: Remove no-longer-reachable 32-bit KVM code
+[PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
-Now that 32-bit KVM host support is gone, KVM can never
+The FPDSCR register has a similar layout to the FPSCR.  In v8.1M it
-be enabled unless CONFIG_AARCH64 is true, and some code
+gains new fields FZ16 (if half-precision floating point is supported)
-paths are no longer reachable and can be deleted.
+and LTPSIZE (always reads as 4).  Update the reset value and the code
 that handles writes to this register accordingly.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
 Message-id: 20200904154156.31943-3-peter.maydell@linaro.org
 ---
- target/arm/kvm-consts.h |   7 ---
+ target/arm/cpu.h      | 5 +++++
- target/arm/kvm_arm.h    |   6 ---
+ hw/intc/armv7m_nvic.c | 9 ++++++++-
- target/arm/cpu.c        | 101 +++++++++++++++++++---------------------
+ target/arm/cpu.c      | 3 +++
- target/arm/kvm.c        |   7 ---
+files changed, 16 insertions(+), 1 deletion(-)
 files changed, 47 insertions(+), 74 deletions(-)
-diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm-consts.h
+--- a/target/arm/cpu.h
-+++ b/target/arm/kvm-consts.h
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED);
+@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
-  */
+ #define FPCR_IXE    (1 << 12)   /* Inexact exception trap enable */
- #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX
+ #define FPCR_IDE    (1 << 15)   /* Input Denormal exception trap enable */
+ #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
--#ifdef TARGET_AARCH64
++#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
- MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8);
+ #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
- MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8);
+ #define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
- MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57);
++#define FPCR_AHP    (1 << 26)   /* Alternative half-precision */
- MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA);
+ #define FPCR_QC     (1 << 27)   /* Cumulative saturation bit */
- MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53);
+ #define FPCR_V      (1 << 28)   /* FP overflow flag */
--#else
+ #define FPCR_C      (1 << 29)   /* FP carry flag */
--MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15);
+ #define FPCR_Z      (1 << 30)   /* FP zero flag */
--MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7);
+ #define FPCR_N      (1 << 31)   /* FP negative flag */
--#endif
++#define FPCR_LTPSIZE_SHIFT 16   /* LTPSIZE, M-profile only */
- #define CP_REG_ARM64                   0x6000000000000000ULL
++#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
- #define CP_REG_ARM_COPROC_MASK         0x000000000FFF0000
++
-@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7);
+ #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
- /* No kernel define but it's useful to QEMU */
+ #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
- #define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT)
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 -#ifdef TARGET_AARCH64
  MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64);
  MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK);
  MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT);
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK);
  MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT);
  MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK);
  MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT);
 -#endif
  #undef MISMATCH_CHECK
 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm_arm.h
+--- a/hw/intc/armv7m_nvic.c
-+++ b/target/arm/kvm_arm.h
++++ b/hw/intc/armv7m_nvic.c
-@@ -XXX,XX +XXX,XX @@ static inline const char *gic_class_name(void)
+@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
- static inline const char *gicv3_class_name(void)
+         break;
- {
+     case 0xf3c: /* FPDSCR */
-     if (kvm_irqchip_in_kernel()) {
+         if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
--#ifdef TARGET_AARCH64
+-            value &= 0x07c00000;
-         return "kvm-arm-gicv3";
++            uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK;
--#else
++            if (cpu_isar_feature(any_fp16, cpu)) {
--        error_report("KVM GICv3 acceleration is not supported on this "
++                mask |= FPCR_FZ16;
--                     "platform");
++            }
--        exit(1);
++            value &= mask;
--#endif
++            if (cpu_isar_feature(aa32_lob, cpu)) {
-     } else {
++                value |= 4 << FPCR_LTPSIZE_SHIFT;
-         if (kvm_enabled()) {
++            }
-             error_report("Userspace GICv3 is not supported with KVM");
+             cpu->env.v7m.fpdscr[attrs.secure] = value;
          }
          break;
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
- }
+              * always reset to 4.
+              */
- #ifndef TARGET_AARCH64
+             env->v7m.ltpsize = 4;
--/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
++            /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
-- * otherwise, a CPU with as many features enabled as our emulation supports.
++            env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
-+/*
++            env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
-+ * -cpu max: a CPU with as many features enabled as our emulation supports.
+         }
-  * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
-- * this only needs to handle 32 bits.
+         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 + * this only needs to handle 32 bits, and need not care about KVM.
   */
  static void arm_max_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 -    if (kvm_enabled()) {
 -        kvm_arm_set_cpu_features_from_host(cpu);
 -    } else {
 -        cortex_a15_initfn(obj);
 +    cortex_a15_initfn(obj);
 -        /* old-style VFP short-vector support */
 -        cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 +    /* old-style VFP short-vector support */
 +    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
  #ifdef CONFIG_USER_ONLY
 -        /* We don't set these in system emulation mode for the moment,
 -         * since we don't correctly set (all of) the ID registers to
 -         * advertise them.
 -         */
 -        set_feature(&cpu->env, ARM_FEATURE_V8);
 -        {
 -            uint32_t t;
 +    /*
 +     * We don't set these in system emulation mode for the moment,
 +     * since we don't correctly set (all of) the ID registers to
 +     * advertise them.
 +     */
 +    set_feature(&cpu->env, ARM_FEATURE_V8);
 +    {
 +        uint32_t t;
 -            t = cpu->isar.id_isar5;
 -            t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 -            t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 -            t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 -            t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 -            t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 -            t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 -            cpu->isar.id_isar5 = t;
 +        t = cpu->isar.id_isar5;
 +        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
 +        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
 +        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
 +        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
 +        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
 +        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
 +        cpu->isar.id_isar5 = t;
 -            t = cpu->isar.id_isar6;
 -            t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 -            t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 -            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 -            t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 -            t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 -            cpu->isar.id_isar6 = t;
 +        t = cpu->isar.id_isar6;
 +        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
 +        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
 +        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
 +        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
 +        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
 +        cpu->isar.id_isar6 = t;
 -            t = cpu->isar.mvfr1;
 -            t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 -            t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 -            cpu->isar.mvfr1 = t;
 +        t = cpu->isar.mvfr1;
 +        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
 +        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
 +        cpu->isar.mvfr1 = t;
 -            t = cpu->isar.mvfr2;
 -            t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 -            t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 -            cpu->isar.mvfr2 = t;
 +        t = cpu->isar.mvfr2;
 +        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
 +        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
 +        cpu->isar.mvfr2 = t;
 -            t = cpu->isar.id_mmfr3;
 -            t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 -            cpu->isar.id_mmfr3 = t;
 +        t = cpu->isar.id_mmfr3;
 +        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
 +        cpu->isar.id_mmfr3 = t;
 -            t = cpu->isar.id_mmfr4;
 -            t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 -            t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 -            t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 -            t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 -            cpu->isar.id_mmfr4 = t;
 -        }
 -#endif
 +        t = cpu->isar.id_mmfr4;
 +        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
 +        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
 +        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
 +        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
 +        cpu->isar.id_mmfr4 = t;
      }
 +#endif
  }
  #endif
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
  static const TypeInfo host_arm_cpu_type_info = {
      .name = TYPE_ARM_HOST_CPU,
 -#ifdef TARGET_AARCH64
      .parent = TYPE_AARCH64_CPU,
 -#else
 -    .parent = TYPE_ARM_CPU,
 -#endif
      .instance_init = arm_host_initfn,
  };
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_process_async_events(CPUState *cs)
      return 0;
  }
 -/* The #ifdef protections are until 32bit headers are imported and can
 - * be removed once both 32 and 64 bit reach feature parity.
 - */
  void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
  {
 -#ifdef KVM_GUESTDBG_USE_SW_BP
      if (kvm_sw_breakpoints_active(cs)) {
          dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
      }
 -#endif
 -#ifdef KVM_GUESTDBG_USE_HW
      if (kvm_arm_hw_debug_active(cs)) {
          dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW;
          kvm_arm_copy_hw_debug_data(&dbg->arch);
      }
 -#endif
  }
  void kvm_arch_init_irq_routing(KVMState *s)
 --
 .20.1

-[PULL 31/36] docs/system: Add Nuvoton machine documentation
+[PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
-From: Havard Skinnemoen <hskinnemoen@google.com>
+In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR
 are zeroed for an exception taken to Non-secure state; for an
 exception taken to Secure state they become UNKNOWN, and we chose to
 leave them at their previous values.
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
+In v8.1M the behaviour is specified more tightly and these registers
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+are always zeroed regardless of the security state that the exception
-Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
+targets (see rule R_KPZV).  Implement this.
-Message-id: 20200911052101.2602693-14-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20201119215617.29887-17-peter.maydell@linaro.org
 ---
- docs/system/arm/nuvoton.rst | 92 +++++++++++++++++++++++++++++++++++++
+ target/arm/m_helper.c | 16 ++++++++++++----
- docs/system/target-arm.rst  |  1 +
+file changed, 12 insertions(+), 4 deletions(-)
 files changed, 93 insertions(+)
  create mode 100644 docs/system/arm/nuvoton.rst
-diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@
 +Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
 +=====================================================
 +
 +The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
 +designed to be used as Baseboard Management Controllers (BMCs) in various
 +servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an
 +assortment of peripherals targeted for either Enterprise or Data Center /
 +Hyperscale applications. The former is a superset of the latter, so NPCM750 has
 +all the peripherals of NPCM730 and more.
 +
 +.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
 +
 +The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise
 +segment. The following machines are based on this chip :
 +
 +- ``npcm750-evb``       Nuvoton NPCM750 Evaluation board
 +
 +The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and
 +Hyperscale applications. The following machines are based on this chip :
 +
 +- ``quanta-gsj``        Quanta GSJ server BMC
 +
 +There are also two more SoCs, NPCM710 and NPCM705, which are single-core
 +variants of NPCM750 and NPCM730, respectively. These are currently not
 +supported by QEMU.
 +
 +Supported devices
 +-----------------
 +
 + * SMP (Dual Core Cortex-A9)
 + * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer
 +   and Watchdog.
 + * SRAM, ROM and DRAM mappings
 + * System Global Control Registers (GCR)
 + * Clock and reset controller (CLK)
 + * Timer controller (TIM)
 + * Serial ports (16550-based)
 + * DDR4 memory controller (dummy interface indicating memory training is done)
 + * OTP controllers (no protection features)
 + * Flash Interface Unit (FIU; no protection features)
 +
 +Missing devices
 +---------------
 +
 + * GPIO controller
 + * LPC/eSPI host-to-BMC interface, including
 +
 +   * Keyboard and mouse controller interface (KBCI)
 +   * Keyboard Controller Style (KCS) channels
 +   * BIOS POST code FIFO
 +   * System Wake-up Control (SWC)
 +   * Shared memory (SHM)
 +   * eSPI slave interface
 +
 + * Ethernet controllers (GMAC and EMC)
 + * USB host (USBH)
 + * USB device (USBD)
 + * SMBus controller (SMBF)
 + * Peripheral SPI controller (PSPI)
 + * Analog to Digital Converter (ADC)
 + * SD/MMC host
 + * Random Number Generator (RNG)
 + * PECI interface
 + * Pulse Width Modulation (PWM)
 + * Tachometer
 + * PCI and PCIe root complex and bridges
 + * VDM and MCTP support
 + * Serial I/O expansion
 + * LPC/eSPI host
 + * Coprocessor
 + * Graphics
 + * Video capture
 + * Encoding compression engine
 + * Security features
 +
 +Boot options
 +------------
 +
 +The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
 +a kernel using the ``-kernel`` option. OpenBMC images for `quanta-gsj` and
 +possibly others can be downloaded from the OpenPOWER jenkins :
 +
 +   https://openpower.xyz/
 +
 +The firmware image should be attached as an MTD drive. Example :
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-arm -machine quanta-gsj -nographic \
 +      -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw
 +
 +The default root password for test images is usually ``0penBmc``.
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-arm.rst
+--- a/target/arm/m_helper.c
-+++ b/docs/system/target-arm.rst
++++ b/target/arm/m_helper.c
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
-    arm/musicpal
+          * Clear registers if necessary to prevent non-secure exception
-    arm/gumstix
+          * code being able to see register values from secure code.
-    arm/nseries
+          * Where register values become architecturally UNKNOWN we leave
-+   arm/nuvoton
+-         * them with their previous values.
-    arm/orangepi
++         * them with their previous values. v8.1M is tighter than v8.0M
-    arm/palm
++         * here and always zeroes the caller-saved registers regardless
-    arm/xscale
++         * of the security state the exception is targeting.
           */
          if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 -            if (!targets_secure) {
 +            if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) {
                  /*
                   * Always clear the caller-saved registers (they have been
                   * pushed to the stack earlier in v7m_push_stack()).
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
                   * v7m_push_callee_stack()).
                   */
                  int i;
 +                /*
 +                 * r4..r11 are callee-saves, zero only if background
 +                 * state was Secure (EXCRET.S == 1) and exception
 +                 * targets Non-secure state
 +                 */
 +                bool zero_callee_saves = !targets_secure &&
 +                    (lr & R_V7M_EXCRET_S_MASK);
                  for (i = 0; i < 13; i++) {
 -                    /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
 -                    if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) {
 +                    if (i < 4 || i > 11 || zero_callee_saves) {
                          env->regs[i] = 0;
                      }
                  }
 --
 .20.1

-[PULL 30/36] hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
+[PULL 27/36] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
-From: Havard Skinnemoen <hskinnemoen@google.com>
+In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule
 R_LLRP).  (In previous versions of the architecture this was either
 required or IMPDEF.)
-When booting directly into a kernel, bypassing the boot loader, the CPU and
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-UART clocks are not set up correctly. This makes the system appear very
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-slow, and causes the initrd boot test to fail when optimization is off.
+Message-id: 20201119215617.29887-18-peter.maydell@linaro.org
 ---
  target/arm/m_helper.c | 6 +++++-
 file changed, 5 insertions(+), 1 deletion(-)
-The UART clock must run at 24 MHz. The default 25 MHz reference clock
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 cannot achieve this, so switch to PLL2/2 @ 480 MHz, which works
 perfectly with the default /20 divider.
 The CPU clock should run at 800 MHz, so switch it to PLL1/2. PLL1 runs
 at 800 MHz by default, so we need to double the feedback divider as well
 to make it run at 1600 MHz (so PLL1/2 runs at 800 MHz).
 We don't bother checking for PLL lock because we know our emulated PLLs
 lock instantly.
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-13-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/npcm7xx.h |  1 +
  hw/arm/npcm7xx.c         | 32 ++++++++++++++++++++++++++++++++
 files changed, 33 insertions(+)
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/npcm7xx.h
+--- a/target/arm/m_helper.c
-+++ b/include/hw/arm/npcm7xx.h
++++ b/target/arm/m_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ load_fail:
- #define NPCM7XX_SMP_LOADER_START        (0xffff0000)  /* Boot ROM */
+      * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
- #define NPCM7XX_SMP_BOOTREG_ADDR        (0xf080013c)  /* GCR.SCRPAD */
+      * secure); otherwise it targets the same security state as the
- #define NPCM7XX_GIC_CPU_IF_ADDR         (0xf03fe100)  /* GIC within A9 */
+      * underlying exception.
-+#define NPCM7XX_BOARD_SETUP_ADDR        (0xffff1000)  /* Boot ROM */
++     * In v8.1M HardFaults from vector table fetch fails don't set FORCED.
+      */
- typedef struct NPCM7xxMachine {
+     if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
-     MachineState        parent;
+         exc_secure = true;
-diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
+     }
-index XXXXXXX..XXXXXXX 100644
+-    env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
---- a/hw/arm/npcm7xx.c
++    env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK;
-+++ b/hw/arm/npcm7xx.c
++    if (!arm_feature(env, ARM_FEATURE_V8_1M)) {
-@@ -XXX,XX +XXX,XX @@
++        env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
  #define NPCM7XX_ROM_BA          (0xffff0000)
  #define NPCM7XX_ROM_SZ          (64 * KiB)
 +/* Clock configuration values to be fixed up when bypassing bootloader */
 +
 +/* Run PLL1 at 1600 MHz */
 +#define NPCM7XX_PLLCON1_FIXUP_VAL   (0x00402101)
 +/* Run the CPU from PLL1 and UART from PLL2 */
 +#define NPCM7XX_CLKSEL_FIXUP_VAL    (0x004aaba9)
 +
  /*
   * Interrupt lines going into the GIC. This does not include internal Cortex-A9
   * interrupts.
@@ -XXX,XX +XXX,XX @@ static const struct {
      },
  };
 +static void npcm7xx_write_board_setup(ARMCPU *cpu,
 +                                      const struct arm_boot_info *info)
 +{
 +    uint32_t board_setup[] = {
 +        0xe59f0010,     /* ldr r0, clk_base_addr */
 +        0xe59f1010,     /* ldr r1, pllcon1_value */
 +        0xe5801010,     /* str r1, [r0, #16] */
 +        0xe59f100c,     /* ldr r1, clksel_value */
 +        0xe5801004,     /* str r1, [r0, #4] */
 +        0xe12fff1e,     /* bx lr */
 +        NPCM7XX_CLK_BA,
 +        NPCM7XX_PLLCON1_FIXUP_VAL,
 +        NPCM7XX_CLKSEL_FIXUP_VAL,
 +    };
 +    int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(board_setup); i++) {
 +        board_setup[i] = tswap32(board_setup[i]);
 +    }
-+    rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup),
+     armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
-+                       info->board_setup_addr);
+     return false;
-+}
+ }
 +
  static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
                                           const struct arm_boot_info *info)
  {
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info npcm7xx_binfo = {
      .gic_cpu_if_addr        = NPCM7XX_GIC_CPU_IF_ADDR,
      .write_secondary_boot   = npcm7xx_write_secondary_boot,
      .board_id               = -1,
 +    .board_setup_addr       = NPCM7XX_BOARD_SETUP_ADDR,
 +    .write_board_setup      = npcm7xx_write_board_setup,
  };
  void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
 --
 .20.1

-[PULL 24/36] roms: Add virtual Boot ROM for NPCM7xx SoCs
+[PULL 28/36] target/arm: Implement v8.1M REVIDR register
-From: Havard Skinnemoen <hskinnemoen@google.com>
+In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc
 and is a read-only IMPDEF register providing implementation specific
 minor revision information, like the v8A REVIDR_EL1. Implement this.
-This is a minimalistic boot ROM written specifically for use with QEMU.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-It supports loading the second-stage loader from SPI flash into RAM, SMP
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-boot, and not much else.
+Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
 ---
  hw/intc/armv7m_nvic.c | 5 +++++
 file changed, 5 insertions(+)
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-7-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  .gitmodules                 |   3 +++
  MAINTAINERS                 |   2 ++
  pc-bios/README              |   6 ++++++
  pc-bios/meson.build         |   1 +
  pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
  roms/Makefile               |   7 +++++++
  roms/vbootrom               |   1 +
 files changed, 20 insertions(+)
  create mode 100644 pc-bios/npcm7xx_bootrom.bin
  create mode 160000 roms/vbootrom
 diff --git a/.gitmodules b/.gitmodules
 index XXXXXXX..XXXXXXX 100644
---- a/.gitmodules
+--- a/hw/intc/armv7m_nvic.c
-+++ b/.gitmodules
++++ b/hw/intc/armv7m_nvic.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
- [submodule "meson"]
+         }
-     path = meson
+         return val;
-     url = https://github.com/mesonbuild/meson/
+     }
-+[submodule "roms/vbootrom"]
++    case 0xcfc:
-+    path = roms/vbootrom
++        if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) {
-+    url = https://github.com/google/vbootrom.git
++            goto bad_offset;
-diff --git a/MAINTAINERS b/MAINTAINERS
++        }
-index XXXXXXX..XXXXXXX 100644
++        return cpu->revidr;
---- a/MAINTAINERS
+     case 0xd00: /* CPUID Base.  */
-+++ b/MAINTAINERS
+         return cpu->midr;
-@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
+     case 0xd04: /* Interrupt Control State (ICSR) */
  S: Supported
  F: hw/*/npcm7xx*
  F: include/hw/*/npcm7xx*
 +F: pc-bios/npcm7xx_bootrom.bin
 +F: roms/vbootrom
  nSeries
  M: Andrzej Zaborowski <balrogg@gmail.com>
 diff --git a/pc-bios/README b/pc-bios/README
 index XXXXXXX..XXXXXXX 100644
 --- a/pc-bios/README
 +++ b/pc-bios/README
@@ -XXX,XX +XXX,XX @@
    ("Simplified BSD License" or "FreeBSD License", SPDX: BSD-2-Clause). OpenSBI
    source code also contains code reused from other projects desribed here:
    https://github.com/riscv/opensbi/blob/master/ThirdPartyNotices.md.
 +
 +- npcm7xx_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for Nuvoton
 +  NPCM7xx BMC devices. It currently implements the bare minimum to load, parse,
 +  initialize and run boot images stored in SPI flash, but may grow more
 +  features over time as needed. The source code is available at:
 +  https://github.com/google/vbootrom
 diff --git a/pc-bios/meson.build b/pc-bios/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/pc-bios/meson.build
 +++ b/pc-bios/meson.build
@@ -XXX,XX +XXX,XX @@ blobs = files(
    'opensbi-riscv64-generic-fw_dynamic.bin',
    'opensbi-riscv32-generic-fw_dynamic.elf',
    'opensbi-riscv64-generic-fw_dynamic.elf',
 +  'npcm7xx_bootrom.bin',
  )
  if install_blobs
 diff --git a/pc-bios/npcm7xx_bootrom.bin b/pc-bios/npcm7xx_bootrom.bin
 new file mode 100644
 index XXXXXXX..XXXXXXX
 GIT binary patch
 literal 768
 zcmd5)JxClu6n-<aczPbVhZYusb8wKx;7TklHfmuZdYT9pDRLwd1p_t-DFpWpyA+8(
 zwKtZg3J4a0aCM3_X(ZL&4g;46VVk5e$K;z;L99|b@aE%v^S$rQ8)h(Vm@cB9IYc+2
 z2SHd4^NwTIGE%w>9S05p1#kf90Sj5Z(jG8}+)IZIp~iXK=T&)dL`%d-q*8aR#mq{7
 z9`=6;Dr(H0ACe72R5x?!)^86Qj-X%{+!K9iZNA@*wkBAV&iZ(l^I9?!Gz=S2I_*1d
 zr+tTQDHjvyzKnw(hu00yX`u!Fv<!~XVcX?@kr#<B0(gGU?$W{gSsQa}CF^8Cfzp2X
 z@P}yDV-bci(K9XL$FU!som2C`c)?Uc&294s^}Wzumap{hg1X^jN|V25M5tQZ=<9lN
 z%(zKz#t-qCwHKb;HygOCpvCNL_4@1tXV1YGf^XUE_$zr{g8zWh-6gz-teI(eibtxo
 z?0OZI4%rU0741PgUD`2xq@H|*4=+Rs?%N)Ox5G+q>C;DilBe_YlkeSUVHA-crNk+k
 jtiF_MudA<CB(}8|fqYwCf3re&=&@_s761P#-ID$TwgmBa
 literal 0
 HcmV?d00001
 diff --git a/roms/Makefile b/roms/Makefile
 index XXXXXXX..XXXXXXX 100644
 --- a/roms/Makefile
 +++ b/roms/Makefile
@@ -XXX,XX +XXX,XX @@ find-cross-gcc = $(firstword $(wildcard $(patsubst %ld,%gcc,$(call find-cross-ld
  # finally strip off path + toolname so we get the prefix
  find-cross-prefix = $(subst gcc,,$(notdir $(call find-cross-gcc,$(1))))
 +arm_cross_prefix := $(call find-cross-prefix,arm)
  powerpc64_cross_prefix := $(call find-cross-prefix,powerpc64)
  powerpc_cross_prefix := $(call find-cross-prefix,powerpc)
  x86_64_cross_prefix := $(call find-cross-prefix,x86_64)
@@ -XXX,XX +XXX,XX @@ default help:
      @echo "  skiboot            -- update skiboot.lid"
      @echo "  u-boot.e500        -- update u-boot.e500"
      @echo "  u-boot.sam460      -- update u-boot.sam460"
 +    @echo "  npcm7xx_bootrom    -- update vbootrom for npcm7xx"
      @echo "  efi                -- update UEFI (edk2) platform firmware"
      @echo "  opensbi32-generic  -- update OpenSBI for 32-bit generic machine"
      @echo "  opensbi64-generic  -- update OpenSBI for 64-bit generic machine"
@@ -XXX,XX +XXX,XX @@ bios-microvm:
      $(MAKE) -C qboot
      cp qboot/bios.bin ../pc-bios/bios-microvm.bin
 +npcm7xx_bootrom:
 +    $(MAKE) -C vbootrom CROSS_COMPILE=$(arm_cross_prefix)
 +    cp vbootrom/npcm7xx_bootrom.bin ../pc-bios/npcm7xx_bootrom.bin
 +
  clean:
      rm -rf seabios/.config seabios/out seabios/builds
      $(MAKE) -C sgabios clean
@@ -XXX,XX +XXX,XX @@ clean:
      $(MAKE) -f Makefile.edk2 clean
      $(MAKE) -C opensbi clean
      $(MAKE) -C qboot clean
 +    $(MAKE) -C vbootrom clean
 diff --git a/roms/vbootrom b/roms/vbootrom
 new file mode 160000
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/roms/vbootrom
@@ -0,0 +1 @@
 +Subproject commit 0c37a43527f0ee2b9584e7fb2fdc805e902635ac
 --
 .20.1

-[PULL 06/36] decodetree: Improve identifier matching
+[PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception return
-From: Richard Henderson <richard.henderson@linaro.org>
+In v8.1M a new exception return check is added which may cause a NOCP
 UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR
 we must check whether access to CP10 from the Security state of the
 returning exception is disabled; if it is then we must take a fault.
-Only argument set members have to be C identifiers, everything
+(Note that for our implementation CPPWR is always RAZ/WI and so can
-else gets prefixed during conversion to C.  Some places just
+never cause CP10 accesses to fail.)
 checked the leading character, and some places matched a leading
 character plus a C identifier.
-Convert everything to match full identifiers, including the
+The other v8.1M change to this register-clearing code is that if MVE
-[&%@&] prefix, and drop the full C identifier requirement.
+is implemented VPR must also be cleared, so add a TODO comment to
 that effect.
-Reported-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200903192334.1603773-1-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20201119215617.29887-20-peter.maydell@linaro.org
 ---
- tests/decode/succ_ident1.decode |  7 +++++
+ target/arm/m_helper.c | 22 +++++++++++++++++++++-
- scripts/decodetree.py           | 46 +++++++++++++++++++++------------
+file changed, 21 insertions(+), 1 deletion(-)
 files changed, 37 insertions(+), 16 deletions(-)
  create mode 100644 tests/decode/succ_ident1.decode
-diff --git a/tests/decode/succ_ident1.decode b/tests/decode/succ_ident1.decode
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/decode/succ_ident1.decode
@@ -XXX,XX +XXX,XX @@
 +%1f   0:8
 +%2f   8:8
 +%3f   16:8
 +
 +&3arg a b c
 +@3arg ........ ........ ........ ........  &3arg a=%1f b=%2f c=%3f
 +3insn 00000000 ........ ........ ........  @3arg
 diff --git a/scripts/decodetree.py b/scripts/decodetree.py
 index XXXXXXX..XXXXXXX 100644
---- a/scripts/decodetree.py
+--- a/target/arm/m_helper.c
-+++ b/scripts/decodetree.py
++++ b/target/arm/m_helper.c
-@@ -XXX,XX +XXX,XX @@ output_fd = None
+@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
- insntype = 'uint32_t'
+             v7m_exception_taken(cpu, excret, true, false);
- decode_function = 'decode'
+             return;
+         } else {
--re_ident = '[a-zA-Z][a-zA-Z0-9_]*'
+-            /* Clear s0..s15 and FPSCR */
-+# An identifier for C.
++            if (arm_feature(env, ARM_FEATURE_V8_1M)) {
-+re_C_ident = '[a-zA-Z][a-zA-Z0-9_]*'
++                /* v8.1M adds this NOCP check */
++                bool nsacr_pass = exc_secure ||
-+# Identifiers for Arguments, Fields, Formats and Patterns.
++                    extract32(env->v7m.nsacr, 10, 1);
-+re_arg_ident = '&[a-zA-Z0-9_]*'
++                bool cpacr_pass = v7m_cpacr_pass(env, exc_secure, true);
-+re_fld_ident = '%[a-zA-Z0-9_]*'
++                if (!nsacr_pass) {
-+re_fmt_ident = '@[a-zA-Z0-9_]*'
++                    armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true);
-+re_pat_ident = '[a-zA-Z0-9_]*'
++                    env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK;
++                    qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
- def error_with_file(file, lineno, *args):
++                        "stackframe: NSACR prevents clearing FPU registers\n");
-     """Print an error message from file:line and args and exit."""
++                    v7m_exception_taken(cpu, excret, true, false);
-@@ -XXX,XX +XXX,XX @@ class ExcMultiPattern(MultiPattern):
++                } else if (!cpacr_pass) {
- def parse_field(lineno, name, toks):
++                    armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
-     """Parse one instruction field from TOKS at LINENO"""
++                                            exc_secure);
-     global fields
++                    env->v7m.cfsr[exc_secure] |= R_V7M_CFSR_NOCP_MASK;
--    global re_ident
++                    qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
-     global insnwidth
++                        "stackframe: CPACR prevents clearing FPU registers\n");
++                    v7m_exception_taken(cpu, excret, true, false);
-     # A "simple" field will have only one entry;
++                }
-@@ -XXX,XX +XXX,XX @@ def parse_field(lineno, name, toks):
++            }
-     width = 0
++            /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemented */
-     func = None
+             int i;
-     for t in toks:
--        if re.fullmatch('!function=' + re_ident, t):
+             for (i = 0; i < 16; i += 2) {
 +        if re.match('^!function=', t):
              if func:
                  error(lineno, 'duplicate function')
              func = t.split('=')
@@ -XXX,XX +XXX,XX @@ def parse_field(lineno, name, toks):
  def parse_arguments(lineno, name, toks):
      """Parse one argument set from TOKS at LINENO"""
      global arguments
 -    global re_ident
 +    global re_C_ident
      global anyextern
      flds = []
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
              extern = True
              anyextern = True
              continue
 -        if not re.fullmatch(re_ident, t):
 +        if not re.fullmatch(re_C_ident, t):
              error(lineno, 'invalid argument set token "{0}"'.format(t))
          if t in flds:
              error(lineno, 'duplicate argument "{0}"'.format(t))
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
      global arguments
      global formats
      global allpatterns
 -    global re_ident
 +    global re_arg_ident
 +    global re_fld_ident
 +    global re_fmt_ident
 +    global re_C_ident
      global insnwidth
      global insnmask
      global variablewidth
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
      fmt = None
      for t in toks:
          # '&Foo' gives a format an explcit argument set.
 -        if t[0] == '&':
 +        if re.fullmatch(re_arg_ident, t):
              tt = t[1:]
              if arg:
                  error(lineno, 'multiple argument sets')
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
              continue
          # '@Foo' gives a pattern an explicit format.
 -        if t[0] == '@':
 +        if re.fullmatch(re_fmt_ident, t):
              tt = t[1:]
              if fmt:
                  error(lineno, 'multiple formats')
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
              continue
          # '%Foo' imports a field.
 -        if t[0] == '%':
 +        if re.fullmatch(re_fld_ident, t):
              tt = t[1:]
              flds = add_field_byname(lineno, flds, tt, tt)
              continue
          # 'Foo=%Bar' imports a field with a different name.
 -        if re.fullmatch(re_ident + '=%' + re_ident, t):
 +        if re.fullmatch(re_C_ident + '=' + re_fld_ident, t):
              (fname, iname) = t.split('=%')
              flds = add_field_byname(lineno, flds, fname, iname)
              continue
          # 'Foo=number' sets an argument field to a constant value
 -        if re.fullmatch(re_ident + '=[+-]?[0-9]+', t):
 +        if re.fullmatch(re_C_ident + '=[+-]?[0-9]+', t):
              (fname, value) = t.split('=')
              value = int(value)
              flds = add_field(lineno, flds, fname, ConstField(value))
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
              fixedmask = (fixedmask << shift) | fms
              undefmask = (undefmask << shift) | ubm
          # Otherwise, fieldname:fieldwidth
 -        elif re.fullmatch(re_ident + ':s?[0-9]+', t):
 +        elif re.fullmatch(re_C_ident + ':s?[0-9]+', t):
              (fname, flen) = t.split(':')
              sign = False
              if flen[0] == 's':
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
  def parse_file(f, parent_pat):
      """Parse all of the patterns within a file"""
 +    global re_arg_ident
 +    global re_fld_ident
 +    global re_fmt_ident
 +    global re_pat_ident
      # Read all of the lines of the file.  Concatenate lines
      # ending in backslash; discard empty lines and comments.
@@ -XXX,XX +XXX,XX @@ def parse_file(f, parent_pat):
              continue
          # Determine the type of object needing to be parsed.
 -        if name[0] == '%':
 +        if re.fullmatch(re_fld_ident, name):
              parse_field(start_lineno, name[1:], toks)
 -        elif name[0] == '&':
 +        elif re.fullmatch(re_arg_ident, name):
              parse_arguments(start_lineno, name[1:], toks)
 -        elif name[0] == '@':
 +        elif re.fullmatch(re_fmt_ident, name):
              parse_generic(start_lineno, None, name[1:], toks)
 -        else:
 +        elif re.fullmatch(re_pat_ident, name):
              parse_generic(start_lineno, parent_pat, name, toks)
 +        else:
 +            error(lineno, 'invalid token "{0}"'.format(name))
          toks = []
      if nesting != 0:
 --
 .20.1

-[PULL 28/36] hw/ssi: NPCM7xx Flash Interface Unit device model
+[PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings
-From: Havard Skinnemoen <hskinnemoen@google.com>
+v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set).
 The only difference is that:
  * the old T1 encodings UNDEF if the implementation implements 32
    Dregs (this is currently architecturally impossible for M-profile)
  * the new T2 encodings have the implementation-defined option to
    read from memory (discarding the data) or write UNKNOWN values to
    memory for the stack slots that would be D16-D31
-This implements a device model for the NPCM7xx SPI flash controller.
+We choose not to make those accesses, so for us the two
 instructions behave identically assuming they don't UNDEF.
-Direct reads and writes, and user-mode transactions have been tested in
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-various modes. Protection features are not implemented yet.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20201119215617.29887-21-peter.maydell@linaro.org
 ---
  target/arm/m-nocp.decode       |  2 +-
  target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++
 files changed, 26 insertions(+), 1 deletion(-)
-All the FIU instances are available in the SoC's address space,
+diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
 regardless of whether or not they're connected to actual flash chips.
 Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Alexander Bulekov <alxndr@bu.edu>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-11-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/npcm7xx.h     |   2 +
  include/hw/ssi/npcm7xx_fiu.h |  73 +++++
  hw/arm/npcm7xx.c             |  58 ++++
  hw/ssi/npcm7xx_fiu.c         | 572 +++++++++++++++++++++++++++++++++++
  hw/arm/Kconfig               |   1 +
  hw/ssi/meson.build           |   1 +
  hw/ssi/trace-events          |  11 +
 files changed, 718 insertions(+)
  create mode 100644 include/hw/ssi/npcm7xx_fiu.h
  create mode 100644 hw/ssi/npcm7xx_fiu.c
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/npcm7xx.h
+--- a/target/arm/m-nocp.decode
-+++ b/include/hw/arm/npcm7xx.h
++++ b/target/arm/m-nocp.decode
 @@ -XXX,XX +XXX,XX @@
- #include "hw/misc/npcm7xx_gcr.h"
- #include "hw/nvram/npcm7xx_otp.h"
+ {
- #include "hw/timer/npcm7xx_timer.h"
+   # Special cases which do not take an early NOCP: VLLDM and VLSTM
-+#include "hw/ssi/npcm7xx_fiu.h"
+-  VLLDM_VLSTM  1110 1100 001 l:1 rn:4 0000 1010 0000 0000
- #include "target/arm/cpu.h"
++  VLLDM_VLSTM  1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000
+   # VSCCLRM (new in v8.1M) is similar:
- #define NPCM7XX_MAX_NUM_CPUS    (2)
+   VSCCLRM      1110 1100 1.01 1111 .... 1011 imm:7 0   vd=%vd_dp size=3
-@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
+   VSCCLRM      1110 1100 1.01 1111 .... 1010 imm:8     vd=%vd_sp size=2
-     NPCM7xxOTPState     key_storage;
+diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
      NPCM7xxOTPState     fuse_array;
      NPCM7xxMCState      mc;
 +    NPCM7xxFIUState     fiu[2];
  } NPCM7xxState;
  #define TYPE_NPCM7XX    "npcm7xx"
 diff --git a/include/hw/ssi/npcm7xx_fiu.h b/include/hw/ssi/npcm7xx_fiu.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/ssi/npcm7xx_fiu.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx Flash Interface Unit (FIU)
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +#ifndef NPCM7XX_FIU_H
 +#define NPCM7XX_FIU_H
 +
 +#include "hw/ssi/ssi.h"
 +#include "hw/sysbus.h"
 +
 +/*
 + * Number of registers in our device state structure. Don't change this without
 + * incrementing the version_id in the vmstate.
 + */
 +#define NPCM7XX_FIU_NR_REGS (0x7c / sizeof(uint32_t))
 +
 +typedef struct NPCM7xxFIUState NPCM7xxFIUState;
 +
 +/**
 + * struct NPCM7xxFIUFlash - Per-chipselect flash controller state.
 + * @direct_access: Memory region for direct flash access.
 + * @fiu: Pointer to flash controller shared state.
 + */
 +typedef struct NPCM7xxFIUFlash {
 +    MemoryRegion direct_access;
 +    NPCM7xxFIUState *fiu;
 +} NPCM7xxFIUFlash;
 +
 +/**
 + * NPCM7xxFIUState - Device state for one Flash Interface Unit.
 + * @parent: System bus device.
 + * @mmio: Memory region for register access.
 + * @cs_count: Number of flash chips that may be connected to this module.
 + * @active_cs: Currently active chip select, or -1 if no chip is selected.
 + * @cs_lines: GPIO lines that may be wired to flash chips.
 + * @flash: Array of @cs_count per-flash-chip state objects.
 + * @spi: The SPI bus mastered by this controller.
 + * @regs: Register contents.
 + *
 + * Each FIU has a shared bank of registers, and controls up to four chip
 + * selects. Each chip select has a dedicated memory region which may be used to
 + * read and write the flash connected to that chip select as if it were memory.
 + */
 +struct NPCM7xxFIUState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion mmio;
 +
 +    int32_t cs_count;
 +    int32_t active_cs;
 +    qemu_irq *cs_lines;
 +    NPCM7xxFIUFlash *flash;
 +
 +    SSIBus *spi;
 +
 +    uint32_t regs[NPCM7XX_FIU_NR_REGS];
 +};
 +
 +#define TYPE_NPCM7XX_FIU "npcm7xx-fiu"
 +#define NPCM7XX_FIU(obj) OBJECT_CHECK(NPCM7xxFIUState, (obj), TYPE_NPCM7XX_FIU)
 +
 +#endif /* NPCM7XX_FIU_H */
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/npcm7xx.c
+--- a/target/arm/translate-vfp.c.inc
-+++ b/hw/arm/npcm7xx.c
++++ b/target/arm/translate-vfp.c.inc
-@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_uart_addr[] = {
+@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
-xf0004000,
+         !arm_dc_feature(s, ARM_FEATURE_V8)) {
- };
+         return false;
 +/* Direct memory-mapped access to SPI0 CS0-1. */
 +static const hwaddr npcm7xx_fiu0_flash_addr[] = {
 +    0x80000000, /* CS0 */
 +    0x88000000, /* CS1 */
 +};
 +
 +/* Direct memory-mapped access to SPI3 CS0-3. */
 +static const hwaddr npcm7xx_fiu3_flash_addr[] = {
 +    0xa0000000, /* CS0 */
 +    0xa8000000, /* CS1 */
 +    0xb0000000, /* CS2 */
 +    0xb8000000, /* CS3 */
 +};
 +
 +static const struct {
 +    const char *name;
 +    hwaddr regs_addr;
 +    int cs_count;
 +    const hwaddr *flash_addr;
 +} npcm7xx_fiu[] = {
 +    {
 +        .name = "fiu0",
 +        .regs_addr = 0xfb000000,
 +        .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
 +        .flash_addr = npcm7xx_fiu0_flash_addr,
 +    }, {
 +        .name = "fiu3",
 +        .regs_addr = 0xc0000000,
 +        .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
 +        .flash_addr = npcm7xx_fiu3_flash_addr,
 +    },
 +};
 +
  static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
                                           const struct arm_boot_info *info)
  {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
          object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
      }
 +
-+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
++    if (a->op) {
-+    for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
++        /*
-+        object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
++         * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
-+                                TYPE_NPCM7XX_FIU);
++         * to take the IMPDEF option to make memory accesses to the stack
-+    }
++         * slots that correspond to the D16-D31 registers (discarding
- }
++         * read data and writing UNKNOWN values), so for us the T2
++         * encoding behaves identically to the T1 encoding.
- static void npcm7xx_realize(DeviceState *dev, Error **errp)
++         */
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
++        if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
-                        serial_hd(i), DEVICE_LITTLE_ENDIAN);
++            return false;
-     }
++        }
++    } else {
-+    /*
++        /*
-+     * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
++         * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
-+     * specified, but this is a programming error.
++         * This is currently architecturally impossible, but we add the
-+     */
++         * check to stay in line with the pseudocode. Note that we must
-+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
++         * emit code for the UNDEF so it takes precedence over the NOCP.
-+    for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
++         */
-+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
++        if (dc_isar_feature(aa32_simd_r32, s)) {
-+        int j;
++            unallocated_encoding(s);
-+
++            return true;
 +        object_property_set_int(OBJECT(sbd), "cs-count",
 +                                npcm7xx_fiu[i].cs_count, &error_abort);
 +        sysbus_realize(sbd, &error_abort);
 +
 +        sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
 +        for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
 +            sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
 +        }
 +    }
 +
-     /* RAM2 (SRAM) */
+     /*
-     memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
+      * If not secure, UNDEF. We must emit code for this
-                            NPCM7XX_RAM2_SZ, &error_abort);
+      * rather than returning false so that this takes
 diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx Flash Interface Unit (FIU)
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
 +#include "qemu/osdep.h"
 +
 +#include "hw/irq.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/ssi/npcm7xx_fiu.h"
 +#include "migration/vmstate.h"
 +#include "qapi/error.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +#include "qemu/units.h"
 +
 +#include "trace.h"
 +
 +/* Up to 128 MiB of flash may be accessed directly as memory. */
 +#define NPCM7XX_FIU_FLASH_WINDOW_SIZE (128 * MiB)
 +
 +/* Each module has 4 KiB of register space. Only a fraction of it is used. */
 +#define NPCM7XX_FIU_CTRL_REGS_SIZE (4 * KiB)
 +
 +/* 32-bit FIU register indices. */
 +enum NPCM7xxFIURegister {
 +    NPCM7XX_FIU_DRD_CFG,
 +    NPCM7XX_FIU_DWR_CFG,
 +    NPCM7XX_FIU_UMA_CFG,
 +    NPCM7XX_FIU_UMA_CTS,
 +    NPCM7XX_FIU_UMA_CMD,
 +    NPCM7XX_FIU_UMA_ADDR,
 +    NPCM7XX_FIU_PRT_CFG,
 +    NPCM7XX_FIU_UMA_DW0 = 0x0020 / sizeof(uint32_t),
 +    NPCM7XX_FIU_UMA_DW1,
 +    NPCM7XX_FIU_UMA_DW2,
 +    NPCM7XX_FIU_UMA_DW3,
 +    NPCM7XX_FIU_UMA_DR0,
 +    NPCM7XX_FIU_UMA_DR1,
 +    NPCM7XX_FIU_UMA_DR2,
 +    NPCM7XX_FIU_UMA_DR3,
 +    NPCM7XX_FIU_PRT_CMD0,
 +    NPCM7XX_FIU_PRT_CMD1,
 +    NPCM7XX_FIU_PRT_CMD2,
 +    NPCM7XX_FIU_PRT_CMD3,
 +    NPCM7XX_FIU_PRT_CMD4,
 +    NPCM7XX_FIU_PRT_CMD5,
 +    NPCM7XX_FIU_PRT_CMD6,
 +    NPCM7XX_FIU_PRT_CMD7,
 +    NPCM7XX_FIU_PRT_CMD8,
 +    NPCM7XX_FIU_PRT_CMD9,
 +    NPCM7XX_FIU_CFG = 0x78 / sizeof(uint32_t),
 +    NPCM7XX_FIU_REGS_END,
 +};
 +
 +/* FIU_{DRD,DWR,UMA,PTR}_CFG cannot be written when this bit is set. */
 +#define NPCM7XX_FIU_CFG_LCK BIT(31)
 +
 +/* Direct Read configuration register fields. */
 +#define FIU_DRD_CFG_ADDSIZ(rv) extract32(rv, 16, 2)
 +#define FIU_ADDSIZ_3BYTES 0
 +#define FIU_ADDSIZ_4BYTES 1
 +#define FIU_DRD_CFG_DBW(rv) extract32(rv, 12, 2)
 +#define FIU_DRD_CFG_ACCTYPE(rv) extract32(rv, 8, 2)
 +#define FIU_DRD_CFG_RDCMD(rv) extract32(rv, 0, 8)
 +
 +/* Direct Write configuration register fields. */
 +#define FIU_DWR_CFG_ADDSIZ(rv) extract32(rv, 16, 2)
 +#define FIU_DWR_CFG_WRCMD(rv) extract32(rv, 0, 8)
 +
 +/* User-Mode Access register fields. */
 +
 +/* Command Mode Lock and the bits protected by it. */
 +#define FIU_UMA_CFG_CMMLCK BIT(30)
 +#define FIU_UMA_CFG_CMMLCK_MASK 0x00000403
 +
 +#define FIU_UMA_CFG_RDATSIZ(rv) extract32(rv, 24, 5)
 +#define FIU_UMA_CFG_DBSIZ(rv) extract32(rv, 21, 3)
 +#define FIU_UMA_CFG_WDATSIZ(rv) extract32(rv, 16, 5)
 +#define FIU_UMA_CFG_ADDSIZ(rv) extract32(rv, 11, 3)
 +#define FIU_UMA_CFG_CMDSIZ(rv) extract32(rv, 10, 1)
 +#define FIU_UMA_CFG_DBPCK(rv) extract32(rv, 6, 2)
 +
 +#define FIU_UMA_CTS_RDYIE BIT(25)
 +#define FIU_UMA_CTS_RDYST BIT(24)
 +#define FIU_UMA_CTS_SW_CS BIT(16)
 +#define FIU_UMA_CTS_DEV_NUM(rv) extract32(rv, 8, 2)
 +#define FIU_UMA_CTS_EXEC_DONE BIT(0)
 +
 +/*
 + * Returns the index of flash in the fiu->flash array. This corresponds to the
 + * chip select ID of the flash.
 + */
 +static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
 +{
 +    int index = flash - fiu->flash;
 +
 +    g_assert(index >= 0 && index < fiu->cs_count);
 +
 +    return index;
 +}
 +
 +/* Assert the chip select specified in the UMA Control/Status Register. */
 +static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id)
 +{
 +    trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id);
 +
 +    if (cs_id < s->cs_count) {
 +        qemu_irq_lower(s->cs_lines[cs_id]);
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: UMA to CS%d; this module has only %d chip selects",
 +                      DEVICE(s)->canonical_path, cs_id, s->cs_count);
 +        cs_id = -1;
 +    }
 +
 +    s->active_cs = cs_id;
 +}
 +
 +/* Deassert the currently active chip select. */
 +static void npcm7xx_fiu_deselect(NPCM7xxFIUState *s)
 +{
 +    if (s->active_cs < 0) {
 +        return;
 +    }
 +
 +    trace_npcm7xx_fiu_deselect(DEVICE(s)->canonical_path, s->active_cs);
 +
 +    qemu_irq_raise(s->cs_lines[s->active_cs]);
 +    s->active_cs = -1;
 +}
 +
 +/* Direct flash memory read handler. */
 +static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
 +                                       unsigned int size)
 +{
 +    NPCM7xxFIUFlash *f = opaque;
 +    NPCM7xxFIUState *fiu = f->fiu;
 +    uint64_t value = 0;
 +    uint32_t drd_cfg;
 +    int dummy_cycles;
 +    int i;
 +
 +    if (fiu->active_cs != -1) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: direct flash read with CS%d already active",
 +                      DEVICE(fiu)->canonical_path, fiu->active_cs);
 +    }
 +
 +    npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f));
 +
 +    drd_cfg = fiu->regs[NPCM7XX_FIU_DRD_CFG];
 +    ssi_transfer(fiu->spi, FIU_DRD_CFG_RDCMD(drd_cfg));
 +
 +    switch (FIU_DRD_CFG_ADDSIZ(drd_cfg)) {
 +    case FIU_ADDSIZ_4BYTES:
 +        ssi_transfer(fiu->spi, extract32(addr, 24, 8));
 +        /* fall through */
 +    case FIU_ADDSIZ_3BYTES:
 +        ssi_transfer(fiu->spi, extract32(addr, 16, 8));
 +        ssi_transfer(fiu->spi, extract32(addr, 8, 8));
 +        ssi_transfer(fiu->spi, extract32(addr, 0, 8));
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
 +                      DEVICE(fiu)->canonical_path, FIU_DRD_CFG_ADDSIZ(drd_cfg));
 +        break;
 +    }
 +
 +    /* Flash chip model expects one transfer per dummy bit, not byte */
 +    dummy_cycles =
 +        (FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg);
 +    for (i = 0; i < dummy_cycles; i++) {
 +        ssi_transfer(fiu->spi, 0);
 +    }
 +
 +    for (i = 0; i < size; i++) {
 +        value = deposit64(value, 8 * i, 8, ssi_transfer(fiu->spi, 0));
 +    }
 +
 +    trace_npcm7xx_fiu_flash_read(DEVICE(fiu)->canonical_path, fiu->active_cs,
 +                                 addr, size, value);
 +
 +    npcm7xx_fiu_deselect(fiu);
 +
 +    return value;
 +}
 +
 +/* Direct flash memory write handler. */
 +static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
 +                                    unsigned int size)
 +{
 +    NPCM7xxFIUFlash *f = opaque;
 +    NPCM7xxFIUState *fiu = f->fiu;
 +    uint32_t dwr_cfg;
 +    int cs_id;
 +    int i;
 +
 +    if (fiu->active_cs != -1) {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: direct flash write with CS%d already active",
 +                      DEVICE(fiu)->canonical_path, fiu->active_cs);
 +    }
 +
 +    cs_id = npcm7xx_fiu_cs_index(fiu, f);
 +    trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
 +                                  size, v);
 +    npcm7xx_fiu_select(fiu, cs_id);
 +
 +    dwr_cfg = fiu->regs[NPCM7XX_FIU_DWR_CFG];
 +    ssi_transfer(fiu->spi, FIU_DWR_CFG_WRCMD(dwr_cfg));
 +
 +    switch (FIU_DWR_CFG_ADDSIZ(dwr_cfg)) {
 +    case FIU_ADDSIZ_4BYTES:
 +        ssi_transfer(fiu->spi, extract32(addr, 24, 8));
 +        /* fall through */
 +    case FIU_ADDSIZ_3BYTES:
 +        ssi_transfer(fiu->spi, extract32(addr, 16, 8));
 +        ssi_transfer(fiu->spi, extract32(addr, 8, 8));
 +        ssi_transfer(fiu->spi, extract32(addr, 0, 8));
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
 +                      DEVICE(fiu)->canonical_path, FIU_DWR_CFG_ADDSIZ(dwr_cfg));
 +        break;
 +    }
 +
 +    for (i = 0; i < size; i++) {
 +        ssi_transfer(fiu->spi, extract64(v, i * 8, 8));
 +    }
 +
 +    npcm7xx_fiu_deselect(fiu);
 +}
 +
 +static const MemoryRegionOps npcm7xx_fiu_flash_ops = {
 +    .read = npcm7xx_fiu_flash_read,
 +    .write = npcm7xx_fiu_flash_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 1,
 +        .max_access_size = 8,
 +        .unaligned = true,
 +    },
 +};
 +
 +/* Control register read handler. */
 +static uint64_t npcm7xx_fiu_ctrl_read(void *opaque, hwaddr addr,
 +                                      unsigned int size)
 +{
 +    hwaddr reg = addr / sizeof(uint32_t);
 +    NPCM7xxFIUState *s = opaque;
 +    uint32_t value;
 +
 +    if (reg < NPCM7XX_FIU_NR_REGS) {
 +        value = s->regs[reg];
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: read from invalid offset 0x%" PRIx64 "\n",
 +                      DEVICE(s)->canonical_path, addr);
 +        value = 0;
 +    }
 +
 +    trace_npcm7xx_fiu_ctrl_read(DEVICE(s)->canonical_path, addr, value);
 +
 +    return value;
 +}
 +
 +/* Send the specified number of address bytes from the UMA address register. */
 +static void send_address(SSIBus *spi, unsigned int addsiz, uint32_t addr)
 +{
 +    switch (addsiz) {
 +    case 4:
 +        ssi_transfer(spi, extract32(addr, 24, 8));
 +        /* fall through */
 +    case 3:
 +        ssi_transfer(spi, extract32(addr, 16, 8));
 +        /* fall through */
 +    case 2:
 +        ssi_transfer(spi, extract32(addr, 8, 8));
 +        /* fall through */
 +    case 1:
 +        ssi_transfer(spi, extract32(addr, 0, 8));
 +        /* fall through */
 +    case 0:
 +        break;
 +    }
 +}
 +
 +/* Send the number of dummy bits specified in the UMA config register. */
 +static void send_dummy_bits(SSIBus *spi, uint32_t uma_cfg, uint32_t uma_cmd)
 +{
 +    unsigned int bits_per_clock = 1U << FIU_UMA_CFG_DBPCK(uma_cfg);
 +    unsigned int i;
 +
 +    for (i = 0; i < FIU_UMA_CFG_DBSIZ(uma_cfg); i++) {
 +        /* Use bytes 0 and 1 first, then keep repeating byte 2 */
 +        unsigned int field = (i < 2) ? ((i + 1) * 8) : 24;
 +        unsigned int j;
 +
 +        for (j = 0; j < 8; j += bits_per_clock) {
 +            ssi_transfer(spi, extract32(uma_cmd, field + j, bits_per_clock));
 +        }
 +    }
 +}
 +
 +/* Perform a User-Mode Access transaction. */
 +static void npcm7xx_fiu_uma_transaction(NPCM7xxFIUState *s)
 +{
 +    uint32_t uma_cts = s->regs[NPCM7XX_FIU_UMA_CTS];
 +    uint32_t uma_cfg;
 +    unsigned int i;
 +
 +    /* SW_CS means the CS is already forced low, so don't touch it. */
 +    if (uma_cts & FIU_UMA_CTS_SW_CS) {
 +        int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]);
 +        npcm7xx_fiu_select(s, cs_id);
 +    }
 +
 +    /* Send command, if present. */
 +    uma_cfg = s->regs[NPCM7XX_FIU_UMA_CFG];
 +    if (FIU_UMA_CFG_CMDSIZ(uma_cfg) > 0) {
 +        ssi_transfer(s->spi, extract32(s->regs[NPCM7XX_FIU_UMA_CMD], 0, 8));
 +    }
 +
 +    /* Send address, if present. */
 +    send_address(s->spi, FIU_UMA_CFG_ADDSIZ(uma_cfg),
 +                 s->regs[NPCM7XX_FIU_UMA_ADDR]);
 +
 +    /* Write data, if present. */
 +    for (i = 0; i < FIU_UMA_CFG_WDATSIZ(uma_cfg); i++) {
 +        unsigned int reg =
 +            (i < 16) ? (NPCM7XX_FIU_UMA_DW0 + i / 4) : NPCM7XX_FIU_UMA_DW3;
 +        unsigned int field = (i % 4) * 8;
 +
 +        ssi_transfer(s->spi, extract32(s->regs[reg], field, 8));
 +    }
 +
 +    /* Send dummy bits, if present. */
 +    send_dummy_bits(s->spi, uma_cfg, s->regs[NPCM7XX_FIU_UMA_CMD]);
 +
 +    /* Read data, if present. */
 +    for (i = 0; i < FIU_UMA_CFG_RDATSIZ(uma_cfg); i++) {
 +        unsigned int reg = NPCM7XX_FIU_UMA_DR0 + i / 4;
 +        unsigned int field = (i % 4) * 8;
 +        uint8_t c;
 +
 +        c = ssi_transfer(s->spi, 0);
 +        if (reg <= NPCM7XX_FIU_UMA_DR3) {
 +            s->regs[reg] = deposit32(s->regs[reg], field, 8, c);
 +        }
 +    }
 +
 +    /* Again, don't touch CS if the user is forcing it low. */
 +    if (uma_cts & FIU_UMA_CTS_SW_CS) {
 +        npcm7xx_fiu_deselect(s);
 +    }
 +
 +    /* RDYST means a command has completed since it was cleared. */
 +    s->regs[NPCM7XX_FIU_UMA_CTS] |= FIU_UMA_CTS_RDYST;
 +    /* EXEC_DONE means Execute Command / Not Done, so clear it here. */
 +    s->regs[NPCM7XX_FIU_UMA_CTS] &= ~FIU_UMA_CTS_EXEC_DONE;
 +}
 +
 +/* Control register write handler. */
 +static void npcm7xx_fiu_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
 +                                   unsigned int size)
 +{
 +    hwaddr reg = addr / sizeof(uint32_t);
 +    NPCM7xxFIUState *s = opaque;
 +    uint32_t value = v;
 +
 +    trace_npcm7xx_fiu_ctrl_write(DEVICE(s)->canonical_path, addr, value);
 +
 +    switch (reg) {
 +    case NPCM7XX_FIU_UMA_CFG:
 +        if (s->regs[reg] & FIU_UMA_CFG_CMMLCK) {
 +            value &= ~FIU_UMA_CFG_CMMLCK_MASK;
 +            value |= (s->regs[reg] & FIU_UMA_CFG_CMMLCK_MASK);
 +        }
 +        /* fall through */
 +    case NPCM7XX_FIU_DRD_CFG:
 +    case NPCM7XX_FIU_DWR_CFG:
 +        if (s->regs[reg] & NPCM7XX_FIU_CFG_LCK) {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "%s: write to locked register @ 0x%" PRIx64 "\n",
 +                          DEVICE(s)->canonical_path, addr);
 +            return;
 +        }
 +        s->regs[reg] = value;
 +        break;
 +
 +    case NPCM7XX_FIU_UMA_CTS:
 +        if (value & FIU_UMA_CTS_RDYST) {
 +            value &= ~FIU_UMA_CTS_RDYST;
 +        } else {
 +            value |= s->regs[reg] & FIU_UMA_CTS_RDYST;
 +        }
 +        if ((s->regs[reg] ^ value) & FIU_UMA_CTS_SW_CS) {
 +            if (value & FIU_UMA_CTS_SW_CS) {
 +                /*
 +                 * Don't drop CS if there's a transfer in progress, or we're
 +                 * about to start one.
 +                 */
 +                if (!((value | s->regs[reg]) & FIU_UMA_CTS_EXEC_DONE)) {
 +                    npcm7xx_fiu_deselect(s);
 +                }
 +            } else {
 +                int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]);
 +                npcm7xx_fiu_select(s, cs_id);
 +            }
 +        }
 +        s->regs[reg] = value | (s->regs[reg] & FIU_UMA_CTS_EXEC_DONE);
 +        if (value & FIU_UMA_CTS_EXEC_DONE) {
 +            npcm7xx_fiu_uma_transaction(s);
 +        }
 +        break;
 +
 +    case NPCM7XX_FIU_UMA_DR0 ... NPCM7XX_FIU_UMA_DR3:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: write to read-only register @ 0x%" PRIx64 "\n",
 +                      DEVICE(s)->canonical_path, addr);
 +        return;
 +
 +    case NPCM7XX_FIU_PRT_CFG:
 +    case NPCM7XX_FIU_PRT_CMD0 ... NPCM7XX_FIU_PRT_CMD9:
 +        qemu_log_mask(LOG_UNIMP, "%s: PRT is not implemented\n", __func__);
 +        break;
 +
 +    case NPCM7XX_FIU_UMA_CMD:
 +    case NPCM7XX_FIU_UMA_ADDR:
 +    case NPCM7XX_FIU_UMA_DW0 ... NPCM7XX_FIU_UMA_DW3:
 +    case NPCM7XX_FIU_CFG:
 +        s->regs[reg] = value;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: write to invalid offset 0x%" PRIx64 "\n",
 +                      DEVICE(s)->canonical_path, addr);
 +        return;
 +    }
 +}
 +
 +static const MemoryRegionOps npcm7xx_fiu_ctrl_ops = {
 +    .read = npcm7xx_fiu_ctrl_read,
 +    .write = npcm7xx_fiu_ctrl_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +        .unaligned = false,
 +    },
 +};
 +
 +static void npcm7xx_fiu_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
 +
 +    trace_npcm7xx_fiu_enter_reset(DEVICE(obj)->canonical_path, type);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    s->regs[NPCM7XX_FIU_DRD_CFG] = 0x0300100b;
 +    s->regs[NPCM7XX_FIU_DWR_CFG] = 0x03000002;
 +    s->regs[NPCM7XX_FIU_UMA_CFG] = 0x00000400;
 +    s->regs[NPCM7XX_FIU_UMA_CTS] = 0x00010000;
 +    s->regs[NPCM7XX_FIU_UMA_CMD] = 0x0000000b;
 +    s->regs[NPCM7XX_FIU_PRT_CFG] = 0x00000400;
 +    s->regs[NPCM7XX_FIU_CFG] = 0x0000000b;
 +}
 +
 +static void npcm7xx_fiu_hold_reset(Object *obj)
 +{
 +    NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
 +    int i;
 +
 +    trace_npcm7xx_fiu_hold_reset(DEVICE(obj)->canonical_path);
 +
 +    for (i = 0; i < s->cs_count; i++) {
 +        qemu_irq_raise(s->cs_lines[i]);
 +    }
 +}
 +
 +static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
 +{
 +    NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
 +    SysBusDevice *sbd = &s->parent;
 +    int i;
 +
 +    if (s->cs_count <= 0) {
 +        error_setg(errp, "%s: %d chip selects specified, need at least one",
 +                   dev->canonical_path, s->cs_count);
 +        return;
 +    }
 +
 +    s->spi = ssi_create_bus(dev, "spi");
 +    s->cs_lines = g_new0(qemu_irq, s->cs_count);
 +    qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", s->cs_count);
 +    s->flash = g_new0(NPCM7xxFIUFlash, s->cs_count);
 +
 +    /*
 +     * Register the control registers region first. It may be followed by one
 +     * or more direct flash access regions.
 +     */
 +    memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_fiu_ctrl_ops, s, "ctrl",
 +                          NPCM7XX_FIU_CTRL_REGS_SIZE);
 +    sysbus_init_mmio(sbd, &s->mmio);
 +
 +    for (i = 0; i < s->cs_count; i++) {
 +        NPCM7xxFIUFlash *flash = &s->flash[i];
 +        flash->fiu = s;
 +        memory_region_init_io(&flash->direct_access, OBJECT(s),
 +                              &npcm7xx_fiu_flash_ops, &s->flash[i], "flash",
 +                              NPCM7XX_FIU_FLASH_WINDOW_SIZE);
 +        sysbus_init_mmio(sbd, &flash->direct_access);
 +    }
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_fiu = {
 +    .name = "npcm7xx-fiu",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_INT32(active_cs, NPCM7xxFIUState),
 +        VMSTATE_UINT32_ARRAY(regs, NPCM7xxFIUState, NPCM7XX_FIU_NR_REGS),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static Property npcm7xx_fiu_properties[] = {
 +    DEFINE_PROP_INT32("cs-count", NPCM7xxFIUState, cs_count, 0),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void npcm7xx_fiu_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    QEMU_BUILD_BUG_ON(NPCM7XX_FIU_REGS_END > NPCM7XX_FIU_NR_REGS);
 +
 +    dc->desc = "NPCM7xx Flash Interface Unit";
 +    dc->realize = npcm7xx_fiu_realize;
 +    dc->vmsd = &vmstate_npcm7xx_fiu;
 +    rc->phases.enter = npcm7xx_fiu_enter_reset;
 +    rc->phases.hold = npcm7xx_fiu_hold_reset;
 +    device_class_set_props(dc, npcm7xx_fiu_properties);
 +}
 +
 +static const TypeInfo npcm7xx_fiu_types[] = {
 +    {
 +        .name = TYPE_NPCM7XX_FIU,
 +        .parent = TYPE_SYS_BUS_DEVICE,
 +        .instance_size = sizeof(NPCM7xxFIUState),
 +        .class_init = npcm7xx_fiu_class_init,
 +    },
 +};
 +DEFINE_TYPES(npcm7xx_fiu_types);
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config NPCM7XX
      select ARM_GIC
      select PL310  # cache controller
      select SERIAL
 +    select SSI
      select UNIMP
  config FSL_IMX25
 diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/ssi/meson.build
 +++ b/hw/ssi/meson.build
@@ -XXX,XX +XXX,XX @@
  softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
  softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
 +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
  softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
  softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_SPI', if_true: files('stm32f2xx_spi.c'))
 diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/ssi/trace-events
 +++ b/hw/ssi/trace-events
@@ -XXX,XX +XXX,XX @@ aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
  aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%08x size:0x%08x"
  aspeed_smc_write(uint64_t addr,  uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
  aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
 +
 +# npcm7xx_fiu.c
 +
 +npcm7xx_fiu_enter_reset(const char *id, int reset_type) "%s reset type: %d"
 +npcm7xx_fiu_hold_reset(const char *id) "%s"
 +npcm7xx_fiu_select(const char *id, int cs) "%s select CS%d"
 +npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d"
 +npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 +npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 +npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 --
 .20.1

-[PULL 05/36] hw/timer/armv7m_systick: assert that board code set system_clock_scale
+[PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
-It is the responsibility of board code for an armv7m system to set
+v8.1M introduces a new TRD flag in the CCR register, which enables
-system_clock_scale appropriately for the CPU speed of the core.
+checking for stack frame integrity signatures on SG instructions.
-If it forgets to do this, then QEMU will hang if the guest tries
+This bit is not banked, and is always RAZ/WI to Non-secure code.
-to use the systick timer in the "tick at the CPU clock frequency" mode.
+Adjust the code for handling CCR reads and writes to handle this.
 We forgot that in a couple of our boards (see commits ce4f70e81ed23c93f,
 e7e5a9595ab1136). Add an assertion in the systick reset method so
 we don't let any new boards in with the same bug.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200825160847.18091-1-peter.maydell@linaro.org
+Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
 ---
- hw/timer/armv7m_systick.c | 8 ++++++++
+ target/arm/cpu.h      |  2 ++
-file changed, 8 insertions(+)
+ hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++--------
 files changed, 20 insertions(+), 8 deletions(-)
-diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/armv7m_systick.c
+--- a/target/arm/cpu.h
-+++ b/hw/timer/armv7m_systick.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void systick_reset(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
- {
+ FIELD(V7M_CCR, DC, 16, 1)
-     SysTickState *s = SYSTICK(dev);
+ FIELD(V7M_CCR, IC, 17, 1)
+ FIELD(V7M_CCR, BP, 18, 1)
-+    /*
++FIELD(V7M_CCR, LOB, 19, 1)
-+     * Forgetting to set system_clock_scale is always a board code
++FIELD(V7M_CCR, TRD, 20, 1)
-+     * bug. We can't check this earlier because for some boards
-+     * (like stellaris) it is not yet configured at the point where
+ /* V7M SCR bits */
-+     * the systick device is realized.
+ FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
-+     */
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
-+    assert(system_clock_scale != 0);
+index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
          }
          return cpu->env.v7m.scr[attrs.secure];
      case 0xd14: /* Configuration Control.  */
 -        /* The BFHFNMIGN bit is the only non-banked bit; we
 -         * keep it in the non-secure copy of the register.
 +        /*
 +         * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register)
 +         * and TRD (stored in the S copy of the register)
           */
          val = cpu->env.v7m.ccr[attrs.secure];
          val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
          cpu->env.v7m.scr[attrs.secure] = value;
          break;
      case 0xd14: /* Configuration Control.  */
 +    {
 +        uint32_t mask;
 +
-     s->control = 0;
+         if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
-     s->reload = 0;
+             goto bad_offset;
-     s->tick = 0;
+         }
          /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
 -        value &= (R_V7M_CCR_STKALIGN_MASK |
 -                  R_V7M_CCR_BFHFNMIGN_MASK |
 -                  R_V7M_CCR_DIV_0_TRP_MASK |
 -                  R_V7M_CCR_UNALIGN_TRP_MASK |
 -                  R_V7M_CCR_USERSETMPEND_MASK |
 -                  R_V7M_CCR_NONBASETHRDENA_MASK);
 +        mask = R_V7M_CCR_STKALIGN_MASK |
 +            R_V7M_CCR_BFHFNMIGN_MASK |
 +            R_V7M_CCR_DIV_0_TRP_MASK |
 +            R_V7M_CCR_UNALIGN_TRP_MASK |
 +            R_V7M_CCR_USERSETMPEND_MASK |
 +            R_V7M_CCR_NONBASETHRDENA_MASK;
 +        if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) {
 +            /* TRD is always RAZ/WI from NS */
 +            mask |= R_V7M_CCR_TRD_MASK;
 +        }
 +        value &= mask;
          if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
              /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
          cpu->env.v7m.ccr[attrs.secure] = value;
          break;
 +    }
      case 0xd24: /* System Handler Control and State (SHCSR) */
          if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
              goto bad_offset;
 --
 .20.1

-[PULL 26/36] hw/nvram: NPCM7xx OTP device model
+[PULL 32/36] target/arm: Implement CCR_S.TRD behaviour for SG insns
-From: Havard Skinnemoen <hskinnemoen@google.com>
+v8.1M introduces a new TRD flag in the CCR register, which enables
 checking for stack frame integrity signatures on SG instructions.
 Add the code in the SG insn implementation for the new behaviour.
-This supports reading and writing OTP fuses and keys. Only fuse reading
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-has been tested. Protection is not implemented.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20201119215617.29887-24-peter.maydell@linaro.org
 ---
  target/arm/m_helper.c | 86 +++++++++++++++++++++++++++++++++++++++++++
 file changed, 86 insertions(+)
-Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Alexander Bulekov <alxndr@bu.edu>
 Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
 Message-id: 20200911052101.2602693-9-hskinnemoen@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/npcm7xx.h       |   3 +
  include/hw/nvram/npcm7xx_otp.h |  79 ++++++
  hw/arm/npcm7xx.c               |  29 +++
  hw/nvram/npcm7xx_otp.c         | 440 +++++++++++++++++++++++++++++++++
  hw/nvram/meson.build           |   1 +
 files changed, 552 insertions(+)
  create mode 100644 include/hw/nvram/npcm7xx_otp.h
  create mode 100644 hw/nvram/npcm7xx_otp.c
 diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/npcm7xx.h
+--- a/target/arm/m_helper.c
-+++ b/include/hw/arm/npcm7xx.h
++++ b/target/arm/m_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
- #include "hw/cpu/a9mpcore.h"
+     return true;
  #include "hw/misc/npcm7xx_clk.h"
  #include "hw/misc/npcm7xx_gcr.h"
 +#include "hw/nvram/npcm7xx_otp.h"
  #include "hw/timer/npcm7xx_timer.h"
  #include "target/arm/cpu.h"
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
      NPCM7xxGCRState     gcr;
      NPCM7xxCLKState     clk;
      NPCM7xxTimerCtrlState tim[3];
 +    NPCM7xxOTPState     key_storage;
 +    NPCM7xxOTPState     fuse_array;
  } NPCM7xxState;
  #define TYPE_NPCM7XX    "npcm7xx"
 diff --git a/include/hw/nvram/npcm7xx_otp.h b/include/hw/nvram/npcm7xx_otp.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/nvram/npcm7xx_otp.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx OTP (Fuse Array) Interface
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +#ifndef NPCM7XX_OTP_H
 +#define NPCM7XX_OTP_H
 +
 +#include "exec/memory.h"
 +#include "hw/sysbus.h"
 +
 +/* Each OTP module holds 8192 bits of one-time programmable storage */
 +#define NPCM7XX_OTP_ARRAY_BITS (8192)
 +#define NPCM7XX_OTP_ARRAY_BYTES (NPCM7XX_OTP_ARRAY_BITS / BITS_PER_BYTE)
 +
 +/* Fuse array offsets */
 +#define NPCM7XX_FUSE_FUSTRAP (0)
 +#define NPCM7XX_FUSE_CP_FUSTRAP (12)
 +#define NPCM7XX_FUSE_DAC_CALIB (16)
 +#define NPCM7XX_FUSE_ADC_CALIB (24)
 +#define NPCM7XX_FUSE_DERIVATIVE (64)
 +#define NPCM7XX_FUSE_TEST_SIG (72)
 +#define NPCM7XX_FUSE_DIE_LOCATION (74)
 +#define NPCM7XX_FUSE_GP1 (80)
 +#define NPCM7XX_FUSE_GP2 (128)
 +
 +/*
 + * Number of registers in our device state structure. Don't change this without
 + * incrementing the version_id in the vmstate.
 + */
 +#define NPCM7XX_OTP_NR_REGS (0x18 / sizeof(uint32_t))
 +
 +/**
 + * struct NPCM7xxOTPState - Device state for one OTP module.
 + * @parent: System bus device.
 + * @mmio: Memory region through which registers are accessed.
 + * @regs: Register contents.
 + * @array: OTP storage array.
 + */
 +typedef struct NPCM7xxOTPState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion mmio;
 +    uint32_t regs[NPCM7XX_OTP_NR_REGS];
 +    uint8_t array[NPCM7XX_OTP_ARRAY_BYTES];
 +} NPCM7xxOTPState;
 +
 +#define TYPE_NPCM7XX_OTP "npcm7xx-otp"
 +#define NPCM7XX_OTP(obj) OBJECT_CHECK(NPCM7xxOTPState, (obj), TYPE_NPCM7XX_OTP)
 +
 +#define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
 +#define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
 +
 +typedef struct NPCM7xxOTPClass NPCM7xxOTPClass;
 +
 +/**
 + * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
 + * @s: OTP module.
 + * @data: Data to be encoded and written.
 + * @offset: Offset of first byte to be written in the OTP array.
 + * @len: Number of bytes before ECC encoding.
 + *
 + * Each nibble of data is encoded into a byte, so the number of bytes written
 + * to the array will be @len * 2.
 + */
 +extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
 +                                    unsigned int offset, unsigned int len);
 +
 +#endif /* NPCM7XX_OTP_H */
 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/npcm7xx.c
 +++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
  #define NPCM7XX_MMIO_BA         (0x80000000)
  #define NPCM7XX_MMIO_SZ         (0x7ffd0000)
 +/* OTP key storage and fuse strap array */
 +#define NPCM7XX_OTP1_BA         (0xf0189000)
 +#define NPCM7XX_OTP2_BA         (0xf018a000)
 +
  /* Core system modules. */
  #define NPCM7XX_L2C_BA          (0xf03fc000)
  #define NPCM7XX_CPUP_BA         (0xf03fe000)
@@ -XXX,XX +XXX,XX @@ void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
      arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
  }
-+static void npcm7xx_init_fuses(NPCM7xxState *s)
++static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
 +                                   uint32_t addr, uint32_t *spdata)
 +{
-+    NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
++    /*
 +     * Read a word of data from the stack for the SG instruction,
 +     * writing the value into *spdata. If the load succeeds, return
 +     * true; otherwise pend an appropriate exception and return false.
 +     * (We can't use data load helpers here that throw an exception
 +     * because of the context we're called in, which is halfway through
 +     * arm_v7m_cpu_do_interrupt().)
 +     */
 +    CPUState *cs = CPU(cpu);
 +    CPUARMState *env = &cpu->env;
 +    MemTxAttrs attrs = {};
 +    MemTxResult txres;
 +    target_ulong page_size;
 +    hwaddr physaddr;
 +    int prot;
 +    ARMMMUFaultInfo fi = {};
 +    ARMCacheAttrs cacheattrs = {};
 +    uint32_t value;
 +
-+    /*
++    if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
-+     * The initial mask of disabled modules indicates the chip derivative (e.g.
++                      &attrs, &prot, &page_size, &fi, &cacheattrs)) {
-+     * NPCM750 or NPCM730).
++        /* MPU/SAU lookup failed */
-+     */
++        if (fi.type == ARMFault_QEMU_SFault) {
-+    value = tswap32(nc->disabled_modules);
++            qemu_log_mask(CPU_LOG_INT,
-+    npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
++                          "...SecureFault during stack word read\n");
-+                            sizeof(value));
++            env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK;
 +            env->v7m.sfar = addr;
 +            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
 +        } else {
 +            qemu_log_mask(CPU_LOG_INT,
 +                          "...MemManageFault during stack word read\n");
 +            env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_DACCVIOL_MASK |
 +                R_V7M_CFSR_MMARVALID_MASK;
 +            env->v7m.mmfar[M_REG_S] = addr;
 +            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false);
 +        }
 +        return false;
 +    }
 +    value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
 +                              attrs, &txres);
 +    if (txres != MEMTX_OK) {
 +        /* BusFault trying to read the data */
 +        qemu_log_mask(CPU_LOG_INT,
 +                      "...BusFault during stack word read\n");
 +        env->v7m.cfsr[M_REG_NS] |=
 +            (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
 +        env->v7m.bfar = addr;
 +        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
 +        return false;
 +    }
 +
 +    *spdata = value;
 +    return true;
 +}
 +
- static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
+ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
  {
-     return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
+     /*
-@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
-     object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
+      */
-                               "power-on-straps");
+     qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
-     object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
+                   ", executing it\n", env->regs[15]);
 +    object_initialize_child(obj, "otp1", &s->key_storage,
 +                            TYPE_NPCM7XX_KEY_STORAGE);
 +    object_initialize_child(obj, "otp2", &s->fuse_array,
 +                            TYPE_NPCM7XX_FUSE_ARRAY);
      for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
          object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
      sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
 +    /* OTP key storage and fuse strap array. Cannot fail. */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
 +    npcm7xx_init_fuses(s);
 +
-     /* Timer Modules (TIM). Cannot fail. */
++    if (cpu_isar_feature(aa32_m_sec_state, cpu) &&
-     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
++        !arm_v7m_is_handler_mode(env)) {
-     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
++        /*
-diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
++         * v8.1M exception stack frame integrity check. Note that we
-new file mode 100644
++         * must perform the memory access even if CCR_S.TRD is zero
-index XXXXXXX..XXXXXXX
++         * and we aren't going to check what the data loaded is.
---- /dev/null
++         */
-+++ b/hw/nvram/npcm7xx_otp.c
++        uint32_t spdata, sp;
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Nuvoton NPCM7xx OTP (Fuse Array) Interface
 + *
 + * Copyright 2020 Google LLC
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License as published by the
 + * Free Software Foundation; either version 2 of the License, or
 + * (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 + * for more details.
 + */
 +
-+#include "qemu/osdep.h"
++        /*
 +         * We know we are currently NS, so the S stack pointers must be
 +         * in other_ss_{psp,msp}, not in regs[13]/other_sp.
 +         */
 +        sp = v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other_ss_msp;
 +        if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) {
 +            /* Stack access failed and an exception has been pended */
 +            return false;
 +        }
 +
-+#include "hw/nvram/npcm7xx_otp.h"
++        if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) {
-+#include "migration/vmstate.h"
++            if (((spdata & ~1) == 0xfefa125a) ||
-+#include "qapi/error.h"
++                !(env->v7m.control[M_REG_S] & 1)) {
-+#include "qemu/bitops.h"
++                goto gen_invep;
-+#include "qemu/log.h"
++            }
-+#include "qemu/module.h"
++        }
 +#include "qemu/units.h"
 +
 +/* Each module has 4 KiB of register space. Only a fraction of it is used. */
 +#define NPCM7XX_OTP_REGS_SIZE (4 * KiB)
 +
 +/* 32-bit register indices. */
 +typedef enum NPCM7xxOTPRegister {
 +    NPCM7XX_OTP_FST,
 +    NPCM7XX_OTP_FADDR,
 +    NPCM7XX_OTP_FDATA,
 +    NPCM7XX_OTP_FCFG,
 +    /* Offset 0x10 is FKEYIND in OTP1, FUSTRAP in OTP2 */
 +    NPCM7XX_OTP_FKEYIND = 0x0010 / sizeof(uint32_t),
 +    NPCM7XX_OTP_FUSTRAP = 0x0010 / sizeof(uint32_t),
 +    NPCM7XX_OTP_FCTL,
 +    NPCM7XX_OTP_REGS_END,
 +} NPCM7xxOTPRegister;
 +
 +/* Register field definitions. */
 +#define FST_RIEN BIT(2)
 +#define FST_RDST BIT(1)
 +#define FST_RDY BIT(0)
 +#define FST_RO_MASK (FST_RDST | FST_RDY)
 +
 +#define FADDR_BYTEADDR(rv) extract32((rv), 0, 10)
 +#define FADDR_BITPOS(rv) extract32((rv), 10, 3)
 +
 +#define FDATA_CLEAR 0x00000001
 +
 +#define FCFG_FDIS BIT(31)
 +#define FCFG_FCFGLK_MASK 0x00ff0000
 +
 +#define FCTL_PROG_CMD1 0x00000001
 +#define FCTL_PROG_CMD2 0xbf79e5d0
 +#define FCTL_READ_CMD 0x00000002
 +
 +/**
 + * struct NPCM7xxOTPClass - OTP module class.
 + * @parent: System bus device class.
 + * @mmio_ops: MMIO register operations for this type of module.
 + *
 + * The two OTP modules (key-storage and fuse-array) have slightly different
 + * behavior, so we give them different MMIO register operations.
 + */
 +struct NPCM7xxOTPClass {
 +    SysBusDeviceClass parent;
 +
 +    const MemoryRegionOps *mmio_ops;
 +};
 +
 +#define NPCM7XX_OTP_CLASS(klass) \
 +    OBJECT_CLASS_CHECK(NPCM7xxOTPClass, (klass), TYPE_NPCM7XX_OTP)
 +#define NPCM7XX_OTP_GET_CLASS(obj) \
 +    OBJECT_GET_CLASS(NPCM7xxOTPClass, (obj), TYPE_NPCM7XX_OTP)
 +
 +static uint8_t ecc_encode_nibble(uint8_t n)
 +{
 +    uint8_t result = n;
 +
 +    result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4;
 +    result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5;
 +    result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6;
 +    result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7;
 +
 +    return result;
 +}
 +
 +void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
 +                             unsigned int offset, unsigned int len)
 +{
 +    const uint8_t *src = data;
 +    uint8_t *dst = &s->array[offset];
 +
 +    while (len-- > 0) {
 +        uint8_t c = *src++;
 +
 +        *dst++ = ecc_encode_nibble(extract8(c, 0, 4));
 +        *dst++ = ecc_encode_nibble(extract8(c, 4, 4));
 +    }
 +}
 +
 +/* Common register read handler for both OTP classes. */
 +static uint64_t npcm7xx_otp_read(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg)
 +{
 +    uint32_t value = 0;
 +
 +    switch (reg) {
 +    case NPCM7XX_OTP_FST:
 +    case NPCM7XX_OTP_FADDR:
 +    case NPCM7XX_OTP_FDATA:
 +    case NPCM7XX_OTP_FCFG:
 +        value = s->regs[reg];
 +        break;
 +
 +    case NPCM7XX_OTP_FCTL:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "%s: read from write-only FCTL register\n",
 +                      DEVICE(s)->canonical_path);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: read from invalid offset 0x%zx\n",
 +                      DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
 +        break;
 +    }
 +
-+    return value;
+     env->regs[14] &= ~1;
-+}
+     env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
-+
+     switch_v7m_security_state(env, true);
 +/* Read a byte from the OTP array into the data register. */
 +static void npcm7xx_otp_read_array(NPCM7xxOTPState *s)
 +{
 +    uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
 +
 +    s->regs[NPCM7XX_OTP_FDATA] = s->array[FADDR_BYTEADDR(faddr)];
 +    s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
 +}
 +
 +/* Program a byte from the data register into the OTP array. */
 +static void npcm7xx_otp_program_array(NPCM7xxOTPState *s)
 +{
 +    uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
 +
 +    /* Bits can only go 0->1, never 1->0. */
 +    s->array[FADDR_BYTEADDR(faddr)] |= (1U << FADDR_BITPOS(faddr));
 +    s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
 +}
 +
 +/* Compute the next value of the FCFG register. */
 +static uint32_t npcm7xx_otp_compute_fcfg(uint32_t cur_value, uint32_t new_value)
 +{
 +    uint32_t lock_mask;
 +    uint32_t value;
 +
 +    /*
 +     * FCFGLK holds sticky bits 16..23, indicating which bits in FPRGLK (8..15)
 +     * and FRDLK (0..7) that are read-only.
 +     */
 +    lock_mask = (cur_value & FCFG_FCFGLK_MASK) >> 8;
 +    lock_mask |= lock_mask >> 8;
 +    /* FDIS and FCFGLK bits are sticky (write 1 to set; can't clear). */
 +    value = cur_value & (FCFG_FDIS | FCFG_FCFGLK_MASK);
 +    /* Preserve read-only bits in FPRGLK and FRDLK */
 +    value |= cur_value & lock_mask;
 +    /* Set all bits that aren't read-only. */
 +    value |= new_value & ~lock_mask;
 +
 +    return value;
 +}
 +
 +/* Common register write handler for both OTP classes. */
 +static void npcm7xx_otp_write(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg,
 +                              uint32_t value)
 +{
 +    switch (reg) {
 +    case NPCM7XX_OTP_FST:
 +        /* RDST is cleared by writing 1 to it. */
 +        if (value & FST_RDST) {
 +            s->regs[NPCM7XX_OTP_FST] &= ~FST_RDST;
 +        }
 +        /* Preserve read-only and write-one-to-clear bits */
 +        value &= ~FST_RO_MASK;
 +        value |= s->regs[NPCM7XX_OTP_FST] & FST_RO_MASK;
 +        break;
 +
 +    case NPCM7XX_OTP_FADDR:
 +        break;
 +
 +    case NPCM7XX_OTP_FDATA:
 +        /*
 +         * This register is cleared by writing a magic value to it; no other
 +         * values can be written.
 +         */
 +        if (value == FDATA_CLEAR) {
 +            value = 0;
 +        } else {
 +            value = s->regs[NPCM7XX_OTP_FDATA];
 +        }
 +        break;
 +
 +    case NPCM7XX_OTP_FCFG:
 +        value = npcm7xx_otp_compute_fcfg(s->regs[NPCM7XX_OTP_FCFG], value);
 +        break;
 +
 +    case NPCM7XX_OTP_FCTL:
 +        switch (value) {
 +        case FCTL_READ_CMD:
 +            npcm7xx_otp_read_array(s);
 +            break;
 +
 +        case FCTL_PROG_CMD1:
 +            /*
 +             * Programming requires writing two separate magic values to this
 +             * register; this is the first one. Just store it so it can be
 +             * verified later when the second magic value is received.
 +             */
 +            break;
 +
 +        case FCTL_PROG_CMD2:
 +            /*
 +             * Only initiate programming if we received the first half of the
 +             * command immediately before this one.
 +             */
 +            if (s->regs[NPCM7XX_OTP_FCTL] == FCTL_PROG_CMD1) {
 +                npcm7xx_otp_program_array(s);
 +            }
 +            break;
 +
 +        default:
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "%s: unrecognized FCNTL value 0x%" PRIx32 "\n",
 +                          DEVICE(s)->canonical_path, value);
 +            break;
 +        }
 +        if (value != FCTL_PROG_CMD1) {
 +            value = 0;
 +        }
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to invalid offset 0x%zx\n",
 +                      DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
 +        return;
 +    }
 +
 +    s->regs[reg] = value;
 +}
 +
 +/* Register read handler specific to the fuse array OTP module. */
 +static uint64_t npcm7xx_fuse_array_read(void *opaque, hwaddr addr,
 +                                        unsigned int size)
 +{
 +    NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
 +    NPCM7xxOTPState *s = opaque;
 +    uint32_t value;
 +
 +    /*
 +     * Only the Fuse Strap register needs special handling; all other registers
 +     * work the same way for both kinds of OTP modules.
 +     */
 +    if (reg != NPCM7XX_OTP_FUSTRAP) {
 +        value = npcm7xx_otp_read(s, reg);
 +    } else {
 +        /* FUSTRAP is stored as three copies in the OTP array. */
 +        uint32_t fustrap[3];
 +
 +        memcpy(fustrap, &s->array[0], sizeof(fustrap));
 +
 +        /* Determine value by a majority vote on each bit. */
 +        value = (fustrap[0] & fustrap[1]) | (fustrap[0] & fustrap[2]) |
 +                (fustrap[1] & fustrap[2]);
 +    }
 +
 +    return value;
 +}
 +
 +/* Register write handler specific to the fuse array OTP module. */
 +static void npcm7xx_fuse_array_write(void *opaque, hwaddr addr, uint64_t v,
 +                                     unsigned int size)
 +{
 +    NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
 +    NPCM7xxOTPState *s = opaque;
 +
 +    /*
 +     * The Fuse Strap register is read-only. Other registers are handled by
 +     * common code.
 +     */
 +    if (reg != NPCM7XX_OTP_FUSTRAP) {
 +        npcm7xx_otp_write(s, reg, v);
 +    }
 +}
 +
 +static const MemoryRegionOps npcm7xx_fuse_array_ops = {
 +    .read       = npcm7xx_fuse_array_read,
 +    .write      = npcm7xx_fuse_array_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +/* Register read handler specific to the key storage OTP module. */
 +static uint64_t npcm7xx_key_storage_read(void *opaque, hwaddr addr,
 +                                         unsigned int size)
 +{
 +    NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
 +    NPCM7xxOTPState *s = opaque;
 +
 +    /*
 +     * Only the Fuse Key Index register needs special handling; all other
 +     * registers work the same way for both kinds of OTP modules.
 +     */
 +    if (reg != NPCM7XX_OTP_FKEYIND) {
 +        return npcm7xx_otp_read(s, reg);
 +    }
 +
 +    qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
 +
 +    return s->regs[NPCM7XX_OTP_FKEYIND];
 +}
 +
 +/* Register write handler specific to the key storage OTP module. */
 +static void npcm7xx_key_storage_write(void *opaque, hwaddr addr, uint64_t v,
 +                                      unsigned int size)
 +{
 +    NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
 +    NPCM7xxOTPState *s = opaque;
 +
 +    /*
 +     * Only the Fuse Key Index register needs special handling; all other
 +     * registers work the same way for both kinds of OTP modules.
 +     */
 +    if (reg != NPCM7XX_OTP_FKEYIND) {
 +        npcm7xx_otp_write(s, reg, v);
 +        return;
 +    }
 +
 +    qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
 +
 +    s->regs[NPCM7XX_OTP_FKEYIND] = v;
 +}
 +
 +static const MemoryRegionOps npcm7xx_key_storage_ops = {
 +    .read       = npcm7xx_key_storage_read,
 +    .write      = npcm7xx_key_storage_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid      = {
 +        .min_access_size        = 4,
 +        .max_access_size        = 4,
 +        .unaligned              = false,
 +    },
 +};
 +
 +static void npcm7xx_otp_enter_reset(Object *obj, ResetType type)
 +{
 +    NPCM7xxOTPState *s = NPCM7XX_OTP(obj);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    s->regs[NPCM7XX_OTP_FST] = 0x00000001;
 +    s->regs[NPCM7XX_OTP_FCFG] = 0x20000000;
 +}
 +
 +static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
 +{
 +    NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
 +    NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
 +    SysBusDevice *sbd = &s->parent;
 +
 +    memset(s->array, 0, sizeof(s->array));
 +
 +    memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
 +                          NPCM7XX_OTP_REGS_SIZE);
 +    sysbus_init_mmio(sbd, &s->mmio);
 +}
 +
 +static const VMStateDescription vmstate_npcm7xx_otp = {
 +    .name = "npcm7xx-otp",
 +    .version_id = 0,
 +    .minimum_version_id = 0,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, NPCM7xxOTPState, NPCM7XX_OTP_NR_REGS),
 +        VMSTATE_UINT8_ARRAY(array, NPCM7xxOTPState, NPCM7XX_OTP_ARRAY_BYTES),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    QEMU_BUILD_BUG_ON(NPCM7XX_OTP_REGS_END > NPCM7XX_OTP_NR_REGS);
 +
 +    dc->realize = npcm7xx_otp_realize;
 +    dc->vmsd = &vmstate_npcm7xx_otp;
 +    rc->phases.enter = npcm7xx_otp_enter_reset;
 +}
 +
 +static void npcm7xx_key_storage_class_init(ObjectClass *klass, void *data)
 +{
 +    NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
 +
 +    oc->mmio_ops = &npcm7xx_key_storage_ops;
 +}
 +
 +static void npcm7xx_fuse_array_class_init(ObjectClass *klass, void *data)
 +{
 +    NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
 +
 +    oc->mmio_ops = &npcm7xx_fuse_array_ops;
 +}
 +
 +static const TypeInfo npcm7xx_otp_types[] = {
 +    {
 +        .name = TYPE_NPCM7XX_OTP,
 +        .parent = TYPE_SYS_BUS_DEVICE,
 +        .instance_size = sizeof(NPCM7xxOTPState),
 +        .class_size = sizeof(NPCM7xxOTPClass),
 +        .class_init = npcm7xx_otp_class_init,
 +        .abstract = true,
 +    },
 +    {
 +        .name = TYPE_NPCM7XX_KEY_STORAGE,
 +        .parent = TYPE_NPCM7XX_OTP,
 +        .class_init = npcm7xx_key_storage_class_init,
 +    },
 +    {
 +        .name = TYPE_NPCM7XX_FUSE_ARRAY,
 +        .parent = TYPE_NPCM7XX_OTP,
 +        .class_init = npcm7xx_fuse_array_class_init,
 +    },
 +};
 +DEFINE_TYPES(npcm7xx_otp_types);
 diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/nvram/meson.build
 +++ b/hw/nvram/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_DS1225Y', if_true: files('ds1225y.c'))
  softmmu_ss.add(when: 'CONFIG_NMC93XX_EEPROM', if_true: files('eeprom93xx.c'))
  softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
  softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
 +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
  softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
  specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
 --
 .20.1

-[PULL 10/36] target/arm: Remove KVM support for 32-bit Arm hosts
+[PULL 33/36] hw/intc/armv7m_nvic: Fix "return from inactive handler" check
-We deprecated the support for KVM on 32-bit Arm hosts in time
+In commit 077d7449100d824a4 we added code to handle the v8M
-for release 5.0, which means that our deprecation policy allows
+requirement that returns from NMI or HardFault forcibly deactivate
-us to drop it in release 5.2. Remove the code.
+those exceptions regardless of what interrupt the guest is trying to
 deactivate.  Unfortunately this broke the handling of the "illegal
 exception return because the returning exception number is not
 active" check for those cases.  In the pseudocode this test is done
 on the exception the guest asks to return from, but because our
 implementation was doing this in armv7m_nvic_complete_irq() after the
 new "deactivate NMI/HardFault regardless" code we ended up doing the
 test on the VecInfo for that exception instead, which usually meant
 failing to raise the illegal exception return fault.
-To repeat the rationale from the deprecation note: the Linux
+In the case for "configurable exception targeting the opposite
-kernel dropped support for 32-bit Arm KVM hosts in 5.7.
+security state" we detected the illegal-return case but went ahead
 and deactivated the VecInfo anyway, which is wrong because that is
 the VecInfo for the other security state.
-Running 32-bit guests on a 64-bit Arm host remains supported.
+Rearrange the code so that we first identify the illegal return
 cases, then see if we really need to deactivate NMI or HardFault
 instead, and finally do the deactivation.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: 20201119215617.29887-25-peter.maydell@linaro.org
 Message-id: 20200904154156.31943-2-peter.maydell@linaro.org
 ---
- docs/system/deprecated.rst |  16 +-
+ hw/intc/armv7m_nvic.c | 59 +++++++++++++++++++++++--------------------
- configure                  |   2 +-
+file changed, 32 insertions(+), 27 deletions(-)
  target/arm/kvm32.c         | 595 -------------------------------------
  target/arm/meson.build     |   5 +-
 files changed, 10 insertions(+), 608 deletions(-)
  delete mode 100644 target/arm/kvm32.c
-diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/deprecated.rst
+--- a/hw/intc/armv7m_nvic.c
-+++ b/docs/system/deprecated.rst
++++ b/hw/intc/armv7m_nvic.c
-@@ -XXX,XX +XXX,XX @@ The ``compat`` property used to set backwards compatibility modes for
+@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
- the processor has been deprecated. The ``max-cpu-compat`` property of
+ {
- the ``pseries`` machine type should be used instead.
+     NVICState *s = (NVICState *)opaque;
+     VecInfo *vec = NULL;
--KVM guest support on 32-bit Arm hosts (since 5.0)
+-    int ret;
--'''''''''''''''''''''''''''''''''''''''''''''''''
++    int ret = 0;
--
--The Linux kernel has dropped support for allowing 32-bit Arm systems
+     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
--to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating
--its support for this configuration and will remove it in a future version.
++    trace_nvic_complete_irq(irq, secure);
 -Running 32-bit guests on a 64-bit Arm host remains supported.
 -
  System emulator devices
  -----------------------
@@ -XXX,XX +XXX,XX @@ should be used instead of the 1.09.1 version.
  System emulator CPUS
  --------------------
 +KVM guest support on 32-bit Arm hosts (removed in 5.2)
 +''''''''''''''''''''''''''''''''''''''''''''''''''''''
 +
-+The Linux kernel has dropped support for allowing 32-bit Arm systems
++    if (secure && exc_is_banked(irq)) {
-+to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating
++        vec = &s->sec_vectors[irq];
-+its support for this configuration and will remove it in a future version.
++    } else {
-+Running 32-bit guests on a 64-bit Arm host remains supported.
++        vec = &s->vectors[irq];
 +    }
 +
- RISC-V ISA Specific CPUs (removed in 5.1)
++    /*
- '''''''''''''''''''''''''''''''''''''''''
++     * Identify illegal exception return cases. We can't immediately
++     * return at this point because we still need to deactivate
-diff --git a/configure b/configure
++     * (either this exception or NMI/HardFault) first.
-index XXXXXXX..XXXXXXX 100755
++     */
---- a/configure
++    if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
-+++ b/configure
++        /*
-@@ -XXX,XX +XXX,XX @@ supported_kvm_target() {
++         * Return from a configurable exception targeting the opposite
-     test "$kvm" = "yes" || return 1
++         * security state from the one we're trying to complete it for.
-     glob "$1" "*-softmmu" || return 1
++         * Clear vec because it's not really the VecInfo for this
-     case "${1%-softmmu}:$cpu" in
++         * (irq, secstate) so we mustn't deactivate it.
--        arm:arm | aarch64:aarch64 | \
++         */
-+        aarch64:aarch64 | \
++        ret = -1;
-         i386:i386 | i386:x86_64 | i386:x32 | \
++        vec = NULL;
-         x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \
++    } else if (!vec->active) {
-         mips:mips | mipsel:mips | mips64:mips | mips64el:mips | \
++        /* Return from an inactive interrupt */
-diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
++        ret = -1;
-deleted file mode 100644
++    } else {
-index XXXXXXX..XXXXXXX
++        /* Legal return, we will return the RETTOBASE bit value to the caller */
---- a/target/arm/kvm32.c
++        ret = nvic_rettobase(s);
-+++ /dev/null
++    }
-@@ -XXX,XX +XXX,XX @@
++
--/*
+     /*
-- * ARM implementation of KVM hooks, 32 bit specific code.
+      * For negative priorities, v8M will forcibly deactivate the appropriate
-- *
+      * NMI or HardFault regardless of what interrupt we're being asked to
-- * Copyright Christoffer Dall 2009-2010
+@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
-- *
+     }
-- * This work is licensed under the terms of the GNU GPL, version 2 or later.
-- * See the COPYING file in the top-level directory.
+     if (!vec) {
-- *
+-        if (secure && exc_is_banked(irq)) {
-- */
+-            vec = &s->sec_vectors[irq];
--
+-        } else {
--#include "qemu/osdep.h"
+-            vec = &s->vectors[irq];
--#include <sys/ioctl.h>
+-        }
 -
 -#include <linux/kvm.h>
 -
 -#include "qemu-common.h"
 -#include "cpu.h"
 -#include "qemu/timer.h"
 -#include "sysemu/runstate.h"
 -#include "sysemu/kvm.h"
 -#include "kvm_arm.h"
 -#include "internals.h"
 -#include "qemu/log.h"
 -
 -static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
 -{
 -    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
 -
 -    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
 -    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
 -}
 -
 -bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 -{
 -    /* Identify the feature bits corresponding to the host CPU, and
 -     * fill out the ARMHostCPUClass fields accordingly. To do this
 -     * we have to create a scratch VM, create a single CPU inside it,
 -     * and then query that CPU for the relevant ID registers.
 -     */
 -    int err = 0, fdarray[3];
 -    uint32_t midr, id_pfr0;
 -    uint64_t features = 0;
 -
 -    /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
 -     * we know these will only support creating one kind of guest CPU,
 -     * which is its preferred CPU type.
 -     */
 -    static const uint32_t cpus_to_try[] = {
 -        QEMU_KVM_ARM_TARGET_CORTEX_A15,
 -        QEMU_KVM_ARM_TARGET_NONE
 -    };
 -    /*
 -     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
 -     * to use the preferred target
 -     */
 -    struct kvm_vcpu_init init = { .target = -1, };
 -
 -    if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
 -        return false;
 -    }
 -
--    ahcf->target = init.target;
+-    trace_nvic_complete_irq(irq, secure);
 -
--    /* This is not strictly blessed by the device tree binding docs yet,
+-    if (!vec->active) {
--     * but in practice the kernel does not care about this string so
+-        /* Tell the caller this was an illegal exception return */
--     * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
+-        return -1;
 -     */
 -    ahcf->dtb_compatible = "arm,arm-v7";
 -
 -    err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
 -    err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
 -
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
 -                          ARM_CP15_REG32(0, 0, 2, 0));
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
 -                          ARM_CP15_REG32(0, 0, 2, 1));
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
 -                          ARM_CP15_REG32(0, 0, 2, 2));
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
 -                          ARM_CP15_REG32(0, 0, 2, 3));
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
 -                          ARM_CP15_REG32(0, 0, 2, 4));
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
 -                          ARM_CP15_REG32(0, 0, 2, 5));
 -    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
 -                       ARM_CP15_REG32(0, 0, 2, 7))) {
 -        /*
 -         * Older kernels don't support reading ID_ISAR6. This register was
 -         * only introduced in ARMv8, so we can assume that it is zero on a
 -         * CPU that a kernel this old is running on.
 -         */
 -        ahcf->isar.id_isar6 = 0;
 -    }
 -
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
 -                          ARM_CP15_REG32(0, 0, 1, 2));
 -
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
 -                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
 -                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
 -                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
 -                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
 -    /*
 -     * FIXME: There is not yet a way to read MVFR2.
 -     * Fortunately there is not yet anything in there that affects migration.
 -     */
 -
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
 -                          ARM_CP15_REG32(0, 0, 1, 4));
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
 -                          ARM_CP15_REG32(0, 0, 1, 5));
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
 -                          ARM_CP15_REG32(0, 0, 1, 6));
 -    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
 -                          ARM_CP15_REG32(0, 0, 1, 7));
 -    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
 -                       ARM_CP15_REG32(0, 0, 2, 6))) {
 -        /*
 -         * Older kernels don't support reading ID_MMFR4 (a new in v8
 -         * register); assume it's zero.
 -         */
 -        ahcf->isar.id_mmfr4 = 0;
 -    }
 -
 -    /*
--     * There is no way to read DBGDIDR, because currently 32-bit KVM
+-     * If this is a configurable exception and it is currently
--     * doesn't implement debug at all. Leave it at zero.
+-     * targeting the opposite security state from the one we're trying
 -     * to complete it for, this counts as an illegal exception return.
 -     * We still need to deactivate whatever vector the logic above has
 -     * selected, though, as it might not be the same as the one for the
 -     * requested exception number.
 -     */
--
+-    if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
--    kvm_arm_destroy_scratch_host_vcpu(fdarray);
+-        ret = -1;
 -
 -    if (err < 0) {
 -        return false;
 -    }
 -
 -    /* Now we've retrieved all the register information we can
 -     * set the feature bits based on the ID register fields.
 -     * We can assume any KVM supporting CPU is at least a v7
 -     * with VFPv3, virtualization extensions, and the generic
 -     * timers; this in turn implies most of the other feature
 -     * bits, but a few must be tested.
 -     */
 -    features |= 1ULL << ARM_FEATURE_V7VE;
 -    features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
 -
 -    if (extract32(id_pfr0, 12, 4) == 1) {
 -        features |= 1ULL << ARM_FEATURE_THUMB2EE;
 -    }
 -    if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
 -        features |= 1ULL << ARM_FEATURE_NEON;
 -    }
 -
 -    ahcf->features = features;
 -
 -    return true;
 -}
 -
 -bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 -{
 -    /* Return true if the regidx is a register we should synchronize
 -     * via the cpreg_tuples array (ie is not a core reg we sync by
 -     * hand in kvm_arch_get/put_registers())
 -     */
 -    switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 -    case KVM_REG_ARM_CORE:
 -    case KVM_REG_ARM_VFP:
 -        return false;
 -    default:
 -        return true;
 -    }
 -}
 -
 -typedef struct CPRegStateLevel {
 -    uint64_t regidx;
 -    int level;
 -} CPRegStateLevel;
 -
 -/* All coprocessor registers not listed in the following table are assumed to
 - * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
 - * often, you must add it to this table with a state of either
 - * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
 - */
 -static const CPRegStateLevel non_runtime_cpregs[] = {
 -    { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
 -};
 -
 -int kvm_arm_cpreg_level(uint64_t regidx)
 -{
 -    int i;
 -
 -    for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
 -        const CPRegStateLevel *l = &non_runtime_cpregs[i];
 -        if (l->regidx == regidx) {
 -            return l->level;
 -        }
 -    }
 -
 -    return KVM_PUT_RUNTIME_STATE;
 -}
 -
 -#define ARM_CPU_ID_MPIDR       0, 0, 0, 5
 -
 -int kvm_arch_init_vcpu(CPUState *cs)
 -{
 -    int ret;
 -    uint64_t v;
 -    uint32_t mpidr;
 -    struct kvm_one_reg r;
 -    ARMCPU *cpu = ARM_CPU(cs);
 -
 -    if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 -        fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 -        return -EINVAL;
 -    }
 -
 -    qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
 -
 -    /* Determine init features for this CPU */
 -    memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 -    if (cs->start_powered_off) {
 -        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 -    }
 -    if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 -        cpu->psci_version = 2;
 -        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 -    }
 -
 -    /* Do KVM_ARM_VCPU_INIT ioctl */
 -    ret = kvm_arm_vcpu_init(cs);
 -    if (ret) {
 -        return ret;
 -    }
 -
 -    /* Query the kernel to make sure it supports 32 VFP
 -     * registers: QEMU's "cortex-a15" CPU is always a
 -     * VFP-D32 core. The simplest way to do this is just
 -     * to attempt to read register d31.
 -     */
 -    r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 -    r.addr = (uintptr_t)(&v);
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 -    if (ret == -ENOENT) {
 -        return -EINVAL;
 -    }
 -
 -    /*
 -     * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
 -     * Currently KVM has its own idea about MPIDR assignment, so we
 -     * override our defaults with what we get from KVM.
 -     */
 -    ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
 -    if (ret) {
 -        return ret;
 -    }
 -    cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
 -
 -    /* Check whether userspace can specify guest syndrome value */
 -    kvm_arm_init_serror_injection(cs);
 -
 -    return kvm_arm_init_cpreg_list(cpu);
 -}
 -
 -int kvm_arch_destroy_vcpu(CPUState *cs)
 -{
 -    return 0;
 -}
 -
 -typedef struct Reg {
 -    uint64_t id;
 -    int offset;
 -} Reg;
 -
 -#define COREREG(KERNELNAME, QEMUFIELD)                       \
 -    {                                                        \
 -        KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 -        KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 -        offsetof(CPUARMState, QEMUFIELD)                     \
 -    }
 -
 -#define VFPSYSREG(R)                                       \
 -    {                                                      \
 -        KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 -        KVM_REG_ARM_VFP_##R,                               \
 -        offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 -    }
 -
 -/* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 -#define COREREG64(KERNELNAME, QEMUFIELD)                     \
 -    {                                                        \
 -        KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 -        KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 -        offsetoflow32(CPUARMState, QEMUFIELD)                \
 -    }
 -
 -static const Reg regs[] = {
 -    /* R0_usr .. R14_usr */
 -    COREREG(usr_regs.uregs[0], regs[0]),
 -    COREREG(usr_regs.uregs[1], regs[1]),
 -    COREREG(usr_regs.uregs[2], regs[2]),
 -    COREREG(usr_regs.uregs[3], regs[3]),
 -    COREREG(usr_regs.uregs[4], regs[4]),
 -    COREREG(usr_regs.uregs[5], regs[5]),
 -    COREREG(usr_regs.uregs[6], regs[6]),
 -    COREREG(usr_regs.uregs[7], regs[7]),
 -    COREREG(usr_regs.uregs[8], usr_regs[0]),
 -    COREREG(usr_regs.uregs[9], usr_regs[1]),
 -    COREREG(usr_regs.uregs[10], usr_regs[2]),
 -    COREREG(usr_regs.uregs[11], usr_regs[3]),
 -    COREREG(usr_regs.uregs[12], usr_regs[4]),
 -    COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
 -    COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
 -    /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 -    COREREG(svc_regs[0], banked_r13[BANK_SVC]),
 -    COREREG(svc_regs[1], banked_r14[BANK_SVC]),
 -    COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
 -    COREREG(abt_regs[0], banked_r13[BANK_ABT]),
 -    COREREG(abt_regs[1], banked_r14[BANK_ABT]),
 -    COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
 -    COREREG(und_regs[0], banked_r13[BANK_UND]),
 -    COREREG(und_regs[1], banked_r14[BANK_UND]),
 -    COREREG64(und_regs[2], banked_spsr[BANK_UND]),
 -    COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
 -    COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
 -    COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
 -    /* R8_fiq .. R14_fiq and SPSR_fiq */
 -    COREREG(fiq_regs[0], fiq_regs[0]),
 -    COREREG(fiq_regs[1], fiq_regs[1]),
 -    COREREG(fiq_regs[2], fiq_regs[2]),
 -    COREREG(fiq_regs[3], fiq_regs[3]),
 -    COREREG(fiq_regs[4], fiq_regs[4]),
 -    COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
 -    COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
 -    COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
 -    /* R15 */
 -    COREREG(usr_regs.uregs[15], regs[15]),
 -    /* VFP system registers */
 -    VFPSYSREG(FPSID),
 -    VFPSYSREG(MVFR1),
 -    VFPSYSREG(MVFR0),
 -    VFPSYSREG(FPEXC),
 -    VFPSYSREG(FPINST),
 -    VFPSYSREG(FPINST2),
 -};
 -
 -int kvm_arch_put_registers(CPUState *cs, int level)
 -{
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    CPUARMState *env = &cpu->env;
 -    struct kvm_one_reg r;
 -    int mode, bn;
 -    int ret, i;
 -    uint32_t cpsr, fpscr;
 -
 -    /* Make sure the banked regs are properly set */
 -    mode = env->uncached_cpsr & CPSR_M;
 -    bn = bank_number(mode);
 -    if (mode == ARM_CPU_MODE_FIQ) {
 -        memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 -    } else {
--        memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
+-        ret = nvic_rettobase(s);
--    }
++        return ret;
--    env->banked_r13[bn] = env->regs[13];
+     }
--    env->banked_spsr[bn] = env->spsr;
--    env->banked_r14[r14_bank_number(mode)] = env->regs[14];
+     vec->active = 0;
 -
 -    /* Now we can safely copy stuff down to the kernel */
 -    for (i = 0; i < ARRAY_SIZE(regs); i++) {
 -        r.id = regs[i].id;
 -        r.addr = (uintptr_t)(env) + regs[i].offset;
 -        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 -        if (ret) {
 -            return ret;
 -        }
 -    }
 -
 -    /* Special cases which aren't a single CPUARMState field */
 -    cpsr = cpsr_read(env);
 -    r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 -        KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 -    r.addr = (uintptr_t)(&cpsr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 -    if (ret) {
 -        return ret;
 -    }
 -
 -    /* VFP registers */
 -    r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 -    for (i = 0; i < 32; i++) {
 -        r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 -        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 -        if (ret) {
 -            return ret;
 -        }
 -        r.id++;
 -    }
 -
 -    r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 -        KVM_REG_ARM_VFP_FPSCR;
 -    fpscr = vfp_get_fpscr(env);
 -    r.addr = (uintptr_t)&fpscr;
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 -    if (ret) {
 -        return ret;
 -    }
 -
 -    write_cpustate_to_list(cpu, true);
 -
 -    if (!write_list_to_kvmstate(cpu, level)) {
 -        return EINVAL;
 -    }
 -
 -    /*
 -     * Setting VCPU events should be triggered after syncing the registers
 -     * to avoid overwriting potential changes made by KVM upon calling
 -     * KVM_SET_VCPU_EVENTS ioctl
 -     */
 -    ret = kvm_put_vcpu_events(cpu);
 -    if (ret) {
 -        return ret;
 -    }
 -
 -    kvm_arm_sync_mpstate_to_kvm(cpu);
 -
 -    return ret;
 -}
 -
 -int kvm_arch_get_registers(CPUState *cs)
 -{
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    CPUARMState *env = &cpu->env;
 -    struct kvm_one_reg r;
 -    int mode, bn;
 -    int ret, i;
 -    uint32_t cpsr, fpscr;
 -
 -    for (i = 0; i < ARRAY_SIZE(regs); i++) {
 -        r.id = regs[i].id;
 -        r.addr = (uintptr_t)(env) + regs[i].offset;
 -        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 -        if (ret) {
 -            return ret;
 -        }
 -    }
 -
 -    /* Special cases which aren't a single CPUARMState field */
 -    r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 -        KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 -    r.addr = (uintptr_t)(&cpsr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 -    if (ret) {
 -        return ret;
 -    }
 -    cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
 -
 -    /* Make sure the current mode regs are properly set */
 -    mode = env->uncached_cpsr & CPSR_M;
 -    bn = bank_number(mode);
 -    if (mode == ARM_CPU_MODE_FIQ) {
 -        memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 -    } else {
 -        memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 -    }
 -    env->regs[13] = env->banked_r13[bn];
 -    env->spsr = env->banked_spsr[bn];
 -    env->regs[14] = env->banked_r14[r14_bank_number(mode)];
 -
 -    /* VFP registers */
 -    r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 -    for (i = 0; i < 32; i++) {
 -        r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 -        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 -        if (ret) {
 -            return ret;
 -        }
 -        r.id++;
 -    }
 -
 -    r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 -        KVM_REG_ARM_VFP_FPSCR;
 -    r.addr = (uintptr_t)&fpscr;
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 -    if (ret) {
 -        return ret;
 -    }
 -    vfp_set_fpscr(env, fpscr);
 -
 -    ret = kvm_get_vcpu_events(cpu);
 -    if (ret) {
 -        return ret;
 -    }
 -
 -    if (!write_kvmstate_to_list(cpu)) {
 -        return EINVAL;
 -    }
 -    /* Note that it's OK to have registers which aren't in CPUState,
 -     * so we can ignore a failure return here.
 -     */
 -    write_list_to_cpustate(cpu);
 -
 -    kvm_arm_sync_mpstate_to_qemu(cpu);
 -
 -    return 0;
 -}
 -
 -int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 -    return -EINVAL;
 -}
 -
 -int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 -    return -EINVAL;
 -}
 -
 -bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 -    return false;
 -}
 -
 -int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 -                                  target_ulong len, int type)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 -    return -EINVAL;
 -}
 -
 -int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 -                                  target_ulong len, int type)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 -    return -EINVAL;
 -}
 -
 -void kvm_arch_remove_all_hw_breakpoints(void)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 -}
 -
 -void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 -}
 -
 -bool kvm_arm_hw_debug_active(CPUState *cs)
 -{
 -    return false;
 -}
 -
 -void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 -}
 -
 -void kvm_arm_pmu_init(CPUState *cs)
 -{
 -    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 -}
 -
 -#define ARM_REG_DFSR  ARM_CP15_REG32(0, 5, 0, 0)
 -#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
 -/*
 - *DFSR:
 - *      TTBCR.EAE == 0
 - *          FS[4]   - DFSR[10]
 - *          FS[3:0] - DFSR[3:0]
 - *      TTBCR.EAE == 1
 - *          FS, bits [5:0]
 - */
 -#define DFSR_FSC(lpae, v) \
 -    ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
 -
 -#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
 -
 -bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
 -{
 -    uint32_t dfsr_val;
 -
 -    if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
 -        ARMCPU *cpu = ARM_CPU(cs);
 -        CPUARMState *env = &cpu->env;
 -        uint32_t ttbcr;
 -        int lpae = 0;
 -
 -        if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
 -            lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
 -        }
 -        /* The verification is based on FS filed of the DFSR reg only*/
 -        return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
 -    }
 -    return false;
 -}
 diff --git a/target/arm/meson.build b/target/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/meson.build
 +++ b/target/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(zlib)
  arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c'))
 -kvm_ss = ss.source_set()
 -kvm_ss.add(when: 'TARGET_AARCH64', if_true: files('kvm64.c'), if_false: files('kvm32.c'))
 -arm_ss.add_all(when: 'CONFIG_KVM', if_true: kvm_ss)
 -arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
 +arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
  arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
    'cpu64.c',
 --
 .20.1

-[PULL 07/36] target/arm: Convert Neon 3-same-fp size field to MO_* in decode
+[PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation"
-In the Neon instructions, some instruction formats have a 2-bit size
+For v8.1M the architecture mandates that CPUs must provide at
-field which corresponds exactly to QEMU's MO_8/16/32/64.  However the
+least the "minimal RAS implementation" from the Reliability,
-floating-point insns in the 3-same group have a 1-bit size field
+Availability and Serviceability extension. This consists of:
-which is "0 for 32-bit float and 1 for 16-bit float".  Currently we
+ * an ESB instruction which is a NOP
-pass these values directly through to trans_ functions, which means
+   -- since it is in the HINT space we need only add a comment
-that when reading a particular trans_ function you need to know if
+ * an RFSR register which will RAZ/WI
-that insn uses a 2-bit size or a 1-bit size.
+ * a RAZ/WI AIRCR.IESB bit
+   -- the code which handles writes to AIRCR does not allow setting
-Move the handling of the 1-bit size to the decodetree file, so that
+      of RES0 bits, so we already treat this as RAZ/WI; add a comment
-all these insns consistently pass a size to the trans_ function which
+      noting that this is deliberate
-is an MO_8/16/32/64 value.
+ * minimal implementation of the RAS register block at 0xe0005000
+   -- this will be in a subsequent commit
-In this commit we switch over the insns using the 3same_fp and
+ * setting the ID_PFR0.RAS field to 0b0010
-same_fp_q0 formats.
+   -- we will do this when we add the Cortex-M55 CPU model
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200903133209.5141-2-peter.maydell@linaro.org
+Message-id: 20201119215617.29887-26-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 15 ++++++++++-----
+ target/arm/cpu.h      | 14 ++++++++++++++
- target/arm/translate-neon.c.inc | 16 +++++++++++-----
+ target/arm/t32.decode |  4 ++++
-files changed, 21 insertions(+), 10 deletions(-)
+ hw/intc/armv7m_nvic.c | 13 +++++++++++++
 files changed, 31 insertions(+)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/target/arm/cpu.h
-+++ b/target/arm/neon-dp.decode
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
- @3same_q0        .... ... . . . size:2 .... .... .... . 0 . . .... \
+ FIELD(ID_MMFR4, CCIDX, 24, 4)
-                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
+ FIELD(ID_MMFR4, EVT, 28, 4)
--# For FP insns the high bit of 'size' is used as part of opcode decode
++FIELD(ID_PFR0, STATE0, 0, 4)
--@3same_fp        .... ... . . . . size:1 .... .... .... . q:1 . . .... \
++FIELD(ID_PFR0, STATE1, 4, 4)
--                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
++FIELD(ID_PFR0, STATE2, 8, 4)
--@3same_fp_q0     .... ... . . . . size:1 .... .... .... . 0 . . .... \
++FIELD(ID_PFR0, STATE3, 12, 4)
--                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
++FIELD(ID_PFR0, CSV2, 16, 4)
-+# For FP insns the high bit of 'size' is used as part of opcode decode,
++FIELD(ID_PFR0, AMU, 20, 4)
-+# and the 'size' bit is 0 for 32-bit float and 1 for 16-bit float.
++FIELD(ID_PFR0, DIT, 24, 4)
-+# This converts this encoding to the same MO_8/16/32/64 values that the
++FIELD(ID_PFR0, RAS, 28, 4)
 +# integer neon insns use.
 +%3same_fp_size   20:1 !function=neon_3same_fp_size
 +
-+@3same_fp        .... ... . . . . . .... .... .... . q:1 . . .... \
+ FIELD(ID_PFR1, PROGMOD, 0, 4)
-+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%3same_fp_size
+ FIELD(ID_PFR1, SECURITY, 4, 4)
-+@3same_fp_q0     .... ... . . . . . .... .... .... . 0 . . .... \
+ FIELD(ID_PFR1, MPROGMOD, 8, 4)
-+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 size=%3same_fp_size
+@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
+     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
  VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
  VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.c.inc
 +++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static inline int rsub_8(DisasContext *s, int x)
      return 8 - x;
  }
-+static inline int neon_3same_fp_size(DisasContext *s, int x)
++static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
 +{
-+    /* Convert 0==fp32, 1==fp16 into a MO_* value */
++    return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
 +    return MO_32 - x;
 +}
 +
- /* Include the generated Neon decoder */
+ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
- #include "decode-neon-dp.c.inc"
+ {
- #include "decode-neon-ls.c.inc"
+     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
-@@ -XXX,XX +XXX,XX @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
+diff --git a/target/arm/t32.decode b/target/arm/t32.decode
-     WRAP_FP_GVEC(gen_##INSN##_fp16_3s, FPST_STD_F16, HFUNC)             \
+index XXXXXXX..XXXXXXX 100644
-     static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a)     \
+--- a/target/arm/t32.decode
-     {                                                                   \
++++ b/target/arm/t32.decode
--        if (a->size != 0) {                                             \
+@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
-+        if (a->size == MO_16) {                                         \
+       # SEV      1111 0011 1010 1111 1000 0000 0000 0100
-             if (!dc_isar_feature(aa32_fp16_arith, s)) {                 \
+       # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
-                 return false;                                           \
-             }                                                           \
++      # For M-profile minimal-RAS ESB can be a NOP, which is the
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a)
++      # default behaviour since it is in the hint space.
-         return false;
++      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
 +
        # The canonical nop ends in 0000 0000, but the whole rest
        # of the space is "reserved hint, behaves as nop".
        NOP        1111 0011 1010 1111 1000 0000 ---- ----
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
              return 0;
          }
          return cpu->env.v7m.sfar;
 +    case 0xf04: /* RFSR */
 +        if (!cpu_isar_feature(aa32_ras, cpu)) {
 +            goto bad_offset;
 +        }
 +        /* We provide minimal-RAS only: RFSR is RAZ/WI */
 +        return 0;
      case 0xf34: /* FPCCR */
          if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
              return 0;
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
                                R_V7M_AIRCR_PRIGROUP_SHIFT,
                                R_V7M_AIRCR_PRIGROUP_LENGTH);
              }
 +            /* AIRCR.IESB is RAZ/WI because we implement only minimal RAS */
              if (attrs.secure) {
                  /* These bits are only writable by secure */
                  cpu->env.v7m.aircr = value &
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
          }
          break;
      }
++    case 0xf04: /* RFSR */
--    if (a->size != 0) {
++        if (!cpu_isar_feature(aa32_ras, cpu)) {
-+    if (a->size == MO_16) {
++            goto bad_offset;
-         if (!dc_isar_feature(aa32_fp16_arith, s)) {
++        }
-             return false;
++        /* We provide minimal-RAS only: RFSR is RAZ/WI */
-         }
++        break;
-@@ -XXX,XX +XXX,XX @@ static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a)
+     case 0xf34: /* FPCCR */
-         return false;
+         if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
-     }
+             /* Not all bits here are banked. */
 -    if (a->size != 0) {
 +    if (a->size == MO_16) {
          if (!dc_isar_feature(aa32_fp16_arith, s)) {
              return false;
          }
@@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a,
      assert(a->q == 0); /* enforced by decode patterns */
 -    fpstatus = fpstatus_ptr(a->size != 0 ? FPST_STD_F16 : FPST_STD);
 +    fpstatus = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
      tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
                         vfp_reg_offset(1, a->vn),
                         vfp_reg_offset(1, a->vm),
@@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a,
  #define DO_3S_FP_PAIR(INSN,FUNC)                                    \
      static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
      {                                                               \
 -        if (a->size != 0) {                                         \
 +        if (a->size == MO_16) {                                     \
              if (!dc_isar_feature(aa32_fp16_arith, s)) {             \
                  return false;                                       \
              }                                                       \
 --
 .20.1

-[PULL 13/36] hw/arm/mps2: New board model mps2-an500
+[PULL 35/36] hw/intc/armv7m_nvic: Implement read/write for RAS register block
-Implement a model of the MPS2 with the AN500 firmware. This is
+The RAS feature has a block of memory-mapped registers at offset
-similar to the AN385, with the following differences:
+x5000 within the PPB.  For a "minimal RAS" implementation we provide
- * Cortex-M7 CPU
+no error records and so the only registers that exist in the block
- * PSRAM is at 0x6000_0000
+are ERRIIDR and ERRDEVID.
- * Ethernet is at 0xa000_0000
- * No zbt_boot_ctrl remapping of the low 16K
+The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour
-   (but QEMU doesn't implement this anyway)
+of the "nvic-default" region is actually valid for minimal-RAS,
- * no "block RAM" at 0x01000000
+so the main benefit of providing an explicit implementation of
 the register block is more accurate LOG_UNIMP messages, and a
 framework for where we could add a real RAS implementation later
 if necessary.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
+Message-id: 20201119215617.29887-27-peter.maydell@linaro.org
 ---
- docs/system/arm/mps2.rst |  6 ++--
+ include/hw/intc/armv7m_nvic.h |  1 +
- hw/arm/mps2.c            | 67 +++++++++++++++++++++++++++++++++-------
+ hw/intc/armv7m_nvic.c         | 56 +++++++++++++++++++++++++++++++++++
-files changed, 60 insertions(+), 13 deletions(-)
+files changed, 57 insertions(+)
-diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
+diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/mps2.rst
+--- a/include/hw/intc/armv7m_nvic.h
-+++ b/docs/system/arm/mps2.rst
++++ b/include/hw/intc/armv7m_nvic.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct NVICState {
--Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
+     MemoryRegion sysreg_ns_mem;
--================================================================================================
+     MemoryRegion systickmem;
-+Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
+     MemoryRegion systick_ns_mem;
-+================================================================================================================
++    MemoryRegion ras_mem;
+     MemoryRegion container;
- These board models all use Arm M-profile CPUs.
+     MemoryRegion defaultmem;
-@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
    Cortex-M3 as documented in ARM Application Note AN385
  ``mps2-an386``
    Cortex-M4 as documented in ARM Application Note AN386
 +``mps2-an500``
 +  Cortex-M7 as documented in ARM Application Note AN500
  ``mps2-an511``
    Cortex-M3 'DesignStart' as documented in AN511
  ``mps2-an505``
 diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
+--- a/hw/intc/armv7m_nvic.c
-+++ b/hw/arm/mps2.c
++++ b/hw/intc/armv7m_nvic.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = {
-  * We model the following FPGA images:
+     .endianness = DEVICE_NATIVE_ENDIAN,
   *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
   *  "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
 + *  "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
   *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
   *
   * Links to the TRM for the board itself and to the various Application
@@ -XXX,XX +XXX,XX @@
  typedef enum MPS2FPGAType {
      FPGA_AN385,
      FPGA_AN386,
 +    FPGA_AN500,
      FPGA_AN511,
  } MPS2FPGAType;
@@ -XXX,XX +XXX,XX @@ struct MPS2MachineClass {
      MachineClass parent;
      MPS2FPGAType fpga_type;
      uint32_t scc_id;
 +    bool has_block_ram;
 +    hwaddr ethernet_base;
 +    hwaddr psram_base;
  };
- typedef struct MPS2MachineClass MPS2MachineClass;
++
-@@ -XXX,XX +XXX,XX @@ typedef struct MPS2MachineState MPS2MachineState;
++static MemTxResult ras_read(void *opaque, hwaddr addr,
- #define TYPE_MPS2_MACHINE "mps2"
++                            uint64_t *data, unsigned size,
- #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
++                            MemTxAttrs attrs)
- #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
++{
-+#define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
++    if (attrs.user) {
- #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
++        return MEMTX_ERROR;
  DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass,
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
       *
       * AN385/AN386/AN511:
       *  0x21000000 .. 0x21ffffff : PSRAM (16MB)
 -     * AN385/AN386 only:
 +     * AN385/AN386/AN500:
       *  0x00000000 .. 0x003fffff : ZBT SSRAM1
       *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
       *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
       *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
 +     * AN385/AN386 only:
       *  0x01000000 .. 0x01003fff : block RAM (16K)
       *  0x01004000 .. 0x01007fff : mirror of above
       *  0x01008000 .. 0x0100bfff : mirror of above
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
       *  0x00400000 .. 0x007fffff : ZBT SSRAM1
       *  0x20000000 .. 0x2001ffff : SRAM
       *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
 +     * AN500 only:
 +     *  0x60000000 .. 0x60ffffff : PSRAM (16MB)
       *
       * The AN385/AN386 has a feature where the lowest 16K can be mapped
       * either to the bottom of the ZBT SSRAM1 or to the block RAM.
       * This is of no use for QEMU so we don't implement it (as if
       * zbt_boot_ctrl is always zero).
       */
 -    memory_region_add_subregion(system_memory, 0x21000000, machine->ram);
 +    memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram);
 -    switch (mmc->fpga_type) {
 -    case FPGA_AN385:
 -    case FPGA_AN386:
 -        make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
 -        make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
 -        make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
 -        make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
 -                       &mms->ssram23, 0x20400000);
 +    if (mmc->has_block_ram) {
          make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
          make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
                         &mms->blockram, 0x01004000);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
                         &mms->blockram, 0x01008000);
          make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
                         &mms->blockram, 0x0100c000);
 +    }
 +
-+    switch (mmc->fpga_type) {
++    switch (addr) {
-+    case FPGA_AN385:
++    case 0xe10: /* ERRIIDR */
-+    case FPGA_AN386:
++        /* architect field = Arm; product/variant/revision 0 */
-+    case FPGA_AN500:
++        *data = 0x43b;
-+        make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
++        break;
-+        make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
++    case 0xfc8: /* ERRDEVID */
-+        make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
++        /* Minimal RAS: we implement 0 error record indexes */
-+        make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
++        *data = 0;
-+                       &mms->ssram23, 0x20400000);
++        break;
-         break;
++    default:
-     case FPGA_AN511:
++        qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
-         make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
++                      (uint32_t)addr);
-@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
++        *data = 0;
-     switch (mmc->fpga_type) {
++        break;
-     case FPGA_AN385:
++    }
-     case FPGA_AN386:
++    return MEMTX_OK;
 +    case FPGA_AN500:
          qdev_prop_set_uint32(armv7m, "num-irq", 32);
          break;
      case FPGA_AN511:
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      switch (mmc->fpga_type) {
      case FPGA_AN385:
      case FPGA_AN386:
 +    case FPGA_AN500:
      {
          /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
           * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      /* In hardware this is a LAN9220; the LAN9118 is software compatible
       * except that it doesn't support the checksum-offload feature.
       */
 -    lan9118_init(&nd_table[0], 0x40200000,
 +    lan9118_init(&nd_table[0], mmc->ethernet_base,
                   qdev_get_gpio_in(armv7m,
                                    mmc->fpga_type == FPGA_AN511 ? 47 : 13));
@@ -XXX,XX +XXX,XX @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
      mmc->fpga_type = FPGA_AN385;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
      mmc->scc_id = 0x41043850;
 +    mmc->psram_base = 0x21000000;
 +    mmc->ethernet_base = 0x40200000;
 +    mmc->has_block_ram = true;
  }
  static void mps2_an386_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void mps2_an386_class_init(ObjectClass *oc, void *data)
      mmc->fpga_type = FPGA_AN386;
      mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
      mmc->scc_id = 0x41043860;
 +    mmc->psram_base = 0x21000000;
 +    mmc->ethernet_base = 0x40200000;
 +    mmc->has_block_ram = true;
 +}
 +
-+static void mps2_an500_class_init(ObjectClass *oc, void *data)
++static MemTxResult ras_write(void *opaque, hwaddr addr,
 +                             uint64_t value, unsigned size,
 +                             MemTxAttrs attrs)
 +{
-+    MachineClass *mc = MACHINE_CLASS(oc);
++    if (attrs.user) {
-+    MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
++        return MEMTX_ERROR;
 +    }
 +
-+    mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
++    switch (addr) {
-+    mmc->fpga_type = FPGA_AN500;
++    default:
-+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
++        qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
-+    mmc->scc_id = 0x41045000;
++                      (uint32_t)addr);
-+    mmc->psram_base = 0x60000000;
++        break;
-+    mmc->ethernet_base = 0xa0000000;
++    }
-+    mmc->has_block_ram = false;
++    return MEMTX_OK;
- }
++}
++
- static void mps2_an511_class_init(ObjectClass *oc, void *data)
++static const MemoryRegionOps ras_ops = {
-@@ -XXX,XX +XXX,XX @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)
++    .read_with_attrs = ras_read,
-     mmc->fpga_type = FPGA_AN511;
++    .write_with_attrs = ras_write,
-     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
++    .endianness = DEVICE_NATIVE_ENDIAN,
      mmc->scc_id = 0x41045110;
 +    mmc->psram_base = 0x21000000;
 +    mmc->ethernet_base = 0x40200000;
 +    mmc->has_block_ram = false;
  }
  static const TypeInfo mps2_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo mps2_an386_info = {
      .class_init = mps2_an386_class_init,
  };
 +static const TypeInfo mps2_an500_info = {
 +    .name = TYPE_MPS2_AN500_MACHINE,
 +    .parent = TYPE_MPS2_MACHINE,
 +    .class_init = mps2_an500_class_init,
 +};
 +
- static const TypeInfo mps2_an511_info = {
+ /*
-     .name = TYPE_MPS2_AN511_MACHINE,
+  * Unassigned portions of the PPB space are RAZ/WI for privileged
-     .parent = TYPE_MPS2_MACHINE,
+  * accesses, and fault for non-privileged accesses.
-@@ -XXX,XX +XXX,XX @@ static void mps2_machine_init(void)
+@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
-     type_register_static(&mps2_info);
+                                             &s->systick_ns_mem, 1);
-     type_register_static(&mps2_an385_info);
+     }
-     type_register_static(&mps2_an386_info);
-+    type_register_static(&mps2_an500_info);
++    if (cpu_isar_feature(aa32_ras, s->cpu)) {
-     type_register_static(&mps2_an511_info);
++        memory_region_init_io(&s->ras_mem, OBJECT(s),
 +                              &ras_ops, s, "nvic_ras", 0x1000);
 +        memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
 +    }
 +
      sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
  }
 --
 .20.1

-[PULL 14/36] docs/system/arm/mps2.rst: Make board list consistent
+[PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name
-Make the list of MPS2 boards consistent in the phrasing of each
+Correct a typo in the name we give the NVIC object.
 entry, use the correct casing of "Arm", and move the mps2-an511
 entry so the list is in numeric order.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200903202048.15370-4-peter.maydell@linaro.org
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20201119215617.29887-28-peter.maydell@linaro.org
 ---
- docs/system/arm/mps2.rst | 14 +++++++-------
+ hw/arm/armv7m.c | 2 +-
-file changed, 7 insertions(+), 7 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
+diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/arm/mps2.rst
+--- a/hw/arm/armv7m.c
-+++ b/docs/system/arm/mps2.rst
++++ b/hw/arm/armv7m.c
-@@ -XXX,XX +XXX,XX @@ as seen by the guest depend significantly on the FPGA image.
+@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
- QEMU models the following FPGA images:
+     memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
- ``mps2-an385``
--  Cortex-M3 as documented in ARM Application Note AN385
+-    object_initialize_child(obj, "nvnic", &s->nvic, TYPE_NVIC);
-+  Cortex-M3 as documented in Arm Application Note AN385
++    object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC);
- ``mps2-an386``
+     object_property_add_alias(obj, "num-irq",
--  Cortex-M4 as documented in ARM Application Note AN386
+                               OBJECT(&s->nvic), "num-irq");
 +  Cortex-M4 as documented in Arm Application Note AN386
  ``mps2-an500``
 -  Cortex-M7 as documented in ARM Application Note AN500
 -``mps2-an511``
 -  Cortex-M3 'DesignStart' as documented in AN511
 +  Cortex-M7 as documented in Arm Application Note AN500
  ``mps2-an505``
 -  Cortex-M33 as documented in ARM Application Note AN505
 +  Cortex-M33 as documented in Arm Application Note AN505
 +``mps2-an511``
 +  Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
  ``mps2-an521``
 -  Dual Cortex-M33 as documented in Application Note AN521
 +  Dual Cortex-M33 as documented in Arm Application Note AN521
  Differences between QEMU and real hardware:
 --
 .20.1

Nuvoton new board models, and some more minor stuff. I also put
in the deprecation patches for unicore32 and lm32.

thanks
-- PMM

The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914

for you to fetch changes up to dd44ae00fc5342ed99acb68ec3508f76a71d523a:

MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller (2020-09-14 14:27:08 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/misc/a9scu: Do not allow invalid CPU count
 * hw/misc/a9scu: Minor cleanups
 * hw/timer/armv7m_systick: assert that board code set system_clock_scale
 * decodetree: Improve identifier matching
 * target/arm: Clean up neon fp insn size field decode
 * target/arm: Remove KVM support for 32-bit Arm hosts
 * hw/arm/mps2: New board models mps2-an386, mps2-an500
 * Deprecate Unicore32 port
 * Deprecate lm32 port
 * target/arm: Count PMU events when MDCR.SPME is set
 * hw/arm: versal-virt: Correct the tx/rx GEM clocks
 * New Nuvoton iBMC board models npcm750-evb, quanta-gsj
 * xlnx-zynqmp: implement ZynqMP CAN controllers

----------------------------------------------------------------
Aaron Lindsay (1):
      target/arm: Count PMU events when MDCR.SPME is set

Edgar E. Iglesias (1):
      hw/arm: versal-virt: Correct the tx/rx GEM clocks

Havard Skinnemoen (14):
      hw/misc: Add NPCM7xx System Global Control Registers device model
      hw/misc: Add NPCM7xx Clock Controller device model
      hw/timer: Add NPCM7xx Timer device model
      hw/arm: Add NPCM730 and NPCM750 SoC models
      hw/arm: Add two NPCM7xx-based machines
      roms: Add virtual Boot ROM for NPCM7xx SoCs
      hw/arm: Load -bios image as a boot ROM for npcm7xx
      hw/nvram: NPCM7xx OTP device model
      hw/mem: Stubbed out NPCM7xx Memory Controller model
      hw/ssi: NPCM7xx Flash Interface Unit device model
      hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
      hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
      docs/system: Add Nuvoton machine documentation
      tests/acceptance: console boot tests for quanta-gsj

Peter Maydell (11):
      hw/timer/armv7m_systick: assert that board code set system_clock_scale
      target/arm: Convert Neon 3-same-fp size field to MO_* in decode
      target/arm: Convert Neon VCVT fp size field to MO_* in decode
      target/arm: Convert VCMLA, VCADD size field to MO_* in decode
      target/arm: Remove KVM support for 32-bit Arm hosts
      target/arm: Remove no-longer-reachable 32-bit KVM code
      hw/arm/mps2: New board model mps2-an386
      hw/arm/mps2: New board model mps2-an500
      docs/system/arm/mps2.rst: Make board list consistent
      Deprecate Unicore32 port
      Deprecate lm32 port

Philippe Mathieu-Daudé (4):
      hw/misc/a9scu: Do not allow invalid CPU count
      hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
      hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
      hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)

Richard Henderson (1):
      decodetree: Improve identifier matching

Vikram Garhwal (4):
      hw/net/can: Introduce Xilinx ZynqMP CAN controller
      xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
      tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
      MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller

docs/system/arm/mps2.rst               |   20 +-
 docs/system/arm/nuvoton.rst            |   92 +++
 docs/system/deprecated.rst             |   32 +-
 docs/system/target-arm.rst             |    1 +
 configure                              |    2 +-
 default-configs/arm-softmmu.mak        |    1 +
 include/hw/arm/npcm7xx.h               |  112 +++
 include/hw/arm/xlnx-zynqmp.h           |    8 +
 include/hw/mem/npcm7xx_mc.h            |   36 +
 include/hw/misc/npcm7xx_clk.h          |   48 ++
 include/hw/misc/npcm7xx_gcr.h          |   43 ++
 include/hw/net/xlnx-zynqmp-can.h       |   78 +++
 include/hw/nvram/npcm7xx_otp.h         |   79 +++
 include/hw/ssi/npcm7xx_fiu.h           |   73 ++
 include/hw/timer/npcm7xx_timer.h       |   78 +++
 target/arm/kvm-consts.h                |    7 -
 target/arm/kvm_arm.h                   |    6 -
 target/arm/neon-dp.decode              |   18 +-
 target/arm/neon-shared.decode          |   18 +-
 tests/decode/succ_ident1.decode        |    7 +
 hw/arm/mps2.c                          |   97 ++-
 hw/arm/npcm7xx.c                       |  532 +++++++++++++++
 hw/arm/npcm7xx_boards.c                |  197 ++++++
 hw/arm/xlnx-versal-virt.c              |    2 +-
 hw/arm/xlnx-zcu102.c                   |   20 +
 hw/arm/xlnx-zynqmp.c                   |   34 +
 hw/mem/npcm7xx_mc.c                    |   84 +++
 hw/misc/a9scu.c                        |   59 +-
 hw/misc/npcm7xx_clk.c                  |  266 ++++++++
 hw/misc/npcm7xx_gcr.c                  |  269 ++++++++
 hw/net/can/xlnx-zynqmp-can.c           | 1165 ++++++++++++++++++++++++++++++++
 hw/nvram/npcm7xx_otp.c                 |  440 ++++++++++++
 hw/ssi/npcm7xx_fiu.c                   |  572 ++++++++++++++++
 hw/timer/armv7m_systick.c              |    8 +
 hw/timer/npcm7xx_timer.c               |  543 +++++++++++++++
 target/arm/cpu.c                       |  101 ++-
 target/arm/helper.c                    |    2 +-
 target/arm/kvm.c                       |    7 -
 target/arm/kvm32.c                     |  595 ----------------
 tests/qtest/xlnx-can-test.c            |  359 ++++++++++
 .gitmodules                            |    3 +
 MAINTAINERS                            |   18 +
 hw/arm/Kconfig                         |    9 +
 hw/arm/meson.build                     |    1 +
 hw/mem/meson.build                     |    1 +
 hw/misc/meson.build                    |    4 +
 hw/misc/trace-events                   |    8 +
 hw/net/can/meson.build                 |    1 +
 hw/nvram/meson.build                   |    1 +
 hw/ssi/meson.build                     |    1 +
 hw/ssi/trace-events                    |   11 +
 hw/timer/meson.build                   |    1 +
 hw/timer/trace-events                  |    5 +
 pc-bios/README                         |    6 +
 pc-bios/meson.build                    |    1 +
 pc-bios/npcm7xx_bootrom.bin            |  Bin 0 -> 768 bytes
 roms/Makefile                          |    7 +
 roms/vbootrom                          |    1 +
 scripts/decodetree.py                  |   46 +-
 target/arm/meson.build                 |    5 +-
 target/arm/translate-neon.c.inc        |   42 +-
 tests/acceptance/boot_linux_console.py |   83 +++
 tests/qtest/meson.build                |    1 +
 63 files changed, 5584 insertions(+), 783 deletions(-)
 create mode 100644 docs/system/arm/nuvoton.rst
 create mode 100644 include/hw/arm/npcm7xx.h
 create mode 100644 include/hw/mem/npcm7xx_mc.h
 create mode 100644 include/hw/misc/npcm7xx_clk.h
 create mode 100644 include/hw/misc/npcm7xx_gcr.h
 create mode 100644 include/hw/net/xlnx-zynqmp-can.h
 create mode 100644 include/hw/nvram/npcm7xx_otp.h
 create mode 100644 include/hw/ssi/npcm7xx_fiu.h
 create mode 100644 include/hw/timer/npcm7xx_timer.h
 create mode 100644 tests/decode/succ_ident1.decode
 create mode 100644 hw/arm/npcm7xx.c
 create mode 100644 hw/arm/npcm7xx_boards.c
 create mode 100644 hw/mem/npcm7xx_mc.c
 create mode 100644 hw/misc/npcm7xx_clk.c
 create mode 100644 hw/misc/npcm7xx_gcr.c
 create mode 100644 hw/net/can/xlnx-zynqmp-can.c
 create mode 100644 hw/nvram/npcm7xx_otp.c
 create mode 100644 hw/ssi/npcm7xx_fiu.c
 create mode 100644 hw/timer/npcm7xx_timer.c
 delete mode 100644 target/arm/kvm32.c
 create mode 100644 tests/qtest/xlnx-can-test.c
 create mode 100644 pc-bios/npcm7xx_bootrom.bin
 create mode 160000 roms/vbootrom

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Per the datasheet (DDI0407 r2p0):

"The SCU connects one to four Cortex-A9 processors to
   the memory system through the AXI interfaces."

Change the instance_init() handler to a device_realize()
one so we can verify the property is in range, and return
an error to the caller if not.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/a9scu.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/a9scu.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
+#include "qapi/error.h"
 #include "qemu/module.h"
 
+#define A9_SCU_CPU_MAX  4
+
 static uint64_t a9_scu_read(void *opaque, hwaddr offset,
                             unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static void a9_scu_reset(DeviceState *dev)
     s->control = 0;
 }
 
-static void a9_scu_init(Object *obj)
+static void a9_scu_realize(DeviceState *dev, Error **errp)
 {
-    A9SCUState *s = A9_SCU(obj);
-    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    A9SCUState *s = A9_SCU(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
-    memory_region_init_io(&s->iomem, obj, &a9_scu_ops, s,
+    if (!s->num_cpu || s->num_cpu > A9_SCU_CPU_MAX) {
+        error_setg(errp, "Illegal CPU count: %u", s->num_cpu);
+        return;
+    }
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &a9_scu_ops, s,
                           "a9-scu", 0x100);
     sysbus_init_mmio(sbd, &s->iomem);
 }
@@ -XXX,XX +XXX,XX @@ static void a9_scu_class_init(ObjectClass *klass, void *data)
     device_class_set_props(dc, a9_scu_properties);
     dc->vmsd = &vmstate_a9_scu;
     dc->reset = a9_scu_reset;
+    dc->realize = a9_scu_realize;
 }
 
 static const TypeInfo a9_scu_info = {
     .name          = TYPE_A9_SCU,
     .parent        = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(A9SCUState),
-    .instance_init = a9_scu_init,
     .class_init    = a9_scu_class_init,
 };
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Per the datasheet (DDI0407 r2p0):

"All SCU registers are byte accessible" and are 32-bit aligned.

Set MemoryRegionOps::valid min/max fields and simplify the write()
handler.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/a9scu.c | 21 +++++----------------
 1 file changed, 5 insertions(+), 16 deletions(-)

diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
 {
     A9SCUState *s = (A9SCUState *)opaque;
-    uint32_t mask;
+    uint32_t mask = MAKE_64BIT_MASK(0, size * 8);
     uint32_t shift;
-    switch (size) {
-    case 1:
-        mask = 0xff;
-        break;
-    case 2:
-        mask = 0xffff;
-        break;
-    case 4:
-        mask = 0xffffffff;
-        break;
-    default:
-        fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n",
-                size, (unsigned)offset);
-        return;
-    }
 
     switch (offset) {
     case 0x00: /* Control */
@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
 static const MemoryRegionOps a9_scu_ops = {
     .read = a9_scu_read,
     .write = a9_scu_write,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 4,
+    },
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

This model implementation is designed for 32-bit accesses.
We can simplify setting the MemoryRegionOps::impl min/max
fields to 32-bit (memory::access_with_adjusted_size() will
take care of the 8/16-bit accesses).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/a9scu.c | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -XXX,XX +XXX,XX @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset,
         return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
     case 0x08: /* CPU Power Status */
         return s->status;
-    case 0x09: /* CPU status.  */
-        return s->status >> 8;
-    case 0x0a: /* CPU status.  */
-        return s->status >> 16;
-    case 0x0b: /* CPU status.  */
-        return s->status >> 24;
     case 0x0c: /* Invalidate All Registers In Secure State */
         return 0;
     case 0x40: /* Filtering Start Address Register */
@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
 {
     A9SCUState *s = (A9SCUState *)opaque;
-    uint32_t mask = MAKE_64BIT_MASK(0, size * 8);
-    uint32_t shift;
 
     switch (offset) {
     case 0x00: /* Control */
@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
     case 0x4: /* Configuration: RO */
         break;
     case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
-        shift = (offset - 0x8) * 8;
-        s->status &= ~(mask << shift);
-        s->status |= ((value & mask) << shift);
+        s->status = value;
         break;
     case 0x0c: /* Invalidate All Registers In Secure State */
         /* no-op as we do not implement caches */
@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
 static const MemoryRegionOps a9_scu_ops = {
     .read = a9_scu_read,
     .write = a9_scu_write,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
     .valid = {
         .min_access_size = 1,
         .max_access_size = 4,
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Report unimplemented register accesses using qemu_log_mask(UNIMP).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200901144100.116742-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/a9scu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/a9scu.c
+++ b/hw/misc/a9scu.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "qapi/error.h"
+#include "qemu/log.h"
 #include "qemu/module.h"
 
 #define A9_SCU_CPU_MAX  4
@@ -XXX,XX +XXX,XX @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset,
     case 0x54: /* SCU Non-secure Access Control Register */
         /* unimplemented, fall through */
     default:
+        qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n",
+                      __func__, offset);
         return 0;
     }
 }
@@ -XXX,XX +XXX,XX @@ static void a9_scu_write(void *opaque, hwaddr offset,
     case 0x54: /* SCU Non-secure Access Control Register */
         /* unimplemented, fall through */
     default:
+        qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx
+                                 " value 0x%"PRIx64"\n",
+                      __func__, offset, value);
         break;
     }
 }
-- 
2.20.1

It is the responsibility of board code for an armv7m system to set
system_clock_scale appropriately for the CPU speed of the core.
If it forgets to do this, then QEMU will hang if the guest tries
to use the systick timer in the "tick at the CPU clock frequency" mode.

We forgot that in a couple of our boards (see commits ce4f70e81ed23c93f,
e7e5a9595ab1136). Add an assertion in the systick reset method so
we don't let any new boards in with the same bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200825160847.18091-1-peter.maydell@linaro.org
---
 hw/timer/armv7m_systick.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/armv7m_systick.c
+++ b/hw/timer/armv7m_systick.c
@@ -XXX,XX +XXX,XX @@ static void systick_reset(DeviceState *dev)
 {
     SysTickState *s = SYSTICK(dev);
 
+    /*
+     * Forgetting to set system_clock_scale is always a board code
+     * bug. We can't check this earlier because for some boards
+     * (like stellaris) it is not yet configured at the point where
+     * the systick device is realized.
+     */
+    assert(system_clock_scale != 0);
+
     s->control = 0;
     s->reload = 0;
     s->tick = 0;
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Only argument set members have to be C identifiers, everything
else gets prefixed during conversion to C.  Some places just
checked the leading character, and some places matched a leading
character plus a C identifier.

Convert everything to match full identifiers, including the
[&%@&] prefix, and drop the full C identifier requirement.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903192334.1603773-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/decode/succ_ident1.decode |  7 +++++
 scripts/decodetree.py           | 46 +++++++++++++++++++++------------
 2 files changed, 37 insertions(+), 16 deletions(-)
 create mode 100644 tests/decode/succ_ident1.decode

diff --git a/tests/decode/succ_ident1.decode b/tests/decode/succ_ident1.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/decode/succ_ident1.decode
@@ -XXX,XX +XXX,XX @@
+%1f   0:8
+%2f   8:8
+%3f   16:8
+
+&3arg a b c
+@3arg ........ ........ ........ ........  &3arg a=%1f b=%2f c=%3f
+3insn 00000000 ........ ........ ........  @3arg
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index XXXXXXX..XXXXXXX 100644
--- a/scripts/decodetree.py
+++ b/scripts/decodetree.py
@@ -XXX,XX +XXX,XX @@ output_fd = None
 insntype = 'uint32_t'
 decode_function = 'decode'
 
-re_ident = '[a-zA-Z][a-zA-Z0-9_]*'
+# An identifier for C.
+re_C_ident = '[a-zA-Z][a-zA-Z0-9_]*'
 
+# Identifiers for Arguments, Fields, Formats and Patterns.
+re_arg_ident = '&[a-zA-Z0-9_]*'
+re_fld_ident = '%[a-zA-Z0-9_]*'
+re_fmt_ident = '@[a-zA-Z0-9_]*'
+re_pat_ident = '[a-zA-Z0-9_]*'
 
 def error_with_file(file, lineno, *args):
     """Print an error message from file:line and args and exit."""
@@ -XXX,XX +XXX,XX @@ class ExcMultiPattern(MultiPattern):
 def parse_field(lineno, name, toks):
     """Parse one instruction field from TOKS at LINENO"""
     global fields
-    global re_ident
     global insnwidth
 
     # A "simple" field will have only one entry;
@@ -XXX,XX +XXX,XX @@ def parse_field(lineno, name, toks):
     width = 0
     func = None
     for t in toks:
-        if re.fullmatch('!function=' + re_ident, t):
+        if re.match('^!function=', t):
             if func:
                 error(lineno, 'duplicate function')
             func = t.split('=')
@@ -XXX,XX +XXX,XX @@ def parse_field(lineno, name, toks):
 def parse_arguments(lineno, name, toks):
     """Parse one argument set from TOKS at LINENO"""
     global arguments
-    global re_ident
+    global re_C_ident
     global anyextern
 
     flds = []
@@ -XXX,XX +XXX,XX @@ def parse_arguments(lineno, name, toks):
             extern = True
             anyextern = True
             continue
-        if not re.fullmatch(re_ident, t):
+        if not re.fullmatch(re_C_ident, t):
             error(lineno, 'invalid argument set token "{0}"'.format(t))
         if t in flds:
             error(lineno, 'duplicate argument "{0}"'.format(t))
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
     global arguments
     global formats
     global allpatterns
-    global re_ident
+    global re_arg_ident
+    global re_fld_ident
+    global re_fmt_ident
+    global re_C_ident
     global insnwidth
     global insnmask
     global variablewidth
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
     fmt = None
     for t in toks:
         # '&Foo' gives a format an explcit argument set.
-        if t[0] == '&':
+        if re.fullmatch(re_arg_ident, t):
             tt = t[1:]
             if arg:
                 error(lineno, 'multiple argument sets')
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
             continue
 
         # '@Foo' gives a pattern an explicit format.
-        if t[0] == '@':
+        if re.fullmatch(re_fmt_ident, t):
             tt = t[1:]
             if fmt:
                 error(lineno, 'multiple formats')
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
             continue
 
         # '%Foo' imports a field.
-        if t[0] == '%':
+        if re.fullmatch(re_fld_ident, t):
             tt = t[1:]
             flds = add_field_byname(lineno, flds, tt, tt)
             continue
 
         # 'Foo=%Bar' imports a field with a different name.
-        if re.fullmatch(re_ident + '=%' + re_ident, t):
+        if re.fullmatch(re_C_ident + '=' + re_fld_ident, t):
             (fname, iname) = t.split('=%')
             flds = add_field_byname(lineno, flds, fname, iname)
             continue
 
         # 'Foo=number' sets an argument field to a constant value
-        if re.fullmatch(re_ident + '=[+-]?[0-9]+', t):
+        if re.fullmatch(re_C_ident + '=[+-]?[0-9]+', t):
             (fname, value) = t.split('=')
             value = int(value)
             flds = add_field(lineno, flds, fname, ConstField(value))
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
             fixedmask = (fixedmask << shift) | fms
             undefmask = (undefmask << shift) | ubm
         # Otherwise, fieldname:fieldwidth
-        elif re.fullmatch(re_ident + ':s?[0-9]+', t):
+        elif re.fullmatch(re_C_ident + ':s?[0-9]+', t):
             (fname, flen) = t.split(':')
             sign = False
             if flen[0] == 's':
@@ -XXX,XX +XXX,XX @@ def parse_generic(lineno, parent_pat, name, toks):
 
 def parse_file(f, parent_pat):
     """Parse all of the patterns within a file"""
+    global re_arg_ident
+    global re_fld_ident
+    global re_fmt_ident
+    global re_pat_ident
 
     # Read all of the lines of the file.  Concatenate lines
     # ending in backslash; discard empty lines and comments.
@@ -XXX,XX +XXX,XX @@ def parse_file(f, parent_pat):
             continue
 
         # Determine the type of object needing to be parsed.
-        if name[0] == '%':
+        if re.fullmatch(re_fld_ident, name):
             parse_field(start_lineno, name[1:], toks)
-        elif name[0] == '&':
+        elif re.fullmatch(re_arg_ident, name):
             parse_arguments(start_lineno, name[1:], toks)
-        elif name[0] == '@':
+        elif re.fullmatch(re_fmt_ident, name):
             parse_generic(start_lineno, None, name[1:], toks)
-        else:
+        elif re.fullmatch(re_pat_ident, name):
             parse_generic(start_lineno, parent_pat, name, toks)
+        else:
+            error(lineno, 'invalid token "{0}"'.format(name))
         toks = []
 
     if nesting != 0:
-- 
2.20.1

In the Neon instructions, some instruction formats have a 2-bit size
field which corresponds exactly to QEMU's MO_8/16/32/64.  However the
floating-point insns in the 3-same group have a 1-bit size field
which is "0 for 32-bit float and 1 for 16-bit float".  Currently we
pass these values directly through to trans_ functions, which means
that when reading a particular trans_ function you need to know if
that insn uses a 2-bit size or a 1-bit size.

Move the handling of the 1-bit size to the decodetree file, so that
all these insns consistently pass a size to the trans_ function which
is an MO_8/16/32/64 value.

In this commit we switch over the insns using the 3same_fp and
3same_fp_q0 formats.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-2-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 15 ++++++++++-----
 target/arm/translate-neon.c.inc | 16 +++++++++++-----
 2 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
 @3same_q0        .... ... . . . size:2 .... .... .... . 0 . . .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
 
-# For FP insns the high bit of 'size' is used as part of opcode decode
-@3same_fp        .... ... . . . . size:1 .... .... .... . q:1 . . .... \
-                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
-@3same_fp_q0     .... ... . . . . size:1 .... .... .... . 0 . . .... \
-                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
+# For FP insns the high bit of 'size' is used as part of opcode decode,
+# and the 'size' bit is 0 for 32-bit float and 1 for 16-bit float.
+# This converts this encoding to the same MO_8/16/32/64 values that the
+# integer neon insns use.
+%3same_fp_size   20:1 !function=neon_3same_fp_size
+
+@3same_fp        .... ... . . . . . .... .... .... . q:1 . . .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%3same_fp_size
+@3same_fp_q0     .... ... . . . . . .... .... .... . 0 . . .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 size=%3same_fp_size
 
 VHADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
 VHADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static inline int rsub_8(DisasContext *s, int x)
     return 8 - x;
 }
 
+static inline int neon_3same_fp_size(DisasContext *s, int x)
+{
+    /* Convert 0==fp32, 1==fp16 into a MO_* value */
+    return MO_32 - x;
+}
+
 /* Include the generated Neon decoder */
 #include "decode-neon-dp.c.inc"
 #include "decode-neon-ls.c.inc"
@@ -XXX,XX +XXX,XX @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
     WRAP_FP_GVEC(gen_##INSN##_fp16_3s, FPST_STD_F16, HFUNC)             \
     static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a)     \
     {                                                                   \
-        if (a->size != 0) {                                             \
+        if (a->size == MO_16) {                                         \
             if (!dc_isar_feature(aa32_fp16_arith, s)) {                 \
                 return false;                                           \
             }                                                           \
@@ -XXX,XX +XXX,XX @@ static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a)
         return false;
     }
 
-    if (a->size != 0) {
+    if (a->size == MO_16) {
         if (!dc_isar_feature(aa32_fp16_arith, s)) {
             return false;
         }
@@ -XXX,XX +XXX,XX @@ static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a)
         return false;
     }
 
-    if (a->size != 0) {
+    if (a->size == MO_16) {
         if (!dc_isar_feature(aa32_fp16_arith, s)) {
             return false;
         }
@@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a,
     assert(a->q == 0); /* enforced by decode patterns */
 
 
-    fpstatus = fpstatus_ptr(a->size != 0 ? FPST_STD_F16 : FPST_STD);
+    fpstatus = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
     tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
                        vfp_reg_offset(1, a->vn),
                        vfp_reg_offset(1, a->vm),
@@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a,
 #define DO_3S_FP_PAIR(INSN,FUNC)                                    \
     static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
     {                                                               \
-        if (a->size != 0) {                                         \
+        if (a->size == MO_16) {                                     \
             if (!dc_isar_feature(aa32_fp16_arith, s)) {             \
                 return false;                                       \
             }                                                       \
-- 
2.20.1

Convert the insns using the 2reg_vcvt and 2reg_vcvt_f16 formats
to pass the size through to the trans function as a MO_* value
rather than the '0==f32, 1==f16' used in the fp 3-same encodings.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-3-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 3 +--
 target/arm/translate-neon.c.inc | 4 ++--
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s     1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
 @2reg_shll_b     .... ... . . . 001 shift:3  .... .... 0 . . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
 
-# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
 @2reg_vcvt       .... ... . . . 1 ..... .... .... . q:1 . . .... \
-                 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
+                 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
 @2reg_vcvt_f16   .... ... . . . 11 .... .... .... . q:1 . . .... \
                  &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
 
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
         return false;
     }
 
-    if (a->size != 0) {
+    if (a->size == MO_16) {
         if (!dc_isar_feature(aa32_fp16_arith, s)) {
             return false;
         }
@@ -XXX,XX +XXX,XX @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
         return true;
     }
 
-    fpst = fpstatus_ptr(a->size ? FPST_STD_F16 : FPST_STD);
+    fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
     tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, vec_size, vec_size, a->shift, fn);
     tcg_temp_free_ptr(fpst);
     return true;
-- 
2.20.1

The VCMLA and VCADD insns have a size field which is 0 for fp16
and 1 for fp32 (note that this is the reverse of the Neon 3-same
encoding!). Convert it to MO_* values in decode for consistency.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-4-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   | 18 ++++++++++++------
 target/arm/translate-neon.c.inc | 22 ++++++++++++----------
 2 files changed, 24 insertions(+), 16 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@
 %vd_dp  22:1 12:4
 %vd_sp  12:4 22:1
 
-VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
-               vm=%vm_dp vn=%vn_dp vd=%vd_dp
+# For VCMLA/VCADD insns, convert the single-bit size field
+# which is 0 for fp16 and 1 for fp32 into a MO_* constant.
+# (Note that this is the reverse of the sense of the 1-bit size
+# field in the 3same_fp Neon insns.)
+%vcadd_size    20:1 !function=plus1
 
-VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
-               vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VCMLA          1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
+
+VCADD          1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size
 
 # VUDOT and VSDOT
 VDOT           1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
@@ -XXX,XX +XXX,XX @@ VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
 
 VCMLA_scalar   1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
-               vn=%vn_dp vd=%vd_dp size=0
+               vn=%vn_dp vd=%vd_dp size=1
 VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
-               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=2 index=0
 
 VDOT_scalar    1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
     gen_helper_gvec_3_ptr *fn_gvec_ptr;
 
     if (!dc_isar_feature(aa32_vcma, s)
-        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+        || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
     }
 
     opr_sz = (1 + a->q) * 8;
-    fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD);
-    fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
+    fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
+    fn_gvec_ptr = (a->size == MO_16) ?
+        gen_helper_gvec_fcmlah : gen_helper_gvec_fcmlas;
     tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
                        vfp_reg_offset(1, a->vn),
                        vfp_reg_offset(1, a->vm),
@@ -XXX,XX +XXX,XX @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
     gen_helper_gvec_3_ptr *fn_gvec_ptr;
 
     if (!dc_isar_feature(aa32_vcma, s)
-        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+        || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
     }
 
     opr_sz = (1 + a->q) * 8;
-    fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD);
-    fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
+    fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
+    fn_gvec_ptr = (a->size == MO_16) ?
+        gen_helper_gvec_fcaddh : gen_helper_gvec_fcadds;
     tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
                        vfp_reg_offset(1, a->vn),
                        vfp_reg_offset(1, a->vm),
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
     if (!dc_isar_feature(aa32_vcma, s)) {
         return false;
     }
-    if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
+    if (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s)) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
         return true;
     }
 
-    fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
-                   : gen_helper_gvec_fcmlah_idx);
+    fn_gvec_ptr = (a->size == MO_16) ?
+        gen_helper_gvec_fcmlah_idx : gen_helper_gvec_fcmlas_idx;
     opr_sz = (1 + a->q) * 8;
-    fpst = fpstatus_ptr(a->size == 0 ? FPST_STD_F16 : FPST_STD);
+    fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
     tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
                        vfp_reg_offset(1, a->vn),
                        vfp_reg_offset(1, a->vm),
-- 
2.20.1

We deprecated the support for KVM on 32-bit Arm hosts in time
for release 5.0, which means that our deprecation policy allows
us to drop it in release 5.2. Remove the code.

To repeat the rationale from the deprecation note: the Linux
kernel dropped support for 32-bit Arm KVM hosts in 5.7.

Running 32-bit guests on a 64-bit Arm host remains supported.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200904154156.31943-2-peter.maydell@linaro.org
---
 docs/system/deprecated.rst |  16 +-
 configure                  |   2 +-
 target/arm/kvm32.c         | 595 -------------------------------------
 target/arm/meson.build     |   5 +-
 4 files changed, 10 insertions(+), 608 deletions(-)
 delete mode 100644 target/arm/kvm32.c

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -XXX,XX +XXX,XX @@ The ``compat`` property used to set backwards compatibility modes for
 the processor has been deprecated. The ``max-cpu-compat`` property of
 the ``pseries`` machine type should be used instead.
 
-KVM guest support on 32-bit Arm hosts (since 5.0)
-'''''''''''''''''''''''''''''''''''''''''''''''''
-
-The Linux kernel has dropped support for allowing 32-bit Arm systems
-to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating
-its support for this configuration and will remove it in a future version.
-Running 32-bit guests on a 64-bit Arm host remains supported.
-
 System emulator devices
 -----------------------
 
@@ -XXX,XX +XXX,XX @@ should be used instead of the 1.09.1 version.
 System emulator CPUS
 --------------------
 
+KVM guest support on 32-bit Arm hosts (removed in 5.2)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The Linux kernel has dropped support for allowing 32-bit Arm systems
+to host KVM guests as of the 5.7 kernel. Accordingly, QEMU is deprecating
+its support for this configuration and will remove it in a future version.
+Running 32-bit guests on a 64-bit Arm host remains supported.
+
 RISC-V ISA Specific CPUs (removed in 5.1)
 '''''''''''''''''''''''''''''''''''''''''
 
diff --git a/configure b/configure
index XXXXXXX..XXXXXXX 100755
--- a/configure
+++ b/configure
@@ -XXX,XX +XXX,XX @@ supported_kvm_target() {
     test "$kvm" = "yes" || return 1
     glob "$1" "*-softmmu" || return 1
     case "${1%-softmmu}:$cpu" in
-        arm:arm | aarch64:aarch64 | \
+        aarch64:aarch64 | \
         i386:i386 | i386:x86_64 | i386:x32 | \
         x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \
         mips:mips | mipsel:mips | mips64:mips | mips64el:mips | \
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/target/arm/kvm32.c
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-/*
- * ARM implementation of KVM hooks, 32 bit specific code.
- *
- * Copyright Christoffer Dall 2009-2010
- *
- * This work is licensed under the terms of the GNU GPL, version 2 or later.
- * See the COPYING file in the top-level directory.
- *
- */
-
-#include "qemu/osdep.h"
-#include <sys/ioctl.h>
-
-#include <linux/kvm.h>
-
-#include "qemu-common.h"
-#include "cpu.h"
-#include "qemu/timer.h"
-#include "sysemu/runstate.h"
-#include "sysemu/kvm.h"
-#include "kvm_arm.h"
-#include "internals.h"
-#include "qemu/log.h"
-
-static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
-{
-    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
-
-    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
-    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
-}
-
-bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
-{
-    /* Identify the feature bits corresponding to the host CPU, and
-     * fill out the ARMHostCPUClass fields accordingly. To do this
-     * we have to create a scratch VM, create a single CPU inside it,
-     * and then query that CPU for the relevant ID registers.
-     */
-    int err = 0, fdarray[3];
-    uint32_t midr, id_pfr0;
-    uint64_t features = 0;
-
-    /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
-     * we know these will only support creating one kind of guest CPU,
-     * which is its preferred CPU type.
-     */
-    static const uint32_t cpus_to_try[] = {
-        QEMU_KVM_ARM_TARGET_CORTEX_A15,
-        QEMU_KVM_ARM_TARGET_NONE
-    };
-    /*
-     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
-     * to use the preferred target
-     */
-    struct kvm_vcpu_init init = { .target = -1, };
-
-    if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
-        return false;
-    }
-
-    ahcf->target = init.target;
-
-    /* This is not strictly blessed by the device tree binding docs yet,
-     * but in practice the kernel does not care about this string so
-     * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
-     */
-    ahcf->dtb_compatible = "arm,arm-v7";
-
-    err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
-    err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
-
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
-                          ARM_CP15_REG32(0, 0, 2, 0));
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
-                          ARM_CP15_REG32(0, 0, 2, 1));
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
-                          ARM_CP15_REG32(0, 0, 2, 2));
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
-                          ARM_CP15_REG32(0, 0, 2, 3));
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
-                          ARM_CP15_REG32(0, 0, 2, 4));
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
-                          ARM_CP15_REG32(0, 0, 2, 5));
-    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
-                       ARM_CP15_REG32(0, 0, 2, 7))) {
-        /*
-         * Older kernels don't support reading ID_ISAR6. This register was
-         * only introduced in ARMv8, so we can assume that it is zero on a
-         * CPU that a kernel this old is running on.
-         */
-        ahcf->isar.id_isar6 = 0;
-    }
-
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
-                          ARM_CP15_REG32(0, 0, 1, 2));
-
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
-                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
-                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
-                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
-                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
-    /*
-     * FIXME: There is not yet a way to read MVFR2.
-     * Fortunately there is not yet anything in there that affects migration.
-     */
-
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
-                          ARM_CP15_REG32(0, 0, 1, 4));
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
-                          ARM_CP15_REG32(0, 0, 1, 5));
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
-                          ARM_CP15_REG32(0, 0, 1, 6));
-    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
-                          ARM_CP15_REG32(0, 0, 1, 7));
-    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
-                       ARM_CP15_REG32(0, 0, 2, 6))) {
-        /*
-         * Older kernels don't support reading ID_MMFR4 (a new in v8
-         * register); assume it's zero.
-         */
-        ahcf->isar.id_mmfr4 = 0;
-    }
-
-    /*
-     * There is no way to read DBGDIDR, because currently 32-bit KVM
-     * doesn't implement debug at all. Leave it at zero.
-     */
-
-    kvm_arm_destroy_scratch_host_vcpu(fdarray);
-
-    if (err < 0) {
-        return false;
-    }
-
-    /* Now we've retrieved all the register information we can
-     * set the feature bits based on the ID register fields.
-     * We can assume any KVM supporting CPU is at least a v7
-     * with VFPv3, virtualization extensions, and the generic
-     * timers; this in turn implies most of the other feature
-     * bits, but a few must be tested.
-     */
-    features |= 1ULL << ARM_FEATURE_V7VE;
-    features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
-
-    if (extract32(id_pfr0, 12, 4) == 1) {
-        features |= 1ULL << ARM_FEATURE_THUMB2EE;
-    }
-    if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
-        features |= 1ULL << ARM_FEATURE_NEON;
-    }
-
-    ahcf->features = features;
-
-    return true;
-}
-
-bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
-{
-    /* Return true if the regidx is a register we should synchronize
-     * via the cpreg_tuples array (ie is not a core reg we sync by
-     * hand in kvm_arch_get/put_registers())
-     */
-    switch (regidx & KVM_REG_ARM_COPROC_MASK) {
-    case KVM_REG_ARM_CORE:
-    case KVM_REG_ARM_VFP:
-        return false;
-    default:
-        return true;
-    }
-}
-
-typedef struct CPRegStateLevel {
-    uint64_t regidx;
-    int level;
-} CPRegStateLevel;
-
-/* All coprocessor registers not listed in the following table are assumed to
- * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
- * often, you must add it to this table with a state of either
- * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
- */
-static const CPRegStateLevel non_runtime_cpregs[] = {
-    { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
-};
-
-int kvm_arm_cpreg_level(uint64_t regidx)
-{
-    int i;
-
-    for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
-        const CPRegStateLevel *l = &non_runtime_cpregs[i];
-        if (l->regidx == regidx) {
-            return l->level;
-        }
-    }
-
-    return KVM_PUT_RUNTIME_STATE;
-}
-
-#define ARM_CPU_ID_MPIDR       0, 0, 0, 5
-
-int kvm_arch_init_vcpu(CPUState *cs)
-{
-    int ret;
-    uint64_t v;
-    uint32_t mpidr;
-    struct kvm_one_reg r;
-    ARMCPU *cpu = ARM_CPU(cs);
-
-    if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
-        fprintf(stderr, "KVM is not supported for this guest CPU type\n");
-        return -EINVAL;
-    }
-
-    qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
-
-    /* Determine init features for this CPU */
-    memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
-    if (cs->start_powered_off) {
-        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
-    }
-    if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
-        cpu->psci_version = 2;
-        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
-    }
-
-    /* Do KVM_ARM_VCPU_INIT ioctl */
-    ret = kvm_arm_vcpu_init(cs);
-    if (ret) {
-        return ret;
-    }
-
-    /* Query the kernel to make sure it supports 32 VFP
-     * registers: QEMU's "cortex-a15" CPU is always a
-     * VFP-D32 core. The simplest way to do this is just
-     * to attempt to read register d31.
-     */
-    r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
-    r.addr = (uintptr_t)(&v);
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
-    if (ret == -ENOENT) {
-        return -EINVAL;
-    }
-
-    /*
-     * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
-     * Currently KVM has its own idea about MPIDR assignment, so we
-     * override our defaults with what we get from KVM.
-     */
-    ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
-    if (ret) {
-        return ret;
-    }
-    cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
-
-    /* Check whether userspace can specify guest syndrome value */
-    kvm_arm_init_serror_injection(cs);
-
-    return kvm_arm_init_cpreg_list(cpu);
-}
-
-int kvm_arch_destroy_vcpu(CPUState *cs)
-{
-	return 0;
-}
-
-typedef struct Reg {
-    uint64_t id;
-    int offset;
-} Reg;
-
-#define COREREG(KERNELNAME, QEMUFIELD)                       \
-    {                                                        \
-        KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
-        KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
-        offsetof(CPUARMState, QEMUFIELD)                     \
-    }
-
-#define VFPSYSREG(R)                                       \
-    {                                                      \
-        KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
-        KVM_REG_ARM_VFP_##R,                               \
-        offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
-    }
-
-/* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
-#define COREREG64(KERNELNAME, QEMUFIELD)                     \
-    {                                                        \
-        KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
-        KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
-        offsetoflow32(CPUARMState, QEMUFIELD)                \
-    }
-
-static const Reg regs[] = {
-    /* R0_usr .. R14_usr */
-    COREREG(usr_regs.uregs[0], regs[0]),
-    COREREG(usr_regs.uregs[1], regs[1]),
-    COREREG(usr_regs.uregs[2], regs[2]),
-    COREREG(usr_regs.uregs[3], regs[3]),
-    COREREG(usr_regs.uregs[4], regs[4]),
-    COREREG(usr_regs.uregs[5], regs[5]),
-    COREREG(usr_regs.uregs[6], regs[6]),
-    COREREG(usr_regs.uregs[7], regs[7]),
-    COREREG(usr_regs.uregs[8], usr_regs[0]),
-    COREREG(usr_regs.uregs[9], usr_regs[1]),
-    COREREG(usr_regs.uregs[10], usr_regs[2]),
-    COREREG(usr_regs.uregs[11], usr_regs[3]),
-    COREREG(usr_regs.uregs[12], usr_regs[4]),
-    COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
-    COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
-    /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
-    COREREG(svc_regs[0], banked_r13[BANK_SVC]),
-    COREREG(svc_regs[1], banked_r14[BANK_SVC]),
-    COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
-    COREREG(abt_regs[0], banked_r13[BANK_ABT]),
-    COREREG(abt_regs[1], banked_r14[BANK_ABT]),
-    COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
-    COREREG(und_regs[0], banked_r13[BANK_UND]),
-    COREREG(und_regs[1], banked_r14[BANK_UND]),
-    COREREG64(und_regs[2], banked_spsr[BANK_UND]),
-    COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
-    COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
-    COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
-    /* R8_fiq .. R14_fiq and SPSR_fiq */
-    COREREG(fiq_regs[0], fiq_regs[0]),
-    COREREG(fiq_regs[1], fiq_regs[1]),
-    COREREG(fiq_regs[2], fiq_regs[2]),
-    COREREG(fiq_regs[3], fiq_regs[3]),
-    COREREG(fiq_regs[4], fiq_regs[4]),
-    COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
-    COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
-    COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
-    /* R15 */
-    COREREG(usr_regs.uregs[15], regs[15]),
-    /* VFP system registers */
-    VFPSYSREG(FPSID),
-    VFPSYSREG(MVFR1),
-    VFPSYSREG(MVFR0),
-    VFPSYSREG(FPEXC),
-    VFPSYSREG(FPINST),
-    VFPSYSREG(FPINST2),
-};
-
-int kvm_arch_put_registers(CPUState *cs, int level)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
-    struct kvm_one_reg r;
-    int mode, bn;
-    int ret, i;
-    uint32_t cpsr, fpscr;
-
-    /* Make sure the banked regs are properly set */
-    mode = env->uncached_cpsr & CPSR_M;
-    bn = bank_number(mode);
-    if (mode == ARM_CPU_MODE_FIQ) {
-        memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
-    } else {
-        memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
-    }
-    env->banked_r13[bn] = env->regs[13];
-    env->banked_spsr[bn] = env->spsr;
-    env->banked_r14[r14_bank_number(mode)] = env->regs[14];
-
-    /* Now we can safely copy stuff down to the kernel */
-    for (i = 0; i < ARRAY_SIZE(regs); i++) {
-        r.id = regs[i].id;
-        r.addr = (uintptr_t)(env) + regs[i].offset;
-        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
-        if (ret) {
-            return ret;
-        }
-    }
-
-    /* Special cases which aren't a single CPUARMState field */
-    cpsr = cpsr_read(env);
-    r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
-        KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
-    r.addr = (uintptr_t)(&cpsr);
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
-    if (ret) {
-        return ret;
-    }
-
-    /* VFP registers */
-    r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
-    for (i = 0; i < 32; i++) {
-        r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
-        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
-        if (ret) {
-            return ret;
-        }
-        r.id++;
-    }
-
-    r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
-        KVM_REG_ARM_VFP_FPSCR;
-    fpscr = vfp_get_fpscr(env);
-    r.addr = (uintptr_t)&fpscr;
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
-    if (ret) {
-        return ret;
-    }
-
-    write_cpustate_to_list(cpu, true);
-
-    if (!write_list_to_kvmstate(cpu, level)) {
-        return EINVAL;
-    }
-
-    /*
-     * Setting VCPU events should be triggered after syncing the registers
-     * to avoid overwriting potential changes made by KVM upon calling
-     * KVM_SET_VCPU_EVENTS ioctl
-     */
-    ret = kvm_put_vcpu_events(cpu);
-    if (ret) {
-        return ret;
-    }
-
-    kvm_arm_sync_mpstate_to_kvm(cpu);
-
-    return ret;
-}
-
-int kvm_arch_get_registers(CPUState *cs)
-{
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
-    struct kvm_one_reg r;
-    int mode, bn;
-    int ret, i;
-    uint32_t cpsr, fpscr;
-
-    for (i = 0; i < ARRAY_SIZE(regs); i++) {
-        r.id = regs[i].id;
-        r.addr = (uintptr_t)(env) + regs[i].offset;
-        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
-        if (ret) {
-            return ret;
-        }
-    }
-
-    /* Special cases which aren't a single CPUARMState field */
-    r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
-        KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
-    r.addr = (uintptr_t)(&cpsr);
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
-    if (ret) {
-        return ret;
-    }
-    cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
-
-    /* Make sure the current mode regs are properly set */
-    mode = env->uncached_cpsr & CPSR_M;
-    bn = bank_number(mode);
-    if (mode == ARM_CPU_MODE_FIQ) {
-        memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
-    } else {
-        memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
-    }
-    env->regs[13] = env->banked_r13[bn];
-    env->spsr = env->banked_spsr[bn];
-    env->regs[14] = env->banked_r14[r14_bank_number(mode)];
-
-    /* VFP registers */
-    r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
-    for (i = 0; i < 32; i++) {
-        r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
-        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
-        if (ret) {
-            return ret;
-        }
-        r.id++;
-    }
-
-    r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
-        KVM_REG_ARM_VFP_FPSCR;
-    r.addr = (uintptr_t)&fpscr;
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
-    if (ret) {
-        return ret;
-    }
-    vfp_set_fpscr(env, fpscr);
-
-    ret = kvm_get_vcpu_events(cpu);
-    if (ret) {
-        return ret;
-    }
-
-    if (!write_kvmstate_to_list(cpu)) {
-        return EINVAL;
-    }
-    /* Note that it's OK to have registers which aren't in CPUState,
-     * so we can ignore a failure return here.
-     */
-    write_list_to_cpustate(cpu);
-
-    kvm_arm_sync_mpstate_to_qemu(cpu);
-
-    return 0;
-}
-
-int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
-    return -EINVAL;
-}
-
-int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
-    return -EINVAL;
-}
-
-bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
-    return false;
-}
-
-int kvm_arch_insert_hw_breakpoint(target_ulong addr,
-                                  target_ulong len, int type)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
-    return -EINVAL;
-}
-
-int kvm_arch_remove_hw_breakpoint(target_ulong addr,
-                                  target_ulong len, int type)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
-    return -EINVAL;
-}
-
-void kvm_arch_remove_all_hw_breakpoints(void)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
-}
-
-void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
-}
-
-bool kvm_arm_hw_debug_active(CPUState *cs)
-{
-    return false;
-}
-
-void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
-}
-
-void kvm_arm_pmu_init(CPUState *cs)
-{
-    qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
-}
-
-#define ARM_REG_DFSR  ARM_CP15_REG32(0, 5, 0, 0)
-#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
-/*
- *DFSR:
- *      TTBCR.EAE == 0
- *          FS[4]   - DFSR[10]
- *          FS[3:0] - DFSR[3:0]
- *      TTBCR.EAE == 1
- *          FS, bits [5:0]
- */
-#define DFSR_FSC(lpae, v) \
-    ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
-
-#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
-
-bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
-{
-    uint32_t dfsr_val;
-
-    if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
-        ARMCPU *cpu = ARM_CPU(cs);
-        CPUARMState *env = &cpu->env;
-        uint32_t ttbcr;
-        int lpae = 0;
-
-        if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
-            lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
-        }
-        /* The verification is based on FS filed of the DFSR reg only*/
-        return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
-    }
-    return false;
-}
diff --git a/target/arm/meson.build b/target/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(zlib)
 
 arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c'))
 
-kvm_ss = ss.source_set()
-kvm_ss.add(when: 'TARGET_AARCH64', if_true: files('kvm64.c'), if_false: files('kvm32.c'))
-arm_ss.add_all(when: 'CONFIG_KVM', if_true: kvm_ss)
-arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c'))
+arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c'))
 
 arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
   'cpu64.c',
-- 
2.20.1

Now that 32-bit KVM host support is gone, KVM can never
be enabled unless CONFIG_AARCH64 is true, and some code
paths are no longer reachable and can be deleted.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200904154156.31943-3-peter.maydell@linaro.org
---
 target/arm/kvm-consts.h |   7 ---
 target/arm/kvm_arm.h    |   6 ---
 target/arm/cpu.c        | 101 +++++++++++++++++++---------------------
 target/arm/kvm.c        |   7 ---
 4 files changed, 47 insertions(+), 74 deletions(-)

diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm-consts.h
+++ b/target/arm/kvm-consts.h
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED);
  */
 #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX
 
-#ifdef TARGET_AARCH64
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8);
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8);
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57);
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA);
 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53);
-#else
-MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15);
-MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7);
-#endif
 
 #define CP_REG_ARM64                   0x6000000000000000ULL
 #define CP_REG_ARM_COPROC_MASK         0x000000000FFF0000
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7);
 /* No kernel define but it's useful to QEMU */
 #define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_SHIFT)
 
-#ifdef TARGET_AARCH64
 MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64);
 MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK);
 MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT);
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_ARM64_SYSREG_CRM_MASK);
 MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHIFT);
 MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK);
 MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHIFT);
-#endif
 
 #undef MISMATCH_CHECK
 
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ static inline const char *gic_class_name(void)
 static inline const char *gicv3_class_name(void)
 {
     if (kvm_irqchip_in_kernel()) {
-#ifdef TARGET_AARCH64
         return "kvm-arm-gicv3";
-#else
-        error_report("KVM GICv3 acceleration is not supported on this "
-                     "platform");
-        exit(1);
-#endif
     } else {
         if (kvm_enabled()) {
             error_report("Userspace GICv3 is not supported with KVM");
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
 }
 
 #ifndef TARGET_AARCH64
-/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
- * otherwise, a CPU with as many features enabled as our emulation supports.
+/*
+ * -cpu max: a CPU with as many features enabled as our emulation supports.
  * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
- * this only needs to handle 32 bits.
+ * this only needs to handle 32 bits, and need not care about KVM.
  */
 static void arm_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
-    if (kvm_enabled()) {
-        kvm_arm_set_cpu_features_from_host(cpu);
-    } else {
-        cortex_a15_initfn(obj);
+    cortex_a15_initfn(obj);
 
-        /* old-style VFP short-vector support */
-        cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+    /* old-style VFP short-vector support */
+    cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
 
 #ifdef CONFIG_USER_ONLY
-        /* We don't set these in system emulation mode for the moment,
-         * since we don't correctly set (all of) the ID registers to
-         * advertise them.
-         */
-        set_feature(&cpu->env, ARM_FEATURE_V8);
-        {
-            uint32_t t;
+    /*
+     * We don't set these in system emulation mode for the moment,
+     * since we don't correctly set (all of) the ID registers to
+     * advertise them.
+     */
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    {
+        uint32_t t;
 
-            t = cpu->isar.id_isar5;
-            t = FIELD_DP32(t, ID_ISAR5, AES, 2);
-            t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
-            t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
-            t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
-            t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
-            t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
-            cpu->isar.id_isar5 = t;
+        t = cpu->isar.id_isar5;
+        t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+        t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+        t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+        t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+        t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+        t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+        cpu->isar.id_isar5 = t;
 
-            t = cpu->isar.id_isar6;
-            t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-            t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-            t = FIELD_DP32(t, ID_ISAR6, SB, 1);
-            t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
-            cpu->isar.id_isar6 = t;
+        t = cpu->isar.id_isar6;
+        t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+        t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+        t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+        t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+        t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+        cpu->isar.id_isar6 = t;
 
-            t = cpu->isar.mvfr1;
-            t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
-            t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
-            cpu->isar.mvfr1 = t;
+        t = cpu->isar.mvfr1;
+        t = FIELD_DP32(t, MVFR1, FPHP, 3);     /* v8.2-FP16 */
+        t = FIELD_DP32(t, MVFR1, SIMDHP, 2);   /* v8.2-FP16 */
+        cpu->isar.mvfr1 = t;
 
-            t = cpu->isar.mvfr2;
-            t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
-            t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
-            cpu->isar.mvfr2 = t;
+        t = cpu->isar.mvfr2;
+        t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+        t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+        cpu->isar.mvfr2 = t;
 
-            t = cpu->isar.id_mmfr3;
-            t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
-            cpu->isar.id_mmfr3 = t;
+        t = cpu->isar.id_mmfr3;
+        t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+        cpu->isar.id_mmfr3 = t;
 
-            t = cpu->isar.id_mmfr4;
-            t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
-            t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
-            t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
-            t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
-            cpu->isar.id_mmfr4 = t;
-        }
-#endif
+        t = cpu->isar.id_mmfr4;
+        t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+        t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+        t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+        t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+        cpu->isar.id_mmfr4 = t;
     }
+#endif
 }
 #endif
 
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
 
 static const TypeInfo host_arm_cpu_type_info = {
     .name = TYPE_ARM_HOST_CPU,
-#ifdef TARGET_AARCH64
     .parent = TYPE_AARCH64_CPU,
-#else
-    .parent = TYPE_ARM_CPU,
-#endif
     .instance_init = arm_host_initfn,
 };
 
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_process_async_events(CPUState *cs)
     return 0;
 }
 
-/* The #ifdef protections are until 32bit headers are imported and can
- * be removed once both 32 and 64 bit reach feature parity.
- */
 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
 {
-#ifdef KVM_GUESTDBG_USE_SW_BP
     if (kvm_sw_breakpoints_active(cs)) {
         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
     }
-#endif
-#ifdef KVM_GUESTDBG_USE_HW
     if (kvm_arm_hw_debug_active(cs)) {
         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW;
         kvm_arm_copy_hw_debug_data(&dbg->arch);
     }
-#endif
 }
 
 void kvm_arch_init_irq_routing(KVMState *s)
-- 
2.20.1

Implement a model of the MPS2 with the AN386 firmware. This is
essentially identical to the AN385 firmware, but it has a
Cortex-M4 rather than a Cortex-M3.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903202048.15370-2-peter.maydell@linaro.org
---
 docs/system/arm/mps2.rst |  8 +++++---
 hw/arm/mps2.c            | 34 +++++++++++++++++++++++++++++-----
 2 files changed, 34 insertions(+), 8 deletions(-)

diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/mps2.rst
+++ b/docs/system/arm/mps2.rst
@@ -XXX,XX +XXX,XX @@
-Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
-================================================================================
+Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
+================================================================================================
 
 These board models all use Arm M-profile CPUs.
 
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
 
 ``mps2-an385``
   Cortex-M3 as documented in ARM Application Note AN385
+``mps2-an386``
+  Cortex-M4 as documented in ARM Application Note AN386
 ``mps2-an511``
   Cortex-M3 'DesignStart' as documented in AN511
 ``mps2-an505``
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
 
 Differences between QEMU and real hardware:
 
-- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to
+- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to
   block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as
   if zbt_boot_ctrl is always zero)
 - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
  * as seen by the guest depend significantly on the FPGA image.
  * We model the following FPGA images:
  *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
+ *  "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
  *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
  *
  * Links to the TRM for the board itself and to the various Application
@@ -XXX,XX +XXX,XX @@
 
 typedef enum MPS2FPGAType {
     FPGA_AN385,
+    FPGA_AN386,
     FPGA_AN511,
 } MPS2FPGAType;
 
@@ -XXX,XX +XXX,XX @@ typedef struct MPS2MachineState MPS2MachineState;
 
 #define TYPE_MPS2_MACHINE "mps2"
 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
+#define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
 
 DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass,
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily
      * call the 16MB our "system memory", as it's the largest lump.
      *
-     * Common to both boards:
-     *  0x21000000..0x21ffffff : PSRAM (16MB)
-     * AN385 only:
+     * AN385/AN386/AN511:
+     *  0x21000000 .. 0x21ffffff : PSRAM (16MB)
+     * AN385/AN386 only:
      *  0x00000000 .. 0x003fffff : ZBT SSRAM1
      *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
      *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      *  0x20000000 .. 0x2001ffff : SRAM
      *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
      *
-     * The AN385 has a feature where the lowest 16K can be mapped
+     * The AN385/AN386 has a feature where the lowest 16K can be mapped
      * either to the bottom of the ZBT SSRAM1 or to the block RAM.
      * This is of no use for QEMU so we don't implement it (as if
      * zbt_boot_ctrl is always zero).
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
 
     switch (mmc->fpga_type) {
     case FPGA_AN385:
+    case FPGA_AN386:
         make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
         make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
         make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     armv7m = DEVICE(&mms->armv7m);
     switch (mmc->fpga_type) {
     case FPGA_AN385:
+    case FPGA_AN386:
         qdev_prop_set_uint32(armv7m, "num-irq", 32);
         break;
     case FPGA_AN511:
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
 
     switch (mmc->fpga_type) {
     case FPGA_AN385:
+    case FPGA_AN386:
     {
         /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
          * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      */
     lan9118_init(&nd_table[0], 0x40200000,
                  qdev_get_gpio_in(armv7m,
-                                  mmc->fpga_type == FPGA_AN385 ? 13 : 47));
+                                  mmc->fpga_type == FPGA_AN511 ? 47 : 13));
 
     system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
 
@@ -XXX,XX +XXX,XX @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
     mmc->scc_id = 0x41043850;
 }
 
+static void mps2_an386_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
+
+    mc->desc = "ARM MPS2 with AN386 FPGA image for Cortex-M4";
+    mmc->fpga_type = FPGA_AN386;
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
+    mmc->scc_id = 0x41043860;
+}
+
 static void mps2_an511_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -XXX,XX +XXX,XX @@ static const TypeInfo mps2_an385_info = {
     .class_init = mps2_an385_class_init,
 };
 
+static const TypeInfo mps2_an386_info = {
+    .name = TYPE_MPS2_AN386_MACHINE,
+    .parent = TYPE_MPS2_MACHINE,
+    .class_init = mps2_an386_class_init,
+};
+
 static const TypeInfo mps2_an511_info = {
     .name = TYPE_MPS2_AN511_MACHINE,
     .parent = TYPE_MPS2_MACHINE,
@@ -XXX,XX +XXX,XX @@ static void mps2_machine_init(void)
 {
     type_register_static(&mps2_info);
     type_register_static(&mps2_an385_info);
+    type_register_static(&mps2_an386_info);
     type_register_static(&mps2_an511_info);
 }
 
-- 
2.20.1

Implement a model of the MPS2 with the AN500 firmware. This is
similar to the AN385, with the following differences:
 * Cortex-M7 CPU
 * PSRAM is at 0x6000_0000
 * Ethernet is at 0xa000_0000
 * No zbt_boot_ctrl remapping of the low 16K
   (but QEMU doesn't implement this anyway)
 * no "block RAM" at 0x01000000

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
---
 docs/system/arm/mps2.rst |  6 ++--
 hw/arm/mps2.c            | 67 +++++++++++++++++++++++++++++++++-------
 2 files changed, 60 insertions(+), 13 deletions(-)

diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/mps2.rst
+++ b/docs/system/arm/mps2.rst
@@ -XXX,XX +XXX,XX @@
-Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
-================================================================================================
+Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``)
+================================================================================================================
 
 These board models all use Arm M-profile CPUs.
 
@@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images:
   Cortex-M3 as documented in ARM Application Note AN385
 ``mps2-an386``
   Cortex-M4 as documented in ARM Application Note AN386
+``mps2-an500``
+  Cortex-M7 as documented in ARM Application Note AN500
 ``mps2-an511``
   Cortex-M3 'DesignStart' as documented in AN511
 ``mps2-an505``
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
  * We model the following FPGA images:
  *  "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385
  *  "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386
+ *  "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500
  *  "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511
  *
  * Links to the TRM for the board itself and to the various Application
@@ -XXX,XX +XXX,XX @@
 typedef enum MPS2FPGAType {
     FPGA_AN385,
     FPGA_AN386,
+    FPGA_AN500,
     FPGA_AN511,
 } MPS2FPGAType;
 
@@ -XXX,XX +XXX,XX @@ struct MPS2MachineClass {
     MachineClass parent;
     MPS2FPGAType fpga_type;
     uint32_t scc_id;
+    bool has_block_ram;
+    hwaddr ethernet_base;
+    hwaddr psram_base;
 };
 typedef struct MPS2MachineClass MPS2MachineClass;
 
@@ -XXX,XX +XXX,XX @@ typedef struct MPS2MachineState MPS2MachineState;
 #define TYPE_MPS2_MACHINE "mps2"
 #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")
 #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386")
+#define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500")
 #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511")
 
 DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass,
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      *
      * AN385/AN386/AN511:
      *  0x21000000 .. 0x21ffffff : PSRAM (16MB)
-     * AN385/AN386 only:
+     * AN385/AN386/AN500:
      *  0x00000000 .. 0x003fffff : ZBT SSRAM1
      *  0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1
      *  0x20000000 .. 0x203fffff : ZBT SSRAM 2&3
      *  0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3
+     * AN385/AN386 only:
      *  0x01000000 .. 0x01003fff : block RAM (16K)
      *  0x01004000 .. 0x01007fff : mirror of above
      *  0x01008000 .. 0x0100bfff : mirror of above
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
      *  0x00400000 .. 0x007fffff : ZBT SSRAM1
      *  0x20000000 .. 0x2001ffff : SRAM
      *  0x20400000 .. 0x207fffff : ZBT SSRAM 2&3
+     * AN500 only:
+     *  0x60000000 .. 0x60ffffff : PSRAM (16MB)
      *
      * The AN385/AN386 has a feature where the lowest 16K can be mapped
      * either to the bottom of the ZBT SSRAM1 or to the block RAM.
      * This is of no use for QEMU so we don't implement it (as if
      * zbt_boot_ctrl is always zero).
      */
-    memory_region_add_subregion(system_memory, 0x21000000, machine->ram);
+    memory_region_add_subregion(system_memory, mmc->psram_base, machine->ram);
 
-    switch (mmc->fpga_type) {
-    case FPGA_AN385:
-    case FPGA_AN386:
-        make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
-        make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
-        make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
-        make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
-                       &mms->ssram23, 0x20400000);
+    if (mmc->has_block_ram) {
         make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000);
         make_ram_alias(&mms->blockram_m1, "mps.blockram_m1",
                        &mms->blockram, 0x01004000);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
                        &mms->blockram, 0x01008000);
         make_ram_alias(&mms->blockram_m3, "mps.blockram_m3",
                        &mms->blockram, 0x0100c000);
+    }
+
+    switch (mmc->fpga_type) {
+    case FPGA_AN385:
+    case FPGA_AN386:
+    case FPGA_AN500:
+        make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000);
+        make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000);
+        make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000);
+        make_ram_alias(&mms->ssram23_m, "mps.ssram23_m",
+                       &mms->ssram23, 0x20400000);
         break;
     case FPGA_AN511:
         make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000);
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     switch (mmc->fpga_type) {
     case FPGA_AN385:
     case FPGA_AN386:
+    case FPGA_AN500:
         qdev_prop_set_uint32(armv7m, "num-irq", 32);
         break;
     case FPGA_AN511:
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     switch (mmc->fpga_type) {
     case FPGA_AN385:
     case FPGA_AN386:
+    case FPGA_AN500:
     {
         /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together.
          * Overflow for UARTs 4 and 5 doesn't trigger any interrupt.
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
     /* In hardware this is a LAN9220; the LAN9118 is software compatible
      * except that it doesn't support the checksum-offload feature.
      */
-    lan9118_init(&nd_table[0], 0x40200000,
+    lan9118_init(&nd_table[0], mmc->ethernet_base,
                  qdev_get_gpio_in(armv7m,
                                   mmc->fpga_type == FPGA_AN511 ? 47 : 13));
 
@@ -XXX,XX +XXX,XX @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)
     mmc->fpga_type = FPGA_AN385;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
     mmc->scc_id = 0x41043850;
+    mmc->psram_base = 0x21000000;
+    mmc->ethernet_base = 0x40200000;
+    mmc->has_block_ram = true;
 }
 
 static void mps2_an386_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void mps2_an386_class_init(ObjectClass *oc, void *data)
     mmc->fpga_type = FPGA_AN386;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
     mmc->scc_id = 0x41043860;
+    mmc->psram_base = 0x21000000;
+    mmc->ethernet_base = 0x40200000;
+    mmc->has_block_ram = true;
+}
+
+static void mps2_an500_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    MPS2MachineClass *mmc = MPS2_MACHINE_CLASS(oc);
+
+    mc->desc = "ARM MPS2 with AN500 FPGA image for Cortex-M7";
+    mmc->fpga_type = FPGA_AN500;
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m7");
+    mmc->scc_id = 0x41045000;
+    mmc->psram_base = 0x60000000;
+    mmc->ethernet_base = 0xa0000000;
+    mmc->has_block_ram = false;
 }
 
 static void mps2_an511_class_init(ObjectClass *oc, void *data)
@@ -XXX,XX +XXX,XX @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)
     mmc->fpga_type = FPGA_AN511;
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
     mmc->scc_id = 0x41045110;
+    mmc->psram_base = 0x21000000;
+    mmc->ethernet_base = 0x40200000;
+    mmc->has_block_ram = false;
 }
 
 static const TypeInfo mps2_info = {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo mps2_an386_info = {
     .class_init = mps2_an386_class_init,
 };
 
+static const TypeInfo mps2_an500_info = {
+    .name = TYPE_MPS2_AN500_MACHINE,
+    .parent = TYPE_MPS2_MACHINE,
+    .class_init = mps2_an500_class_init,
+};
+
 static const TypeInfo mps2_an511_info = {
     .name = TYPE_MPS2_AN511_MACHINE,
     .parent = TYPE_MPS2_MACHINE,
@@ -XXX,XX +XXX,XX @@ static void mps2_machine_init(void)
     type_register_static(&mps2_info);
     type_register_static(&mps2_an385_info);
     type_register_static(&mps2_an386_info);
+    type_register_static(&mps2_an500_info);
     type_register_static(&mps2_an511_info);
 }
 
-- 
2.20.1

Make the list of MPS2 boards consistent in the phrasing of each
entry, use the correct casing of "Arm", and move the mps2-an511
entry so the list is in numeric order.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200903202048.15370-4-peter.maydell@linaro.org
---
 docs/system/arm/mps2.rst | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/mps2.rst
+++ b/docs/system/arm/mps2.rst
@@ -XXX,XX +XXX,XX @@ as seen by the guest depend significantly on the FPGA image.
 QEMU models the following FPGA images:
 
 ``mps2-an385``
-  Cortex-M3 as documented in ARM Application Note AN385
+  Cortex-M3 as documented in Arm Application Note AN385
 ``mps2-an386``
-  Cortex-M4 as documented in ARM Application Note AN386
+  Cortex-M4 as documented in Arm Application Note AN386
 ``mps2-an500``
-  Cortex-M7 as documented in ARM Application Note AN500
-``mps2-an511``
-  Cortex-M3 'DesignStart' as documented in AN511
+  Cortex-M7 as documented in Arm Application Note AN500
 ``mps2-an505``
-  Cortex-M33 as documented in ARM Application Note AN505
+  Cortex-M33 as documented in Arm Application Note AN505
+``mps2-an511``
+  Cortex-M3 'DesignStart' as documented in Arm Application Note AN511
 ``mps2-an521``
-  Dual Cortex-M33 as documented in Application Note AN521
+  Dual Cortex-M33 as documented in Arm Application Note AN521
 
 Differences between QEMU and real hardware:
 
-- 
2.20.1

Deprecate our Unicore32 target support:
 * the Linux kernel dropped support for unicore32 in commit
   05119217a9bd199c for its 5.9 release (with rationale in the
   cover letter: https://lkml.org/lkml/2020/8/3/232 )
 * there is apparently no upstream toolchain that can create unicore32
   binaries
 * the maintainer doesn't seem to have made any contributions to
   QEMU since the port first landed in 2012
 * nobody else seems to have made changes to the unicore code except
   for generic cleanups either

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-id: 20200825172719.19422-1-peter.maydell@linaro.org
---
 docs/system/deprecated.rst | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
 linux-user mode CPUs
 --------------------
 
+``unicore32`` CPUs (since 5.2.0)
+''''''''''''''''''''''''''''''''
+
+The ``unicore32`` guest CPU support is deprecated and will be removed in
+a future version of QEMU. Support for this CPU was removed from the
+upstream Linux kernel, and there is no available upstream toolchain
+to build binaries for it.
+
 ``tilegx`` CPUs (since 5.1.0)
 '''''''''''''''''''''''''''''
 
-- 
2.20.1

Deprecate our lm32 target support. Michael Walle (former lm32 maintainer)
suggested that we do this in 2019:
 https://www.mail-archive.com/qemu-devel@nongnu.org/msg605024.html
because the only public user of the architecture is the many-years-dead
milkymist project. (The Linux port to lm32 was never merged upstream.)

In commit 4b4d96c776f552e (March 2020) we marked it as 'orphan' in
the MAINTAINERS file, but didn't officially deprecate it. Mark it
deprecated now, with the intention of removing it from QEMU in
mid-2021 before the 6.1 release.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Michael Walle <michael@walle.cc>
Message-id: 20200827113259.25064-1-peter.maydell@linaro.org
---
 docs/system/deprecated.rst | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
 linux-user mode CPUs
 --------------------
 
+``lm32`` CPUs (since 5.2.0)
+'''''''''''''''''''''''''''
+
+The ``lm32`` guest CPU support is deprecated and will be removed in
+a future version of QEMU. The only public user of this architecture
+was the milkymist project, which has been dead for years; there was
+never an upstream Linux port.
+
 ``unicore32`` CPUs (since 5.2.0)
 ''''''''''''''''''''''''''''''''
 
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock.
This matches the setup with the fixed-link 100Mbit PHY.
It also avoids the following warnings from the Linux kernel
driver:

eth0: unable to generate target frequency: 125000000 Hz

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200909174647.662864-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal-virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gem_nodes(VersalVirt *s)
                               s->phandle.ethernet_phy[i]);
         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
-                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
+                               s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
         qemu_fdt_setprop(s->fdt, name, "clock-names",
                          clocknames, sizeof(clocknames));
         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

Implement a device model for the System Global Control Registers in the
NPCM730 and NPCM750 BMC SoCs.

This is primarily used to enable SMP boot (the boot ROM spins reading
the SCRPAD register) and DDR memory initialization; other registers are
best effort for now.

The reset values of the MDLR and PWRON registers are determined by the
SoC variant (730 vs 750) and board straps respectively.

Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-2-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/npcm7xx_gcr.h |  43 ++++++
 hw/misc/npcm7xx_gcr.c         | 269 ++++++++++++++++++++++++++++++++++
 MAINTAINERS                   |   8 +
 hw/arm/Kconfig                |   3 +
 hw/misc/meson.build           |   3 +
 hw/misc/trace-events          |   4 +
 6 files changed, 330 insertions(+)
 create mode 100644 include/hw/misc/npcm7xx_gcr.h
 create mode 100644 hw/misc/npcm7xx_gcr.c

diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/npcm7xx_gcr.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx System Global Control Registers.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_GCR_H
+#define NPCM7XX_GCR_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
+
+typedef struct NPCM7xxGCRState {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    uint32_t regs[NPCM7XX_GCR_NR_REGS];
+
+    uint32_t reset_pwron;
+    uint32_t reset_mdlr;
+    uint32_t reset_intcr3;
+} NPCM7xxGCRState;
+
+#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
+#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
+
+#endif /* NPCM7XX_GCR_H */
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/npcm7xx_gcr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx System Global Control Registers.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/misc/npcm7xx_gcr.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/cutils.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+#define NPCM7XX_GCR_MIN_DRAM_SIZE   (128 * MiB)
+#define NPCM7XX_GCR_MAX_DRAM_SIZE   (2 * GiB)
+
+enum NPCM7xxGCRRegisters {
+    NPCM7XX_GCR_PDID,
+    NPCM7XX_GCR_PWRON,
+    NPCM7XX_GCR_MFSEL1          = 0x0c / sizeof(uint32_t),
+    NPCM7XX_GCR_MFSEL2,
+    NPCM7XX_GCR_MISCPE,
+    NPCM7XX_GCR_SPSWC           = 0x038 / sizeof(uint32_t),
+    NPCM7XX_GCR_INTCR,
+    NPCM7XX_GCR_INTSR,
+    NPCM7XX_GCR_HIFCR           = 0x050 / sizeof(uint32_t),
+    NPCM7XX_GCR_INTCR2          = 0x060 / sizeof(uint32_t),
+    NPCM7XX_GCR_MFSEL3,
+    NPCM7XX_GCR_SRCNT,
+    NPCM7XX_GCR_RESSR,
+    NPCM7XX_GCR_RLOCKR1,
+    NPCM7XX_GCR_FLOCKR1,
+    NPCM7XX_GCR_DSCNT,
+    NPCM7XX_GCR_MDLR,
+    NPCM7XX_GCR_SCRPAD3,
+    NPCM7XX_GCR_SCRPAD2,
+    NPCM7XX_GCR_DAVCLVLR        = 0x098 / sizeof(uint32_t),
+    NPCM7XX_GCR_INTCR3,
+    NPCM7XX_GCR_VSINTR          = 0x0ac / sizeof(uint32_t),
+    NPCM7XX_GCR_MFSEL4,
+    NPCM7XX_GCR_CPBPNTR         = 0x0c4 / sizeof(uint32_t),
+    NPCM7XX_GCR_CPCTL           = 0x0d0 / sizeof(uint32_t),
+    NPCM7XX_GCR_CP2BST,
+    NPCM7XX_GCR_B2CPNT,
+    NPCM7XX_GCR_CPPCTL,
+    NPCM7XX_GCR_I2CSEGSEL,
+    NPCM7XX_GCR_I2CSEGCTL,
+    NPCM7XX_GCR_VSRCR,
+    NPCM7XX_GCR_MLOCKR,
+    NPCM7XX_GCR_SCRPAD          = 0x013c / sizeof(uint32_t),
+    NPCM7XX_GCR_USB1PHYCTL,
+    NPCM7XX_GCR_USB2PHYCTL,
+    NPCM7XX_GCR_REGS_END,
+};
+
+static const uint32_t cold_reset_values[NPCM7XX_GCR_NR_REGS] = {
+    [NPCM7XX_GCR_PDID]          = 0x04a92750,   /* Poleg A1 */
+    [NPCM7XX_GCR_MISCPE]        = 0x0000ffff,
+    [NPCM7XX_GCR_SPSWC]         = 0x00000003,
+    [NPCM7XX_GCR_INTCR]         = 0x0000035e,
+    [NPCM7XX_GCR_HIFCR]         = 0x0000004e,
+    [NPCM7XX_GCR_INTCR2]        = (1U << 19),   /* DDR initialized */
+    [NPCM7XX_GCR_RESSR]         = 0x80000000,
+    [NPCM7XX_GCR_DSCNT]         = 0x000000c0,
+    [NPCM7XX_GCR_DAVCLVLR]      = 0x5a00f3cf,
+    [NPCM7XX_GCR_SCRPAD]        = 0x00000008,
+    [NPCM7XX_GCR_USB1PHYCTL]    = 0x034730e4,
+    [NPCM7XX_GCR_USB2PHYCTL]    = 0x034730e4,
+};
+
+static uint64_t npcm7xx_gcr_read(void *opaque, hwaddr offset, unsigned size)
+{
+    uint32_t reg = offset / sizeof(uint32_t);
+    NPCM7xxGCRState *s = opaque;
+
+    if (reg >= NPCM7XX_GCR_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
+                      __func__, offset);
+        return 0;
+    }
+
+    trace_npcm7xx_gcr_read(offset, s->regs[reg]);
+
+    return s->regs[reg];
+}
+
+static void npcm7xx_gcr_write(void *opaque, hwaddr offset,
+                              uint64_t v, unsigned size)
+{
+    uint32_t reg = offset / sizeof(uint32_t);
+    NPCM7xxGCRState *s = opaque;
+    uint32_t value = v;
+
+    trace_npcm7xx_gcr_write(offset, value);
+
+    if (reg >= NPCM7XX_GCR_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
+                      __func__, offset);
+        return;
+    }
+
+    switch (reg) {
+    case NPCM7XX_GCR_PDID:
+    case NPCM7XX_GCR_PWRON:
+    case NPCM7XX_GCR_INTSR:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        return;
+
+    case NPCM7XX_GCR_RESSR:
+    case NPCM7XX_GCR_CP2BST:
+        /* Write 1 to clear */
+        value = s->regs[reg] & ~value;
+        break;
+
+    case NPCM7XX_GCR_RLOCKR1:
+    case NPCM7XX_GCR_MDLR:
+        /* Write 1 to set */
+        value |= s->regs[reg];
+        break;
+    };
+
+    s->regs[reg] = value;
+}
+
+static const struct MemoryRegionOps npcm7xx_gcr_ops = {
+    .read       = npcm7xx_gcr_read,
+    .write      = npcm7xx_gcr_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
+
+    QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
+
+    switch (type) {
+    case RESET_TYPE_COLD:
+        memcpy(s->regs, cold_reset_values, sizeof(s->regs));
+        s->regs[NPCM7XX_GCR_PWRON] = s->reset_pwron;
+        s->regs[NPCM7XX_GCR_MDLR] = s->reset_mdlr;
+        s->regs[NPCM7XX_GCR_INTCR3] = s->reset_intcr3;
+        break;
+    }
+}
+
+static void npcm7xx_gcr_realize(DeviceState *dev, Error **errp)
+{
+    ERRP_GUARD();
+    NPCM7xxGCRState *s = NPCM7XX_GCR(dev);
+    uint64_t dram_size;
+    Object *obj;
+
+    obj = object_property_get_link(OBJECT(dev), "dram-mr", errp);
+    if (!obj) {
+        error_prepend(errp, "%s: required dram-mr link not found: ", __func__);
+        return;
+    }
+    dram_size = memory_region_size(MEMORY_REGION(obj));
+    if (!is_power_of_2(dram_size) ||
+        dram_size < NPCM7XX_GCR_MIN_DRAM_SIZE ||
+        dram_size > NPCM7XX_GCR_MAX_DRAM_SIZE) {
+        g_autofree char *sz = size_to_str(dram_size);
+        g_autofree char *min_sz = size_to_str(NPCM7XX_GCR_MIN_DRAM_SIZE);
+        g_autofree char *max_sz = size_to_str(NPCM7XX_GCR_MAX_DRAM_SIZE);
+        error_setg(errp, "%s: unsupported DRAM size %s", __func__, sz);
+        error_append_hint(errp,
+                          "DRAM size must be a power of two between %s and %s,"
+                          " inclusive.\n", min_sz, max_sz);
+        return;
+    }
+
+    /* Power-on reset value */
+    s->reset_intcr3 = 0x00001002;
+
+    /*
+     * The GMMAP (Graphics Memory Map) field is used by u-boot to detect the
+     * DRAM size, and is normally initialized by the boot block as part of DRAM
+     * training. However, since we don't have a complete emulation of the
+     * memory controller and try to make it look like it has already been
+     * initialized, the boot block will skip this initialization, and we need
+     * to make sure this field is set correctly up front.
+     *
+     * WARNING: some versions of u-boot only looks at bits 8 and 9, so 2 GiB of
+     * DRAM will be interpreted as 128 MiB.
+     *
+     * https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408dbaad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244
+     */
+    s->reset_intcr3 |= ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8;
+}
+
+static void npcm7xx_gcr_init(Object *obj)
+{
+    NPCM7xxGCRState *s = NPCM7XX_GCR(obj);
+
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
+                          TYPE_NPCM7XX_GCR, 4 * KiB);
+    sysbus_init_mmio(&s->parent, &s->iomem);
+}
+
+static const VMStateDescription vmstate_npcm7xx_gcr = {
+    .name = "npcm7xx-gcr",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxGCRState, NPCM7XX_GCR_NR_REGS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static Property npcm7xx_gcr_properties[] = {
+    DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState, reset_mdlr, 0),
+    DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState, reset_pwron, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM7XX_GCR_NR_REGS);
+
+    dc->desc = "NPCM7xx System Global Control Registers";
+    dc->realize = npcm7xx_gcr_realize;
+    dc->vmsd = &vmstate_npcm7xx_gcr;
+    rc->phases.enter = npcm7xx_gcr_enter_reset;
+
+    device_class_set_props(dc, npcm7xx_gcr_properties);
+}
+
+static const TypeInfo npcm7xx_gcr_info = {
+    .name               = TYPE_NPCM7XX_GCR,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxGCRState),
+    .instance_init      = npcm7xx_gcr_init,
+    .class_init         = npcm7xx_gcr_class_init,
+};
+
+static void npcm7xx_gcr_register_type(void)
+{
+    type_register_static(&npcm7xx_gcr_info);
+}
+type_init(npcm7xx_gcr_register_type);
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ S: Odd Fixes
 F: hw/arm/musicpal.c
 F: docs/system/arm/musicpal.rst
 
+Nuvoton NPCM7xx
+M: Havard Skinnemoen <hskinnemoen@google.com>
+M: Tyrone Ting <kfting@nuvoton.com>
+L: qemu-arm@nongnu.org
+S: Supported
+F: hw/*/npcm7xx*
+F: include/hw/*/npcm7xx*
+
 nSeries
 M: Andrzej Zaborowski <balrogg@gmail.com>
 M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
     select VIRTIO_MMIO
     select UNIMP
 
+config NPCM7XX
+    bool
+
 config FSL_IMX25
     bool
     select IMX
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
 ))
 softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-hpdmc.c', 'milkymist-pfpu.c'))
 softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
+  'npcm7xx_gcr.c',
+))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
   'omap_clk.c',
   'omap_gpmc.c',
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
 mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
 mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
 
+# npcm7xx_gcr.c
+npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+
 # stm32f4xx_syscfg.c
 stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
 stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

Enough functionality to boot the Linux kernel has been implemented. This
includes:

- Correct power-on reset values so the various clock rates can be
    accurately calculated.
  - Clock enables stick around when written.

In addition, a best effort attempt to implement SECCNT and CNTR25M was
made even though I don't think the kernel needs them.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-3-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/npcm7xx_clk.h |  48 ++++++
 hw/misc/npcm7xx_clk.c         | 266 ++++++++++++++++++++++++++++++++++
 hw/misc/meson.build           |   1 +
 hw/misc/trace-events          |   4 +
 4 files changed, 319 insertions(+)
 create mode 100644 include/hw/misc/npcm7xx_clk.h
 create mode 100644 hw/misc/npcm7xx_clk.c

diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/npcm7xx_clk.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx Clock Control Registers.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_CLK_H
+#define NPCM7XX_CLK_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+/*
+ * The reference clock frequency for the timer modules, and the SECCNT and
+ * CNTR25M registers in this module, is always 25 MHz.
+ */
+#define NPCM7XX_TIMER_REF_HZ            (25000000)
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM7XX_CLK_NR_REGS             (0x70 / sizeof(uint32_t))
+
+typedef struct NPCM7xxCLKState {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    uint32_t regs[NPCM7XX_CLK_NR_REGS];
+
+    /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
+    int64_t ref_ns;
+} NPCM7xxCLKState;
+
+#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
+#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
+
+#endif /* NPCM7XX_CLK_H */
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/npcm7xx_clk.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx Clock Control Registers.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/misc/npcm7xx_clk.h"
+#include "migration/vmstate.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+#define PLLCON_LOKI     BIT(31)
+#define PLLCON_LOKS     BIT(30)
+#define PLLCON_PWDEN    BIT(12)
+
+enum NPCM7xxCLKRegisters {
+    NPCM7XX_CLK_CLKEN1,
+    NPCM7XX_CLK_CLKSEL,
+    NPCM7XX_CLK_CLKDIV1,
+    NPCM7XX_CLK_PLLCON0,
+    NPCM7XX_CLK_PLLCON1,
+    NPCM7XX_CLK_SWRSTR,
+    NPCM7XX_CLK_IPSRST1         = 0x20 / sizeof(uint32_t),
+    NPCM7XX_CLK_IPSRST2,
+    NPCM7XX_CLK_CLKEN2,
+    NPCM7XX_CLK_CLKDIV2,
+    NPCM7XX_CLK_CLKEN3,
+    NPCM7XX_CLK_IPSRST3,
+    NPCM7XX_CLK_WD0RCR,
+    NPCM7XX_CLK_WD1RCR,
+    NPCM7XX_CLK_WD2RCR,
+    NPCM7XX_CLK_SWRSTC1,
+    NPCM7XX_CLK_SWRSTC2,
+    NPCM7XX_CLK_SWRSTC3,
+    NPCM7XX_CLK_SWRSTC4,
+    NPCM7XX_CLK_PLLCON2,
+    NPCM7XX_CLK_CLKDIV3,
+    NPCM7XX_CLK_CORSTC,
+    NPCM7XX_CLK_PLLCONG,
+    NPCM7XX_CLK_AHBCKFI,
+    NPCM7XX_CLK_SECCNT,
+    NPCM7XX_CLK_CNTR25M,
+    NPCM7XX_CLK_REGS_END,
+};
+
+/*
+ * These reset values were taken from version 0.91 of the NPCM750R data sheet.
+ *
+ * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
+ * core domain reset, but this reset type is not yet supported by QEMU.
+ */
+static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
+    [NPCM7XX_CLK_CLKEN1]        = 0xffffffff,
+    [NPCM7XX_CLK_CLKSEL]        = 0x004aaaaa,
+    [NPCM7XX_CLK_CLKDIV1]       = 0x5413f855,
+    [NPCM7XX_CLK_PLLCON0]       = 0x00222101 | PLLCON_LOKI,
+    [NPCM7XX_CLK_PLLCON1]       = 0x00202101 | PLLCON_LOKI,
+    [NPCM7XX_CLK_IPSRST1]       = 0x00001000,
+    [NPCM7XX_CLK_IPSRST2]       = 0x80000000,
+    [NPCM7XX_CLK_CLKEN2]        = 0xffffffff,
+    [NPCM7XX_CLK_CLKDIV2]       = 0xaa4f8f9f,
+    [NPCM7XX_CLK_CLKEN3]        = 0xffffffff,
+    [NPCM7XX_CLK_IPSRST3]       = 0x03000000,
+    [NPCM7XX_CLK_WD0RCR]        = 0xffffffff,
+    [NPCM7XX_CLK_WD1RCR]        = 0xffffffff,
+    [NPCM7XX_CLK_WD2RCR]        = 0xffffffff,
+    [NPCM7XX_CLK_SWRSTC1]       = 0x00000003,
+    [NPCM7XX_CLK_PLLCON2]       = 0x00c02105 | PLLCON_LOKI,
+    [NPCM7XX_CLK_CORSTC]        = 0x04000003,
+    [NPCM7XX_CLK_PLLCONG]       = 0x01228606 | PLLCON_LOKI,
+    [NPCM7XX_CLK_AHBCKFI]       = 0x000000c8,
+};
+
+static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
+{
+    uint32_t reg = offset / sizeof(uint32_t);
+    NPCM7xxCLKState *s = opaque;
+    int64_t now_ns;
+    uint32_t value = 0;
+
+    if (reg >= NPCM7XX_CLK_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
+                      __func__, offset);
+        return 0;
+    }
+
+    switch (reg) {
+    case NPCM7XX_CLK_SWRSTR:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is write-only\n",
+                      __func__, offset);
+        break;
+
+    case NPCM7XX_CLK_SECCNT:
+        now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+        value = (now_ns - s->ref_ns) / NANOSECONDS_PER_SECOND;
+        break;
+
+    case NPCM7XX_CLK_CNTR25M:
+        now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+        /*
+         * This register counts 25 MHz cycles, updating every 640 ns. It rolls
+         * over to zero every second.
+         *
+         * The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
+         */
+        value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
+        break;
+
+    default:
+        value = s->regs[reg];
+        break;
+    };
+
+    trace_npcm7xx_clk_read(offset, value);
+
+    return value;
+}
+
+static void npcm7xx_clk_write(void *opaque, hwaddr offset,
+                              uint64_t v, unsigned size)
+{
+    uint32_t reg = offset / sizeof(uint32_t);
+    NPCM7xxCLKState *s = opaque;
+    uint32_t value = v;
+
+    trace_npcm7xx_clk_write(offset, value);
+
+    if (reg >= NPCM7XX_CLK_NR_REGS) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: offset 0x%04" HWADDR_PRIx " out of range\n",
+                      __func__, offset);
+        return;
+    }
+
+    switch (reg) {
+    case NPCM7XX_CLK_SWRSTR:
+        qemu_log_mask(LOG_UNIMP, "%s: SW reset not implemented: 0x%02x\n",
+                      __func__, value);
+        value = 0;
+        break;
+
+    case NPCM7XX_CLK_PLLCON0:
+    case NPCM7XX_CLK_PLLCON1:
+    case NPCM7XX_CLK_PLLCON2:
+    case NPCM7XX_CLK_PLLCONG:
+        if (value & PLLCON_PWDEN) {
+            /* Power down -- clear lock and indicate loss of lock */
+            value &= ~PLLCON_LOKI;
+            value |= PLLCON_LOKS;
+        } else {
+            /* Normal mode -- assume always locked */
+            value |= PLLCON_LOKI;
+            /* Keep LOKS unchanged unless cleared by writing 1 */
+            if (value & PLLCON_LOKS) {
+                value &= ~PLLCON_LOKS;
+            } else {
+                value |= (value & PLLCON_LOKS);
+            }
+        }
+        break;
+
+    case NPCM7XX_CLK_CNTR25M:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        return;
+    }
+
+    s->regs[reg] = value;
+}
+
+static const struct MemoryRegionOps npcm7xx_clk_ops = {
+    .read       = npcm7xx_clk_read,
+    .write      = npcm7xx_clk_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
+
+    QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
+
+    switch (type) {
+    case RESET_TYPE_COLD:
+        memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
+        s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+        return;
+    }
+
+    /*
+     * A small number of registers need to be reset on a core domain reset,
+     * but no such reset type exists yet.
+     */
+    qemu_log_mask(LOG_UNIMP, "%s: reset type %d not implemented.",
+                  __func__, type);
+}
+
+static void npcm7xx_clk_init(Object *obj)
+{
+    NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
+
+    memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
+                          TYPE_NPCM7XX_CLK, 4 * KiB);
+    sysbus_init_mmio(&s->parent, &s->iomem);
+}
+
+static const VMStateDescription vmstate_npcm7xx_clk = {
+    .name = "npcm7xx-clk",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
+        VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM7XX_CLK_NR_REGS);
+
+    dc->desc = "NPCM7xx Clock Control Registers";
+    dc->vmsd = &vmstate_npcm7xx_clk;
+    rc->phases.enter = npcm7xx_clk_enter_reset;
+}
+
+static const TypeInfo npcm7xx_clk_info = {
+    .name               = TYPE_NPCM7XX_CLK,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxCLKState),
+    .instance_init      = npcm7xx_clk_init,
+    .class_init         = npcm7xx_clk_class_init,
+};
+
+static void npcm7xx_clk_register_type(void)
+{
+    type_register_static(&npcm7xx_clk_info);
+}
+type_init(npcm7xx_clk_register_type);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
 softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-hpdmc.c', 'milkymist-pfpu.c'))
 softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
 softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
+  'npcm7xx_clk.c',
   'npcm7xx_gcr.c',
 ))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ mos6522_set_sr_int(void) "set sr_int"
 mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
 mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
 
+# npcm7xx_clk.c
+npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+
 # npcm7xx_gcr.c
 npcm7xx_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

The NPCM730 and NPCM750 SoCs have three timer modules each holding five
timers and some shared registers (e.g. interrupt status).

Each timer runs at 25 MHz divided by a prescaler, and counts down from a
configurable initial value to zero. When zero is reached, the interrupt
flag for the timer is set, and the timer is disabled (one-shot mode) or
reloaded from its initial value (periodic mode).

This implementation is sufficient to boot a Linux kernel configured for
NPCM750. Note that the kernel does not seem to actually turn on the
interrupts.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-4-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/timer/npcm7xx_timer.h |  78 +++++
 hw/timer/npcm7xx_timer.c         | 543 +++++++++++++++++++++++++++++++
 hw/timer/meson.build             |   1 +
 hw/timer/trace-events            |   5 +
 4 files changed, 627 insertions(+)
 create mode 100644 include/hw/timer/npcm7xx_timer.h
 create mode 100644 hw/timer/npcm7xx_timer.c

diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/timer/npcm7xx_timer.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx Timer Controller
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_TIMER_H
+#define NPCM7XX_TIMER_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+/* Each Timer Module (TIM) instance holds five 25 MHz timers. */
+#define NPCM7XX_TIMERS_PER_CTRL (5)
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
+
+typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
+
+/**
+ * struct NPCM7xxTimer - Individual timer state.
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
+ * @qtimer: QEMU timer that notifies us on expiration.
+ * @expires_ns: Absolute virtual expiration time.
+ * @remaining_ns: Remaining time until expiration if timer is paused.
+ * @tcsr: The Timer Control and Status Register.
+ * @ticr: The Timer Initial Count Register.
+ */
+typedef struct NPCM7xxTimer {
+    NPCM7xxTimerCtrlState *ctrl;
+
+    qemu_irq    irq;
+    QEMUTimer   qtimer;
+    int64_t     expires_ns;
+    int64_t     remaining_ns;
+
+    uint32_t    tcsr;
+    uint32_t    ticr;
+} NPCM7xxTimer;
+
+/**
+ * struct NPCM7xxTimerCtrlState - Timer Module device state.
+ * @parent: System bus device.
+ * @iomem: Memory region through which registers are accessed.
+ * @tisr: The Timer Interrupt Status Register.
+ * @wtcr: The Watchdog Timer Control Register.
+ * @timer: The five individual timers managed by this module.
+ */
+struct NPCM7xxTimerCtrlState {
+    SysBusDevice parent;
+
+    MemoryRegion iomem;
+
+    uint32_t    tisr;
+    uint32_t    wtcr;
+
+    NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
+};
+
+#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
+#define NPCM7XX_TIMER(obj)                                              \
+    OBJECT_CHECK(NPCM7xxTimerCtrlState, (obj), TYPE_NPCM7XX_TIMER)
+
+#endif /* NPCM7XX_TIMER_H */
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/timer/npcm7xx_timer.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx Timer Controller
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/misc/npcm7xx_clk.h"
+#include "hw/timer/npcm7xx_timer.h"
+#include "migration/vmstate.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/timer.h"
+#include "qemu/units.h"
+#include "trace.h"
+
+/* 32-bit register indices. */
+enum NPCM7xxTimerRegisters {
+    NPCM7XX_TIMER_TCSR0,
+    NPCM7XX_TIMER_TCSR1,
+    NPCM7XX_TIMER_TICR0,
+    NPCM7XX_TIMER_TICR1,
+    NPCM7XX_TIMER_TDR0,
+    NPCM7XX_TIMER_TDR1,
+    NPCM7XX_TIMER_TISR,
+    NPCM7XX_TIMER_WTCR,
+    NPCM7XX_TIMER_TCSR2,
+    NPCM7XX_TIMER_TCSR3,
+    NPCM7XX_TIMER_TICR2,
+    NPCM7XX_TIMER_TICR3,
+    NPCM7XX_TIMER_TDR2,
+    NPCM7XX_TIMER_TDR3,
+    NPCM7XX_TIMER_TCSR4         = 0x0040 / sizeof(uint32_t),
+    NPCM7XX_TIMER_TICR4         = 0x0048 / sizeof(uint32_t),
+    NPCM7XX_TIMER_TDR4          = 0x0050 / sizeof(uint32_t),
+    NPCM7XX_TIMER_REGS_END,
+};
+
+/* Register field definitions. */
+#define NPCM7XX_TCSR_CEN                BIT(30)
+#define NPCM7XX_TCSR_IE                 BIT(29)
+#define NPCM7XX_TCSR_PERIODIC           BIT(27)
+#define NPCM7XX_TCSR_CRST               BIT(26)
+#define NPCM7XX_TCSR_CACT               BIT(25)
+#define NPCM7XX_TCSR_RSVD               0x01ffff00
+#define NPCM7XX_TCSR_PRESCALE_START     0
+#define NPCM7XX_TCSR_PRESCALE_LEN       8
+
+/*
+ * Returns the index of timer in the tc->timer array. This can be used to
+ * locate the registers that belong to this timer.
+ */
+static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer)
+{
+    int index = timer - tc->timer;
+
+    g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL);
+
+    return index;
+}
+
+/* Return the value by which to divide the reference clock rate. */
+static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
+{
+    return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START,
+                     NPCM7XX_TCSR_PRESCALE_LEN) + 1;
+}
+
+/* Convert a timer cycle count to a time interval in nanoseconds. */
+static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
+{
+    int64_t ns = count;
+
+    ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
+    ns *= npcm7xx_tcsr_prescaler(t->tcsr);
+
+    return ns;
+}
+
+/* Convert a time interval in nanoseconds to a timer cycle count. */
+static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
+{
+    int64_t count;
+
+    count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
+    count /= npcm7xx_tcsr_prescaler(t->tcsr);
+
+    return count;
+}
+
+/*
+ * Raise the interrupt line if there's a pending interrupt and interrupts are
+ * enabled for this timer. If not, lower it.
+ */
+static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t)
+{
+    NPCM7xxTimerCtrlState *tc = t->ctrl;
+    int index = npcm7xx_timer_index(tc, t);
+    bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index));
+
+    qemu_set_irq(t->irq, pending);
+    trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending);
+}
+
+/* Start or resume the timer. */
+static void npcm7xx_timer_start(NPCM7xxTimer *t)
+{
+    int64_t now;
+
+    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    t->expires_ns = now + t->remaining_ns;
+    timer_mod(&t->qtimer, t->expires_ns);
+}
+
+/*
+ * Called when the counter reaches zero. Sets the interrupt flag, and either
+ * restarts or disables the timer.
+ */
+static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t)
+{
+    NPCM7xxTimerCtrlState *tc = t->ctrl;
+    int index = npcm7xx_timer_index(tc, t);
+
+    tc->tisr |= BIT(index);
+
+    if (t->tcsr & NPCM7XX_TCSR_PERIODIC) {
+        t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
+        if (t->tcsr & NPCM7XX_TCSR_CEN) {
+            npcm7xx_timer_start(t);
+        }
+    } else {
+        t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT);
+    }
+
+    npcm7xx_timer_check_interrupt(t);
+}
+
+/* Stop counting. Record the time remaining so we can continue later. */
+static void npcm7xx_timer_pause(NPCM7xxTimer *t)
+{
+    int64_t now;
+
+    timer_del(&t->qtimer);
+    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    t->remaining_ns = t->expires_ns - now;
+    if (t->remaining_ns <= 0) {
+        npcm7xx_timer_reached_zero(t);
+    }
+}
+
+/*
+ * Restart the timer from its initial value. If the timer was enabled and stays
+ * enabled, adjust the QEMU timer according to the new count. If the timer is
+ * transitioning from disabled to enabled, the caller is expected to start the
+ * timer later.
+ */
+static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr)
+{
+    t->remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr);
+
+    if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
+        npcm7xx_timer_start(t);
+    }
+}
+
+/* Register read and write handlers */
+
+static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t)
+{
+    if (t->tcsr & NPCM7XX_TCSR_CEN) {
+        int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+        return npcm7xx_timer_ns_to_count(t, t->expires_ns - now);
+    }
+
+    return npcm7xx_timer_ns_to_count(t, t->remaining_ns);
+}
+
+static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr)
+{
+    uint32_t old_tcsr = t->tcsr;
+    uint32_t tdr;
+
+    if (new_tcsr & NPCM7XX_TCSR_RSVD) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits in 0x%08x ignored\n",
+                      __func__, new_tcsr);
+        new_tcsr &= ~NPCM7XX_TCSR_RSVD;
+    }
+    if (new_tcsr & NPCM7XX_TCSR_CACT) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only bits in 0x%08x ignored\n",
+                      __func__, new_tcsr);
+        new_tcsr &= ~NPCM7XX_TCSR_CACT;
+    }
+    if ((new_tcsr & NPCM7XX_TCSR_CRST) && (new_tcsr & NPCM7XX_TCSR_CEN)) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: both CRST and CEN set; ignoring CEN.\n",
+                      __func__);
+        new_tcsr &= ~NPCM7XX_TCSR_CEN;
+    }
+
+    /* Calculate the value of TDR before potentially changing the prescaler. */
+    tdr = npcm7xx_timer_read_tdr(t);
+
+    t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr;
+
+    if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) {
+        /* Recalculate time remaining based on the current TDR value. */
+        t->remaining_ns = npcm7xx_timer_count_to_ns(t, tdr);
+        if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) {
+            npcm7xx_timer_start(t);
+        }
+    }
+
+    if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) {
+        npcm7xx_timer_check_interrupt(t);
+    }
+    if (new_tcsr & NPCM7XX_TCSR_CRST) {
+        npcm7xx_timer_restart(t, old_tcsr);
+        t->tcsr &= ~NPCM7XX_TCSR_CRST;
+    }
+    if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) {
+        if (new_tcsr & NPCM7XX_TCSR_CEN) {
+            t->tcsr |= NPCM7XX_TCSR_CACT;
+            npcm7xx_timer_start(t);
+        } else {
+            t->tcsr &= ~NPCM7XX_TCSR_CACT;
+            npcm7xx_timer_pause(t);
+        }
+    }
+}
+
+static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr)
+{
+    t->ticr = new_ticr;
+
+    npcm7xx_timer_restart(t, t->tcsr);
+}
+
+static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value)
+{
+    int i;
+
+    s->tisr &= ~value;
+    for (i = 0; i < ARRAY_SIZE(s->timer); i++) {
+        if (value & (1U << i)) {
+            npcm7xx_timer_check_interrupt(&s->timer[i]);
+        }
+    }
+}
+
+static hwaddr npcm7xx_tcsr_index(hwaddr reg)
+{
+    switch (reg) {
+    case NPCM7XX_TIMER_TCSR0:
+        return 0;
+    case NPCM7XX_TIMER_TCSR1:
+        return 1;
+    case NPCM7XX_TIMER_TCSR2:
+        return 2;
+    case NPCM7XX_TIMER_TCSR3:
+        return 3;
+    case NPCM7XX_TIMER_TCSR4:
+        return 4;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_ticr_index(hwaddr reg)
+{
+    switch (reg) {
+    case NPCM7XX_TIMER_TICR0:
+        return 0;
+    case NPCM7XX_TIMER_TICR1:
+        return 1;
+    case NPCM7XX_TIMER_TICR2:
+        return 2;
+    case NPCM7XX_TIMER_TICR3:
+        return 3;
+    case NPCM7XX_TIMER_TICR4:
+        return 4;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static hwaddr npcm7xx_tdr_index(hwaddr reg)
+{
+    switch (reg) {
+    case NPCM7XX_TIMER_TDR0:
+        return 0;
+    case NPCM7XX_TIMER_TDR1:
+        return 1;
+    case NPCM7XX_TIMER_TDR2:
+        return 2;
+    case NPCM7XX_TIMER_TDR3:
+        return 3;
+    case NPCM7XX_TIMER_TDR4:
+        return 4;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size)
+{
+    NPCM7xxTimerCtrlState *s = opaque;
+    uint64_t value = 0;
+    hwaddr reg;
+
+    reg = offset / sizeof(uint32_t);
+    switch (reg) {
+    case NPCM7XX_TIMER_TCSR0:
+    case NPCM7XX_TIMER_TCSR1:
+    case NPCM7XX_TIMER_TCSR2:
+    case NPCM7XX_TIMER_TCSR3:
+    case NPCM7XX_TIMER_TCSR4:
+        value = s->timer[npcm7xx_tcsr_index(reg)].tcsr;
+        break;
+
+    case NPCM7XX_TIMER_TICR0:
+    case NPCM7XX_TIMER_TICR1:
+    case NPCM7XX_TIMER_TICR2:
+    case NPCM7XX_TIMER_TICR3:
+    case NPCM7XX_TIMER_TICR4:
+        value = s->timer[npcm7xx_ticr_index(reg)].ticr;
+        break;
+
+    case NPCM7XX_TIMER_TDR0:
+    case NPCM7XX_TIMER_TDR1:
+    case NPCM7XX_TIMER_TDR2:
+    case NPCM7XX_TIMER_TDR3:
+    case NPCM7XX_TIMER_TDR4:
+        value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]);
+        break;
+
+    case NPCM7XX_TIMER_TISR:
+        value = s->tisr;
+        break;
+
+    case NPCM7XX_TIMER_WTCR:
+        value = s->wtcr;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                      __func__, offset);
+        break;
+    }
+
+    trace_npcm7xx_timer_read(DEVICE(s)->canonical_path, offset, value);
+
+    return value;
+}
+
+static void npcm7xx_timer_write(void *opaque, hwaddr offset,
+                                uint64_t v, unsigned size)
+{
+    uint32_t reg = offset / sizeof(uint32_t);
+    NPCM7xxTimerCtrlState *s = opaque;
+    uint32_t value = v;
+
+    trace_npcm7xx_timer_write(DEVICE(s)->canonical_path, offset, value);
+
+    switch (reg) {
+    case NPCM7XX_TIMER_TCSR0:
+    case NPCM7XX_TIMER_TCSR1:
+    case NPCM7XX_TIMER_TCSR2:
+    case NPCM7XX_TIMER_TCSR3:
+    case NPCM7XX_TIMER_TCSR4:
+        npcm7xx_timer_write_tcsr(&s->timer[npcm7xx_tcsr_index(reg)], value);
+        return;
+
+    case NPCM7XX_TIMER_TICR0:
+    case NPCM7XX_TIMER_TICR1:
+    case NPCM7XX_TIMER_TICR2:
+    case NPCM7XX_TIMER_TICR3:
+    case NPCM7XX_TIMER_TICR4:
+        npcm7xx_timer_write_ticr(&s->timer[npcm7xx_ticr_index(reg)], value);
+        return;
+
+    case NPCM7XX_TIMER_TDR0:
+    case NPCM7XX_TIMER_TDR1:
+    case NPCM7XX_TIMER_TDR2:
+    case NPCM7XX_TIMER_TDR3:
+    case NPCM7XX_TIMER_TDR4:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
+                      __func__, offset);
+        return;
+
+    case NPCM7XX_TIMER_TISR:
+        npcm7xx_timer_write_tisr(s, value);
+        return;
+
+    case NPCM7XX_TIMER_WTCR:
+        qemu_log_mask(LOG_UNIMP, "%s: WTCR write not implemented: 0x%08x\n",
+                      __func__, value);
+        return;
+    }
+
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
+                  __func__, offset);
+}
+
+static const struct MemoryRegionOps npcm7xx_timer_ops = {
+    .read       = npcm7xx_timer_read,
+    .write      = npcm7xx_timer_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+/* Called when the QEMU timer expires. */
+static void npcm7xx_timer_expired(void *opaque)
+{
+    NPCM7xxTimer *t = opaque;
+
+    if (t->tcsr & NPCM7XX_TCSR_CEN) {
+        npcm7xx_timer_reached_zero(t);
+    }
+}
+
+static void npcm7xx_timer_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
+        NPCM7xxTimer *t = &s->timer[i];
+
+        timer_del(&t->qtimer);
+        t->expires_ns = 0;
+        t->remaining_ns = 0;
+        t->tcsr = 0x00000005;
+        t->ticr = 0x00000000;
+    }
+
+    s->tisr = 0x00000000;
+    s->wtcr = 0x00000400;
+}
+
+static void npcm7xx_timer_hold_reset(Object *obj)
+{
+    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
+        qemu_irq_lower(s->timer[i].irq);
+    }
+}
+
+static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
+{
+    NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
+    SysBusDevice *sbd = &s->parent;
+    int i;
+
+    for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) {
+        NPCM7xxTimer *t = &s->timer[i];
+        t->ctrl = s;
+        timer_init_ns(&t->qtimer, QEMU_CLOCK_VIRTUAL, npcm7xx_timer_expired, t);
+        sysbus_init_irq(sbd, &t->irq);
+    }
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
+                          TYPE_NPCM7XX_TIMER, 4 * KiB);
+    sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_npcm7xx_timer = {
+    .name = "npcm7xx-timer",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_TIMER(qtimer, NPCM7xxTimer),
+        VMSTATE_INT64(expires_ns, NPCM7xxTimer),
+        VMSTATE_INT64(remaining_ns, NPCM7xxTimer),
+        VMSTATE_UINT32(tcsr, NPCM7xxTimer),
+        VMSTATE_UINT32(ticr, NPCM7xxTimer),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
+    .name = "npcm7xx-timer-ctrl",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
+        VMSTATE_UINT32(wtcr, NPCM7xxTimerCtrlState),
+        VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
+                             NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
+                             NPCM7xxTimer),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
+
+    dc->desc = "NPCM7xx Timer Controller";
+    dc->realize = npcm7xx_timer_realize;
+    dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
+    rc->phases.enter = npcm7xx_timer_enter_reset;
+    rc->phases.hold = npcm7xx_timer_hold_reset;
+}
+
+static const TypeInfo npcm7xx_timer_info = {
+    .name               = TYPE_NPCM7XX_TIMER,
+    .parent             = TYPE_SYS_BUS_DEVICE,
+    .instance_size      = sizeof(NPCM7xxTimerCtrlState),
+    .class_init         = npcm7xx_timer_class_init,
+};
+
+static void npcm7xx_timer_register_type(void)
+{
+    type_register_static(&npcm7xx_timer_info);
+}
+type_init(npcm7xx_timer_register_type);
diff --git a/hw/timer/meson.build b/hw/timer/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/meson.build
+++ b/hw/timer/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_LM32', if_true: files('lm32_timer.c'))
 softmmu_ss.add(when: 'CONFIG_MILKYMIST', if_true: files('milkymist-sysctl.c'))
 softmmu_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gictimer.c'))
 softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-timer.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_timer.c'))
 softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_timer.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gptimer.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_synctimer.c'))
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/trace-events
+++ b/hw/timer/trace-events
@@ -XXX,XX +XXX,XX @@ cmsdk_apb_dualtimer_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK A
 cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB dualtimer write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
 
+# npcm7xx_timer.c
+npcm7xx_timer_read(const char *id, uint64_t offset, uint64_t value) " %s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
+npcm7xx_timer_write(const char *id, uint64_t offset, uint64_t value) "%s offset: 0x%04" PRIx64 " value 0x%08" PRIx64
+npcm7xx_timer_irq(const char *id, int timer, int state) "%s timer %d state %d"
+
 # nrf51_timer.c
 nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
 nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

The Nuvoton NPCM7xx SoC family are used to implement Baseboard
Management Controllers in servers. While the family includes four SoCs,
this patch implements limited support for two of them: NPCM730 (targeted
for Data Center applications) and NPCM750 (targeted for Enterprise
applications).

This patch includes little more than the bare minimum needed to boot a
Linux kernel built with NPCM7xx support in direct-kernel mode:

- Two Cortex-A9 CPU cores with built-in periperhals.
  - Global Configuration Registers.
  - Clock Management.
  - 3 Timer Modules with 5 timers each.
  - 4 serial ports.

The chips themselves have a lot more features, some of which will be
added to the model at a later stage.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-5-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/npcm7xx.h |  85 ++++++++
 hw/arm/npcm7xx.c         | 407 +++++++++++++++++++++++++++++++++++++++
 hw/arm/Kconfig           |   5 +
 hw/arm/meson.build       |   1 +
 4 files changed, 498 insertions(+)
 create mode 100644 include/hw/arm/npcm7xx.h
 create mode 100644 hw/arm/npcm7xx.c

diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx SoC family.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_H
+#define NPCM7XX_H
+
+#include "hw/boards.h"
+#include "hw/cpu/a9mpcore.h"
+#include "hw/misc/npcm7xx_clk.h"
+#include "hw/misc/npcm7xx_gcr.h"
+#include "hw/timer/npcm7xx_timer.h"
+#include "target/arm/cpu.h"
+
+#define NPCM7XX_MAX_NUM_CPUS    (2)
+
+/* The first half of the address space is reserved for DDR4 DRAM. */
+#define NPCM7XX_DRAM_BA         (0x00000000)
+#define NPCM7XX_DRAM_SZ         (2 * GiB)
+
+/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */
+#define NPCM7XX_LOADER_START            (0x00000000)  /* Start of SDRAM */
+#define NPCM7XX_SMP_LOADER_START        (0xffff0000)  /* Boot ROM */
+#define NPCM7XX_SMP_BOOTREG_ADDR        (0xf080013c)  /* GCR.SCRPAD */
+#define NPCM7XX_GIC_CPU_IF_ADDR         (0xf03fe100)  /* GIC within A9 */
+
+typedef struct NPCM7xxState {
+    DeviceState         parent;
+
+    ARMCPU              cpu[NPCM7XX_MAX_NUM_CPUS];
+    A9MPPrivState       a9mpcore;
+
+    MemoryRegion        sram;
+    MemoryRegion        irom;
+    MemoryRegion        ram3;
+    MemoryRegion        *dram;
+
+    NPCM7xxGCRState     gcr;
+    NPCM7xxCLKState     clk;
+    NPCM7xxTimerCtrlState tim[3];
+} NPCM7xxState;
+
+#define TYPE_NPCM7XX    "npcm7xx"
+#define NPCM7XX(obj)    OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
+
+#define TYPE_NPCM730    "npcm730"
+#define TYPE_NPCM750    "npcm750"
+
+typedef struct NPCM7xxClass {
+    DeviceClass         parent;
+
+    /* Bitmask of modules that are permanently disabled on this chip. */
+    uint32_t            disabled_modules;
+    /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */
+    uint32_t            num_cpus;
+} NPCM7xxClass;
+
+#define NPCM7XX_CLASS(klass)                                            \
+    OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
+#define NPCM7XX_GET_CLASS(obj)                                          \
+    OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
+
+/**
+ * npcm7xx_load_kernel - Loads memory with everything needed to boot
+ * @machine - The machine containing the SoC to be booted.
+ * @soc - The SoC containing the CPU to be booted.
+ *
+ * This will set up the ARM boot info structure for the specific NPCM7xx
+ * derivative and call arm_load_kernel() to set up loading of the kernel, etc.
+ * into memory, if requested by the user.
+ */
+void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc);
+
+#endif /* NPCM7XX_H */
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx SoC family.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "exec/address-spaces.h"
+#include "hw/arm/boot.h"
+#include "hw/arm/npcm7xx.h"
+#include "hw/char/serial.h"
+#include "hw/loader.h"
+#include "hw/misc/unimp.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qemu/units.h"
+#include "sysemu/sysemu.h"
+
+/*
+ * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
+ * that aren't handled by any device.
+ */
+#define NPCM7XX_MMIO_BA         (0x80000000)
+#define NPCM7XX_MMIO_SZ         (0x7ffd0000)
+
+/* Core system modules. */
+#define NPCM7XX_L2C_BA          (0xf03fc000)
+#define NPCM7XX_CPUP_BA         (0xf03fe000)
+#define NPCM7XX_GCR_BA          (0xf0800000)
+#define NPCM7XX_CLK_BA          (0xf0801000)
+
+/* Internal AHB SRAM */
+#define NPCM7XX_RAM3_BA         (0xc0008000)
+#define NPCM7XX_RAM3_SZ         (4 * KiB)
+
+/* Memory blocks at the end of the address space */
+#define NPCM7XX_RAM2_BA         (0xfffd0000)
+#define NPCM7XX_RAM2_SZ         (128 * KiB)
+#define NPCM7XX_ROM_BA          (0xffff0000)
+#define NPCM7XX_ROM_SZ          (64 * KiB)
+
+/*
+ * Interrupt lines going into the GIC. This does not include internal Cortex-A9
+ * interrupts.
+ */
+enum NPCM7xxInterrupt {
+    NPCM7XX_UART0_IRQ           = 2,
+    NPCM7XX_UART1_IRQ,
+    NPCM7XX_UART2_IRQ,
+    NPCM7XX_UART3_IRQ,
+    NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
+    NPCM7XX_TIMER1_IRQ,
+    NPCM7XX_TIMER2_IRQ,
+    NPCM7XX_TIMER3_IRQ,
+    NPCM7XX_TIMER4_IRQ,
+    NPCM7XX_TIMER5_IRQ,                 /* Timer Module 1 */
+    NPCM7XX_TIMER6_IRQ,
+    NPCM7XX_TIMER7_IRQ,
+    NPCM7XX_TIMER8_IRQ,
+    NPCM7XX_TIMER9_IRQ,
+    NPCM7XX_TIMER10_IRQ,                /* Timer Module 2 */
+    NPCM7XX_TIMER11_IRQ,
+    NPCM7XX_TIMER12_IRQ,
+    NPCM7XX_TIMER13_IRQ,
+    NPCM7XX_TIMER14_IRQ,
+};
+
+/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
+#define NPCM7XX_NUM_IRQ         (160)
+
+/* Register base address for each Timer Module */
+static const hwaddr npcm7xx_tim_addr[] = {
+    0xf0008000,
+    0xf0009000,
+    0xf000a000,
+};
+
+/* Register base address for each 16550 UART */
+static const hwaddr npcm7xx_uart_addr[] = {
+    0xf0001000,
+    0xf0002000,
+    0xf0003000,
+    0xf0004000,
+};
+
+static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
+                                         const struct arm_boot_info *info)
+{
+    /*
+     * The default smpboot stub halts the secondary CPU with a 'wfi'
+     * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
+     * does not send an IPI to wake it up, so the second CPU fails to boot. So
+     * we need to provide our own smpboot stub that can not use 'wfi', it has
+     * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
+     */
+    uint32_t smpboot[] = {
+        0xe59f2018,     /* ldr r2, bootreg_addr */
+        0xe3a00000,     /* mov r0, #0 */
+        0xe5820000,     /* str r0, [r2] */
+        0xe320f002,     /* wfe */
+        0xe5921000,     /* ldr r1, [r2] */
+        0xe1110001,     /* tst r1, r1 */
+        0x0afffffb,     /* beq <wfe> */
+        0xe12fff11,     /* bx r1 */
+        NPCM7XX_SMP_BOOTREG_ADDR,
+    };
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
+        smpboot[i] = tswap32(smpboot[i]);
+    }
+
+    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
+                       NPCM7XX_SMP_LOADER_START);
+}
+
+static struct arm_boot_info npcm7xx_binfo = {
+    .loader_start           = NPCM7XX_LOADER_START,
+    .smp_loader_start       = NPCM7XX_SMP_LOADER_START,
+    .smp_bootreg_addr       = NPCM7XX_SMP_BOOTREG_ADDR,
+    .gic_cpu_if_addr        = NPCM7XX_GIC_CPU_IF_ADDR,
+    .write_secondary_boot   = npcm7xx_write_secondary_boot,
+    .board_id               = -1,
+};
+
+void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
+{
+    NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc);
+
+    npcm7xx_binfo.ram_size = machine->ram_size;
+    npcm7xx_binfo.nb_cpus = sc->num_cpus;
+
+    arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
+}
+
+static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
+{
+    return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
+}
+
+static void npcm7xx_init(Object *obj)
+{
+    NPCM7xxState *s = NPCM7XX(obj);
+    int i;
+
+    for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
+        object_initialize_child(obj, "cpu[*]", &s->cpu[i],
+                                ARM_CPU_TYPE_NAME("cortex-a9"));
+    }
+
+    object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+    object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
+    object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
+                              "power-on-straps");
+    object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
+
+    for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
+        object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
+    }
+}
+
+static void npcm7xx_realize(DeviceState *dev, Error **errp)
+{
+    NPCM7xxState *s = NPCM7XX(dev);
+    NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
+    int i;
+
+    if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) {
+        error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64
+                   " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB);
+        return;
+    }
+
+    /* CPUs */
+    for (i = 0; i < nc->num_cpus; i++) {
+        object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
+                                arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
+                                &error_abort);
+        object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
+                                NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
+        object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
+                                 &error_abort);
+
+        /* Disable security extensions. */
+        object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
+                                 &error_abort);
+
+        if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
+            return;
+        }
+    }
+
+    /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */
+    object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus,
+                            &error_abort);
+    object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ,
+                            &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
+
+    for (i = 0; i < nc->num_cpus; i++) {
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
+                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
+                           qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
+    }
+
+    /* L2 cache controller */
+    sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
+
+    /* System Global Control Registers (GCR). Can fail due to user input. */
+    object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
+                            nc->disabled_modules, &error_abort);
+    object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
+
+    /* Clock Control Registers (CLK). Cannot fail. */
+    sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
+
+    /* Timer Modules (TIM). Cannot fail. */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
+    for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
+        int first_irq;
+        int j;
+
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
+
+        first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
+        for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
+            qemu_irq irq = npcm7xx_irq(s, first_irq + j);
+            sysbus_connect_irq(sbd, j, irq);
+        }
+    }
+
+    /* UART0..3 (16550 compatible) */
+    for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
+        serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
+                       npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
+                       serial_hd(i), DEVICE_LITTLE_ENDIAN);
+    }
+
+    /* RAM2 (SRAM) */
+    memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
+                           NPCM7XX_RAM2_SZ, &error_abort);
+    memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
+
+    /* RAM3 (SRAM) */
+    memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
+                           NPCM7XX_RAM3_SZ, &error_abort);
+    memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3);
+
+    /* Internal ROM */
+    memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
+
+    create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
+    create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.rng",          0xf000b000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.adc",          0xf000c000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gpio[0]",      0xf0010000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gpio[1]",      0xf0011000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gpio[2]",      0xf0012000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gpio[3]",      0xf0013000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gpio[4]",      0xf0014000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gpio[5]",      0xf0015000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gpio[6]",      0xf0016000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.gpio[7]",      0xf0017000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[0]",     0xf0080000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[1]",     0xf0081000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[2]",     0xf0082000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[3]",     0xf0083000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[4]",     0xf0084000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[5]",     0xf0085000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[6]",     0xf0086000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[7]",     0xf0087000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[8]",     0xf0088000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[9]",     0xf0089000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[10]",    0xf008a000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[11]",    0xf008b000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[12]",    0xf008c000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[13]",    0xf008d000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[14]",    0xf008e000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.smbus[15]",    0xf008f000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.espi",         0xf009f000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.pwm[0]",       0xf0103000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.pwm[1]",       0xf0104000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.mft[3]",       0xf0183000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.mft[4]",       0xf0184000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.mft[5]",       0xf0185000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.mft[6]",       0xf0186000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.mft[7]",       0xf0187000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
+    create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
+    create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
+    create_unimplemented_device("npcm7xx.gmac2",        0xf0804000,   8 * KiB);
+    create_unimplemented_device("npcm7xx.ehci",         0xf0806000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.ohci",         0xf0807000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.vcd",          0xf0810000,  64 * KiB);
+    create_unimplemented_device("npcm7xx.ece",          0xf0820000,   8 * KiB);
+    create_unimplemented_device("npcm7xx.vdma",         0xf0822000,   8 * KiB);
+    create_unimplemented_device("npcm7xx.emc1",         0xf0825000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.emc2",         0xf0826000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[0]",      0xf0830000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[1]",      0xf0831000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[2]",      0xf0832000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[3]",      0xf0833000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[4]",      0xf0834000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[5]",      0xf0835000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[6]",      0xf0836000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[7]",      0xf0837000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[8]",      0xf0838000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.usbd[9]",      0xf0839000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.sd",           0xf0840000,   8 * KiB);
+    create_unimplemented_device("npcm7xx.mmc",          0xf0842000,   8 * KiB);
+    create_unimplemented_device("npcm7xx.pcimbx",       0xf0848000, 512 * KiB);
+    create_unimplemented_device("npcm7xx.aes",          0xf0858000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.des",          0xf0859000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.sha",          0xf085a000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.secacc",       0xf085b000,   4 * KiB);
+    create_unimplemented_device("npcm7xx.spixcs0",      0xf8000000,  16 * MiB);
+    create_unimplemented_device("npcm7xx.spixcs1",      0xf9000000,  16 * MiB);
+    create_unimplemented_device("npcm7xx.spix",         0xfb001000,   4 * KiB);
+}
+
+static Property npcm7xx_properties[] = {
+    DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION,
+                     MemoryRegion *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = npcm7xx_realize;
+    dc->user_creatable = false;
+    device_class_set_props(dc, npcm7xx_properties);
+}
+
+static void npcm730_class_init(ObjectClass *oc, void *data)
+{
+    NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
+
+    /* NPCM730 is optimized for data center use, so no graphics, etc. */
+    nc->disabled_modules = 0x00300395;
+    nc->num_cpus = 2;
+}
+
+static void npcm750_class_init(ObjectClass *oc, void *data)
+{
+    NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
+
+    /* NPCM750 has 2 cores and a full set of peripherals */
+    nc->disabled_modules = 0x00000000;
+    nc->num_cpus = 2;
+}
+
+static const TypeInfo npcm7xx_soc_types[] = {
+    {
+        .name           = TYPE_NPCM7XX,
+        .parent         = TYPE_DEVICE,
+        .instance_size  = sizeof(NPCM7xxState),
+        .instance_init  = npcm7xx_init,
+        .class_size     = sizeof(NPCM7xxClass),
+        .class_init     = npcm7xx_class_init,
+        .abstract       = true,
+    }, {
+        .name           = TYPE_NPCM730,
+        .parent         = TYPE_NPCM7XX,
+        .class_init     = npcm730_class_init,
+    }, {
+        .name           = TYPE_NPCM750,
+        .parent         = TYPE_NPCM7XX,
+        .class_init     = npcm750_class_init,
+    },
+};
+
+DEFINE_TYPES(npcm7xx_soc_types);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config XLNX_VERSAL
 
 config NPCM7XX
     bool
+    select A9MPCORE
+    select ARM_GIC
+    select PL310  # cache controller
+    select SERIAL
+    select UNIMP
 
 config FSL_IMX25
     bool
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
 arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
 arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
 arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
+arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c'))
 arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
 arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
 arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

This adds two new machines, both supported by OpenBMC:

- npcm750-evb: Nuvoton NPCM750 Evaluation Board.
  - quanta-gsj: A board with a NPCM730 chip.

They rely on the NPCM7xx SoC device to do the heavy lifting. They are
almost completely identical at the moment, apart from the SoC type,
which currently only changes the reset contents of one register
(GCR.MDLR), but they might grow apart a bit more as more functionality
is added.

Both machines can boot the Linux kernel into /bin/sh.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-6-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 default-configs/arm-softmmu.mak |   1 +
 include/hw/arm/npcm7xx.h        |  19 +++++
 hw/arm/npcm7xx_boards.c         | 145 ++++++++++++++++++++++++++++++++
 hw/arm/meson.build              |   2 +-
 4 files changed, 166 insertions(+), 1 deletion(-)
 create mode 100644 hw/arm/npcm7xx_boards.c

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_GUMSTIX=y
 CONFIG_SPITZ=y
 CONFIG_TOSA=y
 CONFIG_Z2=y
+CONFIG_NPCM7XX=y
 CONFIG_COLLIE=y
 CONFIG_ASPEED_SOC=y
 CONFIG_NETDUINO2=y
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_SMP_BOOTREG_ADDR        (0xf080013c)  /* GCR.SCRPAD */
 #define NPCM7XX_GIC_CPU_IF_ADDR         (0xf03fe100)  /* GIC within A9 */
 
+typedef struct NPCM7xxMachine {
+    MachineState        parent;
+} NPCM7xxMachine;
+
+#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
+#define NPCM7XX_MACHINE(obj)                                            \
+    OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
+
+typedef struct NPCM7xxMachineClass {
+    MachineClass        parent;
+
+    const char          *soc_type;
+} NPCM7xxMachineClass;
+
+#define NPCM7XX_MACHINE_CLASS(klass)                                    \
+    OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE)
+#define NPCM7XX_MACHINE_GET_CLASS(obj)                                  \
+    OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
+
 typedef struct NPCM7xxState {
     DeviceState         parent;
 
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Machine definitions for boards featuring an NPCM7xx SoC.
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "exec/address-spaces.h"
+#include "hw/arm/npcm7xx.h"
+#include "hw/core/cpu.h"
+#include "qapi/error.h"
+#include "qemu/units.h"
+
+#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
+#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
+
+static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
+{
+    memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
+
+    object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram),
+                             &error_abort);
+}
+
+static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
+                                        uint32_t hw_straps)
+{
+    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
+    MachineClass *mc = &nmc->parent;
+    Object *obj;
+
+    if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
+        error_report("This board can only be used with %s",
+                     mc->default_cpu_type);
+        exit(1);
+    }
+
+    obj = object_new_with_props(nmc->soc_type, OBJECT(machine), "soc",
+                                &error_abort, NULL);
+    object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abort);
+
+    return NPCM7XX(obj);
+}
+
+static void npcm750_evb_init(MachineState *machine)
+{
+    NPCM7xxState *soc;
+
+    soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS);
+    npcm7xx_connect_dram(soc, machine->ram);
+    qdev_realize(DEVICE(soc), NULL, &error_fatal);
+
+    npcm7xx_load_kernel(machine, soc);
+}
+
+static void quanta_gsj_init(MachineState *machine)
+{
+    NPCM7xxState *soc;
+
+    soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS);
+    npcm7xx_connect_dram(soc, machine->ram);
+    qdev_realize(DEVICE(soc), NULL, &error_fatal);
+
+    npcm7xx_load_kernel(machine, soc);
+}
+
+static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type)
+{
+    NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type));
+    MachineClass *mc = MACHINE_CLASS(nmc);
+
+    nmc->soc_type = type;
+    mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus;
+}
+
+static void npcm7xx_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->no_floppy = 1;
+    mc->no_cdrom = 1;
+    mc->no_parallel = 1;
+    mc->default_ram_id = "ram";
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
+}
+
+/*
+ * Schematics:
+ * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf
+ */
+static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
+{
+    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    npcm7xx_set_soc_type(nmc, TYPE_NPCM750);
+
+    mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)";
+    mc->init = npcm750_evb_init;
+    mc->default_ram_size = 512 * MiB;
+};
+
+static void gsj_machine_class_init(ObjectClass *oc, void *data)
+{
+    NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc);
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    npcm7xx_set_soc_type(nmc, TYPE_NPCM730);
+
+    mc->desc = "Quanta GSJ (Cortex A9)";
+    mc->init = quanta_gsj_init;
+    mc->default_ram_size = 512 * MiB;
+};
+
+static const TypeInfo npcm7xx_machine_types[] = {
+    {
+        .name           = TYPE_NPCM7XX_MACHINE,
+        .parent         = TYPE_MACHINE,
+        .instance_size  = sizeof(NPCM7xxMachine),
+        .class_size     = sizeof(NPCM7xxMachineClass),
+        .class_init     = npcm7xx_machine_class_init,
+        .abstract       = true,
+    }, {
+        .name           = MACHINE_TYPE_NAME("npcm750-evb"),
+        .parent         = TYPE_NPCM7XX_MACHINE,
+        .class_init     = npcm750_evb_machine_class_init,
+    }, {
+        .name           = MACHINE_TYPE_NAME("quanta-gsj"),
+        .parent         = TYPE_NPCM7XX_MACHINE,
+        .class_init     = gsj_machine_class_init,
+    },
+};
+
+DEFINE_TYPES(npcm7xx_machine_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
 arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
 arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
 arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
-arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c'))
+arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
 arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
 arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
 arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

This is a minimalistic boot ROM written specifically for use with QEMU.
It supports loading the second-stage loader from SPI flash into RAM, SMP
boot, and not much else.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-7-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 .gitmodules                 |   3 +++
 MAINTAINERS                 |   2 ++
 pc-bios/README              |   6 ++++++
 pc-bios/meson.build         |   1 +
 pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
 roms/Makefile               |   7 +++++++
 roms/vbootrom               |   1 +
 7 files changed, 20 insertions(+)
 create mode 100644 pc-bios/npcm7xx_bootrom.bin
 create mode 160000 roms/vbootrom

diff --git a/.gitmodules b/.gitmodules
index XXXXXXX..XXXXXXX 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -XXX,XX +XXX,XX @@
 [submodule "meson"]
 	path = meson
 	url = https://github.com/mesonbuild/meson/
+[submodule "roms/vbootrom"]
+	path = roms/vbootrom
+	url = https://github.com/google/vbootrom.git
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Supported
 F: hw/*/npcm7xx*
 F: include/hw/*/npcm7xx*
+F: pc-bios/npcm7xx_bootrom.bin
+F: roms/vbootrom
 
 nSeries
 M: Andrzej Zaborowski <balrogg@gmail.com>
diff --git a/pc-bios/README b/pc-bios/README
index XXXXXXX..XXXXXXX 100644
--- a/pc-bios/README
+++ b/pc-bios/README
@@ -XXX,XX +XXX,XX @@
   ("Simplified BSD License" or "FreeBSD License", SPDX: BSD-2-Clause). OpenSBI
   source code also contains code reused from other projects desribed here:
   https://github.com/riscv/opensbi/blob/master/ThirdPartyNotices.md.
+
+- npcm7xx_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for Nuvoton
+  NPCM7xx BMC devices. It currently implements the bare minimum to load, parse,
+  initialize and run boot images stored in SPI flash, but may grow more
+  features over time as needed. The source code is available at:
+  https://github.com/google/vbootrom
diff --git a/pc-bios/meson.build b/pc-bios/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/pc-bios/meson.build
+++ b/pc-bios/meson.build
@@ -XXX,XX +XXX,XX @@ blobs = files(
   'opensbi-riscv64-generic-fw_dynamic.bin',
   'opensbi-riscv32-generic-fw_dynamic.elf',
   'opensbi-riscv64-generic-fw_dynamic.elf',
+  'npcm7xx_bootrom.bin',
 )
 
 if install_blobs
diff --git a/pc-bios/npcm7xx_bootrom.bin b/pc-bios/npcm7xx_bootrom.bin
new file mode 100644
index XXXXXXX..XXXXXXX
GIT binary patch
literal 768
zcmd5)JxClu6n-<aczPbVhZYusb8wKx;7TklHfmuZdYT9pDRLwd1p_t-DFpWpyA+8(
zwKtZg3J4a0aCM3_X(ZL&4g;46VVk5e$K;z;L99|b@aE%v^S$rQ8)h(Vm@cB9IYc+2
z2SHd4^NwTIGE%w>9S05p1#kf90Sj5Z(jG8}+)IZIp~iXK=T&)dL`%d-q*8aR#mq{7
z9`=6;Dr(H0ACe72R5x?!)^86Qj-X%{+!K9iZNA@*wkBAV&iZ(l^I9?!Gz=S2I_*1d
zr+tTQDHjvyzKnw(hu00yX`u!Fv<!~XVcX?@kr#<B0(gGU?$W{gSsQa}CF^8Cfzp2X
z@P}yDV-bci(K9XL$FU!som2C`c)?Uc&294s^}Wzumap{hg1X^jN|V25M5tQZ=<9lN
z%(zKz#t-qCwHKb;HygOCpvCNL_4@1tXV1YGf^XUE_$zr{g8zWh-6gz-teI(eibtxo
z?0OZI4%rU0741PgUD`2xq@H|*4=+Rs?%N)Ox5G+q>C;DilBe_YlkeSUVHA-crNk+k
jtiF_MudA<CB(}8|fqYwCf3re&=&@_s761P#-ID$TwgmBa

literal 0
HcmV?d00001

diff --git a/roms/Makefile b/roms/Makefile
index XXXXXXX..XXXXXXX 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -XXX,XX +XXX,XX @@ find-cross-gcc = $(firstword $(wildcard $(patsubst %ld,%gcc,$(call find-cross-ld
 # finally strip off path + toolname so we get the prefix
 find-cross-prefix = $(subst gcc,,$(notdir $(call find-cross-gcc,$(1))))
 
+arm_cross_prefix := $(call find-cross-prefix,arm)
 powerpc64_cross_prefix := $(call find-cross-prefix,powerpc64)
 powerpc_cross_prefix := $(call find-cross-prefix,powerpc)
 x86_64_cross_prefix := $(call find-cross-prefix,x86_64)
@@ -XXX,XX +XXX,XX @@ default help:
 	@echo "  skiboot            -- update skiboot.lid"
 	@echo "  u-boot.e500        -- update u-boot.e500"
 	@echo "  u-boot.sam460      -- update u-boot.sam460"
+	@echo "  npcm7xx_bootrom    -- update vbootrom for npcm7xx"
 	@echo "  efi                -- update UEFI (edk2) platform firmware"
 	@echo "  opensbi32-generic  -- update OpenSBI for 32-bit generic machine"
 	@echo "  opensbi64-generic  -- update OpenSBI for 64-bit generic machine"
@@ -XXX,XX +XXX,XX @@ bios-microvm:
 	$(MAKE) -C qboot
 	cp qboot/bios.bin ../pc-bios/bios-microvm.bin
 
+npcm7xx_bootrom:
+	$(MAKE) -C vbootrom CROSS_COMPILE=$(arm_cross_prefix)
+	cp vbootrom/npcm7xx_bootrom.bin ../pc-bios/npcm7xx_bootrom.bin
+
 clean:
 	rm -rf seabios/.config seabios/out seabios/builds
 	$(MAKE) -C sgabios clean
@@ -XXX,XX +XXX,XX @@ clean:
 	$(MAKE) -f Makefile.edk2 clean
 	$(MAKE) -C opensbi clean
 	$(MAKE) -C qboot clean
+	$(MAKE) -C vbootrom clean
diff --git a/roms/vbootrom b/roms/vbootrom
new file mode 160000
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/roms/vbootrom
@@ -0,0 +1 @@
+Subproject commit 0c37a43527f0ee2b9584e7fb2fdc805e902635ac
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

If a -bios option is specified on the command line, load the image into
the internal ROM memory region, which contains the first instructions
run by the CPU after reset.

If -bios is not specified, the vbootrom included with qemu is loaded by
default.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-8-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx_boards.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/address-spaces.h"
 #include "hw/arm/npcm7xx.h"
 #include "hw/core/cpu.h"
+#include "hw/loader.h"
 #include "qapi/error.h"
+#include "qemu-common.h"
 #include "qemu/units.h"
+#include "sysemu/sysemu.h"
 
 #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
 
+static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
+
+static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
+{
+    g_autofree char *filename = NULL;
+    int ret;
+
+    if (!bios_name) {
+        bios_name = npcm7xx_default_bootrom;
+    }
+
+    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
+    if (!filename) {
+        error_report("Could not find ROM image '%s'", bios_name);
+        if (!machine->kernel_filename) {
+            /* We can't boot without a bootrom or a kernel image. */
+            exit(1);
+        }
+        return;
+    }
+    ret = load_image_mr(filename, &soc->irom);
+    if (ret < 0) {
+        error_report("Failed to load ROM image '%s'", filename);
+        exit(1);
+    }
+}
+
 static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
 {
     memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
@@ -XXX,XX +XXX,XX @@ static void npcm750_evb_init(MachineState *machine)
     npcm7xx_connect_dram(soc, machine->ram);
     qdev_realize(DEVICE(soc), NULL, &error_fatal);
 
+    npcm7xx_load_bootrom(machine, soc);
     npcm7xx_load_kernel(machine, soc);
 }
 
@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_init(MachineState *machine)
     npcm7xx_connect_dram(soc, machine->ram);
     qdev_realize(DEVICE(soc), NULL, &error_fatal);
 
+    npcm7xx_load_bootrom(machine, soc);
     npcm7xx_load_kernel(machine, soc);
 }
 
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.

Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-9-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/npcm7xx.h       |   3 +
 include/hw/nvram/npcm7xx_otp.h |  79 ++++++
 hw/arm/npcm7xx.c               |  29 +++
 hw/nvram/npcm7xx_otp.c         | 440 +++++++++++++++++++++++++++++++++
 hw/nvram/meson.build           |   1 +
 5 files changed, 552 insertions(+)
 create mode 100644 include/hw/nvram/npcm7xx_otp.h
 create mode 100644 hw/nvram/npcm7xx_otp.c

diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/cpu/a9mpcore.h"
 #include "hw/misc/npcm7xx_clk.h"
 #include "hw/misc/npcm7xx_gcr.h"
+#include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "target/arm/cpu.h"
 
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxGCRState     gcr;
     NPCM7xxCLKState     clk;
     NPCM7xxTimerCtrlState tim[3];
+    NPCM7xxOTPState     key_storage;
+    NPCM7xxOTPState     fuse_array;
 } NPCM7xxState;
 
 #define TYPE_NPCM7XX    "npcm7xx"
diff --git a/include/hw/nvram/npcm7xx_otp.h b/include/hw/nvram/npcm7xx_otp.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/nvram/npcm7xx_otp.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx OTP (Fuse Array) Interface
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_OTP_H
+#define NPCM7XX_OTP_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+/* Each OTP module holds 8192 bits of one-time programmable storage */
+#define NPCM7XX_OTP_ARRAY_BITS (8192)
+#define NPCM7XX_OTP_ARRAY_BYTES (NPCM7XX_OTP_ARRAY_BITS / BITS_PER_BYTE)
+
+/* Fuse array offsets */
+#define NPCM7XX_FUSE_FUSTRAP (0)
+#define NPCM7XX_FUSE_CP_FUSTRAP (12)
+#define NPCM7XX_FUSE_DAC_CALIB (16)
+#define NPCM7XX_FUSE_ADC_CALIB (24)
+#define NPCM7XX_FUSE_DERIVATIVE (64)
+#define NPCM7XX_FUSE_TEST_SIG (72)
+#define NPCM7XX_FUSE_DIE_LOCATION (74)
+#define NPCM7XX_FUSE_GP1 (80)
+#define NPCM7XX_FUSE_GP2 (128)
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM7XX_OTP_NR_REGS (0x18 / sizeof(uint32_t))
+
+/**
+ * struct NPCM7xxOTPState - Device state for one OTP module.
+ * @parent: System bus device.
+ * @mmio: Memory region through which registers are accessed.
+ * @regs: Register contents.
+ * @array: OTP storage array.
+ */
+typedef struct NPCM7xxOTPState {
+    SysBusDevice parent;
+
+    MemoryRegion mmio;
+    uint32_t regs[NPCM7XX_OTP_NR_REGS];
+    uint8_t array[NPCM7XX_OTP_ARRAY_BYTES];
+} NPCM7xxOTPState;
+
+#define TYPE_NPCM7XX_OTP "npcm7xx-otp"
+#define NPCM7XX_OTP(obj) OBJECT_CHECK(NPCM7xxOTPState, (obj), TYPE_NPCM7XX_OTP)
+
+#define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
+#define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
+
+typedef struct NPCM7xxOTPClass NPCM7xxOTPClass;
+
+/**
+ * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
+ * @s: OTP module.
+ * @data: Data to be encoded and written.
+ * @offset: Offset of first byte to be written in the OTP array.
+ * @len: Number of bytes before ECC encoding.
+ *
+ * Each nibble of data is encoded into a byte, so the number of bytes written
+ * to the array will be @len * 2.
+ */
+extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
+                                    unsigned int offset, unsigned int len);
+
+#endif /* NPCM7XX_OTP_H */
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_MMIO_BA         (0x80000000)
 #define NPCM7XX_MMIO_SZ         (0x7ffd0000)
 
+/* OTP key storage and fuse strap array */
+#define NPCM7XX_OTP1_BA         (0xf0189000)
+#define NPCM7XX_OTP2_BA         (0xf018a000)
+
 /* Core system modules. */
 #define NPCM7XX_L2C_BA          (0xf03fc000)
 #define NPCM7XX_CPUP_BA         (0xf03fe000)
@@ -XXX,XX +XXX,XX @@ void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
     arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
 }
 
+static void npcm7xx_init_fuses(NPCM7xxState *s)
+{
+    NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
+    uint32_t value;
+
+    /*
+     * The initial mask of disabled modules indicates the chip derivative (e.g.
+     * NPCM750 or NPCM730).
+     */
+    value = tswap32(nc->disabled_modules);
+    npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
+                            sizeof(value));
+}
+
 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
 {
     return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
     object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
                               "power-on-straps");
     object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
+    object_initialize_child(obj, "otp1", &s->key_storage,
+                            TYPE_NPCM7XX_KEY_STORAGE);
+    object_initialize_child(obj, "otp2", &s->fuse_array,
+                            TYPE_NPCM7XX_FUSE_ARRAY);
 
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
         object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
 
+    /* OTP key storage and fuse strap array. Cannot fail. */
+    sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
+    sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
+    npcm7xx_init_fuses(s);
+
     /* Timer Modules (TIM). Cannot fail. */
     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/nvram/npcm7xx_otp.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx OTP (Fuse Array) Interface
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/nvram/npcm7xx_otp.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+/* Each module has 4 KiB of register space. Only a fraction of it is used. */
+#define NPCM7XX_OTP_REGS_SIZE (4 * KiB)
+
+/* 32-bit register indices. */
+typedef enum NPCM7xxOTPRegister {
+    NPCM7XX_OTP_FST,
+    NPCM7XX_OTP_FADDR,
+    NPCM7XX_OTP_FDATA,
+    NPCM7XX_OTP_FCFG,
+    /* Offset 0x10 is FKEYIND in OTP1, FUSTRAP in OTP2 */
+    NPCM7XX_OTP_FKEYIND = 0x0010 / sizeof(uint32_t),
+    NPCM7XX_OTP_FUSTRAP = 0x0010 / sizeof(uint32_t),
+    NPCM7XX_OTP_FCTL,
+    NPCM7XX_OTP_REGS_END,
+} NPCM7xxOTPRegister;
+
+/* Register field definitions. */
+#define FST_RIEN BIT(2)
+#define FST_RDST BIT(1)
+#define FST_RDY BIT(0)
+#define FST_RO_MASK (FST_RDST | FST_RDY)
+
+#define FADDR_BYTEADDR(rv) extract32((rv), 0, 10)
+#define FADDR_BITPOS(rv) extract32((rv), 10, 3)
+
+#define FDATA_CLEAR 0x00000001
+
+#define FCFG_FDIS BIT(31)
+#define FCFG_FCFGLK_MASK 0x00ff0000
+
+#define FCTL_PROG_CMD1 0x00000001
+#define FCTL_PROG_CMD2 0xbf79e5d0
+#define FCTL_READ_CMD 0x00000002
+
+/**
+ * struct NPCM7xxOTPClass - OTP module class.
+ * @parent: System bus device class.
+ * @mmio_ops: MMIO register operations for this type of module.
+ *
+ * The two OTP modules (key-storage and fuse-array) have slightly different
+ * behavior, so we give them different MMIO register operations.
+ */
+struct NPCM7xxOTPClass {
+    SysBusDeviceClass parent;
+
+    const MemoryRegionOps *mmio_ops;
+};
+
+#define NPCM7XX_OTP_CLASS(klass) \
+    OBJECT_CLASS_CHECK(NPCM7xxOTPClass, (klass), TYPE_NPCM7XX_OTP)
+#define NPCM7XX_OTP_GET_CLASS(obj) \
+    OBJECT_GET_CLASS(NPCM7xxOTPClass, (obj), TYPE_NPCM7XX_OTP)
+
+static uint8_t ecc_encode_nibble(uint8_t n)
+{
+    uint8_t result = n;
+
+    result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4;
+    result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5;
+    result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6;
+    result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7;
+
+    return result;
+}
+
+void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
+                             unsigned int offset, unsigned int len)
+{
+    const uint8_t *src = data;
+    uint8_t *dst = &s->array[offset];
+
+    while (len-- > 0) {
+        uint8_t c = *src++;
+
+        *dst++ = ecc_encode_nibble(extract8(c, 0, 4));
+        *dst++ = ecc_encode_nibble(extract8(c, 4, 4));
+    }
+}
+
+/* Common register read handler for both OTP classes. */
+static uint64_t npcm7xx_otp_read(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg)
+{
+    uint32_t value = 0;
+
+    switch (reg) {
+    case NPCM7XX_OTP_FST:
+    case NPCM7XX_OTP_FADDR:
+    case NPCM7XX_OTP_FDATA:
+    case NPCM7XX_OTP_FCFG:
+        value = s->regs[reg];
+        break;
+
+    case NPCM7XX_OTP_FCTL:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: read from write-only FCTL register\n",
+                      DEVICE(s)->canonical_path);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: read from invalid offset 0x%zx\n",
+                      DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
+        break;
+    }
+
+    return value;
+}
+
+/* Read a byte from the OTP array into the data register. */
+static void npcm7xx_otp_read_array(NPCM7xxOTPState *s)
+{
+    uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
+
+    s->regs[NPCM7XX_OTP_FDATA] = s->array[FADDR_BYTEADDR(faddr)];
+    s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
+}
+
+/* Program a byte from the data register into the OTP array. */
+static void npcm7xx_otp_program_array(NPCM7xxOTPState *s)
+{
+    uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR];
+
+    /* Bits can only go 0->1, never 1->0. */
+    s->array[FADDR_BYTEADDR(faddr)] |= (1U << FADDR_BITPOS(faddr));
+    s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY;
+}
+
+/* Compute the next value of the FCFG register. */
+static uint32_t npcm7xx_otp_compute_fcfg(uint32_t cur_value, uint32_t new_value)
+{
+    uint32_t lock_mask;
+    uint32_t value;
+
+    /*
+     * FCFGLK holds sticky bits 16..23, indicating which bits in FPRGLK (8..15)
+     * and FRDLK (0..7) that are read-only.
+     */
+    lock_mask = (cur_value & FCFG_FCFGLK_MASK) >> 8;
+    lock_mask |= lock_mask >> 8;
+    /* FDIS and FCFGLK bits are sticky (write 1 to set; can't clear). */
+    value = cur_value & (FCFG_FDIS | FCFG_FCFGLK_MASK);
+    /* Preserve read-only bits in FPRGLK and FRDLK */
+    value |= cur_value & lock_mask;
+    /* Set all bits that aren't read-only. */
+    value |= new_value & ~lock_mask;
+
+    return value;
+}
+
+/* Common register write handler for both OTP classes. */
+static void npcm7xx_otp_write(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg,
+                              uint32_t value)
+{
+    switch (reg) {
+    case NPCM7XX_OTP_FST:
+        /* RDST is cleared by writing 1 to it. */
+        if (value & FST_RDST) {
+            s->regs[NPCM7XX_OTP_FST] &= ~FST_RDST;
+        }
+        /* Preserve read-only and write-one-to-clear bits */
+        value &= ~FST_RO_MASK;
+        value |= s->regs[NPCM7XX_OTP_FST] & FST_RO_MASK;
+        break;
+
+    case NPCM7XX_OTP_FADDR:
+        break;
+
+    case NPCM7XX_OTP_FDATA:
+        /*
+         * This register is cleared by writing a magic value to it; no other
+         * values can be written.
+         */
+        if (value == FDATA_CLEAR) {
+            value = 0;
+        } else {
+            value = s->regs[NPCM7XX_OTP_FDATA];
+        }
+        break;
+
+    case NPCM7XX_OTP_FCFG:
+        value = npcm7xx_otp_compute_fcfg(s->regs[NPCM7XX_OTP_FCFG], value);
+        break;
+
+    case NPCM7XX_OTP_FCTL:
+        switch (value) {
+        case FCTL_READ_CMD:
+            npcm7xx_otp_read_array(s);
+            break;
+
+        case FCTL_PROG_CMD1:
+            /*
+             * Programming requires writing two separate magic values to this
+             * register; this is the first one. Just store it so it can be
+             * verified later when the second magic value is received.
+             */
+            break;
+
+        case FCTL_PROG_CMD2:
+            /*
+             * Only initiate programming if we received the first half of the
+             * command immediately before this one.
+             */
+            if (s->regs[NPCM7XX_OTP_FCTL] == FCTL_PROG_CMD1) {
+                npcm7xx_otp_program_array(s);
+            }
+            break;
+
+        default:
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: unrecognized FCNTL value 0x%" PRIx32 "\n",
+                          DEVICE(s)->canonical_path, value);
+            break;
+        }
+        if (value != FCTL_PROG_CMD1) {
+            value = 0;
+        }
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: write to invalid offset 0x%zx\n",
+                      DEVICE(s)->canonical_path, reg * sizeof(uint32_t));
+        return;
+    }
+
+    s->regs[reg] = value;
+}
+
+/* Register read handler specific to the fuse array OTP module. */
+static uint64_t npcm7xx_fuse_array_read(void *opaque, hwaddr addr,
+                                        unsigned int size)
+{
+    NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
+    NPCM7xxOTPState *s = opaque;
+    uint32_t value;
+
+    /*
+     * Only the Fuse Strap register needs special handling; all other registers
+     * work the same way for both kinds of OTP modules.
+     */
+    if (reg != NPCM7XX_OTP_FUSTRAP) {
+        value = npcm7xx_otp_read(s, reg);
+    } else {
+        /* FUSTRAP is stored as three copies in the OTP array. */
+        uint32_t fustrap[3];
+
+        memcpy(fustrap, &s->array[0], sizeof(fustrap));
+
+        /* Determine value by a majority vote on each bit. */
+        value = (fustrap[0] & fustrap[1]) | (fustrap[0] & fustrap[2]) |
+                (fustrap[1] & fustrap[2]);
+    }
+
+    return value;
+}
+
+/* Register write handler specific to the fuse array OTP module. */
+static void npcm7xx_fuse_array_write(void *opaque, hwaddr addr, uint64_t v,
+                                     unsigned int size)
+{
+    NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
+    NPCM7xxOTPState *s = opaque;
+
+    /*
+     * The Fuse Strap register is read-only. Other registers are handled by
+     * common code.
+     */
+    if (reg != NPCM7XX_OTP_FUSTRAP) {
+        npcm7xx_otp_write(s, reg, v);
+    }
+}
+
+static const MemoryRegionOps npcm7xx_fuse_array_ops = {
+    .read       = npcm7xx_fuse_array_read,
+    .write      = npcm7xx_fuse_array_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+/* Register read handler specific to the key storage OTP module. */
+static uint64_t npcm7xx_key_storage_read(void *opaque, hwaddr addr,
+                                         unsigned int size)
+{
+    NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
+    NPCM7xxOTPState *s = opaque;
+
+    /*
+     * Only the Fuse Key Index register needs special handling; all other
+     * registers work the same way for both kinds of OTP modules.
+     */
+    if (reg != NPCM7XX_OTP_FKEYIND) {
+        return npcm7xx_otp_read(s, reg);
+    }
+
+    qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
+
+    return s->regs[NPCM7XX_OTP_FKEYIND];
+}
+
+/* Register write handler specific to the key storage OTP module. */
+static void npcm7xx_key_storage_write(void *opaque, hwaddr addr, uint64_t v,
+                                      unsigned int size)
+{
+    NPCM7xxOTPRegister reg = addr / sizeof(uint32_t);
+    NPCM7xxOTPState *s = opaque;
+
+    /*
+     * Only the Fuse Key Index register needs special handling; all other
+     * registers work the same way for both kinds of OTP modules.
+     */
+    if (reg != NPCM7XX_OTP_FKEYIND) {
+        npcm7xx_otp_write(s, reg, v);
+        return;
+    }
+
+    qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__);
+
+    s->regs[NPCM7XX_OTP_FKEYIND] = v;
+}
+
+static const MemoryRegionOps npcm7xx_key_storage_ops = {
+    .read       = npcm7xx_key_storage_read,
+    .write      = npcm7xx_key_storage_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid      = {
+        .min_access_size        = 4,
+        .max_access_size        = 4,
+        .unaligned              = false,
+    },
+};
+
+static void npcm7xx_otp_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxOTPState *s = NPCM7XX_OTP(obj);
+
+    memset(s->regs, 0, sizeof(s->regs));
+
+    s->regs[NPCM7XX_OTP_FST] = 0x00000001;
+    s->regs[NPCM7XX_OTP_FCFG] = 0x20000000;
+}
+
+static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
+{
+    NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
+    NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
+    SysBusDevice *sbd = &s->parent;
+
+    memset(s->array, 0, sizeof(s->array));
+
+    memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs",
+                          NPCM7XX_OTP_REGS_SIZE);
+    sysbus_init_mmio(sbd, &s->mmio);
+}
+
+static const VMStateDescription vmstate_npcm7xx_otp = {
+    .name = "npcm7xx-otp",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxOTPState, NPCM7XX_OTP_NR_REGS),
+        VMSTATE_UINT8_ARRAY(array, NPCM7xxOTPState, NPCM7XX_OTP_ARRAY_BYTES),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void npcm7xx_otp_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    QEMU_BUILD_BUG_ON(NPCM7XX_OTP_REGS_END > NPCM7XX_OTP_NR_REGS);
+
+    dc->realize = npcm7xx_otp_realize;
+    dc->vmsd = &vmstate_npcm7xx_otp;
+    rc->phases.enter = npcm7xx_otp_enter_reset;
+}
+
+static void npcm7xx_key_storage_class_init(ObjectClass *klass, void *data)
+{
+    NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
+
+    oc->mmio_ops = &npcm7xx_key_storage_ops;
+}
+
+static void npcm7xx_fuse_array_class_init(ObjectClass *klass, void *data)
+{
+    NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass);
+
+    oc->mmio_ops = &npcm7xx_fuse_array_ops;
+}
+
+static const TypeInfo npcm7xx_otp_types[] = {
+    {
+        .name = TYPE_NPCM7XX_OTP,
+        .parent = TYPE_SYS_BUS_DEVICE,
+        .instance_size = sizeof(NPCM7xxOTPState),
+        .class_size = sizeof(NPCM7xxOTPClass),
+        .class_init = npcm7xx_otp_class_init,
+        .abstract = true,
+    },
+    {
+        .name = TYPE_NPCM7XX_KEY_STORAGE,
+        .parent = TYPE_NPCM7XX_OTP,
+        .class_init = npcm7xx_key_storage_class_init,
+    },
+    {
+        .name = TYPE_NPCM7XX_FUSE_ARRAY,
+        .parent = TYPE_NPCM7XX_OTP,
+        .class_init = npcm7xx_fuse_array_class_init,
+    },
+};
+DEFINE_TYPES(npcm7xx_otp_types);
diff --git a/hw/nvram/meson.build b/hw/nvram/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/meson.build
+++ b/hw/nvram/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_DS1225Y', if_true: files('ds1225y.c'))
 softmmu_ss.add(when: 'CONFIG_NMC93XX_EEPROM', if_true: files('eeprom93xx.c'))
 softmmu_ss.add(when: 'CONFIG_AT24C', if_true: files('eeprom_at24c.c'))
 softmmu_ss.add(when: 'CONFIG_MAC_NVRAM', if_true: files('mac_nvram.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_otp.c'))
 softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_nvm.c'))
 
 specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_nvram.c'))
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

This just implements the bare minimum to cause the boot block to skip
memory initialization.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-10-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/npcm7xx.h    |  2 +
 include/hw/mem/npcm7xx_mc.h | 36 ++++++++++++++++
 hw/arm/npcm7xx.c            |  6 +++
 hw/mem/npcm7xx_mc.c         | 84 +++++++++++++++++++++++++++++++++++++
 hw/mem/meson.build          |  1 +
 5 files changed, 129 insertions(+)
 create mode 100644 include/hw/mem/npcm7xx_mc.h
 create mode 100644 hw/mem/npcm7xx_mc.c

From: Havard Skinnemoen <hskinnemoen@google.com>

This implements a device model for the NPCM7xx SPI flash controller.

Direct reads and writes, and user-mode transactions have been tested in
various modes. Protection features are not implemented yet.

All the FIU instances are available in the SoC's address space,
regardless of whether or not they're connected to actual flash chips.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-11-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/npcm7xx.h     |   2 +
 include/hw/ssi/npcm7xx_fiu.h |  73 +++++
 hw/arm/npcm7xx.c             |  58 ++++
 hw/ssi/npcm7xx_fiu.c         | 572 +++++++++++++++++++++++++++++++++++
 hw/arm/Kconfig               |   1 +
 hw/ssi/meson.build           |   1 +
 hw/ssi/trace-events          |  11 +
 7 files changed, 718 insertions(+)
 create mode 100644 include/hw/ssi/npcm7xx_fiu.h
 create mode 100644 hw/ssi/npcm7xx_fiu.c

diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/npcm7xx_gcr.h"
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
+#include "hw/ssi/npcm7xx_fiu.h"
 #include "target/arm/cpu.h"
 
 #define NPCM7XX_MAX_NUM_CPUS    (2)
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
     NPCM7xxOTPState     key_storage;
     NPCM7xxOTPState     fuse_array;
     NPCM7xxMCState      mc;
+    NPCM7xxFIUState     fiu[2];
 } NPCM7xxState;
 
 #define TYPE_NPCM7XX    "npcm7xx"
diff --git a/include/hw/ssi/npcm7xx_fiu.h b/include/hw/ssi/npcm7xx_fiu.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/ssi/npcm7xx_fiu.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx Flash Interface Unit (FIU)
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_FIU_H
+#define NPCM7XX_FIU_H
+
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM7XX_FIU_NR_REGS (0x7c / sizeof(uint32_t))
+
+typedef struct NPCM7xxFIUState NPCM7xxFIUState;
+
+/**
+ * struct NPCM7xxFIUFlash - Per-chipselect flash controller state.
+ * @direct_access: Memory region for direct flash access.
+ * @fiu: Pointer to flash controller shared state.
+ */
+typedef struct NPCM7xxFIUFlash {
+    MemoryRegion direct_access;
+    NPCM7xxFIUState *fiu;
+} NPCM7xxFIUFlash;
+
+/**
+ * NPCM7xxFIUState - Device state for one Flash Interface Unit.
+ * @parent: System bus device.
+ * @mmio: Memory region for register access.
+ * @cs_count: Number of flash chips that may be connected to this module.
+ * @active_cs: Currently active chip select, or -1 if no chip is selected.
+ * @cs_lines: GPIO lines that may be wired to flash chips.
+ * @flash: Array of @cs_count per-flash-chip state objects.
+ * @spi: The SPI bus mastered by this controller.
+ * @regs: Register contents.
+ *
+ * Each FIU has a shared bank of registers, and controls up to four chip
+ * selects. Each chip select has a dedicated memory region which may be used to
+ * read and write the flash connected to that chip select as if it were memory.
+ */
+struct NPCM7xxFIUState {
+    SysBusDevice parent;
+
+    MemoryRegion mmio;
+
+    int32_t cs_count;
+    int32_t active_cs;
+    qemu_irq *cs_lines;
+    NPCM7xxFIUFlash *flash;
+
+    SSIBus *spi;
+
+    uint32_t regs[NPCM7XX_FIU_NR_REGS];
+};
+
+#define TYPE_NPCM7XX_FIU "npcm7xx-fiu"
+#define NPCM7XX_FIU(obj) OBJECT_CHECK(NPCM7xxFIUState, (obj), TYPE_NPCM7XX_FIU)
+
+#endif /* NPCM7XX_FIU_H */
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_uart_addr[] = {
     0xf0004000,
 };
 
+/* Direct memory-mapped access to SPI0 CS0-1. */
+static const hwaddr npcm7xx_fiu0_flash_addr[] = {
+    0x80000000, /* CS0 */
+    0x88000000, /* CS1 */
+};
+
+/* Direct memory-mapped access to SPI3 CS0-3. */
+static const hwaddr npcm7xx_fiu3_flash_addr[] = {
+    0xa0000000, /* CS0 */
+    0xa8000000, /* CS1 */
+    0xb0000000, /* CS2 */
+    0xb8000000, /* CS3 */
+};
+
+static const struct {
+    const char *name;
+    hwaddr regs_addr;
+    int cs_count;
+    const hwaddr *flash_addr;
+} npcm7xx_fiu[] = {
+    {
+        .name = "fiu0",
+        .regs_addr = 0xfb000000,
+        .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
+        .flash_addr = npcm7xx_fiu0_flash_addr,
+    }, {
+        .name = "fiu3",
+        .regs_addr = 0xc0000000,
+        .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
+        .flash_addr = npcm7xx_fiu3_flash_addr,
+    },
+};
+
 static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
                                          const struct arm_boot_info *info)
 {
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
         object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
     }
+
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
+    for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
+        object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
+                                TYPE_NPCM7XX_FIU);
+    }
 }
 
 static void npcm7xx_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
                        serial_hd(i), DEVICE_LITTLE_ENDIAN);
     }
 
+    /*
+     * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
+     * specified, but this is a programming error.
+     */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
+    for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
+        int j;
+
+        object_property_set_int(OBJECT(sbd), "cs-count",
+                                npcm7xx_fiu[i].cs_count, &error_abort);
+        sysbus_realize(sbd, &error_abort);
+
+        sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
+        for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
+            sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
+        }
+    }
+
     /* RAM2 (SRAM) */
     memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
                            NPCM7XX_RAM2_SZ, &error_abort);
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM7xx Flash Interface Unit (FIU)
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/ssi/npcm7xx_fiu.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+/* Up to 128 MiB of flash may be accessed directly as memory. */
+#define NPCM7XX_FIU_FLASH_WINDOW_SIZE (128 * MiB)
+
+/* Each module has 4 KiB of register space. Only a fraction of it is used. */
+#define NPCM7XX_FIU_CTRL_REGS_SIZE (4 * KiB)
+
+/* 32-bit FIU register indices. */
+enum NPCM7xxFIURegister {
+    NPCM7XX_FIU_DRD_CFG,
+    NPCM7XX_FIU_DWR_CFG,
+    NPCM7XX_FIU_UMA_CFG,
+    NPCM7XX_FIU_UMA_CTS,
+    NPCM7XX_FIU_UMA_CMD,
+    NPCM7XX_FIU_UMA_ADDR,
+    NPCM7XX_FIU_PRT_CFG,
+    NPCM7XX_FIU_UMA_DW0 = 0x0020 / sizeof(uint32_t),
+    NPCM7XX_FIU_UMA_DW1,
+    NPCM7XX_FIU_UMA_DW2,
+    NPCM7XX_FIU_UMA_DW3,
+    NPCM7XX_FIU_UMA_DR0,
+    NPCM7XX_FIU_UMA_DR1,
+    NPCM7XX_FIU_UMA_DR2,
+    NPCM7XX_FIU_UMA_DR3,
+    NPCM7XX_FIU_PRT_CMD0,
+    NPCM7XX_FIU_PRT_CMD1,
+    NPCM7XX_FIU_PRT_CMD2,
+    NPCM7XX_FIU_PRT_CMD3,
+    NPCM7XX_FIU_PRT_CMD4,
+    NPCM7XX_FIU_PRT_CMD5,
+    NPCM7XX_FIU_PRT_CMD6,
+    NPCM7XX_FIU_PRT_CMD7,
+    NPCM7XX_FIU_PRT_CMD8,
+    NPCM7XX_FIU_PRT_CMD9,
+    NPCM7XX_FIU_CFG = 0x78 / sizeof(uint32_t),
+    NPCM7XX_FIU_REGS_END,
+};
+
+/* FIU_{DRD,DWR,UMA,PTR}_CFG cannot be written when this bit is set. */
+#define NPCM7XX_FIU_CFG_LCK BIT(31)
+
+/* Direct Read configuration register fields. */
+#define FIU_DRD_CFG_ADDSIZ(rv) extract32(rv, 16, 2)
+#define FIU_ADDSIZ_3BYTES 0
+#define FIU_ADDSIZ_4BYTES 1
+#define FIU_DRD_CFG_DBW(rv) extract32(rv, 12, 2)
+#define FIU_DRD_CFG_ACCTYPE(rv) extract32(rv, 8, 2)
+#define FIU_DRD_CFG_RDCMD(rv) extract32(rv, 0, 8)
+
+/* Direct Write configuration register fields. */
+#define FIU_DWR_CFG_ADDSIZ(rv) extract32(rv, 16, 2)
+#define FIU_DWR_CFG_WRCMD(rv) extract32(rv, 0, 8)
+
+/* User-Mode Access register fields. */
+
+/* Command Mode Lock and the bits protected by it. */
+#define FIU_UMA_CFG_CMMLCK BIT(30)
+#define FIU_UMA_CFG_CMMLCK_MASK 0x00000403
+
+#define FIU_UMA_CFG_RDATSIZ(rv) extract32(rv, 24, 5)
+#define FIU_UMA_CFG_DBSIZ(rv) extract32(rv, 21, 3)
+#define FIU_UMA_CFG_WDATSIZ(rv) extract32(rv, 16, 5)
+#define FIU_UMA_CFG_ADDSIZ(rv) extract32(rv, 11, 3)
+#define FIU_UMA_CFG_CMDSIZ(rv) extract32(rv, 10, 1)
+#define FIU_UMA_CFG_DBPCK(rv) extract32(rv, 6, 2)
+
+#define FIU_UMA_CTS_RDYIE BIT(25)
+#define FIU_UMA_CTS_RDYST BIT(24)
+#define FIU_UMA_CTS_SW_CS BIT(16)
+#define FIU_UMA_CTS_DEV_NUM(rv) extract32(rv, 8, 2)
+#define FIU_UMA_CTS_EXEC_DONE BIT(0)
+
+/*
+ * Returns the index of flash in the fiu->flash array. This corresponds to the
+ * chip select ID of the flash.
+ */
+static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
+{
+    int index = flash - fiu->flash;
+
+    g_assert(index >= 0 && index < fiu->cs_count);
+
+    return index;
+}
+
+/* Assert the chip select specified in the UMA Control/Status Register. */
+static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id)
+{
+    trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id);
+
+    if (cs_id < s->cs_count) {
+        qemu_irq_lower(s->cs_lines[cs_id]);
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: UMA to CS%d; this module has only %d chip selects",
+                      DEVICE(s)->canonical_path, cs_id, s->cs_count);
+        cs_id = -1;
+    }
+
+    s->active_cs = cs_id;
+}
+
+/* Deassert the currently active chip select. */
+static void npcm7xx_fiu_deselect(NPCM7xxFIUState *s)
+{
+    if (s->active_cs < 0) {
+        return;
+    }
+
+    trace_npcm7xx_fiu_deselect(DEVICE(s)->canonical_path, s->active_cs);
+
+    qemu_irq_raise(s->cs_lines[s->active_cs]);
+    s->active_cs = -1;
+}
+
+/* Direct flash memory read handler. */
+static uint64_t npcm7xx_fiu_flash_read(void *opaque, hwaddr addr,
+                                       unsigned int size)
+{
+    NPCM7xxFIUFlash *f = opaque;
+    NPCM7xxFIUState *fiu = f->fiu;
+    uint64_t value = 0;
+    uint32_t drd_cfg;
+    int dummy_cycles;
+    int i;
+
+    if (fiu->active_cs != -1) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: direct flash read with CS%d already active",
+                      DEVICE(fiu)->canonical_path, fiu->active_cs);
+    }
+
+    npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f));
+
+    drd_cfg = fiu->regs[NPCM7XX_FIU_DRD_CFG];
+    ssi_transfer(fiu->spi, FIU_DRD_CFG_RDCMD(drd_cfg));
+
+    switch (FIU_DRD_CFG_ADDSIZ(drd_cfg)) {
+    case FIU_ADDSIZ_4BYTES:
+        ssi_transfer(fiu->spi, extract32(addr, 24, 8));
+        /* fall through */
+    case FIU_ADDSIZ_3BYTES:
+        ssi_transfer(fiu->spi, extract32(addr, 16, 8));
+        ssi_transfer(fiu->spi, extract32(addr, 8, 8));
+        ssi_transfer(fiu->spi, extract32(addr, 0, 8));
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
+                      DEVICE(fiu)->canonical_path, FIU_DRD_CFG_ADDSIZ(drd_cfg));
+        break;
+    }
+
+    /* Flash chip model expects one transfer per dummy bit, not byte */
+    dummy_cycles =
+        (FIU_DRD_CFG_DBW(drd_cfg) * 8) >> FIU_DRD_CFG_ACCTYPE(drd_cfg);
+    for (i = 0; i < dummy_cycles; i++) {
+        ssi_transfer(fiu->spi, 0);
+    }
+
+    for (i = 0; i < size; i++) {
+        value = deposit64(value, 8 * i, 8, ssi_transfer(fiu->spi, 0));
+    }
+
+    trace_npcm7xx_fiu_flash_read(DEVICE(fiu)->canonical_path, fiu->active_cs,
+                                 addr, size, value);
+
+    npcm7xx_fiu_deselect(fiu);
+
+    return value;
+}
+
+/* Direct flash memory write handler. */
+static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
+                                    unsigned int size)
+{
+    NPCM7xxFIUFlash *f = opaque;
+    NPCM7xxFIUState *fiu = f->fiu;
+    uint32_t dwr_cfg;
+    int cs_id;
+    int i;
+
+    if (fiu->active_cs != -1) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: direct flash write with CS%d already active",
+                      DEVICE(fiu)->canonical_path, fiu->active_cs);
+    }
+
+    cs_id = npcm7xx_fiu_cs_index(fiu, f);
+    trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
+                                  size, v);
+    npcm7xx_fiu_select(fiu, cs_id);
+
+    dwr_cfg = fiu->regs[NPCM7XX_FIU_DWR_CFG];
+    ssi_transfer(fiu->spi, FIU_DWR_CFG_WRCMD(dwr_cfg));
+
+    switch (FIU_DWR_CFG_ADDSIZ(dwr_cfg)) {
+    case FIU_ADDSIZ_4BYTES:
+        ssi_transfer(fiu->spi, extract32(addr, 24, 8));
+        /* fall through */
+    case FIU_ADDSIZ_3BYTES:
+        ssi_transfer(fiu->spi, extract32(addr, 16, 8));
+        ssi_transfer(fiu->spi, extract32(addr, 8, 8));
+        ssi_transfer(fiu->spi, extract32(addr, 0, 8));
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad address size %d\n",
+                      DEVICE(fiu)->canonical_path, FIU_DWR_CFG_ADDSIZ(dwr_cfg));
+        break;
+    }
+
+    for (i = 0; i < size; i++) {
+        ssi_transfer(fiu->spi, extract64(v, i * 8, 8));
+    }
+
+    npcm7xx_fiu_deselect(fiu);
+}
+
+static const MemoryRegionOps npcm7xx_fiu_flash_ops = {
+    .read = npcm7xx_fiu_flash_read,
+    .write = npcm7xx_fiu_flash_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 8,
+        .unaligned = true,
+    },
+};
+
+/* Control register read handler. */
+static uint64_t npcm7xx_fiu_ctrl_read(void *opaque, hwaddr addr,
+                                      unsigned int size)
+{
+    hwaddr reg = addr / sizeof(uint32_t);
+    NPCM7xxFIUState *s = opaque;
+    uint32_t value;
+
+    if (reg < NPCM7XX_FIU_NR_REGS) {
+        value = s->regs[reg];
+    } else {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: read from invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        value = 0;
+    }
+
+    trace_npcm7xx_fiu_ctrl_read(DEVICE(s)->canonical_path, addr, value);
+
+    return value;
+}
+
+/* Send the specified number of address bytes from the UMA address register. */
+static void send_address(SSIBus *spi, unsigned int addsiz, uint32_t addr)
+{
+    switch (addsiz) {
+    case 4:
+        ssi_transfer(spi, extract32(addr, 24, 8));
+        /* fall through */
+    case 3:
+        ssi_transfer(spi, extract32(addr, 16, 8));
+        /* fall through */
+    case 2:
+        ssi_transfer(spi, extract32(addr, 8, 8));
+        /* fall through */
+    case 1:
+        ssi_transfer(spi, extract32(addr, 0, 8));
+        /* fall through */
+    case 0:
+        break;
+    }
+}
+
+/* Send the number of dummy bits specified in the UMA config register. */
+static void send_dummy_bits(SSIBus *spi, uint32_t uma_cfg, uint32_t uma_cmd)
+{
+    unsigned int bits_per_clock = 1U << FIU_UMA_CFG_DBPCK(uma_cfg);
+    unsigned int i;
+
+    for (i = 0; i < FIU_UMA_CFG_DBSIZ(uma_cfg); i++) {
+        /* Use bytes 0 and 1 first, then keep repeating byte 2 */
+        unsigned int field = (i < 2) ? ((i + 1) * 8) : 24;
+        unsigned int j;
+
+        for (j = 0; j < 8; j += bits_per_clock) {
+            ssi_transfer(spi, extract32(uma_cmd, field + j, bits_per_clock));
+        }
+    }
+}
+
+/* Perform a User-Mode Access transaction. */
+static void npcm7xx_fiu_uma_transaction(NPCM7xxFIUState *s)
+{
+    uint32_t uma_cts = s->regs[NPCM7XX_FIU_UMA_CTS];
+    uint32_t uma_cfg;
+    unsigned int i;
+
+    /* SW_CS means the CS is already forced low, so don't touch it. */
+    if (uma_cts & FIU_UMA_CTS_SW_CS) {
+        int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]);
+        npcm7xx_fiu_select(s, cs_id);
+    }
+
+    /* Send command, if present. */
+    uma_cfg = s->regs[NPCM7XX_FIU_UMA_CFG];
+    if (FIU_UMA_CFG_CMDSIZ(uma_cfg) > 0) {
+        ssi_transfer(s->spi, extract32(s->regs[NPCM7XX_FIU_UMA_CMD], 0, 8));
+    }
+
+    /* Send address, if present. */
+    send_address(s->spi, FIU_UMA_CFG_ADDSIZ(uma_cfg),
+                 s->regs[NPCM7XX_FIU_UMA_ADDR]);
+
+    /* Write data, if present. */
+    for (i = 0; i < FIU_UMA_CFG_WDATSIZ(uma_cfg); i++) {
+        unsigned int reg =
+            (i < 16) ? (NPCM7XX_FIU_UMA_DW0 + i / 4) : NPCM7XX_FIU_UMA_DW3;
+        unsigned int field = (i % 4) * 8;
+
+        ssi_transfer(s->spi, extract32(s->regs[reg], field, 8));
+    }
+
+    /* Send dummy bits, if present. */
+    send_dummy_bits(s->spi, uma_cfg, s->regs[NPCM7XX_FIU_UMA_CMD]);
+
+    /* Read data, if present. */
+    for (i = 0; i < FIU_UMA_CFG_RDATSIZ(uma_cfg); i++) {
+        unsigned int reg = NPCM7XX_FIU_UMA_DR0 + i / 4;
+        unsigned int field = (i % 4) * 8;
+        uint8_t c;
+
+        c = ssi_transfer(s->spi, 0);
+        if (reg <= NPCM7XX_FIU_UMA_DR3) {
+            s->regs[reg] = deposit32(s->regs[reg], field, 8, c);
+        }
+    }
+
+    /* Again, don't touch CS if the user is forcing it low. */
+    if (uma_cts & FIU_UMA_CTS_SW_CS) {
+        npcm7xx_fiu_deselect(s);
+    }
+
+    /* RDYST means a command has completed since it was cleared. */
+    s->regs[NPCM7XX_FIU_UMA_CTS] |= FIU_UMA_CTS_RDYST;
+    /* EXEC_DONE means Execute Command / Not Done, so clear it here. */
+    s->regs[NPCM7XX_FIU_UMA_CTS] &= ~FIU_UMA_CTS_EXEC_DONE;
+}
+
+/* Control register write handler. */
+static void npcm7xx_fiu_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
+                                   unsigned int size)
+{
+    hwaddr reg = addr / sizeof(uint32_t);
+    NPCM7xxFIUState *s = opaque;
+    uint32_t value = v;
+
+    trace_npcm7xx_fiu_ctrl_write(DEVICE(s)->canonical_path, addr, value);
+
+    switch (reg) {
+    case NPCM7XX_FIU_UMA_CFG:
+        if (s->regs[reg] & FIU_UMA_CFG_CMMLCK) {
+            value &= ~FIU_UMA_CFG_CMMLCK_MASK;
+            value |= (s->regs[reg] & FIU_UMA_CFG_CMMLCK_MASK);
+        }
+        /* fall through */
+    case NPCM7XX_FIU_DRD_CFG:
+    case NPCM7XX_FIU_DWR_CFG:
+        if (s->regs[reg] & NPCM7XX_FIU_CFG_LCK) {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: write to locked register @ 0x%" PRIx64 "\n",
+                          DEVICE(s)->canonical_path, addr);
+            return;
+        }
+        s->regs[reg] = value;
+        break;
+
+    case NPCM7XX_FIU_UMA_CTS:
+        if (value & FIU_UMA_CTS_RDYST) {
+            value &= ~FIU_UMA_CTS_RDYST;
+        } else {
+            value |= s->regs[reg] & FIU_UMA_CTS_RDYST;
+        }
+        if ((s->regs[reg] ^ value) & FIU_UMA_CTS_SW_CS) {
+            if (value & FIU_UMA_CTS_SW_CS) {
+                /*
+                 * Don't drop CS if there's a transfer in progress, or we're
+                 * about to start one.
+                 */
+                if (!((value | s->regs[reg]) & FIU_UMA_CTS_EXEC_DONE)) {
+                    npcm7xx_fiu_deselect(s);
+                }
+            } else {
+                int cs_id = FIU_UMA_CTS_DEV_NUM(s->regs[NPCM7XX_FIU_UMA_CTS]);
+                npcm7xx_fiu_select(s, cs_id);
+            }
+        }
+        s->regs[reg] = value | (s->regs[reg] & FIU_UMA_CTS_EXEC_DONE);
+        if (value & FIU_UMA_CTS_EXEC_DONE) {
+            npcm7xx_fiu_uma_transaction(s);
+        }
+        break;
+
+    case NPCM7XX_FIU_UMA_DR0 ... NPCM7XX_FIU_UMA_DR3:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to read-only register @ 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return;
+
+    case NPCM7XX_FIU_PRT_CFG:
+    case NPCM7XX_FIU_PRT_CMD0 ... NPCM7XX_FIU_PRT_CMD9:
+        qemu_log_mask(LOG_UNIMP, "%s: PRT is not implemented\n", __func__);
+        break;
+
+    case NPCM7XX_FIU_UMA_CMD:
+    case NPCM7XX_FIU_UMA_ADDR:
+    case NPCM7XX_FIU_UMA_DW0 ... NPCM7XX_FIU_UMA_DW3:
+    case NPCM7XX_FIU_CFG:
+        s->regs[reg] = value;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return;
+    }
+}
+
+static const MemoryRegionOps npcm7xx_fiu_ctrl_ops = {
+    .read = npcm7xx_fiu_ctrl_read,
+    .write = npcm7xx_fiu_ctrl_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+        .unaligned = false,
+    },
+};
+
+static void npcm7xx_fiu_enter_reset(Object *obj, ResetType type)
+{
+    NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
+
+    trace_npcm7xx_fiu_enter_reset(DEVICE(obj)->canonical_path, type);
+
+    memset(s->regs, 0, sizeof(s->regs));
+
+    s->regs[NPCM7XX_FIU_DRD_CFG] = 0x0300100b;
+    s->regs[NPCM7XX_FIU_DWR_CFG] = 0x03000002;
+    s->regs[NPCM7XX_FIU_UMA_CFG] = 0x00000400;
+    s->regs[NPCM7XX_FIU_UMA_CTS] = 0x00010000;
+    s->regs[NPCM7XX_FIU_UMA_CMD] = 0x0000000b;
+    s->regs[NPCM7XX_FIU_PRT_CFG] = 0x00000400;
+    s->regs[NPCM7XX_FIU_CFG] = 0x0000000b;
+}
+
+static void npcm7xx_fiu_hold_reset(Object *obj)
+{
+    NPCM7xxFIUState *s = NPCM7XX_FIU(obj);
+    int i;
+
+    trace_npcm7xx_fiu_hold_reset(DEVICE(obj)->canonical_path);
+
+    for (i = 0; i < s->cs_count; i++) {
+        qemu_irq_raise(s->cs_lines[i]);
+    }
+}
+
+static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
+{
+    NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
+    SysBusDevice *sbd = &s->parent;
+    int i;
+
+    if (s->cs_count <= 0) {
+        error_setg(errp, "%s: %d chip selects specified, need at least one",
+                   dev->canonical_path, s->cs_count);
+        return;
+    }
+
+    s->spi = ssi_create_bus(dev, "spi");
+    s->cs_lines = g_new0(qemu_irq, s->cs_count);
+    qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", s->cs_count);
+    s->flash = g_new0(NPCM7xxFIUFlash, s->cs_count);
+
+    /*
+     * Register the control registers region first. It may be followed by one
+     * or more direct flash access regions.
+     */
+    memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_fiu_ctrl_ops, s, "ctrl",
+                          NPCM7XX_FIU_CTRL_REGS_SIZE);
+    sysbus_init_mmio(sbd, &s->mmio);
+
+    for (i = 0; i < s->cs_count; i++) {
+        NPCM7xxFIUFlash *flash = &s->flash[i];
+        flash->fiu = s;
+        memory_region_init_io(&flash->direct_access, OBJECT(s),
+                              &npcm7xx_fiu_flash_ops, &s->flash[i], "flash",
+                              NPCM7XX_FIU_FLASH_WINDOW_SIZE);
+        sysbus_init_mmio(sbd, &flash->direct_access);
+    }
+}
+
+static const VMStateDescription vmstate_npcm7xx_fiu = {
+    .name = "npcm7xx-fiu",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_INT32(active_cs, NPCM7xxFIUState),
+        VMSTATE_UINT32_ARRAY(regs, NPCM7xxFIUState, NPCM7XX_FIU_NR_REGS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static Property npcm7xx_fiu_properties[] = {
+    DEFINE_PROP_INT32("cs-count", NPCM7xxFIUState, cs_count, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void npcm7xx_fiu_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    QEMU_BUILD_BUG_ON(NPCM7XX_FIU_REGS_END > NPCM7XX_FIU_NR_REGS);
+
+    dc->desc = "NPCM7xx Flash Interface Unit";
+    dc->realize = npcm7xx_fiu_realize;
+    dc->vmsd = &vmstate_npcm7xx_fiu;
+    rc->phases.enter = npcm7xx_fiu_enter_reset;
+    rc->phases.hold = npcm7xx_fiu_hold_reset;
+    device_class_set_props(dc, npcm7xx_fiu_properties);
+}
+
+static const TypeInfo npcm7xx_fiu_types[] = {
+    {
+        .name = TYPE_NPCM7XX_FIU,
+        .parent = TYPE_SYS_BUS_DEVICE,
+        .instance_size = sizeof(NPCM7xxFIUState),
+        .class_init = npcm7xx_fiu_class_init,
+    },
+};
+DEFINE_TYPES(npcm7xx_fiu_types);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config NPCM7XX
     select ARM_GIC
     select PL310  # cache controller
     select SERIAL
+    select SSI
     select UNIMP
 
 config FSL_IMX25
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/meson.build
+++ b/hw/ssi/meson.build
@@ -XXX,XX +XXX,XX @@
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
 softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
 softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
 softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_SPI', if_true: files('stm32f2xx_spi.c'))
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -XXX,XX +XXX,XX @@ aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
 aspeed_smc_dma_rw(const char *dir, uint32_t flash_addr, uint32_t dram_addr, uint32_t size) "%s flash:@0x%08x dram:@0x%08x size:0x%08x"
 aspeed_smc_write(uint64_t addr,  uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
 aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
+
+# npcm7xx_fiu.c
+
+npcm7xx_fiu_enter_reset(const char *id, int reset_type) "%s reset type: %d"
+npcm7xx_fiu_hold_reset(const char *id) "%s"
+npcm7xx_fiu_select(const char *id, int cs) "%s select CS%d"
+npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d"
+npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
+npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
+npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

This allows these NPCM7xx-based boards to boot from a flash image, e.g.
one built with OpenBMC. For example like this:

IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc
qemu-system-arm -machine quanta-gsj -nographic \
	-drive file=${IMAGE},if=mtd,bus=0,unit=0,format=raw,snapshot=on

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200911052101.2602693-12-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx_boards.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/npcm7xx.h"
 #include "hw/core/cpu.h"
 #include "hw/loader.h"
+#include "hw/qdev-properties.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
 #include "qemu/units.h"
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_load_bootrom(MachineState *machine, NPCM7xxState *soc)
     }
 }
 
+static void npcm7xx_connect_flash(NPCM7xxFIUState *fiu, int cs_no,
+                                  const char *flash_type, DriveInfo *dinfo)
+{
+    DeviceState *flash;
+    qemu_irq flash_cs;
+
+    flash = qdev_new(flash_type);
+    if (dinfo) {
+        qdev_prop_set_drive(flash, "drive", blk_by_legacy_dinfo(dinfo));
+    }
+    qdev_realize_and_unref(flash, BUS(fiu->spi), &error_fatal);
+
+    flash_cs = qdev_get_gpio_in_named(flash, SSI_GPIO_CS, 0);
+    qdev_connect_gpio_out_named(DEVICE(fiu), "cs", cs_no, flash_cs);
+}
+
 static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram)
 {
     memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram);
@@ -XXX,XX +XXX,XX @@ static void npcm750_evb_init(MachineState *machine)
     qdev_realize(DEVICE(soc), NULL, &error_fatal);
 
     npcm7xx_load_bootrom(machine, soc);
+    npcm7xx_connect_flash(&soc->fiu[0], 0, "w25q256", drive_get(IF_MTD, 0, 0));
     npcm7xx_load_kernel(machine, soc);
 }
 
@@ -XXX,XX +XXX,XX @@ static void quanta_gsj_init(MachineState *machine)
     qdev_realize(DEVICE(soc), NULL, &error_fatal);
 
     npcm7xx_load_bootrom(machine, soc);
+    npcm7xx_connect_flash(&soc->fiu[0], 0, "mx25l25635e",
+                          drive_get(IF_MTD, 0, 0));
     npcm7xx_load_kernel(machine, soc);
 }
 
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

When booting directly into a kernel, bypassing the boot loader, the CPU and
UART clocks are not set up correctly. This makes the system appear very
slow, and causes the initrd boot test to fail when optimization is off.

The UART clock must run at 24 MHz. The default 25 MHz reference clock
cannot achieve this, so switch to PLL2/2 @ 480 MHz, which works
perfectly with the default /20 divider.

The CPU clock should run at 800 MHz, so switch it to PLL1/2. PLL1 runs
at 800 MHz by default, so we need to double the feedback divider as well
to make it run at 1600 MHz (so PLL1/2 runs at 800 MHz).

We don't bother checking for PLL lock because we know our emulated PLLs
lock instantly.

diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_SMP_LOADER_START        (0xffff0000)  /* Boot ROM */
 #define NPCM7XX_SMP_BOOTREG_ADDR        (0xf080013c)  /* GCR.SCRPAD */
 #define NPCM7XX_GIC_CPU_IF_ADDR         (0xf03fe100)  /* GIC within A9 */
+#define NPCM7XX_BOARD_SETUP_ADDR        (0xffff1000)  /* Boot ROM */
 
 typedef struct NPCM7xxMachine {
     MachineState        parent;
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@
 #define NPCM7XX_ROM_BA          (0xffff0000)
 #define NPCM7XX_ROM_SZ          (64 * KiB)
 
+/* Clock configuration values to be fixed up when bypassing bootloader */
+
+/* Run PLL1 at 1600 MHz */
+#define NPCM7XX_PLLCON1_FIXUP_VAL   (0x00402101)
+/* Run the CPU from PLL1 and UART from PLL2 */
+#define NPCM7XX_CLKSEL_FIXUP_VAL    (0x004aaba9)
+
 /*
  * Interrupt lines going into the GIC. This does not include internal Cortex-A9
  * interrupts.
@@ -XXX,XX +XXX,XX @@ static const struct {
     },
 };
 
+static void npcm7xx_write_board_setup(ARMCPU *cpu,
+                                      const struct arm_boot_info *info)
+{
+    uint32_t board_setup[] = {
+        0xe59f0010,     /* ldr r0, clk_base_addr */
+        0xe59f1010,     /* ldr r1, pllcon1_value */
+        0xe5801010,     /* str r1, [r0, #16] */
+        0xe59f100c,     /* ldr r1, clksel_value */
+        0xe5801004,     /* str r1, [r0, #4] */
+        0xe12fff1e,     /* bx lr */
+        NPCM7XX_CLK_BA,
+        NPCM7XX_PLLCON1_FIXUP_VAL,
+        NPCM7XX_CLKSEL_FIXUP_VAL,
+    };
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(board_setup); i++) {
+        board_setup[i] = tswap32(board_setup[i]);
+    }
+    rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup),
+                       info->board_setup_addr);
+}
+
 static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
                                          const struct arm_boot_info *info)
 {
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info npcm7xx_binfo = {
     .gic_cpu_if_addr        = NPCM7XX_GIC_CPU_IF_ADDR,
     .write_secondary_boot   = npcm7xx_write_secondary_boot,
     .board_id               = -1,
+    .board_setup_addr       = NPCM7XX_BOARD_SETUP_ADDR,
+    .write_board_setup      = npcm7xx_write_board_setup,
 };
 
 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200911052101.2602693-14-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst | 92 +++++++++++++++++++++++++++++++++++++
 docs/system/target-arm.rst  |  1 +
 2 files changed, 93 insertions(+)
 create mode 100644 docs/system/arm/nuvoton.rst

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@
+Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
+=====================================================
+
+The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
+designed to be used as Baseboard Management Controllers (BMCs) in various
+servers. They all feature one or two ARM Cortex A9 CPU cores, as well as an
+assortment of peripherals targeted for either Enterprise or Data Center /
+Hyperscale applications. The former is a superset of the latter, so NPCM750 has
+all the peripherals of NPCM730 and more.
+
+.. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
+
+The NPCM750 SoC has two Cortex A9 cores and is targeted for the Enterprise
+segment. The following machines are based on this chip :
+
+- ``npcm750-evb``       Nuvoton NPCM750 Evaluation board
+
+The NPCM730 SoC has two Cortex A9 cores and is targeted for Data Center and
+Hyperscale applications. The following machines are based on this chip :
+
+- ``quanta-gsj``        Quanta GSJ server BMC
+
+There are also two more SoCs, NPCM710 and NPCM705, which are single-core
+variants of NPCM750 and NPCM730, respectively. These are currently not
+supported by QEMU.
+
+Supported devices
+-----------------
+
+ * SMP (Dual Core Cortex-A9)
+ * Cortex-A9MPCore built-in peripherals: SCU, GIC, Global Timer, Private Timer
+   and Watchdog.
+ * SRAM, ROM and DRAM mappings
+ * System Global Control Registers (GCR)
+ * Clock and reset controller (CLK)
+ * Timer controller (TIM)
+ * Serial ports (16550-based)
+ * DDR4 memory controller (dummy interface indicating memory training is done)
+ * OTP controllers (no protection features)
+ * Flash Interface Unit (FIU; no protection features)
+
+Missing devices
+---------------
+
+ * GPIO controller
+ * LPC/eSPI host-to-BMC interface, including
+
+   * Keyboard and mouse controller interface (KBCI)
+   * Keyboard Controller Style (KCS) channels
+   * BIOS POST code FIFO
+   * System Wake-up Control (SWC)
+   * Shared memory (SHM)
+   * eSPI slave interface
+
+ * Ethernet controllers (GMAC and EMC)
+ * USB host (USBH)
+ * USB device (USBD)
+ * SMBus controller (SMBF)
+ * Peripheral SPI controller (PSPI)
+ * Analog to Digital Converter (ADC)
+ * SD/MMC host
+ * Random Number Generator (RNG)
+ * PECI interface
+ * Pulse Width Modulation (PWM)
+ * Tachometer
+ * PCI and PCIe root complex and bridges
+ * VDM and MCTP support
+ * Serial I/O expansion
+ * LPC/eSPI host
+ * Coprocessor
+ * Graphics
+ * Video capture
+ * Encoding compression engine
+ * Security features
+
+Boot options
+------------
+
+The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
+a kernel using the ``-kernel`` option. OpenBMC images for `quanta-gsj` and
+possibly others can be downloaded from the OpenPOWER jenkins :
+
+   https://openpower.xyz/
+
+The firmware image should be attached as an MTD drive. Example :
+
+.. code-block:: bash
+
+  $ qemu-system-arm -machine quanta-gsj -nographic \
+      -drive file=image-bmc,if=mtd,bus=0,unit=0,format=raw
+
+The default root password for test images is usually ``0penBmc``.
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/musicpal
    arm/gumstix
    arm/nseries
+   arm/nuvoton
    arm/orangepi
    arm/palm
    arm/xscale
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

This adds two acceptance tests for the quanta-gsj machine.

One test downloads a lightly patched openbmc flash image from github and
verifies that it boots all the way to the login prompt.

The other test downloads a kernel, initrd and dtb built from the same
openbmc source and verifies that the kernel detects all CPUs and boots
to the point where it can't find the root filesystem (because we have no
flash image in this case).

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest):
                                                 'sda')
         # cubieboard's reboot is not functioning; omit reboot test.
 
+    def test_arm_quanta_gsj(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:quanta-gsj
+        """
+        # 25 MiB compressed, 32 MiB uncompressed.
+        image_url = (
+                'https://github.com/hskinnemoen/openbmc/releases/download/'
+                '20200711-gsj-qemu-0/obmc-phosphor-image-gsj.static.mtd.gz')
+        image_hash = '14895e634923345cb5c8776037ff7876df96f6b1'
+        image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash)
+        image_name = 'obmc.mtd'
+        image_path = os.path.join(self.workdir, image_name)
+        archive.gzip_uncompress(image_path_gz, image_path)
+
+        self.vm.set_console()
+        drive_args = 'file=' + image_path + ',if=mtd,bus=0,unit=0'
+        self.vm.add_args('-drive', drive_args)
+        self.vm.launch()
+
+        # Disable drivers and services that stall for a long time during boot,
+        # to avoid running past the 90-second timeout. These may be removed
+        # as the corresponding device support is added.
+        kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + (
+                'console=${console} '
+                'mem=${mem} '
+                'initcall_blacklist=npcm_i2c_bus_driver_init '
+                'systemd.mask=systemd-random-seed.service '
+                'systemd.mask=dropbearkey.service '
+        )
+
+        self.wait_for_console_pattern('> BootBlock by Nuvoton')
+        self.wait_for_console_pattern('>Device: Poleg BMC NPCM730')
+        self.wait_for_console_pattern('>Skip DDR init.')
+        self.wait_for_console_pattern('U-Boot ')
+        interrupt_interactive_console_until_pattern(
+                self, 'Hit any key to stop autoboot:', 'U-Boot>')
+        exec_command_and_wait_for_pattern(
+                self, "setenv bootargs ${bootargs} " + kernel_command_line,
+                'U-Boot>')
+        exec_command_and_wait_for_pattern(
+                self, 'run romboot', 'Booting Kernel from flash')
+        self.wait_for_console_pattern('Booting Linux on physical CPU 0x0')
+        self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0')
+        self.wait_for_console_pattern('OpenBMC Project Reference Distro')
+        self.wait_for_console_pattern('gsj login:')
+
+    def test_arm_quanta_gsj_initrd(self):
+        """
+        :avocado: tags=arch:arm
+        :avocado: tags=machine:quanta-gsj
+        """
+        initrd_url = (
+                'https://github.com/hskinnemoen/openbmc/releases/download/'
+                '20200711-gsj-qemu-0/obmc-phosphor-initramfs-gsj.cpio.xz')
+        initrd_hash = '98fefe5d7e56727b1eb17d5c00311b1b5c945300'
+        initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+        kernel_url = (
+                'https://github.com/hskinnemoen/openbmc/releases/download/'
+                '20200711-gsj-qemu-0/uImage-gsj.bin')
+        kernel_hash = 'fa67b2f141d56d39b3c54305c0e8a899c99eb2c7'
+        kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+        dtb_url = (
+                'https://github.com/hskinnemoen/openbmc/releases/download/'
+                '20200711-gsj-qemu-0/nuvoton-npcm730-gsj.dtb')
+        dtb_hash = '18315f7006d7b688d8312d5c727eecd819aa36a4'
+        dtb_path = self.fetch_asset(dtb_url, asset_hash=dtb_hash)
+
+        self.vm.set_console()
+        kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
+                               'console=ttyS0,115200n8 '
+                               'earlycon=uart8250,mmio32,0xf0001000')
+        self.vm.add_args('-kernel', kernel_path,
+                         '-initrd', initrd_path,
+                         '-dtb', dtb_path,
+                         '-append', kernel_command_line)
+        self.vm.launch()
+
+        self.wait_for_console_pattern('Booting Linux on physical CPU 0x0')
+        self.wait_for_console_pattern('CPU1: thread -1, cpu 1, socket 0')
+        self.wait_for_console_pattern(
+                'Give root password for system maintenance')
+
     def test_arm_orangepi(self):
         """
         :avocado: tags=arch:arm
-- 
2.20.1

From: Vikram Garhwal <fnu.vikram@xilinx.com>

The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.

Example for using single CAN:
    -object can-bus,id=canbus0 \
    -machine xlnx-zcu102.canbus0=canbus0 \
    -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0

Example for connecting both CAN to same virtual CAN on host machine:
    -object can-bus,id=canbus0 -object can-bus,id=canbus1 \
    -machine xlnx-zcu102.canbus0=canbus0 \
    -machine xlnx-zcu102.canbus1=canbus1 \
    -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 \
    -object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1

To create virtual CAN on the host machine, please check the QEMU CAN docs:
https://github.com/qemu/qemu/blob/master/docs/can.txt

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1597278668-339715-2-git-send-email-fnu.vikram@xilinx.com
[PMM: updated to meson build system]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/net/xlnx-zynqmp-can.h |   78 ++
 hw/net/can/xlnx-zynqmp-can.c     | 1165 ++++++++++++++++++++++++++++++
 hw/net/can/meson.build           |    1 +
 3 files changed, 1244 insertions(+)
 create mode 100644 include/hw/net/xlnx-zynqmp-can.h
 create mode 100644 hw/net/can/xlnx-zynqmp-can.c

diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-can.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/net/xlnx-zynqmp-can.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of the Xilinx ZynqMP CAN controller.
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
+ * Pavel Pisa.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef XLNX_ZYNQMP_CAN_H
+#define XLNX_ZYNQMP_CAN_H
+
+#include "hw/register.h"
+#include "net/can_emu.h"
+#include "net/can_host.h"
+#include "qemu/fifo32.h"
+#include "hw/ptimer.h"
+#include "hw/qdev-clock.h"
+
+#define TYPE_XLNX_ZYNQMP_CAN "xlnx.zynqmp-can"
+
+#define XLNX_ZYNQMP_CAN(obj) \
+     OBJECT_CHECK(XlnxZynqMPCANState, (obj), TYPE_XLNX_ZYNQMP_CAN)
+
+#define MAX_CAN_CTRLS      2
+#define XLNX_ZYNQMP_CAN_R_MAX     (0x84 / 4)
+#define MAILBOX_CAPACITY   64
+#define CAN_TIMER_MAX  0XFFFFUL
+#define CAN_DEFAULT_CLOCK (24 * 1000 * 1000)
+
+/* Each CAN_FRAME will have 4 * 32bit size. */
+#define CAN_FRAME_SIZE     4
+#define RXFIFO_SIZE        (MAILBOX_CAPACITY * CAN_FRAME_SIZE)
+
+typedef struct XlnxZynqMPCANState {
+    SysBusDevice        parent_obj;
+    MemoryRegion        iomem;
+
+    qemu_irq            irq;
+
+    CanBusClientState   bus_client;
+    CanBusState         *canbus;
+
+    struct {
+        uint32_t        ext_clk_freq;
+    } cfg;
+
+    RegisterInfo        reg_info[XLNX_ZYNQMP_CAN_R_MAX];
+    uint32_t            regs[XLNX_ZYNQMP_CAN_R_MAX];
+
+    Fifo32              rx_fifo;
+    Fifo32              tx_fifo;
+    Fifo32              txhpb_fifo;
+
+    ptimer_state        *can_timer;
+} XlnxZynqMPCANState;
+
+#endif
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/net/can/xlnx-zynqmp-can.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of the Xilinx ZynqMP CAN controller.
+ * This implementation is based on the following datasheet:
+ * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
+ * Pavel Pisa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "hw/irq.h"
+#include "qapi/error.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qemu/cutils.h"
+#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "net/can_emu.h"
+#include "net/can_host.h"
+#include "qemu/event_notifier.h"
+#include "qom/object_interfaces.h"
+#include "hw/net/xlnx-zynqmp-can.h"
+
+#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG
+#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT(dev, ...) do { \
+    if (XLNX_ZYNQMP_CAN_ERR_DEBUG) { \
+        g_autofree char *path = object_get_canonical_path(OBJECT(dev)); \
+        qemu_log("%s: %s", path, ## __VA_ARGS__); \
+    } \
+} while (0)
+
+#define MAX_DLC            8
+#undef ERROR
+
+REG32(SOFTWARE_RESET_REGISTER, 0x0)
+    FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
+    FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
+REG32(MODE_SELECT_REGISTER, 0x4)
+    FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
+    FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
+    FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
+REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
+    FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
+REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
+    FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 7, 2)
+    FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 4, 3)
+    FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 4)
+REG32(ERROR_COUNTER_REGISTER, 0x10)
+    FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8)
+    FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
+REG32(ERROR_STATUS_REGISTER, 0x14)
+    FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
+    FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
+    FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
+    FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
+    FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
+REG32(STATUS_REGISTER, 0x18)
+    FIELD(STATUS_REGISTER, SNOOP, 12, 1)
+    FIELD(STATUS_REGISTER, ACFBSY, 11, 1)
+    FIELD(STATUS_REGISTER, TXFLL, 10, 1)
+    FIELD(STATUS_REGISTER, TXBFLL, 9, 1)
+    FIELD(STATUS_REGISTER, ESTAT, 7, 2)
+    FIELD(STATUS_REGISTER, ERRWRN, 6, 1)
+    FIELD(STATUS_REGISTER, BBSY, 5, 1)
+    FIELD(STATUS_REGISTER, BIDLE, 4, 1)
+    FIELD(STATUS_REGISTER, NORMAL, 3, 1)
+    FIELD(STATUS_REGISTER, SLEEP, 2, 1)
+    FIELD(STATUS_REGISTER, LBACK, 1, 1)
+    FIELD(STATUS_REGISTER, CONFIG, 0, 1)
+REG32(INTERRUPT_STATUS_REGISTER, 0x1c)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXFEMP, 14, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXFWMEMP, 13, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, ERROR, 8, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXNEMP, 7, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXOFLW, 6, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXUFLW, 5, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXBFLL, 3, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXFLL, 2, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
+REG32(INTERRUPT_ENABLE_REGISTER, 0x20)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXFEMP, 14, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXFWMEMP, 13, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXNEMP, 7, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXOFLW, 6, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXUFLW, 5, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXBFLL, 3, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXFLL, 2, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, EARBLST, 0, 1)
+REG32(INTERRUPT_CLEAR_REGISTER, 0x24)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXFEMP, 14, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXFWMEMP, 13, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXNEMP, 7, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXOFLW, 6, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXUFLW, 5, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXBFLL, 3, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXFLL, 2, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CARBLST, 0, 1)
+REG32(TIMESTAMP_REGISTER, 0x28)
+    FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
+REG32(WIR, 0x2c)
+    FIELD(WIR, EW, 8, 8)
+    FIELD(WIR, FW, 0, 8)
+REG32(TXFIFO_ID, 0x30)
+    FIELD(TXFIFO_ID, IDH, 21, 11)
+    FIELD(TXFIFO_ID, SRRRTR, 20, 1)
+    FIELD(TXFIFO_ID, IDE, 19, 1)
+    FIELD(TXFIFO_ID, IDL, 1, 18)
+    FIELD(TXFIFO_ID, RTR, 0, 1)
+REG32(TXFIFO_DLC, 0x34)
+    FIELD(TXFIFO_DLC, DLC, 28, 4)
+REG32(TXFIFO_DATA1, 0x38)
+    FIELD(TXFIFO_DATA1, DB0, 24, 8)
+    FIELD(TXFIFO_DATA1, DB1, 16, 8)
+    FIELD(TXFIFO_DATA1, DB2, 8, 8)
+    FIELD(TXFIFO_DATA1, DB3, 0, 8)
+REG32(TXFIFO_DATA2, 0x3c)
+    FIELD(TXFIFO_DATA2, DB4, 24, 8)
+    FIELD(TXFIFO_DATA2, DB5, 16, 8)
+    FIELD(TXFIFO_DATA2, DB6, 8, 8)
+    FIELD(TXFIFO_DATA2, DB7, 0, 8)
+REG32(TXHPB_ID, 0x40)
+    FIELD(TXHPB_ID, IDH, 21, 11)
+    FIELD(TXHPB_ID, SRRRTR, 20, 1)
+    FIELD(TXHPB_ID, IDE, 19, 1)
+    FIELD(TXHPB_ID, IDL, 1, 18)
+    FIELD(TXHPB_ID, RTR, 0, 1)
+REG32(TXHPB_DLC, 0x44)
+    FIELD(TXHPB_DLC, DLC, 28, 4)
+REG32(TXHPB_DATA1, 0x48)
+    FIELD(TXHPB_DATA1, DB0, 24, 8)
+    FIELD(TXHPB_DATA1, DB1, 16, 8)
+    FIELD(TXHPB_DATA1, DB2, 8, 8)
+    FIELD(TXHPB_DATA1, DB3, 0, 8)
+REG32(TXHPB_DATA2, 0x4c)
+    FIELD(TXHPB_DATA2, DB4, 24, 8)
+    FIELD(TXHPB_DATA2, DB5, 16, 8)
+    FIELD(TXHPB_DATA2, DB6, 8, 8)
+    FIELD(TXHPB_DATA2, DB7, 0, 8)
+REG32(RXFIFO_ID, 0x50)
+    FIELD(RXFIFO_ID, IDH, 21, 11)
+    FIELD(RXFIFO_ID, SRRRTR, 20, 1)
+    FIELD(RXFIFO_ID, IDE, 19, 1)
+    FIELD(RXFIFO_ID, IDL, 1, 18)
+    FIELD(RXFIFO_ID, RTR, 0, 1)
+REG32(RXFIFO_DLC, 0x54)
+    FIELD(RXFIFO_DLC, DLC, 28, 4)
+    FIELD(RXFIFO_DLC, RXT, 0, 16)
+REG32(RXFIFO_DATA1, 0x58)
+    FIELD(RXFIFO_DATA1, DB0, 24, 8)
+    FIELD(RXFIFO_DATA1, DB1, 16, 8)
+    FIELD(RXFIFO_DATA1, DB2, 8, 8)
+    FIELD(RXFIFO_DATA1, DB3, 0, 8)
+REG32(RXFIFO_DATA2, 0x5c)
+    FIELD(RXFIFO_DATA2, DB4, 24, 8)
+    FIELD(RXFIFO_DATA2, DB5, 16, 8)
+    FIELD(RXFIFO_DATA2, DB6, 8, 8)
+    FIELD(RXFIFO_DATA2, DB7, 0, 8)
+REG32(AFR, 0x60)
+    FIELD(AFR, UAF4, 3, 1)
+    FIELD(AFR, UAF3, 2, 1)
+    FIELD(AFR, UAF2, 1, 1)
+    FIELD(AFR, UAF1, 0, 1)
+REG32(AFMR1, 0x64)
+    FIELD(AFMR1, AMIDH, 21, 11)
+    FIELD(AFMR1, AMSRR, 20, 1)
+    FIELD(AFMR1, AMIDE, 19, 1)
+    FIELD(AFMR1, AMIDL, 1, 18)
+    FIELD(AFMR1, AMRTR, 0, 1)
+REG32(AFIR1, 0x68)
+    FIELD(AFIR1, AIIDH, 21, 11)
+    FIELD(AFIR1, AISRR, 20, 1)
+    FIELD(AFIR1, AIIDE, 19, 1)
+    FIELD(AFIR1, AIIDL, 1, 18)
+    FIELD(AFIR1, AIRTR, 0, 1)
+REG32(AFMR2, 0x6c)
+    FIELD(AFMR2, AMIDH, 21, 11)
+    FIELD(AFMR2, AMSRR, 20, 1)
+    FIELD(AFMR2, AMIDE, 19, 1)
+    FIELD(AFMR2, AMIDL, 1, 18)
+    FIELD(AFMR2, AMRTR, 0, 1)
+REG32(AFIR2, 0x70)
+    FIELD(AFIR2, AIIDH, 21, 11)
+    FIELD(AFIR2, AISRR, 20, 1)
+    FIELD(AFIR2, AIIDE, 19, 1)
+    FIELD(AFIR2, AIIDL, 1, 18)
+    FIELD(AFIR2, AIRTR, 0, 1)
+REG32(AFMR3, 0x74)
+    FIELD(AFMR3, AMIDH, 21, 11)
+    FIELD(AFMR3, AMSRR, 20, 1)
+    FIELD(AFMR3, AMIDE, 19, 1)
+    FIELD(AFMR3, AMIDL, 1, 18)
+    FIELD(AFMR3, AMRTR, 0, 1)
+REG32(AFIR3, 0x78)
+    FIELD(AFIR3, AIIDH, 21, 11)
+    FIELD(AFIR3, AISRR, 20, 1)
+    FIELD(AFIR3, AIIDE, 19, 1)
+    FIELD(AFIR3, AIIDL, 1, 18)
+    FIELD(AFIR3, AIRTR, 0, 1)
+REG32(AFMR4, 0x7c)
+    FIELD(AFMR4, AMIDH, 21, 11)
+    FIELD(AFMR4, AMSRR, 20, 1)
+    FIELD(AFMR4, AMIDE, 19, 1)
+    FIELD(AFMR4, AMIDL, 1, 18)
+    FIELD(AFMR4, AMRTR, 0, 1)
+REG32(AFIR4, 0x80)
+    FIELD(AFIR4, AIIDH, 21, 11)
+    FIELD(AFIR4, AISRR, 20, 1)
+    FIELD(AFIR4, AIIDE, 19, 1)
+    FIELD(AFIR4, AIIDL, 1, 18)
+    FIELD(AFIR4, AIRTR, 0, 1)
+
+static void can_update_irq(XlnxZynqMPCANState *s)
+{
+    uint32_t irq;
+
+    /* Watermark register interrupts. */
+    if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) >
+            ARRAY_FIELD_EX32(s->regs, WIR, EW)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1);
+    }
+
+    if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) >
+            ARRAY_FIELD_EX32(s->regs, WIR, FW)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1);
+    }
+
+    /* RX Interrupts. */
+    if (fifo32_num_used(&s->rx_fifo) >= CAN_FRAME_SIZE) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1);
+    }
+
+    /* TX interrupts. */
+    if (fifo32_is_empty(&s->tx_fifo)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1);
+    }
+
+    if (fifo32_is_full(&s->tx_fifo)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1);
+    }
+
+    if (fifo32_is_full(&s->txhpb_fifo)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1);
+    }
+
+    irq = s->regs[R_INTERRUPT_STATUS_REGISTER];
+    irq &= s->regs[R_INTERRUPT_ENABLE_REGISTER];
+
+    qemu_set_irq(s->irq, irq);
+}
+
+static void can_ier_post_write(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    can_update_irq(s);
+}
+
+static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t val = val64;
+
+    s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val;
+    can_update_irq(s);
+
+    return 0;
+}
+
+static void can_config_reset(XlnxZynqMPCANState *s)
+{
+    /* Reset all the configuration registers. */
+    register_reset(&s->reg_info[R_SOFTWARE_RESET_REGISTER]);
+    register_reset(&s->reg_info[R_MODE_SELECT_REGISTER]);
+    register_reset(
+              &s->reg_info[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]);
+    register_reset(&s->reg_info[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]);
+    register_reset(&s->reg_info[R_STATUS_REGISTER]);
+    register_reset(&s->reg_info[R_INTERRUPT_STATUS_REGISTER]);
+    register_reset(&s->reg_info[R_INTERRUPT_ENABLE_REGISTER]);
+    register_reset(&s->reg_info[R_INTERRUPT_CLEAR_REGISTER]);
+    register_reset(&s->reg_info[R_WIR]);
+}
+
+static void can_config_mode(XlnxZynqMPCANState *s)
+{
+    register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]);
+    register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]);
+
+    /* Put XlnxZynqMPCAN in configuration mode. */
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0);
+
+    can_update_irq(s);
+}
+
+static void update_status_register_mode_bits(XlnxZynqMPCANState *s)
+{
+    bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP);
+    bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP);
+    /* Wake up interrupt bit. */
+    bool wakeup_irq_val = sleep_status && (sleep_mode == 0);
+    /* Sleep interrupt bit. */
+    bool sleep_irq_val = sleep_mode && (sleep_status == 0);
+
+    /* Clear previous core mode status bits. */
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0);
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0);
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0);
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0);
+
+    /* set current mode bit and generate irqs accordingly. */
+    if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1);
+    } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1);
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP,
+                         sleep_irq_val);
+    } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1);
+    } else {
+        /*
+         * If all bits are zero then XlnxZynqMPCAN is set in normal mode.
+         */
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1);
+        /* Set wakeup interrupt bit. */
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP,
+                         wakeup_irq_val);
+    }
+
+    can_update_irq(s);
+}
+
+static void can_exit_sleep_mode(XlnxZynqMPCANState *s)
+{
+    ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0);
+    update_status_register_mode_bits(s);
+}
+
+static void generate_frame(qemu_can_frame *frame, uint32_t *data)
+{
+    frame->can_id = data[0];
+    frame->can_dlc = FIELD_EX32(data[1], TXFIFO_DLC, DLC);
+
+    frame->data[0] = FIELD_EX32(data[2], TXFIFO_DATA1, DB3);
+    frame->data[1] = FIELD_EX32(data[2], TXFIFO_DATA1, DB2);
+    frame->data[2] = FIELD_EX32(data[2], TXFIFO_DATA1, DB1);
+    frame->data[3] = FIELD_EX32(data[2], TXFIFO_DATA1, DB0);
+
+    frame->data[4] = FIELD_EX32(data[3], TXFIFO_DATA2, DB7);
+    frame->data[5] = FIELD_EX32(data[3], TXFIFO_DATA2, DB6);
+    frame->data[6] = FIELD_EX32(data[3], TXFIFO_DATA2, DB5);
+    frame->data[7] = FIELD_EX32(data[3], TXFIFO_DATA2, DB4);
+}
+
+static bool tx_ready_check(XlnxZynqMPCANState *s)
+{
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
+                      " data while controller is in reset mode.\n",
+                      path);
+        return false;
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer"
+                      " data while controller is in configuration mode. Reset"
+                      " the core so operations can start fresh.\n",
+                      path);
+        return false;
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer"
+                      " data while controller is in SNOOP MODE.\n",
+                      path);
+        return false;
+    }
+
+    return true;
+}
+
+static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo)
+{
+    qemu_can_frame frame;
+    uint32_t data[CAN_FRAME_SIZE];
+    int i;
+    bool can_tx = tx_ready_check(s);
+
+    if (can_tx) {
+        while (!fifo32_is_empty(fifo)) {
+            for (i = 0; i < CAN_FRAME_SIZE; i++) {
+                data[i] = fifo32_pop(fifo);
+            }
+
+            if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
+                /*
+                 * Controller is in loopback. In Loopback mode, the CAN core
+                 * transmits a recessive bitstream on to the XlnxZynqMPCAN Bus.
+                 * Any message transmitted is looped back to the RX line and
+                 * acknowledged. The XlnxZynqMPCAN core receives any message
+                 * that it transmits.
+                 */
+                if (fifo32_is_full(&s->rx_fifo)) {
+                    DB_PRINT(s, "Loopback: RX FIFO is full."
+                             " TX FIFO will be flushed.\n");
+
+                    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER,
+                                     RXOFLW, 1);
+                } else {
+                    for (i = 0; i < CAN_FRAME_SIZE; i++) {
+                        fifo32_push(&s->rx_fifo, data[i]);
+                    }
+
+                    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER,
+                                     RXOK, 1);
+                }
+            } else {
+                /* Normal mode Tx. */
+                generate_frame(&frame, data);
+
+                can_bus_client_send(&s->bus_client, &frame, 1);
+            }
+        }
+
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0);
+
+        if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
+            can_exit_sleep_mode(s);
+        }
+    } else {
+        DB_PRINT(s, "Not enabled for data transfer.\n");
+    }
+
+    can_update_irq(s);
+}
+
+static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t val = val64;
+
+    ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN,
+                     FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN));
+
+    if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) {
+        DB_PRINT(s, "Resetting controller.\n");
+
+        /* First, core will do software reset then will enter in config mode. */
+        can_config_reset(s);
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
+        can_config_mode(s);
+    } else {
+        /*
+         * Leave config mode. Now XlnxZynqMPCAN core will enter normal,
+         * sleep, snoop or loopback mode depending upon LBACK, SLEEP, SNOOP
+         * register states.
+         */
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0);
+
+        ptimer_transaction_begin(s->can_timer);
+        ptimer_set_count(s->can_timer, 0);
+        ptimer_transaction_commit(s->can_timer);
+
+        /* XlnxZynqMPCAN is out of config mode. It will send pending data. */
+        transfer_fifo(s, &s->txhpb_fifo);
+        transfer_fifo(s, &s->tx_fifo);
+    }
+
+    update_status_register_mode_bits(s);
+
+    return s->regs[R_SOFTWARE_RESET_REGISTER];
+}
+
+static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t val = val64;
+    uint8_t multi_mode;
+
+    /*
+     * Multiple mode set check. This is done to make sure user doesn't set
+     * multiple modes.
+     */
+    multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) +
+                 FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) +
+                 FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP);
+
+    if (multi_mode > 1) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to config"
+                      " several modes simultaneously. One mode will be selected"
+                      " according to their priority: LBACK > SLEEP > SNOOP.\n",
+                      path);
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
+        /* We are in configuration mode, any mode can be selected. */
+        s->regs[R_MODE_SELECT_REGISTER] = val;
+    } else {
+        bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP);
+
+        ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit);
+
+        if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) {
+            g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set"
+                          " LBACK mode without setting CEN bit as 0.\n",
+                          path);
+        } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) {
+            g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set"
+                          " SNOOP mode without setting CEN bit as 0.\n",
+                          path);
+        }
+
+        update_status_register_mode_bits(s);
+    }
+
+    return s->regs[R_MODE_SELECT_REGISTER];
+}
+
+static uint64_t can_brpr_pre_write(RegisterInfo  *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t val = val64;
+
+    /* Only allow writes when in config mode. */
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
+        val = s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER];
+    }
+
+    return val;
+}
+
+static uint64_t can_btr_pre_write(RegisterInfo  *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t val = val64;
+
+    /* Only allow writes when in config mode. */
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
+        val = s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER];
+    }
+
+    return val;
+}
+
+static uint64_t can_tcr_pre_write(RegisterInfo  *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t val = val64;
+
+    if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) {
+        ptimer_transaction_begin(s->can_timer);
+        ptimer_set_count(s->can_timer, 0);
+        ptimer_transaction_commit(s->can_timer);
+    }
+
+    return 0;
+}
+
+static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
+{
+    bool filter_pass = false;
+    uint16_t timestamp = 0;
+
+    /* If no filter is enabled. Message will be stored in FIFO. */
+    if (!((ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) |
+       (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) |
+       (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) |
+       (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)))) {
+        filter_pass = true;
+    }
+
+    /*
+     * Messages that pass any of the acceptance filters will be stored in
+     * the RX FIFO.
+     */
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) {
+        uint32_t id_masked = s->regs[R_AFMR1] & frame->can_id;
+        uint32_t filter_id_masked = s->regs[R_AFMR1] & s->regs[R_AFIR1];
+
+        if (filter_id_masked == id_masked) {
+            filter_pass = true;
+        }
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) {
+        uint32_t id_masked = s->regs[R_AFMR2] & frame->can_id;
+        uint32_t filter_id_masked = s->regs[R_AFMR2] & s->regs[R_AFIR2];
+
+        if (filter_id_masked == id_masked) {
+            filter_pass = true;
+        }
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) {
+        uint32_t id_masked = s->regs[R_AFMR3] & frame->can_id;
+        uint32_t filter_id_masked = s->regs[R_AFMR3] & s->regs[R_AFIR3];
+
+        if (filter_id_masked == id_masked) {
+            filter_pass = true;
+        }
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) {
+        uint32_t id_masked = s->regs[R_AFMR4] & frame->can_id;
+        uint32_t filter_id_masked = s->regs[R_AFMR4] & s->regs[R_AFIR4];
+
+        if (filter_id_masked == id_masked) {
+            filter_pass = true;
+        }
+    }
+
+    /* Store the message in fifo if it passed through any of the filters. */
+    if (filter_pass && frame->can_dlc <= MAX_DLC) {
+
+        if (fifo32_is_full(&s->rx_fifo)) {
+            DB_PRINT(s, "RX FIFO is full.\n");
+
+            ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
+        } else {
+            timestamp = CAN_TIMER_MAX - ptimer_get_count(s->can_timer);
+
+            fifo32_push(&s->rx_fifo, frame->can_id);
+
+            fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT,
+                                               R_RXFIFO_DLC_DLC_LENGTH,
+                                               frame->can_dlc) |
+                                     deposit32(0, R_RXFIFO_DLC_RXT_SHIFT,
+                                               R_RXFIFO_DLC_RXT_LENGTH,
+                                               timestamp));
+
+            /* First 32 bit of the data. */
+            fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
+                                               R_TXFIFO_DATA1_DB3_LENGTH,
+                                               frame->data[0]) |
+                                     deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
+                                               R_TXFIFO_DATA1_DB2_LENGTH,
+                                               frame->data[1]) |
+                                     deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
+                                               R_TXFIFO_DATA1_DB1_LENGTH,
+                                               frame->data[2]) |
+                                     deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
+                                               R_TXFIFO_DATA1_DB0_LENGTH,
+                                               frame->data[3]));
+            /* Last 32 bit of the data. */
+            fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
+                                               R_TXFIFO_DATA2_DB7_LENGTH,
+                                               frame->data[4]) |
+                                     deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
+                                               R_TXFIFO_DATA2_DB6_LENGTH,
+                                               frame->data[5]) |
+                                     deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
+                                               R_TXFIFO_DATA2_DB5_LENGTH,
+                                               frame->data[6]) |
+                                     deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
+                                               R_TXFIFO_DATA2_DB4_LENGTH,
+                                               frame->data[7]));
+
+            ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
+        }
+
+        can_update_irq(s);
+    } else {
+        DB_PRINT(s, "Message didn't pass through any filter or dlc"
+                 " is not in range.\n");
+    }
+}
+
+static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t r = 0;
+
+    if (!fifo32_is_empty(&s->rx_fifo)) {
+        r = fifo32_pop(&s->rx_fifo);
+    } else {
+        DB_PRINT(s, "No message in RXFIFO.\n");
+
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1);
+    }
+
+    can_update_irq(s);
+    return r;
+}
+
+static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) &&
+        ARRAY_FIELD_EX32(s->regs, AFR, UAF2) &&
+        ARRAY_FIELD_EX32(s->regs, AFR, UAF3) &&
+        ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 1);
+    } else {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0);
+    }
+}
+
+static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t reg_idx = (reg->access->addr) / 4;
+    uint32_t val = val64;
+    uint32_t filter_number = (reg_idx - R_AFMR1) / 2;
+
+    /* modify an acceptance filter, the corresponding UAF bit should be '0.' */
+    if (!(s->regs[R_AFR] & (1 << filter_number))) {
+        s->regs[reg_idx] = val;
+    } else {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
+                      " mask is not set as corresponding UAF bit is not 0.\n",
+                      path, filter_number + 1);
+    }
+
+    return s->regs[reg_idx];
+}
+
+static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t reg_idx = (reg->access->addr) / 4;
+    uint32_t val = val64;
+    uint32_t filter_number = (reg_idx - R_AFIR1) / 2;
+
+    if (!(s->regs[R_AFR] & (1 << filter_number))) {
+        s->regs[reg_idx] = val;
+    } else {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
+                      " id is not set as corresponding UAF bit is not 0.\n",
+                      path, filter_number + 1);
+    }
+
+    return s->regs[reg_idx];
+}
+
+static void can_tx_post_write(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t val = val64;
+
+    bool is_txhpb = reg->access->addr > A_TXFIFO_DATA2;
+
+    bool initiate_transfer = (reg->access->addr == A_TXFIFO_DATA2) ||
+                             (reg->access->addr == A_TXHPB_DATA2);
+
+    Fifo32 *f = is_txhpb ? &s->txhpb_fifo : &s->tx_fifo;
+
+    DB_PRINT(s, "TX FIFO write.\n");
+
+    if (!fifo32_is_full(f)) {
+        fifo32_push(f, val);
+    } else {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: TX FIFO is full.\n", path);
+    }
+
+    /* Initiate the message send if TX register is written. */
+    if (initiate_transfer &&
+        ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
+        transfer_fifo(s, f);
+    }
+
+    can_update_irq(s);
+}
+
+static const RegisterAccessInfo can_regs_info[] = {
+    {   .name = "SOFTWARE_RESET_REGISTER",
+        .addr = A_SOFTWARE_RESET_REGISTER,
+        .rsvd = 0xfffffffc,
+        .pre_write = can_srr_pre_write,
+    },{ .name = "MODE_SELECT_REGISTER",
+        .addr = A_MODE_SELECT_REGISTER,
+        .rsvd = 0xfffffff8,
+        .pre_write = can_msr_pre_write,
+    },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER",
+        .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER,
+        .rsvd = 0xffffff00,
+        .pre_write = can_brpr_pre_write,
+    },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER",
+        .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER,
+        .rsvd = 0xfffffe00,
+        .pre_write = can_btr_pre_write,
+    },{ .name = "ERROR_COUNTER_REGISTER",
+        .addr = A_ERROR_COUNTER_REGISTER,
+        .rsvd = 0xffff0000,
+        .ro = 0xffffffff,
+    },{ .name = "ERROR_STATUS_REGISTER",
+        .addr = A_ERROR_STATUS_REGISTER,
+        .rsvd = 0xffffffe0,
+        .w1c = 0x1f,
+    },{ .name = "STATUS_REGISTER",  .addr = A_STATUS_REGISTER,
+        .reset = 0x1,
+        .rsvd = 0xffffe000,
+        .ro = 0x1fff,
+    },{ .name = "INTERRUPT_STATUS_REGISTER",
+        .addr = A_INTERRUPT_STATUS_REGISTER,
+        .reset = 0x6000,
+        .rsvd = 0xffff8000,
+        .ro = 0x7fff,
+    },{ .name = "INTERRUPT_ENABLE_REGISTER",
+        .addr = A_INTERRUPT_ENABLE_REGISTER,
+        .rsvd = 0xffff8000,
+        .post_write = can_ier_post_write,
+    },{ .name = "INTERRUPT_CLEAR_REGISTER",
+        .addr = A_INTERRUPT_CLEAR_REGISTER,
+        .rsvd = 0xffff8000,
+        .pre_write = can_icr_pre_write,
+    },{ .name = "TIMESTAMP_REGISTER",
+        .addr = A_TIMESTAMP_REGISTER,
+        .rsvd = 0xfffffffe,
+        .pre_write = can_tcr_pre_write,
+    },{ .name = "WIR",  .addr = A_WIR,
+        .reset = 0x3f3f,
+        .rsvd = 0xffff0000,
+    },{ .name = "TXFIFO_ID",  .addr = A_TXFIFO_ID,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXFIFO_DLC",  .addr = A_TXFIFO_DLC,
+        .rsvd = 0xfffffff,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXFIFO_DATA1",  .addr = A_TXFIFO_DATA1,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXFIFO_DATA2",  .addr = A_TXFIFO_DATA2,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXHPB_ID",  .addr = A_TXHPB_ID,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXHPB_DLC",  .addr = A_TXHPB_DLC,
+        .rsvd = 0xfffffff,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXHPB_DATA1",  .addr = A_TXHPB_DATA1,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXHPB_DATA2",  .addr = A_TXHPB_DATA2,
+        .post_write = can_tx_post_write,
+    },{ .name = "RXFIFO_ID",  .addr = A_RXFIFO_ID,
+        .ro = 0xffffffff,
+        .post_read = can_rxfifo_pre_read,
+    },{ .name = "RXFIFO_DLC",  .addr = A_RXFIFO_DLC,
+        .rsvd = 0xfff0000,
+        .post_read = can_rxfifo_pre_read,
+    },{ .name = "RXFIFO_DATA1",  .addr = A_RXFIFO_DATA1,
+        .post_read = can_rxfifo_pre_read,
+    },{ .name = "RXFIFO_DATA2",  .addr = A_RXFIFO_DATA2,
+        .post_read = can_rxfifo_pre_read,
+    },{ .name = "AFR",  .addr = A_AFR,
+        .rsvd = 0xfffffff0,
+        .post_write = can_filter_enable_post_write,
+    },{ .name = "AFMR1",  .addr = A_AFMR1,
+        .pre_write = can_filter_mask_pre_write,
+    },{ .name = "AFIR1",  .addr = A_AFIR1,
+        .pre_write = can_filter_id_pre_write,
+    },{ .name = "AFMR2",  .addr = A_AFMR2,
+        .pre_write = can_filter_mask_pre_write,
+    },{ .name = "AFIR2",  .addr = A_AFIR2,
+        .pre_write = can_filter_id_pre_write,
+    },{ .name = "AFMR3",  .addr = A_AFMR3,
+        .pre_write = can_filter_mask_pre_write,
+    },{ .name = "AFIR3",  .addr = A_AFIR3,
+        .pre_write = can_filter_id_pre_write,
+    },{ .name = "AFMR4",  .addr = A_AFMR4,
+        .pre_write = can_filter_mask_pre_write,
+    },{ .name = "AFIR4",  .addr = A_AFIR4,
+        .pre_write = can_filter_id_pre_write,
+    }
+};
+
+static void xlnx_zynqmp_can_ptimer_cb(void *opaque)
+{
+    /* No action required on the timer rollover. */
+}
+
+static const MemoryRegionOps can_ops = {
+    .read = register_read_memory,
+    .write = register_write_memory,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
+    unsigned int i;
+
+    for (i = R_RXFIFO_ID; i < ARRAY_SIZE(s->reg_info); ++i) {
+        register_reset(&s->reg_info[i]);
+    }
+
+    ptimer_transaction_begin(s->can_timer);
+    ptimer_set_count(s->can_timer, 0);
+    ptimer_transaction_commit(s->can_timer);
+}
+
+static void xlnx_zynqmp_can_reset_hold(Object *obj)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
+    unsigned int i;
+
+    for (i = 0; i < R_RXFIFO_ID; ++i) {
+        register_reset(&s->reg_info[i]);
+    }
+
+    /*
+     * Reset FIFOs when CAN model is reset. This will clear the fifo writes
+     * done by post_write which gets called from register_reset function,
+     * post_write handle will not be able to trigger tx because CAN will be
+     * disabled when software_reset_register is cleared first.
+     */
+    fifo32_reset(&s->rx_fifo);
+    fifo32_reset(&s->tx_fifo);
+    fifo32_reset(&s->txhpb_fifo);
+}
+
+static bool xlnx_zynqmp_can_can_receive(CanBusClientState *client)
+{
+    XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
+                                         bus_client);
+
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
+        DB_PRINT(s, "Controller is in reset.\n");
+        return false;
+    } else if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) == 0) {
+        DB_PRINT(s, "Controller is disabled. Incoming messages"
+                 " will be discarded.\n");
+        return false;
+    } else {
+        return true;
+    }
+}
+
+static ssize_t xlnx_zynqmp_can_receive(CanBusClientState *client,
+                               const qemu_can_frame *buf, size_t buf_size) {
+    XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
+                                        bus_client);
+    const qemu_can_frame *frame = buf;
+
+    DB_PRINT(s, "Incoming data.\n");
+
+    if (buf_size <= 0) {
+        DB_PRINT(s, "Junk data received.\n");
+        return 0;
+    }
+    if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
+        /*
+         * XlnxZynqMPCAN will not participate in normal bus communication
+         * and will not receive any messages transmitted by other CAN nodes.
+         */
+        DB_PRINT(s, "Controller is in loopback mode. It will not"
+                 " receive data.\n");
+
+    } else if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
+        /* Snoop Mode: Just keep the data. no response back. */
+        update_rx_fifo(s, frame);
+    } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) {
+        /*
+         * XlnxZynqMPCAN is in sleep mode. Any data on bus will bring it to wake
+         * up state.
+         */
+        can_exit_sleep_mode(s);
+        update_rx_fifo(s, frame);
+    } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) == 0) {
+        update_rx_fifo(s, frame);
+    } else {
+        DB_PRINT(s, "Cannot receive data as controller is not configured"
+                 " correctly.\n");
+    }
+
+    return 1;
+}
+
+static CanBusClientInfo can_xilinx_bus_client_info = {
+    .can_receive = xlnx_zynqmp_can_can_receive,
+    .receive = xlnx_zynqmp_can_receive,
+};
+
+static int xlnx_zynqmp_can_connect_to_bus(XlnxZynqMPCANState *s,
+                                          CanBusState *bus)
+{
+    s->bus_client.info = &can_xilinx_bus_client_info;
+
+    if (can_bus_insert_client(bus, &s->bus_client) < 0) {
+        return -1;
+    }
+    return 0;
+}
+
+static void xlnx_zynqmp_can_realize(DeviceState *dev, Error **errp)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(dev);
+
+    if (s->canbus) {
+        if (xlnx_zynqmp_can_connect_to_bus(s, s->canbus) < 0) {
+            g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+            error_setg(errp, "%s: xlnx_zynqmp_can_connect_to_bus"
+                       " failed.", path);
+            return;
+        }
+
+    } else {
+        /* If no bus is set. */
+        DB_PRINT(s, "Canbus property is not set.\n");
+    }
+
+    /* Create RX FIFO, TXFIFO, TXHPB storage. */
+    fifo32_create(&s->rx_fifo, RXFIFO_SIZE);
+    fifo32_create(&s->tx_fifo, RXFIFO_SIZE);
+    fifo32_create(&s->txhpb_fifo, CAN_FRAME_SIZE);
+
+    /* Allocate a new timer. */
+    s->can_timer = ptimer_init(xlnx_zynqmp_can_ptimer_cb, s,
+                               PTIMER_POLICY_DEFAULT);
+
+    ptimer_transaction_begin(s->can_timer);
+
+    ptimer_set_freq(s->can_timer, s->cfg.ext_clk_freq);
+    ptimer_set_limit(s->can_timer, CAN_TIMER_MAX, 1);
+    ptimer_run(s->can_timer, 0);
+    ptimer_transaction_commit(s->can_timer);
+}
+
+static void xlnx_zynqmp_can_init(Object *obj)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+    RegisterInfoArray *reg_array;
+
+    memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_CAN,
+                        XLNX_ZYNQMP_CAN_R_MAX * 4);
+    reg_array = register_init_block32(DEVICE(obj), can_regs_info,
+                               ARRAY_SIZE(can_regs_info),
+                               s->reg_info, s->regs,
+                               &can_ops,
+                               XLNX_ZYNQMP_CAN_ERR_DEBUG,
+                               XLNX_ZYNQMP_CAN_R_MAX * 4);
+
+    memory_region_add_subregion(&s->iomem, 0x00, &reg_array->mem);
+    sysbus_init_mmio(sbd, &s->iomem);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+}
+
+static const VMStateDescription vmstate_can = {
+    .name = TYPE_XLNX_ZYNQMP_CAN,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_FIFO32(rx_fifo, XlnxZynqMPCANState),
+        VMSTATE_FIFO32(tx_fifo, XlnxZynqMPCANState),
+        VMSTATE_FIFO32(txhpb_fifo, XlnxZynqMPCANState),
+        VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCANState, XLNX_ZYNQMP_CAN_R_MAX),
+        VMSTATE_PTIMER(can_timer, XlnxZynqMPCANState),
+        VMSTATE_END_OF_LIST(),
+    }
+};
+
+static Property xlnx_zynqmp_can_properties[] = {
+    DEFINE_PROP_UINT32("ext_clk_freq", XlnxZynqMPCANState, cfg.ext_clk_freq,
+                       CAN_DEFAULT_CLOCK),
+    DEFINE_PROP_LINK("canbus", XlnxZynqMPCANState, canbus, TYPE_CAN_BUS,
+                     CanBusState *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xlnx_zynqmp_can_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    rc->phases.enter = xlnx_zynqmp_can_reset_init;
+    rc->phases.hold = xlnx_zynqmp_can_reset_hold;
+    dc->realize = xlnx_zynqmp_can_realize;
+    device_class_set_props(dc, xlnx_zynqmp_can_properties);
+    dc->vmsd = &vmstate_can;
+}
+
+static const TypeInfo can_info = {
+    .name          = TYPE_XLNX_ZYNQMP_CAN,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(XlnxZynqMPCANState),
+    .class_init    = xlnx_zynqmp_can_class_init,
+    .instance_init = xlnx_zynqmp_can_init,
+};
+
+static void can_register_types(void)
+{
+    type_register_static(&can_info);
+}
+
+type_init(can_register_types)
diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/can/meson.build
+++ b/hw/net/can/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_CAN_SJA1000', if_true: files('can_sja1000.c'))
 softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_kvaser_pci.c'))
 softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c'))
 softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'))
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.c'))
-- 
2.20.1

From: Vikram Garhwal <fnu.vikram@xilinx.com>

Connect CAN0 and CAN1 on the ZynqMP.

Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1597278668-339715-3-git-send-email-fnu.vikram@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-zynqmp.h |  8 ++++++++
 hw/arm/xlnx-zcu102.c         | 20 ++++++++++++++++++++
 hw/arm/xlnx-zynqmp.c         | 34 ++++++++++++++++++++++++++++++++++
 3 files changed, 62 insertions(+)

diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
+#include "hw/net/xlnx-zynqmp-can.h"
 #include "hw/ide/ahci.h"
 #include "hw/sd/sdhci.h"
 #include "hw/ssi/xilinx_spips.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/cpu/cluster.h"
 #include "target/arm/cpu.h"
 #include "qom/object.h"
+#include "net/can_emu.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
 typedef struct XlnxZynqMPState XlnxZynqMPState;
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(XlnxZynqMPState, XLNX_ZYNQMP,
 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
 #define XLNX_ZYNQMP_NUM_GEMS 4
 #define XLNX_ZYNQMP_NUM_UARTS 2
+#define XLNX_ZYNQMP_NUM_CAN 2
+#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
 #define XLNX_ZYNQMP_NUM_SDHCI 2
 #define XLNX_ZYNQMP_NUM_SPIS 2
 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
 
     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+    XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
     SysbusAHCIState sata;
     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
     bool virt;
     /* Has the RPU subsystem?  */
     bool has_rpu;
+
+    /* CAN bus. */
+    CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
 };
 
 #endif
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/qtest.h"
 #include "sysemu/device_tree.h"
 #include "qom/object.h"
+#include "net/can_emu.h"
 
 struct XlnxZCU102 {
     MachineState parent_obj;
@@ -XXX,XX +XXX,XX @@ struct XlnxZCU102 {
     bool secure;
     bool virt;
 
+    CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
+
     struct arm_boot_info binfo;
 };
 typedef struct XlnxZCU102 XlnxZCU102;
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
     object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
                              &error_fatal);
 
+    for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
+        gchar *bus_name = g_strdup_printf("canbus%d", i);
+
+        object_property_set_link(OBJECT(&s->soc), bus_name,
+                                 OBJECT(s->canbus[i]), &error_fatal);
+        g_free(bus_name);
+    }
+
     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
 
     /* Create and plug in the SD cards */
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
                                     "Set on/off to enable/disable emulating a "
                                     "guest CPU which implements the ARM "
                                     "Virtualization Extensions");
+    object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
+                             (Object **)&s->canbus[0],
+                             object_property_allow_set_link,
+                             0);
+
+    object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS,
+                             (Object **)&s->canbus[1],
+                             object_property_allow_set_link,
+                             0);
 }
 
 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
     21, 22,
 };
 
+static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
+    0xFF060000, 0xFF070000,
+};
+
+static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
+    23, 24,
+};
+
 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
     0xFF160000, 0xFF170000,
 };
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
                                 TYPE_CADENCE_UART);
     }
 
+    for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
+        object_initialize_child(obj, "can[*]", &s->can[i],
+                                TYPE_XLNX_ZYNQMP_CAN);
+    }
+
     object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
 
     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
                            gic_spi[uart_intr[i]]);
     }
 
+    for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
+        object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
+                                XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
+
+        object_property_set_link(OBJECT(&s->can[i]), "canbus",
+                                 OBJECT(s->canbus[i]), &error_fatal);
+
+        sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
+                           gic_spi[can_intr[i]]);
+    }
+
     object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
                             &error_abort);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
@@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = {
     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
                      MemoryRegion *),
+    DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
+                     CanBusState *),
+    DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
+                     CanBusState *),
     DEFINE_PROP_END_OF_LIST()
 };
 
-- 
2.20.1

From: Vikram Garhwal <fnu.vikram@xilinx.com>

The QTests perform five tests on the Xilinx ZynqMP CAN controller:
    Tests the CAN controller in loopback, sleep and snoop mode.
    Tests filtering of incoming CAN messages.

Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1597278668-339715-4-git-send-email-fnu.vikram@xilinx.com
[PMM: updated to meson build system]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/xlnx-can-test.c | 359 ++++++++++++++++++++++++++++++++++++
 tests/qtest/meson.build     |   1 +
 2 files changed, 360 insertions(+)
 create mode 100644 tests/qtest/xlnx-can-test.c

diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/xlnx-can-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for the Xilinx ZynqMP CAN controller.
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "libqos/libqtest.h"
+
+/* Base address. */
+#define CAN0_BASE_ADDR          0xFF060000
+#define CAN1_BASE_ADDR          0xFF070000
+
+/* Register addresses. */
+#define R_SRR_OFFSET            0x00
+#define R_MSR_OFFSET            0x04
+#define R_SR_OFFSET             0x18
+#define R_ISR_OFFSET            0x1C
+#define R_ICR_OFFSET            0x24
+#define R_TXID_OFFSET           0x30
+#define R_TXDLC_OFFSET          0x34
+#define R_TXDATA1_OFFSET        0x38
+#define R_TXDATA2_OFFSET        0x3C
+#define R_RXID_OFFSET           0x50
+#define R_RXDLC_OFFSET          0x54
+#define R_RXDATA1_OFFSET        0x58
+#define R_RXDATA2_OFFSET        0x5C
+#define R_AFR                   0x60
+#define R_AFMR1                 0x64
+#define R_AFIR1                 0x68
+#define R_AFMR2                 0x6C
+#define R_AFIR2                 0x70
+#define R_AFMR3                 0x74
+#define R_AFIR3                 0x78
+#define R_AFMR4                 0x7C
+#define R_AFIR4                 0x80
+
+/* CAN modes. */
+#define CONFIG_MODE             0x00
+#define NORMAL_MODE             0x00
+#define LOOPBACK_MODE           0x02
+#define SNOOP_MODE              0x04
+#define SLEEP_MODE              0x01
+#define ENABLE_CAN              (1 << 1)
+#define STATUS_NORMAL_MODE      (1 << 3)
+#define STATUS_LOOPBACK_MODE    (1 << 1)
+#define STATUS_SNOOP_MODE       (1 << 12)
+#define STATUS_SLEEP_MODE       (1 << 2)
+#define ISR_TXOK                (1 << 1)
+#define ISR_RXOK                (1 << 4)
+
+static void match_rx_tx_data(uint32_t *buf_tx, uint32_t *buf_rx,
+                             uint8_t can_timestamp)
+{
+    uint16_t size = 0;
+    uint8_t len = 4;
+
+    while (size < len) {
+        if (R_RXID_OFFSET + 4 * size == R_RXDLC_OFFSET)  {
+            g_assert_cmpint(buf_rx[size], ==, buf_tx[size] + can_timestamp);
+        } else {
+            g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
+        }
+
+        size++;
+    }
+}
+
+static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
+{
+    uint32_t int_status;
+
+    /* Read the interrupt on CAN rx. */
+    int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
+
+    g_assert_cmpint(int_status, ==, ISR_RXOK);
+
+    /* Read the RX register data for CAN. */
+    buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET);
+    buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET);
+    buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET);
+    buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET);
+
+    /* Clear the RX interrupt. */
+    qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK);
+}
+
+static void send_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_tx)
+{
+    uint32_t int_status;
+
+    /* Write the TX register data for CAN. */
+    qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]);
+    qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]);
+    qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]);
+    qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]);
+
+    /* Read the interrupt on CAN for tx. */
+    int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK;
+
+    g_assert_cmpint(int_status, ==, ISR_TXOK);
+
+    /* Clear the interrupt for tx. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK);
+}
+
+/*
+ * This test will be transferring data from CAN0 and CAN1 through canbus. CAN0
+ * initiate the data transfer to can-bus, CAN1 receives the data. Test compares
+ * the data sent from CAN0 with received on CAN1.
+ */
+static void test_can_bus(void)
+{
+    uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+    uint8_t can_timestamp = 1;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0 and CAN1. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+
+    /* Check here if CAN0 and CAN1 are in normal mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    send_data(qts, CAN0_BASE_ADDR, buf_tx);
+
+    read_data(qts, CAN1_BASE_ADDR, buf_rx);
+    match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
+
+    qtest_quit(qts);
+}
+
+/*
+ * This test is performing loopback mode on CAN0 and CAN1. Data sent from TX of
+ * each CAN0 and CAN1 are compared with RX register data for respective CAN.
+ */
+static void test_can_loopback(void)
+{
+    uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0 in loopback mode. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+
+    /* Check here if CAN0 is set in loopback mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+
+    g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
+
+    send_data(qts, CAN0_BASE_ADDR, buf_tx);
+    read_data(qts, CAN0_BASE_ADDR, buf_rx);
+    match_rx_tx_data(buf_tx, buf_rx, 0);
+
+    /* Configure the CAN1 in loopback mode. */
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+
+    /* Check here if CAN1 is set in loopback mode. */
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+
+    g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
+
+    send_data(qts, CAN1_BASE_ADDR, buf_tx);
+    read_data(qts, CAN1_BASE_ADDR, buf_rx);
+    match_rx_tx_data(buf_tx, buf_rx, 0);
+
+    qtest_quit(qts);
+}
+
+/*
+ * Enable filters for CAN1. This will filter incoming messages with ID. In this
+ * test message will pass through filter 2.
+ */
+static void test_can_filter(void)
+{
+    uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+    uint8_t can_timestamp = 1;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0 and CAN1. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+
+    /* Check here if CAN0 and CAN1 are in normal mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    /* Set filter for CAN1 for incoming messages. */
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234);
+
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF);
+
+    send_data(qts, CAN0_BASE_ADDR, buf_tx);
+
+    read_data(qts, CAN1_BASE_ADDR, buf_rx);
+    match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
+
+    qtest_quit(qts);
+}
+
+/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */
+static void test_can_sleepmode(void)
+{
+    uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+    uint8_t can_timestamp = 1;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+
+    /* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_SLEEP_MODE);
+
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    send_data(qts, CAN1_BASE_ADDR, buf_tx);
+
+    /*
+     * Once CAN1 sends data on can-bus. CAN0 should exit sleep mode.
+     * Check the CAN0 status now. It should exit the sleep mode and receive the
+     * incoming data.
+     */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    read_data(qts, CAN0_BASE_ADDR, buf_rx);
+
+    match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
+
+    qtest_quit(qts);
+}
+
+/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */
+static void test_can_snoopmode(void)
+{
+    uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+    uint8_t can_timestamp = 1;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+
+    /* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_SNOOP_MODE);
+
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    send_data(qts, CAN1_BASE_ADDR, buf_tx);
+
+    read_data(qts, CAN0_BASE_ADDR, buf_rx);
+
+    match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
+
+    qtest_quit(qts);
+}
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    qtest_add_func("/net/can/can_bus", test_can_bus);
+    qtest_add_func("/net/can/can_loopback", test_can_loopback);
+    qtest_add_func("/net/can/can_filter", test_can_filter);
+    qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode);
+    qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode);
+
+    return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
   (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
   ['numa-test',
    'boot-serial-test',
+   'xlnx-can-test',
    'migration-test']
 
 qtests_s390x = \
-- 
2.20.1

First pullreq for 6.0: mostly my v8.1M work, plus some other
bits and pieces. (I still have a lot of stuff in my to-review
folder, which I may or may not get to before the Christmas break...)

thanks
-- PMM

The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210

for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:

hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/smmuv3: Fix up L1STD_SPAN decoding
 * xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
 * sbsa-ref: allow to use Cortex-A53/57/72 cpus
 * Various minor code cleanups
 * hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
 * Implement more pieces of ARMv8.1M support

----------------------------------------------------------------
Alex Chen (4):
      i.MX25: Fix bad printf format specifiers
      i.MX31: Fix bad printf format specifiers
      i.MX6: Fix bad printf format specifiers
      i.MX6ul: Fix bad printf format specifiers

Havard Skinnemoen (1):
      tests/qtest/npcm7xx_rng-test: dump random data on failure

Kunkun Jiang (1):
      hw/arm/smmuv3: Fix up L1STD_SPAN decoding

Marcin Juszkiewicz (1):
      sbsa-ref: allow to use Cortex-A53/57/72 cpus

Peter Maydell (25):
      hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
      target/arm: Implement v8.1M PXN extension
      target/arm: Don't clobber ID_PFR1.Security on M-profile cores
      target/arm: Implement VSCCLRM insn
      target/arm: Implement CLRM instruction
      target/arm: Enforce M-profile VMRS/VMSR register restrictions
      target/arm: Refactor M-profile VMSR/VMRS handling
      target/arm: Move general-use constant expanders up in translate.c
      target/arm: Implement VLDR/VSTR system register
      target/arm: Implement M-profile FPSCR_nzcvqc
      target/arm: Use new FPCR_NZCV_MASK constant
      target/arm: Factor out preserve-fp-state from full_vfp_access_check()
      target/arm: Implement FPCXT_S fp system register
      hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
      target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
      target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
      target/arm: Implement v8.1M REVIDR register
      target/arm: Implement new v8.1M NOCP check for exception return
      target/arm: Implement new v8.1M VLLDM and VLSTM encodings
      hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
      target/arm: Implement CCR_S.TRD behaviour for SG insns
      hw/intc/armv7m_nvic: Fix "return from inactive handler" check
      target/arm: Implement M-profile "minimal RAS implementation"
      hw/intc/armv7m_nvic: Implement read/write for RAS register block
      hw/arm/armv7m: Correct typo in QOM object name

From: Vikram Garhwal <fnu.vikram@xilinx.com>

The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.

Example for using single CAN:
    -object can-bus,id=canbus0 \
    -machine xlnx-zcu102.canbus0=canbus0 \
    -object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0

To create virtual CAN on the host machine, please check the QEMU CAN docs:
https://github.com/qemu/qemu/blob/master/docs/can.txt

Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 meson.build                      |    1 +
 hw/net/can/trace.h               |    1 +
 include/hw/net/xlnx-zynqmp-can.h |   78 ++
 hw/net/can/xlnx-zynqmp-can.c     | 1161 ++++++++++++++++++++++++++++++
 hw/Kconfig                       |    1 +
 hw/net/can/meson.build           |    1 +
 hw/net/can/trace-events          |    9 +
 7 files changed, 1252 insertions(+)
 create mode 100644 hw/net/can/trace.h
 create mode 100644 include/hw/net/xlnx-zynqmp-can.h
 create mode 100644 hw/net/can/xlnx-zynqmp-can.c
 create mode 100644 hw/net/can/trace-events

diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
     'hw/misc',
     'hw/misc/macio',
     'hw/net',
+    'hw/net/can',
     'hw/nvram',
     'hw/pci',
     'hw/pci-host',
diff --git a/hw/net/can/trace.h b/hw/net/can/trace.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/net/can/trace.h
@@ -0,0 +1 @@
+#include "trace/trace-hw_net_can.h"
diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-can.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/net/xlnx-zynqmp-can.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of the Xilinx ZynqMP CAN controller.
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
+ * Pavel Pisa.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef XLNX_ZYNQMP_CAN_H
+#define XLNX_ZYNQMP_CAN_H
+
+#include "hw/register.h"
+#include "net/can_emu.h"
+#include "net/can_host.h"
+#include "qemu/fifo32.h"
+#include "hw/ptimer.h"
+#include "hw/qdev-clock.h"
+
+#define TYPE_XLNX_ZYNQMP_CAN "xlnx.zynqmp-can"
+
+#define XLNX_ZYNQMP_CAN(obj) \
+     OBJECT_CHECK(XlnxZynqMPCANState, (obj), TYPE_XLNX_ZYNQMP_CAN)
+
+#define MAX_CAN_CTRLS      2
+#define XLNX_ZYNQMP_CAN_R_MAX     (0x84 / 4)
+#define MAILBOX_CAPACITY   64
+#define CAN_TIMER_MAX  0XFFFFUL
+#define CAN_DEFAULT_CLOCK (24 * 1000 * 1000)
+
+/* Each CAN_FRAME will have 4 * 32bit size. */
+#define CAN_FRAME_SIZE     4
+#define RXFIFO_SIZE        (MAILBOX_CAPACITY * CAN_FRAME_SIZE)
+
+typedef struct XlnxZynqMPCANState {
+    SysBusDevice        parent_obj;
+    MemoryRegion        iomem;
+
+    qemu_irq            irq;
+
+    CanBusClientState   bus_client;
+    CanBusState         *canbus;
+
+    struct {
+        uint32_t        ext_clk_freq;
+    } cfg;
+
+    RegisterInfo        reg_info[XLNX_ZYNQMP_CAN_R_MAX];
+    uint32_t            regs[XLNX_ZYNQMP_CAN_R_MAX];
+
+    Fifo32              rx_fifo;
+    Fifo32              tx_fifo;
+    Fifo32              txhpb_fifo;
+
+    ptimer_state        *can_timer;
+} XlnxZynqMPCANState;
+
+#endif
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/net/can/xlnx-zynqmp-can.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of the Xilinx ZynqMP CAN controller.
+ * This implementation is based on the following datasheet:
+ * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
+ * Pavel Pisa
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "hw/irq.h"
+#include "qapi/error.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qemu/cutils.h"
+#include "sysemu/sysemu.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "net/can_emu.h"
+#include "net/can_host.h"
+#include "qemu/event_notifier.h"
+#include "qom/object_interfaces.h"
+#include "hw/net/xlnx-zynqmp-can.h"
+#include "trace.h"
+
+#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG
+#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0
+#endif
+
+#define MAX_DLC            8
+#undef ERROR
+
+REG32(SOFTWARE_RESET_REGISTER, 0x0)
+    FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
+    FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
+REG32(MODE_SELECT_REGISTER, 0x4)
+    FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
+    FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
+    FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
+REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
+    FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
+REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
+    FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 7, 2)
+    FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 4, 3)
+    FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 4)
+REG32(ERROR_COUNTER_REGISTER, 0x10)
+    FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8)
+    FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
+REG32(ERROR_STATUS_REGISTER, 0x14)
+    FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
+    FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
+    FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
+    FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
+    FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
+REG32(STATUS_REGISTER, 0x18)
+    FIELD(STATUS_REGISTER, SNOOP, 12, 1)
+    FIELD(STATUS_REGISTER, ACFBSY, 11, 1)
+    FIELD(STATUS_REGISTER, TXFLL, 10, 1)
+    FIELD(STATUS_REGISTER, TXBFLL, 9, 1)
+    FIELD(STATUS_REGISTER, ESTAT, 7, 2)
+    FIELD(STATUS_REGISTER, ERRWRN, 6, 1)
+    FIELD(STATUS_REGISTER, BBSY, 5, 1)
+    FIELD(STATUS_REGISTER, BIDLE, 4, 1)
+    FIELD(STATUS_REGISTER, NORMAL, 3, 1)
+    FIELD(STATUS_REGISTER, SLEEP, 2, 1)
+    FIELD(STATUS_REGISTER, LBACK, 1, 1)
+    FIELD(STATUS_REGISTER, CONFIG, 0, 1)
+REG32(INTERRUPT_STATUS_REGISTER, 0x1c)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXFEMP, 14, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXFWMEMP, 13, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, ERROR, 8, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXNEMP, 7, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXOFLW, 6, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXUFLW, 5, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXBFLL, 3, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXFLL, 2, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1)
+    FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
+REG32(INTERRUPT_ENABLE_REGISTER, 0x20)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXFEMP, 14, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXFWMEMP, 13, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXNEMP, 7, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXOFLW, 6, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXUFLW, 5, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXBFLL, 3, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXFLL, 2, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1)
+    FIELD(INTERRUPT_ENABLE_REGISTER, EARBLST, 0, 1)
+REG32(INTERRUPT_CLEAR_REGISTER, 0x24)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXFEMP, 14, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXFWMEMP, 13, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXNEMP, 7, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXOFLW, 6, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXUFLW, 5, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXBFLL, 3, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXFLL, 2, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1)
+    FIELD(INTERRUPT_CLEAR_REGISTER, CARBLST, 0, 1)
+REG32(TIMESTAMP_REGISTER, 0x28)
+    FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
+REG32(WIR, 0x2c)
+    FIELD(WIR, EW, 8, 8)
+    FIELD(WIR, FW, 0, 8)
+REG32(TXFIFO_ID, 0x30)
+    FIELD(TXFIFO_ID, IDH, 21, 11)
+    FIELD(TXFIFO_ID, SRRRTR, 20, 1)
+    FIELD(TXFIFO_ID, IDE, 19, 1)
+    FIELD(TXFIFO_ID, IDL, 1, 18)
+    FIELD(TXFIFO_ID, RTR, 0, 1)
+REG32(TXFIFO_DLC, 0x34)
+    FIELD(TXFIFO_DLC, DLC, 28, 4)
+REG32(TXFIFO_DATA1, 0x38)
+    FIELD(TXFIFO_DATA1, DB0, 24, 8)
+    FIELD(TXFIFO_DATA1, DB1, 16, 8)
+    FIELD(TXFIFO_DATA1, DB2, 8, 8)
+    FIELD(TXFIFO_DATA1, DB3, 0, 8)
+REG32(TXFIFO_DATA2, 0x3c)
+    FIELD(TXFIFO_DATA2, DB4, 24, 8)
+    FIELD(TXFIFO_DATA2, DB5, 16, 8)
+    FIELD(TXFIFO_DATA2, DB6, 8, 8)
+    FIELD(TXFIFO_DATA2, DB7, 0, 8)
+REG32(TXHPB_ID, 0x40)
+    FIELD(TXHPB_ID, IDH, 21, 11)
+    FIELD(TXHPB_ID, SRRRTR, 20, 1)
+    FIELD(TXHPB_ID, IDE, 19, 1)
+    FIELD(TXHPB_ID, IDL, 1, 18)
+    FIELD(TXHPB_ID, RTR, 0, 1)
+REG32(TXHPB_DLC, 0x44)
+    FIELD(TXHPB_DLC, DLC, 28, 4)
+REG32(TXHPB_DATA1, 0x48)
+    FIELD(TXHPB_DATA1, DB0, 24, 8)
+    FIELD(TXHPB_DATA1, DB1, 16, 8)
+    FIELD(TXHPB_DATA1, DB2, 8, 8)
+    FIELD(TXHPB_DATA1, DB3, 0, 8)
+REG32(TXHPB_DATA2, 0x4c)
+    FIELD(TXHPB_DATA2, DB4, 24, 8)
+    FIELD(TXHPB_DATA2, DB5, 16, 8)
+    FIELD(TXHPB_DATA2, DB6, 8, 8)
+    FIELD(TXHPB_DATA2, DB7, 0, 8)
+REG32(RXFIFO_ID, 0x50)
+    FIELD(RXFIFO_ID, IDH, 21, 11)
+    FIELD(RXFIFO_ID, SRRRTR, 20, 1)
+    FIELD(RXFIFO_ID, IDE, 19, 1)
+    FIELD(RXFIFO_ID, IDL, 1, 18)
+    FIELD(RXFIFO_ID, RTR, 0, 1)
+REG32(RXFIFO_DLC, 0x54)
+    FIELD(RXFIFO_DLC, DLC, 28, 4)
+    FIELD(RXFIFO_DLC, RXT, 0, 16)
+REG32(RXFIFO_DATA1, 0x58)
+    FIELD(RXFIFO_DATA1, DB0, 24, 8)
+    FIELD(RXFIFO_DATA1, DB1, 16, 8)
+    FIELD(RXFIFO_DATA1, DB2, 8, 8)
+    FIELD(RXFIFO_DATA1, DB3, 0, 8)
+REG32(RXFIFO_DATA2, 0x5c)
+    FIELD(RXFIFO_DATA2, DB4, 24, 8)
+    FIELD(RXFIFO_DATA2, DB5, 16, 8)
+    FIELD(RXFIFO_DATA2, DB6, 8, 8)
+    FIELD(RXFIFO_DATA2, DB7, 0, 8)
+REG32(AFR, 0x60)
+    FIELD(AFR, UAF4, 3, 1)
+    FIELD(AFR, UAF3, 2, 1)
+    FIELD(AFR, UAF2, 1, 1)
+    FIELD(AFR, UAF1, 0, 1)
+REG32(AFMR1, 0x64)
+    FIELD(AFMR1, AMIDH, 21, 11)
+    FIELD(AFMR1, AMSRR, 20, 1)
+    FIELD(AFMR1, AMIDE, 19, 1)
+    FIELD(AFMR1, AMIDL, 1, 18)
+    FIELD(AFMR1, AMRTR, 0, 1)
+REG32(AFIR1, 0x68)
+    FIELD(AFIR1, AIIDH, 21, 11)
+    FIELD(AFIR1, AISRR, 20, 1)
+    FIELD(AFIR1, AIIDE, 19, 1)
+    FIELD(AFIR1, AIIDL, 1, 18)
+    FIELD(AFIR1, AIRTR, 0, 1)
+REG32(AFMR2, 0x6c)
+    FIELD(AFMR2, AMIDH, 21, 11)
+    FIELD(AFMR2, AMSRR, 20, 1)
+    FIELD(AFMR2, AMIDE, 19, 1)
+    FIELD(AFMR2, AMIDL, 1, 18)
+    FIELD(AFMR2, AMRTR, 0, 1)
+REG32(AFIR2, 0x70)
+    FIELD(AFIR2, AIIDH, 21, 11)
+    FIELD(AFIR2, AISRR, 20, 1)
+    FIELD(AFIR2, AIIDE, 19, 1)
+    FIELD(AFIR2, AIIDL, 1, 18)
+    FIELD(AFIR2, AIRTR, 0, 1)
+REG32(AFMR3, 0x74)
+    FIELD(AFMR3, AMIDH, 21, 11)
+    FIELD(AFMR3, AMSRR, 20, 1)
+    FIELD(AFMR3, AMIDE, 19, 1)
+    FIELD(AFMR3, AMIDL, 1, 18)
+    FIELD(AFMR3, AMRTR, 0, 1)
+REG32(AFIR3, 0x78)
+    FIELD(AFIR3, AIIDH, 21, 11)
+    FIELD(AFIR3, AISRR, 20, 1)
+    FIELD(AFIR3, AIIDE, 19, 1)
+    FIELD(AFIR3, AIIDL, 1, 18)
+    FIELD(AFIR3, AIRTR, 0, 1)
+REG32(AFMR4, 0x7c)
+    FIELD(AFMR4, AMIDH, 21, 11)
+    FIELD(AFMR4, AMSRR, 20, 1)
+    FIELD(AFMR4, AMIDE, 19, 1)
+    FIELD(AFMR4, AMIDL, 1, 18)
+    FIELD(AFMR4, AMRTR, 0, 1)
+REG32(AFIR4, 0x80)
+    FIELD(AFIR4, AIIDH, 21, 11)
+    FIELD(AFIR4, AISRR, 20, 1)
+    FIELD(AFIR4, AIIDE, 19, 1)
+    FIELD(AFIR4, AIIDL, 1, 18)
+    FIELD(AFIR4, AIRTR, 0, 1)
+
+static void can_update_irq(XlnxZynqMPCANState *s)
+{
+    uint32_t irq;
+
+    /* Watermark register interrupts. */
+    if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) >
+            ARRAY_FIELD_EX32(s->regs, WIR, EW)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1);
+    }
+
+    if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) >
+            ARRAY_FIELD_EX32(s->regs, WIR, FW)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1);
+    }
+
+    /* RX Interrupts. */
+    if (fifo32_num_used(&s->rx_fifo) >= CAN_FRAME_SIZE) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1);
+    }
+
+    /* TX interrupts. */
+    if (fifo32_is_empty(&s->tx_fifo)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1);
+    }
+
+    if (fifo32_is_full(&s->tx_fifo)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1);
+    }
+
+    if (fifo32_is_full(&s->txhpb_fifo)) {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1);
+    }
+
+    irq = s->regs[R_INTERRUPT_STATUS_REGISTER];
+    irq &= s->regs[R_INTERRUPT_ENABLE_REGISTER];
+
+    trace_xlnx_can_update_irq(s->regs[R_INTERRUPT_STATUS_REGISTER],
+                              s->regs[R_INTERRUPT_ENABLE_REGISTER], irq);
+    qemu_set_irq(s->irq, irq);
+}
+
+static void can_ier_post_write(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    can_update_irq(s);
+}
+
+static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val;
+    can_update_irq(s);
+
+    return 0;
+}
+
+static void can_config_reset(XlnxZynqMPCANState *s)
+{
+    /* Reset all the configuration registers. */
+    register_reset(&s->reg_info[R_SOFTWARE_RESET_REGISTER]);
+    register_reset(&s->reg_info[R_MODE_SELECT_REGISTER]);
+    register_reset(
+              &s->reg_info[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]);
+    register_reset(&s->reg_info[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]);
+    register_reset(&s->reg_info[R_STATUS_REGISTER]);
+    register_reset(&s->reg_info[R_INTERRUPT_STATUS_REGISTER]);
+    register_reset(&s->reg_info[R_INTERRUPT_ENABLE_REGISTER]);
+    register_reset(&s->reg_info[R_INTERRUPT_CLEAR_REGISTER]);
+    register_reset(&s->reg_info[R_WIR]);
+}
+
+static void can_config_mode(XlnxZynqMPCANState *s)
+{
+    register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]);
+    register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]);
+
+    /* Put XlnxZynqMPCAN in configuration mode. */
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0);
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0);
+
+    can_update_irq(s);
+}
+
+static void update_status_register_mode_bits(XlnxZynqMPCANState *s)
+{
+    bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP);
+    bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP);
+    /* Wake up interrupt bit. */
+    bool wakeup_irq_val = sleep_status && (sleep_mode == 0);
+    /* Sleep interrupt bit. */
+    bool sleep_irq_val = sleep_mode && (sleep_status == 0);
+
+    /* Clear previous core mode status bits. */
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0);
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0);
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0);
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0);
+
+    /* set current mode bit and generate irqs accordingly. */
+    if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1);
+    } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1);
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP,
+                         sleep_irq_val);
+    } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1);
+    } else {
+        /*
+         * If all bits are zero then XlnxZynqMPCAN is set in normal mode.
+         */
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1);
+        /* Set wakeup interrupt bit. */
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP,
+                         wakeup_irq_val);
+    }
+
+    can_update_irq(s);
+}
+
+static void can_exit_sleep_mode(XlnxZynqMPCANState *s)
+{
+    ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0);
+    update_status_register_mode_bits(s);
+}
+
+static void generate_frame(qemu_can_frame *frame, uint32_t *data)
+{
+    frame->can_id = data[0];
+    frame->can_dlc = FIELD_EX32(data[1], TXFIFO_DLC, DLC);
+
+    frame->data[0] = FIELD_EX32(data[2], TXFIFO_DATA1, DB3);
+    frame->data[1] = FIELD_EX32(data[2], TXFIFO_DATA1, DB2);
+    frame->data[2] = FIELD_EX32(data[2], TXFIFO_DATA1, DB1);
+    frame->data[3] = FIELD_EX32(data[2], TXFIFO_DATA1, DB0);
+
+    frame->data[4] = FIELD_EX32(data[3], TXFIFO_DATA2, DB7);
+    frame->data[5] = FIELD_EX32(data[3], TXFIFO_DATA2, DB6);
+    frame->data[6] = FIELD_EX32(data[3], TXFIFO_DATA2, DB5);
+    frame->data[7] = FIELD_EX32(data[3], TXFIFO_DATA2, DB4);
+}
+
+static bool tx_ready_check(XlnxZynqMPCANState *s)
+{
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
+                      " data while controller is in reset mode.\n",
+                      path);
+        return false;
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer"
+                      " data while controller is in configuration mode. Reset"
+                      " the core so operations can start fresh.\n",
+                      path);
+        return false;
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer"
+                      " data while controller is in SNOOP MODE.\n",
+                      path);
+        return false;
+    }
+
+    return true;
+}
+
+static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo)
+{
+    qemu_can_frame frame;
+    uint32_t data[CAN_FRAME_SIZE];
+    int i;
+    bool can_tx = tx_ready_check(s);
+
+    if (!can_tx) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is not enabled for data"
+                      " transfer.\n", path);
+        can_update_irq(s);
+        return;
+    }
+
+    while (!fifo32_is_empty(fifo)) {
+        for (i = 0; i < CAN_FRAME_SIZE; i++) {
+            data[i] = fifo32_pop(fifo);
+        }
+
+        if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
+            /*
+             * Controller is in loopback. In Loopback mode, the CAN core
+             * transmits a recessive bitstream on to the XlnxZynqMPCAN Bus.
+             * Any message transmitted is looped back to the RX line and
+             * acknowledged. The XlnxZynqMPCAN core receives any message
+             * that it transmits.
+             */
+            if (fifo32_is_full(&s->rx_fifo)) {
+                ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
+            } else {
+                for (i = 0; i < CAN_FRAME_SIZE; i++) {
+                    fifo32_push(&s->rx_fifo, data[i]);
+                }
+
+                ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
+            }
+        } else {
+            /* Normal mode Tx. */
+            generate_frame(&frame, data);
+
+            trace_xlnx_can_tx_data(frame.can_id, frame.can_dlc,
+                                   frame.data[0], frame.data[1],
+                                   frame.data[2], frame.data[3],
+                                   frame.data[4], frame.data[5],
+                                   frame.data[6], frame.data[7]);
+            can_bus_client_send(&s->bus_client, &frame, 1);
+        }
+    }
+
+    ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
+    ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0);
+
+    if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
+        can_exit_sleep_mode(s);
+    }
+
+    can_update_irq(s);
+}
+
+static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN,
+                     FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN));
+
+    if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) {
+        trace_xlnx_can_reset(val);
+
+        /* First, core will do software reset then will enter in config mode. */
+        can_config_reset(s);
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
+        can_config_mode(s);
+    } else {
+        /*
+         * Leave config mode. Now XlnxZynqMPCAN core will enter normal,
+         * sleep, snoop or loopback mode depending upon LBACK, SLEEP, SNOOP
+         * register states.
+         */
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0);
+
+        ptimer_transaction_begin(s->can_timer);
+        ptimer_set_count(s->can_timer, 0);
+        ptimer_transaction_commit(s->can_timer);
+
+        /* XlnxZynqMPCAN is out of config mode. It will send pending data. */
+        transfer_fifo(s, &s->txhpb_fifo);
+        transfer_fifo(s, &s->tx_fifo);
+    }
+
+    update_status_register_mode_bits(s);
+
+    return s->regs[R_SOFTWARE_RESET_REGISTER];
+}
+
+static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint8_t multi_mode;
+
+    /*
+     * Multiple mode set check. This is done to make sure user doesn't set
+     * multiple modes.
+     */
+    multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) +
+                 FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) +
+                 FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP);
+
+    if (multi_mode > 1) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to config"
+                      " several modes simultaneously. One mode will be selected"
+                      " according to their priority: LBACK > SLEEP > SNOOP.\n",
+                      path);
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
+        /* We are in configuration mode, any mode can be selected. */
+        s->regs[R_MODE_SELECT_REGISTER] = val;
+    } else {
+        bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP);
+
+        ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit);
+
+        if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) {
+            g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set"
+                          " LBACK mode without setting CEN bit as 0.\n",
+                          path);
+        } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) {
+            g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set"
+                          " SNOOP mode without setting CEN bit as 0.\n",
+                          path);
+        }
+
+        update_status_register_mode_bits(s);
+    }
+
+    return s->regs[R_MODE_SELECT_REGISTER];
+}
+
+static uint64_t can_brpr_pre_write(RegisterInfo  *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    /* Only allow writes when in config mode. */
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
+        return s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER];
+    }
+
+    return val;
+}
+
+static uint64_t can_btr_pre_write(RegisterInfo  *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    /* Only allow writes when in config mode. */
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
+        return s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER];
+    }
+
+    return val;
+}
+
+static uint64_t can_tcr_pre_write(RegisterInfo  *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) {
+        ptimer_transaction_begin(s->can_timer);
+        ptimer_set_count(s->can_timer, 0);
+        ptimer_transaction_commit(s->can_timer);
+    }
+
+    return 0;
+}
+
+static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
+{
+    bool filter_pass = false;
+    uint16_t timestamp = 0;
+
+    /* If no filter is enabled. Message will be stored in FIFO. */
+    if (!((ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) |
+       (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) |
+       (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) |
+       (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)))) {
+        filter_pass = true;
+    }
+
+    /*
+     * Messages that pass any of the acceptance filters will be stored in
+     * the RX FIFO.
+     */
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) {
+        uint32_t id_masked = s->regs[R_AFMR1] & frame->can_id;
+        uint32_t filter_id_masked = s->regs[R_AFMR1] & s->regs[R_AFIR1];
+
+        if (filter_id_masked == id_masked) {
+            filter_pass = true;
+        }
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) {
+        uint32_t id_masked = s->regs[R_AFMR2] & frame->can_id;
+        uint32_t filter_id_masked = s->regs[R_AFMR2] & s->regs[R_AFIR2];
+
+        if (filter_id_masked == id_masked) {
+            filter_pass = true;
+        }
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) {
+        uint32_t id_masked = s->regs[R_AFMR3] & frame->can_id;
+        uint32_t filter_id_masked = s->regs[R_AFMR3] & s->regs[R_AFIR3];
+
+        if (filter_id_masked == id_masked) {
+            filter_pass = true;
+        }
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) {
+        uint32_t id_masked = s->regs[R_AFMR4] & frame->can_id;
+        uint32_t filter_id_masked = s->regs[R_AFMR4] & s->regs[R_AFIR4];
+
+        if (filter_id_masked == id_masked) {
+            filter_pass = true;
+        }
+    }
+
+    if (!filter_pass) {
+        trace_xlnx_can_rx_fifo_filter_reject(frame->can_id, frame->can_dlc);
+        return;
+    }
+
+    /* Store the message in fifo if it passed through any of the filters. */
+    if (filter_pass && frame->can_dlc <= MAX_DLC) {
+
+        if (fifo32_is_full(&s->rx_fifo)) {
+            ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
+        } else {
+            timestamp = CAN_TIMER_MAX - ptimer_get_count(s->can_timer);
+
+            fifo32_push(&s->rx_fifo, frame->can_id);
+
+            fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT,
+                                               R_RXFIFO_DLC_DLC_LENGTH,
+                                               frame->can_dlc) |
+                                     deposit32(0, R_RXFIFO_DLC_RXT_SHIFT,
+                                               R_RXFIFO_DLC_RXT_LENGTH,
+                                               timestamp));
+
+            /* First 32 bit of the data. */
+            fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
+                                               R_TXFIFO_DATA1_DB3_LENGTH,
+                                               frame->data[0]) |
+                                     deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
+                                               R_TXFIFO_DATA1_DB2_LENGTH,
+                                               frame->data[1]) |
+                                     deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
+                                               R_TXFIFO_DATA1_DB1_LENGTH,
+                                               frame->data[2]) |
+                                     deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
+                                               R_TXFIFO_DATA1_DB0_LENGTH,
+                                               frame->data[3]));
+            /* Last 32 bit of the data. */
+            fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
+                                               R_TXFIFO_DATA2_DB7_LENGTH,
+                                               frame->data[4]) |
+                                     deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
+                                               R_TXFIFO_DATA2_DB6_LENGTH,
+                                               frame->data[5]) |
+                                     deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
+                                               R_TXFIFO_DATA2_DB5_LENGTH,
+                                               frame->data[6]) |
+                                     deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
+                                               R_TXFIFO_DATA2_DB4_LENGTH,
+                                               frame->data[7]));
+
+            ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
+            trace_xlnx_can_rx_data(frame->can_id, frame->can_dlc,
+                                   frame->data[0], frame->data[1],
+                                   frame->data[2], frame->data[3],
+                                   frame->data[4], frame->data[5],
+                                   frame->data[6], frame->data[7]);
+        }
+
+        can_update_irq(s);
+    }
+}
+
+static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    if (!fifo32_is_empty(&s->rx_fifo)) {
+        val = fifo32_pop(&s->rx_fifo);
+    } else {
+        ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1);
+    }
+
+    can_update_irq(s);
+    return val;
+}
+
+static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) &&
+        ARRAY_FIELD_EX32(s->regs, AFR, UAF2) &&
+        ARRAY_FIELD_EX32(s->regs, AFR, UAF3) &&
+        ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 1);
+    } else {
+        ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0);
+    }
+}
+
+static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t reg_idx = (reg->access->addr) / 4;
+    uint32_t filter_number = (reg_idx - R_AFMR1) / 2;
+
+    /* modify an acceptance filter, the corresponding UAF bit should be '0'. */
+    if (!(s->regs[R_AFR] & (1 << filter_number))) {
+        s->regs[reg_idx] = val;
+
+        trace_xlnx_can_filter_mask_pre_write(filter_number, s->regs[reg_idx]);
+    } else {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
+                      " mask is not set as corresponding UAF bit is not 0.\n",
+                      path, filter_number + 1);
+    }
+
+    return s->regs[reg_idx];
+}
+
+static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+    uint32_t reg_idx = (reg->access->addr) / 4;
+    uint32_t filter_number = (reg_idx - R_AFIR1) / 2;
+
+    if (!(s->regs[R_AFR] & (1 << filter_number))) {
+        s->regs[reg_idx] = val;
+
+        trace_xlnx_can_filter_id_pre_write(filter_number, s->regs[reg_idx]);
+    } else {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
+                      " id is not set as corresponding UAF bit is not 0.\n",
+                      path, filter_number + 1);
+    }
+
+    return s->regs[reg_idx];
+}
+
+static void can_tx_post_write(RegisterInfo *reg, uint64_t val)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
+
+    bool is_txhpb = reg->access->addr > A_TXFIFO_DATA2;
+
+    bool initiate_transfer = (reg->access->addr == A_TXFIFO_DATA2) ||
+                             (reg->access->addr == A_TXHPB_DATA2);
+
+    Fifo32 *f = is_txhpb ? &s->txhpb_fifo : &s->tx_fifo;
+
+    if (!fifo32_is_full(f)) {
+        fifo32_push(f, val);
+    } else {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: TX FIFO is full.\n", path);
+    }
+
+    /* Initiate the message send if TX register is written. */
+    if (initiate_transfer &&
+        ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
+        transfer_fifo(s, f);
+    }
+
+    can_update_irq(s);
+}
+
+static const RegisterAccessInfo can_regs_info[] = {
+    {   .name = "SOFTWARE_RESET_REGISTER",
+        .addr = A_SOFTWARE_RESET_REGISTER,
+        .rsvd = 0xfffffffc,
+        .pre_write = can_srr_pre_write,
+    },{ .name = "MODE_SELECT_REGISTER",
+        .addr = A_MODE_SELECT_REGISTER,
+        .rsvd = 0xfffffff8,
+        .pre_write = can_msr_pre_write,
+    },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER",
+        .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER,
+        .rsvd = 0xffffff00,
+        .pre_write = can_brpr_pre_write,
+    },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER",
+        .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER,
+        .rsvd = 0xfffffe00,
+        .pre_write = can_btr_pre_write,
+    },{ .name = "ERROR_COUNTER_REGISTER",
+        .addr = A_ERROR_COUNTER_REGISTER,
+        .rsvd = 0xffff0000,
+        .ro = 0xffffffff,
+    },{ .name = "ERROR_STATUS_REGISTER",
+        .addr = A_ERROR_STATUS_REGISTER,
+        .rsvd = 0xffffffe0,
+        .w1c = 0x1f,
+    },{ .name = "STATUS_REGISTER",  .addr = A_STATUS_REGISTER,
+        .reset = 0x1,
+        .rsvd = 0xffffe000,
+        .ro = 0x1fff,
+    },{ .name = "INTERRUPT_STATUS_REGISTER",
+        .addr = A_INTERRUPT_STATUS_REGISTER,
+        .reset = 0x6000,
+        .rsvd = 0xffff8000,
+        .ro = 0x7fff,
+    },{ .name = "INTERRUPT_ENABLE_REGISTER",
+        .addr = A_INTERRUPT_ENABLE_REGISTER,
+        .rsvd = 0xffff8000,
+        .post_write = can_ier_post_write,
+    },{ .name = "INTERRUPT_CLEAR_REGISTER",
+        .addr = A_INTERRUPT_CLEAR_REGISTER,
+        .rsvd = 0xffff8000,
+        .pre_write = can_icr_pre_write,
+    },{ .name = "TIMESTAMP_REGISTER",
+        .addr = A_TIMESTAMP_REGISTER,
+        .rsvd = 0xfffffffe,
+        .pre_write = can_tcr_pre_write,
+    },{ .name = "WIR",  .addr = A_WIR,
+        .reset = 0x3f3f,
+        .rsvd = 0xffff0000,
+    },{ .name = "TXFIFO_ID",  .addr = A_TXFIFO_ID,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXFIFO_DLC",  .addr = A_TXFIFO_DLC,
+        .rsvd = 0xfffffff,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXFIFO_DATA1",  .addr = A_TXFIFO_DATA1,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXFIFO_DATA2",  .addr = A_TXFIFO_DATA2,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXHPB_ID",  .addr = A_TXHPB_ID,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXHPB_DLC",  .addr = A_TXHPB_DLC,
+        .rsvd = 0xfffffff,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXHPB_DATA1",  .addr = A_TXHPB_DATA1,
+        .post_write = can_tx_post_write,
+    },{ .name = "TXHPB_DATA2",  .addr = A_TXHPB_DATA2,
+        .post_write = can_tx_post_write,
+    },{ .name = "RXFIFO_ID",  .addr = A_RXFIFO_ID,
+        .ro = 0xffffffff,
+        .post_read = can_rxfifo_pre_read,
+    },{ .name = "RXFIFO_DLC",  .addr = A_RXFIFO_DLC,
+        .rsvd = 0xfff0000,
+        .post_read = can_rxfifo_pre_read,
+    },{ .name = "RXFIFO_DATA1",  .addr = A_RXFIFO_DATA1,
+        .post_read = can_rxfifo_pre_read,
+    },{ .name = "RXFIFO_DATA2",  .addr = A_RXFIFO_DATA2,
+        .post_read = can_rxfifo_pre_read,
+    },{ .name = "AFR",  .addr = A_AFR,
+        .rsvd = 0xfffffff0,
+        .post_write = can_filter_enable_post_write,
+    },{ .name = "AFMR1",  .addr = A_AFMR1,
+        .pre_write = can_filter_mask_pre_write,
+    },{ .name = "AFIR1",  .addr = A_AFIR1,
+        .pre_write = can_filter_id_pre_write,
+    },{ .name = "AFMR2",  .addr = A_AFMR2,
+        .pre_write = can_filter_mask_pre_write,
+    },{ .name = "AFIR2",  .addr = A_AFIR2,
+        .pre_write = can_filter_id_pre_write,
+    },{ .name = "AFMR3",  .addr = A_AFMR3,
+        .pre_write = can_filter_mask_pre_write,
+    },{ .name = "AFIR3",  .addr = A_AFIR3,
+        .pre_write = can_filter_id_pre_write,
+    },{ .name = "AFMR4",  .addr = A_AFMR4,
+        .pre_write = can_filter_mask_pre_write,
+    },{ .name = "AFIR4",  .addr = A_AFIR4,
+        .pre_write = can_filter_id_pre_write,
+    }
+};
+
+static void xlnx_zynqmp_can_ptimer_cb(void *opaque)
+{
+    /* No action required on the timer rollover. */
+}
+
+static const MemoryRegionOps can_ops = {
+    .read = register_read_memory,
+    .write = register_write_memory,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
+    unsigned int i;
+
+    for (i = R_RXFIFO_ID; i < ARRAY_SIZE(s->reg_info); ++i) {
+        register_reset(&s->reg_info[i]);
+    }
+
+    ptimer_transaction_begin(s->can_timer);
+    ptimer_set_count(s->can_timer, 0);
+    ptimer_transaction_commit(s->can_timer);
+}
+
+static void xlnx_zynqmp_can_reset_hold(Object *obj)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
+    unsigned int i;
+
+    for (i = 0; i < R_RXFIFO_ID; ++i) {
+        register_reset(&s->reg_info[i]);
+    }
+
+    /*
+     * Reset FIFOs when CAN model is reset. This will clear the fifo writes
+     * done by post_write which gets called from register_reset function,
+     * post_write handle will not be able to trigger tx because CAN will be
+     * disabled when software_reset_register is cleared first.
+     */
+    fifo32_reset(&s->rx_fifo);
+    fifo32_reset(&s->tx_fifo);
+    fifo32_reset(&s->txhpb_fifo);
+}
+
+static bool xlnx_zynqmp_can_can_receive(CanBusClientState *client)
+{
+    XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
+                                         bus_client);
+
+    if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in reset state.\n",
+                      path);
+        return false;
+    }
+
+    if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) == 0) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is disabled. Incoming"
+                      " messages will be discarded.\n", path);
+        return false;
+    }
+
+    return true;
+}
+
+static ssize_t xlnx_zynqmp_can_receive(CanBusClientState *client,
+                               const qemu_can_frame *buf, size_t buf_size) {
+    XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
+                                         bus_client);
+    const qemu_can_frame *frame = buf;
+
+    if (buf_size <= 0) {
+        g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Error in the data received.\n",
+                      path);
+        return 0;
+    }
+
+    if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
+        /* Snoop Mode: Just keep the data. no response back. */
+        update_rx_fifo(s, frame);
+    } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) {
+        /*
+         * XlnxZynqMPCAN is in sleep mode. Any data on bus will bring it to wake
+         * up state.
+         */
+        can_exit_sleep_mode(s);
+        update_rx_fifo(s, frame);
+    } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) == 0) {
+        update_rx_fifo(s, frame);
+    } else {
+        /*
+         * XlnxZynqMPCAN will not participate in normal bus communication
+         * and will not receive any messages transmitted by other CAN nodes.
+         */
+        trace_xlnx_can_rx_discard(s->regs[R_STATUS_REGISTER]);
+    }
+
+    return 1;
+}
+
+static CanBusClientInfo can_xilinx_bus_client_info = {
+    .can_receive = xlnx_zynqmp_can_can_receive,
+    .receive = xlnx_zynqmp_can_receive,
+};
+
+static int xlnx_zynqmp_can_connect_to_bus(XlnxZynqMPCANState *s,
+                                          CanBusState *bus)
+{
+    s->bus_client.info = &can_xilinx_bus_client_info;
+
+    if (can_bus_insert_client(bus, &s->bus_client) < 0) {
+        return -1;
+    }
+    return 0;
+}
+
+static void xlnx_zynqmp_can_realize(DeviceState *dev, Error **errp)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(dev);
+
+    if (s->canbus) {
+        if (xlnx_zynqmp_can_connect_to_bus(s, s->canbus) < 0) {
+            g_autofree char *path = object_get_canonical_path(OBJECT(s));
+
+            error_setg(errp, "%s: xlnx_zynqmp_can_connect_to_bus"
+                       " failed.", path);
+            return;
+        }
+    }
+
+    /* Create RX FIFO, TXFIFO, TXHPB storage. */
+    fifo32_create(&s->rx_fifo, RXFIFO_SIZE);
+    fifo32_create(&s->tx_fifo, RXFIFO_SIZE);
+    fifo32_create(&s->txhpb_fifo, CAN_FRAME_SIZE);
+
+    /* Allocate a new timer. */
+    s->can_timer = ptimer_init(xlnx_zynqmp_can_ptimer_cb, s,
+                               PTIMER_POLICY_DEFAULT);
+
+    ptimer_transaction_begin(s->can_timer);
+
+    ptimer_set_freq(s->can_timer, s->cfg.ext_clk_freq);
+    ptimer_set_limit(s->can_timer, CAN_TIMER_MAX, 1);
+    ptimer_run(s->can_timer, 0);
+    ptimer_transaction_commit(s->can_timer);
+}
+
+static void xlnx_zynqmp_can_init(Object *obj)
+{
+    XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+    RegisterInfoArray *reg_array;
+
+    memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_CAN,
+                        XLNX_ZYNQMP_CAN_R_MAX * 4);
+    reg_array = register_init_block32(DEVICE(obj), can_regs_info,
+                               ARRAY_SIZE(can_regs_info),
+                               s->reg_info, s->regs,
+                               &can_ops,
+                               XLNX_ZYNQMP_CAN_ERR_DEBUG,
+                               XLNX_ZYNQMP_CAN_R_MAX * 4);
+
+    memory_region_add_subregion(&s->iomem, 0x00, &reg_array->mem);
+    sysbus_init_mmio(sbd, &s->iomem);
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+}
+
+static const VMStateDescription vmstate_can = {
+    .name = TYPE_XLNX_ZYNQMP_CAN,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_FIFO32(rx_fifo, XlnxZynqMPCANState),
+        VMSTATE_FIFO32(tx_fifo, XlnxZynqMPCANState),
+        VMSTATE_FIFO32(txhpb_fifo, XlnxZynqMPCANState),
+        VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCANState, XLNX_ZYNQMP_CAN_R_MAX),
+        VMSTATE_PTIMER(can_timer, XlnxZynqMPCANState),
+        VMSTATE_END_OF_LIST(),
+    }
+};
+
+static Property xlnx_zynqmp_can_properties[] = {
+    DEFINE_PROP_UINT32("ext_clk_freq", XlnxZynqMPCANState, cfg.ext_clk_freq,
+                       CAN_DEFAULT_CLOCK),
+    DEFINE_PROP_LINK("canbus", XlnxZynqMPCANState, canbus, TYPE_CAN_BUS,
+                     CanBusState *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xlnx_zynqmp_can_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    rc->phases.enter = xlnx_zynqmp_can_reset_init;
+    rc->phases.hold = xlnx_zynqmp_can_reset_hold;
+    dc->realize = xlnx_zynqmp_can_realize;
+    device_class_set_props(dc, xlnx_zynqmp_can_properties);
+    dc->vmsd = &vmstate_can;
+}
+
+static const TypeInfo can_info = {
+    .name          = TYPE_XLNX_ZYNQMP_CAN,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(XlnxZynqMPCANState),
+    .class_init    = xlnx_zynqmp_can_class_init,
+    .instance_init = xlnx_zynqmp_can_init,
+};
+
+static void can_register_types(void)
+{
+    type_register_static(&can_info);
+}
+
+type_init(can_register_types)
diff --git a/hw/Kconfig b/hw/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -XXX,XX +XXX,XX @@ config XILINX_AXI
 config XLNX_ZYNQMP
     bool
     select REGISTER
+    select CAN_BUS
diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/can/meson.build
+++ b/hw/net/can/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c'))
 softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'))
 softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_core.c'))
 softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci.c'))
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.c'))
diff --git a/hw/net/can/trace-events b/hw/net/can/trace-events
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/net/can/trace-events
@@ -XXX,XX +XXX,XX @@
+# xlnx-zynqmp-can.c
+xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
+xlnx_can_reset(uint32_t val) "Resetting controller with value = 0x%08x"
+xlnx_can_rx_fifo_filter_reject(uint32_t id, uint8_t dlc) "Frame: ID: 0x%08x DLC: 0x%02x"
+xlnx_can_filter_id_pre_write(uint8_t filter_num, uint32_t value) "Filter%d ID: 0x%08x"
+xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter%d MASK: 0x%08x"
+xlnx_can_tx_data(uint32_t id, uint8_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
+xlnx_can_rx_data(uint32_t id, uint32_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
+xlnx_can_rx_discard(uint32_t status) "Controller is not enabled for bus communication. Status Register: 0x%08x"
-- 
2.20.1

From: Vikram Garhwal <fnu.vikram@xilinx.com>

Connect CAN0 and CAN1 on the ZynqMP.

Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-zynqmp.h |  8 ++++++++
 hw/arm/xlnx-zcu102.c         | 20 ++++++++++++++++++++
 hw/arm/xlnx-zynqmp.c         | 34 ++++++++++++++++++++++++++++++++++
 3 files changed, 62 insertions(+)

diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
+#include "hw/net/xlnx-zynqmp-can.h"
 #include "hw/ide/ahci.h"
 #include "hw/sd/sdhci.h"
 #include "hw/ssi/xilinx_spips.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/cpu/cluster.h"
 #include "target/arm/cpu.h"
 #include "qom/object.h"
+#include "net/can_emu.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
 #define XLNX_ZYNQMP_NUM_GEMS 4
 #define XLNX_ZYNQMP_NUM_UARTS 2
+#define XLNX_ZYNQMP_NUM_CAN 2
+#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
 #define XLNX_ZYNQMP_NUM_SDHCI 2
 #define XLNX_ZYNQMP_NUM_SPIS 2
 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
 
     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+    XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
     SysbusAHCIState sata;
     SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
     XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
     bool virt;
     /* Has the RPU subsystem?  */
     bool has_rpu;
+
+    /* CAN bus. */
+    CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
 };
 
 #endif
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/qtest.h"
 #include "sysemu/device_tree.h"
 #include "qom/object.h"
+#include "net/can_emu.h"
 
 struct XlnxZCU102 {
     MachineState parent_obj;
@@ -XXX,XX +XXX,XX @@ struct XlnxZCU102 {
     bool secure;
     bool virt;
 
+    CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
+
     struct arm_boot_info binfo;
 };
 
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
     object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
                              &error_fatal);
 
+    for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
+        gchar *bus_name = g_strdup_printf("canbus%d", i);
+
+        object_property_set_link(OBJECT(&s->soc), bus_name,
+                                 OBJECT(s->canbus[i]), &error_fatal);
+        g_free(bus_name);
+    }
+
     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
 
     /* Create and plug in the SD cards */
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
     s->secure = false;
     /* Default to virt (EL2) being disabled */
     s->virt = false;
+    object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
+                             (Object **)&s->canbus[0],
+                             object_property_allow_set_link,
+                             0);
+
+    object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS,
+                             (Object **)&s->canbus[1],
+                             object_property_allow_set_link,
+                             0);
 }
 
 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
     21, 22,
 };
 
+static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
+    0xFF060000, 0xFF070000,
+};
+
+static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
+    23, 24,
+};
+
 static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
     0xFF160000, 0xFF170000,
 };
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
                                 TYPE_CADENCE_UART);
     }
 
+    for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
+        object_initialize_child(obj, "can[*]", &s->can[i],
+                                TYPE_XLNX_ZYNQMP_CAN);
+    }
+
     object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
 
     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
                            gic_spi[uart_intr[i]]);
     }
 
+    for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
+        object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
+                                XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
+
+        object_property_set_link(OBJECT(&s->can[i]), "canbus",
+                                 OBJECT(s->canbus[i]), &error_fatal);
+
+        sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
+                           gic_spi[can_intr[i]]);
+    }
+
     object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
                             &error_abort);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
@@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = {
     DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
     DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
                      MemoryRegion *),
+    DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
+                     CanBusState *),
+    DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
+                     CanBusState *),
     DEFINE_PROP_END_OF_LIST()
 };
 
-- 
2.20.1

From: Vikram Garhwal <fnu.vikram@xilinx.com>

The QTests perform five tests on the Xilinx ZynqMP CAN controller:
    Tests the CAN controller in loopback, sleep and snoop mode.
    Tests filtering of incoming CAN messages.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Message-id: 1605728926-352690-4-git-send-email-fnu.vikram@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/xlnx-can-test.c | 360 ++++++++++++++++++++++++++++++++++++
 tests/qtest/meson.build     |   1 +
 2 files changed, 361 insertions(+)
 create mode 100644 tests/qtest/xlnx-can-test.c

diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/qtest/xlnx-can-test.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QTests for the Xilinx ZynqMP CAN controller.
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "libqos/libqtest.h"
+
+/* Base address. */
+#define CAN0_BASE_ADDR          0xFF060000
+#define CAN1_BASE_ADDR          0xFF070000
+
+/* Register addresses. */
+#define R_SRR_OFFSET            0x00
+#define R_MSR_OFFSET            0x04
+#define R_SR_OFFSET             0x18
+#define R_ISR_OFFSET            0x1C
+#define R_ICR_OFFSET            0x24
+#define R_TXID_OFFSET           0x30
+#define R_TXDLC_OFFSET          0x34
+#define R_TXDATA1_OFFSET        0x38
+#define R_TXDATA2_OFFSET        0x3C
+#define R_RXID_OFFSET           0x50
+#define R_RXDLC_OFFSET          0x54
+#define R_RXDATA1_OFFSET        0x58
+#define R_RXDATA2_OFFSET        0x5C
+#define R_AFR                   0x60
+#define R_AFMR1                 0x64
+#define R_AFIR1                 0x68
+#define R_AFMR2                 0x6C
+#define R_AFIR2                 0x70
+#define R_AFMR3                 0x74
+#define R_AFIR3                 0x78
+#define R_AFMR4                 0x7C
+#define R_AFIR4                 0x80
+
+/* CAN modes. */
+#define CONFIG_MODE             0x00
+#define NORMAL_MODE             0x00
+#define LOOPBACK_MODE           0x02
+#define SNOOP_MODE              0x04
+#define SLEEP_MODE              0x01
+#define ENABLE_CAN              (1 << 1)
+#define STATUS_NORMAL_MODE      (1 << 3)
+#define STATUS_LOOPBACK_MODE    (1 << 1)
+#define STATUS_SNOOP_MODE       (1 << 12)
+#define STATUS_SLEEP_MODE       (1 << 2)
+#define ISR_TXOK                (1 << 1)
+#define ISR_RXOK                (1 << 4)
+
+static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
+                             uint8_t can_timestamp)
+{
+    uint16_t size = 0;
+    uint8_t len = 4;
+
+    while (size < len) {
+        if (R_RXID_OFFSET + 4 * size == R_RXDLC_OFFSET)  {
+            g_assert_cmpint(buf_rx[size], ==, buf_tx[size] + can_timestamp);
+        } else {
+            g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
+        }
+
+        size++;
+    }
+}
+
+static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
+{
+    uint32_t int_status;
+
+    /* Read the interrupt on CAN rx. */
+    int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
+
+    g_assert_cmpint(int_status, ==, ISR_RXOK);
+
+    /* Read the RX register data for CAN. */
+    buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET);
+    buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET);
+    buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET);
+    buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET);
+
+    /* Clear the RX interrupt. */
+    qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK);
+}
+
+static void send_data(QTestState *qts, uint64_t can_base_addr,
+                      const uint32_t *buf_tx)
+{
+    uint32_t int_status;
+
+    /* Write the TX register data for CAN. */
+    qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]);
+    qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]);
+    qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]);
+    qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]);
+
+    /* Read the interrupt on CAN for tx. */
+    int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK;
+
+    g_assert_cmpint(int_status, ==, ISR_TXOK);
+
+    /* Clear the interrupt for tx. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK);
+}
+
+/*
+ * This test will be transferring data from CAN0 and CAN1 through canbus. CAN0
+ * initiate the data transfer to can-bus, CAN1 receives the data. Test compares
+ * the data sent from CAN0 with received on CAN1.
+ */
+static void test_can_bus(void)
+{
+    const uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+    uint8_t can_timestamp = 1;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0 and CAN1. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+
+    /* Check here if CAN0 and CAN1 are in normal mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    send_data(qts, CAN0_BASE_ADDR, buf_tx);
+
+    read_data(qts, CAN1_BASE_ADDR, buf_rx);
+    match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
+
+    qtest_quit(qts);
+}
+
+/*
+ * This test is performing loopback mode on CAN0 and CAN1. Data sent from TX of
+ * each CAN0 and CAN1 are compared with RX register data for respective CAN.
+ */
+static void test_can_loopback(void)
+{
+    uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0 in loopback mode. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+
+    /* Check here if CAN0 is set in loopback mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+
+    g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
+
+    send_data(qts, CAN0_BASE_ADDR, buf_tx);
+    read_data(qts, CAN0_BASE_ADDR, buf_rx);
+    match_rx_tx_data(buf_tx, buf_rx, 0);
+
+    /* Configure the CAN1 in loopback mode. */
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+
+    /* Check here if CAN1 is set in loopback mode. */
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+
+    g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
+
+    send_data(qts, CAN1_BASE_ADDR, buf_tx);
+    read_data(qts, CAN1_BASE_ADDR, buf_rx);
+    match_rx_tx_data(buf_tx, buf_rx, 0);
+
+    qtest_quit(qts);
+}
+
+/*
+ * Enable filters for CAN1. This will filter incoming messages with ID. In this
+ * test message will pass through filter 2.
+ */
+static void test_can_filter(void)
+{
+    uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+    uint8_t can_timestamp = 1;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0 and CAN1. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+
+    /* Check here if CAN0 and CAN1 are in normal mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    /* Set filter for CAN1 for incoming messages. */
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234);
+
+    qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF);
+
+    send_data(qts, CAN0_BASE_ADDR, buf_tx);
+
+    read_data(qts, CAN1_BASE_ADDR, buf_rx);
+    match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
+
+    qtest_quit(qts);
+}
+
+/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */
+static void test_can_sleepmode(void)
+{
+    uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+    uint8_t can_timestamp = 1;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+
+    /* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_SLEEP_MODE);
+
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    send_data(qts, CAN1_BASE_ADDR, buf_tx);
+
+    /*
+     * Once CAN1 sends data on can-bus. CAN0 should exit sleep mode.
+     * Check the CAN0 status now. It should exit the sleep mode and receive the
+     * incoming data.
+     */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    read_data(qts, CAN0_BASE_ADDR, buf_rx);
+
+    match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
+
+    qtest_quit(qts);
+}
+
+/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */
+static void test_can_snoopmode(void)
+{
+    uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
+    uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
+    uint32_t status = 0;
+    uint8_t can_timestamp = 1;
+
+    QTestState *qts = qtest_init("-machine xlnx-zcu102"
+                " -object can-bus,id=canbus0"
+                " -machine xlnx-zcu102.canbus0=canbus0"
+                " -machine xlnx-zcu102.canbus1=canbus0"
+                );
+
+    /* Configure the CAN0. */
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE);
+    qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+
+    qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
+    qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
+
+    /* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */
+    status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_SNOOP_MODE);
+
+    status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
+    g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
+
+    send_data(qts, CAN1_BASE_ADDR, buf_tx);
+
+    read_data(qts, CAN0_BASE_ADDR, buf_rx);
+
+    match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
+
+    qtest_quit(qts);
+}
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    qtest_add_func("/net/can/can_bus", test_can_bus);
+    qtest_add_func("/net/can/can_loopback", test_can_loopback);
+    qtest_add_func("/net/can/can_filter", test_can_filter);
+    qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode);
+    qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode);
+
+    return g_test_run();
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
   ['arm-cpu-features',
    'numa-test',
    'boot-serial-test',
+   'xlnx-can-test',
    'migration-test']
 
 qtests_s390x = \
-- 
2.20.1

From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable
it for QEMU as well. A53 was already enabled there.

1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
     [SBSA_GWDT] = 16,
 };
 
+static const char * const valid_cpus[] = {
+    ARM_CPU_TYPE_NAME("cortex-a53"),
+    ARM_CPU_TYPE_NAME("cortex-a57"),
+    ARM_CPU_TYPE_NAME("cortex-a72"),
+};
+
+static bool cpu_type_valid(const char *cpu)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
+        if (strcmp(cpu, valid_cpus[i]) == 0) {
+            return true;
+        }
+    }
+    return false;
+}
+
 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
 {
     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
     const CPUArchIdList *possible_cpus;
     int n, sbsa_max_cpus;
 
-    if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
-        error_report("sbsa-ref: CPU type other than the built-in "
-                     "cortex-a57 not supported");
+    if (!cpu_type_valid(machine->cpu_type)) {
+        error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
         exit(1);
     }
 
-- 
2.20.1

From: Havard Skinnemoen <hskinnemoen@google.com>

Dump the collected random data after a randomness test failure.

Note that this relies on the test having called
g_test_set_nonfatal_assertions() so we don't abort immediately on the
assertion failure.

Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: minor commit message tweak]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/npcm7xx_rng-test.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/npcm7xx_rng-test.c
+++ b/tests/qtest/npcm7xx_rng-test.c
@@ -XXX,XX +XXX,XX @@
 
 #include "libqtest-single.h"
 #include "qemu/bitops.h"
+#include "qemu-common.h"
 
 #define RNG_BASE_ADDR   0xf000b000
 
@@ -XXX,XX +XXX,XX @@
 /* Number of bits to collect for randomness tests. */
 #define TEST_INPUT_BITS  (128)
 
+static void dump_buf_if_failed(const uint8_t *buf, size_t size)
+{
+    if (g_test_failed()) {
+        qemu_hexdump(stderr, "", buf, size);
+    }
+}
+
 static void rng_writeb(unsigned int offset, uint8_t value)
 {
     writeb(RNG_BASE_ADDR + offset, value);
@@ -XXX,XX +XXX,XX @@ static void test_continuous_monobit(void)
     }
 
     g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
+    dump_buf_if_failed(buf, sizeof(buf));
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void test_continuous_runs(void)
     }
 
     g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
+    dump_buf_if_failed(buf.c, sizeof(buf));
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void test_first_byte_monobit(void)
     }
 
     g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
+    dump_buf_if_failed(buf, sizeof(buf));
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void test_first_byte_runs(void)
     }
 
     g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
+    dump_buf_if_failed(buf.c, sizeof(buf));
 }
 
 int main(int argc, char **argv)
-- 
2.20.1

From: Alex Chen <alex.chen@huawei.com>

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-2-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/imx25_ccm.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx25_ccm.c
+++ b/hw/misc/imx25_ccm.c
@@ -XXX,XX +XXX,XX @@ static const char *imx25_ccm_reg_name(uint32_t reg)
     case IMX25_CCM_LPIMR1_REG:
         return "lpimr1";
     default:
-        sprintf(unknown, "[%d ?]", reg);
+        sprintf(unknown, "[%u ?]", reg);
         return unknown;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev)
         freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ);
     }
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev)
 
     freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV));
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev)
     freq = imx25_ccm_get_mcu_clk(dev)
            / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV));
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev)
 
     freq = imx25_ccm_get_ahb_clk(dev) / 2;
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
         break;
     }
 
-    DPRINTF("Clock = %d) = %d\n", clock, freq);
+    DPRINTF("Clock = %d) = %u\n", clock, freq);
 
     return freq;
 }
-- 
2.20.1

From: Alex Chen <alex.chen@huawei.com>

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-3-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/imx31_ccm.c | 14 +++++++-------
 hw/misc/imx_ccm.c   |  4 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx31_ccm.c
+++ b/hw/misc/imx31_ccm.c
@@ -XXX,XX +XXX,XX @@ static const char *imx31_ccm_reg_name(uint32_t reg)
     case IMX31_CCM_PDR2_REG:
         return "PDR2";
     default:
-        sprintf(unknown, "[%d ?]", reg);
+        sprintf(unknown, "[%u ?]", reg);
         return unknown;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
         freq = CKIH_FREQ;
     }
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
     freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
                             imx31_ccm_get_pll_ref_clk(dev));
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
         freq = imx31_ccm_get_mpll_clk(dev);
     }
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
     freq = imx31_ccm_get_mcu_main_clk(dev)
            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
     freq = imx31_ccm_get_hclk_clk(dev)
            / (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
 
-    DPRINTF("freq = %d\n", freq);
+    DPRINTF("freq = %u\n", freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
         break;
     }
 
-    DPRINTF("Clock = %d) = %d\n", clock, freq);
+    DPRINTF("Clock = %d) = %u\n", clock, freq);
 
     return freq;
 }
diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx_ccm.c
+++ b/hw/misc/imx_ccm.c
@@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
         freq = klass->get_clock_frequency(dev, clock);
     }
 
-    DPRINTF("(clock = %d) = %d\n", clock, freq);
+    DPRINTF("(clock = %d) = %u\n", clock, freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq)
     freq = ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) /
             (mfd * pd)) << 10;
 
-    DPRINTF("(pllreg = 0x%08x, base_freq = %d) = %d\n", pllreg, base_freq,
+    DPRINTF("(pllreg = 0x%08x, base_freq = %u) = %d\n", pllreg, base_freq,
             freq);
 
     return freq;
-- 
2.20.1

From: Alex Chen <alex.chen@huawei.com>

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-4-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/imx6_ccm.c | 20 ++++++++++----------
 hw/misc/imx6_src.c |  2 +-
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx6_ccm.c
+++ b/hw/misc/imx6_ccm.c
@@ -XXX,XX +XXX,XX @@ static const char *imx6_ccm_reg_name(uint32_t reg)
     case CCM_CMEOR:
         return "CMEOR";
     default:
-        sprintf(unknown, "%d ?", reg);
+        sprintf(unknown, "%u ?", reg);
         return unknown;
     }
 }
@@ -XXX,XX +XXX,XX @@ static const char *imx6_analog_reg_name(uint32_t reg)
     case USB_ANALOG_DIGPROG:
         return "USB_ANALOG_DIGPROG";
     default:
-        sprintf(unknown, "%d ?", reg);
+        sprintf(unknown, "%u ?", reg);
         return unknown;
     }
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState *dev)
         freq *= 20;
     }
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMState *dev)
     freq = imx6_analog_get_pll2_clk(dev) * 18
            / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD0_FRAC);
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd2_clk(IMX6CCMState *dev)
     freq = imx6_analog_get_pll2_clk(dev) * 18
            / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD2_FRAC);
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_periph_clk(IMX6CCMState *dev)
         break;
     }
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ahb_clk(IMX6CCMState *dev)
     freq = imx6_analog_get_periph_clk(dev)
            / (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF));
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ipg_clk(IMX6CCMState *dev)
     freq = imx6_ccm_get_ahb_clk(dev)
            / (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF));
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev)
     freq = imx6_ccm_get_ipg_clk(dev)
            / (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF));
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
         break;
     }
 
-    DPRINTF("Clock = %d) = %d\n", clock, freq);
+    DPRINTF("Clock = %d) = %u\n", clock, freq);
 
     return freq;
 }
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx6_src.c
+++ b/hw/misc/imx6_src.c
@@ -XXX,XX +XXX,XX @@ static const char *imx6_src_reg_name(uint32_t reg)
     case SRC_GPR10:
         return "SRC_GPR10";
     default:
-        sprintf(unknown, "%d ?", reg);
+        sprintf(unknown, "%u ?", reg);
         return unknown;
     }
 }
-- 
2.20.1

From: Alex Chen <alex.chen@huawei.com>

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-5-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/imx6ul_ccm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/imx6ul_ccm.c
+++ b/hw/misc/imx6ul_ccm.c
@@ -XXX,XX +XXX,XX @@ static const char *imx6ul_ccm_reg_name(uint32_t reg)
     case CCM_CMEOR:
         return "CMEOR";
     default:
-        sprintf(unknown, "%d ?", reg);
+        sprintf(unknown, "%u ?", reg);
         return unknown;
     }
 }
@@ -XXX,XX +XXX,XX @@ static const char *imx6ul_analog_reg_name(uint32_t reg)
     case USB_ANALOG_DIGPROG:
         return "USB_ANALOG_DIGPROG";
     default:
-        sprintf(unknown, "%d ?", reg);
+        sprintf(unknown, "%u ?", reg);
         return unknown;
     }
 }
-- 
2.20.1

For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the
Private Peripheral Bus range, which includes all of the memory mapped
devices and registers that are part of the CPU itself, including the
NVIC, systick timer, and debug and trace components like the Data
Watchpoint and Trace unit (DWT).  Within this large region, the range
0xe000e000 to 0xe000efff is the System Control Space (NVIC, system
registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure
alias.

The architecture is clear that within the SCS unimplemented registers
should be RES0 for privileged accesses and generate BusFault for
unprivileged accesses, and we currently implement this.

It is less clear about how to handle accesses to unimplemented
regions of the wider PPB.  Unprivileged accesses should definitely
cause BusFaults (R_DQQS), but the behaviour of privileged accesses is
not given as a general rule.  However, the register definitions of
individual registers for components like the DWT all state that they
are RES0 if the relevant component is not implemented, so the
simplest way to provide that is to provide RAZ/WI for the whole range
for privileged accesses.  (The v7M Arm ARM does say that reserved
registers should be UNK/SBZP.)

Expand the container MemoryRegion that the NVIC exposes so that
it covers the whole PPB space. This means:
 * moving the address that the ARMV7M device maps it to down by
   0xe000 bytes
 * moving the off and the offsets within the container of all the
   subregions forward by 0xe000 bytes
 * adding a new default MemoryRegion that covers the whole container
   at a lower priority than anything else and which provides the
   RAZWI/BusFault behaviour

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-2-peter.maydell@linaro.org
---
 include/hw/intc/armv7m_nvic.h |  1 +
 hw/arm/armv7m.c               |  2 +-
 hw/intc/armv7m_nvic.c         | 78 ++++++++++++++++++++++++++++++-----
 3 files changed, 69 insertions(+), 12 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
     MemoryRegion systickmem;
     MemoryRegion systick_ns_mem;
     MemoryRegion container;
+    MemoryRegion defaultmem;
 
     uint32_t num_irq;
     qemu_irq excpout;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(sbd, 0,
                        qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
 
-    memory_region_add_subregion(&s->container, 0xe000e000,
+    memory_region_add_subregion(&s->container, 0xe0000000,
                                 sysbus_mmio_get_region(sbd, 0));
 
     for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
+/*
+ * Unassigned portions of the PPB space are RAZ/WI for privileged
+ * accesses, and fault for non-privileged accesses.
+ */
+static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
+                                    uint64_t *data, unsigned size,
+                                    MemTxAttrs attrs)
+{
+    qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
+                  (uint32_t)addr);
+    if (attrs.user) {
+        return MEMTX_ERROR;
+    }
+    *data = 0;
+    return MEMTX_OK;
+}
+
+static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
+                                     uint64_t value, unsigned size,
+                                     MemTxAttrs attrs)
+{
+    qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
+                  (uint32_t)addr);
+    if (attrs.user) {
+        return MEMTX_ERROR;
+    }
+    return MEMTX_OK;
+}
+
+static const MemoryRegionOps ppb_default_ops = {
+    .read_with_attrs = ppb_default_read,
+    .write_with_attrs = ppb_default_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid.min_access_size = 1,
+    .valid.max_access_size = 8,
+};
+
 static int nvic_post_load(void *opaque, int version_id)
 {
     NVICState *s = opaque;
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
 static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
 {
     NVICState *s = NVIC(dev);
-    int regionlen;
 
     /* The armv7m container object will have set our CPU pointer */
     if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) {
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
                                                   M_REG_S));
     }
 
-    /* The NVIC and System Control Space (SCS) starts at 0xe000e000
+    /*
+     * This device provides a single sysbus memory region which
+     * represents the whole of the "System PPB" space. This is the
+     * range from 0xe0000000 to 0xe00fffff and includes the NVIC,
+     * the System Control Space (system registers), the systick timer,
+     * and for CPUs with the Security extension an NS banked version
+     * of all of these.
+     *
+     * The default behaviour for unimplemented registers/ranges
+     * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
+     * is to RAZ/WI for privileged access and BusFault for non-privileged
+     * access.
+     *
+     * The NVIC and System Control Space (SCS) starts at 0xe000e000
      * and looks like this:
      *  0x004 - ICTR
      *  0x010 - 0xff - systick
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
      * generally code determining which banked register to use should
      * use attrs.secure; code determining actual behaviour of the system
      * should use env->v7m.secure.
+     *
+     * The container covers the whole PPB space. Within it the priority
+     * of overlapping regions is:
+     *  - default region (for RAZ/WI and BusFault) : -1
+     *  - system register regions : 0
+     *  - systick : 1
+     * This is because the systick device is a small block of registers
+     * in the middle of the other system control registers.
      */
-    regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000;
-    memory_region_init(&s->container, OBJECT(s), "nvic", regionlen);
-    /* The system register region goes at the bottom of the priority
-     * stack as it covers the whole page.
-     */
+    memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000);
+    memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
+                          "nvic-default", 0x100000);
+    memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1);
     memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
                           "nvic_sysregs", 0x1000);
-    memory_region_add_subregion(&s->container, 0, &s->sysregmem);
+    memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
 
     memory_region_init_io(&s->systickmem, OBJECT(s),
                           &nvic_systick_ops, s,
                           "nvic_systick", 0xe0);
 
-    memory_region_add_subregion_overlap(&s->container, 0x10,
+    memory_region_add_subregion_overlap(&s->container, 0xe010,
                                         &s->systickmem, 1);
 
     if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
         memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
                               &nvic_sysreg_ns_ops, &s->sysregmem,
                               "nvic_sysregs_ns", 0x1000);
-        memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem);
+        memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
         memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
                               &nvic_sysreg_ns_ops, &s->systickmem,
                               "nvic_systick_ns", 0xe0);
-        memory_region_add_subregion_overlap(&s->container, 0x20010,
+        memory_region_add_subregion_overlap(&s->container, 0x2e010,
                                             &s->systick_ns_mem, 1);
     }
 
-- 
2.20.1

In v8.1M the PXN architecture extension adds a new PXN bit to the
MPU_RLAR registers, which forbids execution of code in the region
from a privileged mode.

This is another feature which is just in the generic "in v8.1M" set
and has no ID register field indicating its presence.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-3-peter.maydell@linaro.org
---
 target/arm/helper.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
     } else {
         uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
         uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
+        bool pxn = false;
+
+        if (arm_feature(env, ARM_FEATURE_V8_1M)) {
+            pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
+        }
 
         if (m_is_system_region(env, address)) {
             /* System space is always execute never */
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
         }
 
         *prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
-        if (*prot && !xn) {
+        if (*prot && !xn && !(pxn && !is_user)) {
             *prot |= PAGE_EXEC;
         }
         /* We don't need to look the attribute up in the MAIR0/MAIR1
-- 
2.20.1

In arm_cpu_realizefn() we check whether the board code disabled EL3
via the has_el3 CPU object property, which we create if the CPU
starts with the ARM_FEATURE_EL3 feature bit.  If it is disabled, then
we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in
the ID_PFR1 and ID_AA64PFR0 registers.

This codepath was incorrectly being taken for M-profile CPUs, which
do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have
the M-profile Security extension and so should have non-zero values
in the ID_PFR1.Security field.

Restrict the handling of the feature flag to A/R-profile cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-4-peter.maydell@linaro.org
---
 target/arm/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         }
     }
 
-    if (!cpu->has_el3) {
+    if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
         /* If the has_el3 CPU property is disabled then we need to disable the
          * feature.
          */
-- 
2.20.1

Implement the v8.1M VSCCLRM insn, which zeros floating point
registers if there is an active floating point context.
This requires support in write_neon_element32() for the MO_32
element size, so add it.

Because we want to use arm_gen_condlabel(), we need to move
the definition of that function up in translate.c so it is
before the #include of translate-vfp.c.inc.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-5-peter.maydell@linaro.org
---
 target/arm/cpu.h               |  9 ++++
 target/arm/m-nocp.decode       |  8 +++-
 target/arm/translate.c         | 21 +++++----
 target/arm/translate-vfp.c.inc | 84 ++++++++++++++++++++++++++++++++++
 4 files changed, 111 insertions(+), 11 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
 }
 
+static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
+{
+    /*
+     * Return true if M-profile state handling insns
+     * (VSCCLRM, CLRM, FPCTX access insns) are implemented
+     */
+    return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
+}
+
 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
 {
     /* Sadly this is encoded differently for A-profile and M-profile */
diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m-nocp.decode
+++ b/target/arm/m-nocp.decode
@@ -XXX,XX +XXX,XX @@
 # If the coprocessor is not present or disabled then we will generate
 # the NOCP exception; otherwise we let the insn through to the main decode.
 
+%vd_dp  22:1 12:4
+%vd_sp  12:4 22:1
+
 &nocp cp
 
 {
   # Special cases which do not take an early NOCP: VLLDM and VLSTM
   VLLDM_VLSTM  1110 1100 001 l:1 rn:4 0000 1010 0000 0000
-  # TODO: VSCCLRM (new in v8.1M) is similar:
-  #VSCCLRM      1110 1100 1-01 1111 ---- 1011 ---- ---0
+  # VSCCLRM (new in v8.1M) is similar:
+  VSCCLRM      1110 1100 1.01 1111 .... 1011 imm:7 0   vd=%vd_dp size=3
+  VSCCLRM      1110 1100 1.01 1111 .... 1010 imm:8     vd=%vd_sp size=2
 
   NOCP         111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp
   NOCP         111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
     a64_translate_init();
 }
 
+/* Generate a label used for skipping this instruction */
+static void arm_gen_condlabel(DisasContext *s)
+{
+    if (!s->condjmp) {
+        s->condlabel = gen_new_label();
+        s->condjmp = 1;
+    }
+}
+
 /* Flags for the disas_set_da_iss info argument:
  * lower bits hold the Rt register number, higher bits are flags.
  */
@@ -XXX,XX +XXX,XX @@ static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
     long off = neon_element_offset(reg, ele, memop);
 
     switch (memop) {
+    case MO_32:
+        tcg_gen_st32_i64(src, cpu_env, off);
+        break;
     case MO_64:
         tcg_gen_st_i64(src, cpu_env, off);
         break;
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
     s->base.is_jmp = DISAS_UPDATE_EXIT;
 }
 
-/* Generate a label used for skipping this instruction */
-static void arm_gen_condlabel(DisasContext *s)
-{
-    if (!s->condjmp) {
-        s->condlabel = gen_new_label();
-        s->condjmp = 1;
-    }
-}
-
 /* Skip this instruction if the ARM condition is false */
 static void arm_skip_unless(DisasContext *s, uint32_t cond)
 {
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
     return true;
 }
 
+static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
+{
+    int btmreg, topreg;
+    TCGv_i64 zero;
+    TCGv_i32 aspen, sfpa;
+
+    if (!dc_isar_feature(aa32_m_sec_state, s)) {
+        /* Before v8.1M, fall through in decode to NOCP check */
+        return false;
+    }
+
+    /* Explicitly UNDEF because this takes precedence over NOCP */
+    if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
+        unallocated_encoding(s);
+        return true;
+    }
+
+    if (!dc_isar_feature(aa32_vfp_simd, s)) {
+        /* NOP if we have neither FP nor MVE */
+        return true;
+    }
+
+    /*
+     * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
+     * active floating point context so we must NOP (without doing
+     * any lazy state preservation or the NOCP check).
+     */
+    aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
+    sfpa = load_cpu_field(v7m.control[M_REG_S]);
+    tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
+    tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
+    tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
+    tcg_gen_or_i32(sfpa, sfpa, aspen);
+    arm_gen_condlabel(s);
+    tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
+
+    if (s->fp_excp_el != 0) {
+        gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+                           syn_uncategorized(), s->fp_excp_el);
+        return true;
+    }
+
+    topreg = a->vd + a->imm - 1;
+    btmreg = a->vd;
+
+    /* Convert to Sreg numbers if the insn specified in Dregs */
+    if (a->size == 3) {
+        topreg = topreg * 2 + 1;
+        btmreg *= 2;
+    }
+
+    if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
+        /* UNPREDICTABLE: we choose to undef */
+        unallocated_encoding(s);
+        return true;
+    }
+
+    /* Silently ignore requests to clear D16-D31 if they don't exist */
+    if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
+        topreg = 31;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /* Zero the Sregs from btmreg to topreg inclusive. */
+    zero = tcg_const_i64(0);
+    if (btmreg & 1) {
+        write_neon_element64(zero, btmreg >> 1, 1, MO_32);
+        btmreg++;
+    }
+    for (; btmreg + 1 <= topreg; btmreg += 2) {
+        write_neon_element64(zero, btmreg >> 1, 0, MO_64);
+    }
+    if (btmreg == topreg) {
+        write_neon_element64(zero, btmreg >> 1, 0, MO_32);
+        btmreg++;
+    }
+    assert(btmreg == topreg + 1);
+    /* TODO: when MVE is implemented, zero VPR here */
+    return true;
+}
+
 static bool trans_NOCP(DisasContext *s, arg_nocp *a)
 {
     /*
-- 
2.20.1

In v8.1M the new CLRM instruction allows zeroing an arbitrary set of
the general-purpose registers and APSR.  Implement this.

The encoding is a subset of the LDMIA T2 encoding, using what would
be Rn=0b1111 (which UNDEFs for LDMIA).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-6-peter.maydell@linaro.org
---
 target/arm/t32.decode  |  6 +++++-
 target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ UXTAB            1111 1010 0101 .... 1111 .... 10.. ....      @rrr_rot
 
 STM_t32          1110 1000 10.0 .... ................         @ldstm i=1 b=0
 STM_t32          1110 1001 00.0 .... ................         @ldstm i=0 b=1
-LDM_t32          1110 1000 10.1 .... ................         @ldstm i=1 b=0
+{
+  # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding
+  CLRM           1110 1000 1001 1111 list:16
+  LDM_t32        1110 1000 10.1 .... ................         @ldstm i=1 b=0
+}
 LDM_t32          1110 1001 00.1 .... ................         @ldstm i=0 b=1
 
 &rfe             !extern rn w pu
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
     return do_ldm(s, a, 1);
 }
 
+static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
+{
+    int i;
+    TCGv_i32 zero;
+
+    if (!dc_isar_feature(aa32_m_sec_state, s)) {
+        return false;
+    }
+
+    if (extract32(a->list, 13, 1)) {
+        return false;
+    }
+
+    if (!a->list) {
+        /* UNPREDICTABLE; we choose to UNDEF */
+        return false;
+    }
+
+    zero = tcg_const_i32(0);
+    for (i = 0; i < 15; i++) {
+        if (extract32(a->list, i, 1)) {
+            /* Clear R[i] */
+            tcg_gen_mov_i32(cpu_R[i], zero);
+        }
+    }
+    if (extract32(a->list, 15, 1)) {
+        /*
+         * Clear APSR (by calling the MSR helper with the same argument
+         * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
+         */
+        TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
+        gen_helper_v7m_msr(cpu_env, maskreg, zero);
+        tcg_temp_free_i32(maskreg);
+    }
+    tcg_temp_free_i32(zero);
+    return true;
+}
+
 /*
  * Branch, branch with link
  */
-- 
2.20.1

For M-profile before v8.1M, the only valid register for VMSR/VMRS is
the FPSCR.  We have a comment that states this, but the actual logic
to forbid accesses for any other register value is missing, so we
would end up with A-profile style behaviour.  Add the missing check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-7-peter.maydell@linaro.org
---
 target/arm/translate-vfp.c.inc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
          * Accesses to R15 are UNPREDICTABLE; we choose to undef.
          * (FPSCR -> r15 is a special case which writes to the PSR flags.)
          */
-        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
+        if (a->reg != ARM_VFP_FPSCR) {
+            return false;
+        }
+        if (a->rt == 15 && !a->l) {
             return false;
         }
     }
-- 
2.20.1

Currently M-profile borrows the A-profile code for VMSR and VMRS
(access to the FP system registers), because all it needs to support
is the FPSCR.  In v8.1M things become significantly more complicated
in two ways:

* there are several new FP system registers; some have side effects
   on read, and one (FPCXT_NS) needs to avoid the usual
   vfp_access_check() and the "only if FPU implemented" check

* all sysregs are now accessible both by VMRS/VMSR (which
   reads/writes a general purpose register) and also by VLDR/VSTR
   (which reads/writes them directly to memory)

Refactor the structure of how we handle VMSR/VMRS to cope with this:

* keep the M-profile code entirely separate from the A-profile code

* abstract out the "read or write the general purpose register" part
   of the code into a loadfn or storefn function pointer, so we can
   reuse it for VLDR/VSTR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-8-peter.maydell@linaro.org
---
 target/arm/cpu.h               |   3 +
 target/arm/translate-vfp.c.inc | 182 ++++++++++++++++++++++++++++++---
 2 files changed, 171 insertions(+), 14 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode {
 #define ARM_VFP_FPINST  9
 #define ARM_VFP_FPINST2 10
 
+/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
+#define QEMU_VFP_FPSCR_NZCV 0xffff
+
 /* iwMMXt coprocessor control registers.  */
 #define ARM_IWMMXT_wCID  0
 #define ARM_IWMMXT_wCon  1
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
     return true;
 }
 
+/*
+ * M-profile provides two different sets of instructions that can
+ * access floating point system registers: VMSR/VMRS (which move
+ * to/from a general purpose register) and VLDR/VSTR sysreg (which
+ * move directly to/from memory). In some cases there are also side
+ * effects which must happen after any write to memory (which could
+ * cause an exception). So we implement the common logic for the
+ * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(),
+ * which take pointers to callback functions which will perform the
+ * actual "read/write general purpose register" and "read/write
+ * memory" operations.
+ */
+
+/*
+ * Emit code to store the sysreg to its final destination; frees the
+ * TCG temp 'value' it is passed.
+ */
+typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value);
+/*
+ * Emit code to load the value to be copied to the sysreg; returns
+ * a new TCG temporary
+ */
+typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque);
+
+/* Common decode/access checks for fp sysreg read/write */
+typedef enum FPSysRegCheckResult {
+    FPSysRegCheckFailed, /* caller should return false */
+    FPSysRegCheckDone, /* caller should return true */
+    FPSysRegCheckContinue, /* caller should continue generating code */
+} FPSysRegCheckResult;
+
+static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
+{
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return FPSysRegCheckFailed;
+    }
+
+    switch (regno) {
+    case ARM_VFP_FPSCR:
+    case QEMU_VFP_FPSCR_NZCV:
+        break;
+    default:
+        return FPSysRegCheckFailed;
+    }
+
+    if (!vfp_access_check(s)) {
+        return FPSysRegCheckDone;
+    }
+
+    return FPSysRegCheckContinue;
+}
+
+static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
+
+                                  fp_sysreg_loadfn *loadfn,
+                                 void *opaque)
+{
+    /* Do a write to an M-profile floating point system register */
+    TCGv_i32 tmp;
+
+    switch (fp_sysreg_checks(s, regno)) {
+    case FPSysRegCheckFailed:
+        return false;
+    case FPSysRegCheckDone:
+        return true;
+    case FPSysRegCheckContinue:
+        break;
+    }
+
+    switch (regno) {
+    case ARM_VFP_FPSCR:
+        tmp = loadfn(s, opaque);
+        gen_helper_vfp_set_fpscr(cpu_env, tmp);
+        tcg_temp_free_i32(tmp);
+        gen_lookup_tb(s);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    return true;
+}
+
+static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
+                                fp_sysreg_storefn *storefn,
+                                void *opaque)
+{
+    /* Do a read from an M-profile floating point system register */
+    TCGv_i32 tmp;
+
+    switch (fp_sysreg_checks(s, regno)) {
+    case FPSysRegCheckFailed:
+        return false;
+    case FPSysRegCheckDone:
+        return true;
+    case FPSysRegCheckContinue:
+        break;
+    }
+
+    switch (regno) {
+    case ARM_VFP_FPSCR:
+        tmp = tcg_temp_new_i32();
+        gen_helper_vfp_get_fpscr(tmp, cpu_env);
+        storefn(s, opaque, tmp);
+        break;
+    case QEMU_VFP_FPSCR_NZCV:
+        /*
+         * Read just NZCV; this is a special case to avoid the
+         * helper call for the "VMRS to CPSR.NZCV" insn.
+         */
+        tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
+        tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
+        storefn(s, opaque, tmp);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    return true;
+}
+
+static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value)
+{
+    arg_VMSR_VMRS *a = opaque;
+
+    if (a->rt == 15) {
+        /* Set the 4 flag bits in the CPSR */
+        gen_set_nzcv(value);
+        tcg_temp_free_i32(value);
+    } else {
+        store_reg(s, a->rt, value);
+    }
+}
+
+static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque)
+{
+    arg_VMSR_VMRS *a = opaque;
+
+    return load_reg(s, a->rt);
+}
+
+static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
+{
+    /*
+     * Accesses to R15 are UNPREDICTABLE; we choose to undef.
+     * FPSCR -> r15 is a special case which writes to the PSR flags;
+     * set a->reg to a special value to tell gen_M_fp_sysreg_read()
+     * we only care about the top 4 bits of FPSCR there.
+     */
+    if (a->rt == 15) {
+        if (a->l && a->reg == ARM_VFP_FPSCR) {
+            a->reg = QEMU_VFP_FPSCR_NZCV;
+        } else {
+            return false;
+        }
+    }
+
+    if (a->l) {
+        /* VMRS, move FP system register to gp register */
+        return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a);
+    } else {
+        /* VMSR, move gp register to FP system register */
+        return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a);
+    }
+}
+
 static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
 {
     TCGv_i32 tmp;
     bool ignore_vfp_enabled = false;
 
-    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
-        return false;
+    if (arm_dc_feature(s, ARM_FEATURE_M)) {
+        return gen_M_VMSR_VMRS(s, a);
     }
 
-    if (arm_dc_feature(s, ARM_FEATURE_M)) {
-        /*
-         * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
-         * Accesses to R15 are UNPREDICTABLE; we choose to undef.
-         * (FPSCR -> r15 is a special case which writes to the PSR flags.)
-         */
-        if (a->reg != ARM_VFP_FPSCR) {
-            return false;
-        }
-        if (a->rt == 15 && !a->l) {
-            return false;
-        }
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
     }
 
     switch (a->reg) {
-- 
2.20.1

The constant-expander functions like negate, plus_2, etc, are
generally useful; move them up in translate.c so we can use them in
the VFP/Neon decoders as well as in the A32/T32/T16 decoders.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-9-peter.maydell@linaro.org
---
 target/arm/translate.c | 46 +++++++++++++++++++++++-------------------
 1 file changed, 25 insertions(+), 21 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void arm_gen_condlabel(DisasContext *s)
     }
 }
 
+/*
+ * Constant expanders for the decoders.
+ */
+
+static int negate(DisasContext *s, int x)
+{
+    return -x;
+}
+
+static int plus_2(DisasContext *s, int x)
+{
+    return x + 2;
+}
+
+static int times_2(DisasContext *s, int x)
+{
+    return x * 2;
+}
+
+static int times_4(DisasContext *s, int x)
+{
+    return x * 4;
+}
+
 /* Flags for the disas_set_da_iss info argument:
  * lower bits hold the Rt register number, higher bits are flags.
  */
@@ -XXX,XX +XXX,XX @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
 
 
 /*
- * Constant expanders for the decoders.
+ * Constant expanders used by T16/T32 decode
  */
 
-static int negate(DisasContext *s, int x)
-{
-    return -x;
-}
-
-static int plus_2(DisasContext *s, int x)
-{
-    return x + 2;
-}
-
-static int times_2(DisasContext *s, int x)
-{
-    return x * 2;
-}
-
-static int times_4(DisasContext *s, int x)
-{
-    return x * 4;
-}
-
 /* Return only the rotation part of T32ExpandImm.  */
 static int t32_expandimm_rot(DisasContext *s, int x)
 {
-- 
2.20.1

Implement the new-in-v8.1M VLDR/VSTR variants which directly
read or write FP system registers to memory.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-10-peter.maydell@linaro.org
---
 target/arm/vfp.decode          | 14 ++++++
 target/arm/translate-vfp.c.inc | 91 ++++++++++++++++++++++++++++++++++
 2 files changed, 105 insertions(+)

diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -XXX,XX +XXX,XX @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8      vd=%vd_sp
 VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8      vd=%vd_sp
 VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8      vd=%vd_dp
 
+# M-profile VLDR/VSTR to sysreg
+%vldr_sysreg 22:1 13:3
+%imm7_0x4 0:7 !function=times_4
+
+&vldr_sysreg rn reg imm a w p
+@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \
+             reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg
+
+# P=0 W=0 is SEE "Related encodings", so split into two patterns
+VLDR_sysreg  ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1
+VLDR_sysreg  ---- 110 0 . . 1   1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
+VSTR_sysreg  ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1
+VSTR_sysreg  ---- 110 0 . . 1   0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
+
 # We split the load/store multiple up into two patterns to avoid
 # overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
 # grouping:
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
     return true;
 }
 
+static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value)
+{
+    arg_vldr_sysreg *a = opaque;
+    uint32_t offset = a->imm;
+    TCGv_i32 addr;
+
+    if (!a->a) {
+        offset = - offset;
+    }
+
+    addr = load_reg(s, a->rn);
+    if (a->p) {
+        tcg_gen_addi_i32(addr, addr, offset);
+    }
+
+    if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+        gen_helper_v8m_stackcheck(cpu_env, addr);
+    }
+
+    gen_aa32_st_i32(s, value, addr, get_mem_index(s),
+                    MO_UL | MO_ALIGN | s->be_data);
+    tcg_temp_free_i32(value);
+
+    if (a->w) {
+        /* writeback */
+        if (!a->p) {
+            tcg_gen_addi_i32(addr, addr, offset);
+        }
+        store_reg(s, a->rn, addr);
+    } else {
+        tcg_temp_free_i32(addr);
+    }
+}
+
+static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque)
+{
+    arg_vldr_sysreg *a = opaque;
+    uint32_t offset = a->imm;
+    TCGv_i32 addr;
+    TCGv_i32 value = tcg_temp_new_i32();
+
+    if (!a->a) {
+        offset = - offset;
+    }
+
+    addr = load_reg(s, a->rn);
+    if (a->p) {
+        tcg_gen_addi_i32(addr, addr, offset);
+    }
+
+    if (s->v8m_stackcheck && a->rn == 13 && a->w) {
+        gen_helper_v8m_stackcheck(cpu_env, addr);
+    }
+
+    gen_aa32_ld_i32(s, value, addr, get_mem_index(s),
+                    MO_UL | MO_ALIGN | s->be_data);
+
+    if (a->w) {
+        /* writeback */
+        if (!a->p) {
+            tcg_gen_addi_i32(addr, addr, offset);
+        }
+        store_reg(s, a->rn, addr);
+    } else {
+        tcg_temp_free_i32(addr);
+    }
+    return value;
+}
+
+static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
+{
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+        return false;
+    }
+    if (a->rn == 15) {
+        return false;
+    }
+    return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a);
+}
+
+static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
+{
+    if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+        return false;
+    }
+    if (a->rn == 15) {
+        return false;
+    }
+    return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a);
+}
+
 static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
 {
     TCGv_i32 tmp;
-- 
2.20.1

v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves
like the existing FPSCR, except that it reads and writes only bits
[31:27] of the FPSCR (the N, Z, C, V and QC flag bits).  (Unlike the
FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not
permitted.)

Implement the register.  Since we don't yet implement MVE, we handle
the QC bit as RES0, with todo comments for where we will need to add
support later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-11-peter.maydell@linaro.org
---
 target/arm/cpu.h               | 13 +++++++++++++
 target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
 #define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
 #define FPCR_QC     (1 << 27)   /* Cumulative saturation bit */
+#define FPCR_V      (1 << 28)   /* FP overflow flag */
+#define FPCR_C      (1 << 29)   /* FP carry flag */
+#define FPCR_Z      (1 << 30)   /* FP zero flag */
+#define FPCR_N      (1 << 31)   /* FP negative flag */
+
+#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
+#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
 
 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
 {
@@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode {
 #define ARM_VFP_FPEXC   8
 #define ARM_VFP_FPINST  9
 #define ARM_VFP_FPINST2 10
+/* These ones are M-profile only */
+#define ARM_VFP_FPSCR_NZCVQC 2
+#define ARM_VFP_VPR 12
+#define ARM_VFP_P0 13
+#define ARM_VFP_FPCXT_NS 14
+#define ARM_VFP_FPCXT_S 15
 
 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
 #define QEMU_VFP_FPSCR_NZCV 0xffff
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
     case ARM_VFP_FPSCR:
     case QEMU_VFP_FPSCR_NZCV:
         break;
+    case ARM_VFP_FPSCR_NZCVQC:
+        if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+            return false;
+        }
+        break;
     default:
         return FPSysRegCheckFailed;
     }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
         tcg_temp_free_i32(tmp);
         gen_lookup_tb(s);
         break;
+    case ARM_VFP_FPSCR_NZCVQC:
+    {
+        TCGv_i32 fpscr;
+        tmp = loadfn(s, opaque);
+        /*
+         * TODO: when we implement MVE, write the QC bit.
+         * For non-MVE, QC is RES0.
+         */
+        tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
+        fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
+        tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
+        tcg_gen_or_i32(fpscr, fpscr, tmp);
+        store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
+        tcg_temp_free_i32(tmp);
+        break;
+    }
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
         gen_helper_vfp_get_fpscr(tmp, cpu_env);
         storefn(s, opaque, tmp);
         break;
+    case ARM_VFP_FPSCR_NZCVQC:
+        /*
+         * TODO: MVE has a QC bit, which we probably won't store
+         * in the xregs[] field. For non-MVE, where QC is RES0,
+         * we can just fall through to the FPSCR_NZCV case.
+         */
     case QEMU_VFP_FPSCR_NZCV:
         /*
          * Read just NZCV; this is a special case to avoid the
-- 
2.20.1

We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
in the previous commit; use it in a couple of places in existing code,
where we're masking out everything except NZCV for the "load to Rt=15
sets CPSR.NZCV" special case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-12-peter.maydell@linaro.org
---
 target/arm/translate-vfp.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Factor out the code which handles M-profile lazy FP state preservation
from full_vfp_access_check(); accesses to the FPCXT_NS register are
a special case which need to do just this part (corresponding in the
pseudocode to the PreserveFPState() function), and not the full
set of actions matching the pseudocode ExecuteFPCheck() which
normal FP instructions need to do.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201119215617.29887-13-peter.maydell@linaro.org
---
 target/arm/translate-vfp.c.inc | 45 ++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 18 deletions(-)

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top)
     return offs;
 }
 
+/*
+ * Generate code for M-profile lazy FP state preservation if needed;
+ * this corresponds to the pseudocode PreserveFPState() function.
+ */
+static void gen_preserve_fp_state(DisasContext *s)
+{
+    if (s->v7m_lspact) {
+        /*
+         * Lazy state saving affects external memory and also the NVIC,
+         * so we must mark it as an IO operation for icount (and cause
+         * this to be the last insn in the TB).
+         */
+        if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
+            s->base.is_jmp = DISAS_UPDATE_EXIT;
+            gen_io_start();
+        }
+        gen_helper_v7m_preserve_fp_state(cpu_env);
+        /*
+         * If the preserve_fp_state helper doesn't throw an exception
+         * then it will clear LSPACT; we don't need to repeat this for
+         * any further FP insns in this TB.
+         */
+        s->v7m_lspact = false;
+    }
+}
+
 /*
  * Check that VFP access is enabled. If it is, do the necessary
  * M-profile lazy-FP handling and then return true.
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
         /* Handle M-profile lazy FP state mechanics */
 
         /* Trigger lazy-state preservation if necessary */
-        if (s->v7m_lspact) {
-            /*
-             * Lazy state saving affects external memory and also the NVIC,
-             * so we must mark it as an IO operation for icount (and cause
-             * this to be the last insn in the TB).
-             */
-            if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
-                s->base.is_jmp = DISAS_UPDATE_EXIT;
-                gen_io_start();
-            }
-            gen_helper_v7m_preserve_fp_state(cpu_env);
-            /*
-             * If the preserve_fp_state helper doesn't throw an exception
-             * then it will clear LSPACT; we don't need to repeat this for
-             * any further FP insns in this TB.
-             */
-            s->v7m_lspact = false;
-        }
+        gen_preserve_fp_state(s);
 
         /* Update ownership of FP context: set FPCCR.S to match current state */
         if (s->v8m_fpccr_s_wrong) {
-- 
2.20.1

Implement the new-in-v8.1M FPCXT_S floating point system register.
This is for saving and restoring the secure floating point context,
and it reads and writes bits [27:0] from the FPSCR and the
CONTROL.SFPA bit in bit [31].

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-14-peter.maydell@linaro.org
---
 target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
             return false;
         }
         break;
+    case ARM_VFP_FPCXT_S:
+        if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+            return false;
+        }
+        if (!s->v8m_secure) {
+            return false;
+        }
+        break;
     default:
         return FPSysRegCheckFailed;
     }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
         tcg_temp_free_i32(tmp);
         break;
     }
+    case ARM_VFP_FPCXT_S:
+    {
+        TCGv_i32 sfpa, control, fpscr;
+        /* Set FPSCR[27:0] and CONTROL.SFPA from value */
+        tmp = loadfn(s, opaque);
+        sfpa = tcg_temp_new_i32();
+        tcg_gen_shri_i32(sfpa, tmp, 31);
+        control = load_cpu_field(v7m.control[M_REG_S]);
+        tcg_gen_deposit_i32(control, control, sfpa,
+                            R_V7M_CONTROL_SFPA_SHIFT, 1);
+        store_cpu_field(control, v7m.control[M_REG_S]);
+        fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
+        tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK);
+        tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
+        tcg_gen_or_i32(fpscr, fpscr, tmp);
+        store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
+        tcg_temp_free_i32(tmp);
+        tcg_temp_free_i32(sfpa);
+        break;
+    }
     default:
         g_assert_not_reached();
     }
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
         tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
         storefn(s, opaque, tmp);
         break;
+    case ARM_VFP_FPCXT_S:
+    {
+        TCGv_i32 control, sfpa, fpscr;
+        /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
+        tmp = tcg_temp_new_i32();
+        sfpa = tcg_temp_new_i32();
+        gen_helper_vfp_get_fpscr(tmp, cpu_env);
+        tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
+        control = load_cpu_field(v7m.control[M_REG_S]);
+        tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
+        tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
+        tcg_gen_or_i32(tmp, tmp, sfpa);
+        tcg_temp_free_i32(sfpa);
+        /*
+         * Store result before updating FPSCR etc, in case
+         * it is a memory write which causes an exception.
+         */
+        storefn(s, opaque, tmp);
+        /*
+         * Now we must reset FPSCR from FPDSCR_NS, and clear
+         * CONTROL.SFPA; so we'll end the TB here.
+         */
+        tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
+        store_cpu_field(control, v7m.control[M_REG_S]);
+        fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
+        gen_helper_vfp_set_fpscr(cpu_env, fpscr);
+        tcg_temp_free_i32(fpscr);
+        gen_lookup_tb(s);
+        break;
+    }
     default:
         g_assert_not_reached();
     }
-- 
2.20.1

The FPDSCR register has a similar layout to the FPSCR.  In v8.1M it
gains new fields FZ16 (if half-precision floating point is supported)
and LTPSIZE (always reads as 4).  Update the reset value and the code
that handles writes to this register accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
---
 target/arm/cpu.h      | 5 +++++
 hw/intc/armv7m_nvic.c | 9 ++++++++-
 target/arm/cpu.c      | 3 +++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 #define FPCR_IXE    (1 << 12)   /* Inexact exception trap enable */
 #define FPCR_IDE    (1 << 15)   /* Input Denormal exception trap enable */
 #define FPCR_FZ16   (1 << 19)   /* ARMv8.2+, FP16 flush-to-zero */
+#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
 #define FPCR_FZ     (1 << 24)   /* Flush-to-zero enable bit */
 #define FPCR_DN     (1 << 25)   /* Default NaN enable bit */
+#define FPCR_AHP    (1 << 26)   /* Alternative half-precision */
 #define FPCR_QC     (1 << 27)   /* Cumulative saturation bit */
 #define FPCR_V      (1 << 28)   /* FP overflow flag */
 #define FPCR_C      (1 << 29)   /* FP carry flag */
 #define FPCR_Z      (1 << 30)   /* FP zero flag */
 #define FPCR_N      (1 << 31)   /* FP negative flag */
 
+#define FPCR_LTPSIZE_SHIFT 16   /* LTPSIZE, M-profile only */
+#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
+
 #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
 #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
 
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
         break;
     case 0xf3c: /* FPDSCR */
         if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
-            value &= 0x07c00000;
+            uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK;
+            if (cpu_isar_feature(any_fp16, cpu)) {
+                mask |= FPCR_FZ16;
+            }
+            value &= mask;
+            if (cpu_isar_feature(aa32_lob, cpu)) {
+                value |= 4 << FPCR_LTPSIZE_SHIFT;
+            }
             cpu->env.v7m.fpdscr[attrs.secure] = value;
         }
         break;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
              * always reset to 4.
              */
             env->v7m.ltpsize = 4;
+            /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
+            env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
+            env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
         }
 
         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
-- 
2.20.1

In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR
are zeroed for an exception taken to Non-secure state; for an
exception taken to Secure state they become UNKNOWN, and we chose to
leave them at their previous values.

In v8.1M the behaviour is specified more tightly and these registers
are always zeroed regardless of the security state that the exception
targets (see rule R_KPZV).  Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-17-peter.maydell@linaro.org
---
 target/arm/m_helper.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
          * Clear registers if necessary to prevent non-secure exception
          * code being able to see register values from secure code.
          * Where register values become architecturally UNKNOWN we leave
-         * them with their previous values.
+         * them with their previous values. v8.1M is tighter than v8.0M
+         * here and always zeroes the caller-saved registers regardless
+         * of the security state the exception is targeting.
          */
         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
-            if (!targets_secure) {
+            if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) {
                 /*
                  * Always clear the caller-saved registers (they have been
                  * pushed to the stack earlier in v7m_push_stack()).
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
                  * v7m_push_callee_stack()).
                  */
                 int i;
+                /*
+                 * r4..r11 are callee-saves, zero only if background
+                 * state was Secure (EXCRET.S == 1) and exception
+                 * targets Non-secure state
+                 */
+                bool zero_callee_saves = !targets_secure &&
+                    (lr & R_V7M_EXCRET_S_MASK);
 
                 for (i = 0; i < 13; i++) {
-                    /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
-                    if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) {
+                    if (i < 4 || i > 11 || zero_callee_saves) {
                         env->regs[i] = 0;
                     }
                 }
-- 
2.20.1

In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule
R_LLRP).  (In previous versions of the architecture this was either
required or IMPDEF.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-18-peter.maydell@linaro.org
---
 target/arm/m_helper.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ load_fail:
      * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
      * secure); otherwise it targets the same security state as the
      * underlying exception.
+     * In v8.1M HardFaults from vector table fetch fails don't set FORCED.
      */
     if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
         exc_secure = true;
     }
-    env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
+    env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK;
+    if (!arm_feature(env, ARM_FEATURE_V8_1M)) {
+        env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
+    }
     armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
     return false;
 }
-- 
2.20.1

In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc
and is a read-only IMPDEF register providing implementation specific
minor revision information, like the v8A REVIDR_EL1. Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         }
         return val;
     }
+    case 0xcfc:
+        if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) {
+            goto bad_offset;
+        }
+        return cpu->revidr;
     case 0xd00: /* CPUID Base.  */
         return cpu->midr;
     case 0xd04: /* Interrupt Control State (ICSR) */
-- 
2.20.1

In v8.1M a new exception return check is added which may cause a NOCP
UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR
we must check whether access to CP10 from the Security state of the
returning exception is disabled; if it is then we must take a fault.

(Note that for our implementation CPPWR is always RAZ/WI and so can
never cause CP10 accesses to fail.)

The other v8.1M change to this register-clearing code is that if MVE
is implemented VPR must also be cleared, so add a TODO comment to
that effect.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-20-peter.maydell@linaro.org
---
 target/arm/m_helper.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
             v7m_exception_taken(cpu, excret, true, false);
             return;
         } else {
-            /* Clear s0..s15 and FPSCR */
+            if (arm_feature(env, ARM_FEATURE_V8_1M)) {
+                /* v8.1M adds this NOCP check */
+                bool nsacr_pass = exc_secure ||
+                    extract32(env->v7m.nsacr, 10, 1);
+                bool cpacr_pass = v7m_cpacr_pass(env, exc_secure, true);
+                if (!nsacr_pass) {
+                    armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true);
+                    env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK;
+                    qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
+                        "stackframe: NSACR prevents clearing FPU registers\n");
+                    v7m_exception_taken(cpu, excret, true, false);
+                } else if (!cpacr_pass) {
+                    armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
+                                            exc_secure);
+                    env->v7m.cfsr[exc_secure] |= R_V7M_CFSR_NOCP_MASK;
+                    qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
+                        "stackframe: CPACR prevents clearing FPU registers\n");
+                    v7m_exception_taken(cpu, excret, true, false);
+                }
+            }
+            /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemented */
             int i;
 
             for (i = 0; i < 16; i += 2) {
-- 
2.20.1

v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set).
The only difference is that:
 * the old T1 encodings UNDEF if the implementation implements 32
   Dregs (this is currently architecturally impossible for M-profile)
 * the new T2 encodings have the implementation-defined option to
   read from memory (discarding the data) or write UNKNOWN values to
   memory for the stack slots that would be D16-D31

We choose not to make those accesses, so for us the two
instructions behave identically assuming they don't UNDEF.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-21-peter.maydell@linaro.org
---
 target/arm/m-nocp.decode       |  2 +-
 target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m-nocp.decode
+++ b/target/arm/m-nocp.decode
@@ -XXX,XX +XXX,XX @@
 
 {
   # Special cases which do not take an early NOCP: VLLDM and VLSTM
-  VLLDM_VLSTM  1110 1100 001 l:1 rn:4 0000 1010 0000 0000
+  VLLDM_VLSTM  1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000
   # VSCCLRM (new in v8.1M) is similar:
   VSCCLRM      1110 1100 1.01 1111 .... 1011 imm:7 0   vd=%vd_dp size=3
   VSCCLRM      1110 1100 1.01 1111 .... 1010 imm:8     vd=%vd_sp size=2
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
         !arm_dc_feature(s, ARM_FEATURE_V8)) {
         return false;
     }
+
+    if (a->op) {
+        /*
+         * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
+         * to take the IMPDEF option to make memory accesses to the stack
+         * slots that correspond to the D16-D31 registers (discarding
+         * read data and writing UNKNOWN values), so for us the T2
+         * encoding behaves identically to the T1 encoding.
+         */
+        if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
+            return false;
+        }
+    } else {
+        /*
+         * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
+         * This is currently architecturally impossible, but we add the
+         * check to stay in line with the pseudocode. Note that we must
+         * emit code for the UNDEF so it takes precedence over the NOCP.
+         */
+        if (dc_isar_feature(aa32_simd_r32, s)) {
+            unallocated_encoding(s);
+            return true;
+        }
+    }
+
     /*
      * If not secure, UNDEF. We must emit code for this
      * rather than returning false so that this takes
-- 
2.20.1

v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
This bit is not banked, and is always RAZ/WI to Non-secure code.
Adjust the code for handling CCR reads and writes to handle this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
---
 target/arm/cpu.h      |  2 ++
 hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++--------
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
 FIELD(V7M_CCR, DC, 16, 1)
 FIELD(V7M_CCR, IC, 17, 1)
 FIELD(V7M_CCR, BP, 18, 1)
+FIELD(V7M_CCR, LOB, 19, 1)
+FIELD(V7M_CCR, TRD, 20, 1)
 
 /* V7M SCR bits */
 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         }
         return cpu->env.v7m.scr[attrs.secure];
     case 0xd14: /* Configuration Control.  */
-        /* The BFHFNMIGN bit is the only non-banked bit; we
-         * keep it in the non-secure copy of the register.
+        /*
+         * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register)
+         * and TRD (stored in the S copy of the register)
          */
         val = cpu->env.v7m.ccr[attrs.secure];
         val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
         cpu->env.v7m.scr[attrs.secure] = value;
         break;
     case 0xd14: /* Configuration Control.  */
+    {
+        uint32_t mask;
+
         if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
             goto bad_offset;
         }
 
         /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
-        value &= (R_V7M_CCR_STKALIGN_MASK |
-                  R_V7M_CCR_BFHFNMIGN_MASK |
-                  R_V7M_CCR_DIV_0_TRP_MASK |
-                  R_V7M_CCR_UNALIGN_TRP_MASK |
-                  R_V7M_CCR_USERSETMPEND_MASK |
-                  R_V7M_CCR_NONBASETHRDENA_MASK);
+        mask = R_V7M_CCR_STKALIGN_MASK |
+            R_V7M_CCR_BFHFNMIGN_MASK |
+            R_V7M_CCR_DIV_0_TRP_MASK |
+            R_V7M_CCR_UNALIGN_TRP_MASK |
+            R_V7M_CCR_USERSETMPEND_MASK |
+            R_V7M_CCR_NONBASETHRDENA_MASK;
+        if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) {
+            /* TRD is always RAZ/WI from NS */
+            mask |= R_V7M_CCR_TRD_MASK;
+        }
+        value &= mask;
 
         if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
             /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
 
         cpu->env.v7m.ccr[attrs.secure] = value;
         break;
+    }
     case 0xd24: /* System Handler Control and State (SHCSR) */
         if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
             goto bad_offset;
-- 
2.20.1

v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
Add the code in the SG insn implementation for the new behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-24-peter.maydell@linaro.org
---
 target/arm/m_helper.c | 86 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 86 insertions(+)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
     return true;
 }
 
+static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
+                                   uint32_t addr, uint32_t *spdata)
+{
+    /*
+     * Read a word of data from the stack for the SG instruction,
+     * writing the value into *spdata. If the load succeeds, return
+     * true; otherwise pend an appropriate exception and return false.
+     * (We can't use data load helpers here that throw an exception
+     * because of the context we're called in, which is halfway through
+     * arm_v7m_cpu_do_interrupt().)
+     */
+    CPUState *cs = CPU(cpu);
+    CPUARMState *env = &cpu->env;
+    MemTxAttrs attrs = {};
+    MemTxResult txres;
+    target_ulong page_size;
+    hwaddr physaddr;
+    int prot;
+    ARMMMUFaultInfo fi = {};
+    ARMCacheAttrs cacheattrs = {};
+    uint32_t value;
+
+    if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
+                      &attrs, &prot, &page_size, &fi, &cacheattrs)) {
+        /* MPU/SAU lookup failed */
+        if (fi.type == ARMFault_QEMU_SFault) {
+            qemu_log_mask(CPU_LOG_INT,
+                          "...SecureFault during stack word read\n");
+            env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK;
+            env->v7m.sfar = addr;
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
+        } else {
+            qemu_log_mask(CPU_LOG_INT,
+                          "...MemManageFault during stack word read\n");
+            env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_DACCVIOL_MASK |
+                R_V7M_CFSR_MMARVALID_MASK;
+            env->v7m.mmfar[M_REG_S] = addr;
+            armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false);
+        }
+        return false;
+    }
+    value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
+                              attrs, &txres);
+    if (txres != MEMTX_OK) {
+        /* BusFault trying to read the data */
+        qemu_log_mask(CPU_LOG_INT,
+                      "...BusFault during stack word read\n");
+        env->v7m.cfsr[M_REG_NS] |=
+            (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
+        env->v7m.bfar = addr;
+        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
+        return false;
+    }
+
+    *spdata = value;
+    return true;
+}
+
 static bool v7m_handle_execute_nsc(ARMCPU *cpu)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
      */
     qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
                   ", executing it\n", env->regs[15]);
+
+    if (cpu_isar_feature(aa32_m_sec_state, cpu) &&
+        !arm_v7m_is_handler_mode(env)) {
+        /*
+         * v8.1M exception stack frame integrity check. Note that we
+         * must perform the memory access even if CCR_S.TRD is zero
+         * and we aren't going to check what the data loaded is.
+         */
+        uint32_t spdata, sp;
+
+        /*
+         * We know we are currently NS, so the S stack pointers must be
+         * in other_ss_{psp,msp}, not in regs[13]/other_sp.
+         */
+        sp = v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other_ss_msp;
+        if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) {
+            /* Stack access failed and an exception has been pended */
+            return false;
+        }
+
+        if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) {
+            if (((spdata & ~1) == 0xfefa125a) ||
+                !(env->v7m.control[M_REG_S] & 1)) {
+                goto gen_invep;
+            }
+        }
+    }
+
     env->regs[14] &= ~1;
     env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
     switch_v7m_security_state(env, true);
-- 
2.20.1

In commit 077d7449100d824a4 we added code to handle the v8M
requirement that returns from NMI or HardFault forcibly deactivate
those exceptions regardless of what interrupt the guest is trying to
deactivate.  Unfortunately this broke the handling of the "illegal
exception return because the returning exception number is not
active" check for those cases.  In the pseudocode this test is done
on the exception the guest asks to return from, but because our
implementation was doing this in armv7m_nvic_complete_irq() after the
new "deactivate NMI/HardFault regardless" code we ended up doing the
test on the VecInfo for that exception instead, which usually meant
failing to raise the illegal exception return fault.

In the case for "configurable exception targeting the opposite
security state" we detected the illegal-return case but went ahead
and deactivated the VecInfo anyway, which is wrong because that is
the VecInfo for the other security state.

Rearrange the code so that we first identify the illegal return
cases, then see if we really need to deactivate NMI or HardFault
instead, and finally do the deactivation.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-25-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 59 +++++++++++++++++++++++--------------------
 1 file changed, 32 insertions(+), 27 deletions(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
 {
     NVICState *s = (NVICState *)opaque;
     VecInfo *vec = NULL;
-    int ret;
+    int ret = 0;
 
     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
 
+    trace_nvic_complete_irq(irq, secure);
+
+    if (secure && exc_is_banked(irq)) {
+        vec = &s->sec_vectors[irq];
+    } else {
+        vec = &s->vectors[irq];
+    }
+
+    /*
+     * Identify illegal exception return cases. We can't immediately
+     * return at this point because we still need to deactivate
+     * (either this exception or NMI/HardFault) first.
+     */
+    if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
+        /*
+         * Return from a configurable exception targeting the opposite
+         * security state from the one we're trying to complete it for.
+         * Clear vec because it's not really the VecInfo for this
+         * (irq, secstate) so we mustn't deactivate it.
+         */
+        ret = -1;
+        vec = NULL;
+    } else if (!vec->active) {
+        /* Return from an inactive interrupt */
+        ret = -1;
+    } else {
+        /* Legal return, we will return the RETTOBASE bit value to the caller */
+        ret = nvic_rettobase(s);
+    }
+
     /*
      * For negative priorities, v8M will forcibly deactivate the appropriate
      * NMI or HardFault regardless of what interrupt we're being asked to
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
     }
 
     if (!vec) {
-        if (secure && exc_is_banked(irq)) {
-            vec = &s->sec_vectors[irq];
-        } else {
-            vec = &s->vectors[irq];
-        }
-    }
-
-    trace_nvic_complete_irq(irq, secure);
-
-    if (!vec->active) {
-        /* Tell the caller this was an illegal exception return */
-        return -1;
-    }
-
-    /*
-     * If this is a configurable exception and it is currently
-     * targeting the opposite security state from the one we're trying
-     * to complete it for, this counts as an illegal exception return.
-     * We still need to deactivate whatever vector the logic above has
-     * selected, though, as it might not be the same as the one for the
-     * requested exception number.
-     */
-    if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
-        ret = -1;
-    } else {
-        ret = nvic_rettobase(s);
+        return ret;
     }
 
     vec->active = 0;
-- 
2.20.1

For v8.1M the architecture mandates that CPUs must provide at
least the "minimal RAS implementation" from the Reliability,
Availability and Serviceability extension. This consists of:
 * an ESB instruction which is a NOP
   -- since it is in the HINT space we need only add a comment
 * an RFSR register which will RAZ/WI
 * a RAZ/WI AIRCR.IESB bit
   -- the code which handles writes to AIRCR does not allow setting
      of RES0 bits, so we already treat this as RAZ/WI; add a comment
      noting that this is deliberate
 * minimal implementation of the RAS register block at 0xe0005000
   -- this will be in a subsequent commit
 * setting the ID_PFR0.RAS field to 0b0010
   -- we will do this when we add the Cortex-M55 CPU model

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-26-peter.maydell@linaro.org
---
 target/arm/cpu.h      | 14 ++++++++++++++
 target/arm/t32.decode |  4 ++++
 hw/intc/armv7m_nvic.c | 13 +++++++++++++
 3 files changed, 31 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
 FIELD(ID_MMFR4, CCIDX, 24, 4)
 FIELD(ID_MMFR4, EVT, 28, 4)
 
+FIELD(ID_PFR0, STATE0, 0, 4)
+FIELD(ID_PFR0, STATE1, 4, 4)
+FIELD(ID_PFR0, STATE2, 8, 4)
+FIELD(ID_PFR0, STATE3, 12, 4)
+FIELD(ID_PFR0, CSV2, 16, 4)
+FIELD(ID_PFR0, AMU, 20, 4)
+FIELD(ID_PFR0, DIT, 24, 4)
+FIELD(ID_PFR0, RAS, 28, 4)
+
 FIELD(ID_PFR1, PROGMOD, 0, 4)
 FIELD(ID_PFR1, SECURITY, 4, 4)
 FIELD(ID_PFR1, MPROGMOD, 8, 4)
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
 }
 
+static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
+}
+
 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
 {
     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -XXX,XX +XXX,XX @@ CLZ              1111 1010 1011 ---- 1111 .... 1000 ....      @rdm
       # SEV      1111 0011 1010 1111 1000 0000 0000 0100
       # SEVL     1111 0011 1010 1111 1000 0000 0000 0101
 
+      # For M-profile minimal-RAS ESB can be a NOP, which is the
+      # default behaviour since it is in the hint space.
+      # ESB      1111 0011 1010 1111 1000 0000 0001 0000
+
       # The canonical nop ends in 0000 0000, but the whole rest
       # of the space is "reserved hint, behaves as nop".
       NOP        1111 0011 1010 1111 1000 0000 ---- ----
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
             return 0;
         }
         return cpu->env.v7m.sfar;
+    case 0xf04: /* RFSR */
+        if (!cpu_isar_feature(aa32_ras, cpu)) {
+            goto bad_offset;
+        }
+        /* We provide minimal-RAS only: RFSR is RAZ/WI */
+        return 0;
     case 0xf34: /* FPCCR */
         if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
             return 0;
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
                               R_V7M_AIRCR_PRIGROUP_SHIFT,
                               R_V7M_AIRCR_PRIGROUP_LENGTH);
             }
+            /* AIRCR.IESB is RAZ/WI because we implement only minimal RAS */
             if (attrs.secure) {
                 /* These bits are only writable by secure */
                 cpu->env.v7m.aircr = value &
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
         }
         break;
     }
+    case 0xf04: /* RFSR */
+        if (!cpu_isar_feature(aa32_ras, cpu)) {
+            goto bad_offset;
+        }
+        /* We provide minimal-RAS only: RFSR is RAZ/WI */
+        break;
     case 0xf34: /* FPCCR */
         if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
             /* Not all bits here are banked. */
-- 
2.20.1

The RAS feature has a block of memory-mapped registers at offset
0x5000 within the PPB.  For a "minimal RAS" implementation we provide
no error records and so the only registers that exist in the block
are ERRIIDR and ERRDEVID.

The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour
of the "nvic-default" region is actually valid for minimal-RAS,
so the main benefit of providing an explicit implementation of
the register block is more accurate LOG_UNIMP messages, and a
framework for where we could add a real RAS implementation later
if necessary.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-27-peter.maydell@linaro.org
---
 include/hw/intc/armv7m_nvic.h |  1 +
 hw/intc/armv7m_nvic.c         | 56 +++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)