Series comparison

-[PULL 00/30] riscv-to-apply queue
+[PULL 00/39] riscv-to-apply queue
-The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:
+The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:
-  Merge remote-tracking branch 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging (2020-09-08 21:21:13 +0100)
+  Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu into staging (2024-12-16 14:20:33 -0500)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241219-1
-for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:
+for you to fetch changes up to 5632d271be16b5e769342d54198c4359658abcb7:
-  hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19 -0700)
+  target/riscv: add support for RV64 Xiangshan Nanhu CPU (2024-12-18 11:07:59 +1000)
 ----------------------------------------------------------------
-This PR includes multiple fixes and features for RISC-V:
+RISC-V PR for 10.0
- - Fixes a bug in printing trap causes
- - Allows 16-bit writes to the SiFive test device. This fixes the
+* Correct the validness check of iova
-   failure to reboot the RISC-V virt machine
+* Fix APLIC in_clrip and clripnum write emulation
- - Support for the Microchip PolarFire SoC and Icicle Kit
+* Support riscv-iommu-sys device
- - A reafactor of RISC-V code out of hw/riscv
+* Add Tenstorrent Ascalon CPU
 * Add AIA userspace irqchip_split support
 * Add Microblaze V generic board
 * Upgrade ACPI SPCR table to support SPCR table revision 4 format
 * Remove tswap64() calls from HTIF
 * Support 64-bit address of initrd
 * Introduce svukte ISA extension
 * Support ssstateen extension
 * Support for RV64 Xiangshan Nanhu CPU
 ----------------------------------------------------------------
-Bin Meng (28):
+Anton Blanchard (1):
-      target/riscv: cpu: Add a new 'resetvec' property
+      target/riscv: Add Tenstorrent Ascalon CPU
       hw/riscv: hart: Add a new 'resetvec' property
       target/riscv: cpu: Set reset vector based on the configured property value
       hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
       hw/char: Add Microchip PolarFire SoC MMUART emulation
       hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
       hw/sd: Add Cadence SDHCI emulation
       hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
       hw/dma: Add SiFive platform DMA controller emulation
       hw/riscv: microchip_pfsoc: Connect a DMA controller
       hw/net: cadence_gem: Add a new 'phy-addr' property
       hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
       hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
       hw/riscv: microchip_pfsoc: Hook GPIO controllers
       hw/riscv: clint: Avoid using hard-coded timebase frequency
       hw/riscv: sifive_u: Connect a DMA controller
       hw/riscv: Move sifive_e_prci model to hw/misc
       hw/riscv: Move sifive_u_prci model to hw/misc
       hw/riscv: Move sifive_u_otp model to hw/misc
       hw/riscv: Move sifive_gpio model to hw/gpio
       hw/riscv: Move sifive_clint model to hw/intc
       hw/riscv: Move sifive_plic model to hw/intc
       hw/riscv: Move riscv_htif model to hw/char
       hw/riscv: Move sifive_uart model to hw/char
       hw/riscv: Move sifive_test model to hw/misc
       hw/riscv: Always build riscv_hart.c
       hw/riscv: Drop CONFIG_SIFIVE
       hw/riscv: Sort the Kconfig options in alphabetical order
-Nathan Chancellor (1):
+Daniel Henrique Barboza (15):
-      riscv: sifive_test: Allow 16-bit writes to memory region
+      hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()
       hw/riscv/riscv-iommu: parametrize CAP.IGS
       hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support
       hw/riscv/riscv-iommu: implement reset protocol
       docs/specs: add riscv-iommu-sys information
       hw/intc/riscv_aplic: rename is_kvm_aia()
       hw/riscv/virt.c: reduce virt_use_kvm_aia() usage
       hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()
       target/riscv/kvm: consider irqchip_split() in aia_create()
       hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers
       hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic
       target/riscv/kvm: remove irqchip_split() restriction
       docs: update riscv/virt.rst with kernel-irqchip=split support
       target/riscv/tcg: hide warn for named feats when disabling via priv_ver
       target/riscv: add ssstateen
-Yifei Jiang (1):
+Fea.Wang (6):
-      target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
+      target/riscv: Add svukte extension capability variable
       target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
       target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
       target/riscv: Check memory access to meet svukte rule
       target/riscv: Expose svukte ISA extension
       target/riscv: Check svukte is not enabled in RV32
- default-configs/riscv64-softmmu.mak         |   1 +
+Jason Chien (1):
- {include/hw/riscv => hw/intc}/sifive_plic.h |   0
+      hw/riscv/riscv-iommu.c: Correct the validness check of iova
  hw/riscv/trace.h                            |   1 -
  include/hw/char/mchp_pfsoc_mmuart.h         |  61 ++++
  include/hw/{riscv => char}/riscv_htif.h     |   0
  include/hw/{riscv => char}/sifive_uart.h    |   0
  include/hw/dma/sifive_pdma.h                |  57 ++++
  include/hw/{riscv => gpio}/sifive_gpio.h    |   0
  include/hw/{riscv => intc}/sifive_clint.h   |   4 +-
  include/hw/{riscv => misc}/sifive_e_prci.h  |   0
  include/hw/{riscv => misc}/sifive_test.h    |   0
  include/hw/{riscv => misc}/sifive_u_otp.h   |   0
  include/hw/{riscv => misc}/sifive_u_prci.h  |   0
  include/hw/net/cadence_gem.h                |   2 +
  include/hw/riscv/microchip_pfsoc.h          | 133 +++++++++
  include/hw/riscv/riscv_hart.h               |   1 +
  include/hw/riscv/sifive_e.h                 |   2 +-
  include/hw/riscv/sifive_u.h                 |  17 +-
  include/hw/sd/cadence_sdhci.h               |  47 +++
  target/riscv/cpu.h                          |   8 +-
  hw/arm/xilinx_zynq.c                        |   1 +
  hw/arm/xlnx-versal.c                        |   1 +
  hw/arm/xlnx-zynqmp.c                        |   2 +
  hw/char/mchp_pfsoc_mmuart.c                 |  86 ++++++
  hw/{riscv => char}/riscv_htif.c             |   2 +-
  hw/{riscv => char}/sifive_uart.c            |   2 +-
  hw/dma/sifive_pdma.c                        | 313 ++++++++++++++++++++
  hw/{riscv => gpio}/sifive_gpio.c            |   2 +-
  hw/{riscv => intc}/sifive_clint.c           |  28 +-
  hw/{riscv => intc}/sifive_plic.c            |   2 +-
  hw/{riscv => misc}/sifive_e_prci.c          |   2 +-
  hw/{riscv => misc}/sifive_test.c            |   4 +-
  hw/{riscv => misc}/sifive_u_otp.c           |   2 +-
  hw/{riscv => misc}/sifive_u_prci.c          |   2 +-
  hw/net/cadence_gem.c                        |   7 +-
  hw/riscv/microchip_pfsoc.c                  | 437 ++++++++++++++++++++++++++++
  hw/riscv/opentitan.c                        |   1 +
  hw/riscv/riscv_hart.c                       |   3 +
  hw/riscv/sifive_e.c                         |  12 +-
  hw/riscv/sifive_u.c                         |  41 ++-
  hw/riscv/spike.c                            |   7 +-
  hw/riscv/virt.c                             |   9 +-
  hw/sd/cadence_sdhci.c                       | 193 ++++++++++++
  target/riscv/cpu.c                          |  19 +-
  target/riscv/cpu_helper.c                   |   8 +-
  target/riscv/csr.c                          |   4 +-
  MAINTAINERS                                 |   9 +
  hw/char/Kconfig                             |   9 +
  hw/char/meson.build                         |   3 +
  hw/dma/Kconfig                              |   3 +
  hw/dma/meson.build                          |   1 +
  hw/gpio/Kconfig                             |   3 +
  hw/gpio/meson.build                         |   1 +
  hw/gpio/trace-events                        |   6 +
  hw/intc/Kconfig                             |   6 +
  hw/intc/meson.build                         |   2 +
  hw/misc/Kconfig                             |  12 +
  hw/misc/meson.build                         |   6 +
  hw/riscv/Kconfig                            |  70 +++--
  hw/riscv/meson.build                        |  12 +-
  hw/riscv/trace-events                       |   7 -
  hw/sd/Kconfig                               |   4 +
  hw/sd/meson.build                           |   1 +
  meson.build                                 |   1 -
 files changed, 1575 insertions(+), 105 deletions(-)
  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
  delete mode 100644 hw/riscv/trace.h
  create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
  rename include/hw/{riscv => char}/riscv_htif.h (100%)
  rename include/hw/{riscv => char}/sifive_uart.h (100%)
  create mode 100644 include/hw/dma/sifive_pdma.h
  rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
  rename include/hw/{riscv => intc}/sifive_clint.h (92%)
  rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
  rename include/hw/{riscv => misc}/sifive_test.h (100%)
  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
  rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
  create mode 100644 include/hw/riscv/microchip_pfsoc.h
  create mode 100644 include/hw/sd/cadence_sdhci.h
  create mode 100644 hw/char/mchp_pfsoc_mmuart.c
  rename hw/{riscv => char}/riscv_htif.c (99%)
  rename hw/{riscv => char}/sifive_uart.c (99%)
  create mode 100644 hw/dma/sifive_pdma.c
  rename hw/{riscv => gpio}/sifive_gpio.c (99%)
  rename hw/{riscv => intc}/sifive_clint.c (90%)
  rename hw/{riscv => intc}/sifive_plic.c (99%)
  rename hw/{riscv => misc}/sifive_e_prci.c (99%)
  rename hw/{riscv => misc}/sifive_test.c (97%)
  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
  rename hw/{riscv => misc}/sifive_u_prci.c (99%)
  create mode 100644 hw/riscv/microchip_pfsoc.c
  create mode 100644 hw/sd/cadence_sdhci.c
  delete mode 100644 hw/riscv/trace-events
+Jim Shu (3):
+      hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
+      hw/riscv: Add a new struct RISCVBootInfo
+      hw/riscv: Add the checking if DTB overlaps to kernel or initrd
+MollyChen (1):
+      target/riscv: add support for RV64 Xiangshan Nanhu CPU
+Philippe Mathieu-Daudé (5):
+      MAINTAINERS: Cover RISC-V HTIF interface
+      hw/char/riscv_htif: Explicit little-endian implementation
+      hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses
+      target/riscv: Include missing headers in 'vector_internals.h'
+      target/riscv: Include missing headers in 'internals.h'
+Sai Pavan Boddu (1):
+      hw/riscv: Add Microblaze V generic board
+Sia Jee Heng (3):
+      qtest: allow SPCR acpi table changes
+      hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
+      tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V
+Sunil V L (1):
+      hw/riscv/virt: Add IOMMU as platform device if the option is set
+Tomasz Jeznach (1):
+      hw/riscv: add riscv-iommu-sys platform device
+Yong-Xuan Wang (1):
+      hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
+ MAINTAINERS                                |   8 +
+ docs/specs/index.rst                       |   1 +
+ docs/specs/riscv-aia.rst                   |  83 ++++++++++
+ docs/specs/riscv-iommu.rst                 |  30 +++-
+ docs/system/riscv/microblaze-v-generic.rst |  42 +++++
+ docs/system/riscv/virt.rst                 |  17 ++
+ docs/system/target-riscv.rst               |   1 +
+ hw/riscv/riscv-iommu-bits.h                |   6 +
+ hw/riscv/riscv-iommu.h                     |   5 +
+ include/hw/acpi/acpi-defs.h                |   7 +-
+ include/hw/acpi/aml-build.h                |   2 +-
+ include/hw/intc/riscv_aplic.h              |   8 +
+ include/hw/riscv/boot.h                    |  28 +++-
+ include/hw/riscv/iommu.h                   |  10 +-
+ include/hw/riscv/virt.h                    |   6 +-
+ target/riscv/cpu-qom.h                     |   2 +
+ target/riscv/cpu_bits.h                    |   2 +
+ target/riscv/cpu_cfg.h                     |   2 +
+ target/riscv/internals.h                   |   3 +
+ target/riscv/vector_internals.h            |   1 +
+ hw/acpi/aml-build.c                        |  20 ++-
+ hw/arm/virt-acpi-build.c                   |   8 +-
+ hw/char/riscv_htif.c                       |  15 +-
+ hw/intc/riscv_aplic.c                      |  74 +++++++--
+ hw/loongarch/acpi-build.c                  |   6 +-
+ hw/riscv/boot.c                            | 100 +++++++----
+ hw/riscv/microblaze-v-generic.c            | 184 +++++++++++++++++++++
+ hw/riscv/microchip_pfsoc.c                 |  13 +-
+ hw/riscv/opentitan.c                       |   4 +-
+ hw/riscv/riscv-iommu-pci.c                 |  21 +++
+ hw/riscv/riscv-iommu-sys.c                 | 256 +++++++++++++++++++++++++++++
+ hw/riscv/riscv-iommu.c                     | 137 ++++++++++-----
+ hw/riscv/sifive_e.c                        |   4 +-
+ hw/riscv/sifive_u.c                        |  18 +-
+ hw/riscv/spike.c                           |  14 +-
+ hw/riscv/virt-acpi-build.c                 |  12 +-
+ hw/riscv/virt.c                            | 159 +++++++++++++++---
+ target/riscv/cpu.c                         | 101 ++++++++++++
+ target/riscv/cpu_helper.c                  |  55 +++++++
+ target/riscv/csr.c                         |   7 +
+ target/riscv/kvm/kvm-cpu.c                 |  43 ++---
+ target/riscv/tcg/tcg-cpu.c                 |  27 ++-
+ hw/riscv/Kconfig                           |   8 +
+ hw/riscv/meson.build                       |   3 +-
+ hw/riscv/trace-events                      |   4 +
+ tests/data/acpi/riscv64/virt/SPCR          | Bin 80 -> 90 bytes
+files changed, 1380 insertions(+), 177 deletions(-)
+ create mode 100644 docs/specs/riscv-aia.rst
+ create mode 100644 docs/system/riscv/microblaze-v-generic.rst
+ create mode 100644 hw/riscv/microblaze-v-generic.c
+ create mode 100644 hw/riscv/riscv-iommu-sys.c

-New patch
+[PULL 01/39] hw/riscv/riscv-iommu.c: Correct the validness check of iova
+From: Jason Chien <jason.chien@sifive.com>
+From RISCV IOMMU spec section 2.1.3:
+When SXL is 1, the following rules apply:
+- If the first-stage is not Bare, then a page fault corresponding to the
+original access type occurs if the IOVA has bits beyond bit 31 set to 1.
+- If the second-stage is not Bare, then a guest page fault corresponding
+to the original access type occurs if the incoming GPA has bits beyond bit
+set to 1.
+From RISCV IOMMU spec section 2.3 step 17:
+Use the process specified in Section "Two-Stage Address Translation" of
+the RISC-V Privileged specification to determine the GPA accessed by the
+transaction.
+From RISCV IOMMU spec section 2.3 step 19:
+Use the second-stage address translation process specified in Section
+"Two-Stage Address Translation" of the RISC-V Privileged specification
+to translate the GPA A to determine the SPA accessed by the transaction.
+This commit adds the iova check with the following rules:
+- For Sv32, Sv32x4, Sv39x4, Sv48x4 and Sv57x4, the iova must be zero
+extended.
+- For Sv39, Sv48 and Sv57, the iova must be signed extended with most
+significant bit.
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-ID: <20241114065617.25133-1-jason.chien@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/riscv-iommu.c | 23 ++++++++++++++++++++---
+file changed, 20 insertions(+), 3 deletions(-)
+diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/riscv-iommu.c
++++ b/hw/riscv/riscv-iommu.c
+@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
+         /* Address range check before first level lookup */
+         if (!sc[pass].step) {
+-            const uint64_t va_mask = (1ULL << (va_skip + va_bits)) - 1;
+-            if ((addr & va_mask) != addr) {
+-                return RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED;
++            const uint64_t va_len = va_skip + va_bits;
++            const uint64_t va_mask = (1ULL << va_len) - 1;
++
++            if (pass == S_STAGE && va_len > 32) {
++                target_ulong mask, masked_msbs;
++
++                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
++                masked_msbs = (addr >> (va_len - 1)) & mask;
++
++                if (masked_msbs != 0 && masked_msbs != mask) {
++                    return (iotlb->perm & IOMMU_WO) ?
++                                RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S :
++                                RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S;
++                }
++            } else {
++                if ((addr & va_mask) != addr) {
++                    return (iotlb->perm & IOMMU_WO) ?
++                                RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS :
++                                RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS;
++                }
+             }
+         }
+--
+.47.1

-New patch
+[PULL 02/39] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
+In the section "4.7 Precise effects on interrupt-pending bits"
+of the RISC-V AIA specification defines that:
+"If the source mode is Level1 or Level0 and the interrupt domain
+is configured in MSI delivery mode (domaincfg.DM = 1):
+The pending bit is cleared whenever the rectified input value is
+low, when the interrupt is forwarded by MSI, or by a relevant
+write to an in_clrip register or to clripnum."
+Update the riscv_aplic_set_pending() to match the spec.
+Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode")
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20241029085349.30412-1-yongxuan.wang@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/intc/riscv_aplic.c | 6 +++++-
+file changed, 5 insertions(+), 1 deletion(-)
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/riscv_aplic.c
++++ b/hw/intc/riscv_aplic.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
+     if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
+         (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
+-        if (!aplic->msimode || (aplic->msimode && !pending)) {
++        if (!aplic->msimode) {
+             return;
+         }
++        if (aplic->msimode && !pending) {
++            goto noskip_write_pending;
++        }
+         if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
+             (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
+             return;
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
+         }
+     }
++noskip_write_pending:
+     riscv_aplic_set_pending_raw(aplic, irq, pending);
+ }
+--
+.47.1

-[PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region
+[PULL 03/39] hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()
-From: Nathan Chancellor <natechancellor@gmail.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-When shutting down the machine running a mainline Linux kernel, the
+Move all the static initializion of the device to an init() function,
-following error happens:
+leaving only the dynamic initialization to be done during realize.
-$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
+With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
-    -display none -initrd rootfs.cpio -kernel Image -m 512m \
+init(), and realize() will increment s->cap with the extra caps.
     -nodefaults -serial mon:stdio
 ...
 Requesting system poweroff
 [    4.999630] reboot: Power down
 sbi_trap_error: hart0: trap handler failed (error -2)
 sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
 sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
 sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
 sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
 sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
 sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
 sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
 sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
 sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
 sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
 sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
 sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
 sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
 sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
 sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
 sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
 sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
 sbi_trap_error: hart0: t6=0x0000000000000000
-The kernel does a 16-bit write when powering off the machine, which
+This will allow callers to add IOMMU capabilities before the
-was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
+realization.
 mismatching sizes in memory_region_access_valid""). Make min_access_size
 match reality so that the machine can shut down properly now.
-Cc: qemu-stable@nongnu.org
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
 Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"")
 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
 Acked-by: Michael S. Tsirkin <mst@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com>
+Message-ID: <20241106133407.604587-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/sifive_test.c | 2 +-
+ hw/riscv/riscv-iommu.c | 71 +++++++++++++++++++++++-------------------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 39 insertions(+), 32 deletions(-)
-diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
+diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_test.c
+--- a/hw/riscv/riscv-iommu.c
-+++ b/hw/riscv/sifive_test.c
++++ b/hw/riscv/riscv-iommu.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_test_ops = {
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps riscv_iommu_trap_ops = {
      .write = sifive_test_write,
      .endianness = DEVICE_NATIVE_ENDIAN,
      .valid = {
 -        .min_access_size = 4,
 +        .min_access_size = 2,
          .max_access_size = 4
      }
  };
++static void riscv_iommu_instance_init(Object *obj)
++{
++    RISCVIOMMUState *s = RISCV_IOMMU(obj);
++
++    /* Enable translation debug interface */
++    s->cap = RISCV_IOMMU_CAP_DBG;
++
++    /* Report QEMU target physical address space limits */
++    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
++                       TARGET_PHYS_ADDR_SPACE_BITS);
++
++    /* TODO: method to report supported PID bits */
++    s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
++    s->cap |= RISCV_IOMMU_CAP_PD8;
++
++    /* register storage */
++    s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
++    s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
++    s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
++
++     /* Mark all registers read-only */
++    memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
++
++    /* Device translation context cache */
++    s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
++                                         riscv_iommu_ctx_equal,
++                                         g_free, NULL);
++
++    s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash,
++                                         riscv_iommu_iot_equal,
++                                         g_free, NULL);
++
++    s->iommus.le_next = NULL;
++    s->iommus.le_prev = NULL;
++    QLIST_INIT(&s->spaces);
++}
++
+ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
+ {
+     RISCVIOMMUState *s = RISCV_IOMMU(dev);
+-    s->cap = s->version & RISCV_IOMMU_CAP_VERSION;
++    s->cap |= s->version & RISCV_IOMMU_CAP_VERSION;
+     if (s->enable_msi) {
+         s->cap |= RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF;
+     }
+@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
+         s->cap |= RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 |
+                   RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
+     }
+-    /* Enable translation debug interface */
+-    s->cap |= RISCV_IOMMU_CAP_DBG;
+-
+-    /* Report QEMU target physical address space limits */
+-    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
+-                       TARGET_PHYS_ADDR_SPACE_BITS);
+-
+-    /* TODO: method to report supported PID bits */
+-    s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
+-    s->cap |= RISCV_IOMMU_CAP_PD8;
+     /* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough) */
+     s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ?
+                         RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE);
+-    /* register storage */
+-    s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+-    s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+-    s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+-
+-     /* Mark all registers read-only */
+-    memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
+-
+     /*
+      * Register complete MMIO space, including MSI/PBA registers.
+      * Note, PCIDevice implementation will add overlapping MR for MSI/PBA,
+@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
+     memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops, s,
+             "riscv-iommu-trap", ~0ULL);
+     address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as");
+-
+-    /* Device translation context cache */
+-    s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
+-                                         riscv_iommu_ctx_equal,
+-                                         g_free, NULL);
+-
+-    s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash,
+-                                         riscv_iommu_iot_equal,
+-                                         g_free, NULL);
+-
+-    s->iommus.le_next = NULL;
+-    s->iommus.le_prev = NULL;
+-    QLIST_INIT(&s->spaces);
+ }
+ static void riscv_iommu_unrealize(DeviceState *dev)
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_iommu_info = {
+     .name = TYPE_RISCV_IOMMU,
+     .parent = TYPE_DEVICE,
+     .instance_size = sizeof(RISCVIOMMUState),
++    .instance_init = riscv_iommu_instance_init,
+     .class_init = riscv_iommu_class_init,
+ };
 --
-.28.0
+.47.1

-[PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio
+[PULL 04/39] hw/riscv/riscv-iommu: parametrize CAP.IGS
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Interrupt Generation Support (IGS) is a capability that is tied to the
-should only contain the RISC-V SoC / machine codes plus generic
+interrupt deliver mechanism, not with the core IOMMU emulation. We
-codes. Let's move sifive_gpio model to hw/gpio directory.
+should allow device implementations to set IGS as they wish.
-Note this also removes the trace-events in the hw/riscv directory,
+A new helper is added to make it easier for device impls to set IGS. Use
-since gpio is the only supported trace target in that directory.
+it in our existing IOMMU device (riscv-iommu-pci) to set
 RISCV_IOMMU_CAPS_IGS_MSI.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241106133407.604587-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/trace.h                         | 1 -
+ hw/riscv/riscv-iommu-bits.h | 6 ++++++
- include/hw/{riscv => gpio}/sifive_gpio.h | 0
+ hw/riscv/riscv-iommu.h      | 4 ++++
- include/hw/riscv/sifive_e.h              | 2 +-
+ hw/riscv/riscv-iommu-pci.c  | 1 +
- include/hw/riscv/sifive_u.h              | 2 +-
+ hw/riscv/riscv-iommu.c      | 5 +++++
- hw/{riscv => gpio}/sifive_gpio.c         | 2 +-
+files changed, 16 insertions(+)
  hw/gpio/Kconfig                          | 3 +++
  hw/gpio/meson.build                      | 1 +
  hw/gpio/trace-events                     | 6 ++++++
  hw/riscv/Kconfig                         | 2 ++
  hw/riscv/meson.build                     | 1 -
  hw/riscv/trace-events                    | 7 -------
  meson.build                              | 1 -
 files changed, 15 insertions(+), 13 deletions(-)
  delete mode 100644 hw/riscv/trace.h
  rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
  rename hw/{riscv => gpio}/sifive_gpio.c (99%)
  delete mode 100644 hw/riscv/trace-events
-diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
+diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/hw/riscv/trace.h
 +++ /dev/null
@@ -1 +0,0 @@
 -#include "trace/trace-hw_riscv.h"
 diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
 similarity index 100%
 rename from include/hw/riscv/sifive_gpio.h
 rename to include/hw/gpio/sifive_gpio.h
 diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_e.h
+--- a/hw/riscv/riscv-iommu-bits.h
-+++ b/include/hw/riscv/sifive_e.h
++++ b/hw/riscv/riscv-iommu-bits.h
@@ -XXX,XX +XXX,XX @@ struct riscv_iommu_pq_record {
  #define RISCV_IOMMU_CAP_PD17            BIT_ULL(39)
  #define RISCV_IOMMU_CAP_PD20            BIT_ULL(40)
 +enum riscv_iommu_igs_modes {
 +    RISCV_IOMMU_CAP_IGS_MSI = 0,
 +    RISCV_IOMMU_CAP_IGS_WSI,
 +    RISCV_IOMMU_CAP_IGS_BOTH
 +};
 +
  /* 5.4 Features control register (32bits) */
  #define RISCV_IOMMU_REG_FCTL            0x0008
  #define RISCV_IOMMU_FCTL_BE             BIT(0)
 diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/riscv-iommu.h
 +++ b/hw/riscv/riscv-iommu.h
 @@ -XXX,XX +XXX,XX @@
- #include "hw/riscv/riscv_hart.h"
+ #include "qom/object.h"
- #include "hw/riscv/sifive_cpu.h"
+ #include "hw/riscv/iommu.h"
--#include "hw/riscv/sifive_gpio.h"
++#include "hw/riscv/riscv-iommu-bits.h"
-+#include "hw/gpio/sifive_gpio.h"
++
++typedef enum riscv_iommu_igs_modes riscv_iommu_igs_mode;
- #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
- #define RISCV_E_SOC(obj) \
+ struct RISCVIOMMUState {
-diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
+     /*< private >*/
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
  void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
           Error **errp);
 +void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode);
  /* private helpers */
 diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/hw/riscv/riscv-iommu-pci.c
-+++ b/include/hw/riscv/sifive_u.h
++++ b/hw/riscv/riscv-iommu-pci.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_pci_init(Object *obj)
- #include "hw/net/cadence_gem.h"
+     qdev_alias_all_properties(DEVICE(iommu), obj);
- #include "hw/riscv/riscv_hart.h"
- #include "hw/riscv/sifive_cpu.h"
+     iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;
--#include "hw/riscv/sifive_gpio.h"
++    riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI);
-+#include "hw/gpio/sifive_gpio.h"
+ }
- #include "hw/misc/sifive_u_otp.h"
- #include "hw/misc/sifive_u_prci.h"
+ static const Property riscv_iommu_pci_properties[] = {
+diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
 diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
 similarity index 99%
 rename from hw/riscv/sifive_gpio.c
 rename to hw/gpio/sifive_gpio.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_gpio.c
+--- a/hw/riscv/riscv-iommu.c
-+++ b/hw/gpio/sifive_gpio.c
++++ b/hw/riscv/riscv-iommu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps riscv_iommu_trap_ops = {
- #include "qemu/log.h"
+     }
- #include "hw/irq.h"
+ };
- #include "hw/qdev-properties.h"
--#include "hw/riscv/sifive_gpio.h"
++void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode)
-+#include "hw/gpio/sifive_gpio.h"
++{
- #include "migration/vmstate.h"
++    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_IGS, mode);
- #include "trace.h"
++}
 diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/Kconfig
 +++ b/hw/gpio/Kconfig
@@ -XXX,XX +XXX,XX @@ config PL061
  config GPIO_KEY
      bool
 +
-+config SIFIVE_GPIO
+ static void riscv_iommu_instance_init(Object *obj)
-+    bool
+ {
-diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
+     RISCVIOMMUState *s = RISCV_IOMMU(obj);
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/meson.build
 +++ b/hw/gpio/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
  softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
  nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
  nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
  nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 +
 +# sifive_gpio.c
 +sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 +sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 +sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 +sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
      bool
      select HART
      select SIFIVE
 +    select SIFIVE_GPIO
      select SIFIVE_E_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select CADENCE
      select HART
      select SIFIVE
 +    select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_U_OTP
      select SIFIVE_U_PRCI
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/hw/riscv/trace-events
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# See docs/devel/tracing.txt for syntax documentation.
 -
 -# hw/gpio/sifive_gpio.c
 -sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 -sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 -sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 -sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/meson.build
 +++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
      'hw/watchdog',
      'hw/xen',
      'hw/gpio',
 -    'hw/riscv',
      'migration',
      'net',
      'ui',
 --
-.28.0
+.47.1

-[PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation
+[PULL 05/39] hw/riscv: add riscv-iommu-sys platform device
-From: Bin Meng <bin.meng@windriver.com>
+From: Tomasz Jeznach <tjeznach@rivosinc.com>
-Microchip PolarFire SoC MMUART is ns16550 compatible, with some
+This device models the RISC-V IOMMU as a sysbus device. The same design
-additional registers. Create a simple MMUART model built on top
+decisions taken in the riscv-iommu-pci device were kept, namely the
-of the existing ns16550 model.
+existence of 4 vectors are available for each interrupt cause.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+The WSIs are emitted using the input of the s->notify() callback as a
 index to an IRQ list. The IRQ list starts at 'base_irq' and goes until
 base_irq + 3. This means that boards must have 4 contiguous IRQ lines
 available, starting from 'base_irq'.
 Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241106133407.604587-4-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
+ include/hw/riscv/iommu.h   |   4 ++
- hw/char/mchp_pfsoc_mmuart.c         | 86 +++++++++++++++++++++++++++++
+ hw/riscv/riscv-iommu-sys.c | 128 +++++++++++++++++++++++++++++++++++++
- MAINTAINERS                         |  2 +
+ hw/riscv/riscv-iommu.c     |   3 +-
- hw/char/Kconfig                     |  3 +
+ hw/riscv/meson.build       |   2 +-
- hw/char/meson.build                 |  1 +
+files changed, 134 insertions(+), 3 deletions(-)
-files changed, 153 insertions(+)
+ create mode 100644 hw/riscv/riscv-iommu-sys.c
- create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
- create mode 100644 hw/char/mchp_pfsoc_mmuart.c
+diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
+index XXXXXXX..XXXXXXX 100644
-diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
+--- a/include/hw/riscv/iommu.h
 +++ b/include/hw/riscv/iommu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
  OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
  typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
 +#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
 +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
 +typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
 +
  #endif
 diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/char/mchp_pfsoc_mmuart.h
++++ b/hw/riscv/riscv-iommu-sys.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * Microchip PolarFire SoC MMUART emulation
++ * QEMU emulation of an RISC-V IOMMU Platform Device
 + *
-+ * Copyright (c) 2020 Wind River Systems, Inc.
++ * Copyright (C) 2022-2023 Rivos Inc.
 + *
-+ * Author:
++ * This program is free software; you can redistribute it and/or modify it
-+ *   Bin Meng <bin.meng@windriver.com>
++ * under the terms and conditions of the GNU General Public License,
-+ *
++ * version 2 or later, as published by the Free Software Foundation.
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_MCHP_PFSOC_MMUART_H
 +#define HW_MCHP_PFSOC_MMUART_H
 +
 +#include "hw/char/serial.h"
 +
 +#define MCHP_PFSOC_MMUART_REG_SIZE  52
 +
 +typedef struct MchpPfSoCMMUartState {
 +    MemoryRegion iomem;
 +    hwaddr base;
 +    qemu_irq irq;
 +
 +    SerialMM *serial;
 +
 +    uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
 +} MchpPfSoCMMUartState;
 +
 +/**
 + * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
 + *
 + * This is a helper routine for board to create a MMUART device that is
 + * compatible with Microchip PolarFire SoC.
 + *
 + * @sysmem: system memory region to map
 + * @base: base address of the MMUART registers
 + * @irq: IRQ number of the MMUART device
 + * @chr: character device to associate to
 + *
 + * @return: a pointer to the device specific control structure
 + */
 +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
 +    hwaddr base, qemu_irq irq, Chardev *chr);
 +
 +#endif /* HW_MCHP_PFSOC_MMUART_H */
 diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Microchip PolarFire SoC MMUART emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
-+#include "qemu/log.h"
++#include "hw/irq.h"
-+#include "chardev/char.h"
++#include "hw/pci/pci_bus.h"
-+#include "exec/address-spaces.h"
++#include "hw/qdev-properties.h"
-+#include "hw/char/mchp_pfsoc_mmuart.h"
++#include "hw/sysbus.h"
-+
++#include "qapi/error.h"
-+static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
++#include "qemu/error-report.h"
-+{
++#include "qemu/host-utils.h"
-+    MchpPfSoCMMUartState *s = opaque;
++#include "qemu/module.h"
-+
++#include "qom/object.h"
-+    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
++
-+        qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
++#include "riscv-iommu.h"
-+                      __func__, addr);
++
-+        return 0;
++#define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
-+    }
++
-+
++/* RISC-V IOMMU System Platform Device Emulation */
-+    return s->reg[addr / sizeof(uint32_t)];
++
-+}
++struct RISCVIOMMUStateSys {
-+
++    SysBusDevice     parent;
-+static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
++    uint64_t         addr;
-+                                    uint64_t value, unsigned size)
++    uint32_t         base_irq;
-+{
++    DeviceState      *irqchip;
-+    MchpPfSoCMMUartState *s = opaque;
++    RISCVIOMMUState  iommu;
-+    uint32_t val32 = (uint32_t)value;
++    qemu_irq         irqs[RISCV_IOMMU_INTR_COUNT];
-+
++};
-+    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
++
-+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
++static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
-+                      " v=0x%x\n", __func__, addr, val32);
++                                      unsigned vector)
 +{
 +    RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu);
 +    uint32_t fctl =  riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
 +
 +    /* We do not support MSIs yet */
 +    if (!(fctl & RISCV_IOMMU_FCTL_WSI)) {
 +        return;
 +    }
 +
-+    s->reg[addr / sizeof(uint32_t)] = val32;
++    qemu_irq_pulse(s->irqs[vector]);
 +}
 +
-+static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
++static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
-+    .read = mchp_pfsoc_mmuart_read,
++{
-+    .write = mchp_pfsoc_mmuart_write,
++    RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev);
-+    .endianness = DEVICE_LITTLE_ENDIAN,
++    SysBusDevice *sysdev = SYS_BUS_DEVICE(s);
-+    .impl = {
++    PCIBus *pci_bus;
-+        .min_access_size = 4,
++    qemu_irq irq;
-+        .max_access_size = 4,
++
-+    },
++    qdev_realize(DEVICE(&s->iommu), NULL, errp);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr);
 +    if (s->addr) {
 +        sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr);
 +    }
 +
 +    pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL);
 +    if (pci_bus) {
 +        riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp);
 +    }
 +
 +    s->iommu.notify = riscv_iommu_sysdev_notify;
 +
 +    /* 4 IRQs are defined starting from s->base_irq */
 +    for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) {
 +        sysbus_init_irq(sysdev, &s->irqs[i]);
 +        irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i);
 +        sysbus_connect_irq(sysdev, i, irq);
 +    }
 +}
 +
 +static void riscv_iommu_sys_init(Object *obj)
 +{
 +    RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj);
 +    RISCVIOMMUState *iommu = &s->iommu;
 +
 +    object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU);
 +    qdev_alias_all_properties(DEVICE(iommu), obj);
 +
 +    iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
 +    riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI);
 +}
 +
 +static Property riscv_iommu_sys_properties[] = {
 +    DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0),
 +    DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0),
 +    DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip,
 +                     TYPE_DEVICE, DeviceState *),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
-+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
++static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
-+    hwaddr base, qemu_irq irq, Chardev *chr)
++{
-+{
++    DeviceClass *dc = DEVICE_CLASS(klass);
-+    MchpPfSoCMMUartState *s;
++    dc->realize = riscv_iommu_sys_realize;
-+
++    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
-+    s = g_new0(MchpPfSoCMMUartState, 1);
++    device_class_set_props(dc, riscv_iommu_sys_properties);
-+
++}
-+    memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
++
-+                          "mchp.pfsoc.mmuart", 0x1000);
++static const TypeInfo riscv_iommu_sys = {
-+
++    .name          = TYPE_RISCV_IOMMU_SYS,
-+    s->base = base;
++    .parent        = TYPE_SYS_BUS_DEVICE,
-+    s->irq = irq;
++    .class_init    = riscv_iommu_sys_class_init,
-+
++    .instance_init = riscv_iommu_sys_init,
-+    s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
++    .instance_size = sizeof(RISCVIOMMUStateSys),
-+                               DEVICE_LITTLE_ENDIAN);
++};
 +
-+    memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
++static void riscv_iommu_register_sys(void)
-+
++{
-+    return s;
++    type_register_static(&riscv_iommu_sys);
 +}
-diff --git a/MAINTAINERS b/MAINTAINERS
++
 +type_init(riscv_iommu_register_sys)
 diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/hw/riscv/riscv-iommu.c
-+++ b/MAINTAINERS
++++ b/hw/riscv/riscv-iommu.c
-@@ -XXX,XX +XXX,XX @@ M: Bin Meng <bin.meng@windriver.com>
+@@ -XXX,XX +XXX,XX @@ static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t vec_type)
- L: qemu-riscv@nongnu.org
- S: Supported
+ static void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type)
- F: hw/riscv/microchip_pfsoc.c
+ {
-+F: hw/char/mchp_pfsoc_mmuart.c
+-    const uint32_t fctl = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FCTL);
- F: include/hw/riscv/microchip_pfsoc.h
+     uint32_t ipsr, icvec, vector;
-+F: include/hw/char/mchp_pfsoc_mmuart.h
+-    if (fctl & RISCV_IOMMU_FCTL_WSI || !s->notify) {
- RX Machines
++    if (!s->notify) {
- -----------
+         return;
-diff --git a/hw/char/Kconfig b/hw/char/Kconfig
+     }
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/Kconfig
+--- a/hw/riscv/meson.build
-+++ b/hw/char/Kconfig
++++ b/hw/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@ config RENESAS_SCI
+@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
+ riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
- config AVR_USART
+ riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
-     bool
+ riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
-+
+-riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c'))
-+config MCHP_PFSOC_MMUART
++riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
-+    bool
-diff --git a/hw/char/meson.build b/hw/char/meson.build
+ hw_arch += {'riscv': riscv_ss}
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/meson.build
 +++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
  softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
  softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
 +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
  specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
  specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
 --
-.28.0
+.47.1

-[PULL 27/30] hw/riscv: Move sifive_test model to hw/misc
+[PULL 06/39] hw/riscv/virt: Add IOMMU as platform device if the option is set
-From: Bin Meng <bin.meng@windriver.com>
+From: Sunil V L <sunilvl@ventanamicro.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Add a new machine option called 'iommu-sys' that enables a
-should only contain the RISC-V SoC / machine codes plus generic
+riscv-iommu-sys platform device for the 'virt' machine. The option is
-codes. Let's move sifive_test model to hw/misc directory.
+default 'off'.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+The device will use IRQs 36 to 39.
 We will not support both riscv-iommu-sys and riscv-iommu-pci devices in
 the same board in this first implementation. If a riscv-iommu-pci device
 is added in the command line we will disable the riscv-iommu-sys device.
 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241106133407.604587-5-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => misc}/sifive_test.h | 0
+ include/hw/riscv/iommu.h |   2 +
- hw/{riscv => misc}/sifive_test.c         | 2 +-
+ include/hw/riscv/virt.h  |   6 ++-
- hw/riscv/virt.c                          | 2 +-
+ hw/riscv/virt.c          | 104 ++++++++++++++++++++++++++++++++++++++-
- hw/misc/Kconfig                          | 3 +++
+files changed, 109 insertions(+), 3 deletions(-)
- hw/misc/meson.build                      | 1 +
- hw/riscv/Kconfig                         | 1 +
+diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
  hw/riscv/meson.build                     | 1 -
 files changed, 7 insertions(+), 3 deletions(-)
  rename include/hw/{riscv => misc}/sifive_test.h (100%)
  rename hw/{riscv => misc}/sifive_test.c (98%)
 diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
 similarity index 100%
 rename from include/hw/riscv/sifive_test.h
 rename to include/hw/misc/sifive_test.h
 diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
 similarity index 98%
 rename from hw/riscv/sifive_test.c
 rename to hw/misc/sifive_test.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_test.c
+--- a/include/hw/riscv/iommu.h
-+++ b/hw/misc/sifive_test.c
++++ b/include/hw/riscv/iommu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
- #include "qemu/module.h"
+ OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
- #include "sysemu/runstate.h"
+ typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
- #include "hw/hw.h"
--#include "hw/riscv/sifive_test.h"
++#define FDT_IRQ_TYPE_EDGE_LOW 1
-+#include "hw/misc/sifive_test.h"
++
+ #endif
- static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
+diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
- {
+index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/riscv/virt.h
 +++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
      OnOffAuto acpi;
      const MemMapEntry *memmap;
      struct GPEXHost *gpex_host;
 +    OnOffAuto iommu_sys;
  };
  enum {
@@ -XXX,XX +XXX,XX @@ enum {
      VIRT_PCIE_MMIO,
      VIRT_PCIE_PIO,
      VIRT_PLATFORM_BUS,
 -    VIRT_PCIE_ECAM
 +    VIRT_PCIE_ECAM,
 +    VIRT_IOMMU_SYS,
  };
  enum {
@@ -XXX,XX +XXX,XX @@ enum {
      VIRTIO_IRQ = 1, /* 1 to 8 */
      VIRTIO_COUNT = 8,
      PCIE_IRQ = 0x20, /* 32 to 35 */
 +    IOMMU_SYS_IRQ = 0x24, /* 36-39 */
      VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
  };
@@ -XXX,XX +XXX,XX @@ enum {
 + FDT_APLIC_INT_CELLS)
  bool virt_is_acpi_enabled(RISCVVirtState *s);
 +bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
  void virt_acpi_setup(RISCVVirtState *vms);
  uint32_t imsic_num_bits(uint32_t count);
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/char/serial.h"
+ #include "target/riscv/pmu.h"
  #include "target/riscv/cpu.h"
  #include "hw/riscv/riscv_hart.h"
--#include "hw/riscv/sifive_test.h"
+ #include "hw/riscv/iommu.h"
 +#include "hw/riscv/riscv-iommu-bits.h"
  #include "hw/riscv/virt.h"
  #include "hw/riscv/boot.h"
  #include "hw/riscv/numa.h"
- #include "hw/intc/sifive_clint.h"
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
- #include "hw/intc/sifive_plic.h"
+     [VIRT_CLINT] =        {  0x2000000,       0x10000 },
-+#include "hw/misc/sifive_test.h"
+     [VIRT_ACLINT_SSWI] =  {  0x2F00000,        0x4000 },
- #include "chardev/char.h"
+     [VIRT_PCIE_PIO] =     {  0x3000000,       0x10000 },
- #include "sysemu/arch_init.h"
++    [VIRT_IOMMU_SYS] =    {  0x3010000,        0x1000 },
- #include "sysemu/device_tree.h"
+     [VIRT_PLATFORM_BUS] = {  0x4000000,     0x2000000 },
-diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
+     [VIRT_PLIC] =         {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
-index XXXXXXX..XXXXXXX 100644
+     [VIRT_APLIC_M] =      {  0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
---- a/hw/misc/Kconfig
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
-+++ b/hw/misc/Kconfig
-@@ -XXX,XX +XXX,XX @@ config MAC_VIA
+ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
- config AVR_POWER
+                             uint32_t irq_pcie_phandle,
-     bool
+-                            uint32_t msi_pcie_phandle)
++                            uint32_t msi_pcie_phandle,
-+config SIFIVE_TEST
++                            uint32_t iommu_sys_phandle)
-+    bool
+ {
-+
+     g_autofree char *name = NULL;
- config SIFIVE_E_PRCI
+     MachineState *ms = MACHINE(s);
-     bool
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
+, virt_high_pcie_memmap.base,
-diff --git a/hw/misc/meson.build b/hw/misc/meson.build
+, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/meson.build
++    if (virt_is_iommu_sys_enabled(s)) {
-+++ b/hw/misc/meson.build
++        qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map",
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
++                               0, iommu_sys_phandle, 0, 0, 0,
- softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
++                               iommu_sys_phandle, 0, 0xffff);
++    }
- # RISC-V devices
++
-+softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
+     create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
- softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+ }
- softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
- softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+                            bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
-index XXXXXXX..XXXXXXX 100644
+ }
---- a/hw/riscv/Kconfig
-+++ b/hw/riscv/Kconfig
++static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
++                                 uint32_t *iommu_sys_phandle)
-     select SIFIVE
++{
-     select SIFIVE_CLINT
++    const char comp[] = "riscv,iommu";
-     select SIFIVE_PLIC
++    void *fdt = MACHINE(s)->fdt;
-+    select SIFIVE_TEST
++    uint32_t iommu_phandle;
++    g_autofree char *iommu_node = NULL;
- config MICROCHIP_PFSOC
++    hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base;
-     bool
++    hwaddr size = s->memmap[VIRT_IOMMU_SYS].size;
-diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
++    uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = {
-index XXXXXXX..XXXXXXX 100644
++        IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ,
---- a/hw/riscv/meson.build
++        IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ,
-+++ b/hw/riscv/meson.build
++        IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM,
-@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
++        IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ,
- riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
++    };
- riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
++
- riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
++    iommu_node = g_strdup_printf("/soc/iommu@%x",
--riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
++                               (unsigned int) s->memmap[VIRT_IOMMU_SYS].base);
- riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
++    iommu_phandle = qemu_fdt_alloc_phandle(fdt);
- riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
++    qemu_fdt_add_subnode(fdt, iommu_node);
- riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
++
 +    qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
 +    qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
 +    qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
 +
 +    qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
 +                           addr >> 32, addr, size >> 32, size);
 +    qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
 +
 +    qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",
 +        iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW,
 +        iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW,
 +        iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
 +        iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
 +
 +    *iommu_sys_phandle = iommu_phandle;
 +}
 +
  static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf)
  {
      const char comp[] = "riscv,pci-iommu";
@@ -XXX,XX +XXX,XX @@ static void finalize_fdt(RISCVVirtState *s)
  {
      uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
      uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
 +    uint32_t iommu_sys_phandle = 1;
      create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle,
                         &irq_pcie_phandle, &irq_virtio_phandle,
@@ -XXX,XX +XXX,XX @@ static void finalize_fdt(RISCVVirtState *s)
      create_fdt_virtio(s, virt_memmap, irq_virtio_phandle);
 -    create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle);
 +    if (virt_is_iommu_sys_enabled(s)) {
 +        create_fdt_iommu_sys(s, irq_mmio_phandle, &iommu_sys_phandle);
 +    }
 +    create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle,
 +                    iommu_sys_phandle);
      create_fdt_reset(s, virt_memmap, &phandle);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
          create_fdt(s, memmap);
      }
 +    if (virt_is_iommu_sys_enabled(s)) {
 +        DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS);
 +
 +        object_property_set_uint(OBJECT(iommu_sys), "addr",
 +                                 s->memmap[VIRT_IOMMU_SYS].base,
 +                                 &error_fatal);
 +        object_property_set_uint(OBJECT(iommu_sys), "base-irq",
 +                                 IOMMU_SYS_IRQ,
 +                                 &error_fatal);
 +        object_property_set_link(OBJECT(iommu_sys), "irqchip",
 +                                 OBJECT(mmio_irqchip),
 +                                 &error_fatal);
 +
 +        sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);
 +    }
 +
      s->machine_done.notify = virt_machine_done;
      qemu_add_machine_init_done_notifier(&s->machine_done);
  }
@@ -XXX,XX +XXX,XX @@ static void virt_machine_instance_init(Object *obj)
      s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
      s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
      s->acpi = ON_OFF_AUTO_AUTO;
 +    s->iommu_sys = ON_OFF_AUTO_AUTO;
  }
  static char *virt_get_aia_guests(Object *obj, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void virt_set_aclint(Object *obj, bool value, Error **errp)
      s->have_aclint = value;
  }
 +bool virt_is_iommu_sys_enabled(RISCVVirtState *s)
 +{
 +    return s->iommu_sys == ON_OFF_AUTO_ON;
 +}
 +
 +static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name,
 +                               void *opaque, Error **errp)
 +{
 +    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
 +    OnOffAuto iommu_sys = s->iommu_sys;
 +
 +    visit_type_OnOffAuto(v, name, &iommu_sys, errp);
 +}
 +
 +static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name,
 +                               void *opaque, Error **errp)
 +{
 +    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
 +
 +    visit_type_OnOffAuto(v, name, &s->iommu_sys, errp);
 +}
 +
  bool virt_is_acpi_enabled(RISCVVirtState *s)
  {
      return s->acpi != ON_OFF_AUTO_OFF;
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
                                                          DeviceState *dev)
  {
      MachineClass *mc = MACHINE_GET_CLASS(machine);
 +    RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
      if (device_is_dynamic_sysbus(mc, dev) ||
          object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
          object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
 +        s->iommu_sys = ON_OFF_AUTO_OFF;
          return HOTPLUG_HANDLER(machine);
      }
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
      if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
          create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
 +        s->iommu_sys = ON_OFF_AUTO_OFF;
      }
  }
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
                                NULL, NULL);
      object_class_property_set_description(oc, "acpi",
                                            "Enable ACPI");
 +
 +    object_class_property_add(oc, "iommu-sys", "OnOffAuto",
 +                              virt_get_iommu_sys, virt_set_iommu_sys,
 +                              NULL, NULL);
 +    object_class_property_set_description(oc, "iommu-sys",
 +                                          "Enable IOMMU platform device");
  }
  static const TypeInfo virt_machine_typeinfo = {
 --
-.28.0
+.47.1

-New patch
+[PULL 07/39] hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 MSIx support is added in the RISC-V IOMMU platform device by including
 the required MSIx facilities to alow software to properly setup the MSIx
 subsystem.
 We took inspiration of what is being done in the riscv-iommu-pci device,
 mainly msix_init() and msix_notify(), while keeping in mind that
 riscv-iommu-sys isn't a true PCI device and we don't need to copy/paste
 all the contents of these MSIx functions.
 Two extra MSI MemoryRegions were added: 'msix-table' and 'msix-pba'.
 They are used to manage r/w of the MSI table and Pending Bit Array (PBA)
 respectively. Both are subregions of the main IOMMU memory region,
 iommu->regs_mr, initialized during riscv_iommu_realize(), and each one
 has their own handlers for MSIx reads and writes.
 This is the expected memory map when using this device in the 'virt'
 machine:
     0000000003010000-0000000003010fff (prio 0, i/o): riscv-iommu-regs
       0000000003010300-000000000301034f (prio 0, i/o): msix-table
       0000000003010400-0000000003010407 (prio 0, i/o): msix-pba
 We're now able to set IGS to RISCV_IOMMU_CAP_IGS_BOTH, and userspace is
 free to decide which interrupt model to use.
 Enabling MSIx support for this device in the 'virt' machine requires
 adding 'msi-parent' in the iommu-sys DT.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20241106133407.604587-6-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  hw/riscv/riscv-iommu-sys.c | 116 +++++++++++++++++++++++++++++++++++--
  hw/riscv/virt.c            |   6 +-
  hw/riscv/trace-events      |   2 +
 files changed, 119 insertions(+), 5 deletions(-)
 diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/riscv-iommu-sys.c
 +++ b/hw/riscv/riscv-iommu-sys.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/host-utils.h"
  #include "qemu/module.h"
  #include "qom/object.h"
 +#include "exec/exec-all.h"
 +#include "trace.h"
  #include "riscv-iommu.h"
  #define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
 +#define RISCV_IOMMU_PCI_MSIX_VECTORS 5
 +
  /* RISC-V IOMMU System Platform Device Emulation */
  struct RISCVIOMMUStateSys {
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUStateSys {
      uint32_t         base_irq;
      DeviceState      *irqchip;
      RISCVIOMMUState  iommu;
 +
 +    /* Wired int support */
      qemu_irq         irqs[RISCV_IOMMU_INTR_COUNT];
 +
 +    /* Memory Regions for MSIX table and pending bit entries. */
 +    MemoryRegion msix_table_mmio;
 +    MemoryRegion msix_pba_mmio;
 +    uint8_t *msix_table;
 +    uint8_t *msix_pba;
 +};
 +
 +static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
 +                                     unsigned size)
 +{
 +    RISCVIOMMUStateSys *s = opaque;
 +
 +    g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE);
 +    return pci_get_long(s->msix_table + addr);
 +}
 +
 +static void msix_table_mmio_write(void *opaque, hwaddr addr,
 +                                  uint64_t val, unsigned size)
 +{
 +    RISCVIOMMUStateSys *s = opaque;
 +
 +    g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE);
 +    pci_set_long(s->msix_table + addr, val);
 +}
 +
 +static const MemoryRegionOps msix_table_mmio_ops = {
 +    .read = msix_table_mmio_read,
 +    .write = msix_table_mmio_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 8,
 +    },
 +    .impl = {
 +        .max_access_size = 4,
 +    },
 +};
 +
 +static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
 +                                   unsigned size)
 +{
 +    RISCVIOMMUStateSys *s = opaque;
 +
 +    return pci_get_long(s->msix_pba + addr);
 +}
 +
 +static void msix_pba_mmio_write(void *opaque, hwaddr addr,
 +                                uint64_t val, unsigned size)
 +{
 +}
 +
 +static const MemoryRegionOps msix_pba_mmio_ops = {
 +    .read = msix_pba_mmio_read,
 +    .write = msix_pba_mmio_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 8,
 +    },
 +    .impl = {
 +        .max_access_size = 4,
 +    },
  };
 +static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s,
 +                                        uint32_t n_vectors)
 +{
 +    RISCVIOMMUState *iommu = &s->iommu;
 +    uint32_t table_size = table_size = n_vectors * PCI_MSIX_ENTRY_SIZE;
 +    uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG;
 +    uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8;
 +    uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256;
 +
 +    s->msix_table = g_malloc0(table_size);
 +    s->msix_pba = g_malloc0(pba_size);
 +
 +    memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio_ops,
 +                          s, "msix-table", table_size);
 +    memory_region_add_subregion(&iommu->regs_mr, table_offset,
 +                                &s->msix_table_mmio);
 +
 +    memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops, s,
 +                          "msix-pba", pba_size);
 +    memory_region_add_subregion(&iommu->regs_mr, pba_offset,
 +                                &s->msix_pba_mmio);
 +}
 +
 +static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s,
 +                                        uint32_t vector)
 +{
 +    uint8_t *table_entry = s->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
 +    uint64_t msi_addr = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
 +    uint32_t msi_data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
 +    MemTxResult result;
 +
 +    address_space_stl_le(&address_space_memory, msi_addr,
 +                         msi_data, MEMTXATTRS_UNSPECIFIED, &result);
 +    trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result);
 +}
 +
  static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
                                        unsigned vector)
  {
      RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu);
      uint32_t fctl =  riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
 -    /* We do not support MSIs yet */
 -    if (!(fctl & RISCV_IOMMU_FCTL_WSI)) {
 +    if (fctl & RISCV_IOMMU_FCTL_WSI) {
 +        qemu_irq_pulse(s->irqs[vector]);
 +        trace_riscv_iommu_sys_irq_sent(vector);
          return;
      }
 -    qemu_irq_pulse(s->irqs[vector]);
 +    riscv_iommu_sysdev_send_MSI(s, vector);
  }
  static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
          irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i);
          sysbus_connect_irq(sysdev, i, irq);
      }
 +
 +    riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS);
  }
  static void riscv_iommu_sys_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_sys_init(Object *obj)
      qdev_alias_all_properties(DEVICE(iommu), obj);
      iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
 -    riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI);
 +    riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH);
  }
  static Property riscv_iommu_sys_properties[] = {
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
  }
  static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
 +                                 uint32_t msi_phandle,
                                   uint32_t *iommu_sys_phandle)
  {
      const char comp[] = "riscv,iommu";
@@ -XXX,XX +XXX,XX @@ static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
          iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
          iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
 +    qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle);
 +
      *iommu_sys_phandle = iommu_phandle;
  }
@@ -XXX,XX +XXX,XX @@ static void finalize_fdt(RISCVVirtState *s)
      create_fdt_virtio(s, virt_memmap, irq_virtio_phandle);
      if (virt_is_iommu_sys_enabled(s)) {
 -        create_fdt_iommu_sys(s, irq_mmio_phandle, &iommu_sys_phandle);
 +        create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle,
 +                             &iommu_sys_phandle);
      }
      create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle,
                      iommu_sys_phandle);
 diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/trace-events
 +++ b/hw/riscv/trace-events
@@ -XXX,XX +XXX,XX @@ riscv_iommu_icvec_write(uint32_t orig, uint32_t actual) "ICVEC write: incoming 0
  riscv_iommu_ats(const char *id, unsigned b, unsigned d, unsigned f, uint64_t iova) "%s: translate request %04x:%02x.%u iova: 0x%"PRIx64
  riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb invalidate"
  riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group response"
 +riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u"
 +riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x result %u"
 --
 .47.1

-[PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
+[PULL 08/39] hw/riscv/riscv-iommu: implement reset protocol
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
+Add a riscv_iommu_reset() helper in the base emulation code that
-wires 4 of them out. Let's connect all 5 MMUARTs.
+implements the expected reset behavior as defined by the riscv-iommu
+spec.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Devices can then use this helper in their own reset callbacks.
-Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20241106133407.604587-7-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
+ hw/riscv/riscv-iommu.h     |  1 +
- hw/riscv/microchip_pfsoc.c         | 30 ++++++++++++++++++++++++++++++
+ include/hw/riscv/iommu.h   |  6 ++++--
- hw/riscv/Kconfig                   |  1 +
+ hw/riscv/riscv-iommu-pci.c | 20 ++++++++++++++++++++
-files changed, 51 insertions(+)
+ hw/riscv/riscv-iommu-sys.c | 20 ++++++++++++++++++++
+ hw/riscv/riscv-iommu.c     | 35 +++++++++++++++++++++++++++++++++++
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+ hw/riscv/trace-events      |  2 ++
-index XXXXXXX..XXXXXXX 100644
+files changed, 82 insertions(+), 2 deletions(-)
---- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/riscv-iommu.h
 +++ b/hw/riscv/riscv-iommu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
  void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
           Error **errp);
  void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode);
 +void riscv_iommu_reset(RISCVIOMMUState *s);
  /* private helpers */
 diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/riscv/iommu.h
 +++ b/include/hw/riscv/iommu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVIOMMUState RISCVIOMMUState;
  typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
  #define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
 -OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
 +OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PCI)
  typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
 +typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass;
  #define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
 -OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
 +OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SYS)
  typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
 +typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass;
  #define FDT_IRQ_TYPE_EDGE_LOW 1
 diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/riscv-iommu-pci.c
 +++ b/hw/riscv/riscv-iommu-pci.c
 @@ -XXX,XX +XXX,XX @@
- #ifndef HW_MICROCHIP_PFSOC_H
+ #include "cpu_bits.h"
- #define HW_MICROCHIP_PFSOC_H
+ #include "riscv-iommu.h"
+ #include "riscv-iommu-bits.h"
-+#include "hw/char/mchp_pfsoc_mmuart.h"
++#include "trace.h"
-+
- typedef struct MicrochipPFSoCState {
+ /* RISC-V IOMMU PCI Device Emulation */
-     /*< private >*/
+ #define RISCV_PCI_CLASS_SYSTEM_IOMMU     0x0806
-     DeviceState parent_obj;
+@@ -XXX,XX +XXX,XX @@ typedef struct RISCVIOMMUStatePci {
-@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
+     RISCVIOMMUState  iommu;   /* common IOMMU state */
-     RISCVHartArrayState e_cpus;
+ } RISCVIOMMUStatePci;
-     RISCVHartArrayState u_cpus;
-     DeviceState *plic;
++struct RISCVIOMMUPciClass {
-+    MchpPfSoCMMUartState *serial0;
++    /*< public >*/
-+    MchpPfSoCMMUartState *serial1;
++    DeviceRealize parent_realize;
-+    MchpPfSoCMMUartState *serial2;
++    ResettablePhases parent_phases;
-+    MchpPfSoCMMUartState *serial3;
++};
-+    MchpPfSoCMMUartState *serial4;
++
- } MicrochipPFSoCState;
+ /* interrupt delivery callback */
+ static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector)
- #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
+ {
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ static const Property riscv_iommu_pci_properties[] = {
-     MICROCHIP_PFSOC_L2CC,
+     DEFINE_PROP_END_OF_LIST(),
      MICROCHIP_PFSOC_L2LIM,
      MICROCHIP_PFSOC_PLIC,
 +    MICROCHIP_PFSOC_MMUART0,
      MICROCHIP_PFSOC_SYSREG,
      MICROCHIP_PFSOC_MPUCFG,
 +    MICROCHIP_PFSOC_MMUART1,
 +    MICROCHIP_PFSOC_MMUART2,
 +    MICROCHIP_PFSOC_MMUART3,
 +    MICROCHIP_PFSOC_MMUART4,
      MICROCHIP_PFSOC_ENVM_CFG,
      MICROCHIP_PFSOC_ENVM_DATA,
      MICROCHIP_PFSOC_IOSCB_CFG,
      MICROCHIP_PFSOC_DRAM,
  };
-+enum {
++static void riscv_iommu_pci_reset_hold(Object *obj, ResetType type)
-+    MICROCHIP_PFSOC_MMUART0_IRQ = 90,
++{
-+    MICROCHIP_PFSOC_MMUART1_IRQ = 91,
++    RISCVIOMMUStatePci *pci = RISCV_IOMMU_PCI(obj);
-+    MICROCHIP_PFSOC_MMUART2_IRQ = 92,
++    RISCVIOMMUState *iommu = &pci->iommu;
-+    MICROCHIP_PFSOC_MMUART3_IRQ = 93,
++
-+    MICROCHIP_PFSOC_MMUART4_IRQ = 94,
++    riscv_iommu_reset(iommu);
 +
 +    trace_riscv_iommu_pci_reset_hold(type);
 +}
 +
  static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
      PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +
 +    rc->phases.hold = riscv_iommu_pci_reset_hold;
      k->realize = riscv_iommu_pci_realize;
      k->exit = riscv_iommu_pci_exit;
 diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/riscv-iommu-sys.c
 +++ b/hw/riscv/riscv-iommu-sys.c
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUStateSys {
      uint8_t *msix_pba;
  };
 +struct RISCVIOMMUSysClass {
 +    /*< public >*/
 +    DeviceRealize parent_realize;
 +    ResettablePhases parent_phases;
 +};
 +
- #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
+ static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
- #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
+                                      unsigned size)
+ {
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+@@ -XXX,XX +XXX,XX @@ static Property riscv_iommu_sys_properties[] = {
-index XXXXXXX..XXXXXXX 100644
+     DEFINE_PROP_END_OF_LIST(),
---- a/hw/riscv/microchip_pfsoc.c
+ };
-+++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@
++static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type)
-  * 0) CLINT (Core Level Interruptor)
++{
-  * 1) PLIC (Platform Level Interrupt Controller)
++    RISCVIOMMUStateSys *sys = RISCV_IOMMU_SYS(obj);
-  * 2) eNVM (Embedded Non-Volatile Memory)
++    RISCVIOMMUState *iommu = &sys->iommu;
-+ * 3) MMUARTs (Multi-Mode UART)
++
-  *
++    riscv_iommu_reset(iommu);
-  * This board currently generates devicetree dynamically that indicates at least
++
-  * two harts and up to five harts.
++    trace_riscv_iommu_sys_reset_hold(type);
-@@ -XXX,XX +XXX,XX @@
++}
- #include "hw/irq.h"
++
- #include "hw/loader.h"
+ static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
- #include "hw/sysbus.h"
+ {
-+#include "chardev/char.h"
+     DeviceClass *dc = DEVICE_CLASS(klass);
- #include "hw/cpu/cluster.h"
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
- #include "target/riscv/cpu.h"
++
- #include "hw/misc/unimp.h"
++    rc->phases.hold = riscv_iommu_sys_reset_hold;
-@@ -XXX,XX +XXX,XX @@
++
- #include "hw/riscv/sifive_clint.h"
+     dc->realize = riscv_iommu_sys_realize;
- #include "hw/riscv/sifive_plic.h"
+     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
- #include "hw/riscv/microchip_pfsoc.h"
+     device_class_set_props(dc, riscv_iommu_sys_properties);
-+#include "sysemu/sysemu.h"
+diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
+index XXXXXXX..XXXXXXX 100644
- /*
+--- a/hw/riscv/riscv-iommu.c
-  * The BIOS image used by this machine is called Hart Software Services (HSS).
++++ b/hw/riscv/riscv-iommu.c
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
+@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_unrealize(DeviceState *dev)
-     [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
+     g_hash_table_unref(s->ctx_cache);
-     [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
+ }
-     [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
-+    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
++void riscv_iommu_reset(RISCVIOMMUState *s)
-     [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
++{
-     [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
++    uint32_t reg_clr;
-+    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
++    int ddtp_mode;
-+    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
++
-+    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
++    /*
-+    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
++     * Clear DDTP while setting DDTP_mode back to user
-     [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
++     * initial setting.
-     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
++     */
-     [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
++    ddtp_mode = s->enable_off ?
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
++                RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE;
-         memmap[MICROCHIP_PFSOC_MPUCFG].base,
++    s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, ddtp_mode);
-         memmap[MICROCHIP_PFSOC_MPUCFG].size);
++    riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_DDTP, s->ddtp);
++
-+    /* MMUARTs */
++    reg_clr = RISCV_IOMMU_CQCSR_CQEN | RISCV_IOMMU_CQCSR_CIE |
-+    s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
++              RISCV_IOMMU_CQCSR_CQON | RISCV_IOMMU_CQCSR_BUSY;
-+        memmap[MICROCHIP_PFSOC_MMUART0].base,
++    riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, 0, reg_clr);
-+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
++
-+        serial_hd(0));
++    reg_clr = RISCV_IOMMU_FQCSR_FQEN | RISCV_IOMMU_FQCSR_FIE |
-+    s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
++              RISCV_IOMMU_FQCSR_FQON | RISCV_IOMMU_FQCSR_BUSY;
-+        memmap[MICROCHIP_PFSOC_MMUART1].base,
++    riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_FQCSR, 0, reg_clr);
-+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
++
-+        serial_hd(1));
++    reg_clr = RISCV_IOMMU_PQCSR_PQEN | RISCV_IOMMU_PQCSR_PIE |
-+    s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
++              RISCV_IOMMU_PQCSR_PQON | RISCV_IOMMU_PQCSR_BUSY;
-+        memmap[MICROCHIP_PFSOC_MMUART2].base,
++    riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, 0, reg_clr);
-+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
++
-+        serial_hd(2));
++    riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_TR_REQ_CTL, 0,
-+    s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
++                          RISCV_IOMMU_TR_REQ_CTL_GO_BUSY);
-+        memmap[MICROCHIP_PFSOC_MMUART3].base,
++
-+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
++    riscv_iommu_reg_set32(s, RISCV_IOMMU_REG_IPSR, 0);
-+        serial_hd(3));
++
-+    s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
++    g_hash_table_remove_all(s->ctx_cache);
-+        memmap[MICROCHIP_PFSOC_MMUART4].base,
++    g_hash_table_remove_all(s->iot_cache);
-+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
++}
-+        serial_hd(4));
++
-+
+ static const Property riscv_iommu_properties[] = {
-     /* eNVM */
+     DEFINE_PROP_UINT32("version", RISCVIOMMUState, version,
-     memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
+         RISCV_IOMMU_SPEC_DOT_VER),
-                            memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
+diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/trace-events
---- a/hw/riscv/Kconfig
++++ b/hw/riscv/trace-events
-+++ b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb invalidate"
-@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
+ riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group response"
-     select HART
+ riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u"
-     select SIFIVE
+ riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x result %u"
-     select UNIMP
++riscv_iommu_sys_reset_hold(int reset_type) "reset type %d"
-+    select MCHP_PFSOC_MMUART
++riscv_iommu_pci_reset_hold(int reset_type) "reset type %d"
 --
-.28.0
+.47.1

-New patch
+[PULL 09/39] docs/specs: add riscv-iommu-sys information
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20241106133407.604587-8-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ docs/specs/riscv-iommu.rst | 30 +++++++++++++++++++++++++++---
+ docs/system/riscv/virt.rst | 10 ++++++++++
+files changed, 37 insertions(+), 3 deletions(-)
+diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/specs/riscv-iommu.rst
++++ b/docs/specs/riscv-iommu.rst
+@@ -XXX,XX +XXX,XX @@ RISC-V IOMMU support for RISC-V machines
+ QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
+ version 1.0 `iommu1.0`_.
+-The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
+-RISC-V boards can use.  The 'virt' RISC-V machine is compatible with this
+-device.
++The emulation includes a PCI reference device (riscv-iommu-pci) and a platform
++bus device (riscv-iommu-sys) that QEMU RISC-V boards can use.  The 'virt'
++RISC-V machine is compatible with both devices.
+ riscv-iommu-pci reference device
+ --------------------------------
+@@ -XXX,XX +XXX,XX @@ Several options are available to control the capabilities of the device, namely:
+ - "s-stage": enable s-stage support
+ - "g-stage": enable g-stage support
++riscv-iommu-sys device
++----------------------
++
++This device implements the RISC-V IOMMU emulation as a platform bus device that
++RISC-V boards can use.
++
++For the 'virt' board the device is disabled by default.  To enable it use the
++'iommu-sys' machine option:
++
++.. code-block:: bash
++
++  $ qemu-system-riscv64 -M virt,iommu-sys=on (...)
++
++There is no options to configure the capabilities of this device in the 'virt'
++board using the QEMU command line.  The device is configured with the following
++riscv-iommu options:
++
++- "ioatc-limit": default value (2Mb)
++- "intremap": enabled
++- "ats": enabled
++- "off": on (DMA disabled)
++- "s-stage": enabled
++- "g-stage": enabled
++
+ .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
+ .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/
+diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/riscv/virt.rst
++++ b/docs/system/riscv/virt.rst
+@@ -XXX,XX +XXX,XX @@ command line:
+   $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...)
++It also has support for the riscv-iommu-sys platform device:
++
++.. code-block:: bash
++
++  $ qemu-system-riscv64 -M virt,iommu-sys=on (...)
++
+ Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU support
+ works.
+@@ -XXX,XX +XXX,XX @@ The following machine-specific options are supported:
+   having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
+   the default number of per-HART VS-level AIA IMSIC pages is 0.
++- iommu-sys=[on|off]
++
++  Enables the riscv-iommu-sys platform device. Defaults to 'off'.
++
+ Running Linux kernel
+ --------------------
+--
+.47.1

-New patch
+[PULL 10/39] target/riscv: Add Tenstorrent Ascalon CPU
+From: Anton Blanchard <antonb@tenstorrent.com>
+Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
+wide RV64 cores. More details can be found at
+https://tenstorrent.com/ip/tt-ascalon
+Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-ID: <20241113110459.1607299-1-antonb@tenstorrent.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu-qom.h |  1 +
+ target/riscv/cpu.c     | 67 ++++++++++++++++++++++++++++++++++++++++++
+files changed, 68 insertions(+)
+diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu-qom.h
++++ b/target/riscv/cpu-qom.h
+@@ -XXX,XX +XXX,XX @@
+ #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
+ #define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
+ #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
++#define TYPE_RISCV_CPU_TT_ASCALON       RISCV_CPU_TYPE_NAME("tt-ascalon")
+ #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
+ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void rv64_veyron_v1_cpu_init(Object *obj)
+ #endif
+ }
++/* Tenstorrent Ascalon */
++static void rv64_tt_ascalon_cpu_init(Object *obj)
++{
++    CPURISCVState *env = &RISCV_CPU(obj)->env;
++    RISCVCPU *cpu = RISCV_CPU(obj);
++
++    riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV);
++    env->priv_ver = PRIV_VERSION_1_13_0;
++
++    /* Enable ISA extensions */
++    cpu->cfg.mmu = true;
++    cpu->cfg.vlenb = 256 >> 3;
++    cpu->cfg.elen = 64;
++    cpu->env.vext_ver = VEXT_VERSION_1_00_0;
++    cpu->cfg.rvv_ma_all_1s = true;
++    cpu->cfg.rvv_ta_all_1s = true;
++    cpu->cfg.misa_w = true;
++    cpu->cfg.pmp = true;
++    cpu->cfg.cbom_blocksize = 64;
++    cpu->cfg.cbop_blocksize = 64;
++    cpu->cfg.cboz_blocksize = 64;
++    cpu->cfg.ext_zic64b = true;
++    cpu->cfg.ext_zicbom = true;
++    cpu->cfg.ext_zicbop = true;
++    cpu->cfg.ext_zicboz = true;
++    cpu->cfg.ext_zicntr = true;
++    cpu->cfg.ext_zicond = true;
++    cpu->cfg.ext_zicsr = true;
++    cpu->cfg.ext_zifencei = true;
++    cpu->cfg.ext_zihintntl = true;
++    cpu->cfg.ext_zihintpause = true;
++    cpu->cfg.ext_zihpm = true;
++    cpu->cfg.ext_zimop = true;
++    cpu->cfg.ext_zawrs = true;
++    cpu->cfg.ext_zfa = true;
++    cpu->cfg.ext_zfbfmin = true;
++    cpu->cfg.ext_zfh = true;
++    cpu->cfg.ext_zfhmin = true;
++    cpu->cfg.ext_zcb = true;
++    cpu->cfg.ext_zcmop = true;
++    cpu->cfg.ext_zba = true;
++    cpu->cfg.ext_zbb = true;
++    cpu->cfg.ext_zbs = true;
++    cpu->cfg.ext_zkt = true;
++    cpu->cfg.ext_zvbb = true;
++    cpu->cfg.ext_zvbc = true;
++    cpu->cfg.ext_zvfbfmin = true;
++    cpu->cfg.ext_zvfbfwma = true;
++    cpu->cfg.ext_zvfh = true;
++    cpu->cfg.ext_zvfhmin = true;
++    cpu->cfg.ext_zvkng = true;
++    cpu->cfg.ext_smaia = true;
++    cpu->cfg.ext_smstateen = true;
++    cpu->cfg.ext_ssaia = true;
++    cpu->cfg.ext_sscofpmf = true;
++    cpu->cfg.ext_sstc = true;
++    cpu->cfg.ext_svade = true;
++    cpu->cfg.ext_svinval = true;
++    cpu->cfg.ext_svnapot = true;
++    cpu->cfg.ext_svpbmt = true;
++
++#ifndef CONFIG_USER_ONLY
++    set_satp_mode_max_supported(cpu, VM_1_10_SV57);
++#endif
++}
++
+ #ifdef CONFIG_TCG
+ static void rv128_base_cpu_init(Object *obj)
+ {
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
+     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,  rv64_sifive_u_cpu_init),
+     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C,   MXL_RV64,  rv64_sifive_u_cpu_init),
+     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,  rv64_thead_c906_cpu_init),
++    DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64,  rv64_tt_ascalon_cpu_init),
+     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1,  MXL_RV64,  rv64_veyron_v1_cpu_init),
+ #ifdef CONFIG_TCG
+     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,   MXL_RV128, rv128_base_cpu_init),
+--
+.47.1

-New patch
+[PULL 11/39] hw/intc/riscv_aplic: rename is_kvm_aia()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+The helper is_kvm_aia() is checking not only for AIA, but for
+aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an
+in-kernel chip present.
+Rename it to be a bit clear what the helper is doing since we'll add
+more AIA helpers in the next patches.
+Make the helper public because the 'virt' machine will use it as well.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20241119191706.718860-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ include/hw/intc/riscv_aplic.h | 1 +
+ hw/intc/riscv_aplic.c         | 8 ++++----
+files changed, 5 insertions(+), 4 deletions(-)
+diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/riscv_aplic.h
++++ b/include/hw/intc/riscv_aplic.h
+@@ -XXX,XX +XXX,XX @@ struct RISCVAPLICState {
+ };
+ void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
++bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
+ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+     uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/riscv_aplic.c
++++ b/hw/intc/riscv_aplic.c
+@@ -XXX,XX +XXX,XX @@
+  * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use
+  * APLIC Wired.
+  */
+-static bool is_kvm_aia(bool msimode)
++bool riscv_is_kvm_aia_aplic_imsic(bool msimode)
+ {
+     return kvm_irqchip_in_kernel() && msimode;
+ }
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
+     uint32_t i;
+     RISCVAPLICState *aplic = RISCV_APLIC(dev);
+-    if (!is_kvm_aia(aplic->msimode)) {
++    if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
+         aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
+         aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
+         aplic->state = g_new0(uint32_t, aplic->num_irqs);
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
+      * have IRQ lines delegated by their parent APLIC.
+      */
+     if (!aplic->parent) {
+-        if (kvm_enabled() && is_kvm_aia(aplic->msimode)) {
++        if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
+             qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
+         } else {
+             qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+-    if (!is_kvm_aia(msimode)) {
++    if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
+         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+     }
+--
+.47.1

-New patch
+[PULL 12/39] hw/riscv/virt.c: reduce virt_use_kvm_aia() usage
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+In create_fdt_sockets() we have the following pattern:
+    if (kvm_enabled() && virt_use_kvm_aia(s)) {
+        (... do stuff ...)
+    } else {
+        (... do other stuff ...)
+    }
+    if (kvm_enabled() && virt_use_kvm_aia(s)) {
+        (... do more stuff ...)
+    } else {
+        (... do more other stuff)
+    }
+Do everything in a single if/else clause to reduce the usage of
+virt_use_kvm_aia() helper and to make the code a bit less repetitive.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20241119191706.718860-3-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/virt.c | 10 ++++------
+file changed, 4 insertions(+), 6 deletions(-)
+diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/virt.c
++++ b/hw/riscv/virt.c
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
+                                 msi_m_phandle, msi_s_phandle, phandle,
+                                 &intc_phandles[0], xplic_phandles,
+                                 ms->smp.cpus);
++
++        *irq_mmio_phandle = xplic_phandles[0];
++        *irq_virtio_phandle = xplic_phandles[0];
++        *irq_pcie_phandle = xplic_phandles[0];
+     } else {
+         phandle_pos = ms->smp.cpus;
+         for (socket = (socket_count - 1); socket >= 0; socket--) {
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
+                                         s->soc[socket].num_harts);
+             }
+         }
+-    }
+-    if (kvm_enabled() && virt_use_kvm_aia(s)) {
+-        *irq_mmio_phandle = xplic_phandles[0];
+-        *irq_virtio_phandle = xplic_phandles[0];
+-        *irq_pcie_phandle = xplic_phandles[0];
+-    } else {
+         for (socket = 0; socket < socket_count; socket++) {
+             if (socket == 0) {
+                 *irq_mmio_phandle = xplic_phandles[socket];
+--
+.47.1

-New patch
+[PULL 13/39] hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c,
+the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with
+in-kernel irqchip enabled. It is not checking for a generic AIA support.
+Rename the helper to virt_use_kvm_aia_aplic_imsic() to reflect what the
+helper is doing, and use the existing riscv_is_kvm_aia_aplic_imsic() to
+obscure details such as the presence of the in-kernel irqchip.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20241119191706.718860-4-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/virt.c | 12 +++++++-----
+file changed, 7 insertions(+), 5 deletions(-)
+diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/virt.c
++++ b/hw/riscv/virt.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/virtio/virtio-iommu.h"
+ /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
+-static bool virt_use_kvm_aia(RISCVVirtState *s)
++static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
+ {
+-    return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
++    bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
++
++    return riscv_is_kvm_aia_aplic_imsic(msimode);
+ }
+ static bool virt_aclint_allowed(void)
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
+         *msi_pcie_phandle = msi_s_phandle;
+     }
+-    /* KVM AIA only has one APLIC instance */
+-    if (kvm_enabled() && virt_use_kvm_aia(s)) {
++    /* KVM AIA aplic-imsic only has one APLIC instance */
++    if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
+         create_fdt_socket_aplic(s, memmap, 0,
+                                 msi_m_phandle, msi_s_phandle, phandle,
+                                 &intc_phandles[0], xplic_phandles,
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+         }
+     }
+-    if (kvm_enabled() && virt_use_kvm_aia(s)) {
++    if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
+         kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
+                              VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
+                              memmap[VIRT_APLIC_S].base,
+--
+.47.1

-New patch
+[PULL 14/39] target/riscv/kvm: consider irqchip_split() in aia_create()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Before adding support to kernel-irqchip=split when using KVM AIA we need
+to change how we create the in-kernel AIA device.
+In the use case we have so far, i.e. in-kernel irqchip without split
+mode, both the s-mode APLIC and IMSIC controllers are provided by the
+irqchip. In irqchip_split() mode we'll emulate the s-mode APLIC
+controller, which will send MSIs to the in-kernel IMSIC controller. To
+do that we need to change kvm_riscv_aia_create() to not create the
+in-kernel s-mode APLIC controller.
+In the kernel source arch/riscv/kvm/aia_aplic.c, function
+kvm_riscv_aia_aplic_init(), we verify that the APLIC controller won't be
+instantiated by KVM if we do not set 'nr_sources', which is set via
+KVM_DEV_RISCV_AIA_CONFIG_SRCS. For QEMU this means that we should not
+set 'aia_irq_num' during kvm_riscv_aia_create() in irqchip_split() mode.
+In this same condition, skip KVM_DEV_RISCV_AIA_ADDR_APLIC as well since
+it is used to set the base address for the in-kernel APLIC controller.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20241119191706.718860-5-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm/kvm-cpu.c | 38 +++++++++++++++++++++++---------------
+file changed, 23 insertions(+), 15 deletions(-)
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm/kvm-cpu.c
++++ b/target/riscv/kvm/kvm-cpu.c
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+         }
+     }
+-    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+-                            KVM_DEV_RISCV_AIA_CONFIG_SRCS,
+-                            &aia_irq_num, true, NULL);
+-    if (ret < 0) {
+-        error_report("KVM AIA: failed to set number of input irq lines");
+-        exit(1);
+-    }
++    /*
++     * Skip APLIC creation in KVM if we're running split mode.
++     * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS
++     * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC
++     * since KVM won't be using it.
++     */
++    if (!kvm_kernel_irqchip_split()) {
++        ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
++                                KVM_DEV_RISCV_AIA_CONFIG_SRCS,
++                                &aia_irq_num, true, NULL);
++        if (ret < 0) {
++            error_report("KVM AIA: failed to set number of input irq lines");
++            exit(1);
++        }
++
++        ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
++                                KVM_DEV_RISCV_AIA_ADDR_APLIC,
++                                &aplic_base, true, NULL);
++        if (ret < 0) {
++            error_report("KVM AIA: failed to set the base address of APLIC");
++            exit(1);
++        }
++     }
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                             KVM_DEV_RISCV_AIA_CONFIG_IDS,
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+         exit(1);
+     }
+-    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
+-                            KVM_DEV_RISCV_AIA_ADDR_APLIC,
+-                            &aplic_base, true, NULL);
+-    if (ret < 0) {
+-        error_report("KVM AIA: failed to set the base address of APLIC");
+-        exit(1);
+-    }
+-
+     for (socket = 0; socket < socket_count; socket++) {
+         socket_imsic_base = imsic_base + socket * (1U << group_shift);
+         hart_count = riscv_socket_hart_count(machine, socket);
+--
+.47.1

-[PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc
+[PULL 15/39] hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+The current logic to determine if we don't need an emulated APLIC
-should only contain the RISC-V SoC / machine codes plus generic
+controller, i.e. KVM will provide for us, is to determine if we're
-codes. Let's move sifive_plic model to hw/intc directory.
+running KVM, with in-kernel irqchip support, and running
 aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and
 virt_use_kvm_aia_aplic_imsic().
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+This won't suffice to support irqchip_split() mode: it will match
 exactly the same conditions as the one above, but setting the irqchip to
 'split' mode will now require us to emulate an APLIC s-mode controller,
 like we're doing with 'aia=aplic'.
 Create a new riscv_use_emulated_aplic() helper that will encapsulate
 this logic. Replace the uses of "riscv_is_kvm_aia_aplic_imsic()" with
 this helper every time we're taking a decision on emulate an APLIC
 controller or not. Do the same in virt.c with virt_use_emulated_aplic().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241119191706.718860-6-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- {include/hw/riscv => hw/intc}/sifive_plic.h | 0
+ include/hw/intc/riscv_aplic.h |  1 +
- hw/{riscv => intc}/sifive_plic.c            | 2 +-
+ hw/intc/riscv_aplic.c         | 24 +++++++++++++++++++++---
- hw/riscv/microchip_pfsoc.c                  | 2 +-
+ hw/riscv/virt.c               | 14 ++++++++++++--
- hw/riscv/sifive_e.c                         | 2 +-
+files changed, 34 insertions(+), 5 deletions(-)
  hw/riscv/sifive_u.c                         | 2 +-
  hw/riscv/virt.c                             | 2 +-
  hw/intc/Kconfig                             | 3 +++
  hw/intc/meson.build                         | 1 +
  hw/riscv/Kconfig                            | 5 +++++
  hw/riscv/meson.build                        | 1 -
 files changed, 14 insertions(+), 6 deletions(-)
  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
  rename hw/{riscv => intc}/sifive_plic.c (99%)
-diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
+diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
 similarity index 100%
 rename from include/hw/riscv/sifive_plic.h
 rename to hw/intc/sifive_plic.h
 diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
 similarity index 99%
 rename from hw/riscv/sifive_plic.c
 rename to hw/intc/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_plic.c
+--- a/include/hw/intc/riscv_aplic.h
-+++ b/hw/intc/sifive_plic.c
++++ b/include/hw/intc/riscv_aplic.h
@@ -XXX,XX +XXX,XX @@ struct RISCVAPLICState {
  void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
  bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
 +bool riscv_use_emulated_aplic(bool msimode);
  DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
      uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
 diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/riscv_aplic.c
 +++ b/hw/intc/riscv_aplic.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/pci/msi.h"
- #include "hw/boards.h"
- #include "hw/qdev-properties.h"
-+#include "hw/intc/sifive_plic.h"
  #include "target/riscv/cpu.h"
  #include "sysemu/sysemu.h"
--#include "hw/riscv/sifive_plic.h"
+ #include "sysemu/kvm.h"
++#include "sysemu/tcg.h"
- #define RISCV_DEBUG_PLIC 0
+ #include "kvm/kvm_riscv.h"
+ #include "migration/vmstate.h"
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ bool riscv_is_kvm_aia_aplic_imsic(bool msimode)
---- a/hw/riscv/microchip_pfsoc.c
+     return kvm_irqchip_in_kernel() && msimode;
-+++ b/hw/riscv/microchip_pfsoc.c
+ }
-@@ -XXX,XX +XXX,XX @@
- #include "hw/misc/unimp.h"
++bool riscv_use_emulated_aplic(bool msimode)
- #include "hw/riscv/boot.h"
++{
- #include "hw/riscv/riscv_hart.h"
++#ifdef CONFIG_KVM
--#include "hw/riscv/sifive_plic.h"
++    if (tcg_enabled()) {
- #include "hw/riscv/microchip_pfsoc.h"
++        return true;
- #include "hw/intc/sifive_clint.h"
++    }
-+#include "hw/intc/sifive_plic.h"
++
- #include "sysemu/sysemu.h"
++    if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
++        return true;
- /*
++    }
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
++
-index XXXXXXX..XXXXXXX 100644
++    return kvm_kernel_irqchip_split();
---- a/hw/riscv/sifive_e.c
++#else
-+++ b/hw/riscv/sifive_e.c
++    return true;
-@@ -XXX,XX +XXX,XX @@
++#endif
- #include "hw/misc/unimp.h"
++}
- #include "target/riscv/cpu.h"
++
- #include "hw/riscv/riscv_hart.h"
+ static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic,
--#include "hw/riscv/sifive_plic.h"
+                                           uint32_t irq)
- #include "hw/riscv/sifive_uart.h"
+ {
- #include "hw/riscv/sifive_e.h"
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
- #include "hw/riscv/boot.h"
+     uint32_t i;
- #include "hw/intc/sifive_clint.h"
+     RISCVAPLICState *aplic = RISCV_APLIC(dev);
-+#include "hw/intc/sifive_plic.h"
- #include "hw/misc/sifive_e_prci.h"
+-    if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
- #include "chardev/char.h"
++    if (riscv_use_emulated_aplic(aplic->msimode)) {
- #include "sysemu/arch_init.h"
+         aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+         aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
-index XXXXXXX..XXXXXXX 100644
+         aplic->state = g_new0(uint32_t, aplic->num_irqs);
---- a/hw/riscv/sifive_u.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
-+++ b/hw/riscv/sifive_u.c
+      * have IRQ lines delegated by their parent APLIC.
-@@ -XXX,XX +XXX,XX @@
+      */
- #include "hw/misc/unimp.h"
+     if (!aplic->parent) {
- #include "target/riscv/cpu.h"
+-        if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
- #include "hw/riscv/riscv_hart.h"
++        if (kvm_enabled() && !riscv_use_emulated_aplic(aplic->msimode)) {
--#include "hw/riscv/sifive_plic.h"
+             qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
- #include "hw/riscv/sifive_uart.h"
+         } else {
- #include "hw/riscv/sifive_u.h"
+             qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
- #include "hw/riscv/boot.h"
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
- #include "hw/intc/sifive_clint.h"
-+#include "hw/intc/sifive_plic.h"
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- #include "chardev/char.h"
- #include "net/eth.h"
+-    if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
- #include "sysemu/arch_init.h"
++    if (riscv_use_emulated_aplic(msimode)) {
          sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
      }
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
- #include "hw/char/serial.h"
+     return riscv_is_kvm_aia_aplic_imsic(msimode);
- #include "target/riscv/cpu.h"
+ }
- #include "hw/riscv/riscv_hart.h"
--#include "hw/riscv/sifive_plic.h"
++static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type)
- #include "hw/riscv/sifive_test.h"
++{
- #include "hw/riscv/virt.h"
++    bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
  #include "hw/riscv/boot.h"
  #include "hw/riscv/numa.h"
  #include "hw/intc/sifive_clint.h"
 +#include "hw/intc/sifive_plic.h"
  #include "chardev/char.h"
  #include "sysemu/arch_init.h"
  #include "sysemu/device_tree.h"
 diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/Kconfig
 +++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config LOONGSON_LIOINTC
  config SIFIVE_CLINT
      bool
 +
-+config SIFIVE_PLIC
++    return riscv_use_emulated_aplic(msimode);
-+    bool
++}
-diff --git a/hw/intc/meson.build b/hw/intc/meson.build
++
-index XXXXXXX..XXXXXXX 100644
+ static bool virt_aclint_allowed(void)
---- a/hw/intc/meson.build
+ {
-+++ b/hw/intc/meson.build
+     return tcg_enabled() || qtest_enabled();
-@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
+@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
- specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
+         *msi_pcie_phandle = msi_s_phandle;
- specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
+     }
- specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
-+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
+-    /* KVM AIA aplic-imsic only has one APLIC instance */
- specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
+-    if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
- specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
++    /*
- specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
++     * With KVM AIA aplic-imsic, using an irqchip without split
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
++     * mode, we'll use only one APLIC instance.
-index XXXXXXX..XXXXXXX 100644
++     */
---- a/hw/riscv/Kconfig
++    if (!virt_use_emulated_aplic(s->aia_type)) {
-+++ b/hw/riscv/Kconfig
+         create_fdt_socket_aplic(s, memmap, 0,
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
+                                 msi_m_phandle, msi_s_phandle, phandle,
-     select SIFIVE
+                                 &intc_phandles[0], xplic_phandles,
      select SIFIVE_CLINT
      select SIFIVE_GPIO
 +    select SIFIVE_PLIC
      select SIFIVE_E_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select SIFIVE_CLINT
      select SIFIVE_GPIO
      select SIFIVE_PDMA
 +    select SIFIVE_PLIC
      select SIFIVE_U_OTP
      select SIFIVE_U_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SPIKE
      select HTIF
      select SIFIVE
      select SIFIVE_CLINT
 +    select SIFIVE_PLIC
  config OPENTITAN
      bool
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select PFLASH_CFI01
      select SIFIVE
      select SIFIVE_CLINT
 +    select SIFIVE_PLIC
  config MICROCHIP_PFSOC
      bool
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
      select UNIMP
      select MCHP_PFSOC_MMUART
      select SIFIVE_PDMA
 +    select SIFIVE_PLIC
      select CADENCE_SDHCI
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 --
-.28.0
+.47.1

-[PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller
+[PULL 16/39] hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
+The last step to enable KVM AIA aplic-imsic with irqchip in split mode
-controller to move the 2nd stage bootloader in the system memory.
+is to deal with how MSIs are going to be sent. In our current design we
-Let's connect a DMA controller to Microchip PolarFire SoC.
+don't allow an APLIC controller to send MSIs unless it's on m-mode. And
 we also do not allow Supervisor MSI address configuration via the
 'smsiaddrcfg' and 'smsiaddrcfgh' registers unless it's also a m-mode
 APLIC controller.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Add a new RISCVACPLICState attribute called 'kvm_msicfgaddr'. This
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+attribute represents the base configuration address for MSIs, in our
-Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
+case the base addr of the IMSIC controller. This attribute is being set
 only when running irqchip_split() mode with aia=aplic-imsic.
 During riscv_aplic_msi_send() we'll check if the attribute was set to
 skip the check for a m-mode APLIC controller and to change the resulting
 MSI addr by adding kvm_msicfgaddr right before address_space_stl_le().
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20241119191706.718860-7-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
+ include/hw/intc/riscv_aplic.h |  6 +++++
- hw/riscv/microchip_pfsoc.c         | 15 +++++++++++++++
+ hw/intc/riscv_aplic.c         | 42 +++++++++++++++++++++++++++--------
- hw/riscv/Kconfig                   |  1 +
+ hw/riscv/virt.c               |  6 ++++-
-files changed, 27 insertions(+)
+files changed, 44 insertions(+), 10 deletions(-)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/include/hw/intc/riscv_aplic.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/include/hw/intc/riscv_aplic.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct RISCVAPLICState {
- #define HW_MICROCHIP_PFSOC_H
+     uint32_t num_irqs;
+     bool msimode;
- #include "hw/char/mchp_pfsoc_mmuart.h"
+     bool mmode;
-+#include "hw/dma/sifive_pdma.h"
++
- #include "hw/sd/cadence_sdhci.h"
++    /* To support KVM aia=aplic-imsic with irqchip split mode */
++    bool kvm_splitmode;
- typedef struct MicrochipPFSoCState {
++    uint32_t kvm_msicfgaddr;
-@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
++    uint32_t kvm_msicfgaddrH;
      MchpPfSoCMMUartState *serial2;
      MchpPfSoCMMUartState *serial3;
      MchpPfSoCMMUartState *serial4;
 +    SiFivePDMAState dma;
      CadenceSDHCIState sdhci;
  } MicrochipPFSoCState;
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_BUSERR_UNIT4,
      MICROCHIP_PFSOC_CLINT,
      MICROCHIP_PFSOC_L2CC,
 +    MICROCHIP_PFSOC_DMA,
      MICROCHIP_PFSOC_L2LIM,
      MICROCHIP_PFSOC_PLIC,
      MICROCHIP_PFSOC_MMUART0,
@@ -XXX,XX +XXX,XX @@ enum {
  };
- enum {
+ void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
-+    MICROCHIP_PFSOC_DMA_IRQ0 = 5,
+ bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
-+    MICROCHIP_PFSOC_DMA_IRQ1 = 6,
+ bool riscv_use_emulated_aplic(bool msimode);
-+    MICROCHIP_PFSOC_DMA_IRQ2 = 7,
++void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr);
-+    MICROCHIP_PFSOC_DMA_IRQ3 = 8,
-+    MICROCHIP_PFSOC_DMA_IRQ4 = 9,
+ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
-+    MICROCHIP_PFSOC_DMA_IRQ5 = 10,
+     uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
-+    MICROCHIP_PFSOC_DMA_IRQ6 = 11,
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
 +    MICROCHIP_PFSOC_DMA_IRQ7 = 12,
      MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
      MICROCHIP_PFSOC_MMUART0_IRQ = 90,
      MICROCHIP_PFSOC_MMUART1_IRQ = 91,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
+--- a/hw/intc/riscv_aplic.c
-+++ b/hw/riscv/microchip_pfsoc.c
++++ b/hw/intc/riscv_aplic.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ bool riscv_use_emulated_aplic(bool msimode)
-  * 2) eNVM (Embedded Non-Volatile Memory)
+ #endif
-  * 3) MMUARTs (Multi-Mode UART)
+ }
-  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
-+ * 5) SiFive Platform DMA (Direct Memory Access Controller)
++void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr)
-  *
++{
-  * This board currently generates devicetree dynamically that indicates at least
++#ifdef CONFIG_KVM
-  * two harts and up to five harts.
++    if (riscv_use_emulated_aplic(aplic->msimode)) {
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
++        aplic->kvm_msicfgaddr = extract64(addr, 0, 32);
-     [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
++        aplic->kvm_msicfgaddrH = extract64(addr, 32, 32);
-     [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
++    }
-     [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
++#endif
-+    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,   0x100000 },
++}
      [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
      [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
      [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
                           TYPE_RISCV_CPU_SIFIVE_U54);
      qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
 +    object_initialize_child(obj, "dma-controller", &s->dma,
 +                            TYPE_SIFIVE_PDMA);
 +
-     object_initialize_child(obj, "sd-controller", &s->sdhci,
+ static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic,
-                             TYPE_CADENCE_SDHCI);
+                                           uint32_t irq)
- }
+ {
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
-         memmap[MICROCHIP_PFSOC_PLIC].size);
+     uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH;
-     g_free(plic_hart_config);
+     aplic_m = aplic;
-+    /* DMA */
+-    while (aplic_m && !aplic_m->mmode) {
-+    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+-        aplic_m = aplic_m->parent;
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
+-    }
-+                    memmap[MICROCHIP_PFSOC_DMA].base);
+-    if (!aplic_m) {
-+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+-        qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
-+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+-                      __func__);
-+                           qdev_get_gpio_in(DEVICE(s->plic),
+-        return;
-+                                            MICROCHIP_PFSOC_DMA_IRQ0 + i));
++
 +    if (!aplic->kvm_splitmode) {
 +        while (aplic_m && !aplic_m->mmode) {
 +            aplic_m = aplic_m->parent;
 +        }
 +        if (!aplic_m) {
 +            qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
 +                          __func__);
 +            return;
 +        }
      }
      if (aplic->mmode) {
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
      addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
      addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
 +    if (aplic->kvm_splitmode) {
 +        addr |= aplic->kvm_msicfgaddr;
 +        addr |= ((uint64_t)aplic->kvm_msicfgaddrH << 32);
 +    }
 +
-     /* SYSREG */
+     address_space_stl_le(&address_space_memory, addr,
-     create_unimplemented_device("microchip.pfsoc.sysreg",
+                          eiid, MEMTXATTRS_UNSPECIFIED, &result);
-         memmap[MICROCHIP_PFSOC_SYSREG].base,
+     if (result != MEMTX_OK) {
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
          memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
                                aplic, TYPE_RISCV_APLIC, aplic->aperture_size);
          sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
 +
 +        if (kvm_enabled()) {
 +            aplic->kvm_splitmode = true;
 +        }
      }
      /*
@@ -XXX,XX +XXX,XX @@ static const Property riscv_aplic_properties[] = {
  static const VMStateDescription vmstate_riscv_aplic = {
      .name = "riscv_aplic",
 -    .version_id = 1,
 -    .minimum_version_id = 1,
 +    .version_id = 2,
 +    .minimum_version_id = 2,
      .fields = (const VMStateField[]) {
              VMSTATE_UINT32(domaincfg, RISCVAPLICState),
              VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_riscv_aplic = {
              VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState),
              VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState),
              VMSTATE_UINT32(genmsi, RISCVAPLICState),
 +            VMSTATE_UINT32(kvm_msicfgaddr, RISCVAPLICState),
 +            VMSTATE_UINT32(kvm_msicfgaddrH, RISCVAPLICState),
              VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState,
                                    num_irqs, 0,
                                    vmstate_info_uint32, uint32_t),
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/hw/riscv/virt.c
-+++ b/hw/riscv/Kconfig
++++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
+@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
-     select SIFIVE
+                                     int base_hartid, int hart_count)
-     select UNIMP
+ {
-     select MCHP_PFSOC_MMUART
+     int i;
-+    select SIFIVE_PDMA
+-    hwaddr addr;
-     select CADENCE_SDHCI
++    hwaddr addr = 0;
      uint32_t guest_bits;
      DeviceState *aplic_s = NULL;
      DeviceState *aplic_m = NULL;
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
                                   VIRT_IRQCHIP_NUM_PRIO_BITS,
                                   msimode, false, aplic_m);
 +    if (kvm_enabled() && msimode) {
 +        riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr);
 +    }
 +
      return kvm_enabled() ? aplic_s : aplic_m;
  }
 --
-.28.0
+.47.1

-[PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order
+[PULL 17/39] target/riscv/kvm: remove irqchip_split() restriction
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-At present the Kconfig file is in disorder. Let's sort the options.
+Remove the 'irqchip_split()' restriction in kvm_arch_init() now that
 we have support for "-accel kvm,kernel-irqchip=split".
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241119191706.718860-8-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/Kconfig | 58 ++++++++++++++++++++++++------------------------
+ target/riscv/kvm/kvm-cpu.c | 5 -----
-file changed, 29 insertions(+), 29 deletions(-)
+file changed, 5 deletions(-)
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/hw/riscv/Kconfig
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
- config IBEX
-     bool
+ int kvm_arch_irqchip_create(KVMState *s)
+ {
--config SIFIVE_E
+-    if (kvm_kernel_irqchip_split()) {
--    bool
+-        error_report("-machine kernel_irqchip=split is not supported on RISC-V.");
--    select MSI_NONBROKEN
+-        exit(1);
--    select SIFIVE_CLINT
+-    }
 -    select SIFIVE_GPIO
 -    select SIFIVE_PLIC
 -    select SIFIVE_UART
 -    select SIFIVE_E_PRCI
 -    select UNIMP
 -
--config SIFIVE_U
+     /*
-+config MICROCHIP_PFSOC
+      * We can create the VAIA using the newer device control API.
-     bool
+      */
 -    select CADENCE
 +    select CADENCE_SDHCI
 +    select MCHP_PFSOC_MMUART
      select MSI_NONBROKEN
      select SIFIVE_CLINT
 -    select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_PLIC
 -    select SIFIVE_UART
 -    select SIFIVE_U_OTP
 -    select SIFIVE_U_PRCI
      select UNIMP
 -config SPIKE
 -    bool
 -    select HTIF
 -    select MSI_NONBROKEN
 -    select SIFIVE_CLINT
 -    select SIFIVE_PLIC
 -
  config OPENTITAN
      bool
      select IBEX
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      bool
      imply PCI_DEVICES
      imply TEST_DEVICES
 +    select GOLDFISH_RTC
      select MSI_NONBROKEN
      select PCI
 -    select SERIAL
 -    select GOLDFISH_RTC
 -    select VIRTIO_MMIO
      select PCI_EXPRESS_GENERIC_BRIDGE
      select PFLASH_CFI01
 +    select SERIAL
      select SIFIVE_CLINT
      select SIFIVE_PLIC
      select SIFIVE_TEST
 +    select VIRTIO_MMIO
 -config MICROCHIP_PFSOC
 +config SIFIVE_E
      bool
      select MSI_NONBROKEN
      select SIFIVE_CLINT
 +    select SIFIVE_GPIO
 +    select SIFIVE_PLIC
 +    select SIFIVE_UART
 +    select SIFIVE_E_PRCI
      select UNIMP
 -    select MCHP_PFSOC_MMUART
 +
 +config SIFIVE_U
 +    bool
 +    select CADENCE
 +    select MSI_NONBROKEN
 +    select SIFIVE_CLINT
 +    select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_PLIC
 -    select CADENCE_SDHCI
 +    select SIFIVE_UART
 +    select SIFIVE_U_OTP
 +    select SIFIVE_U_PRCI
 +    select UNIMP
 +
 +config SPIKE
 +    bool
 +    select HTIF
 +    select MSI_NONBROKEN
 +    select SIFIVE_CLINT
 +    select SIFIVE_PLIC
 --
-.28.0
+.47.1

-[PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE
+[PULL 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-The name SIFIVE is too vague to convey the required component of
+Also add a new page, docs/specs/riscv-aia.rst, where we're documenting
-MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
+the state of AIA support in QEMU w.r.t the controllers being emulated or
-each machine instead.
+not depending on the AIA and accelerator settings.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241119191706.718860-9-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/Kconfig | 14 +++++---------
+ docs/specs/index.rst       |  1 +
-file changed, 5 insertions(+), 9 deletions(-)
+ docs/specs/riscv-aia.rst   | 83 ++++++++++++++++++++++++++++++++++++++
  docs/system/riscv/virt.rst |  7 ++++
 files changed, 91 insertions(+)
  create mode 100644 docs/specs/riscv-aia.rst
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+diff --git a/docs/specs/index.rst b/docs/specs/index.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/docs/specs/index.rst
-+++ b/hw/riscv/Kconfig
++++ b/docs/specs/index.rst
@@ -XXX,XX +XXX,XX @@ guest hardware that is specific to QEMU.
     rapl-msr
     rocker
     riscv-iommu
 +   riscv-aia
 diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/specs/riscv-aia.rst
 @@ -XXX,XX +XXX,XX @@
- config IBEX
++.. _riscv-aia:
-     bool
++
++RISC-V AIA support for RISC-V machines
--config SIFIVE
++======================================
--    bool
++
--    select MSI_NONBROKEN
++AIA (Advanced Interrupt Architecture) support is implemented in the ``virt``
--
++RISC-V machine for TCG and KVM accelerators.
- config SIFIVE_E
++
-     bool
++The support consists of two main modes:
--    select SIFIVE
++
-+    select MSI_NONBROKEN
++- "aia=aplic": adds one or more APLIC (Advanced Platform Level Interrupt Controller)
-     select SIFIVE_CLINT
++  devices
-     select SIFIVE_GPIO
++- "aia=aplic-imsic": adds one or more APLIC device and an IMSIC (Incoming MSI
-     select SIFIVE_PLIC
++   Controller) device for each CPU
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
++
- config SIFIVE_U
++From an user standpoint, these modes will behave the same regardless of the accelerator
-     bool
++used.  From a developer standpoint the accelerator settings will change what it being
-     select CADENCE
++emulated in userspace versus what is being emulated by an in-kernel irqchip.
--    select SIFIVE
++
-+    select MSI_NONBROKEN
++When running TCG, all controllers are emulated in userspace, including machine mode
-     select SIFIVE_CLINT
++(m-mode) APLIC and IMSIC (when applicable).
-     select SIFIVE_GPIO
++
-     select SIFIVE_PDMA
++When running KVM:
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
++
- config SPIKE
++- no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation regardless of
-     bool
++  the AIA mode chosen
-     select HTIF
++- with "aia=aplic", s-mode APLIC will be emulated by userspace
--    select SIFIVE
++- with "aia=aplic-imsic" there are two possibilities.  If no additional KVM option
-+    select MSI_NONBROKEN
++  is provided there will be no APLIC or IMSIC emulation in userspace, and the virtual
-     select SIFIVE_CLINT
++  machine will use the provided in-kernel APLIC and IMSIC controllers.  If the user
-     select SIFIVE_PLIC
++  chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split",
++  s-mode APLIC will be emulated while using the s-mode IMSIC from the irqchip
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
++
-     bool
++The following table summarizes how the AIA and accelerator options defines what
-     imply PCI_DEVICES
++we will emulate in userspace:
-     imply TEST_DEVICES
++
-+    select MSI_NONBROKEN
++
-     select PCI
++.. list-table:: How AIA and accel options changes controller emulation
-     select SERIAL
++   :widths: 25 25 25 25 25 25 25
-     select GOLDFISH_RTC
++   :header-rows: 1
-     select VIRTIO_MMIO
++
-     select PCI_EXPRESS_GENERIC_BRIDGE
++   * - Accel
-     select PFLASH_CFI01
++     - Accel props
--    select SIFIVE
++     - AIA type
-     select SIFIVE_CLINT
++     - APLIC m-mode
-     select SIFIVE_PLIC
++     - IMSIC m-mode
-     select SIFIVE_TEST
++     - APLIC s-mode
++     - IMSIC s-mode
- config MICROCHIP_PFSOC
++   * - tcg
-     bool
++     - ---
--    select SIFIVE
++     - aplic
-+    select MSI_NONBROKEN
++     - emul
-     select SIFIVE_CLINT
++     - n/a
-     select UNIMP
++     - emul
-     select MCHP_PFSOC_MMUART
++     - n/a
 +   * - tcg
 +     - ---
 +     - aplic-imsic
 +     - emul
 +     - emul
 +     - emul
 +     - emul
 +   * - kvm
 +     - ---
 +     - aplic
 +     - n/a
 +     - n/a
 +     - emul
 +     - n/a
 +   * - kvm
 +     - none
 +     - aplic-imsic
 +     - n/a
 +     - n/a
 +     - in-kernel
 +     - in-kernel
 +   * - kvm
 +     - irqchip=split
 +     - aplic-imsic
 +     - n/a
 +     - n/a
 +     - emul
 +     - in-kernel
 diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/system/riscv/virt.rst
 +++ b/docs/system/riscv/virt.rst
@@ -XXX,XX +XXX,XX @@ The following machine-specific options are supported:
    MSIs. When not specified, this option is assumed to be "none" which selects
    SiFive PLIC to handle wired interrupts.
 +  This option also interacts with '-accel kvm'.  When using "aia=aplic-imsic"
 +  with KVM, it is possible to set the use of the kernel irqchip in split mode
 +  by using "-accel kvm,kernel-irqchip=split".  In this case the ``virt`` machine
 +  will emulate the APLIC controller instead of using the APLIC controller from
 +  the irqchip.  See :ref:`riscv-aia` for more details on all available AIA
 +  modes.
 +
  - aia-guests=nnn
    The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
 --
-.28.0
+.47.1

-[PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
+[PULL 19/39] hw/riscv: Add Microblaze V generic board
-From: Bin Meng <bin.meng@windriver.com>
+From: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
-This is an initial support for Microchip PolarFire SoC Icicle Kit.
+Add a basic board with interrupt controller (intc), timer, serial
-The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
+(uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000
-E51 plus four U54 cores and many on-chip peripherals and an FPGA.
+(configured via command line eg. -m 2g).
+This is basic configuration which matches HW generated out of AMD Vivado
-For more details about Microchip PolarFire Soc, please see:
+(design tools). But initial configuration is going beyond what it is
-https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
+configured by default because validation should be done on other
+configurations too. That's why wire also additional uart16500, axi
-Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
+ethernet(with axi dma).
-The following perepherals are created as an unimplemented device:
+GPIOs, i2c and qspi is also listed for completeness.
-- Bus Error Uint 0/1/2/3/4
+IRQ map is: (addr)
-- L2 cache controller
+- timer (0x41c00000)
-- SYSREG
+- uartlite (0x40600000)
-- MPUCFG
+- i2c (0x40800000)
-- IOSCBCFG
+- qspi (0x44a00000)
+- uart16550 (0x44a10000)
-More devices will be added later.
+- emaclite (0x40e00000)
+- timer2 (0x41c10000)
-The BIOS image used by this machine is hss.bin, aka Hart Software
+- axi emac (0x40c00000)
-Services, which can be built from:
+- axi dma (0x41e00000)
-https://github.com/polarfire-soc/hart-software-services
+- axi dma
+- gpio (0x40000000)
-To launch this machine:
+- gpio2 (0x40010000)
-$ qemu-system-riscv64 -nographic -M microchip-icicle-kit
+- gpio3 (0x40020000)
-The memory is set to 1 GiB by default to match the hardware.
+Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
-A sanity check on ram size is performed in the machine init routine
+Signed-off-by: Michal Simek <michal.simek@amd.com>
 to prompt user to increase the RAM size to > 1 GiB when less than
 GiB ram is detected.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241125134739.18189-1-sai.pavan.boddu@amd.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- default-configs/riscv64-softmmu.mak |   1 +
+ MAINTAINERS                                |   6 +
- include/hw/riscv/microchip_pfsoc.h  |  88 ++++++++
+ docs/system/riscv/microblaze-v-generic.rst |  42 +++++
- hw/riscv/microchip_pfsoc.c          | 312 ++++++++++++++++++++++++++++
+ docs/system/target-riscv.rst               |   1 +
- MAINTAINERS                         |   7 +
+ hw/riscv/microblaze-v-generic.c            | 184 +++++++++++++++++++++
- hw/riscv/Kconfig                    |   6 +
+ hw/riscv/Kconfig                           |   8 +
- hw/riscv/meson.build                |   1 +
+ hw/riscv/meson.build                       |   1 +
-files changed, 415 insertions(+)
+files changed, 242 insertions(+)
- create mode 100644 include/hw/riscv/microchip_pfsoc.h
+ create mode 100644 docs/system/riscv/microblaze-v-generic.rst
- create mode 100644 hw/riscv/microchip_pfsoc.c
+ create mode 100644 hw/riscv/microblaze-v-generic.c
 diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/default-configs/riscv64-softmmu.mak
 +++ b/default-configs/riscv64-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_SPIKE=y
  CONFIG_SIFIVE_E=y
  CONFIG_SIFIVE_U=y
  CONFIG_RISCV_VIRT=y
 +CONFIG_MICROCHIP_PFSOC=y
 diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Microchip PolarFire SoC machine interface
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef HW_MICROCHIP_PFSOC_H
 +#define HW_MICROCHIP_PFSOC_H
 +
 +typedef struct MicrochipPFSoCState {
 +    /*< private >*/
 +    DeviceState parent_obj;
 +
 +    /*< public >*/
 +    CPUClusterState e_cluster;
 +    CPUClusterState u_cluster;
 +    RISCVHartArrayState e_cpus;
 +    RISCVHartArrayState u_cpus;
 +    DeviceState *plic;
 +} MicrochipPFSoCState;
 +
 +#define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
 +#define MICROCHIP_PFSOC(obj) \
 +    OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
 +
 +typedef struct MicrochipIcicleKitState {
 +    /*< private >*/
 +    MachineState parent_obj;
 +
 +    /*< public >*/
 +    MicrochipPFSoCState soc;
 +} MicrochipIcicleKitState;
 +
 +#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
 +    MACHINE_TYPE_NAME("microchip-icicle-kit")
 +#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
 +    OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
 +                 TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
 +
 +enum {
 +    MICROCHIP_PFSOC_DEBUG,
 +    MICROCHIP_PFSOC_E51_DTIM,
 +    MICROCHIP_PFSOC_BUSERR_UNIT0,
 +    MICROCHIP_PFSOC_BUSERR_UNIT1,
 +    MICROCHIP_PFSOC_BUSERR_UNIT2,
 +    MICROCHIP_PFSOC_BUSERR_UNIT3,
 +    MICROCHIP_PFSOC_BUSERR_UNIT4,
 +    MICROCHIP_PFSOC_CLINT,
 +    MICROCHIP_PFSOC_L2CC,
 +    MICROCHIP_PFSOC_L2LIM,
 +    MICROCHIP_PFSOC_PLIC,
 +    MICROCHIP_PFSOC_SYSREG,
 +    MICROCHIP_PFSOC_MPUCFG,
 +    MICROCHIP_PFSOC_ENVM_CFG,
 +    MICROCHIP_PFSOC_ENVM_DATA,
 +    MICROCHIP_PFSOC_IOSCB_CFG,
 +    MICROCHIP_PFSOC_DRAM,
 +};
 +
 +#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
 +#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
 +
 +#define MICROCHIP_PFSOC_PLIC_HART_CONFIG        "MS"
 +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
 +#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
 +#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
 +#define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
 +#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
 +#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
 +#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE       0x200000
 +#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE     0x1000
 +
 +#endif /* HW_MICROCHIP_PFSOC_H */
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
 + *
 + * 0) CLINT (Core Level Interruptor)
 + * 1) PLIC (Platform Level Interrupt Controller)
 + * 2) eNVM (Embedded Non-Volatile Memory)
 + *
 + * This board currently generates devicetree dynamically that indicates at least
 + * two harts and up to five harts.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qemu/units.h"
 +#include "qemu/cutils.h"
 +#include "qapi/error.h"
 +#include "hw/boards.h"
 +#include "hw/irq.h"
 +#include "hw/loader.h"
 +#include "hw/sysbus.h"
 +#include "hw/cpu/cluster.h"
 +#include "target/riscv/cpu.h"
 +#include "hw/misc/unimp.h"
 +#include "hw/riscv/boot.h"
 +#include "hw/riscv/riscv_hart.h"
 +#include "hw/riscv/sifive_clint.h"
 +#include "hw/riscv/sifive_plic.h"
 +#include "hw/riscv/microchip_pfsoc.h"
 +
 +/*
 + * The BIOS image used by this machine is called Hart Software Services (HSS).
 + * See https://github.com/polarfire-soc/hart-software-services
 + */
 +#define BIOS_FILENAME   "hss.bin"
 +#define RESET_VECTOR    0x20220000
 +
 +static const struct MemmapEntry {
 +    hwaddr base;
 +    hwaddr size;
 +} microchip_pfsoc_memmap[] = {
 +    [MICROCHIP_PFSOC_DEBUG] =           {        0x0,     0x1000 },
 +    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,     0x2000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,     0x1000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,     0x1000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,     0x1000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,     0x1000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
 +    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
 +    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
 +    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
 +    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
 +    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
 +    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
 +    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
 +    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
 +    [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
 +    [MICROCHIP_PFSOC_DRAM] =            { 0x80000000,        0x0 },
 +};
 +
 +static void microchip_pfsoc_soc_instance_init(Object *obj)
 +{
 +    MachineState *ms = MACHINE(qdev_get_machine());
 +    MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
 +
 +    object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
 +    qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
 +
 +    object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
 +                            TYPE_RISCV_HART_ARRAY);
 +    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
 +    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
 +    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
 +                         TYPE_RISCV_CPU_SIFIVE_E51);
 +    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
 +
 +    object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
 +    qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
 +
 +    object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
 +                            TYPE_RISCV_HART_ARRAY);
 +    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
 +    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 +    qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
 +                         TYPE_RISCV_CPU_SIFIVE_U54);
 +    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
 +}
 +
 +static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
 +{
 +    MachineState *ms = MACHINE(qdev_get_machine());
 +    MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
 +    const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
 +    MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
 +    MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
 +    MemoryRegion *envm_data = g_new(MemoryRegion, 1);
 +    char *plic_hart_config;
 +    size_t plic_hart_config_len;
 +    int i;
 +
 +    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
 +    /*
 +     * The cluster must be realized after the RISC-V hart array container,
 +     * as the container's CPU object is only created on realize, and the
 +     * CPU must exist and have been parented into the cluster before the
 +     * cluster is realized.
 +     */
 +    qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
 +    qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
 +
 +    /* E51 DTIM */
 +    memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
 +                           memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_E51_DTIM].base,
 +                                e51_dtim_mem);
 +
 +    /* Bus Error Units */
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
 +
 +    /* CLINT */
 +    sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
 +        memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
 +        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
 +
 +    /* L2 cache controller */
 +    create_unimplemented_device("microchip.pfsoc.l2cc",
 +        memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
 +
 +    /*
 +     * Add L2-LIM at reset size.
 +     * This should be reduced in size as the L2 Cache Controller WayEnable
 +     * register is incremented. Unfortunately I don't see a nice (or any) way
 +     * to handle reducing or blocking out the L2 LIM while still allowing it
 +     * be re returned to all enabled after a reset. For the time being, just
 +     * leave it enabled all the time. This won't break anything, but will be
 +     * too generous to misbehaving guests.
 +     */
 +    memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
 +                           memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_L2LIM].base,
 +                                l2lim_mem);
 +
 +    /* create PLIC hart topology configuration string */
 +    plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
 +                           ms->smp.cpus;
 +    plic_hart_config = g_malloc0(plic_hart_config_len);
 +    for (i = 0; i < ms->smp.cpus; i++) {
 +        if (i != 0) {
 +            strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
 +                    plic_hart_config_len);
 +        } else {
 +            strncat(plic_hart_config, "M", plic_hart_config_len);
 +        }
 +        plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
 +    }
 +
 +    /* PLIC */
 +    s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
 +        plic_hart_config, 0,
 +        MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
 +        MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
 +        MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
 +        MICROCHIP_PFSOC_PLIC_PENDING_BASE,
 +        MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
 +        MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
 +        MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
 +        MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
 +        memmap[MICROCHIP_PFSOC_PLIC].size);
 +    g_free(plic_hart_config);
 +
 +    /* SYSREG */
 +    create_unimplemented_device("microchip.pfsoc.sysreg",
 +        memmap[MICROCHIP_PFSOC_SYSREG].base,
 +        memmap[MICROCHIP_PFSOC_SYSREG].size);
 +
 +    /* MPUCFG */
 +    create_unimplemented_device("microchip.pfsoc.mpucfg",
 +        memmap[MICROCHIP_PFSOC_MPUCFG].base,
 +        memmap[MICROCHIP_PFSOC_MPUCFG].size);
 +
 +    /* eNVM */
 +    memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
 +                           memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
 +                           &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
 +                                envm_data);
 +
 +    /* IOSCBCFG */
 +    create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
 +        memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
 +        memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
 +}
 +
 +static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(oc);
 +
 +    dc->realize = microchip_pfsoc_soc_realize;
 +    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 +    dc->user_creatable = false;
 +}
 +
 +static const TypeInfo microchip_pfsoc_soc_type_info = {
 +    .name = TYPE_MICROCHIP_PFSOC,
 +    .parent = TYPE_DEVICE,
 +    .instance_size = sizeof(MicrochipPFSoCState),
 +    .instance_init = microchip_pfsoc_soc_instance_init,
 +    .class_init = microchip_pfsoc_soc_class_init,
 +};
 +
 +static void microchip_pfsoc_soc_register_types(void)
 +{
 +    type_register_static(&microchip_pfsoc_soc_type_info);
 +}
 +
 +type_init(microchip_pfsoc_soc_register_types)
 +
 +static void microchip_icicle_kit_machine_init(MachineState *machine)
 +{
 +    MachineClass *mc = MACHINE_GET_CLASS(machine);
 +    const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
 +    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
 +    MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 +
 +    /* Sanity check on RAM size */
 +    if (machine->ram_size < mc->default_ram_size) {
 +        char *sz = size_to_str(mc->default_ram_size);
 +        error_report("Invalid RAM size, should be bigger than %s", sz);
 +        g_free(sz);
 +        exit(EXIT_FAILURE);
 +    }
 +
 +    /* Initialize SoC */
 +    object_initialize_child(OBJECT(machine), "soc", &s->soc,
 +                            TYPE_MICROCHIP_PFSOC);
 +    qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 +
 +    /* Register RAM */
 +    memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
 +                           machine->ram_size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
 +
 +    /* Load the firmware */
 +    riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
 +}
 +
 +static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
 +{
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +
 +    mc->desc = "Microchip PolarFire SoC Icicle Kit";
 +    mc->init = microchip_icicle_kit_machine_init;
 +    mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
 +                   MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
 +    mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
 +    mc->default_cpus = mc->min_cpus;
 +    mc->default_ram_size = 1 * GiB;
 +}
 +
 +static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
 +    .name       = MACHINE_TYPE_NAME("microchip-icicle-kit"),
 +    .parent     = TYPE_MACHINE,
 +    .class_init = microchip_icicle_kit_machine_class_init,
 +    .instance_size = sizeof(MicrochipIcicleKitState),
 +};
 +
 +static void microchip_icicle_kit_machine_init_register_types(void)
 +{
 +    type_register_static(&microchip_icicle_kit_machine_typeinfo);
 +}
 +
 +type_init(microchip_icicle_kit_machine_init_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/opentitan.h
+@@ -XXX,XX +XXX,XX @@ F: docs/system/riscv/sifive_u.rst
- F: include/hw/char/ibex_uart.h
+ F: hw/*/*sifive*.c
- F: include/hw/intc/ibex_plic.h
+ F: include/hw/*/*sifive*.h
-+Microchip PolarFire SoC Icicle Kit
++AMD Microblaze-V Generic Board
-+M: Bin Meng <bin.meng@windriver.com>
++M: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
-+L: qemu-riscv@nongnu.org
++S: Maintained
-+S: Supported
++F: hw/riscv/microblaze-v-generic.c
-+F: hw/riscv/microchip_pfsoc.c
++F: docs/system/riscv/microblaze-v-generic.rst
 +F: include/hw/riscv/microchip_pfsoc.h
 +
  RX Machines
  -----------
  rx-gdbsim
+diff --git a/docs/system/riscv/microblaze-v-generic.rst b/docs/system/riscv/microblaze-v-generic.rst
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/docs/system/riscv/microblaze-v-generic.rst
+@@ -XXX,XX +XXX,XX @@
++Microblaze-V generic board (``amd-microblaze-v-generic``)
++=========================================================
++The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
++adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
++64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
++compatible with the classic MicroBlaze™ V processor (i.e it is a drop in
++replacement for the classic MicroBlaze™ processor in existing RTL designs).
++More information can be found in below document.
++
++https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture
++
++The MicroBlaze™ V generic board in QEMU has following supported devices:
++
++    - timer
++    - uartlite
++    - uart16550
++    - emaclite
++    - timer2
++    - axi emac
++    - axi dma
++
++The MicroBlaze™ V core in QEMU has the following configuration:
++
++    - RV32I base integer instruction set
++    - "Zicsr" Control and Status register instructions
++    - "Zifencei" instruction-fetch
++    - Extensions: m, a, f, c
++
++Running
++"""""""
++Below is an example command line for launching mainline U-boot
++(xilinx_mbv32_defconfig) on the Microblaze-V generic board.
++
++.. code-block:: bash
++
++   $ qemu-system-riscv32 -M amd-microblaze-v-generic \
++     -display none \
++     -device loader,addr=0x80000000,file=u-boot-spl.bin,cpu-num=0 \
++     -device loader,addr=0x80200000,file=u-boot.img \
++     -serial mon:stdio \
++     -device loader,addr=0x83000000,file=system.dtb \
++     -m 2g
+diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/target-riscv.rst
++++ b/docs/system/target-riscv.rst
+@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+ .. toctree::
+    :maxdepth: 1
++   riscv/microblaze-v-generic
+    riscv/microchip-icicle-kit
+    riscv/shakti-c
+    riscv/sifive_u
+diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/riscv/microblaze-v-generic.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * QEMU model of Microblaze V generic board.
++ *
++ * based on hw/microblaze/petalogix_ml605_mmu.c
++ *
++ * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
++ * Copyright (c) 2011 PetaLogix
++ * Copyright (c) 2009 Edgar E. Iglesias.
++ * Copyright (C) 2024, Advanced Micro Devices, Inc.
++ * SPDX-License-Identifier: GPL-2.0-or-later
++ *
++ * Written by Sai Pavan Boddu <sai.pavan.boddu@amd.com
++ *     and by Michal Simek <michal.simek@amd.com>.
++ */
++
++#include "qemu/osdep.h"
++#include "qemu/units.h"
++#include "qapi/error.h"
++#include "cpu.h"
++#include "hw/sysbus.h"
++#include "sysemu/sysemu.h"
++#include "net/net.h"
++#include "hw/boards.h"
++#include "hw/char/serial-mm.h"
++#include "exec/address-spaces.h"
++#include "hw/char/xilinx_uartlite.h"
++#include "hw/misc/unimp.h"
++
++#define LMB_BRAM_SIZE (128 * KiB)
++#define MEMORY_BASEADDR 0x80000000
++#define INTC_BASEADDR 0x41200000
++#define TIMER_BASEADDR 0x41c00000
++#define TIMER_BASEADDR2 0x41c10000
++#define UARTLITE_BASEADDR 0x40600000
++#define ETHLITE_BASEADDR 0x40e00000
++#define UART16550_BASEADDR 0x44a10000
++#define AXIENET_BASEADDR 0x40c00000
++#define AXIDMA_BASEADDR 0x41e00000
++#define GPIO_BASEADDR 0x40000000
++#define GPIO_BASEADDR2 0x40010000
++#define GPIO_BASEADDR3 0x40020000
++#define I2C_BASEADDR 0x40800000
++#define QSPI_BASEADDR 0x44a00000
++
++#define TIMER_IRQ           0
++#define UARTLITE_IRQ        1
++#define UART16550_IRQ       4
++#define ETHLITE_IRQ         5
++#define TIMER_IRQ2          6
++#define AXIENET_IRQ         7
++#define AXIDMA_IRQ1         8
++#define AXIDMA_IRQ0         9
++
++static void mb_v_generic_init(MachineState *machine)
++{
++    ram_addr_t ram_size = machine->ram_size;
++    DeviceState *dev, *dma, *eth0;
++    Object *ds, *cs;
++    int i;
++    RISCVCPU *cpu;
++    hwaddr ddr_base = MEMORY_BASEADDR;
++    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
++    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
++    qemu_irq irq[32];
++    MemoryRegion *sysmem = get_system_memory();
++
++    cpu = RISCV_CPU(object_new(machine->cpu_type));
++    object_property_set_bool(OBJECT(cpu), "h", false, NULL);
++    object_property_set_bool(OBJECT(cpu), "d", false, NULL);
++    qdev_realize(DEVICE(cpu), NULL, &error_abort);
++    /* Attach emulated BRAM through the LMB.  */
++    memory_region_init_ram(phys_lmb_bram, NULL,
++                           "mb_v.lmb_bram", LMB_BRAM_SIZE,
++                           &error_fatal);
++    memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
++
++    memory_region_init_ram(phys_ram, NULL, "mb_v.ram",
++                           ram_size, &error_fatal);
++    memory_region_add_subregion(sysmem, ddr_base, phys_ram);
++
++    dev = qdev_new("xlnx.xps-intc");
++    qdev_prop_set_uint32(dev, "kind-of-intr",
++                         1 << UARTLITE_IRQ);
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
++    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
++                       qdev_get_gpio_in(DEVICE(cpu), 11));
++    for (i = 0; i < 32; i++) {
++        irq[i] = qdev_get_gpio_in(dev, i);
++    }
++
++    /* Uartlite */
++    dev = qdev_new(TYPE_XILINX_UARTLITE);
++    qdev_prop_set_chr(dev, "chardev", serial_hd(0));
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
++    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);
++
++    /* Full uart */
++    serial_mm_init(sysmem, UART16550_BASEADDR + 0x1000, 2,
++                   irq[UART16550_IRQ], 115200, serial_hd(1),
++                   DEVICE_LITTLE_ENDIAN);
++
++    /* 2 timers at irq 0 @ 100 Mhz.  */
++    dev = qdev_new("xlnx.xps-timer");
++    qdev_prop_set_uint32(dev, "one-timer-only", 0);
++    qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
++    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
++
++    /* 2 timers at irq 3 @ 100 Mhz.  */
++    dev = qdev_new("xlnx.xps-timer");
++    qdev_prop_set_uint32(dev, "one-timer-only", 0);
++    qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR2);
++    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ2]);
++
++    /* Emaclite */
++    dev = qdev_new("xlnx.xps-ethernetlite");
++    qemu_configure_nic_device(dev, true, NULL);
++    qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
++    qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
++    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
++
++    /* axi ethernet and dma initialization. */
++    eth0 = qdev_new("xlnx.axi-ethernet");
++    dma = qdev_new("xlnx.axi-dma");
++
++    /* FIXME: attach to the sysbus instead */
++    object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0));
++    object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma));
++
++    ds = object_property_get_link(OBJECT(dma),
++                                  "axistream-connected-target", NULL);
++    cs = object_property_get_link(OBJECT(dma),
++                                  "axistream-control-connected-target", NULL);
++    qemu_configure_nic_device(eth0, true, NULL);
++    qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
++    qdev_prop_set_uint32(eth0, "txmem", 0x1000);
++    object_property_set_link(OBJECT(eth0), "axistream-connected", ds,
++                             &error_abort);
++    object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs,
++                             &error_abort);
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
++    sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
++
++    ds = object_property_get_link(OBJECT(eth0),
++                                  "axistream-connected-target", NULL);
++    cs = object_property_get_link(OBJECT(eth0),
++                                  "axistream-control-connected-target", NULL);
++    qdev_prop_set_uint32(dma, "freqhz", 100000000);
++    object_property_set_link(OBJECT(dma), "axistream-connected", ds,
++                             &error_abort);
++    object_property_set_link(OBJECT(dma), "axistream-control-connected", cs,
++                             &error_abort);
++    sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
++    sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
++    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
++    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
++
++    /* unimplemented devices */
++    create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
++    create_unimplemented_device("gpio2", GPIO_BASEADDR2, 0x10000);
++    create_unimplemented_device("gpio3", GPIO_BASEADDR3, 0x10000);
++    create_unimplemented_device("i2c", I2C_BASEADDR, 0x10000);
++    create_unimplemented_device("qspi", QSPI_BASEADDR, 0x10000);
++}
++
++static void mb_v_generic_machine_init(MachineClass *mc)
++{
++    mc->desc = "AMD Microblaze-V generic platform";
++    mc->init = mb_v_generic_init;
++    mc->min_cpus = 1;
++    mc->max_cpus = 1;
++    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
++    mc->default_cpus = 1;
++}
++
++DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init)
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
+@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
-     select PCI_EXPRESS_GENERIC_BRIDGE
+     select SIFIVE_PLIC
-     select PFLASH_CFI01
+     select UNIMP
-     select SIFIVE
-+
++config MICROBLAZE_V
 +config MICROCHIP_PFSOC
 +    bool
-+    select HART
++    default y
-+    select SIFIVE
++    depends on RISCV32 || RISCV64
-+    select UNIMP
++    select XILINX
 +    select XILINX_AXI
 +    select XILINX_ETHLITE
 +
  config OPENTITAN
      bool
      default y
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
+@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
- riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
+ riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
- riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
+ riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
- riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
+ riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
-+riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
++riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
  hw_arch += {'riscv': riscv_ss}
 --
-.28.0
+.47.1

-[PULL 28/30] hw/riscv: Always build riscv_hart.c
+[PULL 20/39] qtest: allow SPCR acpi table changes
-From: Bin Meng <bin.meng@windriver.com>
+From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
-Every RISC-V machine needs riscv_hart hence there is no need to
+Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
-have a dedicated Kconfig option for it. Drop the Kconfig option
+Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
-and always build riscv_hart.c.
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20241028015744.624943-2-jeeheng.sia@starfivetech.com>
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/Kconfig     | 9 ---------
+ tests/qtest/bios-tables-test-allowed-diff.h | 1 +
- hw/riscv/meson.build | 2 +-
+file changed, 1 insertion(+)
 files changed, 1 insertion(+), 10 deletions(-)
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
-+++ b/hw/riscv/Kconfig
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
-@@ -XXX,XX +XXX,XX @@
+@@ -1 +1,2 @@
--config HART
+ /* List of comma-separated changed AML files to ignore */
--    bool
++"tests/data/acpi/riscv64/virt/SPCR",
 -
  config IBEX
      bool
@@ -XXX,XX +XXX,XX @@ config SIFIVE
  config SIFIVE_E
      bool
 -    select HART
      select SIFIVE
      select SIFIVE_CLINT
      select SIFIVE_GPIO
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
  config SIFIVE_U
      bool
      select CADENCE
 -    select HART
      select SIFIVE
      select SIFIVE_CLINT
      select SIFIVE_GPIO
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
  config SPIKE
      bool
 -    select HART
      select HTIF
      select SIFIVE
      select SIFIVE_CLINT
@@ -XXX,XX +XXX,XX @@ config SPIKE
  config OPENTITAN
      bool
      select IBEX
 -    select HART
      select UNIMP
  config RISCV_VIRT
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      imply PCI_DEVICES
      imply TEST_DEVICES
      select PCI
 -    select HART
      select SERIAL
      select GOLDFISH_RTC
      select VIRTIO_MMIO
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
  config MICROCHIP_PFSOC
      bool
 -    select HART
      select SIFIVE
      select SIFIVE_CLINT
      select UNIMP
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
  riscv_ss = ss.source_set()
  riscv_ss.add(files('boot.c'), fdt)
  riscv_ss.add(files('numa.c'))
 -riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 +riscv_ss.add(files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 --
-.28.0
+.47.1

-[PULL 21/30] hw/riscv: Move sifive_u_otp model to hw/misc
+[PULL 21/39] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
-From: Bin Meng <bin.meng@windriver.com>
+From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Update the SPCR table to accommodate the SPCR Table revision 4 [1].
-should only contain the RISC-V SoC / machine codes plus generic
+The SPCR table has been modified to adhere to the revision 4 format [2].
 codes. Let's move sifive_u_otp model to hw/misc directory.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+[2]: https://github.com/acpica/acpica/pull/931
-Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
 Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
 Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Bibo Mao <maobibo@loongson.cn>
 Message-ID: <20241028015744.624943-3-jeeheng.sia@starfivetech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => misc}/sifive_u_otp.h | 0
+ include/hw/acpi/acpi-defs.h |  7 +++++--
- include/hw/riscv/sifive_u.h               | 2 +-
+ include/hw/acpi/aml-build.h |  2 +-
- hw/{riscv => misc}/sifive_u_otp.c         | 2 +-
+ hw/acpi/aml-build.c         | 20 ++++++++++++++++----
- hw/misc/Kconfig                           | 3 +++
+ hw/arm/virt-acpi-build.c    |  8 ++++++--
- hw/misc/meson.build                       | 1 +
+ hw/loongarch/acpi-build.c   |  6 +++++-
- hw/riscv/Kconfig                          | 1 +
+ hw/riscv/virt-acpi-build.c  | 12 +++++++++---
- hw/riscv/meson.build                      | 1 -
+files changed, 42 insertions(+), 13 deletions(-)
 files changed, 7 insertions(+), 3 deletions(-)
  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
-diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
+diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
 similarity index 100%
 rename from include/hw/riscv/sifive_u_otp.h
 rename to include/hw/misc/sifive_u_otp.h
 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/include/hw/acpi/acpi-defs.h
-+++ b/include/hw/riscv/sifive_u.h
++++ b/include/hw/acpi/acpi-defs.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct AcpiSpcrData {
- #include "hw/riscv/riscv_hart.h"
+     uint8_t flow_control;
- #include "hw/riscv/sifive_cpu.h"
+     uint8_t terminal_type;
- #include "hw/riscv/sifive_gpio.h"
+     uint8_t language;
--#include "hw/riscv/sifive_u_otp.h"
+-    uint8_t reserved1;
-+#include "hw/misc/sifive_u_otp.h"
+     uint16_t pci_device_id;    /* Must be 0xffff if not PCI device */
- #include "hw/misc/sifive_u_prci.h"
+     uint16_t pci_vendor_id;    /* Must be 0xffff if not PCI device */
+     uint8_t pci_bus;
- #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
+@@ -XXX,XX +XXX,XX @@ typedef struct AcpiSpcrData {
-diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
+     uint8_t pci_function;
-similarity index 99%
+     uint32_t pci_flags;
-rename from hw/riscv/sifive_u_otp.c
+     uint8_t pci_segment;
-rename to hw/misc/sifive_u_otp.c
+-    uint32_t reserved2;
 +    uint32_t uart_clk_freq;
 +    uint32_t precise_baudrate;
 +    uint32_t namespace_string_length;
 +    uint32_t namespace_string_offset;
 +    char namespace_string[];
  } AcpiSpcrData;
  #define ACPI_FADT_ARM_PSCI_COMPLIANT  (1 << 0)
 diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u_otp.c
+--- a/include/hw/acpi/aml-build.h
-+++ b/hw/misc/sifive_u_otp.c
++++ b/include/hw/acpi/aml-build.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
- #include "hw/sysbus.h"
- #include "qemu/log.h"
+ void build_spcr(GArray *table_data, BIOSLinker *linker,
- #include "qemu/module.h"
+                 const AcpiSpcrData *f, const uint8_t rev,
--#include "hw/riscv/sifive_u_otp.h"
+-                const char *oem_id, const char *oem_table_id);
-+#include "hw/misc/sifive_u_otp.h"
++                const char *oem_id, const char *oem_table_id, const char *name);
+ #endif
- static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
+diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/acpi/aml-build.c
 +++ b/hw/acpi/aml-build.c
@@ -XXX,XX +XXX,XX @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags,
  void build_spcr(GArray *table_data, BIOSLinker *linker,
                  const AcpiSpcrData *f, const uint8_t rev,
 -                const char *oem_id, const char *oem_table_id)
 +                const char *oem_id, const char *oem_table_id, const char *name)
  {
-diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
+     AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
                          .oem_table_id = oem_table_id };
@@ -XXX,XX +XXX,XX @@ void build_spcr(GArray *table_data, BIOSLinker *linker,
      build_append_int_noprefix(table_data, f->pci_flags, 4);
      /* PCI Segment */
      build_append_int_noprefix(table_data, f->pci_segment, 1);
 -    /* Reserved */
 -    build_append_int_noprefix(table_data, 0, 4);
 -
 +    if (rev < 4) {
 +        /* Reserved */
 +        build_append_int_noprefix(table_data, 0, 4);
 +    } else {
 +        /* UartClkFreq */
 +        build_append_int_noprefix(table_data, f->uart_clk_freq, 4);
 +        /* PreciseBaudrate */
 +        build_append_int_noprefix(table_data, f->precise_baudrate, 4);
 +        /* NameSpaceStringLength */
 +        build_append_int_noprefix(table_data, f->namespace_string_length, 2);
 +        /* NameSpaceStringOffset */
 +        build_append_int_noprefix(table_data, f->namespace_string_offset, 2);
 +        /* NamespaceString[] */
 +        g_array_append_vals(table_data, name, f->namespace_string_length);
 +    }
      acpi_table_end(linker, &table);
  }
  /*
 diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Kconfig
+--- a/hw/arm/virt-acpi-build.c
-+++ b/hw/misc/Kconfig
++++ b/hw/arm/virt-acpi-build.c
-@@ -XXX,XX +XXX,XX @@ config AVR_POWER
+@@ -XXX,XX +XXX,XX @@ spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
- config SIFIVE_E_PRCI
+         .pci_flags = 0,
-     bool
+         .pci_segment = 0,
+     };
-+config SIFIVE_U_OTP
+-
-+    bool
+-    build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
-+
++    /*
- config SIFIVE_U_PRCI
++     * Passing NULL as the SPCR Table for Revision 2 doesn't support
-     bool
++     * NameSpaceString.
++     */
-diff --git a/hw/misc/meson.build b/hw/misc/meson.build
++    build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id,
 +               NULL);
  }
  /*
 diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/meson.build
+--- a/hw/loongarch/acpi-build.c
-+++ b/hw/misc/meson.build
++++ b/hw/loongarch/acpi-build.c
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
+@@ -XXX,XX +XXX,XX @@ spcr_setup(GArray *table_data, BIOSLinker *linker, MachineState *machine)
+     };
- # RISC-V devices
- softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+     lvms = LOONGARCH_VIRT_MACHINE(machine);
-+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
++    /*
- softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
++     * Passing NULL as the SPCR Table for Revision 2 doesn't support
++     * NameSpaceString.
- # PKUnity SoC devices
++     */
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+     build_spcr(table_data, linker, &serial, 2, lvms->oem_id,
 -               lvms->oem_table_id);
 +               lvms->oem_table_id, NULL);
  }
  typedef
 diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/hw/riscv/virt-acpi-build.c
-+++ b/hw/riscv/Kconfig
++++ b/hw/riscv/virt-acpi-build.c
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
+@@ -XXX,XX +XXX,XX @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
-     select HART
-     select SIFIVE
+ /*
-     select SIFIVE_PDMA
+  * Serial Port Console Redirection Table (SPCR)
-+    select SIFIVE_U_OTP
+- * Rev: 1.07
-     select SIFIVE_U_PRCI
++ * Rev: 1.10
-     select UNIMP
+  */
-diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
+ static void
-index XXXXXXX..XXXXXXX 100644
+ spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
---- a/hw/riscv/meson.build
+ {
-+++ b/hw/riscv/meson.build
++    const char name[] = ".";
-@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
+     AcpiSpcrData serial = {
- riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
+-        .interface_type = 0,       /* 16550 compatible */
- riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
++        .interface_type = 0x12,       /* 16550 compatible */
- riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
+         .base_addr.id = AML_AS_SYSTEM_MEMORY,
--riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
+         .base_addr.width = 32,
- riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
+         .base_addr.offset = 0,
- riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
+@@ -XXX,XX +XXX,XX @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
- riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
+         .pci_function = 0,
          .pci_flags = 0,
          .pci_segment = 0,
 +        .uart_clk_freq = 0,
 +        .precise_baudrate = 0,
 +        .namespace_string_length = sizeof(name),
 +        .namespace_string_offset = 88,
      };
 -    build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
 +    build_spcr(table_data, linker, &serial, 4, s->oem_id, s->oem_table_id,
 +               name);
  }
  /* RHCT Node[N] starts at offset 56 */
 --
-.28.0
+.47.1

-[PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc
+[PULL 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V
-From: Bin Meng <bin.meng@windriver.com>
+From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Update the virt SPCR golden reference file for RISC-V to accommodate the
-should only contain the RISC-V SoC / machine codes plus generic
+SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
-codes. Let's move sifive_u_prci model to hw/misc directory.
+latest ACPICA repository. The SPCR table has been modified to
 adhere to the revision 4 format [2].
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+[2]: https://github.com/acpica/acpica/pull/931
-Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
 Diffs from iasl:
 /*
   * Intel ACPI Component Architecture
   * AML/ASL+ Disassembler version 20200925 (64-bit version)
   * Copyright (c) 2000 - 2020 Intel Corporation
   *
 - * Disassembly of tests/data/acpi/riscv64/virt/SPCR, Wed Aug 28 18:28:19 2024
 + * Disassembly of /tmp/aml-MN0NS2, Wed Aug 28 18:28:19 2024
   *
   * ACPI Data Table [SPCR]
   *
   * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
   */
  [000h 0000   4]                    Signature : "SPCR"    [Serial Port Console Redirection table]
 -[004h 0004   4]                 Table Length : 00000050
 -[008h 0008   1]                     Revision : 02
 -[009h 0009   1]                     Checksum : B9
 +[004h 0004   4]                 Table Length : 0000005A
 +[008h 0008   1]                     Revision : 04
 +[009h 0009   1]                     Checksum : 13
  [00Ah 0010   6]                       Oem ID : "BOCHS "
  [010h 0016   8]                 Oem Table ID : "BXPC    "
  [018h 0024   4]                 Oem Revision : 00000001
  [01Ch 0028   4]              Asl Compiler ID : "BXPC"
  [020h 0032   4]        Asl Compiler Revision : 00000001
 -[024h 0036   1]               Interface Type : 00
 +[024h 0036   1]               Interface Type : 12
  [025h 0037   3]                     Reserved : 000000
  [028h 0040  12]         Serial Port Register : [Generic Address Structure]
  [028h 0040   1]                     Space ID : 00 [SystemMemory]
  [029h 0041   1]                    Bit Width : 20
  [02Ah 0042   1]                   Bit Offset : 00
  [02Bh 0043   1]         Encoded Access Width : 01 [Byte Access:8]
  [02Ch 0044   8]                      Address : 0000000010000000
  [034h 0052   1]               Interrupt Type : 10
  [035h 0053   1]          PCAT-compatible IRQ : 00
  [036h 0054   4]                    Interrupt : 0000000A
  [03Ah 0058   1]                    Baud Rate : 07
  [03Bh 0059   1]                       Parity : 00
  [03Ch 0060   1]                    Stop Bits : 01
  [03Dh 0061   1]                 Flow Control : 00
  [03Eh 0062   1]                Terminal Type : 00
  [04Ch 0076   1]                     Reserved : 00
  [040h 0064   2]                PCI Device ID : FFFF
  [042h 0066   2]                PCI Vendor ID : FFFF
  [044h 0068   1]                      PCI Bus : 00
  [045h 0069   1]                   PCI Device : 00
  [046h 0070   1]                 PCI Function : 00
  [047h 0071   4]                    PCI Flags : 00000000
  [04Bh 0075   1]                  PCI Segment : 00
 -[04Ch 0076   4]                     Reserved : 00000000
 +[04Ch 0076 004h]             Uart Clock Freq : 00000000
 +[050h 0080 004h]           Precise Baud rate : 00000000
 +[054h 0084 002h]       NameSpaceStringLength : 0002
 +[056h 0086 002h]       NameSpaceStringOffset : 0058
 +[058h 0088 002h]             NamespaceString : "."
 -Raw Table Data: Length 80 (0x50)
 +Raw Table Data: Length 90 (0x5A)
 -    0000: 53 50 43 52 50 00 00 00 02 B9 42 4F 43 48 53 20  // SPCRP.....BOCHS
 +    0000: 53 50 43 52 5A 00 00 00 04 13 42 4F 43 48 53 20  // SPCRZ.....BOCHS
 : 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC    ....BXPC
 -    0020: 01 00 00 00 00 00 00 00 00 20 00 01 00 00 00 10  // ......... ......
 +    0020: 01 00 00 00 12 00 00 00 00 20 00 01 00 00 00 10  // ......... ......
 : 00 00 00 00 10 00 0A 00 00 00 07 00 01 00 00 03  // ................
 : FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00  // ................
 +    0050: 00 00 00 00 02 00 58 00 2E 00                    // ......X...
 Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
 Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
 Message-ID: <20241028015744.624943-4-jeeheng.sia@starfivetech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => misc}/sifive_u_prci.h | 0
+ tests/qtest/bios-tables-test-allowed-diff.h |   1 -
- include/hw/riscv/sifive_u.h                | 2 +-
+ tests/data/acpi/riscv64/virt/SPCR           | Bin 80 -> 90 bytes
- hw/{riscv => misc}/sifive_u_prci.c         | 2 +-
+files changed, 1 deletion(-)
  hw/misc/Kconfig                            | 3 +++
  hw/misc/meson.build                        | 1 +
  hw/riscv/Kconfig                           | 1 +
  hw/riscv/meson.build                       | 1 -
 files changed, 7 insertions(+), 3 deletions(-)
  rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
  rename hw/{riscv => misc}/sifive_u_prci.c (99%)
-diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
+diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
 similarity index 100%
 rename from include/hw/riscv/sifive_u_prci.h
 rename to include/hw/misc/sifive_u_prci.h
 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/tests/qtest/bios-tables-test-allowed-diff.h
-+++ b/include/hw/riscv/sifive_u.h
++++ b/tests/qtest/bios-tables-test-allowed-diff.h
-@@ -XXX,XX +XXX,XX @@
+@@ -1,2 +1 @@
- #include "hw/riscv/riscv_hart.h"
+ /* List of comma-separated changed AML files to ignore */
- #include "hw/riscv/sifive_cpu.h"
+-"tests/data/acpi/riscv64/virt/SPCR",
- #include "hw/riscv/sifive_gpio.h"
+diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/virt/SPCR
 -#include "hw/riscv/sifive_u_prci.h"
  #include "hw/riscv/sifive_u_otp.h"
 +#include "hw/misc/sifive_u_prci.h"
  #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
  #define RISCV_U_SOC(obj) \
 diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
 similarity index 99%
 rename from hw/riscv/sifive_u_prci.c
 rename to hw/misc/sifive_u_prci.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u_prci.c
+Binary files a/tests/data/acpi/riscv64/virt/SPCR and b/tests/data/acpi/riscv64/virt/SPCR differ
 +++ b/hw/misc/sifive_u_prci.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/sysbus.h"
  #include "qemu/log.h"
  #include "qemu/module.h"
 -#include "hw/riscv/sifive_u_prci.h"
 +#include "hw/misc/sifive_u_prci.h"
  static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
  {
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
  config SIFIVE_E_PRCI
      bool
 +config SIFIVE_U_PRCI
 +    bool
 +
  source macio/Kconfig
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
  # RISC-V devices
  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
  # PKUnity SoC devices
  softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select HART
      select SIFIVE
      select SIFIVE_PDMA
 +    select SIFIVE_U_PRCI
      select UNIMP
  config SPIKE
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 --
-.28.0
+.47.1

-[PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc
+[PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface
-From: Bin Meng <bin.meng@windriver.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-This is an effort to clean up the hw/riscv directory. Ideally it
+The HTIF interface is RISC-V specific, add
-should only contain the RISC-V SoC / machine codes plus generic
+it within the MAINTAINERS section covering
-codes. Let's move sifive_e_prci model to hw/misc directory.
+hw/riscv/.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20241129154304.34946-2-philmd@linaro.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => misc}/sifive_e_prci.h | 0
+ MAINTAINERS | 2 ++
- hw/{riscv => misc}/sifive_e_prci.c         | 2 +-
+file changed, 2 insertions(+)
  hw/riscv/sifive_e.c                        | 2 +-
  hw/misc/Kconfig                            | 3 +++
  hw/misc/meson.build                        | 3 +++
  hw/riscv/Kconfig                           | 1 +
  hw/riscv/meson.build                       | 1 -
 files changed, 9 insertions(+), 3 deletions(-)
  rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
  rename hw/{riscv => misc}/sifive_e_prci.c (99%)
-diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
+diff --git a/MAINTAINERS b/MAINTAINERS
 similarity index 100%
 rename from include/hw/riscv/sifive_e_prci.h
 rename to include/hw/misc/sifive_e_prci.h
 diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
 similarity index 99%
 rename from hw/riscv/sifive_e_prci.c
 rename to hw/misc/sifive_e_prci.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_e_prci.c
+--- a/MAINTAINERS
-+++ b/hw/misc/sifive_e_prci.c
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ S: Supported
- #include "qemu/log.h"
+ F: configs/targets/riscv*
- #include "qemu/module.h"
+ F: docs/system/target-riscv.rst
- #include "hw/hw.h"
+ F: target/riscv/
--#include "hw/riscv/sifive_e_prci.h"
++F: hw/char/riscv_htif.c
-+#include "hw/misc/sifive_e_prci.h"
+ F: hw/riscv/
+ F: hw/intc/riscv*
- static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
++F: include/hw/char/riscv_htif.h
- {
+ F: include/hw/riscv/
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
+ F: linux-user/host/riscv32/
-index XXXXXXX..XXXXXXX 100644
+ F: linux-user/host/riscv64/
 --- a/hw/riscv/sifive_e.c
 +++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/riscv/sifive_clint.h"
  #include "hw/riscv/sifive_uart.h"
  #include "hw/riscv/sifive_e.h"
 -#include "hw/riscv/sifive_e_prci.h"
  #include "hw/riscv/boot.h"
 +#include "hw/misc/sifive_e_prci.h"
  #include "chardev/char.h"
  #include "sysemu/arch_init.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
  config AVR_POWER
      bool
 +config SIFIVE_E_PRCI
 +    bool
 +
  source macio/Kconfig
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
  # Mac devices
  softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 +# RISC-V devices
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 +
  # PKUnity SoC devices
  softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
      bool
      select HART
      select SIFIVE
 +    select SIFIVE_E_PRCI
      select UNIMP
  config SIFIVE_U
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
 --
-.28.0
+.47.1

-[PULL 25/30] hw/riscv: Move riscv_htif model to hw/char
+[PULL 24/39] hw/char/riscv_htif: Explicit little-endian implementation
-From: Bin Meng <bin.meng@windriver.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Since our RISC-V system emulation is only built for little
-should only contain the RISC-V SoC / machine codes plus generic
+endian, the HTIF device aims to interface with little endian
-codes. Let's move riscv_htif model to hw/char directory.
+memory accesses, thus we can explicit htif_mm_ops:endianness
 being DEVICE_LITTLE_ENDIAN.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+In that case tswap64() is equivalent to le64_to_cpu(), as in
 "convert this 64-bit little-endian value into host cpu order".
 Replace to simplify.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20241129154304.34946-3-philmd@linaro.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => char}/riscv_htif.h | 0
+ hw/char/riscv_htif.c | 11 ++++++-----
- hw/{riscv => char}/riscv_htif.c         | 2 +-
+file changed, 6 insertions(+), 5 deletions(-)
  hw/riscv/spike.c                        | 2 +-
  hw/char/Kconfig                         | 3 +++
  hw/char/meson.build                     | 1 +
  hw/riscv/Kconfig                        | 3 ---
  hw/riscv/meson.build                    | 1 -
 files changed, 6 insertions(+), 6 deletions(-)
  rename include/hw/{riscv => char}/riscv_htif.h (100%)
  rename hw/{riscv => char}/riscv_htif.c (99%)
-diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
+diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
 similarity index 100%
 rename from include/hw/riscv/riscv_htif.h
 rename to include/hw/char/riscv_htif.h
 diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
 similarity index 99%
 rename from hw/riscv/riscv_htif.c
 rename to hw/char/riscv_htif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/riscv_htif.c
+--- a/hw/char/riscv_htif.c
 +++ b/hw/char/riscv_htif.c
 @@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "qemu/log.h"
- #include "hw/sysbus.h"
-+#include "hw/char/riscv_htif.h"
- #include "hw/char/serial.h"
- #include "chardev/char.h"
- #include "chardev/char-fe.h"
--#include "hw/riscv/riscv_htif.h"
  #include "qemu/timer.h"
  #include "qemu/error-report.h"
+ #include "exec/address-spaces.h"
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+-#include "exec/tswap.h"
-index XXXXXXX..XXXXXXX 100644
++#include "qemu/bswap.h"
---- a/hw/riscv/spike.c
+ #include "sysemu/dma.h"
-+++ b/hw/riscv/spike.c
+ #include "sysemu/runstate.h"
-@@ -XXX,XX +XXX,XX @@
- #include "hw/loader.h"
+@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
- #include "hw/sysbus.h"
+             } else {
- #include "target/riscv/cpu.h"
+                 uint64_t syscall[8];
--#include "hw/riscv/riscv_htif.h"
+                 cpu_physical_memory_read(payload, syscall, sizeof(syscall));
- #include "hw/riscv/riscv_hart.h"
+-                if (tswap64(syscall[0]) == PK_SYS_WRITE &&
- #include "hw/riscv/spike.h"
+-                    tswap64(syscall[1]) == HTIF_DEV_CONSOLE &&
- #include "hw/riscv/boot.h"
+-                    tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
- #include "hw/riscv/numa.h"
++                if (le64_to_cpu(syscall[0]) == PK_SYS_WRITE &&
-+#include "hw/char/riscv_htif.h"
++                    le64_to_cpu(syscall[1]) == HTIF_DEV_CONSOLE &&
- #include "hw/intc/sifive_clint.h"
++                    le64_to_cpu(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
- #include "chardev/char.h"
+                     uint8_t ch;
- #include "sysemu/arch_init.h"
+-                    cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1);
-diff --git a/hw/char/Kconfig b/hw/char/Kconfig
++                    cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch, 1);
-index XXXXXXX..XXXXXXX 100644
+                     /*
---- a/hw/char/Kconfig
+                      * XXX this blocks entire thread. Rewrite to use
-+++ b/hw/char/Kconfig
+                      * qemu_chr_fe_write and background I/O callbacks
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void htif_mm_write(void *opaque, hwaddr addr,
- config ESCC
+ static const MemoryRegionOps htif_mm_ops = {
-     bool
+     .read = htif_mm_read,
+     .write = htif_mm_write,
-+config HTIF
++    .endianness = DEVICE_LITTLE_ENDIAN,
-+    bool
+ };
-+
- config PARALLEL
+ HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
      bool
      default y
 diff --git a/hw/char/meson.build b/hw/char/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/meson.build
 +++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
 +specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
  specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
  specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
  specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@
 -config HTIF
 -    bool
 -
  config HART
      bool
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 --
-.28.0
+.47.1

-[PULL 09/30] hw/sd: Add Cadence SDHCI emulation
+[PULL 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses
-From: Bin Meng <bin.meng@windriver.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
+Looking at htif_mm_ops[] read/write handlers, we notice they
-controller. The SDHCI compatible registers start from offset 0x200,
+expect 32-bit values to accumulate into to the 'fromhost' and
-which are called Slot Register Set (SRS) in its datasheet.
+'tohost' 64-bit variables. Explicit by setting the .impl
 min/max fields.
-This creates a Cadence SDHCI model built on top of the existing
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 generic SDHCI model. Cadence specific Host Register Set (HRS) is
 implemented to make guest software happy.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20241129154304.34946-4-philmd@linaro.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/sd/cadence_sdhci.h |  47 +++++++++
+ hw/char/riscv_htif.c | 4 ++++
- hw/sd/cadence_sdhci.c         | 193 ++++++++++++++++++++++++++++++++++
+file changed, 4 insertions(+)
  hw/sd/Kconfig                 |   4 +
  hw/sd/meson.build             |   1 +
 files changed, 245 insertions(+)
  create mode 100644 include/hw/sd/cadence_sdhci.h
  create mode 100644 hw/sd/cadence_sdhci.c
-diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h
+diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/hw/char/riscv_htif.c
---- /dev/null
++++ b/hw/char/riscv_htif.c
-+++ b/include/hw/sd/cadence_sdhci.h
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = {
-@@ -XXX,XX +XXX,XX @@
+     .read = htif_mm_read,
-+/*
+     .write = htif_mm_write,
-+ * Cadence SDHCI emulation
+     .endianness = DEVICE_LITTLE_ENDIAN,
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef CADENCE_SDHCI_H
 +#define CADENCE_SDHCI_H
 +
 +#include "hw/sd/sdhci.h"
 +
 +#define CADENCE_SDHCI_REG_SIZE  0x100
 +#define CADENCE_SDHCI_NUM_REGS  (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
 +
 +typedef struct CadenceSDHCIState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion container;
 +    MemoryRegion iomem;
 +    BusState *bus;
 +
 +    uint32_t regs[CADENCE_SDHCI_NUM_REGS];
 +
 +    SDHCIState sdhci;
 +} CadenceSDHCIState;
 +
 +#define TYPE_CADENCE_SDHCI  "cadence.sdhci"
 +#define CADENCE_SDHCI(obj)  OBJECT_CHECK(CadenceSDHCIState, (obj), \
 +                                         TYPE_CADENCE_SDHCI)
 +
 +#endif /* CADENCE_SDHCI_H */
 diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/sd/cadence_sdhci.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Cadence SDHCI emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qapi/error.h"
 +#include "migration/vmstate.h"
 +#include "hw/irq.h"
 +#include "hw/sd/cadence_sdhci.h"
 +#include "sdhci-internal.h"
 +
 +/* HRS - Host Register Set (specific to Cadence) */
 +
 +#define CADENCE_SDHCI_HRS00             0x00    /* general information */
 +#define CADENCE_SDHCI_HRS00_SWR             BIT(0)
 +#define CADENCE_SDHCI_HRS00_POR_VAL         0x00010000
 +
 +#define CADENCE_SDHCI_HRS04             0x10    /* PHY access port */
 +#define CADENCE_SDHCI_HRS04_WR              BIT(24)
 +#define CADENCE_SDHCI_HRS04_RD              BIT(25)
 +#define CADENCE_SDHCI_HRS04_ACK             BIT(26)
 +
 +#define CADENCE_SDHCI_HRS06             0x18    /* eMMC control */
 +#define CADENCE_SDHCI_HRS06_TUNE_UP         BIT(15)
 +
 +/* SRS - Slot Register Set (SDHCI-compatible) */
 +
 +#define CADENCE_SDHCI_SRS_BASE          0x200
 +
 +#define TO_REG(addr)    ((addr) / sizeof(uint32_t))
 +
 +static void cadence_sdhci_instance_init(Object *obj)
 +{
 +    CadenceSDHCIState *s = CADENCE_SDHCI(obj);
 +
 +    object_initialize_child(OBJECT(s), "generic-sdhci",
 +                            &s->sdhci, TYPE_SYSBUS_SDHCI);
 +}
 +
 +static void cadence_sdhci_reset(DeviceState *dev)
 +{
 +    CadenceSDHCIState *s = CADENCE_SDHCI(dev);
 +
 +    memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE);
 +    s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL;
 +
 +    device_cold_reset(DEVICE(&s->sdhci));
 +}
 +
 +static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
 +{
 +    CadenceSDHCIState *s = opaque;
 +    uint32_t val;
 +
 +    val = s->regs[TO_REG(addr)];
 +
 +    return (uint64_t)val;
 +}
 +
 +static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
 +                                unsigned int size)
 +{
 +    CadenceSDHCIState *s = opaque;
 +    uint32_t val32 = (uint32_t)val;
 +
 +    switch (addr) {
 +    case CADENCE_SDHCI_HRS00:
 +        /*
 +         * The only writable bit is SWR (software reset) and it automatically
 +         * clears to zero, so essentially this register remains unchanged.
 +         */
 +        if (val32 & CADENCE_SDHCI_HRS00_SWR) {
 +            cadence_sdhci_reset(DEVICE(s));
 +        }
 +
 +        break;
 +    case CADENCE_SDHCI_HRS04:
 +        /*
 +         * Only emulate the ACK bit behavior when read or write transaction
 +         * are requested.
 +         */
 +        if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) {
 +            val32 |= CADENCE_SDHCI_HRS04_ACK;
 +        } else {
 +            val32 &= ~CADENCE_SDHCI_HRS04_ACK;
 +        }
 +
 +        s->regs[TO_REG(addr)] = val32;
 +        break;
 +    case CADENCE_SDHCI_HRS06:
 +        if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) {
 +            val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP;
 +        }
 +
 +        s->regs[TO_REG(addr)] = val32;
 +        break;
 +    default:
 +        s->regs[TO_REG(addr)] = val32;
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps cadence_sdhci_ops = {
 +    .read = cadence_sdhci_read,
 +    .write = cadence_sdhci_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .impl = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
-+    .valid = {
+ };
-+        .min_access_size = 4,
-+        .max_access_size = 4,
+ HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
 +    }
 +};
 +
 +static void cadence_sdhci_realize(DeviceState *dev, Error **errp)
 +{
 +    CadenceSDHCIState *s = CADENCE_SDHCI(dev);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
 +
 +    memory_region_init(&s->container, OBJECT(s),
 +                       "cadence.sdhci-container", 0x1000);
 +    sysbus_init_mmio(sbd, &s->container);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops,
 +                          s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE);
 +    memory_region_add_subregion(&s->container, 0, &s->iomem);
 +
 +    sysbus_realize(sbd_sdhci, errp);
 +    memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE,
 +                                sysbus_mmio_get_region(sbd_sdhci, 0));
 +
 +    /* propagate irq and "sd-bus" from generic-sdhci */
 +    sysbus_pass_irq(sbd, sbd_sdhci);
 +    s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
 +}
 +
 +static const VMStateDescription vmstate_cadence_sdhci = {
 +    .name = TYPE_CADENCE_SDHCI,
 +    .version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(classp);
 +
 +    dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)";
 +    dc->realize = cadence_sdhci_realize;
 +    dc->reset = cadence_sdhci_reset;
 +    dc->vmsd = &vmstate_cadence_sdhci;
 +}
 +
 +static TypeInfo cadence_sdhci_info = {
 +    .name          = TYPE_CADENCE_SDHCI,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(CadenceSDHCIState),
 +    .instance_init = cadence_sdhci_instance_init,
 +    .class_init    = cadence_sdhci_class_init,
 +};
 +
 +static void cadence_sdhci_register_types(void)
 +{
 +    type_register_static(&cadence_sdhci_info);
 +}
 +
 +type_init(cadence_sdhci_register_types)
 diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/Kconfig
 +++ b/hw/sd/Kconfig
@@ -XXX,XX +XXX,XX @@ config SDHCI_PCI
      default y if PCI_DEVICES
      depends on PCI
      select SDHCI
 +
 +config CADENCE_SDHCI
 +    bool
 +    select SDHCI
 diff --git a/hw/sd/meson.build b/hw/sd/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/meson.build
 +++ b/hw/sd/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c'))
  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
  softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
 +softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
 --
-.28.0
+.47.1

-[PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency
+[PULL 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
-From: Bin Meng <bin.meng@windriver.com>
+From: Jim Shu <jim.shu@sifive.com>
-At present the CLINT timestamp is using a hard-coded timebase
+Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
-frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
+system doesn't have 32-bit addressable issue, we just load DTB to the end
-true for all boards.
+of dram in 64-bit system.
-Add a new 'timebase-freq' property to the CLINT device, and
+Signed-off-by: Jim Shu <jim.shu@sifive.com>
 update various functions to accept this as a parameter.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20241120153935.24706-2-jim.shu@sifive.com>
 [ Changes by AF
  -  Store fdt_load_addr_hi32 in the reset vector
 ]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/sifive_clint.h |  4 +++-
+ include/hw/riscv/boot.h    |  2 +-
- target/riscv/cpu.h              |  6 ++++--
+ hw/riscv/boot.c            | 14 +++++++++-----
- hw/riscv/microchip_pfsoc.c      |  6 +++++-
+ hw/riscv/microchip_pfsoc.c |  4 ++--
- hw/riscv/sifive_clint.c         | 26 +++++++++++++++-----------
+ hw/riscv/sifive_u.c        |  8 +++++---
- hw/riscv/sifive_e.c             |  3 ++-
+ hw/riscv/spike.c           |  4 ++--
- hw/riscv/sifive_u.c             |  3 ++-
+ hw/riscv/virt.c            |  2 +-
- hw/riscv/spike.c                |  3 ++-
+files changed, 20 insertions(+), 14 deletions(-)
  hw/riscv/virt.c                 |  3 ++-
  target/riscv/cpu_helper.c       |  4 +++-
  target/riscv/csr.c              |  4 ++--
 files changed, 40 insertions(+), 22 deletions(-)
-diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
+diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_clint.h
+--- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/sifive_clint.h
++++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
+@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
-     uint32_t timecmp_base;
+                                bool load_initrd,
-     uint32_t time_base;
+                                symbol_fn_t sym_cb);
-     uint32_t aperture_size;
+ uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
-+    uint32_t timebase_freq;
+-                                MachineState *ms);
- } SiFiveCLINTState;
++                                MachineState *ms, RISCVHartArrayState *harts);
+ void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
- DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
+ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
-     uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
+                                hwaddr saddr,
--    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 +    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
 +    bool provide_rdtime);
  enum {
      SIFIVE_SIP_BASE     = 0x0,
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/hw/riscv/boot.c
-+++ b/target/riscv/cpu.h
++++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ out:
-     pmp_table_t pmp_state;
+  * The FDT is fdt_packed() during the calculation.
+  */
-     /* machine specific rdtime callback */
+ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
--    uint64_t (*rdtime_fn)(void);
+-                                MachineState *ms)
-+    uint64_t (*rdtime_fn)(uint32_t);
++                                MachineState *ms, RISCVHartArrayState *harts)
-+    uint32_t rdtime_fn_arg;
+ {
+     int ret = fdt_pack(ms->fdt);
-     /* True if in debugger mode.  */
+     hwaddr dram_end, temp;
-     bool debugger;
+@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
- int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
+     /*
- uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
+      * We should put fdt as far as possible to avoid kernel/initrd overwriting
- #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
+-     * its content. But it should be addressable by 32 bit system as well.
--void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
+-     * Thus, put it at an 2MB aligned address that less than fdt size from the
-+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+-     * end of dram or 3GB whichever is lesser.
-+                             uint32_t arg);
++     * its content. But it should be addressable by 32 bit system as well in RV32.
- #endif
++     * Thus, put it near to the end of dram in RV64, and put it near to the end
- void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
++     * of dram or 3GB whichever is lesser in RV32.
+      */
 -    temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
 +    if (!riscv_is_32bit(harts)) {
 +        temp = dram_end;
 +    } else {
 +        temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
 +    }
      return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
  }
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
- #define BIOS_FILENAME   "hss.bin"
+     bool kernel_as_payload = false;
- #define RESET_VECTOR    0x20220000
+     target_ulong firmware_end_addr, kernel_start_addr;
+     uint64_t kernel_entry;
-+/* CLINT timebase frequency */
+-    uint32_t fdt_load_addr;
-+#define CLINT_TIMEBASE_FREQ 1000000
++    uint64_t fdt_load_addr;
-+
+     DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
- /* GEM version */
- #define GEM_REVISION    0x0107010c
+     /* Sanity check on RAM size */
+@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+         /* Compute the fdt load address in dram */
-     /* CLINT */
+         fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
-     sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
+                                                memmap[MICROCHIP_PFSOC_DRAM_LO].size,
-         memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
+-                                               machine);
--        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
++                                               machine, &s->soc.u_cpus);
-+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+         riscv_load_fdt(fdt_load_addr, machine->fdt);
-+        CLINT_TIMEBASE_FREQ, false);
+         /* Load the reset vector */
      /* L2 cache controller */
      create_unimplemented_device("microchip.pfsoc.l2cc",
 diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_clint.c
 +++ b/hw/riscv/sifive_clint.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/riscv/sifive_clint.h"
  #include "qemu/timer.h"
 -static uint64_t cpu_riscv_read_rtc(void)
 +static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
  {
      return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 -        SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
 +        timebase_freq, NANOSECONDS_PER_SECOND);
  }
  /*
   * Called when timecmp is written to update the QEMU timer or immediately
   * trigger timer interrupt if mtimecmp <= current timer value.
   */
 -static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
 +static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
 +                                       uint32_t timebase_freq)
  {
      uint64_t next;
      uint64_t diff;
 -    uint64_t rtc_r = cpu_riscv_read_rtc();
 +    uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
      cpu->env.timecmp = value;
      if (cpu->env.timecmp <= rtc_r) {
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
      diff = cpu->env.timecmp - rtc_r;
      /* back to ns (note args switched in muldiv64) */
      next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 -        muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
 +        muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
      timer_mod(cpu->env.timer, next);
  }
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
          }
      } else if (addr == clint->time_base) {
          /* time_lo */
 -        return cpu_riscv_read_rtc() & 0xFFFFFFFF;
 +        return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF;
      } else if (addr == clint->time_base + 4) {
          /* time_hi */
 -        return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
 +        return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF;
      }
      error_report("clint: invalid read: %08x", (uint32_t)addr);
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
              /* timecmp_lo */
              uint64_t timecmp_hi = env->timecmp >> 32;
              sifive_clint_write_timecmp(RISCV_CPU(cpu),
 -                timecmp_hi << 32 | (value & 0xFFFFFFFF));
 +                timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq);
              return;
          } else if ((addr & 0x7) == 4) {
              /* timecmp_hi */
              uint64_t timecmp_lo = env->timecmp;
              sifive_clint_write_timecmp(RISCV_CPU(cpu),
 -                value << 32 | (timecmp_lo & 0xFFFFFFFF));
 +                value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq);
          } else {
              error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
          }
@@ -XXX,XX +XXX,XX @@ static Property sifive_clint_properties[] = {
      DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
      DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
      DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
 +    DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types)
   */
  DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
      uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
 -    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
 +    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
 +    bool provide_rdtime)
  {
      int i;
      for (i = 0; i < num_harts; i++) {
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
              continue;
          }
          if (provide_rdtime) {
 -            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
 +            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
          }
          env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                    &sifive_clint_timer_cb, cpu);
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
      qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
      qdev_prop_set_uint32(dev, "time-base", time_base);
      qdev_prop_set_uint32(dev, "aperture-size", size);
 +    qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
      sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
      return dev;
 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_e.c
 +++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
          memmap[SIFIVE_E_PLIC].size);
      sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
          memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
 -        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
 +        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 +        SIFIVE_CLINT_TIMEBASE_FREQ, false);
      create_unimplemented_device("riscv.sifive.e.aon",
          memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
      sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
-         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
+     target_ulong firmware_end_addr, kernel_start_addr;
-     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
+     const char *firmware_name;
-         memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
+     uint32_t start_addr_hi32 = 0x00000000;
--        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
++    uint32_t fdt_load_addr_hi32 = 0x00000000;
-+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+     int i;
-+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
+-    uint32_t fdt_load_addr;
++    uint64_t fdt_load_addr;
-     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
+     uint64_t kernel_entry;
-         return;
+     DriveInfo *dinfo;
      BlockBackend *blk;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
      fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
                                             memmap[SIFIVE_U_DEV_DRAM].size,
 -                                           machine);
 +                                           machine, &s->soc.u_cpus);
      riscv_load_fdt(fdt_load_addr, machine->fdt);
      if (!riscv_is_32bit(&s->soc.u_cpus)) {
          start_addr_hi32 = (uint64_t)start_addr >> 32;
 +        fdt_load_addr_hi32 = fdt_load_addr >> 32;
      }
      /* reset vector */
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
          start_addr,                    /* start: .dword */
          start_addr_hi32,
          fdt_load_addr,                 /* fdt_laddr: .dword */
 -        0x00000000,
 +        fdt_load_addr_hi32,
 x00000000,
                                         /* fw_dyn: */
      };
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
 @@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-         sifive_clint_create(
+     hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base;
-             memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
+     target_ulong kernel_start_addr;
-             memmap[SPIKE_CLINT].size, base_hartid, hart_count,
+     char *firmware_name;
--            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+-    uint32_t fdt_load_addr;
-+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
++    uint64_t fdt_load_addr;
-+            SIFIVE_CLINT_TIMEBASE_FREQ, false);
+     uint64_t kernel_entry;
-     }
+     char *soc_name;
+     int i, base_hartid, hart_count;
-     /* register system main memory (actual RAM) */
+@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
                                             memmap[SPIKE_DRAM].size,
 -                                           machine);
 +                                           machine, &s->soc[0]);
      riscv_load_fdt(fdt_load_addr, machine->fdt);
      /* load the reset vector */
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
-         sifive_clint_create(
-             memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
+     fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
-             memmap[VIRT_CLINT].size, base_hartid, hart_count,
+                                            memmap[VIRT_DRAM].size,
--            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
+-                                           machine);
-+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
++                                           machine, &s->soc[0]);
-+            SIFIVE_CLINT_TIMEBASE_FREQ, true);
+     riscv_load_fdt(fdt_load_addr, machine->fdt);
-         /* Per-socket PLIC hart topology configuration string */
+     /* load the reset vector */
          plic_hart_config_len =
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
      return old;
  }
 -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
 +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
 +                             uint32_t arg)
  {
      env->rdtime_fn = fn;
 +    env->rdtime_fn_arg = arg;
  }
  void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
          return -RISCV_EXCP_ILLEGAL_INST;
      }
 -    *val = env->rdtime_fn() + delta;
 +    *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
          return -RISCV_EXCP_ILLEGAL_INST;
      }
 -    *val = (env->rdtime_fn() + delta) >> 32;
 +    *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
      return 0;
  }
  #endif
 --
-.28.0
+.47.1

-[PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc
+[PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo
-From: Bin Meng <bin.meng@windriver.com>
+From: Jim Shu <jim.shu@sifive.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Add a new struct RISCVBootInfo to sync boot information between multiple
-should only contain the RISC-V SoC / machine codes plus generic
+boot functions.
 codes. Let's move sifive_clint model to hw/intc directory.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Jim Shu <jim.shu@sifive.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20241120153935.24706-3-jim.shu@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => intc}/sifive_clint.h | 0
+ include/hw/riscv/boot.h    | 25 ++++++++++-----
- hw/{riscv => intc}/sifive_clint.c         | 2 +-
+ hw/riscv/boot.c            | 65 ++++++++++++++++++++++----------------
- hw/riscv/microchip_pfsoc.c                | 2 +-
+ hw/riscv/microchip_pfsoc.c | 11 ++++---
- hw/riscv/sifive_e.c                       | 2 +-
+ hw/riscv/opentitan.c       |  4 ++-
- hw/riscv/sifive_u.c                       | 2 +-
+ hw/riscv/sifive_e.c        |  4 ++-
- hw/riscv/spike.c                          | 2 +-
+ hw/riscv/sifive_u.c        | 12 ++++---
- hw/riscv/virt.c                           | 2 +-
+ hw/riscv/spike.c           | 12 ++++---
- hw/intc/Kconfig                           | 3 +++
+ hw/riscv/virt.c            | 13 +++++---
- hw/intc/meson.build                       | 1 +
+files changed, 90 insertions(+), 56 deletions(-)
  hw/riscv/Kconfig                          | 5 +++++
  hw/riscv/meson.build                      | 1 -
 files changed, 15 insertions(+), 7 deletions(-)
  rename include/hw/{riscv => intc}/sifive_clint.h (100%)
  rename hw/{riscv => intc}/sifive_clint.c (99%)
-diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
+diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
-similarity index 100%
+index XXXXXXX..XXXXXXX 100644
-rename from include/hw/riscv/sifive_clint.h
+--- a/include/hw/riscv/boot.h
-rename to include/hw/intc/sifive_clint.h
++++ b/include/hw/riscv/boot.h
 diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
 similarity index 99%
 rename from hw/riscv/sifive_clint.c
 rename to hw/intc/sifive_clint.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_clint.c
 +++ b/hw/intc/sifive_clint.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
+ #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
- #include "target/riscv/cpu.h"
+ #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
- #include "hw/qdev-properties.h"
--#include "hw/riscv/sifive_clint.h"
++typedef struct RISCVBootInfo {
-+#include "hw/intc/sifive_clint.h"
++    ssize_t kernel_size;
- #include "qemu/timer.h"
++    hwaddr image_low_addr;
++    hwaddr image_high_addr;
- static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
++
 +    bool is_32bit;
 +} RISCVBootInfo;
 +
  bool riscv_is_32bit(RISCVHartArrayState *harts);
  char *riscv_plic_hart_config_string(int hart_count);
 -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
 +void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
 +target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
                                            target_ulong firmware_end_addr);
  target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                            const char *default_machine_firmware,
@@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename,
  target_ulong riscv_load_firmware(const char *firmware_filename,
                                   hwaddr *firmware_load_addr,
                                   symbol_fn_t sym_cb);
 -target_ulong riscv_load_kernel(MachineState *machine,
 -                               RISCVHartArrayState *harts,
 -                               target_ulong firmware_end_addr,
 -                               bool load_initrd,
 -                               symbol_fn_t sym_cb);
 -uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
 -                                MachineState *ms, RISCVHartArrayState *harts);
 +void riscv_load_kernel(MachineState *machine,
 +                       RISCVBootInfo *info,
 +                       target_ulong kernel_start_addr,
 +                       bool load_initrd,
 +                       symbol_fn_t sym_cb);
 +uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
 +                                MachineState *ms, RISCVBootInfo *info);
  void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
  void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
                                 hwaddr saddr,
 diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ char *riscv_plic_hart_config_string(int hart_count)
      return g_strjoinv(",", (char **)vals);
  }
 -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
 +void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
 +{
 +    info->kernel_size = 0;
 +    info->is_32bit = riscv_is_32bit(harts);
 +}
 +
 +target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
                                            target_ulong firmware_end_addr) {
 -    if (riscv_is_32bit(harts)) {
 +    if (info->is_32bit) {
          return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
      } else {
          return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
      exit(1);
  }
 -static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
 +static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
  {
      const char *filename = machine->initrd_filename;
      uint64_t mem_size = machine->ram_size;
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
       * halfway into RAM, and for boards with 1GB of RAM or more we put
       * the initrd at 512MB.
       */
 -    start = kernel_entry + MIN(mem_size / 2, 512 * MiB);
 +    start = info->image_low_addr + MIN(mem_size / 2, 512 * MiB);
      size = load_ramdisk(filename, start, mem_size - start);
      if (size == -1) {
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
      }
  }
 -target_ulong riscv_load_kernel(MachineState *machine,
 -                               RISCVHartArrayState *harts,
 -                               target_ulong kernel_start_addr,
 -                               bool load_initrd,
 -                               symbol_fn_t sym_cb)
 +void riscv_load_kernel(MachineState *machine,
 +                       RISCVBootInfo *info,
 +                       target_ulong kernel_start_addr,
 +                       bool load_initrd,
 +                       symbol_fn_t sym_cb)
  {
      const char *kernel_filename = machine->kernel_filename;
 -    uint64_t kernel_load_base, kernel_entry;
 +    ssize_t kernel_size;
      void *fdt = machine->fdt;
      g_assert(kernel_filename != NULL);
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
       * the (expected) load address load address. This allows kernels to have
       * separate SBI and ELF entry points (used by FreeBSD, for example).
       */
 -    if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
 -                         NULL, &kernel_load_base, NULL, NULL, 0,
 -                         EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
 -        kernel_entry = kernel_load_base;
 +    kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL,
 +                                   &info->image_low_addr, &info->image_high_addr,
 +                                   NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb);
 +    if (kernel_size > 0) {
 +        info->kernel_size = kernel_size;
          goto out;
      }
 -    if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
 -                       NULL, NULL, NULL) > 0) {
 +    kernel_size = load_uimage_as(kernel_filename, &info->image_low_addr,
 +                                 NULL, NULL, NULL, NULL, NULL);
 +    if (kernel_size > 0) {
 +        info->kernel_size = kernel_size;
 +        info->image_high_addr = info->image_low_addr + kernel_size;
          goto out;
      }
 -    if (load_image_targphys_as(kernel_filename, kernel_start_addr,
 -                               current_machine->ram_size, NULL) > 0) {
 -        kernel_entry = kernel_start_addr;
 +    kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr,
 +                                         current_machine->ram_size, NULL);
 +    if (kernel_size > 0) {
 +        info->kernel_size = kernel_size;
 +        info->image_low_addr = kernel_start_addr;
 +        info->image_high_addr = info->image_low_addr + kernel_size;
          goto out;
      }
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
  out:
      /*
 -     * For 32 bit CPUs 'kernel_entry' can be sign-extended by
 +     * For 32 bit CPUs 'image_low_addr' can be sign-extended by
       * load_elf_ram_sym().
       */
 -    if (riscv_is_32bit(harts)) {
 -        kernel_entry = extract64(kernel_entry, 0, 32);
 +    if (info->is_32bit) {
 +        info->image_low_addr = extract64(info->image_low_addr, 0, 32);
      }
      if (load_initrd && machine->initrd_filename) {
 -        riscv_load_initrd(machine, kernel_entry);
 +        riscv_load_initrd(machine, info);
      }
      if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
          qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
                                  machine->kernel_cmdline);
      }
 -
 -    return kernel_entry;
  }
  /*
@@ -XXX,XX +XXX,XX @@ out:
   * The FDT is fdt_packed() during the calculation.
   */
  uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
 -                                MachineState *ms, RISCVHartArrayState *harts)
 +                                MachineState *ms, RISCVBootInfo *info)
  {
      int ret = fdt_pack(ms->fdt);
      hwaddr dram_end, temp;
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
       * Thus, put it near to the end of dram in RV64, and put it near to the end
       * of dram or 3GB whichever is lesser in RV32.
       */
 -    if (!riscv_is_32bit(harts)) {
 +    if (!info->is_32bit) {
          temp = dram_end;
      } else {
          temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
- #include "hw/misc/unimp.h"
+     uint64_t kernel_entry;
- #include "hw/riscv/boot.h"
+     uint64_t fdt_load_addr;
- #include "hw/riscv/riscv_hart.h"
+     DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
--#include "hw/riscv/sifive_clint.h"
++    RISCVBootInfo boot_info;
- #include "hw/riscv/sifive_plic.h"
- #include "hw/riscv/microchip_pfsoc.h"
+     /* Sanity check on RAM size */
-+#include "hw/intc/sifive_clint.h"
+     if (machine->ram_size < mc->default_ram_size) {
- #include "sysemu/sysemu.h"
+@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
+     firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
- /*
+                                                      &firmware_load_addr, NULL);
 +    riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
      if (kernel_as_payload) {
 -        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
 +        kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
                                                           firmware_end_addr);
 -        kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
 -                                         kernel_start_addr, true, NULL);
 +        riscv_load_kernel(machine, &boot_info, kernel_start_addr,
 +                          true, NULL);
 +        kernel_entry = boot_info.image_low_addr;
          /* Compute the fdt load address in dram */
          fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
                                                 memmap[MICROCHIP_PFSOC_DRAM_LO].size,
 -                                               machine, &s->soc.u_cpus);
 +                                               machine, &boot_info);
          riscv_load_fdt(fdt_load_addr, machine->fdt);
          /* Load the reset vector */
 diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/opentitan.c
 +++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void opentitan_machine_init(MachineState *machine)
      OpenTitanState *s = OPENTITAN_MACHINE(machine);
      const MemMapEntry *memmap = ibex_memmap;
      MemoryRegion *sys_mem = get_system_memory();
 +    RISCVBootInfo boot_info;
      if (machine->ram_size != mc->default_ram_size) {
          char *sz = size_to_str(mc->default_ram_size);
@@ -XXX,XX +XXX,XX @@ static void opentitan_machine_init(MachineState *machine)
          riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);
      }
 +    riscv_boot_info_init(&boot_info, &s->soc.cpus);
      if (machine->kernel_filename) {
 -        riscv_load_kernel(machine, &s->soc.cpus,
 +        riscv_load_kernel(machine, &boot_info,
                            memmap[IBEX_DEV_RAM].base,
                            false, NULL);
      }
 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_e.c
 +++ b/hw/riscv/sifive_e.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_init(MachineState *machine)
- #include "target/riscv/cpu.h"
+     SiFiveEState *s = RISCV_E_MACHINE(machine);
- #include "hw/riscv/riscv_hart.h"
+     MemoryRegion *sys_mem = get_system_memory();
- #include "hw/riscv/sifive_plic.h"
+     int i;
--#include "hw/riscv/sifive_clint.h"
++    RISCVBootInfo boot_info;
- #include "hw/riscv/sifive_uart.h"
- #include "hw/riscv/sifive_e.h"
+     if (machine->ram_size != mc->default_ram_size) {
- #include "hw/riscv/boot.h"
+         char *sz = size_to_str(mc->default_ram_size);
-+#include "hw/intc/sifive_clint.h"
+@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_init(MachineState *machine)
- #include "hw/misc/sifive_e_prci.h"
+     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- #include "chardev/char.h"
+                           memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
- #include "sysemu/arch_init.h"
 +    riscv_boot_info_init(&boot_info, &s->soc.cpus);
      if (machine->kernel_filename) {
 -        riscv_load_kernel(machine, &s->soc.cpus,
 +        riscv_load_kernel(machine, &boot_info,
                            memmap[SIFIVE_E_DEV_DTIM].base,
                            false, NULL);
      }
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
- #include "target/riscv/cpu.h"
+     BlockBackend *blk;
- #include "hw/riscv/riscv_hart.h"
+     DeviceState *flash_dev, *sd_dev, *card_dev;
- #include "hw/riscv/sifive_plic.h"
+     qemu_irq flash_cs, sd_cs;
--#include "hw/riscv/sifive_clint.h"
++    RISCVBootInfo boot_info;
- #include "hw/riscv/sifive_uart.h"
- #include "hw/riscv/sifive_u.h"
+     /* Initialize SoC */
- #include "hw/riscv/boot.h"
+     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
-+#include "hw/intc/sifive_clint.h"
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
- #include "chardev/char.h"
+     firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
- #include "net/eth.h"
+                                                      &start_addr, NULL);
- #include "sysemu/arch_init.h"
 +    riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
      if (machine->kernel_filename) {
 -        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
 +        kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
                                                           firmware_end_addr);
 -
 -        kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
 -                                         kernel_start_addr, true, NULL);
 +        riscv_load_kernel(machine, &boot_info, kernel_start_addr,
 +                          true, NULL);
 +        kernel_entry = boot_info.image_low_addr;
      } else {
         /*
          * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
      fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
                                             memmap[SIFIVE_U_DEV_DRAM].size,
 -                                           machine, &s->soc.u_cpus);
 +                                           machine, &boot_info);
      riscv_load_fdt(fdt_load_addr, machine->fdt);
      if (!riscv_is_32bit(&s->soc.u_cpus)) {
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
- #include "target/riscv/cpu.h"
+     char *soc_name;
- #include "hw/riscv/riscv_htif.h"
+     int i, base_hartid, hart_count;
- #include "hw/riscv/riscv_hart.h"
+     bool htif_custom_base = false;
--#include "hw/riscv/sifive_clint.h"
++    RISCVBootInfo boot_info;
- #include "hw/riscv/spike.h"
- #include "hw/riscv/boot.h"
+     /* Check socket count limit */
- #include "hw/riscv/numa.h"
+     if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
-+#include "hw/intc/sifive_clint.h"
+@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
- #include "chardev/char.h"
+     create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
- #include "sysemu/arch_init.h"
- #include "sysemu/device_tree.h"
+     /* Load kernel */
 +    riscv_boot_info_init(&boot_info, &s->soc[0]);
      if (machine->kernel_filename) {
 -        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
 +        kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
                                                           firmware_end_addr);
 -        kernel_entry = riscv_load_kernel(machine, &s->soc[0],
 -                                         kernel_start_addr,
 -                                         true, htif_symbol_callback);
 +        riscv_load_kernel(machine, &boot_info, kernel_start_addr,
 +                          true, htif_symbol_callback);
 +        kernel_entry = boot_info.image_low_addr;
      } else {
         /*
          * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
                                             memmap[SPIKE_DRAM].size,
 -                                           machine, &s->soc[0]);
 +                                           machine, &boot_info);
      riscv_load_fdt(fdt_load_addr, machine->fdt);
      /* load the reset vector */
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
- #include "target/riscv/cpu.h"
+     uint64_t fdt_load_addr;
- #include "hw/riscv/riscv_hart.h"
+     uint64_t kernel_entry = 0;
- #include "hw/riscv/sifive_plic.h"
+     BlockBackend *pflash_blk0;
--#include "hw/riscv/sifive_clint.h"
++    RISCVBootInfo boot_info;
- #include "hw/riscv/sifive_test.h"
- #include "hw/riscv/virt.h"
+     /*
- #include "hw/riscv/boot.h"
+      * An user provided dtb must include everything, including
- #include "hw/riscv/numa.h"
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
-+#include "hw/intc/sifive_clint.h"
+         }
- #include "chardev/char.h"
+     }
- #include "sysemu/arch_init.h"
- #include "sysemu/device_tree.h"
++    riscv_boot_info_init(&boot_info, &s->soc[0]);
 diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/Kconfig
 +++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config RX_ICU
  config LOONGSON_LIOINTC
      bool
 +
-+config SIFIVE_CLINT
+     if (machine->kernel_filename && !kernel_entry) {
-+    bool
+-        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
-diff --git a/hw/intc/meson.build b/hw/intc/meson.build
++        kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
-index XXXXXXX..XXXXXXX 100644
+                                                          firmware_end_addr);
---- a/hw/intc/meson.build
+-
-+++ b/hw/intc/meson.build
+-        kernel_entry = riscv_load_kernel(machine, &s->soc[0],
-@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
+-                                         kernel_start_addr, true, NULL);
- specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
++        riscv_load_kernel(machine, &boot_info, kernel_start_addr,
- specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
++                          true, NULL);
- specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
++        kernel_entry = boot_info.image_low_addr;
-+specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
+     }
- specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
- specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
+     fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
- specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
+                                            memmap[VIRT_DRAM].size,
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+-                                           machine, &s->soc[0]);
-index XXXXXXX..XXXXXXX 100644
++                                           machine, &boot_info);
---- a/hw/riscv/Kconfig
+     riscv_load_fdt(fdt_load_addr, machine->fdt);
-+++ b/hw/riscv/Kconfig
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
+     /* load the reset vector */
      bool
      select HART
      select SIFIVE
 +    select SIFIVE_CLINT
      select SIFIVE_GPIO
      select SIFIVE_E_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select CADENCE
      select HART
      select SIFIVE
 +    select SIFIVE_CLINT
      select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_U_OTP
@@ -XXX,XX +XXX,XX @@ config SPIKE
      select HART
      select HTIF
      select SIFIVE
 +    select SIFIVE_CLINT
  config OPENTITAN
      bool
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select PCI_EXPRESS_GENERIC_BRIDGE
      select PFLASH_CFI01
      select SIFIVE
 +    select SIFIVE_CLINT
  config MICROCHIP_PFSOC
      bool
      select HART
      select SIFIVE
 +    select SIFIVE_CLINT
      select UNIMP
      select MCHP_PFSOC_MMUART
      select SIFIVE_PDMA
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 --
-.28.0
+.47.1

-[PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller
+[PULL 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd
-From: Bin Meng <bin.meng@windriver.com>
+From: Jim Shu <jim.shu@sifive.com>
-SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
+DTB is placed to the end of memory, so we will check if the start
-channels. This connects the exsiting SiFive PDMA model to the SoC,
+address of DTB overlaps to the address of kernel/initrd.
 and adds its device tree data as well.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Jim Shu <jim.shu@sifive.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20241120153935.24706-4-jim.shu@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/sifive_u.h | 11 +++++++++++
+ include/hw/riscv/boot.h |  3 +++
- hw/riscv/sifive_u.c         | 30 ++++++++++++++++++++++++++++++
+ hw/riscv/boot.c         | 25 ++++++++++++++++++++++++-
- hw/riscv/Kconfig            |  1 +
+files changed, 27 insertions(+), 1 deletion(-)
 files changed, 42 insertions(+)
-diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
+diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/include/hw/riscv/boot.h
-+++ b/include/hw/riscv/sifive_u.h
++++ b/include/hw/riscv/boot.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct RISCVBootInfo {
- #ifndef HW_SIFIVE_U_H
+     hwaddr image_low_addr;
- #define HW_SIFIVE_U_H
+     hwaddr image_high_addr;
-+#include "hw/dma/sifive_pdma.h"
++    hwaddr initrd_start;
- #include "hw/net/cadence_gem.h"
++    ssize_t initrd_size;
- #include "hw/riscv/riscv_hart.h"
++
- #include "hw/riscv/sifive_cpu.h"
+     bool is_32bit;
-@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUSoCState {
+ } RISCVBootInfo;
-     SiFiveUPRCIState prci;
-     SIFIVEGPIOState gpio;
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
      SiFiveUOTPState otp;
 +    SiFivePDMAState dma;
      CadenceGEMState gem;
      uint32_t serial;
@@ -XXX,XX +XXX,XX @@ enum {
      SIFIVE_U_MROM,
      SIFIVE_U_CLINT,
      SIFIVE_U_L2CC,
 +    SIFIVE_U_PDMA,
      SIFIVE_U_L2LIM,
      SIFIVE_U_PLIC,
      SIFIVE_U_PRCI,
@@ -XXX,XX +XXX,XX @@ enum {
      SIFIVE_U_GPIO_IRQ13 = 20,
      SIFIVE_U_GPIO_IRQ14 = 21,
      SIFIVE_U_GPIO_IRQ15 = 22,
 +    SIFIVE_U_PDMA_IRQ0 = 23,
 +    SIFIVE_U_PDMA_IRQ1 = 24,
 +    SIFIVE_U_PDMA_IRQ2 = 25,
 +    SIFIVE_U_PDMA_IRQ3 = 26,
 +    SIFIVE_U_PDMA_IRQ4 = 27,
 +    SIFIVE_U_PDMA_IRQ5 = 28,
 +    SIFIVE_U_PDMA_IRQ6 = 29,
 +    SIFIVE_U_PDMA_IRQ7 = 30,
      SIFIVE_U_GEM_IRQ = 0x35
  };
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
+--- a/hw/riscv/boot.c
-+++ b/hw/riscv/sifive_u.c
++++ b/hw/riscv/boot.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ char *riscv_plic_hart_config_string(int hart_count)
-  * 4) GPIO (General Purpose Input/Output Controller)
+ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
-  * 5) OTP (One-Time Programmable) memory with stored serial number
+ {
-  * 6) GEM (Gigabit Ethernet Controller) and management block
+     info->kernel_size = 0;
-+ * 7) DMA (Direct Memory Access Controller)
++    info->initrd_size = 0;
-  *
+     info->is_32bit = riscv_is_32bit(harts);
-  * This board currently generates devicetree dynamically that indicates at least
+ }
-  * two harts and up to five harts.
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
-     [SIFIVE_U_MROM] =     {     0x1000,     0xf000 },
+         }
-     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
+     }
-     [SIFIVE_U_L2CC] =     {  0x2010000,     0x1000 },
-+    [SIFIVE_U_PDMA] =     {  0x3000000,   0x100000 },
++    info->initrd_start = start;
-     [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
++    info->initrd_size = size;
      [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
      [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
      qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
      g_free(nodename);
 +    nodename = g_strdup_printf("/soc/dma@%lx",
 +        (long)memmap[SIFIVE_U_PDMA].base);
 +    qemu_fdt_add_subnode(fdt, nodename);
 +    qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
 +    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
 +        SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
 +        SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
 +        SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
 +    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 +    qemu_fdt_setprop_cells(fdt, nodename, "reg",
 +        0x0, memmap[SIFIVE_U_PDMA].base,
 +        0x0, memmap[SIFIVE_U_PDMA].size);
 +    qemu_fdt_setprop_string(fdt, nodename, "compatible",
 +                            "sifive,fu540-c000-pdma");
 +    g_free(nodename);
 +
-     nodename = g_strdup_printf("/soc/cache-controller@%lx",
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
-         (long)memmap[SIFIVE_U_L2CC].base);
+     if (fdt) {
-     qemu_fdt_add_subnode(fdt, nodename);
+         end = start + size;
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
-     object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
+     int ret = fdt_pack(ms->fdt);
-     object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
+     hwaddr dram_end, temp;
-     object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
+     int fdtsize;
-+    object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
++    uint64_t dtb_start, dtb_start_limit;
- }
+     /* Should only fail if we've built a corrupted tree */
- static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
+     g_assert(ret == 0);
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
-                                             SIFIVE_U_GPIO_IRQ0 + i));
+         exit(1);
      }
-+    /* PDMA */
++    if (info->initrd_size) {
-+    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
++        /* If initrd is successfully loaded, place DTB after it. */
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
++        dtb_start_limit = info->initrd_start + info->initrd_size;
-+
++    } else if (info->kernel_size) {
-+    /* Connect PDMA interrupts to the PLIC */
++        /* If only kernel is successfully loaded, place DTB after it. */
-+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
++        dtb_start_limit = info->image_high_addr;
-+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
++    } else {
-+                           qdev_get_gpio_in(DEVICE(s->plic),
++        /* Otherwise, do not check DTB overlapping */
-+                                            SIFIVE_U_PDMA_IRQ0 + i));
++        dtb_start_limit = 0;
 +    }
 +
-     qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
+     /*
-     if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
+      * A dram_size == 0, usually from a MemMapEntry[].size element,
-         return;
+      * means that the DRAM block goes all the way to ms->ram_size.
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
-index XXXXXXX..XXXXXXX 100644
+         temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
---- a/hw/riscv/Kconfig
+     }
-+++ b/hw/riscv/Kconfig
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
+-    return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
-     select CADENCE
++    dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
-     select HART
++
-     select SIFIVE
++    if (dtb_start_limit && (dtb_start < dtb_start_limit)) {
-+    select SIFIVE_PDMA
++        error_report("No enough memory to place DTB after kernel/initrd");
-     select UNIMP
++        exit(1);
++    }
- config SPIKE
++
 +    return dtb_start;
  }
  /*
 --
-.28.0
+.47.1

-[PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers
+[PULL 29/39] target/riscv: Add svukte extension capability variable
-From: Bin Meng <bin.meng@windriver.com>
+From: "Fea.Wang" <fea.wang@sifive.com>
-Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
+Refer to the draft of svukte extension from:
-enough to create unimplemented devices to cover their register
+https://github.com/riscv/riscv-isa-manual/pull/1564
 spaces at this point.
-With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
+Svukte provides a means to make user-mode accesses to supervisor memory
-all the way to the Linux shell login prompt, with a modified HSS
+raise page faults in constant time, mitigating attacks that attempt to
-(1st stage bootloader).
+discover the supervisor software's address-space layout.
-For detailed instructions on how to create images for the Icicle
+Signed-off-by: Fea.Wang <fea.wang@sifive.com>
-Kit board, please check QEMU RISC-V WiKi page at:
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-https://wiki.qemu.org/Documentation/Platforms/RISCV
+Reviewed-by: Jim Shu <jim.shu@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-ID: <20241203034932.25185-2-fea.wang@sifive.com>
 Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h |  3 +++
+ target/riscv/cpu_cfg.h | 1 +
- hw/riscv/microchip_pfsoc.c         | 14 ++++++++++++++
+file changed, 1 insertion(+)
 files changed, 17 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ enum {
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-     MICROCHIP_PFSOC_MMUART4,
+     bool ext_svnapot;
-     MICROCHIP_PFSOC_GEM0,
+     bool ext_svpbmt;
-     MICROCHIP_PFSOC_GEM1,
+     bool ext_svvptc;
-+    MICROCHIP_PFSOC_GPIO0,
++    bool ext_svukte;
-+    MICROCHIP_PFSOC_GPIO1,
+     bool ext_zdinx;
-+    MICROCHIP_PFSOC_GPIO2,
+     bool ext_zaamo;
-     MICROCHIP_PFSOC_ENVM_CFG,
+     bool ext_zacas;
      MICROCHIP_PFSOC_ENVM_DATA,
      MICROCHIP_PFSOC_IOSCB_CFG,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
      [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
      [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
 +    [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,     0x1000 },
 +    [MICROCHIP_PFSOC_GPIO1] =           { 0x20121000,     0x1000 },
 +    [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
      [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
          qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
 +    /* GPIOs */
 +    create_unimplemented_device("microchip.pfsoc.gpio0",
 +        memmap[MICROCHIP_PFSOC_GPIO0].base,
 +        memmap[MICROCHIP_PFSOC_GPIO0].size);
 +    create_unimplemented_device("microchip.pfsoc.gpio1",
 +        memmap[MICROCHIP_PFSOC_GPIO1].base,
 +        memmap[MICROCHIP_PFSOC_GPIO1].size);
 +    create_unimplemented_device("microchip.pfsoc.gpio2",
 +        memmap[MICROCHIP_PFSOC_GPIO2].base,
 +        memmap[MICROCHIP_PFSOC_GPIO2].size);
 +
      /* eNVM */
      memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
                             memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
 --
-.28.0
+.47.1

-[PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
+[PULL 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
-From: Bin Meng <bin.meng@windriver.com>
+From: "Fea.Wang" <fea.wang@sifive.com>
-Microchip PolarFire SoC integrates 2 Candence GEMs to provide
+Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
-IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
+supported when the svukte extension is enabled.
-On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
+When senvcfg[UKTE] bit is set, the memory access from U-mode should do
-GEM1 connects to a PHY at address 9.
+the svukte check only except HLV/HLVX/HSV H-mode instructions which
 depend on hstatus[HUKTE].
-The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
+Signed-off-by: Fea.Wang <fea.wang@sifive.com>
-must specify 2 '-nic' options from the command line in order to get
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-a working ethernet.
+Reviewed-by: Jim Shu <jim.shu@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-ID: <20241203034932.25185-3-fea.wang@sifive.com>
 Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h |  7 ++++++
+ target/riscv/cpu_bits.h | 1 +
- hw/riscv/microchip_pfsoc.c         | 39 ++++++++++++++++++++++++++++++
+ target/riscv/csr.c      | 4 ++++
-files changed, 46 insertions(+)
+files changed, 5 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/cpu_bits.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
+ #define SENVCFG_CBIE                       MENVCFG_CBIE
- #include "hw/char/mchp_pfsoc_mmuart.h"
+ #define SENVCFG_CBCFE                      MENVCFG_CBCFE
- #include "hw/dma/sifive_pdma.h"
+ #define SENVCFG_CBZE                       MENVCFG_CBZE
-+#include "hw/net/cadence_gem.h"
++#define SENVCFG_UKTE                       BIT(8)
- #include "hw/sd/cadence_sdhci.h"
+ #define HENVCFG_FIOM                       MENVCFG_FIOM
- typedef struct MicrochipPFSoCState {
+ #define HENVCFG_LPE                        MENVCFG_LPE
-@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
      MchpPfSoCMMUartState *serial3;
      MchpPfSoCMMUartState *serial4;
      SiFivePDMAState dma;
 +    CadenceGEMState gem0;
 +    CadenceGEMState gem1;
      CadenceSDHCIState sdhci;
  } MicrochipPFSoCState;
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_MMUART2,
      MICROCHIP_PFSOC_MMUART3,
      MICROCHIP_PFSOC_MMUART4,
 +    MICROCHIP_PFSOC_GEM0,
 +    MICROCHIP_PFSOC_GEM1,
      MICROCHIP_PFSOC_ENVM_CFG,
      MICROCHIP_PFSOC_ENVM_DATA,
      MICROCHIP_PFSOC_IOSCB_CFG,
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_DMA_IRQ5 = 10,
      MICROCHIP_PFSOC_DMA_IRQ6 = 11,
      MICROCHIP_PFSOC_DMA_IRQ7 = 12,
 +    MICROCHIP_PFSOC_GEM0_IRQ = 64,
 +    MICROCHIP_PFSOC_GEM1_IRQ = 70,
      MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
      MICROCHIP_PFSOC_MMUART0_IRQ = 90,
      MICROCHIP_PFSOC_MMUART1_IRQ = 91,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
+--- a/target/riscv/csr.c
-+++ b/hw/riscv/microchip_pfsoc.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
-  * 3) MMUARTs (Multi-Mode UART)
+         mask |= SENVCFG_SSE;
-  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
+     }
-  * 5) SiFive Platform DMA (Direct Memory Access Controller)
-+ * 6) GEM (Gigabit Ethernet MAC Controller)
++    if (env_archcpu(env)->cfg.ext_svukte) {
-  *
++        mask |= SENVCFG_UKTE;
   * This board currently generates devicetree dynamically that indicates at least
   * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@
  #define BIOS_FILENAME   "hss.bin"
  #define RESET_VECTOR    0x20220000
 +/* GEM version */
 +#define GEM_REVISION    0x0107010c
 +
  static const struct MemmapEntry {
      hwaddr base;
      hwaddr size;
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
 +    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
 +    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
      [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
      [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
      object_initialize_child(obj, "dma-controller", &s->dma,
                              TYPE_SIFIVE_PDMA);
 +    object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
 +    object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
 +
      object_initialize_child(obj, "sd-controller", &s->sdhci,
                              TYPE_CADENCE_SDHCI);
  }
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      MemoryRegion *envm_data = g_new(MemoryRegion, 1);
      char *plic_hart_config;
      size_t plic_hart_config_len;
 +    NICInfo *nd;
      int i;
      sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
          qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
          serial_hd(4));
 +    /* GEMs */
 +
 +    nd = &nd_table[0];
 +    if (nd->used) {
 +        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 +        qdev_set_nic_properties(DEVICE(&s->gem0), nd);
 +    }
 +    nd = &nd_table[1];
 +    if (nd->used) {
 +        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 +        qdev_set_nic_properties(DEVICE(&s->gem1), nd);
 +    }
 +
-+    object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
+     env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
-+    object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
+     return RISCV_EXCP_NONE;
-+    sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
+ }
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
 +                    memmap[MICROCHIP_PFSOC_GEM0].base);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
 +        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
 +
 +    object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
 +    object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
 +                    memmap[MICROCHIP_PFSOC_GEM1].base);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
 +        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
 +
      /* eNVM */
      memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
                             memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
 --
-.28.0
+.47.1

-[PULL 04/30] hw/riscv: hart: Add a new 'resetvec' property
+[PULL 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
-From: Bin Meng <bin.meng@windriver.com>
+From: "Fea.Wang" <fea.wang@sifive.com>
-RISC-V machines do not instantiate RISC-V CPUs directly, instead
+Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
-they do that via the hart array. Add a new property for the reset
+value will be masked when the svukte extension is not enabled.
 vector address to allow the value to be passed to the CPU, before
 CPU is realized.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
 do svukte check.
 Signed-off-by: Fea.Wang <fea.wang@sifive.com>
 Reviewed-by: Frank Chang <frank.chang@sifive.com>
 Reviewed-by: Jim Shu <jim.shu@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-ID: <20241203034932.25185-4-fea.wang@sifive.com>
 Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/riscv_hart.h | 1 +
+ target/riscv/cpu_bits.h | 1 +
- hw/riscv/riscv_hart.c         | 3 +++
+ target/riscv/csr.c      | 3 +++
 files changed, 4 insertions(+)
-diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/riscv_hart.h
+--- a/target/riscv/cpu_bits.h
-+++ b/include/hw/riscv/riscv_hart.h
++++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@ typedef struct RISCVHartArrayState {
+@@ -XXX,XX +XXX,XX @@ typedef enum {
-     uint32_t num_harts;
+ #define HSTATUS_VTVM         0x00100000
-     uint32_t hartid_base;
+ #define HSTATUS_VTW          0x00200000
-     char *cpu_type;
+ #define HSTATUS_VTSR         0x00400000
-+    uint64_t resetvec;
++#define HSTATUS_HUKTE        0x01000000
-     RISCVCPU *harts;
+ #define HSTATUS_VSXL         0x300000000
- } RISCVHartArrayState;
+ #define HSTATUS32_WPRI       0xFF8FF87E
-diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/riscv_hart.c
+--- a/target/riscv/csr.c
-+++ b/hw/riscv/riscv_hart.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_harts_props[] = {
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
-     DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
+ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
-     DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
+                                     target_ulong val)
      DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
 +    DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
 +                       DEFAULT_RSTVEC),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
                                 char *cpu_type, Error **errp)
  {
-     object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
++    if (!env_archcpu(env)->cfg.ext_svukte) {
-+    qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
++        val = val & (~HSTATUS_HUKTE);
-     s->harts[idx].env.mhartid = s->hartid_base + idx;
++    }
-     qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
+     env->hstatus = val;
-     return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
+     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
          qemu_log_mask(LOG_UNIMP,
 --
-.28.0
+.47.1

-[PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation
+[PULL 32/39] target/riscv: Check memory access to meet svukte rule
-From: Bin Meng <bin.meng@windriver.com>
+From: "Fea.Wang" <fea.wang@sifive.com>
-Microchip PolarFire SoC integrates a DMA engine that supports:
+Follow the Svukte spec, do the memory access address checking
 * Independent concurrent DMA transfers using 4 DMA channels
 * Generation of interrupts on various conditions during execution
 which is actually an IP reused from the SiFive FU540 chip.
-This creates a model to support both polling and interrupt modes.
+. Include instruction fetches or explicit memory accesses
 . System run in effective privilege U or VU
 . Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
 instruction is HLV, HLVX, HSV and execute from U mode to VU mode
 . Depend on Sv39 and check virtual addresses bit[SXLEN-1]
 . Raises a page-fault exception corresponding to the original access
 type.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
 Signed-off-by: Fea.Wang <fea.wang@sifive.com>
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Jim Shu <jim.shu@sifive.com>
 Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-ID: <20241203034932.25185-5-fea.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/dma/sifive_pdma.h |  57 +++++++
+ target/riscv/cpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++++
- hw/dma/sifive_pdma.c         | 313 +++++++++++++++++++++++++++++++++++
+file changed, 55 insertions(+)
  hw/dma/Kconfig               |   3 +
  hw/dma/meson.build           |   1 +
 files changed, 374 insertions(+)
  create mode 100644 include/hw/dma/sifive_pdma.h
  create mode 100644 hw/dma/sifive_pdma.c
-diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/riscv/cpu_helper.c
---- /dev/null
++++ b/target/riscv/cpu_helper.c
-+++ b/include/hw/dma/sifive_pdma.h
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
-@@ -XXX,XX +XXX,XX @@
+     return TRANSLATE_SUCCESS;
-+/*
+ }
-+ * SiFive Platform DMA emulation
-+ *
++/* Returns 'true' if a svukte address check is needed */
-+ * Copyright (c) 2020 Wind River Systems, Inc.
++static bool do_svukte_check(CPURISCVState *env, bool first_stage,
-+ *
++                             int mode, bool virt)
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef SIFIVE_PDMA_H
 +#define SIFIVE_PDMA_H
 +
 +struct sifive_pdma_chan {
 +    uint32_t control;
 +    uint32_t next_config;
 +    uint64_t next_bytes;
 +    uint64_t next_dst;
 +    uint64_t next_src;
 +    uint32_t exec_config;
 +    uint64_t exec_bytes;
 +    uint64_t exec_dst;
 +    uint64_t exec_src;
 +    int state;
 +};
 +
 +#define SIFIVE_PDMA_CHANS           4
 +#define SIFIVE_PDMA_IRQS            (SIFIVE_PDMA_CHANS * 2)
 +#define SIFIVE_PDMA_REG_SIZE        0x100000
 +#define SIFIVE_PDMA_CHAN_NO(reg)    ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
 +
 +typedef struct SiFivePDMAState {
 +    SysBusDevice parent;
 +    MemoryRegion iomem;
 +    qemu_irq irq[SIFIVE_PDMA_IRQS];
 +
 +    struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
 +} SiFivePDMAState;
 +
 +#define TYPE_SIFIVE_PDMA    "sifive.pdma"
 +
 +#define SIFIVE_PDMA(obj)    \
 +    OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
 +
 +#endif /* SIFIVE_PDMA_H */
 diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/dma/sifive_pdma.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SiFive Platform DMA emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/log.h"
 +#include "qapi/error.h"
 +#include "hw/hw.h"
 +#include "hw/irq.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/sysbus.h"
 +#include "migration/vmstate.h"
 +#include "sysemu/dma.h"
 +#include "hw/dma/sifive_pdma.h"
 +
 +#define DMA_CONTROL         0x000
 +#define   CONTROL_CLAIM     BIT(0)
 +#define   CONTROL_RUN       BIT(1)
 +#define   CONTROL_DONE_IE   BIT(14)
 +#define   CONTROL_ERR_IE    BIT(15)
 +#define   CONTROL_DONE      BIT(30)
 +#define   CONTROL_ERR       BIT(31)
 +
 +#define DMA_NEXT_CONFIG     0x004
 +#define   CONFIG_REPEAT     BIT(2)
 +#define   CONFIG_ORDER      BIT(3)
 +#define   CONFIG_WRSZ_SHIFT 24
 +#define   CONFIG_RDSZ_SHIFT 28
 +#define   CONFIG_SZ_MASK    0xf
 +
 +#define DMA_NEXT_BYTES      0x008
 +#define DMA_NEXT_DST        0x010
 +#define DMA_NEXT_SRC        0x018
 +#define DMA_EXEC_CONFIG     0x104
 +#define DMA_EXEC_BYTES      0x108
 +#define DMA_EXEC_DST        0x110
 +#define DMA_EXEC_SRC        0x118
 +
 +enum dma_chan_state {
 +    DMA_CHAN_STATE_IDLE,
 +    DMA_CHAN_STATE_STARTED,
 +    DMA_CHAN_STATE_ERROR,
 +    DMA_CHAN_STATE_DONE
 +};
 +
 +static void sifive_pdma_run(SiFivePDMAState *s, int ch)
 +{
-+    uint64_t bytes = s->chan[ch].next_bytes;
++    /* Svukte extension depends on Sv39. */
-+    uint64_t dst = s->chan[ch].next_dst;
++    if (!(env_archcpu(env)->cfg.ext_svukte ||
-+    uint64_t src = s->chan[ch].next_src;
++        !first_stage ||
-+    uint32_t config = s->chan[ch].next_config;
++        VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
-+    int wsize, rsize, size;
++        return false;
 +    uint8_t buf[64];
 +    int n;
 +
 +    /* do nothing if bytes to transfer is zero */
 +    if (!bytes) {
 +        goto error;
 +    }
 +
 +    /*
-+     * The manual does not describe how the hardware behaviors when
++     * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
-+     * config.wsize and config.rsize are given different values.
++     * executing HLV/HLVX/HSV in U-mode.
-+     * A common case is memory to memory DMA, and in this case they
++     * For other cases, check senvcfg.UKTE.
 +     * are normally the same. Abort if this expectation fails.
 +     */
-+    wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
++    if (env->priv == PRV_U && !env->virt_enabled && virt) {
-+    rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
++        if (!get_field(env->hstatus, HSTATUS_HUKTE)) {
-+    if (wsize != rsize) {
++            return false;
-+        goto error;
++        }
 +    } else if (!get_field(env->senvcfg, SENVCFG_UKTE)) {
 +        return false;
 +    }
 +
 +    /*
-+     * Calculate the transaction size
++     * Svukte extension is qualified only in U or VU-mode.
 +     *
-+     * size field is base 2 logarithm of DMA transaction size,
++     * Effective mode can be switched to U or VU-mode by:
-+     * but there is an upper limit of 64 bytes per transaction.
++     *   - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
 +     *   - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
 +     *   - U-mode.
 +     *   - VU-mode.
 +     *   - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
 +     */
-+    size = wsize;
++    if (mode != PRV_U) {
-+    if (size > 6) {
++        return false;
 +        size = 6;
 +    }
 +    size = 1 << size;
 +
 +    /* the bytes to transfer should be multiple of transaction size */
 +    if (bytes % size) {
 +        goto error;
 +    }
 +
-+    /* indicate a DMA transfer is started */
++    return true;
-+    s->chan[ch].state = DMA_CHAN_STATE_STARTED;
++}
 +    s->chan[ch].control &= ~CONTROL_DONE;
 +    s->chan[ch].control &= ~CONTROL_ERR;
 +
-+    /* load the next_ registers into their exec_ counterparts */
++static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
-+    s->chan[ch].exec_config = config;
++{
-+    s->chan[ch].exec_bytes = bytes;
++    /* svukte extension excludes RV32 */
-+    s->chan[ch].exec_dst = dst;
++    uint32_t sxlen = 32 * riscv_cpu_sxl(env);
-+    s->chan[ch].exec_src = src;
++    uint64_t high_bit = addr & (1UL << (sxlen - 1));
 +    return !high_bit;
 +}
 +
-+    for (n = 0; n < bytes / size; n++) {
+ /*
-+        cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);
+  * get_physical_address - get the physical address for this virtual address
-+        cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);
+  *
-+        s->chan[ch].exec_src += size;
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-+        s->chan[ch].exec_dst += size;
+     MemTxResult res;
-+        s->chan[ch].exec_bytes -= size;
+     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
      int mode = mmuidx_priv(mmu_idx);
 +    bool virt = mmuidx_2stage(mmu_idx);
      bool use_background = false;
      hwaddr ppn;
      int napot_bits = 0;
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE);
      bool sstack_page = false;
 +    if (do_svukte_check(env, first_stage, mode, virt) &&
 +        !check_svukte_addr(env, addr)) {
 +        return TRANSLATE_FAIL;
 +    }
 +
-+    /* indicate a DMA transfer is done */
+     /*
-+    s->chan[ch].state = DMA_CHAN_STATE_DONE;
+      * Check if we should use the background registers for the two
-+    s->chan[ch].control &= ~CONTROL_RUN;
+      * stage translation. We don't need to check if we actually need
 +    s->chan[ch].control |= CONTROL_DONE;
 +
 +    /* reload exec_ registers if repeat is required */
 +    if (s->chan[ch].next_config & CONFIG_REPEAT) {
 +        s->chan[ch].exec_bytes = bytes;
 +        s->chan[ch].exec_dst = dst;
 +        s->chan[ch].exec_src = src;
 +    }
 +
 +    return;
 +
 +error:
 +    s->chan[ch].state = DMA_CHAN_STATE_ERROR;
 +    s->chan[ch].control |= CONTROL_ERR;
 +    return;
 +}
 +
 +static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
 +{
 +    bool done_ie, err_ie;
 +
 +    done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);
 +    err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);
 +
 +    if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {
 +        qemu_irq_raise(s->irq[ch * 2]);
 +    } else {
 +        qemu_irq_lower(s->irq[ch * 2]);
 +    }
 +
 +    if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {
 +        qemu_irq_raise(s->irq[ch * 2 + 1]);
 +    } else {
 +        qemu_irq_lower(s->irq[ch * 2 + 1]);
 +    }
 +
 +    s->chan[ch].state = DMA_CHAN_STATE_IDLE;
 +}
 +
 +static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    SiFivePDMAState *s = opaque;
 +    int ch = SIFIVE_PDMA_CHAN_NO(offset);
 +    uint64_t val = 0;
 +
 +    if (ch >= SIFIVE_PDMA_CHANS) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
 +                      __func__, ch);
 +        return 0;
 +    }
 +
 +    offset &= 0xfff;
 +    switch (offset) {
 +    case DMA_CONTROL:
 +        val = s->chan[ch].control;
 +        break;
 +    case DMA_NEXT_CONFIG:
 +        val = s->chan[ch].next_config;
 +        break;
 +    case DMA_NEXT_BYTES:
 +        val = s->chan[ch].next_bytes;
 +        break;
 +    case DMA_NEXT_DST:
 +        val = s->chan[ch].next_dst;
 +        break;
 +    case DMA_NEXT_SRC:
 +        val = s->chan[ch].next_src;
 +        break;
 +    case DMA_EXEC_CONFIG:
 +        val = s->chan[ch].exec_config;
 +        break;
 +    case DMA_EXEC_BYTES:
 +        val = s->chan[ch].exec_bytes;
 +        break;
 +    case DMA_EXEC_DST:
 +        val = s->chan[ch].exec_dst;
 +        break;
 +    case DMA_EXEC_SRC:
 +        val = s->chan[ch].exec_src;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static void sifive_pdma_write(void *opaque, hwaddr offset,
 +                              uint64_t value, unsigned size)
 +{
 +    SiFivePDMAState *s = opaque;
 +    int ch = SIFIVE_PDMA_CHAN_NO(offset);
 +
 +    if (ch >= SIFIVE_PDMA_CHANS) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
 +                      __func__, ch);
 +        return;
 +    }
 +
 +    offset &= 0xfff;
 +    switch (offset) {
 +    case DMA_CONTROL:
 +        s->chan[ch].control = value;
 +
 +        if (value & CONTROL_RUN) {
 +            sifive_pdma_run(s, ch);
 +        }
 +
 +        sifive_pdma_update_irq(s, ch);
 +        break;
 +    case DMA_NEXT_CONFIG:
 +        s->chan[ch].next_config = value;
 +        break;
 +    case DMA_NEXT_BYTES:
 +        s->chan[ch].next_bytes = value;
 +        break;
 +    case DMA_NEXT_DST:
 +        s->chan[ch].next_dst = value;
 +        break;
 +    case DMA_NEXT_SRC:
 +        s->chan[ch].next_src = value;
 +        break;
 +    case DMA_EXEC_CONFIG:
 +    case DMA_EXEC_BYTES:
 +    case DMA_EXEC_DST:
 +    case DMA_EXEC_SRC:
 +        /* these are read-only registers */
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps sifive_pdma_ops = {
 +    .read = sifive_pdma_read,
 +    .write = sifive_pdma_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    /* there are 32-bit and 64-bit wide registers */
 +    .impl = {
 +        .min_access_size = 4,
 +        .max_access_size = 8,
 +    }
 +};
 +
 +static void sifive_pdma_realize(DeviceState *dev, Error **errp)
 +{
 +    SiFivePDMAState *s = SIFIVE_PDMA(dev);
 +    int i;
 +
 +    memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,
 +                          TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 +
 +    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
 +        sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
 +    }
 +}
 +
 +static void sifive_pdma_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "SiFive Platform DMA controller";
 +    dc->realize = sifive_pdma_realize;
 +}
 +
 +static const TypeInfo sifive_pdma_info = {
 +    .name          = TYPE_SIFIVE_PDMA,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(SiFivePDMAState),
 +    .class_init    = sifive_pdma_class_init,
 +};
 +
 +static void sifive_pdma_register_types(void)
 +{
 +    type_register_static(&sifive_pdma_info);
 +}
 +
 +type_init(sifive_pdma_register_types)
 diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/dma/Kconfig
 +++ b/hw/dma/Kconfig
@@ -XXX,XX +XXX,XX @@ config ZYNQ_DEVCFG
  config STP2000
      bool
 +
 +config SIFIVE_PDMA
 +    bool
 diff --git a/hw/dma/meson.build b/hw/dma/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/dma/meson.build
 +++ b/hw/dma/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
  softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c'))
 --
-.28.0
+.47.1

-[PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property
+[PULL 33/39] target/riscv: Expose svukte ISA extension
-From: Bin Meng <bin.meng@windriver.com>
+From: "Fea.Wang" <fea.wang@sifive.com>
-Currently the reset vector address is hard-coded in a RISC-V CPU's
+Add "svukte" in the ISA string when svukte extension is enabled.
 instance_init() routine. In a real world we can have 2 exact same
 CPUs except for the reset vector address, which is pretty common in
 the RISC-V core IP licensing business.
-Normally reset vector address is a configurable parameter. Let's
+Signed-off-by: Fea.Wang <fea.wang@sifive.com>
-create a 64-bit property to store the reset vector address which
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
-covers both 32-bit and 64-bit CPUs.
+Reviewed-by: Jim Shu <jim.shu@sifive.com>
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-ID: <20241203034932.25185-6-fea.wang@sifive.com>
 Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h | 1 +
+ target/riscv/cpu.c | 2 ++
- target/riscv/cpu.c | 1 +
+file changed, 2 insertions(+)
 files changed, 2 insertions(+)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
-+++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPU {
-         uint16_t elen;
-         bool mmu;
-         bool pmp;
-+        uint64_t resetvec;
-     } cfg;
- } RISCVCPU;
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
-     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+     ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
-     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+     ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
-     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+     ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
-+    DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
++    ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
      ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
      ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
      ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
  /* These are experimental so mark with 'x-' */
  const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
 +    MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
      DEFINE_PROP_END_OF_LIST(),
  };
 --
-.28.0
+.47.1

-[PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
+[PULL 34/39] target/riscv: Check svukte is not enabled in RV32
-From: Bin Meng <bin.meng@windriver.com>
+From: "Fea.Wang" <fea.wang@sifive.com>
-When cadence_gem model was created for Xilinx boards, the PHY address
+The spec explicitly says svukte doesn't support RV32. So check that it
-was hard-coded to 23 in the GEM model. Now that we have introduced a
+is not enabled in RV32.
 property we can use that to tell GEM model what our PHY address is.
 Change all boards' GEM 'phy-addr' property value to 23, and set the
 PHY address default value to 0 in the GEM model.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Fea.Wang <fea.wang@sifive.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241203034932.25185-7-fea.wang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/arm/xilinx_zynq.c | 1 +
+ target/riscv/tcg/tcg-cpu.c | 5 +++++
- hw/arm/xlnx-versal.c | 1 +
+file changed, 5 insertions(+)
  hw/arm/xlnx-zynqmp.c | 2 ++
  hw/net/cadence_gem.c | 6 +++---
 files changed, 7 insertions(+), 3 deletions(-)
-diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xilinx_zynq.c
+--- a/target/riscv/tcg/tcg-cpu.c
-+++ b/hw/arm/xilinx_zynq.c
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+         return;
          qdev_set_nic_properties(dev, nd);
      }
-+    object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
-     s = SYS_BUS_DEVICE(dev);
++    if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
-     sysbus_realize_and_unref(s, &error_fatal);
++        error_setg(errp, "svukte is not supported for RV32");
-     sysbus_mmio_map(s, 0, base);
++        return;
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
++    }
-index XXXXXXX..XXXXXXX 100644
++
---- a/hw/arm/xlnx-versal.c
+     /*
-+++ b/hw/arm/xlnx-versal.c
+      * Disable isa extensions based on priv spec after we
-@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
+      * validated and set everything we need.
              qemu_check_nic_model(nd, "cadence_gem");
              qdev_set_nic_properties(dev, nd);
          }
 +        object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
          object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
                                  &error_abort);
          object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
 diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-zynqmp.c
 +++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
          }
          object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
                                  &error_abort);
 +        object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
 +                                &error_abort);
          object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
                                  &error_abort);
          if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
 diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/cadence_gem.c
 +++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@
  #define GEM_PHYMNTNC_REG_SHIFT 18
  /* Marvell PHY definitions */
 -#define BOARD_PHY_ADDRESS    23 /* PHY address we will emulate a device at */
 +#define BOARD_PHY_ADDRESS    0 /* PHY address we will emulate a device at */
  #define PHY_REG_CONTROL      0
  #define PHY_REG_STATUS       1
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
              uint32_t phy_addr, reg_num;
              phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
 -            if (phy_addr == s->phy_addr || phy_addr == 0) {
 +            if (phy_addr == s->phy_addr) {
                  reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                  retval &= 0xFFFF0000;
                  retval |= gem_phy_read(s, reg_num);
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
              uint32_t phy_addr, reg_num;
              phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
 -            if (phy_addr == s->phy_addr || phy_addr == 0) {
 +            if (phy_addr == s->phy_addr) {
                  reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                  gem_phy_write(s, reg_num, val);
              }
 --
-.28.0
+.47.1

-[PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property
+[PULL 35/39] target/riscv: Include missing headers in 'vector_internals.h'
-From: Bin Meng <bin.meng@windriver.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-At present the PHY address of the PHY connected to GEM is hard-coded
+Rather than relying on implicit includes, explicit them,
-to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
+in order to avoid when refactoring unrelated headers:
 all boards. Add a new 'phy-addr' property so that board can specify
 the PHY address for each GEM instance.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+  target/riscv/vector_internals.h:36:12: error: call to undeclared function 'FIELD_EX32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+|     return FIELD_EX32(simd_data(desc), VDATA, NF);
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+        |            ^
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20241203200828.47311-2-philmd@linaro.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/net/cadence_gem.h | 2 ++
+ target/riscv/vector_internals.h | 1 +
- hw/net/cadence_gem.c         | 5 +++--
+file changed, 1 insertion(+)
 files changed, 5 insertions(+), 2 deletions(-)
-diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
+diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/net/cadence_gem.h
+--- a/target/riscv/vector_internals.h
-+++ b/include/hw/net/cadence_gem.h
++++ b/target/riscv/vector_internals.h
-@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
+@@ -XXX,XX +XXX,XX @@
-     /* Mask of register bits which are write 1 to clear */
+ #define TARGET_RISCV_VECTOR_INTERNALS_H
-     uint32_t regs_w1c[CADENCE_GEM_MAXREG];
+ #include "qemu/bitops.h"
-+    /* PHY address */
++#include "hw/registerfields.h"
-+    uint8_t phy_addr;
+ #include "cpu.h"
-     /* PHY registers backing store */
+ #include "tcg/tcg-gvec-desc.h"
-     uint16_t phy_regs[32];
+ #include "internals.h"
 diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/net/cadence_gem.c
 +++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
              uint32_t phy_addr, reg_num;
              phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
 -            if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
 +            if (phy_addr == s->phy_addr || phy_addr == 0) {
                  reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                  retval &= 0xFFFF0000;
                  retval |= gem_phy_read(s, reg_num);
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
              uint32_t phy_addr, reg_num;
              phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
 -            if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
 +            if (phy_addr == s->phy_addr || phy_addr == 0) {
                  reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                  gem_phy_write(s, reg_num, val);
              }
@@ -XXX,XX +XXX,XX @@ static Property gem_properties[] = {
      DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
      DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
                         GEM_MODID_VALUE),
 +    DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
      DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
                        num_priority_queues, 1),
      DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
 --
-.28.0
+.47.1

-[PULL 26/30] hw/riscv: Move sifive_uart model to hw/char
+[PULL 36/39] target/riscv: Include missing headers in 'internals.h'
-From: Bin Meng <bin.meng@windriver.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Rather than relying on implicit includes, explicit them,
-should only contain the RISC-V SoC / machine codes plus generic
+in order to avoid when refactoring unrelated headers:
 codes. Let's move sifive_uart model to hw/char directory.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+  target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S'
 |         ret = PRV_S;
         |               ^
   target/riscv/internals.h:93:9: error: call to undeclared function 'env_archcpu'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
 |     if (env_archcpu(env)->cfg.ext_zfinx) {
         |         ^
   target/riscv/internals.h:101:15: error: unknown type name 'float32'; did you mean 'float'?
 | static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
         |               ^~~~~~~
         |               float
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Message-ID: <20241203200828.47311-3-philmd@linaro.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => char}/sifive_uart.h | 0
+ target/riscv/internals.h | 3 +++
- hw/{riscv => char}/sifive_uart.c         | 2 +-
+file changed, 3 insertions(+)
  hw/riscv/sifive_e.c                      | 2 +-
  hw/riscv/sifive_u.c                      | 2 +-
  hw/char/Kconfig                          | 3 +++
  hw/char/meson.build                      | 1 +
  hw/riscv/Kconfig                         | 2 ++
  hw/riscv/meson.build                     | 1 -
 files changed, 9 insertions(+), 4 deletions(-)
  rename include/hw/{riscv => char}/sifive_uart.h (100%)
  rename hw/{riscv => char}/sifive_uart.c (99%)
-diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
+diff --git a/target/riscv/internals.h b/target/riscv/internals.h
 similarity index 100%
 rename from include/hw/riscv/sifive_uart.h
 rename to include/hw/char/sifive_uart.h
 diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
 similarity index 99%
 rename from hw/riscv/sifive_uart.c
 rename to hw/char/sifive_uart.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_uart.c
+--- a/target/riscv/internals.h
-+++ b/hw/char/sifive_uart.c
++++ b/target/riscv/internals.h
 @@ -XXX,XX +XXX,XX @@
- #include "chardev/char-fe.h"
+ #ifndef RISCV_CPU_INTERNALS_H
- #include "hw/hw.h"
+ #define RISCV_CPU_INTERNALS_H
- #include "hw/irq.h"
--#include "hw/riscv/sifive_uart.h"
++#include "exec/cpu-common.h"
-+#include "hw/char/sifive_uart.h"
+ #include "hw/registerfields.h"
 +#include "fpu/softfloat-types.h"
 +#include "target/riscv/cpu_bits.h"
  /*
-  * Not yet implemented:
+  * The current MMU Modes are:
 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_e.c
 +++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/unimp.h"
  #include "target/riscv/cpu.h"
  #include "hw/riscv/riscv_hart.h"
 -#include "hw/riscv/sifive_uart.h"
  #include "hw/riscv/sifive_e.h"
  #include "hw/riscv/boot.h"
 +#include "hw/char/sifive_uart.h"
  #include "hw/intc/sifive_clint.h"
  #include "hw/intc/sifive_plic.h"
  #include "hw/misc/sifive_e_prci.h"
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/unimp.h"
  #include "target/riscv/cpu.h"
  #include "hw/riscv/riscv_hart.h"
 -#include "hw/riscv/sifive_uart.h"
  #include "hw/riscv/sifive_u.h"
  #include "hw/riscv/boot.h"
 +#include "hw/char/sifive_uart.h"
  #include "hw/intc/sifive_clint.h"
  #include "hw/intc/sifive_plic.h"
  #include "chardev/char.h"
 diff --git a/hw/char/Kconfig b/hw/char/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/Kconfig
 +++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_USART
  config MCHP_PFSOC_MMUART
      bool
 +
 +config SIFIVE_UART
 +    bool
 diff --git a/hw/char/meson.build b/hw/char/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/meson.build
 +++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
  softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
  softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
      select SIFIVE_CLINT
      select SIFIVE_GPIO
      select SIFIVE_PLIC
 +    select SIFIVE_UART
      select SIFIVE_E_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_PLIC
 +    select SIFIVE_UART
      select SIFIVE_U_OTP
      select SIFIVE_U_PRCI
      select UNIMP
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 --
-.28.0
+.47.1

-[PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
+[PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Microchip PolarFire SoC integrates one Cadence SDHCI controller.
+Commit 68c9e54bea handled a situation where a warning was being shown
-On the Icicle Kit board, one eMMC chip and an external SD card
+when using the 'sifive_e' cpu when disabling the named extension zic64b.
-connect to this controller depending on different configuration.
+It makes little sense to show user warnings for named extensions that
 users can't control, and the solution taken was to disable zic64b
 manually in riscv_cpu_update_named_features().
-As QEMU does not support eMMC yet, we just emulate the SD card
+This solution won't scale well when adding more named features, and can
-configuration. To test this, the Hart Software Services (HSS)
+eventually end up repeating riscv_cpu_disable_priv_spec_isa_exts().
 should choose the SD card configuration:
-$ cp boards/icicle-kit-es/def_config.sdcard .config
+Change riscv_cpu_disable_priv_spec_isa_exts() to not show warnings when
-$ make BOARD=icicle-kit-es
+disabling a named feature. This will accomplish the same thing we're
 doing today while avoiding having two points where we're disabling
 exts via priv_ver mismatch.
-The SD card image can be built from the Yocto BSP at:
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp
 Note the generated SD card image should be resized before use:
 $ qemu-img resize /path/to/sdcard.img 4G
 Launch QEMU with the following command:
 $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
+Message-ID: <20241113171755.978109-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h |  4 ++++
+ target/riscv/tcg/tcg-cpu.c | 13 ++++++++++---
- hw/riscv/microchip_pfsoc.c         | 23 +++++++++++++++++++++++
+file changed, 10 insertions(+), 3 deletions(-)
  hw/riscv/Kconfig                   |  1 +
 files changed, 28 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/tcg/tcg-cpu.c
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
- #define HW_MICROCHIP_PFSOC_H
+             }
- #include "hw/char/mchp_pfsoc_mmuart.h"
+             isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
 +#include "hw/sd/cadence_sdhci.h"
  typedef struct MicrochipPFSoCState {
      /*< private >*/
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
      MchpPfSoCMMUartState *serial2;
      MchpPfSoCMMUartState *serial3;
      MchpPfSoCMMUartState *serial4;
 +    CadenceSDHCIState sdhci;
  } MicrochipPFSoCState;
  #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_MMUART0,
      MICROCHIP_PFSOC_SYSREG,
      MICROCHIP_PFSOC_MPUCFG,
 +    MICROCHIP_PFSOC_EMMC_SD,
      MICROCHIP_PFSOC_MMUART1,
      MICROCHIP_PFSOC_MMUART2,
      MICROCHIP_PFSOC_MMUART3,
@@ -XXX,XX +XXX,XX @@ enum {
  };
  enum {
 +    MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
      MICROCHIP_PFSOC_MMUART0_IRQ = 90,
      MICROCHIP_PFSOC_MMUART1_IRQ = 91,
      MICROCHIP_PFSOC_MMUART2_IRQ = 92,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
   * 1) PLIC (Platform Level Interrupt Controller)
   * 2) eNVM (Embedded Non-Volatile Memory)
   * 3) MMUARTs (Multi-Mode UART)
 + * 4) Cadence eMMC/SDHC controller and an SD card connected to it
   *
   * This board currently generates devicetree dynamically that indicates at least
   * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
      [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
      [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
 +    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
      qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
                           TYPE_RISCV_CPU_SIFIVE_U54);
      qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
 +
-+    object_initialize_child(obj, "sd-controller", &s->sdhci,
++            /*
-+                            TYPE_CADENCE_SDHCI);
++             * Do not show user warnings for named features that users
 +             * can't enable/disable in the command line. See commit
 +             * 68c9e54bea for more info.
 +             */
 +            if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) {
 +                continue;
 +            }
  #ifndef CONFIG_USER_ONLY
              warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
                          " because privilege spec version does not match",
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
          cpu->cfg.has_priv_1_13 = true;
      }
 -    /* zic64b is 1.12 or later */
      cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
                            cpu->cfg.cbop_blocksize == 64 &&
 -                          cpu->cfg.cboz_blocksize == 64 &&
 -                          cpu->cfg.has_priv_1_12;
 +                          cpu->cfg.cboz_blocksize == 64;
  }
- static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+ static void riscv_cpu_validate_g(RISCVCPU *cpu)
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
          memmap[MICROCHIP_PFSOC_MPUCFG].base,
          memmap[MICROCHIP_PFSOC_MPUCFG].size);
 +    /* SDHCI */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
 +                    memmap[MICROCHIP_PFSOC_EMMC_SD].base);
 +    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
 +        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
 +
      /* MMUARTs */
      s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
          memmap[MICROCHIP_PFSOC_MMUART0].base,
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
      MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
      MemoryRegion *system_memory = get_system_memory();
      MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 +    DriveInfo *dinfo = drive_get_next(IF_SD);
      /* Sanity check on RAM size */
      if (machine->ram_size < mc->default_ram_size) {
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
      /* Load the firmware */
      riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
 +
 +    /* Attach an SD card */
 +    if (dinfo) {
 +        CadenceSDHCIState *sdhci = &(s->soc.sdhci);
 +        DeviceState *card = qdev_new(TYPE_SD_CARD);
 +
 +        qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 +                                &error_fatal);
 +        qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
 +    }
  }
  static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
      select SIFIVE
      select UNIMP
      select MCHP_PFSOC_MMUART
 +    select CADENCE_SDHCI
 --
-.28.0
+.47.1

-[PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value
+[PULL 38/39] target/riscv: add ssstateen
-From: Bin Meng <bin.meng@windriver.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Now that we have the newly introduced 'resetvec' property in the
+ssstateen is defined in RVA22 as:
 RISC-V CPU and HART, instead of hard-coding the reset vector addr
 in the CPU's instance_init(), move that to riscv_cpu_realize()
 based on the configured property value from the RISC-V machines.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+"Supervisor-mode view of the state-enable extension. The supervisor-mode
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+(sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+must be provided."
-Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
 Add ssstateen as a named feature that is available if we also have
 smstateen.
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
 Message-ID: <20241113171755.978109-3-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/opentitan.c | 1 +
+ target/riscv/cpu_cfg.h     | 1 +
- hw/riscv/sifive_e.c  | 1 +
+ target/riscv/cpu.c         | 2 ++
- hw/riscv/sifive_u.c  | 2 ++
+ target/riscv/tcg/tcg-cpu.c | 9 ++++++++-
- target/riscv/cpu.c   | 7 ++-----
+files changed, 11 insertions(+), 1 deletion(-)
 files changed, 6 insertions(+), 5 deletions(-)
-diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/opentitan.c
+--- a/target/riscv/cpu_cfg.h
-+++ b/hw/riscv/opentitan.c
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
-                             &error_abort);
+     /* Named features  */
-     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
+     bool ext_svade;
-                             &error_abort);
+     bool ext_zic64b;
-+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
++    bool ext_ssstateen;
-     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+     /*
-     /* Boot ROM */
+      * Always 'true' booleans for named features
 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_e.c
 +++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_init(Object *obj)
      object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
      object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                              &error_abort);
 +    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
      object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
                              TYPE_SIFIVE_GPIO);
  }
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
      qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
      qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
      qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
 +    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
      object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
      qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
      qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
      qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
      qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
 +    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
      object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
      object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
-     CPURISCVState *env = &RISCV_CPU(obj)->env;
+     ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
-     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+     ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
-     set_priv_version(env, PRIV_VERSION_1_11_0);
+     ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
--    set_resetvec(env, DEFAULT_RSTVEC);
++    ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
      ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
      ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
      ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
   */
  const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
      MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
 +    MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
      DEFINE_PROP_END_OF_LIST(),
  };
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.c
 +++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
        * All other named features are already enabled
        * in riscv_tcg_cpu_instance_init().
        */
 -    if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) {
 +    switch (feat_offset) {
 +    case CPU_CFG_OFFSET(ext_zic64b):
          cpu->cfg.cbom_blocksize = 64;
          cpu->cfg.cbop_blocksize = 64;
          cpu->cfg.cboz_blocksize = 64;
 +        break;
 +    case CPU_CFG_OFFSET(ext_ssstateen):
 +        cpu->cfg.ext_smstateen = true;
 +        break;
      }
  }
- static void riscv_base_cpu_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
-@@ -XXX,XX +XXX,XX @@ static void riscv_base_cpu_init(Object *obj)
+     cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
-     CPURISCVState *env = &RISCV_CPU(obj)->env;
+                           cpu->cfg.cbop_blocksize == 64 &&
-     /* We set this in the realise function */
+                           cpu->cfg.cboz_blocksize == 64;
-     set_misa(env, 0);
++
--    set_resetvec(env, DEFAULT_RSTVEC);
++    cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen;
  }
- static void rvxx_sifive_u_cpu_init(Object *obj)
+ static void riscv_cpu_validate_g(RISCVCPU *cpu)
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_u_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    set_resetvec(env, 0x1004);
  }
  static void rvxx_sifive_e_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_e_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    set_resetvec(env, 0x1004);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      set_misa(env, RV32 | RVI | RVM | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    set_resetvec(env, 0x8090);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
  }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
          set_feature(env, RISCV_FEATURE_PMP);
      }
 +    set_resetvec(env, cpu->cfg.resetvec);
 +
      /* If misa isn't set (rv32 and rv64 machines) set it here */
      if (!env->misa) {
          /* Do some ISA extension error checking */
 --
-.28.0
+.47.1

-[PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
+[PULL 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU
-From: Yifei Jiang <jiangyifei@huawei.com>
+From: MollyChen <xiaoou@iscas.ac.cn>
-When the cause number is equal to or greater than 23, print "(unknown)" in
+Add a CPU entry for the RV64 XiangShan NANHU CPU which
-trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
+supports single-core and dual-core configurations. More
-excpetion "guest_store_page_fault" can not be printed.
+details can be found at
 https://docs.xiangshan.cc/zh-cn/latest/integration/overview
-In addition, the current check of cause is invalid for riscv_intr_names. So
+Signed-off-by: MollyChen <xiaoou@iscas.ac.cn>
-introduce riscv_cpu_get_trap_name to get the trap cause name.
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
+Message-ID: <20241205073622.46052-1-xiaoou@iscas.ac.cn>
-Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
+[ Changes by AF
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+ - Fixup code formatting
-Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
+]
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  1 +
+ target/riscv/cpu-qom.h |  1 +
- target/riscv/cpu.c        | 11 +++++++++++
+ target/riscv/cpu.c     | 30 ++++++++++++++++++++++++++++++
- target/riscv/cpu_helper.c |  4 ++--
+files changed, 31 insertions(+)
 files changed, 14 insertions(+), 2 deletions(-)
-diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu.h
+--- a/target/riscv/cpu-qom.h
-+++ b/target/riscv/cpu.h
++++ b/target/riscv/cpu-qom.h
-@@ -XXX,XX +XXX,XX @@ extern const char * const riscv_fpr_regnames[];
+@@ -XXX,XX +XXX,XX @@
- extern const char * const riscv_excp_names[];
+ #define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
- extern const char * const riscv_intr_names[];
+ #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
+ #define TYPE_RISCV_CPU_TT_ASCALON       RISCV_CPU_TYPE_NAME("tt-ascalon")
-+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
++#define TYPE_RISCV_CPU_XIANGSHAN_NANHU  RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
- void riscv_cpu_do_interrupt(CPUState *cpu);
+ #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
- int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
- int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
+@@ -XXX,XX +XXX,XX @@ static void rv64_tt_ascalon_cpu_init(Object *obj)
-     "reserved"
+ #endif
- };
+ }
-+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
++static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
 +{
-+    if (async) {
++    CPURISCVState *env = &RISCV_CPU(obj)->env;
-+        return (cause < ARRAY_SIZE(riscv_intr_names)) ?
++    RISCVCPU *cpu = RISCV_CPU(obj);
-+               riscv_intr_names[cause] : "(unknown)";
++
-+    } else {
++    riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU);
-+        return (cause < ARRAY_SIZE(riscv_excp_names)) ?
++    env->priv_ver = PRIV_VERSION_1_12_0;
-+               riscv_excp_names[cause] : "(unknown)";
++
-+    }
++    /* Enable ISA extensions */
 +    cpu->cfg.ext_zbc = true;
 +    cpu->cfg.ext_zbkb = true;
 +    cpu->cfg.ext_zbkc = true;
 +    cpu->cfg.ext_zbkx = true;
 +    cpu->cfg.ext_zknd = true;
 +    cpu->cfg.ext_zkne = true;
 +    cpu->cfg.ext_zknh = true;
 +    cpu->cfg.ext_zksed = true;
 +    cpu->cfg.ext_zksh = true;
 +    cpu->cfg.ext_svinval = true;
 +
 +    cpu->cfg.mmu = true;
 +    cpu->cfg.pmp = true;
 +
 +#ifndef CONFIG_USER_ONLY
 +    set_satp_mode_max_supported(cpu, VM_1_10_SV39);
 +#endif
 +}
 +
- static void set_misa(CPURISCVState *env, target_ulong misa)
+ #ifdef CONFIG_TCG
  static void rv128_base_cpu_init(Object *obj)
  {
-     env->misa_mask = env->misa = misa;
+@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,  rv64_thead_c906_cpu_init),
-index XXXXXXX..XXXXXXX 100644
+     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64,  rv64_tt_ascalon_cpu_init),
---- a/target/riscv/cpu_helper.c
+     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1,  MXL_RV64,  rv64_veyron_v1_cpu_init),
-+++ b/target/riscv/cpu_helper.c
++    DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
++                                                 MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
-         }
+ #ifdef CONFIG_TCG
-     }
+     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,   MXL_RV128, rv128_base_cpu_init),
+ #endif /* CONFIG_TCG */
 -    trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
 -        (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
 +    trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
 +        riscv_cpu_get_trap_name(cause, async));
      if (env->priv <= PRV_S &&
              cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
 --
-.28.0
+.47.1

The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:

Merge remote-tracking branch 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging (2020-09-08 21:21:13 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910

for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:

hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19 -0700)

----------------------------------------------------------------
This PR includes multiple fixes and features for RISC-V:
 - Fixes a bug in printing trap causes
 - Allows 16-bit writes to the SiFive test device. This fixes the
   failure to reboot the RISC-V virt machine
 - Support for the Microchip PolarFire SoC and Icicle Kit
 - A reafactor of RISC-V code out of hw/riscv

----------------------------------------------------------------
Bin Meng (28):
      target/riscv: cpu: Add a new 'resetvec' property
      hw/riscv: hart: Add a new 'resetvec' property
      target/riscv: cpu: Set reset vector based on the configured property value
      hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
      hw/char: Add Microchip PolarFire SoC MMUART emulation
      hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
      hw/sd: Add Cadence SDHCI emulation
      hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
      hw/dma: Add SiFive platform DMA controller emulation
      hw/riscv: microchip_pfsoc: Connect a DMA controller
      hw/net: cadence_gem: Add a new 'phy-addr' property
      hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
      hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
      hw/riscv: microchip_pfsoc: Hook GPIO controllers
      hw/riscv: clint: Avoid using hard-coded timebase frequency
      hw/riscv: sifive_u: Connect a DMA controller
      hw/riscv: Move sifive_e_prci model to hw/misc
      hw/riscv: Move sifive_u_prci model to hw/misc
      hw/riscv: Move sifive_u_otp model to hw/misc
      hw/riscv: Move sifive_gpio model to hw/gpio
      hw/riscv: Move sifive_clint model to hw/intc
      hw/riscv: Move sifive_plic model to hw/intc
      hw/riscv: Move riscv_htif model to hw/char
      hw/riscv: Move sifive_uart model to hw/char
      hw/riscv: Move sifive_test model to hw/misc
      hw/riscv: Always build riscv_hart.c
      hw/riscv: Drop CONFIG_SIFIVE
      hw/riscv: Sort the Kconfig options in alphabetical order

Nathan Chancellor (1):
      riscv: sifive_test: Allow 16-bit writes to memory region

Yifei Jiang (1):
      target/riscv: Fix bug in getting trap cause name for trace_riscv_trap

default-configs/riscv64-softmmu.mak         |   1 +
 {include/hw/riscv => hw/intc}/sifive_plic.h |   0
 hw/riscv/trace.h                            |   1 -
 include/hw/char/mchp_pfsoc_mmuart.h         |  61 ++++
 include/hw/{riscv => char}/riscv_htif.h     |   0
 include/hw/{riscv => char}/sifive_uart.h    |   0
 include/hw/dma/sifive_pdma.h                |  57 ++++
 include/hw/{riscv => gpio}/sifive_gpio.h    |   0
 include/hw/{riscv => intc}/sifive_clint.h   |   4 +-
 include/hw/{riscv => misc}/sifive_e_prci.h  |   0
 include/hw/{riscv => misc}/sifive_test.h    |   0
 include/hw/{riscv => misc}/sifive_u_otp.h   |   0
 include/hw/{riscv => misc}/sifive_u_prci.h  |   0
 include/hw/net/cadence_gem.h                |   2 +
 include/hw/riscv/microchip_pfsoc.h          | 133 +++++++++
 include/hw/riscv/riscv_hart.h               |   1 +
 include/hw/riscv/sifive_e.h                 |   2 +-
 include/hw/riscv/sifive_u.h                 |  17 +-
 include/hw/sd/cadence_sdhci.h               |  47 +++
 target/riscv/cpu.h                          |   8 +-
 hw/arm/xilinx_zynq.c                        |   1 +
 hw/arm/xlnx-versal.c                        |   1 +
 hw/arm/xlnx-zynqmp.c                        |   2 +
 hw/char/mchp_pfsoc_mmuart.c                 |  86 ++++++
 hw/{riscv => char}/riscv_htif.c             |   2 +-
 hw/{riscv => char}/sifive_uart.c            |   2 +-
 hw/dma/sifive_pdma.c                        | 313 ++++++++++++++++++++
 hw/{riscv => gpio}/sifive_gpio.c            |   2 +-
 hw/{riscv => intc}/sifive_clint.c           |  28 +-
 hw/{riscv => intc}/sifive_plic.c            |   2 +-
 hw/{riscv => misc}/sifive_e_prci.c          |   2 +-
 hw/{riscv => misc}/sifive_test.c            |   4 +-
 hw/{riscv => misc}/sifive_u_otp.c           |   2 +-
 hw/{riscv => misc}/sifive_u_prci.c          |   2 +-
 hw/net/cadence_gem.c                        |   7 +-
 hw/riscv/microchip_pfsoc.c                  | 437 ++++++++++++++++++++++++++++
 hw/riscv/opentitan.c                        |   1 +
 hw/riscv/riscv_hart.c                       |   3 +
 hw/riscv/sifive_e.c                         |  12 +-
 hw/riscv/sifive_u.c                         |  41 ++-
 hw/riscv/spike.c                            |   7 +-
 hw/riscv/virt.c                             |   9 +-
 hw/sd/cadence_sdhci.c                       | 193 ++++++++++++
 target/riscv/cpu.c                          |  19 +-
 target/riscv/cpu_helper.c                   |   8 +-
 target/riscv/csr.c                          |   4 +-
 MAINTAINERS                                 |   9 +
 hw/char/Kconfig                             |   9 +
 hw/char/meson.build                         |   3 +
 hw/dma/Kconfig                              |   3 +
 hw/dma/meson.build                          |   1 +
 hw/gpio/Kconfig                             |   3 +
 hw/gpio/meson.build                         |   1 +
 hw/gpio/trace-events                        |   6 +
 hw/intc/Kconfig                             |   6 +
 hw/intc/meson.build                         |   2 +
 hw/misc/Kconfig                             |  12 +
 hw/misc/meson.build                         |   6 +
 hw/riscv/Kconfig                            |  70 +++--
 hw/riscv/meson.build                        |  12 +-
 hw/riscv/trace-events                       |   7 -
 hw/sd/Kconfig                               |   4 +
 hw/sd/meson.build                           |   1 +
 meson.build                                 |   1 -
 64 files changed, 1575 insertions(+), 105 deletions(-)
 rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
 delete mode 100644 hw/riscv/trace.h
 create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
 rename include/hw/{riscv => char}/riscv_htif.h (100%)
 rename include/hw/{riscv => char}/sifive_uart.h (100%)
 create mode 100644 include/hw/dma/sifive_pdma.h
 rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
 rename include/hw/{riscv => intc}/sifive_clint.h (92%)
 rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
 rename include/hw/{riscv => misc}/sifive_test.h (100%)
 rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
 rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
 create mode 100644 include/hw/riscv/microchip_pfsoc.h
 create mode 100644 include/hw/sd/cadence_sdhci.h
 create mode 100644 hw/char/mchp_pfsoc_mmuart.c
 rename hw/{riscv => char}/riscv_htif.c (99%)
 rename hw/{riscv => char}/sifive_uart.c (99%)
 create mode 100644 hw/dma/sifive_pdma.c
 rename hw/{riscv => gpio}/sifive_gpio.c (99%)
 rename hw/{riscv => intc}/sifive_clint.c (90%)
 rename hw/{riscv => intc}/sifive_plic.c (99%)
 rename hw/{riscv => misc}/sifive_e_prci.c (99%)
 rename hw/{riscv => misc}/sifive_test.c (97%)
 rename hw/{riscv => misc}/sifive_u_otp.c (99%)
 rename hw/{riscv => misc}/sifive_u_prci.c (99%)
 create mode 100644 hw/riscv/microchip_pfsoc.c
 create mode 100644 hw/sd/cadence_sdhci.c
 delete mode 100644 hw/riscv/trace-events

From: Yifei Jiang <jiangyifei@huawei.com>

When the cause number is equal to or greater than 23, print "(unknown)" in
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
excpetion "guest_store_page_fault" can not be printed.

In addition, the current check of cause is invalid for riscv_intr_names. So
introduce riscv_cpu_get_trap_name to get the trap cause name.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  1 +
 target/riscv/cpu.c        | 11 +++++++++++
 target/riscv/cpu_helper.c |  4 ++--
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ extern const char * const riscv_fpr_regnames[];
 extern const char * const riscv_excp_names[];
 extern const char * const riscv_intr_names[];
 
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 void riscv_cpu_do_interrupt(CPUState *cpu);
 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
     "reserved"
 };
 
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+{
+    if (async) {
+        return (cause < ARRAY_SIZE(riscv_intr_names)) ?
+               riscv_intr_names[cause] : "(unknown)";
+    } else {
+        return (cause < ARRAY_SIZE(riscv_excp_names)) ?
+               riscv_excp_names[cause] : "(unknown)";
+    }
+}
+
 static void set_misa(CPURISCVState *env, target_ulong misa)
 {
     env->misa_mask = env->misa = misa;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         }
     }
 
-    trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
-        (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
+    trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
+        riscv_cpu_get_trap_name(cause, async));
 
     if (env->priv <= PRV_S &&
             cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
-- 
2.28.0

From: Nathan Chancellor <natechancellor@gmail.com>

When shutting down the machine running a mainline Linux kernel, the
following error happens:

$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
    -display none -initrd rootfs.cpio -kernel Image -m 512m \
    -nodefaults -serial mon:stdio
...
Requesting system poweroff
[    4.999630] reboot: Power down
sbi_trap_error: hart0: trap handler failed (error -2)
sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
sbi_trap_error: hart0: t6=0x0000000000000000

The kernel does a 16-bit write when powering off the machine, which
was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
mismatching sizes in memory_region_access_valid""). Make min_access_size
match reality so that the machine can shut down properly now.

Cc: qemu-stable@nongnu.org
Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_test_ops = {
     .write = sifive_test_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid = {
-        .min_access_size = 4,
+        .min_access_size = 2,
         .max_access_size = 4
     }
 };
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.

Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 1 +
 target/riscv/cpu.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPU {
         uint16_t elen;
         bool mmu;
         bool pmp;
+        uint64_t resetvec;
     } cfg;
 } RISCVCPU;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+    DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/riscv_hart.h | 1 +
 hw/riscv/riscv_hart.c         | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVHartArrayState {
     uint32_t num_harts;
     uint32_t hartid_base;
     char *cpu_type;
+    uint64_t resetvec;
     RISCVCPU *harts;
 } RISCVHartArrayState;
 
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_harts_props[] = {
     DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
     DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
     DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
+    DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
+                       DEFAULT_RSTVEC),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
                                char *cpu_type, Error **errp)
 {
     object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
+    qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
     s->harts[idx].env.mhartid = s->hartid_base + idx;
     qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
     return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 1 +
 hw/riscv/sifive_e.c  | 1 +
 hw/riscv/sifive_u.c  | 2 ++
 target/riscv/cpu.c   | 7 ++-----
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 
     /* Boot ROM */
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_init(Object *obj)
     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
     object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
                             TYPE_SIFIVE_GPIO);
 }
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
     qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
+    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
 
     object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
     qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
+    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
 
     object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
     object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_11_0);
-    set_resetvec(env, DEFAULT_RSTVEC);
 }
 
 static void riscv_base_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void riscv_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, 0);
-    set_resetvec(env, DEFAULT_RSTVEC);
 }
 
 static void rvxx_sifive_u_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_u_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, 0x1004);
 }
 
 static void rvxx_sifive_e_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_e_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, 0x1004);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
 
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, 0x8090);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         set_feature(env, RISCV_FEATURE_PMP);
     }
 
+    set_resetvec(env, cpu->cfg.resetvec);
+
     /* If misa isn't set (rv32 and rv64 machines) set it here */
     if (!env->misa) {
         /* Do some ISA extension error checking */
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.

For more details about Microchip PolarFire Soc, please see:
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga

Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
The following perepherals are created as an unimplemented device:

- Bus Error Uint 0/1/2/3/4
- L2 cache controller
- SYSREG
- MPUCFG
- IOSCBCFG

More devices will be added later.

The BIOS image used by this machine is hss.bin, aka Hart Software
Services, which can be built from:
https://github.com/polarfire-soc/hart-software-services

To launch this machine:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit

The memory is set to 1 GiB by default to match the hardware.
A sanity check on ram size is performed in the machine init routine
to prompt user to increase the RAM size to > 1 GiB when less than
1 GiB ram is detected.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/riscv64-softmmu.mak |   1 +
 include/hw/riscv/microchip_pfsoc.h  |  88 ++++++++
 hw/riscv/microchip_pfsoc.c          | 312 ++++++++++++++++++++++++++++
 MAINTAINERS                         |   7 +
 hw/riscv/Kconfig                    |   6 +
 hw/riscv/meson.build                |   1 +
 6 files changed, 415 insertions(+)
 create mode 100644 include/hw/riscv/microchip_pfsoc.h
 create mode 100644 hw/riscv/microchip_pfsoc.c

diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_SPIKE=y
 CONFIG_SIFIVE_E=y
 CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
+CONFIG_MICROCHIP_PFSOC=y
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC machine interface
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MICROCHIP_PFSOC_H
+#define HW_MICROCHIP_PFSOC_H
+
+typedef struct MicrochipPFSoCState {
+    /*< private >*/
+    DeviceState parent_obj;
+
+    /*< public >*/
+    CPUClusterState e_cluster;
+    CPUClusterState u_cluster;
+    RISCVHartArrayState e_cpus;
+    RISCVHartArrayState u_cpus;
+    DeviceState *plic;
+} MicrochipPFSoCState;
+
+#define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
+#define MICROCHIP_PFSOC(obj) \
+    OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
+
+typedef struct MicrochipIcicleKitState {
+    /*< private >*/
+    MachineState parent_obj;
+
+    /*< public >*/
+    MicrochipPFSoCState soc;
+} MicrochipIcicleKitState;
+
+#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
+    MACHINE_TYPE_NAME("microchip-icicle-kit")
+#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
+    OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
+                 TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
+
+enum {
+    MICROCHIP_PFSOC_DEBUG,
+    MICROCHIP_PFSOC_E51_DTIM,
+    MICROCHIP_PFSOC_BUSERR_UNIT0,
+    MICROCHIP_PFSOC_BUSERR_UNIT1,
+    MICROCHIP_PFSOC_BUSERR_UNIT2,
+    MICROCHIP_PFSOC_BUSERR_UNIT3,
+    MICROCHIP_PFSOC_BUSERR_UNIT4,
+    MICROCHIP_PFSOC_CLINT,
+    MICROCHIP_PFSOC_L2CC,
+    MICROCHIP_PFSOC_L2LIM,
+    MICROCHIP_PFSOC_PLIC,
+    MICROCHIP_PFSOC_SYSREG,
+    MICROCHIP_PFSOC_MPUCFG,
+    MICROCHIP_PFSOC_ENVM_CFG,
+    MICROCHIP_PFSOC_ENVM_DATA,
+    MICROCHIP_PFSOC_IOSCB_CFG,
+    MICROCHIP_PFSOC_DRAM,
+};
+
+#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
+#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
+
+#define MICROCHIP_PFSOC_PLIC_HART_CONFIG        "MS"
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
+#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
+#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
+#define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
+#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
+#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE       0x200000
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE     0x1000
+
+#endif /* HW_MICROCHIP_PFSOC_H */
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
+ *
+ * 0) CLINT (Core Level Interruptor)
+ * 1) PLIC (Platform Level Interrupt Controller)
+ * 2) eNVM (Embedded Non-Volatile Memory)
+ *
+ * This board currently generates devicetree dynamically that indicates at least
+ * two harts and up to five harts.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "hw/loader.h"
+#include "hw/sysbus.h"
+#include "hw/cpu/cluster.h"
+#include "target/riscv/cpu.h"
+#include "hw/misc/unimp.h"
+#include "hw/riscv/boot.h"
+#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/sifive_clint.h"
+#include "hw/riscv/sifive_plic.h"
+#include "hw/riscv/microchip_pfsoc.h"
+
+/*
+ * The BIOS image used by this machine is called Hart Software Services (HSS).
+ * See https://github.com/polarfire-soc/hart-software-services
+ */
+#define BIOS_FILENAME   "hss.bin"
+#define RESET_VECTOR    0x20220000
+
+static const struct MemmapEntry {
+    hwaddr base;
+    hwaddr size;
+} microchip_pfsoc_memmap[] = {
+    [MICROCHIP_PFSOC_DEBUG] =           {        0x0,     0x1000 },
+    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,     0x2000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,     0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,     0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,     0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,     0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
+    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
+    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
+    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
+    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
+    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
+    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
+    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
+    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
+    [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
+    [MICROCHIP_PFSOC_DRAM] =            { 0x80000000,        0x0 },
+};
+
+static void microchip_pfsoc_soc_instance_init(Object *obj)
+{
+    MachineState *ms = MACHINE(qdev_get_machine());
+    MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
+
+    object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
+    qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
+
+    object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
+                            TYPE_RISCV_HART_ARRAY);
+    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
+    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
+    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
+                         TYPE_RISCV_CPU_SIFIVE_E51);
+    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
+
+    object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
+    qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
+
+    object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
+                            TYPE_RISCV_HART_ARRAY);
+    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
+    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
+    qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
+                         TYPE_RISCV_CPU_SIFIVE_U54);
+    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
+}
+
+static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+{
+    MachineState *ms = MACHINE(qdev_get_machine());
+    MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
+    const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
+    MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
+    MemoryRegion *envm_data = g_new(MemoryRegion, 1);
+    char *plic_hart_config;
+    size_t plic_hart_config_len;
+    int i;
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+    /*
+     * The cluster must be realized after the RISC-V hart array container,
+     * as the container's CPU object is only created on realize, and the
+     * CPU must exist and have been parented into the cluster before the
+     * cluster is realized.
+     */
+    qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
+    qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
+
+    /* E51 DTIM */
+    memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
+                           memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_E51_DTIM].base,
+                                e51_dtim_mem);
+
+    /* Bus Error Units */
+    create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
+    create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
+    create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
+    create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
+    create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
+
+    /* CLINT */
+    sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
+        memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+
+    /* L2 cache controller */
+    create_unimplemented_device("microchip.pfsoc.l2cc",
+        memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
+
+    /*
+     * Add L2-LIM at reset size.
+     * This should be reduced in size as the L2 Cache Controller WayEnable
+     * register is incremented. Unfortunately I don't see a nice (or any) way
+     * to handle reducing or blocking out the L2 LIM while still allowing it
+     * be re returned to all enabled after a reset. For the time being, just
+     * leave it enabled all the time. This won't break anything, but will be
+     * too generous to misbehaving guests.
+     */
+    memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
+                           memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_L2LIM].base,
+                                l2lim_mem);
+
+    /* create PLIC hart topology configuration string */
+    plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
+                           ms->smp.cpus;
+    plic_hart_config = g_malloc0(plic_hart_config_len);
+    for (i = 0; i < ms->smp.cpus; i++) {
+        if (i != 0) {
+            strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
+                    plic_hart_config_len);
+        } else {
+            strncat(plic_hart_config, "M", plic_hart_config_len);
+        }
+        plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
+    }
+
+    /* PLIC */
+    s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
+        plic_hart_config, 0,
+        MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
+        MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
+        MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
+        MICROCHIP_PFSOC_PLIC_PENDING_BASE,
+        MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
+        MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
+        MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
+        MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
+        memmap[MICROCHIP_PFSOC_PLIC].size);
+    g_free(plic_hart_config);
+
+    /* SYSREG */
+    create_unimplemented_device("microchip.pfsoc.sysreg",
+        memmap[MICROCHIP_PFSOC_SYSREG].base,
+        memmap[MICROCHIP_PFSOC_SYSREG].size);
+
+    /* MPUCFG */
+    create_unimplemented_device("microchip.pfsoc.mpucfg",
+        memmap[MICROCHIP_PFSOC_MPUCFG].base,
+        memmap[MICROCHIP_PFSOC_MPUCFG].size);
+
+    /* eNVM */
+    memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
+                           memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
+                           &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
+                                envm_data);
+
+    /* IOSCBCFG */
+    create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
+        memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
+        memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+}
+
+static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = microchip_pfsoc_soc_realize;
+    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
+    dc->user_creatable = false;
+}
+
+static const TypeInfo microchip_pfsoc_soc_type_info = {
+    .name = TYPE_MICROCHIP_PFSOC,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(MicrochipPFSoCState),
+    .instance_init = microchip_pfsoc_soc_instance_init,
+    .class_init = microchip_pfsoc_soc_class_init,
+};
+
+static void microchip_pfsoc_soc_register_types(void)
+{
+    type_register_static(&microchip_pfsoc_soc_type_info);
+}
+
+type_init(microchip_pfsoc_soc_register_types)
+
+static void microchip_icicle_kit_machine_init(MachineState *machine)
+{
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
+    const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
+    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+    /* Sanity check on RAM size */
+    if (machine->ram_size < mc->default_ram_size) {
+        char *sz = size_to_str(mc->default_ram_size);
+        error_report("Invalid RAM size, should be bigger than %s", sz);
+        g_free(sz);
+        exit(EXIT_FAILURE);
+    }
+
+    /* Initialize SoC */
+    object_initialize_child(OBJECT(machine), "soc", &s->soc,
+                            TYPE_MICROCHIP_PFSOC);
+    qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
+
+    /* Register RAM */
+    memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
+                           machine->ram_size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
+
+    /* Load the firmware */
+    riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
+}
+
+static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "Microchip PolarFire SoC Icicle Kit";
+    mc->init = microchip_icicle_kit_machine_init;
+    mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
+                   MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
+    mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
+    mc->default_cpus = mc->min_cpus;
+    mc->default_ram_size = 1 * GiB;
+}
+
+static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
+    .name       = MACHINE_TYPE_NAME("microchip-icicle-kit"),
+    .parent     = TYPE_MACHINE,
+    .class_init = microchip_icicle_kit_machine_class_init,
+    .instance_size = sizeof(MicrochipIcicleKitState),
+};
+
+static void microchip_icicle_kit_machine_init_register_types(void)
+{
+    type_register_static(&microchip_icicle_kit_machine_typeinfo);
+}
+
+type_init(microchip_icicle_kit_machine_init_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/opentitan.h
 F: include/hw/char/ibex_uart.h
 F: include/hw/intc/ibex_plic.h
 
+Microchip PolarFire SoC Icicle Kit
+M: Bin Meng <bin.meng@windriver.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/microchip_pfsoc.c
+F: include/hw/riscv/microchip_pfsoc.h
+
 RX Machines
 -----------
 rx-gdbsim
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
     select SIFIVE
+
+config MICROCHIP_PFSOC
+    bool
+    select HART
+    select SIFIVE
+    select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
+riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 
 hw_arch += {'riscv': riscv_ss}
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC MMUART is ns16550 compatible, with some
additional registers. Create a simple MMUART model built on top
of the existing ns16550 model.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
 hw/char/mchp_pfsoc_mmuart.c         | 86 +++++++++++++++++++++++++++++
 MAINTAINERS                         |  2 +
 hw/char/Kconfig                     |  3 +
 hw/char/meson.build                 |  1 +
 5 files changed, 153 insertions(+)
 create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
 create mode 100644 hw/char/mchp_pfsoc_mmuart.c

diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC MMUART emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MCHP_PFSOC_MMUART_H
+#define HW_MCHP_PFSOC_MMUART_H
+
+#include "hw/char/serial.h"
+
+#define MCHP_PFSOC_MMUART_REG_SIZE  52
+
+typedef struct MchpPfSoCMMUartState {
+    MemoryRegion iomem;
+    hwaddr base;
+    qemu_irq irq;
+
+    SerialMM *serial;
+
+    uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
+} MchpPfSoCMMUartState;
+
+/**
+ * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
+ *
+ * This is a helper routine for board to create a MMUART device that is
+ * compatible with Microchip PolarFire SoC.
+ *
+ * @sysmem: system memory region to map
+ * @base: base address of the MMUART registers
+ * @irq: IRQ number of the MMUART device
+ * @chr: character device to associate to
+ *
+ * @return: a pointer to the device specific control structure
+ */
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+    hwaddr base, qemu_irq irq, Chardev *chr);
+
+#endif /* HW_MCHP_PFSOC_MMUART_H */
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC MMUART emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "chardev/char.h"
+#include "exec/address-spaces.h"
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
+static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
+{
+    MchpPfSoCMMUartState *s = opaque;
+
+    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        return 0;
+    }
+
+    return s->reg[addr / sizeof(uint32_t)];
+}
+
+static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
+                                    uint64_t value, unsigned size)
+{
+    MchpPfSoCMMUartState *s = opaque;
+    uint32_t val32 = (uint32_t)value;
+
+    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
+                      " v=0x%x\n", __func__, addr, val32);
+        return;
+    }
+
+    s->reg[addr / sizeof(uint32_t)] = val32;
+}
+
+static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
+    .read = mchp_pfsoc_mmuart_read,
+    .write = mchp_pfsoc_mmuart_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+    hwaddr base, qemu_irq irq, Chardev *chr)
+{
+    MchpPfSoCMMUartState *s;
+
+    s = g_new0(MchpPfSoCMMUartState, 1);
+
+    memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
+                          "mchp.pfsoc.mmuart", 0x1000);
+
+    s->base = base;
+    s->irq = irq;
+
+    s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
+                               DEVICE_LITTLE_ENDIAN);
+
+    memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
+
+    return s;
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Bin Meng <bin.meng@windriver.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: hw/riscv/microchip_pfsoc.c
+F: hw/char/mchp_pfsoc_mmuart.c
 F: include/hw/riscv/microchip_pfsoc.h
+F: include/hw/char/mchp_pfsoc_mmuart.h
 
 RX Machines
 -----------
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@ config RENESAS_SCI
 
 config AVR_USART
     bool
+
+config MCHP_PFSOC_MMUART
+    bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
 softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
 softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
 
 specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
 specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
 hw/riscv/microchip_pfsoc.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig                   |  1 +
 3 files changed, 51 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 #ifndef HW_MICROCHIP_PFSOC_H
 #define HW_MICROCHIP_PFSOC_H
 
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
 typedef struct MicrochipPFSoCState {
     /*< private >*/
     DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     RISCVHartArrayState e_cpus;
     RISCVHartArrayState u_cpus;
     DeviceState *plic;
+    MchpPfSoCMMUartState *serial0;
+    MchpPfSoCMMUartState *serial1;
+    MchpPfSoCMMUartState *serial2;
+    MchpPfSoCMMUartState *serial3;
+    MchpPfSoCMMUartState *serial4;
 } MicrochipPFSoCState;
 
 #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_L2CC,
     MICROCHIP_PFSOC_L2LIM,
     MICROCHIP_PFSOC_PLIC,
+    MICROCHIP_PFSOC_MMUART0,
     MICROCHIP_PFSOC_SYSREG,
     MICROCHIP_PFSOC_MPUCFG,
+    MICROCHIP_PFSOC_MMUART1,
+    MICROCHIP_PFSOC_MMUART2,
+    MICROCHIP_PFSOC_MMUART3,
+    MICROCHIP_PFSOC_MMUART4,
     MICROCHIP_PFSOC_ENVM_CFG,
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_IOSCB_CFG,
     MICROCHIP_PFSOC_DRAM,
 };
 
+enum {
+    MICROCHIP_PFSOC_MMUART0_IRQ = 90,
+    MICROCHIP_PFSOC_MMUART1_IRQ = 91,
+    MICROCHIP_PFSOC_MMUART2_IRQ = 92,
+    MICROCHIP_PFSOC_MMUART3_IRQ = 93,
+    MICROCHIP_PFSOC_MMUART4_IRQ = 94,
+};
+
 #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
 
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 0) CLINT (Core Level Interruptor)
  * 1) PLIC (Platform Level Interrupt Controller)
  * 2) eNVM (Embedded Non-Volatile Memory)
+ * 3) MMUARTs (Multi-Mode UART)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "hw/loader.h"
 #include "hw/sysbus.h"
+#include "chardev/char.h"
 #include "hw/cpu/cluster.h"
 #include "target/riscv/cpu.h"
 #include "hw/misc/unimp.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
+#include "sysemu/sysemu.h"
 
 /*
  * The BIOS image used by this machine is called Hart Software Services (HSS).
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
     [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
     [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
+    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
     [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
     [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
+    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
+    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
+    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
+    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         memmap[MICROCHIP_PFSOC_MPUCFG].base,
         memmap[MICROCHIP_PFSOC_MPUCFG].size);
 
+    /* MMUARTs */
+    s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART0].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
+        serial_hd(0));
+    s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART1].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
+        serial_hd(1));
+    s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART2].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
+        serial_hd(2));
+    s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART3].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
+        serial_hd(3));
+    s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART4].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
+        serial_hd(4));
+
     /* eNVM */
     memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
                            memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select HART
     select SIFIVE
     select UNIMP
+    select MCHP_PFSOC_MMUART
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.

This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/sd/cadence_sdhci.h |  47 +++++++++
 hw/sd/cadence_sdhci.c         | 193 ++++++++++++++++++++++++++++++++++
 hw/sd/Kconfig                 |   4 +
 hw/sd/meson.build             |   1 +
 4 files changed, 245 insertions(+)
 create mode 100644 include/hw/sd/cadence_sdhci.h
 create mode 100644 hw/sd/cadence_sdhci.c

diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/sd/cadence_sdhci.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Cadence SDHCI emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CADENCE_SDHCI_H
+#define CADENCE_SDHCI_H
+
+#include "hw/sd/sdhci.h"
+
+#define CADENCE_SDHCI_REG_SIZE  0x100
+#define CADENCE_SDHCI_NUM_REGS  (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
+
+typedef struct CadenceSDHCIState {
+    SysBusDevice parent;
+
+    MemoryRegion container;
+    MemoryRegion iomem;
+    BusState *bus;
+
+    uint32_t regs[CADENCE_SDHCI_NUM_REGS];
+
+    SDHCIState sdhci;
+} CadenceSDHCIState;
+
+#define TYPE_CADENCE_SDHCI  "cadence.sdhci"
+#define CADENCE_SDHCI(obj)  OBJECT_CHECK(CadenceSDHCIState, (obj), \
+                                         TYPE_CADENCE_SDHCI)
+
+#endif /* CADENCE_SDHCI_H */
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/sd/cadence_sdhci.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Cadence SDHCI emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/sd/cadence_sdhci.h"
+#include "sdhci-internal.h"
+
+/* HRS - Host Register Set (specific to Cadence) */
+
+#define CADENCE_SDHCI_HRS00             0x00    /* general information */
+#define CADENCE_SDHCI_HRS00_SWR             BIT(0)
+#define CADENCE_SDHCI_HRS00_POR_VAL         0x00010000
+
+#define CADENCE_SDHCI_HRS04             0x10    /* PHY access port */
+#define CADENCE_SDHCI_HRS04_WR              BIT(24)
+#define CADENCE_SDHCI_HRS04_RD              BIT(25)
+#define CADENCE_SDHCI_HRS04_ACK             BIT(26)
+
+#define CADENCE_SDHCI_HRS06             0x18    /* eMMC control */
+#define CADENCE_SDHCI_HRS06_TUNE_UP         BIT(15)
+
+/* SRS - Slot Register Set (SDHCI-compatible) */
+
+#define CADENCE_SDHCI_SRS_BASE          0x200
+
+#define TO_REG(addr)    ((addr) / sizeof(uint32_t))
+
+static void cadence_sdhci_instance_init(Object *obj)
+{
+    CadenceSDHCIState *s = CADENCE_SDHCI(obj);
+
+    object_initialize_child(OBJECT(s), "generic-sdhci",
+                            &s->sdhci, TYPE_SYSBUS_SDHCI);
+}
+
+static void cadence_sdhci_reset(DeviceState *dev)
+{
+    CadenceSDHCIState *s = CADENCE_SDHCI(dev);
+
+    memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE);
+    s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL;
+
+    device_cold_reset(DEVICE(&s->sdhci));
+}
+
+static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    CadenceSDHCIState *s = opaque;
+    uint32_t val;
+
+    val = s->regs[TO_REG(addr)];
+
+    return (uint64_t)val;
+}
+
+static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
+                                unsigned int size)
+{
+    CadenceSDHCIState *s = opaque;
+    uint32_t val32 = (uint32_t)val;
+
+    switch (addr) {
+    case CADENCE_SDHCI_HRS00:
+        /*
+         * The only writable bit is SWR (software reset) and it automatically
+         * clears to zero, so essentially this register remains unchanged.
+         */
+        if (val32 & CADENCE_SDHCI_HRS00_SWR) {
+            cadence_sdhci_reset(DEVICE(s));
+        }
+
+        break;
+    case CADENCE_SDHCI_HRS04:
+        /*
+         * Only emulate the ACK bit behavior when read or write transaction
+         * are requested.
+         */
+        if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) {
+            val32 |= CADENCE_SDHCI_HRS04_ACK;
+        } else {
+            val32 &= ~CADENCE_SDHCI_HRS04_ACK;
+        }
+
+        s->regs[TO_REG(addr)] = val32;
+        break;
+    case CADENCE_SDHCI_HRS06:
+        if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) {
+            val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP;
+        }
+
+        s->regs[TO_REG(addr)] = val32;
+        break;
+    default:
+        s->regs[TO_REG(addr)] = val32;
+        break;
+    }
+}
+
+static const MemoryRegionOps cadence_sdhci_ops = {
+    .read = cadence_sdhci_read,
+    .write = cadence_sdhci_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    }
+};
+
+static void cadence_sdhci_realize(DeviceState *dev, Error **errp)
+{
+    CadenceSDHCIState *s = CADENCE_SDHCI(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
+
+    memory_region_init(&s->container, OBJECT(s),
+                       "cadence.sdhci-container", 0x1000);
+    sysbus_init_mmio(sbd, &s->container);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops,
+                          s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE);
+    memory_region_add_subregion(&s->container, 0, &s->iomem);
+
+    sysbus_realize(sbd_sdhci, errp);
+    memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE,
+                                sysbus_mmio_get_region(sbd_sdhci, 0));
+
+    /* propagate irq and "sd-bus" from generic-sdhci */
+    sysbus_pass_irq(sbd, sbd_sdhci);
+    s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
+}
+
+static const VMStateDescription vmstate_cadence_sdhci = {
+    .name = TYPE_CADENCE_SDHCI,
+    .version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(classp);
+
+    dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)";
+    dc->realize = cadence_sdhci_realize;
+    dc->reset = cadence_sdhci_reset;
+    dc->vmsd = &vmstate_cadence_sdhci;
+}
+
+static TypeInfo cadence_sdhci_info = {
+    .name          = TYPE_CADENCE_SDHCI,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(CadenceSDHCIState),
+    .instance_init = cadence_sdhci_instance_init,
+    .class_init    = cadence_sdhci_class_init,
+};
+
+static void cadence_sdhci_register_types(void)
+{
+    type_register_static(&cadence_sdhci_info);
+}
+
+type_init(cadence_sdhci_register_types)
diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/Kconfig
+++ b/hw/sd/Kconfig
@@ -XXX,XX +XXX,XX @@ config SDHCI_PCI
     default y if PCI_DEVICES
     depends on PCI
     select SDHCI
+
+config CADENCE_SDHCI
+    bool
+    select SDHCI
diff --git a/hw/sd/meson.build b/hw/sd/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/meson.build
+++ b/hw/sd/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
+softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.

As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test this, the Hart Software Services (HSS)
should choose the SD card configuration:

$ cp boards/icicle-kit-es/def_config.sdcard .config
$ make BOARD=icicle-kit-es

The SD card image can be built from the Yocto BSP at:
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp

Note the generated SD card image should be resized before use:
$ qemu-img resize /path/to/sdcard.img 4G

Launch QEMU with the following command:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  4 ++++
 hw/riscv/microchip_pfsoc.c         | 23 +++++++++++++++++++++++
 hw/riscv/Kconfig                   |  1 +
 3 files changed, 28 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 #define HW_MICROCHIP_PFSOC_H
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     MchpPfSoCMMUartState *serial2;
     MchpPfSoCMMUartState *serial3;
     MchpPfSoCMMUartState *serial4;
+    CadenceSDHCIState sdhci;
 } MicrochipPFSoCState;
 
 #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_MMUART0,
     MICROCHIP_PFSOC_SYSREG,
     MICROCHIP_PFSOC_MPUCFG,
+    MICROCHIP_PFSOC_EMMC_SD,
     MICROCHIP_PFSOC_MMUART1,
     MICROCHIP_PFSOC_MMUART2,
     MICROCHIP_PFSOC_MMUART3,
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
+    MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
     MICROCHIP_PFSOC_MMUART0_IRQ = 90,
     MICROCHIP_PFSOC_MMUART1_IRQ = 91,
     MICROCHIP_PFSOC_MMUART2_IRQ = 92,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 1) PLIC (Platform Level Interrupt Controller)
  * 2) eNVM (Embedded Non-Volatile Memory)
  * 3) MMUARTs (Multi-Mode UART)
+ * 4) Cadence eMMC/SDHC controller and an SD card connected to it
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
     [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
     [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
+    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
                          TYPE_RISCV_CPU_SIFIVE_U54);
     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
+
+    object_initialize_child(obj, "sd-controller", &s->sdhci,
+                            TYPE_CADENCE_SDHCI);
 }
 
 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         memmap[MICROCHIP_PFSOC_MPUCFG].base,
         memmap[MICROCHIP_PFSOC_MPUCFG].size);
 
+    /* SDHCI */
+    sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
+                    memmap[MICROCHIP_PFSOC_EMMC_SD].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
+
     /* MMUARTs */
     s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
         memmap[MICROCHIP_PFSOC_MMUART0].base,
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+    DriveInfo *dinfo = drive_get_next(IF_SD);
 
     /* Sanity check on RAM size */
     if (machine->ram_size < mc->default_ram_size) {
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
 
     /* Load the firmware */
     riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
+
+    /* Attach an SD card */
+    if (dinfo) {
+        CadenceSDHCIState *sdhci = &(s->soc.sdhci);
+        DeviceState *card = qdev_new(TYPE_SD_CARD);
+
+        qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
+                                &error_fatal);
+        qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
+    }
 }
 
 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select SIFIVE
     select UNIMP
     select MCHP_PFSOC_MMUART
+    select CADENCE_SDHCI
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution
which is actually an IP reused from the SiFive FU540 chip.

This creates a model to support both polling and interrupt modes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/dma/sifive_pdma.h |  57 +++++++
 hw/dma/sifive_pdma.c         | 313 +++++++++++++++++++++++++++++++++++
 hw/dma/Kconfig               |   3 +
 hw/dma/meson.build           |   1 +
 4 files changed, 374 insertions(+)
 create mode 100644 include/hw/dma/sifive_pdma.h
 create mode 100644 hw/dma/sifive_pdma.c

diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/dma/sifive_pdma.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SiFive Platform DMA emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SIFIVE_PDMA_H
+#define SIFIVE_PDMA_H
+
+struct sifive_pdma_chan {
+    uint32_t control;
+    uint32_t next_config;
+    uint64_t next_bytes;
+    uint64_t next_dst;
+    uint64_t next_src;
+    uint32_t exec_config;
+    uint64_t exec_bytes;
+    uint64_t exec_dst;
+    uint64_t exec_src;
+    int state;
+};
+
+#define SIFIVE_PDMA_CHANS           4
+#define SIFIVE_PDMA_IRQS            (SIFIVE_PDMA_CHANS * 2)
+#define SIFIVE_PDMA_REG_SIZE        0x100000
+#define SIFIVE_PDMA_CHAN_NO(reg)    ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
+
+typedef struct SiFivePDMAState {
+    SysBusDevice parent;
+    MemoryRegion iomem;
+    qemu_irq irq[SIFIVE_PDMA_IRQS];
+
+    struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
+} SiFivePDMAState;
+
+#define TYPE_SIFIVE_PDMA    "sifive.pdma"
+
+#define SIFIVE_PDMA(obj)    \
+    OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
+
+#endif /* SIFIVE_PDMA_H */
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/dma/sifive_pdma.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SiFive Platform DMA emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "sysemu/dma.h"
+#include "hw/dma/sifive_pdma.h"
+
+#define DMA_CONTROL         0x000
+#define   CONTROL_CLAIM     BIT(0)
+#define   CONTROL_RUN       BIT(1)
+#define   CONTROL_DONE_IE   BIT(14)
+#define   CONTROL_ERR_IE    BIT(15)
+#define   CONTROL_DONE      BIT(30)
+#define   CONTROL_ERR       BIT(31)
+
+#define DMA_NEXT_CONFIG     0x004
+#define   CONFIG_REPEAT     BIT(2)
+#define   CONFIG_ORDER      BIT(3)
+#define   CONFIG_WRSZ_SHIFT 24
+#define   CONFIG_RDSZ_SHIFT 28
+#define   CONFIG_SZ_MASK    0xf
+
+#define DMA_NEXT_BYTES      0x008
+#define DMA_NEXT_DST        0x010
+#define DMA_NEXT_SRC        0x018
+#define DMA_EXEC_CONFIG     0x104
+#define DMA_EXEC_BYTES      0x108
+#define DMA_EXEC_DST        0x110
+#define DMA_EXEC_SRC        0x118
+
+enum dma_chan_state {
+    DMA_CHAN_STATE_IDLE,
+    DMA_CHAN_STATE_STARTED,
+    DMA_CHAN_STATE_ERROR,
+    DMA_CHAN_STATE_DONE
+};
+
+static void sifive_pdma_run(SiFivePDMAState *s, int ch)
+{
+    uint64_t bytes = s->chan[ch].next_bytes;
+    uint64_t dst = s->chan[ch].next_dst;
+    uint64_t src = s->chan[ch].next_src;
+    uint32_t config = s->chan[ch].next_config;
+    int wsize, rsize, size;
+    uint8_t buf[64];
+    int n;
+
+    /* do nothing if bytes to transfer is zero */
+    if (!bytes) {
+        goto error;
+    }
+
+    /*
+     * The manual does not describe how the hardware behaviors when
+     * config.wsize and config.rsize are given different values.
+     * A common case is memory to memory DMA, and in this case they
+     * are normally the same. Abort if this expectation fails.
+     */
+    wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
+    rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
+    if (wsize != rsize) {
+        goto error;
+    }
+
+    /*
+     * Calculate the transaction size
+     *
+     * size field is base 2 logarithm of DMA transaction size,
+     * but there is an upper limit of 64 bytes per transaction.
+     */
+    size = wsize;
+    if (size > 6) {
+        size = 6;
+    }
+    size = 1 << size;
+
+    /* the bytes to transfer should be multiple of transaction size */
+    if (bytes % size) {
+        goto error;
+    }
+
+    /* indicate a DMA transfer is started */
+    s->chan[ch].state = DMA_CHAN_STATE_STARTED;
+    s->chan[ch].control &= ~CONTROL_DONE;
+    s->chan[ch].control &= ~CONTROL_ERR;
+
+    /* load the next_ registers into their exec_ counterparts */
+    s->chan[ch].exec_config = config;
+    s->chan[ch].exec_bytes = bytes;
+    s->chan[ch].exec_dst = dst;
+    s->chan[ch].exec_src = src;
+
+    for (n = 0; n < bytes / size; n++) {
+        cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);
+        cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);
+        s->chan[ch].exec_src += size;
+        s->chan[ch].exec_dst += size;
+        s->chan[ch].exec_bytes -= size;
+    }
+
+    /* indicate a DMA transfer is done */
+    s->chan[ch].state = DMA_CHAN_STATE_DONE;
+    s->chan[ch].control &= ~CONTROL_RUN;
+    s->chan[ch].control |= CONTROL_DONE;
+
+    /* reload exec_ registers if repeat is required */
+    if (s->chan[ch].next_config & CONFIG_REPEAT) {
+        s->chan[ch].exec_bytes = bytes;
+        s->chan[ch].exec_dst = dst;
+        s->chan[ch].exec_src = src;
+    }
+
+    return;
+
+error:
+    s->chan[ch].state = DMA_CHAN_STATE_ERROR;
+    s->chan[ch].control |= CONTROL_ERR;
+    return;
+}
+
+static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
+{
+    bool done_ie, err_ie;
+
+    done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);
+    err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);
+
+    if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {
+        qemu_irq_raise(s->irq[ch * 2]);
+    } else {
+        qemu_irq_lower(s->irq[ch * 2]);
+    }
+
+    if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {
+        qemu_irq_raise(s->irq[ch * 2 + 1]);
+    } else {
+        qemu_irq_lower(s->irq[ch * 2 + 1]);
+    }
+
+    s->chan[ch].state = DMA_CHAN_STATE_IDLE;
+}
+
+static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned size)
+{
+    SiFivePDMAState *s = opaque;
+    int ch = SIFIVE_PDMA_CHAN_NO(offset);
+    uint64_t val = 0;
+
+    if (ch >= SIFIVE_PDMA_CHANS) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
+                      __func__, ch);
+        return 0;
+    }
+
+    offset &= 0xfff;
+    switch (offset) {
+    case DMA_CONTROL:
+        val = s->chan[ch].control;
+        break;
+    case DMA_NEXT_CONFIG:
+        val = s->chan[ch].next_config;
+        break;
+    case DMA_NEXT_BYTES:
+        val = s->chan[ch].next_bytes;
+        break;
+    case DMA_NEXT_DST:
+        val = s->chan[ch].next_dst;
+        break;
+    case DMA_NEXT_SRC:
+        val = s->chan[ch].next_src;
+        break;
+    case DMA_EXEC_CONFIG:
+        val = s->chan[ch].exec_config;
+        break;
+    case DMA_EXEC_BYTES:
+        val = s->chan[ch].exec_bytes;
+        break;
+    case DMA_EXEC_DST:
+        val = s->chan[ch].exec_dst;
+        break;
+    case DMA_EXEC_SRC:
+        val = s->chan[ch].exec_src;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+                      __func__, offset);
+        break;
+    }
+
+    return val;
+}
+
+static void sifive_pdma_write(void *opaque, hwaddr offset,
+                              uint64_t value, unsigned size)
+{
+    SiFivePDMAState *s = opaque;
+    int ch = SIFIVE_PDMA_CHAN_NO(offset);
+
+    if (ch >= SIFIVE_PDMA_CHANS) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
+                      __func__, ch);
+        return;
+    }
+
+    offset &= 0xfff;
+    switch (offset) {
+    case DMA_CONTROL:
+        s->chan[ch].control = value;
+
+        if (value & CONTROL_RUN) {
+            sifive_pdma_run(s, ch);
+        }
+
+        sifive_pdma_update_irq(s, ch);
+        break;
+    case DMA_NEXT_CONFIG:
+        s->chan[ch].next_config = value;
+        break;
+    case DMA_NEXT_BYTES:
+        s->chan[ch].next_bytes = value;
+        break;
+    case DMA_NEXT_DST:
+        s->chan[ch].next_dst = value;
+        break;
+    case DMA_NEXT_SRC:
+        s->chan[ch].next_src = value;
+        break;
+    case DMA_EXEC_CONFIG:
+    case DMA_EXEC_BYTES:
+    case DMA_EXEC_DST:
+    case DMA_EXEC_SRC:
+        /* these are read-only registers */
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+                      __func__, offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps sifive_pdma_ops = {
+    .read = sifive_pdma_read,
+    .write = sifive_pdma_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    /* there are 32-bit and 64-bit wide registers */
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 8,
+    }
+};
+
+static void sifive_pdma_realize(DeviceState *dev, Error **errp)
+{
+    SiFivePDMAState *s = SIFIVE_PDMA(dev);
+    int i;
+
+    memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,
+                          TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
+
+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+        sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
+    }
+}
+
+static void sifive_pdma_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "SiFive Platform DMA controller";
+    dc->realize = sifive_pdma_realize;
+}
+
+static const TypeInfo sifive_pdma_info = {
+    .name          = TYPE_SIFIVE_PDMA,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SiFivePDMAState),
+    .class_init    = sifive_pdma_class_init,
+};
+
+static void sifive_pdma_register_types(void)
+{
+    type_register_static(&sifive_pdma_info);
+}
+
+type_init(sifive_pdma_register_types)
diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/Kconfig
+++ b/hw/dma/Kconfig
@@ -XXX,XX +XXX,XX @@ config ZYNQ_DEVCFG
 
 config STP2000
     bool
+
+config SIFIVE_PDMA
+    bool
diff --git a/hw/dma/meson.build b/hw/dma/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/meson.build
+++ b/hw/dma/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
 softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in the system memory.
Let's connect a DMA controller to Microchip PolarFire SoC.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
 hw/riscv/microchip_pfsoc.c         | 15 +++++++++++++++
 hw/riscv/Kconfig                   |  1 +
 3 files changed, 27 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 #define HW_MICROCHIP_PFSOC_H
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/dma/sifive_pdma.h"
 #include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     MchpPfSoCMMUartState *serial2;
     MchpPfSoCMMUartState *serial3;
     MchpPfSoCMMUartState *serial4;
+    SiFivePDMAState dma;
     CadenceSDHCIState sdhci;
 } MicrochipPFSoCState;
 
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_BUSERR_UNIT4,
     MICROCHIP_PFSOC_CLINT,
     MICROCHIP_PFSOC_L2CC,
+    MICROCHIP_PFSOC_DMA,
     MICROCHIP_PFSOC_L2LIM,
     MICROCHIP_PFSOC_PLIC,
     MICROCHIP_PFSOC_MMUART0,
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
+    MICROCHIP_PFSOC_DMA_IRQ0 = 5,
+    MICROCHIP_PFSOC_DMA_IRQ1 = 6,
+    MICROCHIP_PFSOC_DMA_IRQ2 = 7,
+    MICROCHIP_PFSOC_DMA_IRQ3 = 8,
+    MICROCHIP_PFSOC_DMA_IRQ4 = 9,
+    MICROCHIP_PFSOC_DMA_IRQ5 = 10,
+    MICROCHIP_PFSOC_DMA_IRQ6 = 11,
+    MICROCHIP_PFSOC_DMA_IRQ7 = 12,
     MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
     MICROCHIP_PFSOC_MMUART0_IRQ = 90,
     MICROCHIP_PFSOC_MMUART1_IRQ = 91,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 2) eNVM (Embedded Non-Volatile Memory)
  * 3) MMUARTs (Multi-Mode UART)
  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
+ * 5) SiFive Platform DMA (Direct Memory Access Controller)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
     [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
     [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
+    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,   0x100000 },
     [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
     [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
     [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
                          TYPE_RISCV_CPU_SIFIVE_U54);
     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
 
+    object_initialize_child(obj, "dma-controller", &s->dma,
+                            TYPE_SIFIVE_PDMA);
+
     object_initialize_child(obj, "sd-controller", &s->sdhci,
                             TYPE_CADENCE_SDHCI);
 }
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         memmap[MICROCHIP_PFSOC_PLIC].size);
     g_free(plic_hart_config);
 
+    /* DMA */
+    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
+                    memmap[MICROCHIP_PFSOC_DMA].base);
+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+                           qdev_get_gpio_in(DEVICE(s->plic),
+                                            MICROCHIP_PFSOC_DMA_IRQ0 + i));
+    }
+
     /* SYSREG */
     create_unimplemented_device("microchip.pfsoc.sysreg",
         memmap[MICROCHIP_PFSOC_SYSREG].base,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select SIFIVE
     select UNIMP
     select MCHP_PFSOC_MMUART
+    select SIFIVE_PDMA
     select CADENCE_SDHCI
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

At present the PHY address of the PHY connected to GEM is hard-coded
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
all boards. Add a new 'phy-addr' property so that board can specify
the PHY address for each GEM instance.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/net/cadence_gem.h | 2 ++
 hw/net/cadence_gem.c         | 5 +++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
     /* Mask of register bits which are write 1 to clear */
     uint32_t regs_w1c[CADENCE_GEM_MAXREG];
 
+    /* PHY address */
+    uint8_t phy_addr;
     /* PHY registers backing store */
     uint16_t phy_regs[32];
 
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
             uint32_t phy_addr, reg_num;
 
             phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-            if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+            if (phy_addr == s->phy_addr || phy_addr == 0) {
                 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                 retval &= 0xFFFF0000;
                 retval |= gem_phy_read(s, reg_num);
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
             uint32_t phy_addr, reg_num;
 
             phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-            if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+            if (phy_addr == s->phy_addr || phy_addr == 0) {
                 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                 gem_phy_write(s, reg_num, val);
             }
@@ -XXX,XX +XXX,XX @@ static Property gem_properties[] = {
     DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
     DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
                        GEM_MODID_VALUE),
+    DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
     DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
                       num_priority_queues, 1),
     DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

When cadence_gem model was created for Xilinx boards, the PHY address
was hard-coded to 23 in the GEM model. Now that we have introduced a
property we can use that to tell GEM model what our PHY address is.
Change all boards' GEM 'phy-addr' property value to 23, and set the
PHY address default value to 0 in the GEM model.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/arm/xilinx_zynq.c | 1 +
 hw/arm/xlnx-versal.c | 1 +
 hw/arm/xlnx-zynqmp.c | 2 ++
 hw/net/cadence_gem.c | 6 +++---
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
         qdev_set_nic_properties(dev, nd);
     }
+    object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
     s = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(s, &error_fatal);
     sysbus_mmio_map(s, 0, base);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
             qemu_check_nic_model(nd, "cadence_gem");
             qdev_set_nic_properties(dev, nd);
         }
+        object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
         object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
                                 &error_abort);
         object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
         }
         object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
                                 &error_abort);
+        object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
+                                &error_abort);
         object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
                                 &error_abort);
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@
 #define GEM_PHYMNTNC_REG_SHIFT 18
 
 /* Marvell PHY definitions */
-#define BOARD_PHY_ADDRESS    23 /* PHY address we will emulate a device at */
+#define BOARD_PHY_ADDRESS    0 /* PHY address we will emulate a device at */
 
 #define PHY_REG_CONTROL      0
 #define PHY_REG_STATUS       1
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
             uint32_t phy_addr, reg_num;
 
             phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-            if (phy_addr == s->phy_addr || phy_addr == 0) {
+            if (phy_addr == s->phy_addr) {
                 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                 retval &= 0xFFFF0000;
                 retval |= gem_phy_read(s, reg_num);
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
             uint32_t phy_addr, reg_num;
 
             phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-            if (phy_addr == s->phy_addr || phy_addr == 0) {
+            if (phy_addr == s->phy_addr) {
                 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                 gem_phy_write(s, reg_num, val);
             }
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.

On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.

The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
must specify 2 '-nic' options from the command line in order to get
a working ethernet.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  7 ++++++
 hw/riscv/microchip_pfsoc.c         | 39 ++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
 #include "hw/dma/sifive_pdma.h"
+#include "hw/net/cadence_gem.h"
 #include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     MchpPfSoCMMUartState *serial3;
     MchpPfSoCMMUartState *serial4;
     SiFivePDMAState dma;
+    CadenceGEMState gem0;
+    CadenceGEMState gem1;
     CadenceSDHCIState sdhci;
 } MicrochipPFSoCState;
 
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_MMUART2,
     MICROCHIP_PFSOC_MMUART3,
     MICROCHIP_PFSOC_MMUART4,
+    MICROCHIP_PFSOC_GEM0,
+    MICROCHIP_PFSOC_GEM1,
     MICROCHIP_PFSOC_ENVM_CFG,
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_IOSCB_CFG,
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_DMA_IRQ5 = 10,
     MICROCHIP_PFSOC_DMA_IRQ6 = 11,
     MICROCHIP_PFSOC_DMA_IRQ7 = 12,
+    MICROCHIP_PFSOC_GEM0_IRQ = 64,
+    MICROCHIP_PFSOC_GEM1_IRQ = 70,
     MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
     MICROCHIP_PFSOC_MMUART0_IRQ = 90,
     MICROCHIP_PFSOC_MMUART1_IRQ = 91,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 3) MMUARTs (Multi-Mode UART)
  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
  * 5) SiFive Platform DMA (Direct Memory Access Controller)
+ * 6) GEM (Gigabit Ethernet MAC Controller)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR    0x20220000
 
+/* GEM version */
+#define GEM_REVISION    0x0107010c
+
 static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
+    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
+    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
     [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
     object_initialize_child(obj, "dma-controller", &s->dma,
                             TYPE_SIFIVE_PDMA);
 
+    object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
+    object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
+
     object_initialize_child(obj, "sd-controller", &s->sdhci,
                             TYPE_CADENCE_SDHCI);
 }
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     MemoryRegion *envm_data = g_new(MemoryRegion, 1);
     char *plic_hart_config;
     size_t plic_hart_config_len;
+    NICInfo *nd;
     int i;
 
     sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
         serial_hd(4));
 
+    /* GEMs */
+
+    nd = &nd_table[0];
+    if (nd->used) {
+        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+        qdev_set_nic_properties(DEVICE(&s->gem0), nd);
+    }
+    nd = &nd_table[1];
+    if (nd->used) {
+        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+        qdev_set_nic_properties(DEVICE(&s->gem1), nd);
+    }
+
+    object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
+    object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
+    sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
+                    memmap[MICROCHIP_PFSOC_GEM0].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
+
+    object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
+    object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
+    sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
+                    memmap[MICROCHIP_PFSOC_GEM1].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
+
     /* eNVM */
     memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
                            memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.

With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
(1st stage bootloader).

For detailed instructions on how to create images for the Icicle
Kit board, please check QEMU RISC-V WiKi page at:
https://wiki.qemu.org/Documentation/Platforms/RISCV

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  3 +++
 hw/riscv/microchip_pfsoc.c         | 14 ++++++++++++++
 2 files changed, 17 insertions(+)

From: Bin Meng <bin.meng@windriver.com>

At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.

Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_clint.h |  4 +++-
 target/riscv/cpu.h              |  6 ++++--
 hw/riscv/microchip_pfsoc.c      |  6 +++++-
 hw/riscv/sifive_clint.c         | 26 +++++++++++++++-----------
 hw/riscv/sifive_e.c             |  3 ++-
 hw/riscv/sifive_u.c             |  3 ++-
 hw/riscv/spike.c                |  3 ++-
 hw/riscv/virt.c                 |  3 ++-
 target/riscv/cpu_helper.c       |  4 +++-
 target/riscv/csr.c              |  4 ++--
 10 files changed, 40 insertions(+), 22 deletions(-)

diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_clint.h
+++ b/include/hw/riscv/sifive_clint.h
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
     uint32_t timecmp_base;
     uint32_t time_base;
     uint32_t aperture_size;
+    uint32_t timebase_freq;
 } SiFiveCLINTState;
 
 DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
     uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
-    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
+    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
+    bool provide_rdtime);
 
 enum {
     SIFIVE_SIP_BASE     = 0x0,
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     pmp_table_t pmp_state;
 
     /* machine specific rdtime callback */
-    uint64_t (*rdtime_fn)(void);
+    uint64_t (*rdtime_fn)(uint32_t);
+    uint32_t rdtime_fn_arg;
 
     /* True if in debugger mode.  */
     bool debugger;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+                             uint32_t arg);
 #endif
 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR    0x20220000
 
+/* CLINT timebase frequency */
+#define CLINT_TIMEBASE_FREQ 1000000
+
 /* GEM version */
 #define GEM_REVISION    0x0107010c
 
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     /* CLINT */
     sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
         memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
-        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        CLINT_TIMEBASE_FREQ, false);
 
     /* L2 cache controller */
     create_unimplemented_device("microchip.pfsoc.l2cc",
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/sifive_clint.h"
 #include "qemu/timer.h"
 
-static uint64_t cpu_riscv_read_rtc(void)
+static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
 {
     return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
-        SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
+        timebase_freq, NANOSECONDS_PER_SECOND);
 }
 
 /*
  * Called when timecmp is written to update the QEMU timer or immediately
  * trigger timer interrupt if mtimecmp <= current timer value.
  */
-static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
+static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
+                                       uint32_t timebase_freq)
 {
     uint64_t next;
     uint64_t diff;
 
-    uint64_t rtc_r = cpu_riscv_read_rtc();
+    uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
 
     cpu->env.timecmp = value;
     if (cpu->env.timecmp <= rtc_r) {
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
     diff = cpu->env.timecmp - rtc_r;
     /* back to ns (note args switched in muldiv64) */
     next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
-        muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
+        muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
     timer_mod(cpu->env.timer, next);
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
         }
     } else if (addr == clint->time_base) {
         /* time_lo */
-        return cpu_riscv_read_rtc() & 0xFFFFFFFF;
+        return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF;
     } else if (addr == clint->time_base + 4) {
         /* time_hi */
-        return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
+        return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF;
     }
 
     error_report("clint: invalid read: %08x", (uint32_t)addr);
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
             /* timecmp_lo */
             uint64_t timecmp_hi = env->timecmp >> 32;
             sifive_clint_write_timecmp(RISCV_CPU(cpu),
-                timecmp_hi << 32 | (value & 0xFFFFFFFF));
+                timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq);
             return;
         } else if ((addr & 0x7) == 4) {
             /* timecmp_hi */
             uint64_t timecmp_lo = env->timecmp;
             sifive_clint_write_timecmp(RISCV_CPU(cpu),
-                value << 32 | (timecmp_lo & 0xFFFFFFFF));
+                value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq);
         } else {
             error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
         }
@@ -XXX,XX +XXX,XX @@ static Property sifive_clint_properties[] = {
     DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
     DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
     DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
+    DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types)
  */
 DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
     uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
-    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
+    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
+    bool provide_rdtime)
 {
     int i;
     for (i = 0; i < num_harts; i++) {
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
             continue;
         }
         if (provide_rdtime) {
-            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
+            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
         }
         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                   &sifive_clint_timer_cb, cpu);
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
     qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
     qdev_prop_set_uint32(dev, "time-base", time_base);
     qdev_prop_set_uint32(dev, "aperture-size", size);
+    qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     return dev;
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
         memmap[SIFIVE_E_PLIC].size);
     sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
         memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
-        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
     create_unimplemented_device("riscv.sifive.e.aon",
         memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
     sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
         memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
-        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
         return;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         sifive_clint_create(
             memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
             memmap[SPIKE_CLINT].size, base_hartid, hart_count,
-            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+            SIFIVE_CLINT_TIMEBASE_FREQ, false);
     }
 
     /* register system main memory (actual RAM) */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         sifive_clint_create(
             memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
             memmap[VIRT_CLINT].size, base_hartid, hart_count,
-            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+            SIFIVE_CLINT_TIMEBASE_FREQ, true);
 
         /* Per-socket PLIC hart topology configuration string */
         plic_hart_config_len =
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
     return old;
 }
 
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+                             uint32_t arg)
 {
     env->rdtime_fn = fn;
+    env->rdtime_fn_arg = arg;
 }
 
 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
         return -RISCV_EXCP_ILLEGAL_INST;
     }
 
-    *val = env->rdtime_fn() + delta;
+    *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
         return -RISCV_EXCP_ILLEGAL_INST;
     }
 
-    *val = (env->rdtime_fn() + delta) >> 32;
+    *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
     return 0;
 }
 #endif
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_u.h | 11 +++++++++++
 hw/riscv/sifive_u.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig            |  1 +
 3 files changed, 42 insertions(+)

diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@
 #ifndef HW_SIFIVE_U_H
 #define HW_SIFIVE_U_H
 
+#include "hw/dma/sifive_pdma.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUSoCState {
     SiFiveUPRCIState prci;
     SIFIVEGPIOState gpio;
     SiFiveUOTPState otp;
+    SiFivePDMAState dma;
     CadenceGEMState gem;
 
     uint32_t serial;
@@ -XXX,XX +XXX,XX @@ enum {
     SIFIVE_U_MROM,
     SIFIVE_U_CLINT,
     SIFIVE_U_L2CC,
+    SIFIVE_U_PDMA,
     SIFIVE_U_L2LIM,
     SIFIVE_U_PLIC,
     SIFIVE_U_PRCI,
@@ -XXX,XX +XXX,XX @@ enum {
     SIFIVE_U_GPIO_IRQ13 = 20,
     SIFIVE_U_GPIO_IRQ14 = 21,
     SIFIVE_U_GPIO_IRQ15 = 22,
+    SIFIVE_U_PDMA_IRQ0 = 23,
+    SIFIVE_U_PDMA_IRQ1 = 24,
+    SIFIVE_U_PDMA_IRQ2 = 25,
+    SIFIVE_U_PDMA_IRQ3 = 26,
+    SIFIVE_U_PDMA_IRQ4 = 27,
+    SIFIVE_U_PDMA_IRQ5 = 28,
+    SIFIVE_U_PDMA_IRQ6 = 29,
+    SIFIVE_U_PDMA_IRQ7 = 30,
     SIFIVE_U_GEM_IRQ = 0x35
 };
 
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
  * 4) GPIO (General Purpose Input/Output Controller)
  * 5) OTP (One-Time Programmable) memory with stored serial number
  * 6) GEM (Gigabit Ethernet Controller) and management block
+ * 7) DMA (Direct Memory Access Controller)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [SIFIVE_U_MROM] =     {     0x1000,     0xf000 },
     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
     [SIFIVE_U_L2CC] =     {  0x2010000,     0x1000 },
+    [SIFIVE_U_PDMA] =     {  0x3000000,   0x100000 },
     [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
     [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
     g_free(nodename);
 
+    nodename = g_strdup_printf("/soc/dma@%lx",
+        (long)memmap[SIFIVE_U_PDMA].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+        SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
+        SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
+        SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
+    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+    qemu_fdt_setprop_cells(fdt, nodename, "reg",
+        0x0, memmap[SIFIVE_U_PDMA].base,
+        0x0, memmap[SIFIVE_U_PDMA].size);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible",
+                            "sifive,fu540-c000-pdma");
+    g_free(nodename);
+
     nodename = g_strdup_printf("/soc/cache-controller@%lx",
         (long)memmap[SIFIVE_U_L2CC].base);
     qemu_fdt_add_subnode(fdt, nodename);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
     object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
     object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
     object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
+    object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
 }
 
 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
                                             SIFIVE_U_GPIO_IRQ0 + i));
     }
 
+    /* PDMA */
+    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
+
+    /* Connect PDMA interrupts to the PLIC */
+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+                           qdev_get_gpio_in(DEVICE(s->plic),
+                                            SIFIVE_U_PDMA_IRQ0 + i));
+    }
+
     qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
         return;
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select CADENCE
     select HART
     select SIFIVE
+    select SIFIVE_PDMA
     select UNIMP
 
 config SPIKE
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => misc}/sifive_e_prci.h | 0
 hw/{riscv => misc}/sifive_e_prci.c         | 2 +-
 hw/riscv/sifive_e.c                        | 2 +-
 hw/misc/Kconfig                            | 3 +++
 hw/misc/meson.build                        | 3 +++
 hw/riscv/Kconfig                           | 1 +
 hw/riscv/meson.build                       | 1 -
 7 files changed, 9 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
 rename hw/{riscv => misc}/sifive_e_prci.c (99%)

diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_e_prci.h
rename to include/hw/misc/sifive_e_prci.h
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
similarity index 99%
rename from hw/riscv/sifive_e_prci.c
rename to hw/misc/sifive_e_prci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/misc/sifive_e_prci.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "hw/hw.h"
-#include "hw/riscv/sifive_e_prci.h"
+#include "hw/misc/sifive_e_prci.h"
 
 static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
-#include "hw/riscv/sifive_e_prci.h"
 #include "hw/riscv/boot.h"
+#include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
 config AVR_POWER
     bool
 
+config SIFIVE_E_PRCI
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
 # Mac devices
 softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
+# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+
 # PKUnity SoC devices
 softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
 
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_E_PRCI
     select UNIMP
 
 config SIFIVE_U
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => misc}/sifive_u_prci.h | 0
 include/hw/riscv/sifive_u.h                | 2 +-
 hw/{riscv => misc}/sifive_u_prci.c         | 2 +-
 hw/misc/Kconfig                            | 3 +++
 hw/misc/meson.build                        | 1 +
 hw/riscv/Kconfig                           | 1 +
 hw/riscv/meson.build                       | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
 rename hw/{riscv => misc}/sifive_u_prci.c (99%)

diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_u_prci.h
rename to include/hw/misc/sifive_u_prci.h
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_prci.h"
 #include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
similarity index 99%
rename from hw/riscv/sifive_u_prci.c
rename to hw/misc/sifive_u_prci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u_prci.c
+++ b/hw/misc/sifive_u_prci.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-#include "hw/riscv/sifive_u_prci.h"
+#include "hw/misc/sifive_u_prci.h"
 
 static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
 config SIFIVE_E_PRCI
     bool
 
+config SIFIVE_U_PRCI
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
 
 # PKUnity SoC devices
 softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select HART
     select SIFIVE
     select SIFIVE_PDMA
+    select SIFIVE_U_PRCI
     select UNIMP
 
 config SPIKE
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => misc}/sifive_u_otp.h | 0
 include/hw/riscv/sifive_u.h               | 2 +-
 hw/{riscv => misc}/sifive_u_otp.c         | 2 +-
 hw/misc/Kconfig                           | 3 +++
 hw/misc/meson.build                       | 1 +
 hw/riscv/Kconfig                          | 1 +
 hw/riscv/meson.build                      | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
 rename hw/{riscv => misc}/sifive_u_otp.c (99%)

diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
similarity index 100%
rename from include/hw/riscv/sifive_u_otp.h
rename to include/hw/misc/sifive_u_otp.h
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_otp.h"
 #include "hw/misc/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
similarity index 99%
rename from hw/riscv/sifive_u_otp.c
rename to hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_otp.h"
 
 static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
 config SIFIVE_E_PRCI
     bool
 
+config SIFIVE_U_OTP
+    bool
+
 config SIFIVE_U_PRCI
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
 
 # PKUnity SoC devices
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select HART
     select SIFIVE
     select SIFIVE_PDMA
+    select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
 
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.

Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/trace.h                         | 1 -
 include/hw/{riscv => gpio}/sifive_gpio.h | 0
 include/hw/riscv/sifive_e.h              | 2 +-
 include/hw/riscv/sifive_u.h              | 2 +-
 hw/{riscv => gpio}/sifive_gpio.c         | 2 +-
 hw/gpio/Kconfig                          | 3 +++
 hw/gpio/meson.build                      | 1 +
 hw/gpio/trace-events                     | 6 ++++++
 hw/riscv/Kconfig                         | 2 ++
 hw/riscv/meson.build                     | 1 -
 hw/riscv/trace-events                    | 7 -------
 meson.build                              | 1 -
 12 files changed, 15 insertions(+), 13 deletions(-)
 delete mode 100644 hw/riscv/trace.h
 rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
 rename hw/{riscv => gpio}/sifive_gpio.c (99%)
 delete mode 100644 hw/riscv/trace-events

diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/hw/riscv/trace.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "trace/trace-hw_riscv.h"
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
similarity index 100%
rename from include/hw/riscv/sifive_gpio.h
rename to include/hw/gpio/sifive_gpio.h
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 
 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
 #define RISCV_E_SOC(obj) \
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 #include "hw/misc/sifive_u_otp.h"
 #include "hw/misc/sifive_u_prci.h"
 
diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
similarity index 99%
rename from hw/riscv/sifive_gpio.c
rename to hw/gpio/sifive_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/gpio/sifive_gpio.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 #include "migration/vmstate.h"
 #include "trace.h"
 
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -XXX,XX +XXX,XX @@ config PL061
 
 config GPIO_KEY
     bool
+
+config SIFIVE_GPIO
+    bool
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
 nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+
+# sifive_gpio.c
+sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_GPIO
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select CADENCE
     select HART
     select SIFIVE
+    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/hw/riscv/trace-events
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# See docs/devel/tracing.txt for syntax documentation.
-
-# hw/gpio/sifive_gpio.c
-sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
-sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
-sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
     'hw/watchdog',
     'hw/xen',
     'hw/gpio',
-    'hw/riscv',
     'migration',
     'net',
     'ui',
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => intc}/sifive_clint.h | 0
 hw/{riscv => intc}/sifive_clint.c         | 2 +-
 hw/riscv/microchip_pfsoc.c                | 2 +-
 hw/riscv/sifive_e.c                       | 2 +-
 hw/riscv/sifive_u.c                       | 2 +-
 hw/riscv/spike.c                          | 2 +-
 hw/riscv/virt.c                           | 2 +-
 hw/intc/Kconfig                           | 3 +++
 hw/intc/meson.build                       | 1 +
 hw/riscv/Kconfig                          | 5 +++++
 hw/riscv/meson.build                      | 1 -
 11 files changed, 15 insertions(+), 7 deletions(-)
 rename include/hw/{riscv => intc}/sifive_clint.h (100%)
 rename hw/{riscv => intc}/sifive_clint.c (99%)

diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
similarity index 100%
rename from include/hw/riscv/sifive_clint.h
rename to include/hw/intc/sifive_clint.h
diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
similarity index 99%
rename from hw/riscv/sifive_clint.c
rename to hw/intc/sifive_clint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/intc/sifive_clint.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "target/riscv/cpu.h"
 #include "hw/qdev-properties.h"
-#include "hw/riscv/sifive_clint.h"
+#include "hw/intc/sifive_clint.h"
 #include "qemu/timer.h"
 
 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
+#include "hw/intc/sifive_clint.h"
 #include "sysemu/sysemu.h"
 
 /*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
+#include "hw/intc/sifive_clint.h"
 #include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "net/eth.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_htif.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/spike.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config RX_ICU
 
 config LOONGSON_LIOINTC
     bool
+
+config SIFIVE_CLINT
+    bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
 specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
 specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
 specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
 specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_E_PRCI
     select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select CADENCE
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_U_OTP
@@ -XXX,XX +XXX,XX @@ config SPIKE
     select HART
     select HTIF
     select SIFIVE
+    select SIFIVE_CLINT
 
 config OPENTITAN
     bool
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
     select SIFIVE
+    select SIFIVE_CLINT
 
 config MICROCHIP_PFSOC
     bool
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select UNIMP
     select MCHP_PFSOC_MMUART
     select SIFIVE_PDMA
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 {include/hw/riscv => hw/intc}/sifive_plic.h | 0
 hw/{riscv => intc}/sifive_plic.c            | 2 +-
 hw/riscv/microchip_pfsoc.c                  | 2 +-
 hw/riscv/sifive_e.c                         | 2 +-
 hw/riscv/sifive_u.c                         | 2 +-
 hw/riscv/virt.c                             | 2 +-
 hw/intc/Kconfig                             | 3 +++
 hw/intc/meson.build                         | 1 +
 hw/riscv/Kconfig                            | 5 +++++
 hw/riscv/meson.build                        | 1 -
 10 files changed, 14 insertions(+), 6 deletions(-)
 rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
 rename hw/{riscv => intc}/sifive_plic.c (99%)

diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
similarity index 100%
rename from include/hw/riscv/sifive_plic.h
rename to hw/intc/sifive_plic.h
diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
similarity index 99%
rename from hw/riscv/sifive_plic.c
rename to hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/pci/msi.h"
 #include "hw/boards.h"
 #include "hw/qdev-properties.h"
+#include "hw/intc/sifive_plic.h"
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
-#include "hw/riscv/sifive_plic.h"
 
 #define RISCV_DEBUG_PLIC 0
 
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "sysemu/sysemu.h"
 
 /*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
 #include "net/eth.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config LOONGSON_LIOINTC
 
 config SIFIVE_CLINT
     bool
+
+config SIFIVE_PLIC
+    bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
 specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
 specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
 specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
 specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
 specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
+    select SIFIVE_PLIC
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PDMA
+    select SIFIVE_PLIC
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
@@ -XXX,XX +XXX,XX @@ config SPIKE
     select HTIF
     select SIFIVE
     select SIFIVE_CLINT
+    select SIFIVE_PLIC
 
 config OPENTITAN
     bool
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select PFLASH_CFI01
     select SIFIVE
     select SIFIVE_CLINT
+    select SIFIVE_PLIC
 
 config MICROCHIP_PFSOC
     bool
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select UNIMP
     select MCHP_PFSOC_MMUART
     select SIFIVE_PDMA
+    select SIFIVE_PLIC
     select CADENCE_SDHCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => char}/riscv_htif.h | 0
 hw/{riscv => char}/riscv_htif.c         | 2 +-
 hw/riscv/spike.c                        | 2 +-
 hw/char/Kconfig                         | 3 +++
 hw/char/meson.build                     | 1 +
 hw/riscv/Kconfig                        | 3 ---
 hw/riscv/meson.build                    | 1 -
 7 files changed, 6 insertions(+), 6 deletions(-)
 rename include/hw/{riscv => char}/riscv_htif.h (100%)
 rename hw/{riscv => char}/riscv_htif.c (99%)

diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
similarity index 100%
rename from include/hw/riscv/riscv_htif.h
rename to include/hw/char/riscv_htif.h
diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
similarity index 99%
rename from hw/riscv/riscv_htif.c
rename to hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "qemu/log.h"
 #include "hw/sysbus.h"
+#include "hw/char/riscv_htif.h"
 #include "hw/char/serial.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
-#include "hw/riscv/riscv_htif.h"
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/loader.h"
 #include "hw/sysbus.h"
 #include "target/riscv/cpu.h"
-#include "hw/riscv/riscv_htif.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/spike.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/char/riscv_htif.h"
 #include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@
 config ESCC
     bool
 
+config HTIF
+    bool
+
 config PARALLEL
     bool
     default y
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
 
+specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
 specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
 specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
 specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@
-config HTIF
-    bool
-
 config HART
     bool
 
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => char}/sifive_uart.h | 0
 hw/{riscv => char}/sifive_uart.c         | 2 +-
 hw/riscv/sifive_e.c                      | 2 +-
 hw/riscv/sifive_u.c                      | 2 +-
 hw/char/Kconfig                          | 3 +++
 hw/char/meson.build                      | 1 +
 hw/riscv/Kconfig                         | 2 ++
 hw/riscv/meson.build                     | 1 -
 8 files changed, 9 insertions(+), 4 deletions(-)
 rename include/hw/{riscv => char}/sifive_uart.h (100%)
 rename hw/{riscv => char}/sifive_uart.c (99%)

diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
similarity index 100%
rename from include/hw/riscv/sifive_uart.h
rename to include/hw/char/sifive_uart.h
diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
similarity index 99%
rename from hw/riscv/sifive_uart.c
rename to hw/char/sifive_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -XXX,XX +XXX,XX @@
 #include "chardev/char-fe.h"
 #include "hw/hw.h"
 #include "hw/irq.h"
-#include "hw/riscv/sifive_uart.h"
+#include "hw/char/sifive_uart.h"
 
 /*
  * Not yet implemented:
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
 #include "hw/misc/sifive_e_prci.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_USART
 
 config MCHP_PFSOC_MMUART
     bool
+
+config SIFIVE_UART
+    bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
 softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
 softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PLIC
+    select SIFIVE_UART
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
+    select SIFIVE_UART
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => misc}/sifive_test.h | 0
 hw/{riscv => misc}/sifive_test.c         | 2 +-
 hw/riscv/virt.c                          | 2 +-
 hw/misc/Kconfig                          | 3 +++
 hw/misc/meson.build                      | 1 +
 hw/riscv/Kconfig                         | 1 +
 hw/riscv/meson.build                     | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_test.h (100%)
 rename hw/{riscv => misc}/sifive_test.c (98%)

diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
similarity index 100%
rename from include/hw/riscv/sifive_test.h
rename to include/hw/misc/sifive_test.h
diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
similarity index 98%
rename from hw/riscv/sifive_test.c
rename to hw/misc/sifive_test.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/misc/sifive_test.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "sysemu/runstate.h"
 #include "hw/hw.h"
-#include "hw/riscv/sifive_test.h"
+#include "hw/misc/sifive_test.h"
 
 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
+#include "hw/misc/sifive_test.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
 config AVR_POWER
     bool
 
+config SIFIVE_TEST
+    bool
+
 config SIFIVE_E_PRCI
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
 softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_PLIC
+    select SIFIVE_TEST
 
 config MICROCHIP_PFSOC
     bool
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Every RISC-V machine needs riscv_hart hence there is no need to
have a dedicated Kconfig option for it. Drop the Kconfig option
and always build riscv_hart.c.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/Kconfig     | 9 ---------
 hw/riscv/meson.build | 2 +-
 2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@
-config HART
-    bool
-
 config IBEX
     bool
 
@@ -XXX,XX +XXX,XX @@ config SIFIVE
 
 config SIFIVE_E
     bool
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
 config SIFIVE_U
     bool
     select CADENCE
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
 
 config SPIKE
     bool
-    select HART
     select HTIF
     select SIFIVE
     select SIFIVE_CLINT
@@ -XXX,XX +XXX,XX @@ config SPIKE
 config OPENTITAN
     bool
     select IBEX
-    select HART
     select UNIMP
 
 config RISCV_VIRT
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     imply PCI_DEVICES
     imply TEST_DEVICES
     select PCI
-    select HART
     select SERIAL
     select GOLDFISH_RTC
     select VIRTIO_MMIO
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
 
 config MICROCHIP_PFSOC
     bool
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
 riscv_ss = ss.source_set()
 riscv_ss.add(files('boot.c'), fdt)
 riscv_ss.add(files('numa.c'))
-riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
+riscv_ss.add(files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

The name SIFIVE is too vague to convey the required component of
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
each machine instead.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/Kconfig | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

From: Bin Meng <bin.meng@windriver.com>

At present the Kconfig file is in disorder. Let's sort the options.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/Kconfig | 58 ++++++++++++++++++++++++------------------------
 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@
 config IBEX
     bool
 
-config SIFIVE_E
-    bool
-    select MSI_NONBROKEN
-    select SIFIVE_CLINT
-    select SIFIVE_GPIO
-    select SIFIVE_PLIC
-    select SIFIVE_UART
-    select SIFIVE_E_PRCI
-    select UNIMP
-
-config SIFIVE_U
+config MICROCHIP_PFSOC
     bool
-    select CADENCE
+    select CADENCE_SDHCI
+    select MCHP_PFSOC_MMUART
     select MSI_NONBROKEN
     select SIFIVE_CLINT
-    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
-    select SIFIVE_UART
-    select SIFIVE_U_OTP
-    select SIFIVE_U_PRCI
     select UNIMP
 
-config SPIKE
-    bool
-    select HTIF
-    select MSI_NONBROKEN
-    select SIFIVE_CLINT
-    select SIFIVE_PLIC
-
 config OPENTITAN
     bool
     select IBEX
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     bool
     imply PCI_DEVICES
     imply TEST_DEVICES
+    select GOLDFISH_RTC
     select MSI_NONBROKEN
     select PCI
-    select SERIAL
-    select GOLDFISH_RTC
-    select VIRTIO_MMIO
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
+    select SERIAL
     select SIFIVE_CLINT
     select SIFIVE_PLIC
     select SIFIVE_TEST
+    select VIRTIO_MMIO
 
-config MICROCHIP_PFSOC
+config SIFIVE_E
     bool
     select MSI_NONBROKEN
     select SIFIVE_CLINT
+    select SIFIVE_GPIO
+    select SIFIVE_PLIC
+    select SIFIVE_UART
+    select SIFIVE_E_PRCI
     select UNIMP
-    select MCHP_PFSOC_MMUART
+
+config SIFIVE_U
+    bool
+    select CADENCE
+    select MSI_NONBROKEN
+    select SIFIVE_CLINT
+    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
-    select CADENCE_SDHCI
+    select SIFIVE_UART
+    select SIFIVE_U_OTP
+    select SIFIVE_U_PRCI
+    select UNIMP
+
+config SPIKE
+    bool
+    select HTIF
+    select MSI_NONBROKEN
+    select SIFIVE_CLINT
+    select SIFIVE_PLIC
-- 
2.28.0

The following changes since commit 8032c78e556cd0baec111740a6c636863f9bd7c8:

Merge tag 'firmware-20241216-pull-request' of https://gitlab.com/kraxel/qemu into staging (2024-12-16 14:20:33 -0500)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241219-1

for you to fetch changes up to 5632d271be16b5e769342d54198c4359658abcb7:

target/riscv: add support for RV64 Xiangshan Nanhu CPU (2024-12-18 11:07:59 +1000)

----------------------------------------------------------------
RISC-V PR for 10.0

* Correct the validness check of iova
* Fix APLIC in_clrip and clripnum write emulation
* Support riscv-iommu-sys device
* Add Tenstorrent Ascalon CPU
* Add AIA userspace irqchip_split support
* Add Microblaze V generic board
* Upgrade ACPI SPCR table to support SPCR table revision 4 format
* Remove tswap64() calls from HTIF
* Support 64-bit address of initrd
* Introduce svukte ISA extension
* Support ssstateen extension
* Support for RV64 Xiangshan Nanhu CPU

----------------------------------------------------------------
Anton Blanchard (1):
      target/riscv: Add Tenstorrent Ascalon CPU

Daniel Henrique Barboza (15):
      hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init()
      hw/riscv/riscv-iommu: parametrize CAP.IGS
      hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support
      hw/riscv/riscv-iommu: implement reset protocol
      docs/specs: add riscv-iommu-sys information
      hw/intc/riscv_aplic: rename is_kvm_aia()
      hw/riscv/virt.c: reduce virt_use_kvm_aia() usage
      hw/riscv/virt.c: rename helper to virt_use_kvm_aia_aplic_imsic()
      target/riscv/kvm: consider irqchip_split() in aia_create()
      hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers
      hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic
      target/riscv/kvm: remove irqchip_split() restriction
      docs: update riscv/virt.rst with kernel-irqchip=split support
      target/riscv/tcg: hide warn for named feats when disabling via priv_ver
      target/riscv: add ssstateen

Fea.Wang (6):
      target/riscv: Add svukte extension capability variable
      target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
      target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
      target/riscv: Check memory access to meet svukte rule
      target/riscv: Expose svukte ISA extension
      target/riscv: Check svukte is not enabled in RV32

Jason Chien (1):
      hw/riscv/riscv-iommu.c: Correct the validness check of iova

Jim Shu (3):
      hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
      hw/riscv: Add a new struct RISCVBootInfo
      hw/riscv: Add the checking if DTB overlaps to kernel or initrd

MollyChen (1):
      target/riscv: add support for RV64 Xiangshan Nanhu CPU

Philippe Mathieu-Daudé (5):
      MAINTAINERS: Cover RISC-V HTIF interface
      hw/char/riscv_htif: Explicit little-endian implementation
      hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses
      target/riscv: Include missing headers in 'vector_internals.h'
      target/riscv: Include missing headers in 'internals.h'

Sai Pavan Boddu (1):
      hw/riscv: Add Microblaze V generic board

Sia Jee Heng (3):
      qtest: allow SPCR acpi table changes
      hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
      tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V

Sunil V L (1):
      hw/riscv/virt: Add IOMMU as platform device if the option is set

Tomasz Jeznach (1):
      hw/riscv: add riscv-iommu-sys platform device

Yong-Xuan Wang (1):
      hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation

From: Jason Chien <jason.chien@sifive.com>

From RISCV IOMMU spec section 2.1.3:
When SXL is 1, the following rules apply:
- If the first-stage is not Bare, then a page fault corresponding to the
original access type occurs if the IOVA has bits beyond bit 31 set to 1.
- If the second-stage is not Bare, then a guest page fault corresponding
to the original access type occurs if the incoming GPA has bits beyond bit
33 set to 1.

From RISCV IOMMU spec section 2.3 step 17:
Use the process specified in Section "Two-Stage Address Translation" of
the RISC-V Privileged specification to determine the GPA accessed by the
transaction.

From RISCV IOMMU spec section 2.3 step 19:
Use the second-stage address translation process specified in Section
"Two-Stage Address Translation" of the RISC-V Privileged specification
to translate the GPA A to determine the SPA accessed by the transaction.

This commit adds the iova check with the following rules:
- For Sv32, Sv32x4, Sv39x4, Sv48x4 and Sv57x4, the iova must be zero
extended.
- For Sv39, Sv48 and Sv57, the iova must be signed extended with most
significant bit.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241114065617.25133-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/riscv-iommu.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -XXX,XX +XXX,XX @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
 
         /* Address range check before first level lookup */
         if (!sc[pass].step) {
-            const uint64_t va_mask = (1ULL << (va_skip + va_bits)) - 1;
-            if ((addr & va_mask) != addr) {
-                return RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED;
+            const uint64_t va_len = va_skip + va_bits;
+            const uint64_t va_mask = (1ULL << va_len) - 1;
+
+            if (pass == S_STAGE && va_len > 32) {
+                target_ulong mask, masked_msbs;
+
+                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
+                masked_msbs = (addr >> (va_len - 1)) & mask;
+
+                if (masked_msbs != 0 && masked_msbs != mask) {
+                    return (iotlb->perm & IOMMU_WO) ?
+                                RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S :
+                                RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S;
+                }
+            } else {
+                if ((addr & va_mask) != addr) {
+                    return (iotlb->perm & IOMMU_WO) ?
+                                RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS :
+                                RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS;
+                }
             }
         }
 
-- 
2.47.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:

"If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit is cleared whenever the rectified input value is
low, when the interrupt is forwarded by MSI, or by a relevant
write to an in_clrip register or to clripnum."

Update the riscv_aplic_set_pending() to match the spec.

Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode")
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241029085349.30412-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
 
     if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
         (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
-        if (!aplic->msimode || (aplic->msimode && !pending)) {
+        if (!aplic->msimode) {
             return;
         }
+        if (aplic->msimode && !pending) {
+            goto noskip_write_pending;
+        }
         if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
             (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
             return;
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
         }
     }
 
+noskip_write_pending:
     riscv_aplic_set_pending_raw(aplic, irq, pending);
 }
 
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Move all the static initializion of the device to an init() function,
leaving only the dynamic initialization to be done during realize.

With this change s->cap is initialized with RISCV_IOMMU_CAP_DBG during
init(), and realize() will increment s->cap with the extra caps.

This will allow callers to add IOMMU capabilities before the
realization.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/riscv-iommu.c | 71 +++++++++++++++++++++++-------------------
 1 file changed, 39 insertions(+), 32 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps riscv_iommu_trap_ops = {
     }
 };
 
+static void riscv_iommu_instance_init(Object *obj)
+{
+    RISCVIOMMUState *s = RISCV_IOMMU(obj);
+
+    /* Enable translation debug interface */
+    s->cap = RISCV_IOMMU_CAP_DBG;
+
+    /* Report QEMU target physical address space limits */
+    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
+                       TARGET_PHYS_ADDR_SPACE_BITS);
+
+    /* TODO: method to report supported PID bits */
+    s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
+    s->cap |= RISCV_IOMMU_CAP_PD8;
+
+    /* register storage */
+    s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+    s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+    s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
+
+     /* Mark all registers read-only */
+    memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
+
+    /* Device translation context cache */
+    s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
+                                         riscv_iommu_ctx_equal,
+                                         g_free, NULL);
+
+    s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash,
+                                         riscv_iommu_iot_equal,
+                                         g_free, NULL);
+
+    s->iommus.le_next = NULL;
+    s->iommus.le_prev = NULL;
+    QLIST_INIT(&s->spaces);
+}
+
 static void riscv_iommu_realize(DeviceState *dev, Error **errp)
 {
     RISCVIOMMUState *s = RISCV_IOMMU(dev);
 
-    s->cap = s->version & RISCV_IOMMU_CAP_VERSION;
+    s->cap |= s->version & RISCV_IOMMU_CAP_VERSION;
     if (s->enable_msi) {
         s->cap |= RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF;
     }
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
         s->cap |= RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 |
                   RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
     }
-    /* Enable translation debug interface */
-    s->cap |= RISCV_IOMMU_CAP_DBG;
-
-    /* Report QEMU target physical address space limits */
-    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,
-                       TARGET_PHYS_ADDR_SPACE_BITS);
-
-    /* TODO: method to report supported PID bits */
-    s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */
-    s->cap |= RISCV_IOMMU_CAP_PD8;
 
     /* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough) */
     s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ?
                         RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE);
 
-    /* register storage */
-    s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
-    s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
-    s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE);
-
-     /* Mark all registers read-only */
-    memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE);
-
     /*
      * Register complete MMIO space, including MSI/PBA registers.
      * Note, PCIDevice implementation will add overlapping MR for MSI/PBA,
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
     memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops, s,
             "riscv-iommu-trap", ~0ULL);
     address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as");
-
-    /* Device translation context cache */
-    s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash,
-                                         riscv_iommu_ctx_equal,
-                                         g_free, NULL);
-
-    s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash,
-                                         riscv_iommu_iot_equal,
-                                         g_free, NULL);
-
-    s->iommus.le_next = NULL;
-    s->iommus.le_prev = NULL;
-    QLIST_INIT(&s->spaces);
 }
 
 static void riscv_iommu_unrealize(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_iommu_info = {
     .name = TYPE_RISCV_IOMMU,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(RISCVIOMMUState),
+    .instance_init = riscv_iommu_instance_init,
     .class_init = riscv_iommu_class_init,
 };
 
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Interrupt Generation Support (IGS) is a capability that is tied to the
interrupt deliver mechanism, not with the core IOMMU emulation. We
should allow device implementations to set IGS as they wish.

A new helper is added to make it easier for device impls to set IGS. Use
it in our existing IOMMU device (riscv-iommu-pci) to set
RISCV_IOMMU_CAPS_IGS_MSI.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/riscv-iommu-bits.h | 6 ++++++
 hw/riscv/riscv-iommu.h      | 4 ++++
 hw/riscv/riscv-iommu-pci.c  | 1 +
 hw/riscv/riscv-iommu.c      | 5 +++++
 4 files changed, 16 insertions(+)

diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu-bits.h
+++ b/hw/riscv/riscv-iommu-bits.h
@@ -XXX,XX +XXX,XX @@ struct riscv_iommu_pq_record {
 #define RISCV_IOMMU_CAP_PD17            BIT_ULL(39)
 #define RISCV_IOMMU_CAP_PD20            BIT_ULL(40)
 
+enum riscv_iommu_igs_modes {
+    RISCV_IOMMU_CAP_IGS_MSI = 0,
+    RISCV_IOMMU_CAP_IGS_WSI,
+    RISCV_IOMMU_CAP_IGS_BOTH
+};
+
 /* 5.4 Features control register (32bits) */
 #define RISCV_IOMMU_REG_FCTL            0x0008
 #define RISCV_IOMMU_FCTL_BE             BIT(0)
diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu.h
+++ b/hw/riscv/riscv-iommu.h
@@ -XXX,XX +XXX,XX @@
 
 #include "qom/object.h"
 #include "hw/riscv/iommu.h"
+#include "hw/riscv/riscv-iommu-bits.h"
+
+typedef enum riscv_iommu_igs_modes riscv_iommu_igs_mode;
 
 struct RISCVIOMMUState {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
 
 void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
          Error **errp);
+void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode);
 
 /* private helpers */
 
diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu-pci.c
+++ b/hw/riscv/riscv-iommu-pci.c
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_pci_init(Object *obj)
     qdev_alias_all_properties(DEVICE(iommu), obj);
 
     iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;
+    riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI);
 }
 
 static const Property riscv_iommu_pci_properties[] = {
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps riscv_iommu_trap_ops = {
     }
 };
 
+void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode)
+{
+    s->cap = set_field(s->cap, RISCV_IOMMU_CAP_IGS, mode);
+}
+
 static void riscv_iommu_instance_init(Object *obj)
 {
     RISCVIOMMUState *s = RISCV_IOMMU(obj);
-- 
2.47.1

From: Tomasz Jeznach <tjeznach@rivosinc.com>

This device models the RISC-V IOMMU as a sysbus device. The same design
decisions taken in the riscv-iommu-pci device were kept, namely the
existence of 4 vectors are available for each interrupt cause.

The WSIs are emitted using the input of the s->notify() callback as a
index to an IRQ list. The IRQ list starts at 'base_irq' and goes until
base_irq + 3. This means that boards must have 4 contiguous IRQ lines
available, starting from 'base_irq'.

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/iommu.h   |   4 ++
 hw/riscv/riscv-iommu-sys.c | 128 +++++++++++++++++++++++++++++++++++++
 hw/riscv/riscv-iommu.c     |   3 +-
 hw/riscv/meson.build       |   2 +-
 4 files changed, 134 insertions(+), 3 deletions(-)
 create mode 100644 hw/riscv/riscv-iommu-sys.c

From: Sunil V L <sunilvl@ventanamicro.com>

Add a new machine option called 'iommu-sys' that enables a
riscv-iommu-sys platform device for the 'virt' machine. The option is
default 'off'.

The device will use IRQs 36 to 39.

We will not support both riscv-iommu-sys and riscv-iommu-pci devices in
the same board in this first implementation. If a riscv-iommu-pci device
is added in the command line we will disable the riscv-iommu-sys device.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/iommu.h |   2 +
 include/hw/riscv/virt.h  |   6 ++-
 hw/riscv/virt.c          | 104 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 109 insertions(+), 3 deletions(-)

diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/iommu.h
+++ b/include/hw/riscv/iommu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
 OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
 typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
 
+#define FDT_IRQ_TYPE_EDGE_LOW 1
+
 #endif
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@ struct RISCVVirtState {
     OnOffAuto acpi;
     const MemMapEntry *memmap;
     struct GPEXHost *gpex_host;
+    OnOffAuto iommu_sys;
 };
 
 enum {
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PCIE_MMIO,
     VIRT_PCIE_PIO,
     VIRT_PLATFORM_BUS,
-    VIRT_PCIE_ECAM
+    VIRT_PCIE_ECAM,
+    VIRT_IOMMU_SYS,
 };
 
 enum {
@@ -XXX,XX +XXX,XX @@ enum {
     VIRTIO_IRQ = 1, /* 1 to 8 */
     VIRTIO_COUNT = 8,
     PCIE_IRQ = 0x20, /* 32 to 35 */
+    IOMMU_SYS_IRQ = 0x24, /* 36-39 */
     VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
 };
 
@@ -XXX,XX +XXX,XX @@ enum {
                                  1 + FDT_APLIC_INT_CELLS)
 
 bool virt_is_acpi_enabled(RISCVVirtState *s);
+bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
 void virt_acpi_setup(RISCVVirtState *vms);
 uint32_t imsic_num_bits(uint32_t count);
 
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/pmu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/iommu.h"
+#include "hw/riscv/riscv-iommu-bits.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry virt_memmap[] = {
     [VIRT_CLINT] =        {  0x2000000,       0x10000 },
     [VIRT_ACLINT_SSWI] =  {  0x2F00000,        0x4000 },
     [VIRT_PCIE_PIO] =     {  0x3000000,       0x10000 },
+    [VIRT_IOMMU_SYS] =    {  0x3010000,        0x1000 },
     [VIRT_PLATFORM_BUS] = {  0x4000000,     0x2000000 },
     [VIRT_PLIC] =         {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_APLIC_M] =      {  0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
 
 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
                             uint32_t irq_pcie_phandle,
-                            uint32_t msi_pcie_phandle)
+                            uint32_t msi_pcie_phandle,
+                            uint32_t iommu_sys_phandle)
 {
     g_autofree char *name = NULL;
     MachineState *ms = MACHINE(s);
@@ -XXX,XX +XXX,XX @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
         2, virt_high_pcie_memmap.base,
         2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
 
+    if (virt_is_iommu_sys_enabled(s)) {
+        qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map",
+                               0, iommu_sys_phandle, 0, 0, 0,
+                               iommu_sys_phandle, 0, 0xffff);
+    }
+
     create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle);
 }
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
                            bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf);
 }
 
+static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
+                                 uint32_t *iommu_sys_phandle)
+{
+    const char comp[] = "riscv,iommu";
+    void *fdt = MACHINE(s)->fdt;
+    uint32_t iommu_phandle;
+    g_autofree char *iommu_node = NULL;
+    hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base;
+    hwaddr size = s->memmap[VIRT_IOMMU_SYS].size;
+    uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = {
+        IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ,
+        IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ,
+        IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM,
+        IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ,
+    };
+
+    iommu_node = g_strdup_printf("/soc/iommu@%x",
+                               (unsigned int) s->memmap[VIRT_IOMMU_SYS].base);
+    iommu_phandle = qemu_fdt_alloc_phandle(fdt);
+    qemu_fdt_add_subnode(fdt, iommu_node);
+
+    qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp));
+    qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
+    qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
+
+    qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
+                           addr >> 32, addr, size >> 32, size);
+    qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
+
+    qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",
+        iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW,
+        iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW,
+        iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
+        iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
+
+    *iommu_sys_phandle = iommu_phandle;
+}
+
 static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf)
 {
     const char comp[] = "riscv,pci-iommu";
@@ -XXX,XX +XXX,XX @@ static void finalize_fdt(RISCVVirtState *s)
 {
     uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
     uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
+    uint32_t iommu_sys_phandle = 1;
 
     create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle,
                        &irq_pcie_phandle, &irq_virtio_phandle,
@@ -XXX,XX +XXX,XX @@ static void finalize_fdt(RISCVVirtState *s)
 
     create_fdt_virtio(s, virt_memmap, irq_virtio_phandle);
 
-    create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle);
+    if (virt_is_iommu_sys_enabled(s)) {
+        create_fdt_iommu_sys(s, irq_mmio_phandle, &iommu_sys_phandle);
+    }
+    create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle,
+                    iommu_sys_phandle);
 
     create_fdt_reset(s, virt_memmap, &phandle);
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         create_fdt(s, memmap);
     }
 
+    if (virt_is_iommu_sys_enabled(s)) {
+        DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS);
+
+        object_property_set_uint(OBJECT(iommu_sys), "addr",
+                                 s->memmap[VIRT_IOMMU_SYS].base,
+                                 &error_fatal);
+        object_property_set_uint(OBJECT(iommu_sys), "base-irq",
+                                 IOMMU_SYS_IRQ,
+                                 &error_fatal);
+        object_property_set_link(OBJECT(iommu_sys), "irqchip",
+                                 OBJECT(mmio_irqchip),
+                                 &error_fatal);
+
+        sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);
+    }
+
     s->machine_done.notify = virt_machine_done;
     qemu_add_machine_init_done_notifier(&s->machine_done);
 }
@@ -XXX,XX +XXX,XX @@ static void virt_machine_instance_init(Object *obj)
     s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
     s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
     s->acpi = ON_OFF_AUTO_AUTO;
+    s->iommu_sys = ON_OFF_AUTO_AUTO;
 }
 
 static char *virt_get_aia_guests(Object *obj, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void virt_set_aclint(Object *obj, bool value, Error **errp)
     s->have_aclint = value;
 }
 
+bool virt_is_iommu_sys_enabled(RISCVVirtState *s)
+{
+    return s->iommu_sys == ON_OFF_AUTO_ON;
+}
+
+static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+    OnOffAuto iommu_sys = s->iommu_sys;
+
+    visit_type_OnOffAuto(v, name, &iommu_sys, errp);
+}
+
+static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
+
+    visit_type_OnOffAuto(v, name, &s->iommu_sys, errp);
+}
+
 bool virt_is_acpi_enabled(RISCVVirtState *s)
 {
     return s->acpi != ON_OFF_AUTO_OFF;
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
                                                         DeviceState *dev)
 {
     MachineClass *mc = MACHINE_GET_CLASS(machine);
+    RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
 
     if (device_is_dynamic_sysbus(mc, dev) ||
         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
         object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
+        s->iommu_sys = ON_OFF_AUTO_OFF;
         return HOTPLUG_HANDLER(machine);
     }
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
 
     if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) {
         create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev)));
+        s->iommu_sys = ON_OFF_AUTO_OFF;
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
                               NULL, NULL);
     object_class_property_set_description(oc, "acpi",
                                           "Enable ACPI");
+
+    object_class_property_add(oc, "iommu-sys", "OnOffAuto",
+                              virt_get_iommu_sys, virt_set_iommu_sys,
+                              NULL, NULL);
+    object_class_property_set_description(oc, "iommu-sys",
+                                          "Enable IOMMU platform device");
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

MSIx support is added in the RISC-V IOMMU platform device by including
the required MSIx facilities to alow software to properly setup the MSIx
subsystem.

We took inspiration of what is being done in the riscv-iommu-pci device,
mainly msix_init() and msix_notify(), while keeping in mind that
riscv-iommu-sys isn't a true PCI device and we don't need to copy/paste
all the contents of these MSIx functions.

Two extra MSI MemoryRegions were added: 'msix-table' and 'msix-pba'.
They are used to manage r/w of the MSI table and Pending Bit Array (PBA)
respectively. Both are subregions of the main IOMMU memory region,
iommu->regs_mr, initialized during riscv_iommu_realize(), and each one
has their own handlers for MSIx reads and writes.

This is the expected memory map when using this device in the 'virt'
machine:

0000000003010000-0000000003010fff (prio 0, i/o): riscv-iommu-regs
      0000000003010300-000000000301034f (prio 0, i/o): msix-table
      0000000003010400-0000000003010407 (prio 0, i/o): msix-pba

We're now able to set IGS to RISCV_IOMMU_CAP_IGS_BOTH, and userspace is
free to decide which interrupt model to use.

Enabling MSIx support for this device in the 'virt' machine requires
adding 'msi-parent' in the iommu-sys DT.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/riscv-iommu-sys.c | 116 +++++++++++++++++++++++++++++++++++--
 hw/riscv/virt.c            |   6 +-
 hw/riscv/trace-events      |   2 +
 3 files changed, 119 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu-sys.c
+++ b/hw/riscv/riscv-iommu-sys.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/host-utils.h"
 #include "qemu/module.h"
 #include "qom/object.h"
+#include "exec/exec-all.h"
+#include "trace.h"
 
 #include "riscv-iommu.h"
 
 #define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333
 
+#define RISCV_IOMMU_PCI_MSIX_VECTORS 5
+
 /* RISC-V IOMMU System Platform Device Emulation */
 
 struct RISCVIOMMUStateSys {
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUStateSys {
     uint32_t         base_irq;
     DeviceState      *irqchip;
     RISCVIOMMUState  iommu;
+
+    /* Wired int support */
     qemu_irq         irqs[RISCV_IOMMU_INTR_COUNT];
+
+    /* Memory Regions for MSIX table and pending bit entries. */
+    MemoryRegion msix_table_mmio;
+    MemoryRegion msix_pba_mmio;
+    uint8_t *msix_table;
+    uint8_t *msix_pba;
+};
+
+static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
+                                     unsigned size)
+{
+    RISCVIOMMUStateSys *s = opaque;
+
+    g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE);
+    return pci_get_long(s->msix_table + addr);
+}
+
+static void msix_table_mmio_write(void *opaque, hwaddr addr,
+                                  uint64_t val, unsigned size)
+{
+    RISCVIOMMUStateSys *s = opaque;
+
+    g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE);
+    pci_set_long(s->msix_table + addr, val);
+}
+
+static const MemoryRegionOps msix_table_mmio_ops = {
+    .read = msix_table_mmio_read,
+    .write = msix_table_mmio_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 8,
+    },
+    .impl = {
+        .max_access_size = 4,
+    },
+};
+
+static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
+                                   unsigned size)
+{
+    RISCVIOMMUStateSys *s = opaque;
+
+    return pci_get_long(s->msix_pba + addr);
+}
+
+static void msix_pba_mmio_write(void *opaque, hwaddr addr,
+                                uint64_t val, unsigned size)
+{
+}
+
+static const MemoryRegionOps msix_pba_mmio_ops = {
+    .read = msix_pba_mmio_read,
+    .write = msix_pba_mmio_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 8,
+    },
+    .impl = {
+        .max_access_size = 4,
+    },
 };
 
+static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s,
+                                        uint32_t n_vectors)
+{
+    RISCVIOMMUState *iommu = &s->iommu;
+    uint32_t table_size = table_size = n_vectors * PCI_MSIX_ENTRY_SIZE;
+    uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG;
+    uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8;
+    uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256;
+
+    s->msix_table = g_malloc0(table_size);
+    s->msix_pba = g_malloc0(pba_size);
+
+    memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio_ops,
+                          s, "msix-table", table_size);
+    memory_region_add_subregion(&iommu->regs_mr, table_offset,
+                                &s->msix_table_mmio);
+
+    memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops, s,
+                          "msix-pba", pba_size);
+    memory_region_add_subregion(&iommu->regs_mr, pba_offset,
+                                &s->msix_pba_mmio);
+}
+
+static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s,
+                                        uint32_t vector)
+{
+    uint8_t *table_entry = s->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
+    uint64_t msi_addr = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
+    uint32_t msi_data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
+    MemTxResult result;
+
+    address_space_stl_le(&address_space_memory, msi_addr,
+                         msi_data, MEMTXATTRS_UNSPECIFIED, &result);
+    trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result);
+}
+
 static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu,
                                       unsigned vector)
 {
     RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu);
     uint32_t fctl =  riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL);
 
-    /* We do not support MSIs yet */
-    if (!(fctl & RISCV_IOMMU_FCTL_WSI)) {
+    if (fctl & RISCV_IOMMU_FCTL_WSI) {
+        qemu_irq_pulse(s->irqs[vector]);
+        trace_riscv_iommu_sys_irq_sent(vector);
         return;
     }
 
-    qemu_irq_pulse(s->irqs[vector]);
+    riscv_iommu_sysdev_send_MSI(s, vector);
 }
 
 static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp)
         irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i);
         sysbus_connect_irq(sysdev, i, irq);
     }
+
+    riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS);
 }
 
 static void riscv_iommu_sys_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_sys_init(Object *obj)
     qdev_alias_all_properties(DEVICE(iommu), obj);
 
     iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS;
-    riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_WSI);
+    riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH);
 }
 
 static Property riscv_iommu_sys_properties[] = {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf)
 }
 
 static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
+                                 uint32_t msi_phandle,
                                  uint32_t *iommu_sys_phandle)
 {
     const char comp[] = "riscv,iommu";
@@ -XXX,XX +XXX,XX @@ static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
         iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW,
         iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW);
 
+    qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle);
+
     *iommu_sys_phandle = iommu_phandle;
 }
 
@@ -XXX,XX +XXX,XX @@ static void finalize_fdt(RISCVVirtState *s)
     create_fdt_virtio(s, virt_memmap, irq_virtio_phandle);
 
     if (virt_is_iommu_sys_enabled(s)) {
-        create_fdt_iommu_sys(s, irq_mmio_phandle, &iommu_sys_phandle);
+        create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle,
+                             &iommu_sys_phandle);
     }
     create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle,
                     iommu_sys_phandle);
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/trace-events
+++ b/hw/riscv/trace-events
@@ -XXX,XX +XXX,XX @@ riscv_iommu_icvec_write(uint32_t orig, uint32_t actual) "ICVEC write: incoming 0
 riscv_iommu_ats(const char *id, unsigned b, unsigned d, unsigned f, uint64_t iova) "%s: translate request %04x:%02x.%u iova: 0x%"PRIx64
 riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb invalidate"
 riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group response"
+riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u"
+riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x result %u"
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add a riscv_iommu_reset() helper in the base emulation code that
implements the expected reset behavior as defined by the riscv-iommu
spec.

Devices can then use this helper in their own reset callbacks.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/riscv-iommu.h     |  1 +
 include/hw/riscv/iommu.h   |  6 ++++--
 hw/riscv/riscv-iommu-pci.c | 20 ++++++++++++++++++++
 hw/riscv/riscv-iommu-sys.c | 20 ++++++++++++++++++++
 hw/riscv/riscv-iommu.c     | 35 +++++++++++++++++++++++++++++++++++
 hw/riscv/trace-events      |  2 ++
 6 files changed, 82 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu.h
+++ b/hw/riscv/riscv-iommu.h
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUState {
 void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
          Error **errp);
 void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode);
+void riscv_iommu_reset(RISCVIOMMUState *s);
 
 /* private helpers */
 
diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/iommu.h
+++ b/include/hw/riscv/iommu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVIOMMUState RISCVIOMMUState;
 typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
 
 #define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
-OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
+OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PCI)
 typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
+typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass;
 
 #define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
-OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
+OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SYS)
 typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
+typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass;
 
 #define FDT_IRQ_TYPE_EDGE_LOW 1
 
diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu-pci.c
+++ b/hw/riscv/riscv-iommu-pci.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu_bits.h"
 #include "riscv-iommu.h"
 #include "riscv-iommu-bits.h"
+#include "trace.h"
 
 /* RISC-V IOMMU PCI Device Emulation */
 #define RISCV_PCI_CLASS_SYSTEM_IOMMU     0x0806
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVIOMMUStatePci {
     RISCVIOMMUState  iommu;   /* common IOMMU state */
 } RISCVIOMMUStatePci;
 
+struct RISCVIOMMUPciClass {
+    /*< public >*/
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
 /* interrupt delivery callback */
 static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector)
 {
@@ -XXX,XX +XXX,XX @@ static const Property riscv_iommu_pci_properties[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static void riscv_iommu_pci_reset_hold(Object *obj, ResetType type)
+{
+    RISCVIOMMUStatePci *pci = RISCV_IOMMU_PCI(obj);
+    RISCVIOMMUState *iommu = &pci->iommu;
+
+    riscv_iommu_reset(iommu);
+
+    trace_riscv_iommu_pci_reset_hold(type);
+}
+
 static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    rc->phases.hold = riscv_iommu_pci_reset_hold;
 
     k->realize = riscv_iommu_pci_realize;
     k->exit = riscv_iommu_pci_exit;
diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu-sys.c
+++ b/hw/riscv/riscv-iommu-sys.c
@@ -XXX,XX +XXX,XX @@ struct RISCVIOMMUStateSys {
     uint8_t *msix_pba;
 };
 
+struct RISCVIOMMUSysClass {
+    /*< public >*/
+    DeviceRealize parent_realize;
+    ResettablePhases parent_phases;
+};
+
 static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
                                      unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static Property riscv_iommu_sys_properties[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type)
+{
+    RISCVIOMMUStateSys *sys = RISCV_IOMMU_SYS(obj);
+    RISCVIOMMUState *iommu = &sys->iommu;
+
+    riscv_iommu_reset(iommu);
+
+    trace_riscv_iommu_sys_reset_hold(type);
+}
+
 static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+    rc->phases.hold = riscv_iommu_sys_reset_hold;
+
     dc->realize = riscv_iommu_sys_realize;
     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
     device_class_set_props(dc, riscv_iommu_sys_properties);
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_iommu_unrealize(DeviceState *dev)
     g_hash_table_unref(s->ctx_cache);
 }
 
+void riscv_iommu_reset(RISCVIOMMUState *s)
+{
+    uint32_t reg_clr;
+    int ddtp_mode;
+
+    /*
+     * Clear DDTP while setting DDTP_mode back to user
+     * initial setting.
+     */
+    ddtp_mode = s->enable_off ?
+                RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE;
+    s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, ddtp_mode);
+    riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_DDTP, s->ddtp);
+
+    reg_clr = RISCV_IOMMU_CQCSR_CQEN | RISCV_IOMMU_CQCSR_CIE |
+              RISCV_IOMMU_CQCSR_CQON | RISCV_IOMMU_CQCSR_BUSY;
+    riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, 0, reg_clr);
+
+    reg_clr = RISCV_IOMMU_FQCSR_FQEN | RISCV_IOMMU_FQCSR_FIE |
+              RISCV_IOMMU_FQCSR_FQON | RISCV_IOMMU_FQCSR_BUSY;
+    riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_FQCSR, 0, reg_clr);
+
+    reg_clr = RISCV_IOMMU_PQCSR_PQEN | RISCV_IOMMU_PQCSR_PIE |
+              RISCV_IOMMU_PQCSR_PQON | RISCV_IOMMU_PQCSR_BUSY;
+    riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, 0, reg_clr);
+
+    riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_TR_REQ_CTL, 0,
+                          RISCV_IOMMU_TR_REQ_CTL_GO_BUSY);
+
+    riscv_iommu_reg_set32(s, RISCV_IOMMU_REG_IPSR, 0);
+
+    g_hash_table_remove_all(s->ctx_cache);
+    g_hash_table_remove_all(s->iot_cache);
+}
+
 static const Property riscv_iommu_properties[] = {
     DEFINE_PROP_UINT32("version", RISCVIOMMUState, version,
         RISCV_IOMMU_SPEC_DOT_VER),
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/trace-events
+++ b/hw/riscv/trace-events
@@ -XXX,XX +XXX,XX @@ riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb invalidate"
 riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group response"
 riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u"
 riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%lx msi_data 0x%x result %u"
+riscv_iommu_sys_reset_hold(int reset_type) "reset type %d"
+riscv_iommu_pci_reset_hold(int reset_type) "reset type %d"
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/specs/riscv-iommu.rst | 30 +++++++++++++++++++++++++++---
 docs/system/riscv/virt.rst | 10 ++++++++++
 2 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/specs/riscv-iommu.rst
+++ b/docs/specs/riscv-iommu.rst
@@ -XXX,XX +XXX,XX @@ RISC-V IOMMU support for RISC-V machines
 QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
 version 1.0 `iommu1.0`_.
 
-The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
-RISC-V boards can use.  The 'virt' RISC-V machine is compatible with this
-device.
+The emulation includes a PCI reference device (riscv-iommu-pci) and a platform
+bus device (riscv-iommu-sys) that QEMU RISC-V boards can use.  The 'virt'
+RISC-V machine is compatible with both devices.
 
 riscv-iommu-pci reference device
 --------------------------------
@@ -XXX,XX +XXX,XX @@ Several options are available to control the capabilities of the device, namely:
 - "s-stage": enable s-stage support
 - "g-stage": enable g-stage support
 
+riscv-iommu-sys device
+----------------------
+
+This device implements the RISC-V IOMMU emulation as a platform bus device that
+RISC-V boards can use.
+
+For the 'virt' board the device is disabled by default.  To enable it use the
+'iommu-sys' machine option:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M virt,iommu-sys=on (...)
+
+There is no options to configure the capabilities of this device in the 'virt'
+board using the QEMU command line.  The device is configured with the following
+riscv-iommu options:
+
+- "ioatc-limit": default value (2Mb)
+- "intremap": enabled
+- "ats": enabled
+- "off": on (DMA disabled)
+- "s-stage": enabled
+- "g-stage": enabled
+
 .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
 
 .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -XXX,XX +XXX,XX @@ command line:
 
   $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...)
 
+It also has support for the riscv-iommu-sys platform device:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M virt,iommu-sys=on (...)
+
 Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU support
 works.
 
@@ -XXX,XX +XXX,XX @@ The following machine-specific options are supported:
   having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
   the default number of per-HART VS-level AIA IMSIC pages is 0.
 
+- iommu-sys=[on|off]
+
+  Enables the riscv-iommu-sys platform device. Defaults to 'off'.
+
 Running Linux kernel
 --------------------
 
-- 
2.47.1

From: Anton Blanchard <antonb@tenstorrent.com>

Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to
8 wide RV64 cores. More details can be found at
https://tenstorrent.com/ip/tt-ascalon

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241113110459.1607299-1-antonb@tenstorrent.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu-qom.h |  1 +
 target/riscv/cpu.c     | 67 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -XXX,XX +XXX,XX @@
 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
 #define TYPE_RISCV_CPU_THEAD_C906       RISCV_CPU_TYPE_NAME("thead-c906")
 #define TYPE_RISCV_CPU_VEYRON_V1        RISCV_CPU_TYPE_NAME("veyron-v1")
+#define TYPE_RISCV_CPU_TT_ASCALON       RISCV_CPU_TYPE_NAME("tt-ascalon")
 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_veyron_v1_cpu_init(Object *obj)
 #endif
 }
 
+/* Tenstorrent Ascalon */
+static void rv64_tt_ascalon_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    RISCVCPU *cpu = RISCV_CPU(obj);
+
+    riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV);
+    env->priv_ver = PRIV_VERSION_1_13_0;
+
+    /* Enable ISA extensions */
+    cpu->cfg.mmu = true;
+    cpu->cfg.vlenb = 256 >> 3;
+    cpu->cfg.elen = 64;
+    cpu->env.vext_ver = VEXT_VERSION_1_00_0;
+    cpu->cfg.rvv_ma_all_1s = true;
+    cpu->cfg.rvv_ta_all_1s = true;
+    cpu->cfg.misa_w = true;
+    cpu->cfg.pmp = true;
+    cpu->cfg.cbom_blocksize = 64;
+    cpu->cfg.cbop_blocksize = 64;
+    cpu->cfg.cboz_blocksize = 64;
+    cpu->cfg.ext_zic64b = true;
+    cpu->cfg.ext_zicbom = true;
+    cpu->cfg.ext_zicbop = true;
+    cpu->cfg.ext_zicboz = true;
+    cpu->cfg.ext_zicntr = true;
+    cpu->cfg.ext_zicond = true;
+    cpu->cfg.ext_zicsr = true;
+    cpu->cfg.ext_zifencei = true;
+    cpu->cfg.ext_zihintntl = true;
+    cpu->cfg.ext_zihintpause = true;
+    cpu->cfg.ext_zihpm = true;
+    cpu->cfg.ext_zimop = true;
+    cpu->cfg.ext_zawrs = true;
+    cpu->cfg.ext_zfa = true;
+    cpu->cfg.ext_zfbfmin = true;
+    cpu->cfg.ext_zfh = true;
+    cpu->cfg.ext_zfhmin = true;
+    cpu->cfg.ext_zcb = true;
+    cpu->cfg.ext_zcmop = true;
+    cpu->cfg.ext_zba = true;
+    cpu->cfg.ext_zbb = true;
+    cpu->cfg.ext_zbs = true;
+    cpu->cfg.ext_zkt = true;
+    cpu->cfg.ext_zvbb = true;
+    cpu->cfg.ext_zvbc = true;
+    cpu->cfg.ext_zvfbfmin = true;
+    cpu->cfg.ext_zvfbfwma = true;
+    cpu->cfg.ext_zvfh = true;
+    cpu->cfg.ext_zvfhmin = true;
+    cpu->cfg.ext_zvkng = true;
+    cpu->cfg.ext_smaia = true;
+    cpu->cfg.ext_smstateen = true;
+    cpu->cfg.ext_ssaia = true;
+    cpu->cfg.ext_sscofpmf = true;
+    cpu->cfg.ext_sstc = true;
+    cpu->cfg.ext_svade = true;
+    cpu->cfg.ext_svinval = true;
+    cpu->cfg.ext_svnapot = true;
+    cpu->cfg.ext_svpbmt = true;
+
+#ifndef CONFIG_USER_ONLY
+    set_satp_mode_max_supported(cpu, VM_1_10_SV57);
+#endif
+}
+
 #ifdef CONFIG_TCG
 static void rv128_base_cpu_init(Object *obj)
 {
@@ -XXX,XX +XXX,XX @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,  rv64_sifive_u_cpu_init),
     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C,   MXL_RV64,  rv64_sifive_u_cpu_init),
     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,  rv64_thead_c906_cpu_init),
+    DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64,  rv64_tt_ascalon_cpu_init),
     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1,  MXL_RV64,  rv64_veyron_v1_cpu_init),
 #ifdef CONFIG_TCG
     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,   MXL_RV128, rv128_base_cpu_init),
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The helper is_kvm_aia() is checking not only for AIA, but for
aplic-imsic (i.e. "aia=aplic-imsic" in 'virt' RISC-V machine) with an
in-kernel chip present.

Rename it to be a bit clear what the helper is doing since we'll add
more AIA helpers in the next patches.

Make the helper public because the 'virt' machine will use it as well.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/riscv_aplic.h | 1 +
 hw/intc/riscv_aplic.c         | 8 ++++----
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/riscv_aplic.h
+++ b/include/hw/intc/riscv_aplic.h
@@ -XXX,XX +XXX,XX @@ struct RISCVAPLICState {
 };
 
 void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
+bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
 
 DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@
  * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use
  * APLIC Wired.
  */
-static bool is_kvm_aia(bool msimode)
+bool riscv_is_kvm_aia_aplic_imsic(bool msimode)
 {
     return kvm_irqchip_in_kernel() && msimode;
 }
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
     uint32_t i;
     RISCVAPLICState *aplic = RISCV_APLIC(dev);
 
-    if (!is_kvm_aia(aplic->msimode)) {
+    if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
         aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
         aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
         aplic->state = g_new0(uint32_t, aplic->num_irqs);
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
      * have IRQ lines delegated by their parent APLIC.
      */
     if (!aplic->parent) {
-        if (kvm_enabled() && is_kvm_aia(aplic->msimode)) {
+        if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
             qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
         } else {
             qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
 
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
-    if (!is_kvm_aia(msimode)) {
+    if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

In create_fdt_sockets() we have the following pattern:

if (kvm_enabled() && virt_use_kvm_aia(s)) {
        (... do stuff ...)
    } else {
        (... do other stuff ...)
    }
    if (kvm_enabled() && virt_use_kvm_aia(s)) {
        (... do more stuff ...)
    } else {
        (... do more other stuff)
    }

Do everything in a single if/else clause to reduce the usage of
virt_use_kvm_aia() helper and to make the code a bit less repetitive.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
                                 msi_m_phandle, msi_s_phandle, phandle,
                                 &intc_phandles[0], xplic_phandles,
                                 ms->smp.cpus);
+
+        *irq_mmio_phandle = xplic_phandles[0];
+        *irq_virtio_phandle = xplic_phandles[0];
+        *irq_pcie_phandle = xplic_phandles[0];
     } else {
         phandle_pos = ms->smp.cpus;
         for (socket = (socket_count - 1); socket >= 0; socket--) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
                                         s->soc[socket].num_harts);
             }
         }
-    }
 
-    if (kvm_enabled() && virt_use_kvm_aia(s)) {
-        *irq_mmio_phandle = xplic_phandles[0];
-        *irq_virtio_phandle = xplic_phandles[0];
-        *irq_pcie_phandle = xplic_phandles[0];
-    } else {
         for (socket = 0; socket < socket_count; socket++) {
             if (socket == 0) {
                 *irq_mmio_phandle = xplic_phandles[socket];
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Similar to the riscv_is_kvm_aia_aplic_imsic() helper from riscv_aplic.c,
the existing virt_use_kvm_aia() is testing for KVM aia=aplic-imsic with
in-kernel irqchip enabled. It is not checking for a generic AIA support.

Rename the helper to virt_use_kvm_aia_aplic_imsic() to reflect what the
helper is doing, and use the existing riscv_is_kvm_aia_aplic_imsic() to
obscure details such as the presence of the in-kernel irqchip.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/virtio/virtio-iommu.h"
 
 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */
-static bool virt_use_kvm_aia(RISCVVirtState *s)
+static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
 {
-    return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
+    bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
+
+    return riscv_is_kvm_aia_aplic_imsic(msimode);
 }
 
 static bool virt_aclint_allowed(void)
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
         *msi_pcie_phandle = msi_s_phandle;
     }
 
-    /* KVM AIA only has one APLIC instance */
-    if (kvm_enabled() && virt_use_kvm_aia(s)) {
+    /* KVM AIA aplic-imsic only has one APLIC instance */
+    if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
         create_fdt_socket_aplic(s, memmap, 0,
                                 msi_m_phandle, msi_s_phandle, phandle,
                                 &intc_phandles[0], xplic_phandles,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         }
     }
 
-    if (kvm_enabled() && virt_use_kvm_aia(s)) {
+    if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
         kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT,
                              VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS,
                              memmap[VIRT_APLIC_S].base,
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Before adding support to kernel-irqchip=split when using KVM AIA we need
to change how we create the in-kernel AIA device.

In the use case we have so far, i.e. in-kernel irqchip without split
mode, both the s-mode APLIC and IMSIC controllers are provided by the
irqchip. In irqchip_split() mode we'll emulate the s-mode APLIC
controller, which will send MSIs to the in-kernel IMSIC controller. To
do that we need to change kvm_riscv_aia_create() to not create the
in-kernel s-mode APLIC controller.

In the kernel source arch/riscv/kvm/aia_aplic.c, function
kvm_riscv_aia_aplic_init(), we verify that the APLIC controller won't be
instantiated by KVM if we do not set 'nr_sources', which is set via
KVM_DEV_RISCV_AIA_CONFIG_SRCS. For QEMU this means that we should not
set 'aia_irq_num' during kvm_riscv_aia_create() in irqchip_split() mode.

In this same condition, skip KVM_DEV_RISCV_AIA_ADDR_APLIC as well since
it is used to set the base address for the in-kernel APLIC controller.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 38 +++++++++++++++++++++++---------------
 1 file changed, 23 insertions(+), 15 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
-                            KVM_DEV_RISCV_AIA_CONFIG_SRCS,
-                            &aia_irq_num, true, NULL);
-    if (ret < 0) {
-        error_report("KVM AIA: failed to set number of input irq lines");
-        exit(1);
-    }
+    /*
+     * Skip APLIC creation in KVM if we're running split mode.
+     * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS
+     * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC
+     * since KVM won't be using it.
+     */
+    if (!kvm_kernel_irqchip_split()) {
+        ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                                KVM_DEV_RISCV_AIA_CONFIG_SRCS,
+                                &aia_irq_num, true, NULL);
+        if (ret < 0) {
+            error_report("KVM AIA: failed to set number of input irq lines");
+            exit(1);
+        }
+
+        ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
+                                KVM_DEV_RISCV_AIA_ADDR_APLIC,
+                                &aplic_base, true, NULL);
+        if (ret < 0) {
+            error_report("KVM AIA: failed to set the base address of APLIC");
+            exit(1);
+        }
+     }
 
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_IDS,
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         exit(1);
     }
 
-    ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR,
-                            KVM_DEV_RISCV_AIA_ADDR_APLIC,
-                            &aplic_base, true, NULL);
-    if (ret < 0) {
-        error_report("KVM AIA: failed to set the base address of APLIC");
-        exit(1);
-    }
-
     for (socket = 0; socket < socket_count; socket++) {
         socket_imsic_base = imsic_base + socket * (1U << group_shift);
         hart_count = riscv_socket_hart_count(machine, socket);
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The current logic to determine if we don't need an emulated APLIC
controller, i.e. KVM will provide for us, is to determine if we're
running KVM, with in-kernel irqchip support, and running
aia=aplic-imsic. This is modelled by riscv_is_kvm_aia_aplic_imsic() and
virt_use_kvm_aia_aplic_imsic().

This won't suffice to support irqchip_split() mode: it will match
exactly the same conditions as the one above, but setting the irqchip to
'split' mode will now require us to emulate an APLIC s-mode controller,
like we're doing with 'aia=aplic'.

Create a new riscv_use_emulated_aplic() helper that will encapsulate
this logic. Replace the uses of "riscv_is_kvm_aia_aplic_imsic()" with
this helper every time we're taking a decision on emulate an APLIC
controller or not. Do the same in virt.c with virt_use_emulated_aplic().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/riscv_aplic.h |  1 +
 hw/intc/riscv_aplic.c         | 24 +++++++++++++++++++++---
 hw/riscv/virt.c               | 14 ++++++++++++--
 3 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/riscv_aplic.h
+++ b/include/hw/intc/riscv_aplic.h
@@ -XXX,XX +XXX,XX @@ struct RISCVAPLICState {
 
 void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
 bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
+bool riscv_use_emulated_aplic(bool msimode);
 
 DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
 #include "kvm/kvm_riscv.h"
 #include "migration/vmstate.h"
 
@@ -XXX,XX +XXX,XX @@ bool riscv_is_kvm_aia_aplic_imsic(bool msimode)
     return kvm_irqchip_in_kernel() && msimode;
 }
 
+bool riscv_use_emulated_aplic(bool msimode)
+{
+#ifdef CONFIG_KVM
+    if (tcg_enabled()) {
+        return true;
+    }
+
+    if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
+        return true;
+    }
+
+    return kvm_kernel_irqchip_split();
+#else
+    return true;
+#endif
+}
+
 static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic,
                                           uint32_t irq)
 {
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
     uint32_t i;
     RISCVAPLICState *aplic = RISCV_APLIC(dev);
 
-    if (!riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
+    if (riscv_use_emulated_aplic(aplic->msimode)) {
         aplic->bitfield_words = (aplic->num_irqs + 31) >> 5;
         aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs);
         aplic->state = g_new0(uint32_t, aplic->num_irqs);
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
      * have IRQ lines delegated by their parent APLIC.
      */
     if (!aplic->parent) {
-        if (kvm_enabled() && riscv_is_kvm_aia_aplic_imsic(aplic->msimode)) {
+        if (kvm_enabled() && !riscv_use_emulated_aplic(aplic->msimode)) {
             qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs);
         } else {
             qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
 
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
-    if (!riscv_is_kvm_aia_aplic_imsic(msimode)) {
+    if (riscv_use_emulated_aplic(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
     return riscv_is_kvm_aia_aplic_imsic(msimode);
 }
 
+static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type)
+{
+    bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
+
+    return riscv_use_emulated_aplic(msimode);
+}
+
 static bool virt_aclint_allowed(void)
 {
     return tcg_enabled() || qtest_enabled();
@@ -XXX,XX +XXX,XX @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
         *msi_pcie_phandle = msi_s_phandle;
     }
 
-    /* KVM AIA aplic-imsic only has one APLIC instance */
-    if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) {
+    /*
+     * With KVM AIA aplic-imsic, using an irqchip without split
+     * mode, we'll use only one APLIC instance.
+     */
+    if (!virt_use_emulated_aplic(s->aia_type)) {
         create_fdt_socket_aplic(s, memmap, 0,
                                 msi_m_phandle, msi_s_phandle, phandle,
                                 &intc_phandles[0], xplic_phandles,
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

The last step to enable KVM AIA aplic-imsic with irqchip in split mode
is to deal with how MSIs are going to be sent. In our current design we
don't allow an APLIC controller to send MSIs unless it's on m-mode. And
we also do not allow Supervisor MSI address configuration via the
'smsiaddrcfg' and 'smsiaddrcfgh' registers unless it's also a m-mode
APLIC controller.

Add a new RISCVACPLICState attribute called 'kvm_msicfgaddr'. This
attribute represents the base configuration address for MSIs, in our
case the base addr of the IMSIC controller. This attribute is being set
only when running irqchip_split() mode with aia=aplic-imsic.

During riscv_aplic_msi_send() we'll check if the attribute was set to
skip the check for a m-mode APLIC controller and to change the resulting
MSI addr by adding kvm_msicfgaddr right before address_space_stl_le().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-7-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/riscv_aplic.h |  6 +++++
 hw/intc/riscv_aplic.c         | 42 +++++++++++++++++++++++++++--------
 hw/riscv/virt.c               |  6 ++++-
 3 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/riscv_aplic.h
+++ b/include/hw/intc/riscv_aplic.h
@@ -XXX,XX +XXX,XX @@ struct RISCVAPLICState {
     uint32_t num_irqs;
     bool msimode;
     bool mmode;
+
+    /* To support KVM aia=aplic-imsic with irqchip split mode */
+    bool kvm_splitmode;
+    uint32_t kvm_msicfgaddr;
+    uint32_t kvm_msicfgaddrH;
 };
 
 void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
 bool riscv_is_kvm_aia_aplic_imsic(bool msimode);
 bool riscv_use_emulated_aplic(bool msimode);
+void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr);
 
 DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ bool riscv_use_emulated_aplic(bool msimode)
 #endif
 }
 
+void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr)
+{
+#ifdef CONFIG_KVM
+    if (riscv_use_emulated_aplic(aplic->msimode)) {
+        aplic->kvm_msicfgaddr = extract64(addr, 0, 32);
+        aplic->kvm_msicfgaddrH = extract64(addr, 32, 32);
+    }
+#endif
+}
+
 static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic,
                                           uint32_t irq)
 {
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
     uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH;
 
     aplic_m = aplic;
-    while (aplic_m && !aplic_m->mmode) {
-        aplic_m = aplic_m->parent;
-    }
-    if (!aplic_m) {
-        qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
-                      __func__);
-        return;
+
+    if (!aplic->kvm_splitmode) {
+        while (aplic_m && !aplic_m->mmode) {
+            aplic_m = aplic_m->parent;
+        }
+        if (!aplic_m) {
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n",
+                          __func__);
+            return;
+        }
     }
 
     if (aplic->mmode) {
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic,
     addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs));
     addr <<= APLIC_xMSICFGADDR_PPN_SHIFT;
 
+    if (aplic->kvm_splitmode) {
+        addr |= aplic->kvm_msicfgaddr;
+        addr |= ((uint64_t)aplic->kvm_msicfgaddrH << 32);
+    }
+
     address_space_stl_le(&address_space_memory, addr,
                          eiid, MEMTXATTRS_UNSPECIFIED, &result);
     if (result != MEMTX_OK) {
@@ -XXX,XX +XXX,XX @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp)
         memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
                               aplic, TYPE_RISCV_APLIC, aplic->aperture_size);
         sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
+
+        if (kvm_enabled()) {
+            aplic->kvm_splitmode = true;
+        }
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ static const Property riscv_aplic_properties[] = {
 
 static const VMStateDescription vmstate_riscv_aplic = {
     .name = "riscv_aplic",
-    .version_id = 1,
-    .minimum_version_id = 1,
+    .version_id = 2,
+    .minimum_version_id = 2,
     .fields = (const VMStateField[]) {
             VMSTATE_UINT32(domaincfg, RISCVAPLICState),
             VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState),
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_riscv_aplic = {
             VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState),
             VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState),
             VMSTATE_UINT32(genmsi, RISCVAPLICState),
+            VMSTATE_UINT32(kvm_msicfgaddr, RISCVAPLICState),
+            VMSTATE_UINT32(kvm_msicfgaddrH, RISCVAPLICState),
             VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState,
                                   num_irqs, 0,
                                   vmstate_info_uint32, uint32_t),
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
                                     int base_hartid, int hart_count)
 {
     int i;
-    hwaddr addr;
+    hwaddr addr = 0;
     uint32_t guest_bits;
     DeviceState *aplic_s = NULL;
     DeviceState *aplic_m = NULL;
@@ -XXX,XX +XXX,XX @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
                                  VIRT_IRQCHIP_NUM_PRIO_BITS,
                                  msimode, false, aplic_m);
 
+    if (kvm_enabled() && msimode) {
+        riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr);
+    }
+
     return kvm_enabled() ? aplic_s : aplic_m;
 }
 
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Remove the 'irqchip_split()' restriction in kvm_arch_init() now that
we have support for "-accel kvm,kernel-irqchip=split".

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
 
 int kvm_arch_irqchip_create(KVMState *s)
 {
-    if (kvm_kernel_irqchip_split()) {
-        error_report("-machine kernel_irqchip=split is not supported on RISC-V.");
-        exit(1);
-    }
-
     /*
      * We can create the VAIA using the newer device control API.
      */
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Also add a new page, docs/specs/riscv-aia.rst, where we're documenting
the state of AIA support in QEMU w.r.t the controllers being emulated or
not depending on the AIA and accelerator settings.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241119191706.718860-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/specs/index.rst       |  1 +
 docs/specs/riscv-aia.rst   | 83 ++++++++++++++++++++++++++++++++++++++
 docs/system/riscv/virt.rst |  7 ++++
 3 files changed, 91 insertions(+)
 create mode 100644 docs/specs/riscv-aia.rst

diff --git a/docs/specs/index.rst b/docs/specs/index.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/specs/index.rst
+++ b/docs/specs/index.rst
@@ -XXX,XX +XXX,XX @@ guest hardware that is specific to QEMU.
    rapl-msr
    rocker
    riscv-iommu
+   riscv-aia
diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/specs/riscv-aia.rst
@@ -XXX,XX +XXX,XX @@
+.. _riscv-aia:
+
+RISC-V AIA support for RISC-V machines
+======================================
+
+AIA (Advanced Interrupt Architecture) support is implemented in the ``virt``
+RISC-V machine for TCG and KVM accelerators.
+
+The support consists of two main modes:
+
+- "aia=aplic": adds one or more APLIC (Advanced Platform Level Interrupt Controller)
+  devices
+- "aia=aplic-imsic": adds one or more APLIC device and an IMSIC (Incoming MSI
+   Controller) device for each CPU
+
+From an user standpoint, these modes will behave the same regardless of the accelerator
+used.  From a developer standpoint the accelerator settings will change what it being
+emulated in userspace versus what is being emulated by an in-kernel irqchip.
+
+When running TCG, all controllers are emulated in userspace, including machine mode
+(m-mode) APLIC and IMSIC (when applicable).
+
+When running KVM:
+
+- no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation regardless of
+  the AIA mode chosen
+- with "aia=aplic", s-mode APLIC will be emulated by userspace
+- with "aia=aplic-imsic" there are two possibilities.  If no additional KVM option
+  is provided there will be no APLIC or IMSIC emulation in userspace, and the virtual
+  machine will use the provided in-kernel APLIC and IMSIC controllers.  If the user
+  chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split",
+  s-mode APLIC will be emulated while using the s-mode IMSIC from the irqchip
+
+The following table summarizes how the AIA and accelerator options defines what
+we will emulate in userspace:
+
+
+.. list-table:: How AIA and accel options changes controller emulation
+   :widths: 25 25 25 25 25 25 25
+   :header-rows: 1
+
+   * - Accel
+     - Accel props
+     - AIA type
+     - APLIC m-mode
+     - IMSIC m-mode
+     - APLIC s-mode
+     - IMSIC s-mode
+   * - tcg
+     - ---
+     - aplic
+     - emul
+     - n/a
+     - emul
+     - n/a
+   * - tcg
+     - ---
+     - aplic-imsic
+     - emul
+     - emul
+     - emul
+     - emul
+   * - kvm
+     - ---
+     - aplic
+     - n/a
+     - n/a
+     - emul
+     - n/a
+   * - kvm
+     - none
+     - aplic-imsic
+     - n/a
+     - n/a
+     - in-kernel
+     - in-kernel
+   * - kvm
+     - irqchip=split
+     - aplic-imsic
+     - n/a
+     - n/a
+     - emul
+     - in-kernel
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -XXX,XX +XXX,XX @@ The following machine-specific options are supported:
   MSIs. When not specified, this option is assumed to be "none" which selects
   SiFive PLIC to handle wired interrupts.
 
+  This option also interacts with '-accel kvm'.  When using "aia=aplic-imsic"
+  with KVM, it is possible to set the use of the kernel irqchip in split mode
+  by using "-accel kvm,kernel-irqchip=split".  In this case the ``virt`` machine
+  will emulate the APLIC controller instead of using the APLIC controller from
+  the irqchip.  See :ref:`riscv-aia` for more details on all available AIA
+  modes.
+
 - aia-guests=nnn
 
   The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
-- 
2.47.1

From: Sai Pavan Boddu <sai.pavan.boddu@amd.com>

Add a basic board with interrupt controller (intc), timer, serial
(uartlite), small memory called LMB@0 (128kB) and DDR@0x80000000
(configured via command line eg. -m 2g).
This is basic configuration which matches HW generated out of AMD Vivado
(design tools). But initial configuration is going beyond what it is
configured by default because validation should be done on other
configurations too. That's why wire also additional uart16500, axi
ethernet(with axi dma).
GPIOs, i2c and qspi is also listed for completeness.

IRQ map is: (addr)
0 - timer (0x41c00000)
1 - uartlite (0x40600000)
2 - i2c (0x40800000)
3 - qspi (0x44a00000)
4 - uart16550 (0x44a10000)
5 - emaclite (0x40e00000)
6 - timer2 (0x41c10000)
7 - axi emac (0x40c00000)
8 - axi dma (0x41e00000)
9 - axi dma
10 - gpio (0x40000000)
11 - gpio2 (0x40010000)
12 - gpio3 (0x40020000)

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241125134739.18189-1-sai.pavan.boddu@amd.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS                                |   6 +
 docs/system/riscv/microblaze-v-generic.rst |  42 +++++
 docs/system/target-riscv.rst               |   1 +
 hw/riscv/microblaze-v-generic.c            | 184 +++++++++++++++++++++
 hw/riscv/Kconfig                           |   8 +
 hw/riscv/meson.build                       |   1 +
 6 files changed, 242 insertions(+)
 create mode 100644 docs/system/riscv/microblaze-v-generic.rst
 create mode 100644 hw/riscv/microblaze-v-generic.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: docs/system/riscv/sifive_u.rst
 F: hw/*/*sifive*.c
 F: include/hw/*/*sifive*.h
 
+AMD Microblaze-V Generic Board
+M: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
+S: Maintained
+F: hw/riscv/microblaze-v-generic.c
+F: docs/system/riscv/microblaze-v-generic.rst
+
 RX Machines
 -----------
 rx-gdbsim
diff --git a/docs/system/riscv/microblaze-v-generic.rst b/docs/system/riscv/microblaze-v-generic.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/riscv/microblaze-v-generic.rst
@@ -XXX,XX +XXX,XX @@
+Microblaze-V generic board (``amd-microblaze-v-generic``)
+=========================================================
+The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
+adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
+64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
+compatible with the classic MicroBlaze™ V processor (i.e it is a drop in
+replacement for the classic MicroBlaze™ processor in existing RTL designs).
+More information can be found in below document.
+
+https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture
+
+The MicroBlaze™ V generic board in QEMU has following supported devices:
+
+    - timer
+    - uartlite
+    - uart16550
+    - emaclite
+    - timer2
+    - axi emac
+    - axi dma
+
+The MicroBlaze™ V core in QEMU has the following configuration:
+
+    - RV32I base integer instruction set
+    - "Zicsr" Control and Status register instructions
+    - "Zifencei" instruction-fetch
+    - Extensions: m, a, f, c
+
+Running
+"""""""
+Below is an example command line for launching mainline U-boot
+(xilinx_mbv32_defconfig) on the Microblaze-V generic board.
+
+.. code-block:: bash
+
+   $ qemu-system-riscv32 -M amd-microblaze-v-generic \
+     -display none \
+     -device loader,addr=0x80000000,file=u-boot-spl.bin,cpu-num=0 \
+     -device loader,addr=0x80200000,file=u-boot.img \
+     -serial mon:stdio \
+     -device loader,addr=0x83000000,file=system.dtb \
+     -m 2g
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
 .. toctree::
    :maxdepth: 1
 
+   riscv/microblaze-v-generic
    riscv/microchip-icicle-kit
    riscv/shakti-c
    riscv/sifive_u
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/riscv/microblaze-v-generic.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of Microblaze V generic board.
+ *
+ * based on hw/microblaze/petalogix_ml605_mmu.c
+ *
+ * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
+ * Copyright (c) 2011 PetaLogix
+ * Copyright (c) 2009 Edgar E. Iglesias.
+ * Copyright (C) 2024, Advanced Micro Devices, Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Sai Pavan Boddu <sai.pavan.boddu@amd.com
+ *     and by Michal Simek <michal.simek@amd.com>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "net/net.h"
+#include "hw/boards.h"
+#include "hw/char/serial-mm.h"
+#include "exec/address-spaces.h"
+#include "hw/char/xilinx_uartlite.h"
+#include "hw/misc/unimp.h"
+
+#define LMB_BRAM_SIZE (128 * KiB)
+#define MEMORY_BASEADDR 0x80000000
+#define INTC_BASEADDR 0x41200000
+#define TIMER_BASEADDR 0x41c00000
+#define TIMER_BASEADDR2 0x41c10000
+#define UARTLITE_BASEADDR 0x40600000
+#define ETHLITE_BASEADDR 0x40e00000
+#define UART16550_BASEADDR 0x44a10000
+#define AXIENET_BASEADDR 0x40c00000
+#define AXIDMA_BASEADDR 0x41e00000
+#define GPIO_BASEADDR 0x40000000
+#define GPIO_BASEADDR2 0x40010000
+#define GPIO_BASEADDR3 0x40020000
+#define I2C_BASEADDR 0x40800000
+#define QSPI_BASEADDR 0x44a00000
+
+#define TIMER_IRQ           0
+#define UARTLITE_IRQ        1
+#define UART16550_IRQ       4
+#define ETHLITE_IRQ         5
+#define TIMER_IRQ2          6
+#define AXIENET_IRQ         7
+#define AXIDMA_IRQ1         8
+#define AXIDMA_IRQ0         9
+
+static void mb_v_generic_init(MachineState *machine)
+{
+    ram_addr_t ram_size = machine->ram_size;
+    DeviceState *dev, *dma, *eth0;
+    Object *ds, *cs;
+    int i;
+    RISCVCPU *cpu;
+    hwaddr ddr_base = MEMORY_BASEADDR;
+    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
+    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
+    qemu_irq irq[32];
+    MemoryRegion *sysmem = get_system_memory();
+
+    cpu = RISCV_CPU(object_new(machine->cpu_type));
+    object_property_set_bool(OBJECT(cpu), "h", false, NULL);
+    object_property_set_bool(OBJECT(cpu), "d", false, NULL);
+    qdev_realize(DEVICE(cpu), NULL, &error_abort);
+    /* Attach emulated BRAM through the LMB.  */
+    memory_region_init_ram(phys_lmb_bram, NULL,
+                           "mb_v.lmb_bram", LMB_BRAM_SIZE,
+                           &error_fatal);
+    memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
+
+    memory_region_init_ram(phys_ram, NULL, "mb_v.ram",
+                           ram_size, &error_fatal);
+    memory_region_add_subregion(sysmem, ddr_base, phys_ram);
+
+    dev = qdev_new("xlnx.xps-intc");
+    qdev_prop_set_uint32(dev, "kind-of-intr",
+                         1 << UARTLITE_IRQ);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
+                       qdev_get_gpio_in(DEVICE(cpu), 11));
+    for (i = 0; i < 32; i++) {
+        irq[i] = qdev_get_gpio_in(dev, i);
+    }
+
+    /* Uartlite */
+    dev = qdev_new(TYPE_XILINX_UARTLITE);
+    qdev_prop_set_chr(dev, "chardev", serial_hd(0));
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);
+
+    /* Full uart */
+    serial_mm_init(sysmem, UART16550_BASEADDR + 0x1000, 2,
+                   irq[UART16550_IRQ], 115200, serial_hd(1),
+                   DEVICE_LITTLE_ENDIAN);
+
+    /* 2 timers at irq 0 @ 100 Mhz.  */
+    dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_uint32(dev, "one-timer-only", 0);
+    qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
+
+    /* 2 timers at irq 3 @ 100 Mhz.  */
+    dev = qdev_new("xlnx.xps-timer");
+    qdev_prop_set_uint32(dev, "one-timer-only", 0);
+    qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR2);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ2]);
+
+    /* Emaclite */
+    dev = qdev_new("xlnx.xps-ethernetlite");
+    qemu_configure_nic_device(dev, true, NULL);
+    qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
+    qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
+
+    /* axi ethernet and dma initialization. */
+    eth0 = qdev_new("xlnx.axi-ethernet");
+    dma = qdev_new("xlnx.axi-dma");
+
+    /* FIXME: attach to the sysbus instead */
+    object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0));
+    object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma));
+
+    ds = object_property_get_link(OBJECT(dma),
+                                  "axistream-connected-target", NULL);
+    cs = object_property_get_link(OBJECT(dma),
+                                  "axistream-control-connected-target", NULL);
+    qemu_configure_nic_device(eth0, true, NULL);
+    qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
+    qdev_prop_set_uint32(eth0, "txmem", 0x1000);
+    object_property_set_link(OBJECT(eth0), "axistream-connected", ds,
+                             &error_abort);
+    object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs,
+                             &error_abort);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
+
+    ds = object_property_get_link(OBJECT(eth0),
+                                  "axistream-connected-target", NULL);
+    cs = object_property_get_link(OBJECT(eth0),
+                                  "axistream-control-connected-target", NULL);
+    qdev_prop_set_uint32(dma, "freqhz", 100000000);
+    object_property_set_link(OBJECT(dma), "axistream-connected", ds,
+                             &error_abort);
+    object_property_set_link(OBJECT(dma), "axistream-control-connected", cs,
+                             &error_abort);
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
+    sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
+
+    /* unimplemented devices */
+    create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
+    create_unimplemented_device("gpio2", GPIO_BASEADDR2, 0x10000);
+    create_unimplemented_device("gpio3", GPIO_BASEADDR3, 0x10000);
+    create_unimplemented_device("i2c", I2C_BASEADDR, 0x10000);
+    create_unimplemented_device("qspi", QSPI_BASEADDR, 0x10000);
+}
+
+static void mb_v_generic_machine_init(MachineClass *mc)
+{
+    mc->desc = "AMD Microblaze-V generic platform";
+    mc->init = mb_v_generic_init;
+    mc->min_cpus = 1;
+    mc->max_cpus = 1;
+    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+    mc->default_cpus = 1;
+}
+
+DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select SIFIVE_PLIC
     select UNIMP
 
+config MICROBLAZE_V
+    bool
+    default y
+    depends on RISCV32 || RISCV64
+    select XILINX
+    select XILINX_AXI
+    select XILINX_ETHLITE
+
 config OPENTITAN
     bool
     default y
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c'))
+riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
 
 hw_arch += {'riscv': riscv_ss}
-- 
2.47.1

From: Sia Jee Heng <jeeheng.sia@starfivetech.com>

Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].

[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931

Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-ID: <20241028015744.624943-3-jeeheng.sia@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/acpi/acpi-defs.h |  7 +++++--
 include/hw/acpi/aml-build.h |  2 +-
 hw/acpi/aml-build.c         | 20 ++++++++++++++++----
 hw/arm/virt-acpi-build.c    |  8 ++++++--
 hw/loongarch/acpi-build.c   |  6 +++++-
 hw/riscv/virt-acpi-build.c  | 12 +++++++++---
 6 files changed, 42 insertions(+), 13 deletions(-)

diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -XXX,XX +XXX,XX @@ typedef struct AcpiSpcrData {
     uint8_t flow_control;
     uint8_t terminal_type;
     uint8_t language;
-    uint8_t reserved1;
     uint16_t pci_device_id;    /* Must be 0xffff if not PCI device */
     uint16_t pci_vendor_id;    /* Must be 0xffff if not PCI device */
     uint8_t pci_bus;
@@ -XXX,XX +XXX,XX @@ typedef struct AcpiSpcrData {
     uint8_t pci_function;
     uint32_t pci_flags;
     uint8_t pci_segment;
-    uint32_t reserved2;
+    uint32_t uart_clk_freq;
+    uint32_t precise_baudrate;
+    uint32_t namespace_string_length;
+    uint32_t namespace_string_offset;
+    char namespace_string[];
 } AcpiSpcrData;
 
 #define ACPI_FADT_ARM_PSCI_COMPLIANT  (1 << 0)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -XXX,XX +XXX,XX @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
 
 void build_spcr(GArray *table_data, BIOSLinker *linker,
                 const AcpiSpcrData *f, const uint8_t rev,
-                const char *oem_id, const char *oem_table_id);
+                const char *oem_id, const char *oem_table_id, const char *name);
 #endif
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -XXX,XX +XXX,XX @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags,
 
 void build_spcr(GArray *table_data, BIOSLinker *linker,
                 const AcpiSpcrData *f, const uint8_t rev,
-                const char *oem_id, const char *oem_table_id)
+                const char *oem_id, const char *oem_table_id, const char *name)
 {
     AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
                         .oem_table_id = oem_table_id };
@@ -XXX,XX +XXX,XX @@ void build_spcr(GArray *table_data, BIOSLinker *linker,
     build_append_int_noprefix(table_data, f->pci_flags, 4);
     /* PCI Segment */
     build_append_int_noprefix(table_data, f->pci_segment, 1);
-    /* Reserved */
-    build_append_int_noprefix(table_data, 0, 4);
-
+    if (rev < 4) {
+        /* Reserved */
+        build_append_int_noprefix(table_data, 0, 4);
+    } else {
+        /* UartClkFreq */
+        build_append_int_noprefix(table_data, f->uart_clk_freq, 4);
+        /* PreciseBaudrate */
+        build_append_int_noprefix(table_data, f->precise_baudrate, 4);
+        /* NameSpaceStringLength */
+        build_append_int_noprefix(table_data, f->namespace_string_length, 2);
+        /* NameSpaceStringOffset */
+        build_append_int_noprefix(table_data, f->namespace_string_offset, 2);
+        /* NamespaceString[] */
+        g_array_append_vals(table_data, name, f->namespace_string_length);
+    }
     acpi_table_end(linker, &table);
 }
 /*
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         .pci_flags = 0,
         .pci_segment = 0,
     };
-
-    build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
+    /*
+     * Passing NULL as the SPCR Table for Revision 2 doesn't support
+     * NameSpaceString.
+     */
+    build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id,
+               NULL);
 }
 
 /*
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -XXX,XX +XXX,XX @@ spcr_setup(GArray *table_data, BIOSLinker *linker, MachineState *machine)
     };
 
     lvms = LOONGARCH_VIRT_MACHINE(machine);
+    /*
+     * Passing NULL as the SPCR Table for Revision 2 doesn't support
+     * NameSpaceString.
+     */
     build_spcr(table_data, linker, &serial, 2, lvms->oem_id,
-               lvms->oem_table_id);
+               lvms->oem_table_id, NULL);
 }
 
 typedef
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
 
 /*
  * Serial Port Console Redirection Table (SPCR)
- * Rev: 1.07
+ * Rev: 1.10
  */
 
 static void
 spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
 {
+    const char name[] = ".";
     AcpiSpcrData serial = {
-        .interface_type = 0,       /* 16550 compatible */
+        .interface_type = 0x12,       /* 16550 compatible */
         .base_addr.id = AML_AS_SYSTEM_MEMORY,
         .base_addr.width = 32,
         .base_addr.offset = 0,
@@ -XXX,XX +XXX,XX @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
         .pci_function = 0,
         .pci_flags = 0,
         .pci_segment = 0,
+        .uart_clk_freq = 0,
+        .precise_baudrate = 0,
+        .namespace_string_length = sizeof(name),
+        .namespace_string_offset = 88,
     };
 
-    build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
+    build_spcr(table_data, linker, &serial, 4, s->oem_id, s->oem_table_id,
+               name);
 }
 
 /* RHCT Node[N] starts at offset 56 */
-- 
2.47.1

From: Sia Jee Heng <jeeheng.sia@starfivetech.com>

Update the virt SPCR golden reference file for RISC-V to accommodate the
SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
latest ACPICA repository. The SPCR table has been modified to
adhere to the revision 4 format [2].

[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931

Diffs from iasl:
/*
  * Intel ACPI Component Architecture
  * AML/ASL+ Disassembler version 20200925 (64-bit version)
  * Copyright (c) 2000 - 2020 Intel Corporation
  *
- * Disassembly of tests/data/acpi/riscv64/virt/SPCR, Wed Aug 28 18:28:19 2024
+ * Disassembly of /tmp/aml-MN0NS2, Wed Aug 28 18:28:19 2024
  *
  * ACPI Data Table [SPCR]
  *
  * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
  */

[000h 0000   4]                    Signature : "SPCR"    [Serial Port Console Redirection table]
-[004h 0004   4]                 Table Length : 00000050
-[008h 0008   1]                     Revision : 02
-[009h 0009   1]                     Checksum : B9
+[004h 0004   4]                 Table Length : 0000005A
+[008h 0008   1]                     Revision : 04
+[009h 0009   1]                     Checksum : 13
 [00Ah 0010   6]                       Oem ID : "BOCHS "
 [010h 0016   8]                 Oem Table ID : "BXPC    "
 [018h 0024   4]                 Oem Revision : 00000001
 [01Ch 0028   4]              Asl Compiler ID : "BXPC"
 [020h 0032   4]        Asl Compiler Revision : 00000001

-[024h 0036   1]               Interface Type : 00
+[024h 0036   1]               Interface Type : 12
 [025h 0037   3]                     Reserved : 000000

[028h 0040  12]         Serial Port Register : [Generic Address Structure]
 [028h 0040   1]                     Space ID : 00 [SystemMemory]
 [029h 0041   1]                    Bit Width : 20
 [02Ah 0042   1]                   Bit Offset : 00
 [02Bh 0043   1]         Encoded Access Width : 01 [Byte Access:8]
 [02Ch 0044   8]                      Address : 0000000010000000

[034h 0052   1]               Interrupt Type : 10
 [035h 0053   1]          PCAT-compatible IRQ : 00
 [036h 0054   4]                    Interrupt : 0000000A
 [03Ah 0058   1]                    Baud Rate : 07
 [03Bh 0059   1]                       Parity : 00
 [03Ch 0060   1]                    Stop Bits : 01
 [03Dh 0061   1]                 Flow Control : 00
 [03Eh 0062   1]                Terminal Type : 00
 [04Ch 0076   1]                     Reserved : 00
 [040h 0064   2]                PCI Device ID : FFFF
 [042h 0066   2]                PCI Vendor ID : FFFF
 [044h 0068   1]                      PCI Bus : 00
 [045h 0069   1]                   PCI Device : 00
 [046h 0070   1]                 PCI Function : 00
 [047h 0071   4]                    PCI Flags : 00000000
 [04Bh 0075   1]                  PCI Segment : 00
-[04Ch 0076   4]                     Reserved : 00000000
+[04Ch 0076 004h]             Uart Clock Freq : 00000000
+[050h 0080 004h]           Precise Baud rate : 00000000
+[054h 0084 002h]       NameSpaceStringLength : 0002
+[056h 0086 002h]       NameSpaceStringOffset : 0058
+[058h 0088 002h]             NamespaceString : "."

-Raw Table Data: Length 80 (0x50)
+Raw Table Data: Length 90 (0x5A)

-    0000: 53 50 43 52 50 00 00 00 02 B9 42 4F 43 48 53 20  // SPCRP.....BOCHS
+    0000: 53 50 43 52 5A 00 00 00 04 13 42 4F 43 48 53 20  // SPCRZ.....BOCHS
     0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC    ....BXPC
-    0020: 01 00 00 00 00 00 00 00 00 20 00 01 00 00 00 10  // ......... ......
+    0020: 01 00 00 00 12 00 00 00 00 20 00 01 00 00 00 10  // ......... ......
     0030: 00 00 00 00 10 00 0A 00 00 00 07 00 01 00 00 03  // ................
     0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00  // ................
+    0050: 00 00 00 00 02 00 58 00 2E 00                    // ......X...

Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Message-ID: <20241028015744.624943-4-jeeheng.sia@starfivetech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 tests/qtest/bios-tables-test-allowed-diff.h |   1 -
 tests/data/acpi/riscv64/virt/SPCR           | Bin 80 -> 90 bytes
 2 files changed, 1 deletion(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/riscv64/virt/SPCR",
diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/virt/SPCR
index XXXXXXX..XXXXXXX 100644
Binary files a/tests/data/acpi/riscv64/virt/SPCR and b/tests/data/acpi/riscv64/virt/SPCR differ
-- 
2.47.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Since our RISC-V system emulation is only built for little
endian, the HTIF device aims to interface with little endian
memory accesses, thus we can explicit htif_mm_ops:endianness
being DEVICE_LITTLE_ENDIAN.

In that case tswap64() is equivalent to le64_to_cpu(), as in
"convert this 64-bit little-endian value into host cpu order".
Replace to simplify.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/riscv_htif.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
 #include "exec/address-spaces.h"
-#include "exec/tswap.h"
+#include "qemu/bswap.h"
 #include "sysemu/dma.h"
 #include "sysemu/runstate.h"
 
@@ -XXX,XX +XXX,XX @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written)
             } else {
                 uint64_t syscall[8];
                 cpu_physical_memory_read(payload, syscall, sizeof(syscall));
-                if (tswap64(syscall[0]) == PK_SYS_WRITE &&
-                    tswap64(syscall[1]) == HTIF_DEV_CONSOLE &&
-                    tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
+                if (le64_to_cpu(syscall[0]) == PK_SYS_WRITE &&
+                    le64_to_cpu(syscall[1]) == HTIF_DEV_CONSOLE &&
+                    le64_to_cpu(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) {
                     uint8_t ch;
-                    cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1);
+                    cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch, 1);
                     /*
                      * XXX this blocks entire thread. Rewrite to use
                      * qemu_chr_fe_write and background I/O callbacks
@@ -XXX,XX +XXX,XX @@ static void htif_mm_write(void *opaque, hwaddr addr,
 static const MemoryRegionOps htif_mm_ops = {
     .read = htif_mm_read,
     .write = htif_mm_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
 HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
-- 
2.47.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Looking at htif_mm_ops[] read/write handlers, we notice they
expect 32-bit values to accumulate into to the 'fromhost' and
'tohost' 64-bit variables. Explicit by setting the .impl
min/max fields.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241129154304.34946-4-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/char/riscv_htif.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps htif_mm_ops = {
     .read = htif_mm_read,
     .write = htif_mm_write,
     .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
 };
 
 HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr,
-- 
2.47.1

From: Jim Shu <jim.shu@sifive.com>

Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241120153935.24706-2-jim.shu@sifive.com>
[ Changes by AF
 -  Store fdt_load_addr_hi32 in the reset vector
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h    |  2 +-
 hw/riscv/boot.c            | 14 +++++++++-----
 hw/riscv/microchip_pfsoc.c |  4 ++--
 hw/riscv/sifive_u.c        |  8 +++++---
 hw/riscv/spike.c           |  4 ++--
 hw/riscv/virt.c            |  2 +-
 6 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
                                bool load_initrd,
                                symbol_fn_t sym_cb);
 uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
-                                MachineState *ms);
+                                MachineState *ms, RISCVHartArrayState *harts);
 void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
                                hwaddr saddr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ out:
  * The FDT is fdt_packed() during the calculation.
  */
 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
-                                MachineState *ms)
+                                MachineState *ms, RISCVHartArrayState *harts)
 {
     int ret = fdt_pack(ms->fdt);
     hwaddr dram_end, temp;
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
 
     /*
      * We should put fdt as far as possible to avoid kernel/initrd overwriting
-     * its content. But it should be addressable by 32 bit system as well.
-     * Thus, put it at an 2MB aligned address that less than fdt size from the
-     * end of dram or 3GB whichever is lesser.
+     * its content. But it should be addressable by 32 bit system as well in RV32.
+     * Thus, put it near to the end of dram in RV64, and put it near to the end
+     * of dram or 3GB whichever is lesser in RV32.
      */
-    temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
+    if (!riscv_is_32bit(harts)) {
+        temp = dram_end;
+    } else {
+        temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
+    }
 
     return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
 }
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     bool kernel_as_payload = false;
     target_ulong firmware_end_addr, kernel_start_addr;
     uint64_t kernel_entry;
-    uint32_t fdt_load_addr;
+    uint64_t fdt_load_addr;
     DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
 
     /* Sanity check on RAM size */
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
         /* Compute the fdt load address in dram */
         fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
                                                memmap[MICROCHIP_PFSOC_DRAM_LO].size,
-                                               machine);
+                                               machine, &s->soc.u_cpus);
         riscv_load_fdt(fdt_load_addr, machine->fdt);
 
         /* Load the reset vector */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     target_ulong firmware_end_addr, kernel_start_addr;
     const char *firmware_name;
     uint32_t start_addr_hi32 = 0x00000000;
+    uint32_t fdt_load_addr_hi32 = 0x00000000;
     int i;
-    uint32_t fdt_load_addr;
+    uint64_t fdt_load_addr;
     uint64_t kernel_entry;
     DriveInfo *dinfo;
     BlockBackend *blk;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
                                            memmap[SIFIVE_U_DEV_DRAM].size,
-                                           machine);
+                                           machine, &s->soc.u_cpus);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     if (!riscv_is_32bit(&s->soc.u_cpus)) {
         start_addr_hi32 = (uint64_t)start_addr >> 32;
+        fdt_load_addr_hi32 = fdt_load_addr >> 32;
     }
 
     /* reset vector */
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
         start_addr,                    /* start: .dword */
         start_addr_hi32,
         fdt_load_addr,                 /* fdt_laddr: .dword */
-        0x00000000,
+        fdt_load_addr_hi32,
         0x00000000,
                                        /* fw_dyn: */
     };
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base;
     target_ulong kernel_start_addr;
     char *firmware_name;
-    uint32_t fdt_load_addr;
+    uint64_t fdt_load_addr;
     uint64_t kernel_entry;
     char *soc_name;
     int i, base_hartid, hart_count;
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
                                            memmap[SPIKE_DRAM].size,
-                                           machine);
+                                           machine, &s->soc[0]);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     /* load the reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
                                            memmap[VIRT_DRAM].size,
-                                           machine);
+                                           machine, &s->soc[0]);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     /* load the reset vector */
-- 
2.47.1

From: Jim Shu <jim.shu@sifive.com>

Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241120153935.24706-3-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/boot.h    | 25 ++++++++++-----
 hw/riscv/boot.c            | 65 ++++++++++++++++++++++----------------
 hw/riscv/microchip_pfsoc.c | 11 ++++---
 hw/riscv/opentitan.c       |  4 ++-
 hw/riscv/sifive_e.c        |  4 ++-
 hw/riscv/sifive_u.c        | 12 ++++---
 hw/riscv/spike.c           | 12 ++++---
 hw/riscv/virt.c            | 13 +++++---
 8 files changed, 90 insertions(+), 56 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@
 #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
 #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
 
+typedef struct RISCVBootInfo {
+    ssize_t kernel_size;
+    hwaddr image_low_addr;
+    hwaddr image_high_addr;
+
+    bool is_32bit;
+} RISCVBootInfo;
+
 bool riscv_is_32bit(RISCVHartArrayState *harts);
 
 char *riscv_plic_hart_config_string(int hart_count);
 
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
+void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
+target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
                                           target_ulong firmware_end_addr);
 target_ulong riscv_find_and_load_firmware(MachineState *machine,
                                           const char *default_machine_firmware,
@@ -XXX,XX +XXX,XX @@ char *riscv_find_firmware(const char *firmware_filename,
 target_ulong riscv_load_firmware(const char *firmware_filename,
                                  hwaddr *firmware_load_addr,
                                  symbol_fn_t sym_cb);
-target_ulong riscv_load_kernel(MachineState *machine,
-                               RISCVHartArrayState *harts,
-                               target_ulong firmware_end_addr,
-                               bool load_initrd,
-                               symbol_fn_t sym_cb);
-uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
-                                MachineState *ms, RISCVHartArrayState *harts);
+void riscv_load_kernel(MachineState *machine,
+                       RISCVBootInfo *info,
+                       target_ulong kernel_start_addr,
+                       bool load_initrd,
+                       symbol_fn_t sym_cb);
+uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
+                                MachineState *ms, RISCVBootInfo *info);
 void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
                                hwaddr saddr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ char *riscv_plic_hart_config_string(int hart_count)
     return g_strjoinv(",", (char **)vals);
 }
 
-target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
+void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
+{
+    info->kernel_size = 0;
+    info->is_32bit = riscv_is_32bit(harts);
+}
+
+target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
                                           target_ulong firmware_end_addr) {
-    if (riscv_is_32bit(harts)) {
+    if (info->is_32bit) {
         return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
     } else {
         return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_firmware(const char *firmware_filename,
     exit(1);
 }
 
-static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
 {
     const char *filename = machine->initrd_filename;
     uint64_t mem_size = machine->ram_size;
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
      * halfway into RAM, and for boards with 1GB of RAM or more we put
      * the initrd at 512MB.
      */
-    start = kernel_entry + MIN(mem_size / 2, 512 * MiB);
+    start = info->image_low_addr + MIN(mem_size / 2, 512 * MiB);
 
     size = load_ramdisk(filename, start, mem_size - start);
     if (size == -1) {
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     }
 }
 
-target_ulong riscv_load_kernel(MachineState *machine,
-                               RISCVHartArrayState *harts,
-                               target_ulong kernel_start_addr,
-                               bool load_initrd,
-                               symbol_fn_t sym_cb)
+void riscv_load_kernel(MachineState *machine,
+                       RISCVBootInfo *info,
+                       target_ulong kernel_start_addr,
+                       bool load_initrd,
+                       symbol_fn_t sym_cb)
 {
     const char *kernel_filename = machine->kernel_filename;
-    uint64_t kernel_load_base, kernel_entry;
+    ssize_t kernel_size;
     void *fdt = machine->fdt;
 
     g_assert(kernel_filename != NULL);
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
      * the (expected) load address load address. This allows kernels to have
      * separate SBI and ELF entry points (used by FreeBSD, for example).
      */
-    if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
-                         NULL, &kernel_load_base, NULL, NULL, 0,
-                         EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
-        kernel_entry = kernel_load_base;
+    kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL,
+                                   &info->image_low_addr, &info->image_high_addr,
+                                   NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb);
+    if (kernel_size > 0) {
+        info->kernel_size = kernel_size;
         goto out;
     }
 
-    if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
-                       NULL, NULL, NULL) > 0) {
+    kernel_size = load_uimage_as(kernel_filename, &info->image_low_addr,
+                                 NULL, NULL, NULL, NULL, NULL);
+    if (kernel_size > 0) {
+        info->kernel_size = kernel_size;
+        info->image_high_addr = info->image_low_addr + kernel_size;
         goto out;
     }
 
-    if (load_image_targphys_as(kernel_filename, kernel_start_addr,
-                               current_machine->ram_size, NULL) > 0) {
-        kernel_entry = kernel_start_addr;
+    kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr,
+                                         current_machine->ram_size, NULL);
+    if (kernel_size > 0) {
+        info->kernel_size = kernel_size;
+        info->image_low_addr = kernel_start_addr;
+        info->image_high_addr = info->image_low_addr + kernel_size;
         goto out;
     }
 
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(MachineState *machine,
 
 out:
     /*
-     * For 32 bit CPUs 'kernel_entry' can be sign-extended by
+     * For 32 bit CPUs 'image_low_addr' can be sign-extended by
      * load_elf_ram_sym().
      */
-    if (riscv_is_32bit(harts)) {
-        kernel_entry = extract64(kernel_entry, 0, 32);
+    if (info->is_32bit) {
+        info->image_low_addr = extract64(info->image_low_addr, 0, 32);
     }
 
     if (load_initrd && machine->initrd_filename) {
-        riscv_load_initrd(machine, kernel_entry);
+        riscv_load_initrd(machine, info);
     }
 
     if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) {
         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
                                 machine->kernel_cmdline);
     }
-
-    return kernel_entry;
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ out:
  * The FDT is fdt_packed() during the calculation.
  */
 uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
-                                MachineState *ms, RISCVHartArrayState *harts)
+                                MachineState *ms, RISCVBootInfo *info)
 {
     int ret = fdt_pack(ms->fdt);
     hwaddr dram_end, temp;
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
      * Thus, put it near to the end of dram in RV64, and put it near to the end
      * of dram or 3GB whichever is lesser in RV32.
      */
-    if (!riscv_is_32bit(harts)) {
+    if (!info->is_32bit) {
         temp = dram_end;
     } else {
         temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     uint64_t kernel_entry;
     uint64_t fdt_load_addr;
     DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
+    RISCVBootInfo boot_info;
 
     /* Sanity check on RAM size */
     if (machine->ram_size < mc->default_ram_size) {
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
                                                      &firmware_load_addr, NULL);
 
+    riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
     if (kernel_as_payload) {
-        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
+        kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
                                                          firmware_end_addr);
 
-        kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
-                                         kernel_start_addr, true, NULL);
+        riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+                          true, NULL);
+        kernel_entry = boot_info.image_low_addr;
 
         /* Compute the fdt load address in dram */
         fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
                                                memmap[MICROCHIP_PFSOC_DRAM_LO].size,
-                                               machine, &s->soc.u_cpus);
+                                               machine, &boot_info);
         riscv_load_fdt(fdt_load_addr, machine->fdt);
 
         /* Load the reset vector */
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void opentitan_machine_init(MachineState *machine)
     OpenTitanState *s = OPENTITAN_MACHINE(machine);
     const MemMapEntry *memmap = ibex_memmap;
     MemoryRegion *sys_mem = get_system_memory();
+    RISCVBootInfo boot_info;
 
     if (machine->ram_size != mc->default_ram_size) {
         char *sz = size_to_str(mc->default_ram_size);
@@ -XXX,XX +XXX,XX @@ static void opentitan_machine_init(MachineState *machine)
         riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);
     }
 
+    riscv_boot_info_init(&boot_info, &s->soc.cpus);
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine, &s->soc.cpus,
+        riscv_load_kernel(machine, &boot_info,
                           memmap[IBEX_DEV_RAM].base,
                           false, NULL);
     }
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_init(MachineState *machine)
     SiFiveEState *s = RISCV_E_MACHINE(machine);
     MemoryRegion *sys_mem = get_system_memory();
     int i;
+    RISCVBootInfo boot_info;
 
     if (machine->ram_size != mc->default_ram_size) {
         char *sz = size_to_str(mc->default_ram_size);
@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_init(MachineState *machine)
     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                           memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
 
+    riscv_boot_info_init(&boot_info, &s->soc.cpus);
     if (machine->kernel_filename) {
-        riscv_load_kernel(machine, &s->soc.cpus,
+        riscv_load_kernel(machine, &boot_info,
                           memmap[SIFIVE_E_DEV_DTIM].base,
                           false, NULL);
     }
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     BlockBackend *blk;
     DeviceState *flash_dev, *sd_dev, *card_dev;
     qemu_irq flash_cs, sd_cs;
+    RISCVBootInfo boot_info;
 
     /* Initialize SoC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
                                                      &start_addr, NULL);
 
+    riscv_boot_info_init(&boot_info, &s->soc.u_cpus);
     if (machine->kernel_filename) {
-        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
+        kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
                                                          firmware_end_addr);
-
-        kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
-                                         kernel_start_addr, true, NULL);
+        riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+                          true, NULL);
+        kernel_entry = boot_info.image_low_addr;
     } else {
        /*
         * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
                                            memmap[SIFIVE_U_DEV_DRAM].size,
-                                           machine, &s->soc.u_cpus);
+                                           machine, &boot_info);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     if (!riscv_is_32bit(&s->soc.u_cpus)) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     char *soc_name;
     int i, base_hartid, hart_count;
     bool htif_custom_base = false;
+    RISCVBootInfo boot_info;
 
     /* Check socket count limit */
     if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base);
 
     /* Load kernel */
+    riscv_boot_info_init(&boot_info, &s->soc[0]);
     if (machine->kernel_filename) {
-        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
+        kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
                                                          firmware_end_addr);
 
-        kernel_entry = riscv_load_kernel(machine, &s->soc[0],
-                                         kernel_start_addr,
-                                         true, htif_symbol_callback);
+        riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+                          true, htif_symbol_callback);
+        kernel_entry = boot_info.image_low_addr;
     } else {
        /*
         * If dynamic firmware is used, it doesn't know where is the next mode
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base,
                                            memmap[SPIKE_DRAM].size,
-                                           machine, &s->soc[0]);
+                                           machine, &boot_info);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     /* load the reset vector */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
     uint64_t fdt_load_addr;
     uint64_t kernel_entry = 0;
     BlockBackend *pflash_blk0;
+    RISCVBootInfo boot_info;
 
     /*
      * An user provided dtb must include everything, including
@@ -XXX,XX +XXX,XX @@ static void virt_machine_done(Notifier *notifier, void *data)
         }
     }
 
+    riscv_boot_info_init(&boot_info, &s->soc[0]);
+
     if (machine->kernel_filename && !kernel_entry) {
-        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
+        kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info,
                                                          firmware_end_addr);
-
-        kernel_entry = riscv_load_kernel(machine, &s->soc[0],
-                                         kernel_start_addr, true, NULL);
+        riscv_load_kernel(machine, &boot_info, kernel_start_addr,
+                          true, NULL);
+        kernel_entry = boot_info.image_low_addr;
     }
 
     fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base,
                                            memmap[VIRT_DRAM].size,
-                                           machine, &s->soc[0]);
+                                           machine, &boot_info);
     riscv_load_fdt(fdt_load_addr, machine->fdt);
 
     /* load the reset vector */
-- 
2.47.1

From: Jim Shu <jim.shu@sifive.com>

DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVBootInfo {
     hwaddr image_low_addr;
     hwaddr image_high_addr;
 
+    hwaddr initrd_start;
+    ssize_t initrd_size;
+
     bool is_32bit;
 } RISCVBootInfo;
 
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ char *riscv_plic_hart_config_string(int hart_count)
 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
 {
     info->kernel_size = 0;
+    info->initrd_size = 0;
     info->is_32bit = riscv_is_32bit(harts);
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info)
         }
     }
 
+    info->initrd_start = start;
+    info->initrd_size = size;
+
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
     int ret = fdt_pack(ms->fdt);
     hwaddr dram_end, temp;
     int fdtsize;
+    uint64_t dtb_start, dtb_start_limit;
 
     /* Should only fail if we've built a corrupted tree */
     g_assert(ret == 0);
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
         exit(1);
     }
 
+    if (info->initrd_size) {
+        /* If initrd is successfully loaded, place DTB after it. */
+        dtb_start_limit = info->initrd_start + info->initrd_size;
+    } else if (info->kernel_size) {
+        /* If only kernel is successfully loaded, place DTB after it. */
+        dtb_start_limit = info->image_high_addr;
+    } else {
+        /* Otherwise, do not check DTB overlapping */
+        dtb_start_limit = 0;
+    }
+
     /*
      * A dram_size == 0, usually from a MemMapEntry[].size element,
      * means that the DRAM block goes all the way to ms->ram_size.
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size,
         temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
     }
 
-    return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+    dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+
+    if (dtb_start_limit && (dtb_start < dtb_start_limit)) {
+        error_report("No enough memory to place DTB after kernel/initrd");
+        exit(1);
+    }
+
+    return dtb_start;
 }
 
 /*
-- 
2.47.1

From: "Fea.Wang" <fea.wang@sifive.com>

Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564

Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-2-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_svnapot;
     bool ext_svpbmt;
     bool ext_svvptc;
+    bool ext_svukte;
     bool ext_zdinx;
     bool ext_zaamo;
     bool ext_zacas;
-- 
2.47.1

From: "Fea.Wang" <fea.wang@sifive.com>

Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.

When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
depend on hstatus[HUKTE].

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-3-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 1 +
 target/riscv/csr.c      | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
 #define SENVCFG_CBIE                       MENVCFG_CBIE
 #define SENVCFG_CBCFE                      MENVCFG_CBCFE
 #define SENVCFG_CBZE                       MENVCFG_CBZE
+#define SENVCFG_UKTE                       BIT(8)
 
 #define HENVCFG_FIOM                       MENVCFG_FIOM
 #define HENVCFG_LPE                        MENVCFG_LPE
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
         mask |= SENVCFG_SSE;
     }
 
+    if (env_archcpu(env)->cfg.ext_svukte) {
+        mask |= SENVCFG_UKTE;
+    }
+
     env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
     return RISCV_EXCP_NONE;
 }
-- 
2.47.1

From: "Fea.Wang" <fea.wang@sifive.com>

Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.

When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-4-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 1 +
 target/riscv/csr.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum {
 #define HSTATUS_VTVM         0x00100000
 #define HSTATUS_VTW          0x00200000
 #define HSTATUS_VTSR         0x00400000
+#define HSTATUS_HUKTE        0x01000000
 #define HSTATUS_VSXL         0x300000000
 
 #define HSTATUS32_WPRI       0xFF8FF87E
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
+    if (!env_archcpu(env)->cfg.ext_svukte) {
+        val = val & (~HSTATUS_HUKTE);
+    }
     env->hstatus = val;
     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
         qemu_log_mask(LOG_UNIMP,
-- 
2.47.1

From: "Fea.Wang" <fea.wang@sifive.com>

Follow the Svukte spec, do the memory access address checking

1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and execute from U mode to VU mode
4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
5. Raises a page-fault exception corresponding to the original access
type.

Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-5-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
     return TRANSLATE_SUCCESS;
 }
 
+/* Returns 'true' if a svukte address check is needed */
+static bool do_svukte_check(CPURISCVState *env, bool first_stage,
+                             int mode, bool virt)
+{
+    /* Svukte extension depends on Sv39. */
+    if (!(env_archcpu(env)->cfg.ext_svukte ||
+        !first_stage ||
+        VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
+        return false;
+    }
+
+    /*
+     * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
+     * executing HLV/HLVX/HSV in U-mode.
+     * For other cases, check senvcfg.UKTE.
+     */
+    if (env->priv == PRV_U && !env->virt_enabled && virt) {
+        if (!get_field(env->hstatus, HSTATUS_HUKTE)) {
+            return false;
+        }
+    } else if (!get_field(env->senvcfg, SENVCFG_UKTE)) {
+        return false;
+    }
+
+    /*
+     * Svukte extension is qualified only in U or VU-mode.
+     *
+     * Effective mode can be switched to U or VU-mode by:
+     *   - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
+     *   - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
+     *   - U-mode.
+     *   - VU-mode.
+     *   - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
+     */
+    if (mode != PRV_U) {
+        return false;
+    }
+
+    return true;
+}
+
+static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
+{
+    /* svukte extension excludes RV32 */
+    uint32_t sxlen = 32 * riscv_cpu_sxl(env);
+    uint64_t high_bit = addr & (1UL << (sxlen - 1));
+    return !high_bit;
+}
+
 /*
  * get_physical_address - get the physical address for this virtual address
  *
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     MemTxResult res;
     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
     int mode = mmuidx_priv(mmu_idx);
+    bool virt = mmuidx_2stage(mmu_idx);
     bool use_background = false;
     hwaddr ppn;
     int napot_bits = 0;
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE);
     bool sstack_page = false;
 
+    if (do_svukte_check(env, first_stage, mode, virt) &&
+        !check_svukte_addr(env, addr)) {
+        return TRANSLATE_FAIL;
+    }
+
     /*
      * Check if we should use the background registers for the two
      * stage translation. We don't need to check if we actually need
-- 
2.47.1

From: "Fea.Wang" <fea.wang@sifive.com>

Add "svukte" in the ISA string when svukte extension is enabled.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241203034932.25185-6-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
     ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
     ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+    ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
     ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
     ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
     ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
 
 /* These are experimental so mark with 'x-' */
 const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+    MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.47.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:

target/riscv/vector_internals.h:36:12: error: call to undeclared function 'FIELD_EX32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     36 |     return FIELD_EX32(simd_data(desc), VDATA, NF);
        |            ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241203200828.47311-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -XXX,XX +XXX,XX @@
 #define TARGET_RISCV_VECTOR_INTERNALS_H
 
 #include "qemu/bitops.h"
+#include "hw/registerfields.h"
 #include "cpu.h"
 #include "tcg/tcg-gvec-desc.h"
 #include "internals.h"
-- 
2.47.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Rather than relying on implicit includes, explicit them,
in order to avoid when refactoring unrelated headers:

target/riscv/internals.h:49:15: error: use of undeclared identifier 'PRV_S'
     49 |         ret = PRV_S;
        |               ^
  target/riscv/internals.h:93:9: error: call to undeclared function 'env_archcpu'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
     93 |     if (env_archcpu(env)->cfg.ext_zfinx) {
        |         ^
  target/riscv/internals.h:101:15: error: unknown type name 'float32'; did you mean 'float'?
    101 | static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
        |               ^~~~~~~
        |               float

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241203200828.47311-3-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/internals.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -XXX,XX +XXX,XX @@
 #ifndef RISCV_CPU_INTERNALS_H
 #define RISCV_CPU_INTERNALS_H
 
+#include "exec/cpu-common.h"
 #include "hw/registerfields.h"
+#include "fpu/softfloat-types.h"
+#include "target/riscv/cpu_bits.h"
 
 /*
  * The current MMU Modes are:
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 68c9e54bea handled a situation where a warning was being shown
when using the 'sifive_e' cpu when disabling the named extension zic64b.
It makes little sense to show user warnings for named extensions that
users can't control, and the solution taken was to disable zic64b
manually in riscv_cpu_update_named_features().

This solution won't scale well when adding more named features, and can
eventually end up repeating riscv_cpu_disable_priv_spec_isa_exts().

Change riscv_cpu_disable_priv_spec_isa_exts() to not show warnings when
disabling a named feature. This will accomplish the same thing we're
doing today while avoiding having two points where we're disabling
exts via priv_ver mismatch.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241113171755.978109-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/tcg/tcg-cpu.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
             }
 
             isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
+
+            /*
+             * Do not show user warnings for named features that users
+             * can't enable/disable in the command line. See commit
+             * 68c9e54bea for more info.
+             */
+            if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) {
+                continue;
+            }
 #ifndef CONFIG_USER_ONLY
             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
                         " because privilege spec version does not match",
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
         cpu->cfg.has_priv_1_13 = true;
     }
 
-    /* zic64b is 1.12 or later */
     cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
                           cpu->cfg.cbop_blocksize == 64 &&
-                          cpu->cfg.cboz_blocksize == 64 &&
-                          cpu->cfg.has_priv_1_12;
+                          cpu->cfg.cboz_blocksize == 64;
 }
 
 static void riscv_cpu_validate_g(RISCVCPU *cpu)
-- 
2.47.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

ssstateen is defined in RVA22 as:

"Supervisor-mode view of the state-enable extension. The supervisor-mode
(sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers
must be provided."

Add ssstateen as a named feature that is available if we also have
smstateen.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20241113171755.978109-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     | 1 +
 target/riscv/cpu.c         | 2 ++
 target/riscv/tcg/tcg-cpu.c | 9 ++++++++-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     /* Named features  */
     bool ext_svade;
     bool ext_zic64b;
+    bool ext_ssstateen;
 
     /*
      * Always 'true' booleans for named features
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
     ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
     ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
+    ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
     ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
     ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
  */
 const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
     MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
+    MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
 
     DEFINE_PROP_END_OF_LIST(),
 };
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset)
       * All other named features are already enabled
       * in riscv_tcg_cpu_instance_init().
       */
-    if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) {
+    switch (feat_offset) {
+    case CPU_CFG_OFFSET(ext_zic64b):
         cpu->cfg.cbom_blocksize = 64;
         cpu->cfg.cbop_blocksize = 64;
         cpu->cfg.cboz_blocksize = 64;
+        break;
+    case CPU_CFG_OFFSET(ext_ssstateen):
+        cpu->cfg.ext_smstateen = true;
+        break;
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
     cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
                           cpu->cfg.cbop_blocksize == 64 &&
                           cpu->cfg.cboz_blocksize == 64;
+
+    cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen;
 }
 
 static void riscv_cpu_validate_g(RISCVCPU *cpu)
-- 
2.47.1

From: MollyChen <xiaoou@iscas.ac.cn>

Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview

Signed-off-by: MollyChen <xiaoou@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241205073622.46052-1-xiaoou@iscas.ac.cn>
[ Changes by AF
 - Fixup code formatting
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu-qom.h |  1 +
 target/riscv/cpu.c     | 30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+)