[PULL 00/30] riscv-to-apply queue
[PULL v2 00/31] riscv-to-apply queue
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The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:
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From: Alistair Francis <alistair.francis@wdc.com>
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Merge remote-tracking branch 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging (2020-09-08 21:21:13 +0100)
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The following changes since commit da5006445a92bb7801f54a93452fac63ca2f634c:
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Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2022-04-21 15:16:52 -0700)
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are available in the Git repository at:
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are available in the Git repository at:
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
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git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220422-1
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for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:
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for you to fetch changes up to faee5441a038898f64b335dbaecab102ba406552:
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hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19 -0700)
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hw/riscv: boot: Support 64bit fdt address. (2022-04-22 10:35:16 +1000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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This PR includes multiple fixes and features for RISC-V:
16
First RISC-V PR for QEMU 7.1
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- Fixes a bug in printing trap causes
17
16
- Allows 16-bit writes to the SiFive test device. This fixes the
18
* Add support for Ibex SPI to OpenTitan
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failure to reboot the RISC-V virt machine
19
* Add support for privileged spec version 1.12.0
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- Support for the Microchip PolarFire SoC and Icicle Kit
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* Use privileged spec version 1.12.0 for virt machine by default
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- A reafactor of RISC-V code out of hw/riscv
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* Allow software access to MIP SEIP
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* Add initial support for the Sdtrig extension
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* Optimisations for vector extensions
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* Improvements to the misa ISA string
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* Add isa extenstion strings to the device tree
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* Don't allow `-bios` options with KVM machines
27
* Fix NAPOT range computation overflow
28
* Fix DT property mmu-type when CPU mmu option is disabled
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* Make RISC-V ACLINT mtime MMIO register writable
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* Add and enable native debug feature
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* Support 64bit fdt address.
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----------------------------------------------------------------
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----------------------------------------------------------------
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Bin Meng (28):
34
Alistair Francis (2):
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target/riscv: cpu: Add a new 'resetvec' property
35
target/riscv: cpu: Fixup indentation
24
hw/riscv: hart: Add a new 'resetvec' property
36
target/riscv: Allow software access to MIP SEIP
25
target/riscv: cpu: Set reset vector based on the configured property value
26
hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
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hw/char: Add Microchip PolarFire SoC MMUART emulation
28
hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
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hw/sd: Add Cadence SDHCI emulation
30
hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
31
hw/dma: Add SiFive platform DMA controller emulation
32
hw/riscv: microchip_pfsoc: Connect a DMA controller
33
hw/net: cadence_gem: Add a new 'phy-addr' property
34
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
35
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
36
hw/riscv: microchip_pfsoc: Hook GPIO controllers
37
hw/riscv: clint: Avoid using hard-coded timebase frequency
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hw/riscv: sifive_u: Connect a DMA controller
39
hw/riscv: Move sifive_e_prci model to hw/misc
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hw/riscv: Move sifive_u_prci model to hw/misc
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hw/riscv: Move sifive_u_otp model to hw/misc
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hw/riscv: Move sifive_gpio model to hw/gpio
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hw/riscv: Move sifive_clint model to hw/intc
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hw/riscv: Move sifive_plic model to hw/intc
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hw/riscv: Move riscv_htif model to hw/char
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hw/riscv: Move sifive_uart model to hw/char
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hw/riscv: Move sifive_test model to hw/misc
48
hw/riscv: Always build riscv_hart.c
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hw/riscv: Drop CONFIG_SIFIVE
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hw/riscv: Sort the Kconfig options in alphabetical order
51
37
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Nathan Chancellor (1):
38
Atish Patra (7):
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riscv: sifive_test: Allow 16-bit writes to memory region
39
target/riscv: Define simpler privileged spec version numbering
40
target/riscv: Add the privileged spec version 1.12.0
41
target/riscv: Introduce privilege version field in the CSR ops.
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target/riscv: Add support for mconfigptr
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target/riscv: Add *envcfg* CSRs support
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target/riscv: Enable privileged spec version 1.12
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target/riscv: Add isa extenstion strings to the device tree
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46
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Yifei Jiang (1):
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Bin Meng (7):
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target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
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target/riscv: Add initial support for the Sdtrig extension
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target/riscv: debug: Implement debug related TCGCPUOps
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target/riscv: cpu: Add a config option for native debug
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target/riscv: csr: Hook debug CSR read/write
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target/riscv: machine: Add debug state description
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target/riscv: cpu: Enable native debug feature
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hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
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default-configs/riscv64-softmmu.mak | 1 +
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Dylan Jhong (1):
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{include/hw/riscv => hw/intc}/sifive_plic.h | 0
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hw/riscv: boot: Support 64bit fdt address.
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hw/riscv/trace.h | 1 -
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include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++
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include/hw/{riscv => char}/riscv_htif.h | 0
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include/hw/{riscv => char}/sifive_uart.h | 0
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include/hw/dma/sifive_pdma.h | 57 ++++
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include/hw/{riscv => gpio}/sifive_gpio.h | 0
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include/hw/{riscv => intc}/sifive_clint.h | 4 +-
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include/hw/{riscv => misc}/sifive_e_prci.h | 0
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include/hw/{riscv => misc}/sifive_test.h | 0
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include/hw/{riscv => misc}/sifive_u_otp.h | 0
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include/hw/{riscv => misc}/sifive_u_prci.h | 0
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include/hw/net/cadence_gem.h | 2 +
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include/hw/riscv/microchip_pfsoc.h | 133 +++++++++
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include/hw/riscv/riscv_hart.h | 1 +
74
include/hw/riscv/sifive_e.h | 2 +-
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include/hw/riscv/sifive_u.h | 17 +-
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include/hw/sd/cadence_sdhci.h | 47 +++
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target/riscv/cpu.h | 8 +-
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hw/arm/xilinx_zynq.c | 1 +
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hw/arm/xlnx-versal.c | 1 +
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hw/arm/xlnx-zynqmp.c | 2 +
81
hw/char/mchp_pfsoc_mmuart.c | 86 ++++++
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hw/{riscv => char}/riscv_htif.c | 2 +-
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hw/{riscv => char}/sifive_uart.c | 2 +-
84
hw/dma/sifive_pdma.c | 313 ++++++++++++++++++++
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hw/{riscv => gpio}/sifive_gpio.c | 2 +-
86
hw/{riscv => intc}/sifive_clint.c | 28 +-
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hw/{riscv => intc}/sifive_plic.c | 2 +-
88
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
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hw/{riscv => misc}/sifive_test.c | 4 +-
90
hw/{riscv => misc}/sifive_u_otp.c | 2 +-
91
hw/{riscv => misc}/sifive_u_prci.c | 2 +-
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hw/net/cadence_gem.c | 7 +-
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hw/riscv/microchip_pfsoc.c | 437 ++++++++++++++++++++++++++++
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hw/riscv/opentitan.c | 1 +
95
hw/riscv/riscv_hart.c | 3 +
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hw/riscv/sifive_e.c | 12 +-
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hw/riscv/sifive_u.c | 41 ++-
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hw/riscv/spike.c | 7 +-
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hw/riscv/virt.c | 9 +-
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hw/sd/cadence_sdhci.c | 193 ++++++++++++
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target/riscv/cpu.c | 19 +-
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target/riscv/cpu_helper.c | 8 +-
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target/riscv/csr.c | 4 +-
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MAINTAINERS | 9 +
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hw/char/Kconfig | 9 +
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hw/char/meson.build | 3 +
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hw/dma/Kconfig | 3 +
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hw/dma/meson.build | 1 +
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hw/gpio/Kconfig | 3 +
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hw/gpio/meson.build | 1 +
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hw/gpio/trace-events | 6 +
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hw/intc/Kconfig | 6 +
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hw/intc/meson.build | 2 +
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hw/misc/Kconfig | 12 +
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hw/misc/meson.build | 6 +
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hw/riscv/Kconfig | 70 +++--
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hw/riscv/meson.build | 12 +-
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hw/riscv/trace-events | 7 -
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hw/sd/Kconfig | 4 +
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hw/sd/meson.build | 1 +
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meson.build | 1 -
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64 files changed, 1575 insertions(+), 105 deletions(-)
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rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
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delete mode 100644 hw/riscv/trace.h
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create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
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rename include/hw/{riscv => char}/riscv_htif.h (100%)
127
rename include/hw/{riscv => char}/sifive_uart.h (100%)
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create mode 100644 include/hw/dma/sifive_pdma.h
129
rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
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rename include/hw/{riscv => intc}/sifive_clint.h (92%)
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rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
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rename include/hw/{riscv => misc}/sifive_test.h (100%)
133
rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
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rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
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create mode 100644 include/hw/riscv/microchip_pfsoc.h
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create mode 100644 include/hw/sd/cadence_sdhci.h
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create mode 100644 hw/char/mchp_pfsoc_mmuart.c
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rename hw/{riscv => char}/riscv_htif.c (99%)
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rename hw/{riscv => char}/sifive_uart.c (99%)
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create mode 100644 hw/dma/sifive_pdma.c
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rename hw/{riscv => gpio}/sifive_gpio.c (99%)
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rename hw/{riscv => intc}/sifive_clint.c (90%)
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rename hw/{riscv => intc}/sifive_plic.c (99%)
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rename hw/{riscv => misc}/sifive_e_prci.c (99%)
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rename hw/{riscv => misc}/sifive_test.c (97%)
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rename hw/{riscv => misc}/sifive_u_otp.c (99%)
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rename hw/{riscv => misc}/sifive_u_prci.c (99%)
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create mode 100644 hw/riscv/microchip_pfsoc.c
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create mode 100644 hw/sd/cadence_sdhci.c
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delete mode 100644 hw/riscv/trace-events
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59
Frank Chang (3):
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hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
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hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
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hw/intc: Make RISC-V ACLINT mtime MMIO register writable
63
64
Jim Shu (1):
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hw/intc: riscv_aclint: Add reset function of ACLINT devices
66
67
Nicolas Pitre (1):
68
target/riscv/pmp: fix NAPOT range computation overflow
69
70
Niklas Cassel (1):
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hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
72
73
Ralf Ramsauer (1):
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hw/riscv: virt: Exit if the user provided -bios in combination with KVM
75
76
Richard Henderson (1):
77
target/riscv: Use cpu_loop_exit_restore directly from mmu faults
78
79
Tsukasa OI (1):
80
target/riscv: misa to ISA string conversion fix
81
82
Weiwei Li (3):
83
target/riscv: optimize condition assign for scale < 0
84
target/riscv: optimize helper for vmv<nr>r.v
85
target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
86
87
Wilfred Mallawa (2):
88
hw/ssi: Add Ibex SPI device model
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riscv: opentitan: Connect opentitan SPI Host
90
91
include/hw/core/tcg-cpu-ops.h | 1 +
92
include/hw/intc/riscv_aclint.h | 1 +
93
include/hw/riscv/boot.h | 4 +-
94
include/hw/riscv/opentitan.h | 30 +-
95
include/hw/ssi/ibex_spi_host.h | 94 +++++
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target/riscv/cpu.h | 40 ++-
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target/riscv/cpu_bits.h | 40 +++
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target/riscv/debug.h | 114 ++++++
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target/riscv/helper.h | 5 +-
100
hw/intc/riscv_aclint.c | 144 ++++++--
101
hw/riscv/boot.c | 12 +-
102
hw/riscv/opentitan.c | 36 +-
103
hw/riscv/virt.c | 24 +-
104
hw/ssi/ibex_spi_host.c | 612 ++++++++++++++++++++++++++++++++
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target/riscv/cpu.c | 120 ++++++-
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target/riscv/cpu_helper.c | 10 +-
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target/riscv/csr.c | 282 +++++++++++++--
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target/riscv/debug.c | 441 +++++++++++++++++++++++
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target/riscv/machine.c | 55 +++
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target/riscv/pmp.c | 14 +-
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target/riscv/vector_helper.c | 31 +-
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target/riscv/insn_trans/trans_rvv.c.inc | 25 +-
113
hw/ssi/meson.build | 1 +
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hw/ssi/trace-events | 7 +
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target/riscv/meson.build | 1 +
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25 files changed, 1971 insertions(+), 173 deletions(-)
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create mode 100644 include/hw/ssi/ibex_spi_host.h
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create mode 100644 target/riscv/debug.h
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create mode 100644 hw/ssi/ibex_spi_host.c
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create mode 100644 target/riscv/debug.c
diff view generated by jsdifflib
[PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation
[PULL v2 01/31] hw/ssi: Add Ibex SPI device model
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From: Bin Meng <bin.meng@windriver.com>
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From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
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Microchip PolarFire SoC MMUART is ns16550 compatible, with some
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Adds the SPI_HOST device model for ibex. The device specification is as per
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additional registers. Create a simple MMUART model built on top
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[1]. The model has been tested on opentitan with spi_host unit tests
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of the existing ns16550 model.
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written for TockOS.
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6
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Signed-off-by: Bin Meng <bin.meng@windriver.com>
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[1] https://docs.opentitan.org/hw/ip/spi_host/doc/
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Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
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Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Message-Id: <20220303045426.511588-1-alistair.francis@opensource.wdc.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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---
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---
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include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
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include/hw/ssi/ibex_spi_host.h | 94 +++++
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hw/char/mchp_pfsoc_mmuart.c | 86 +++++++++++++++++++++++++++++
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hw/ssi/ibex_spi_host.c | 612 +++++++++++++++++++++++++++++++++
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MAINTAINERS | 2 +
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hw/ssi/meson.build | 1 +
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hw/char/Kconfig | 3 +
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hw/ssi/trace-events | 7 +
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hw/char/meson.build | 1 +
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4 files changed, 714 insertions(+)
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5 files changed, 153 insertions(+)
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create mode 100644 include/hw/ssi/ibex_spi_host.h
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create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
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create mode 100644 hw/ssi/ibex_spi_host.c
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create mode 100644 hw/char/mchp_pfsoc_mmuart.c
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diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
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diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h
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new file mode 100644
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new file mode 100644
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index XXXXXXX..XXXXXXX
25
index XXXXXXX..XXXXXXX
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--- /dev/null
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--- /dev/null
25
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
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+++ b/include/hw/ssi/ibex_spi_host.h
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@@ -XXX,XX +XXX,XX @@
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@@ -XXX,XX +XXX,XX @@
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+
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+/*
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+/*
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+ * Microchip PolarFire SoC MMUART emulation
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+ * QEMU model of the Ibex SPI Controller
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+ *
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+ * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/
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+ * Copyright (c) 2020 Wind River Systems, Inc.
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+ *
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+ *
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+ * Copyright (C) 2022 Western Digital
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+ * Author:
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+ * Bin Meng <bin.meng@windriver.com>
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+ *
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a copy
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+ * Permission is hereby granted, free of charge, to any person obtaining a copy
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+ * of this software and associated documentation files (the "Software"), to deal
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+ * of this software and associated documentation files (the "Software"), to deal
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+ * in the Software without restriction, including without limitation the rights
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+ * in the Software without restriction, including without limitation the rights
38
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
...
...
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+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
50
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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+ * THE SOFTWARE.
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+ * THE SOFTWARE.
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+ */
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+ */
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+
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+
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+#ifndef HW_MCHP_PFSOC_MMUART_H
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+#ifndef IBEX_SPI_HOST_H
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+#define HW_MCHP_PFSOC_MMUART_H
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+#define IBEX_SPI_HOST_H
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+
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+
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+#include "hw/char/serial.h"
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+#include "hw/sysbus.h"
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+
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+#include "hw/hw.h"
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+#define MCHP_PFSOC_MMUART_REG_SIZE 52
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+#include "hw/ssi/ssi.h"
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+
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+#include "qemu/fifo8.h"
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+typedef struct MchpPfSoCMMUartState {
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+#include "qom/object.h"
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+ MemoryRegion iomem;
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+#include "hw/registerfields.h"
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+ hwaddr base;
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+#include "qemu/timer.h"
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+ qemu_irq irq;
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+
65
+
66
+#define TYPE_IBEX_SPI_HOST "ibex-spi"
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+ SerialMM *serial;
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+#define IBEX_SPI_HOST(obj) \
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+
68
+ OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST)
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+ uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
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+
69
+} MchpPfSoCMMUartState;
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+/* SPI Registers */
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+
71
+#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw */
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+/**
72
+#define IBEX_SPI_HOST_INTR_ENABLE (0x04 / 4) /* rw */
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+ * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
73
+#define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */
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+ *
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+#define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */
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+ * This is a helper routine for board to create a MMUART device that is
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+#define IBEX_SPI_HOST_CONTROL (0x10 / 4) /* rw */
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+ * compatible with Microchip PolarFire SoC.
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+#define IBEX_SPI_HOST_STATUS (0x14 / 4) /* ro */
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+ *
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+#define IBEX_SPI_HOST_CONFIGOPTS (0x18 / 4) /* rw */
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+ * @sysmem: system memory region to map
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+#define IBEX_SPI_HOST_CSID (0x1c / 4) /* rw */
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+ * @base: base address of the MMUART registers
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+#define IBEX_SPI_HOST_COMMAND (0x20 / 4) /* wo */
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+ * @irq: IRQ number of the MMUART device
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+/* RX/TX Modelled by FIFO */
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+ * @chr: character device to associate to
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+#define IBEX_SPI_HOST_RXDATA (0x24 / 4)
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+ *
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+#define IBEX_SPI_HOST_TXDATA (0x28 / 4)
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+ * @return: a pointer to the device specific control structure
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+
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+ */
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+#define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */
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+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
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+#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw */
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+ hwaddr base, qemu_irq irq, Chardev *chr);
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+#define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */
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+
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+
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+#endif /* HW_MCHP_PFSOC_MMUART_H */
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+/* FIFO Len in Bytes */
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diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
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+#define IBEX_SPI_HOST_TXFIFO_LEN 288
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+#define IBEX_SPI_HOST_RXFIFO_LEN 256
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+
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+/* Max Register (Based on addr) */
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+#define IBEX_SPI_HOST_MAX_REGS (IBEX_SPI_HOST_EVENT_ENABLE + 1)
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+
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+/* MISC */
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+#define TX_INTERRUPT_TRIGGER_DELAY_NS 100
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+#define BIDIRECTIONAL_TRANSFER 3
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+
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+typedef struct {
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+ /* <private> */
101
+ SysBusDevice parent_obj;
102
+
103
+ /* <public> */
104
+ MemoryRegion mmio;
105
+ uint32_t regs[IBEX_SPI_HOST_MAX_REGS];
106
+ /* Multi-reg that sets config opts per CS */
107
+ uint32_t *config_opts;
108
+ Fifo8 rx_fifo;
109
+ Fifo8 tx_fifo;
110
+ QEMUTimer *fifo_trigger_handle;
111
+
112
+ qemu_irq event;
113
+ qemu_irq host_err;
114
+ uint32_t num_cs;
115
+ qemu_irq *cs_lines;
116
+ SSIBus *ssi;
117
+
118
+ /* Used to track the init status, for replicating TXDATA ghost writes */
119
+ bool init_status;
120
+} IbexSPIHostState;
121
+
122
+#endif
123
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
89
new file mode 100644
124
new file mode 100644
90
index XXXXXXX..XXXXXXX
125
index XXXXXXX..XXXXXXX
91
--- /dev/null
126
--- /dev/null
92
+++ b/hw/char/mchp_pfsoc_mmuart.c
127
+++ b/hw/ssi/ibex_spi_host.c
93
@@ -XXX,XX +XXX,XX @@
128
@@ -XXX,XX +XXX,XX @@
94
+/*
129
+/*
95
+ * Microchip PolarFire SoC MMUART emulation
130
+ * QEMU model of the Ibex SPI Controller
96
+ *
131
+ * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/
97
+ * Copyright (c) 2020 Wind River Systems, Inc.
132
+ *
98
+ *
133
+ * Copyright (C) 2022 Western Digital
99
+ * Author:
134
+ *
100
+ * Bin Meng <bin.meng@windriver.com>
135
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
101
+ *
136
+ * of this software and associated documentation files (the "Software"), to deal
102
+ * This program is free software; you can redistribute it and/or
137
+ * in the Software without restriction, including without limitation the rights
103
+ * modify it under the terms of the GNU General Public License as
138
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
104
+ * published by the Free Software Foundation; either version 2 or
139
+ * copies of the Software, and to permit persons to whom the Software is
105
+ * (at your option) version 3 of the License.
140
+ * furnished to do so, subject to the following conditions:
106
+ *
141
+ *
107
+ * This program is distributed in the hope that it will be useful,
142
+ * The above copyright notice and this permission notice shall be included in
108
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
143
+ * all copies or substantial portions of the Software.
109
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
144
+ *
110
+ * GNU General Public License for more details.
145
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
111
+ *
146
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
112
+ * You should have received a copy of the GNU General Public License along
147
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
113
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
148
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
149
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
150
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
151
+ * THE SOFTWARE.
114
+ */
152
+ */
115
+
153
+
116
+#include "qemu/osdep.h"
154
+#include "qemu/osdep.h"
117
+#include "qemu/log.h"
155
+#include "qemu/log.h"
118
+#include "chardev/char.h"
156
+#include "qemu/module.h"
119
+#include "exec/address-spaces.h"
157
+#include "hw/ssi/ibex_spi_host.h"
120
+#include "hw/char/mchp_pfsoc_mmuart.h"
158
+#include "hw/irq.h"
121
+
159
+#include "hw/qdev-properties.h"
122
+static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
160
+#include "hw/qdev-properties-system.h"
123
+{
161
+#include "migration/vmstate.h"
124
+ MchpPfSoCMMUartState *s = opaque;
162
+#include "trace.h"
125
+
163
+
126
+ if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
164
+REG32(INTR_STATE, 0x00)
127
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
165
+ FIELD(INTR_STATE, ERROR, 0, 1)
128
+ __func__, addr);
166
+ FIELD(INTR_STATE, SPI_EVENT, 1, 1)
129
+ return 0;
167
+REG32(INTR_ENABLE, 0x04)
168
+ FIELD(INTR_ENABLE, ERROR, 0, 1)
169
+ FIELD(INTR_ENABLE, SPI_EVENT, 1, 1)
170
+REG32(INTR_TEST, 0x08)
171
+ FIELD(INTR_TEST, ERROR, 0, 1)
172
+ FIELD(INTR_TEST, SPI_EVENT, 1, 1)
173
+REG32(ALERT_TEST, 0x0c)
174
+ FIELD(ALERT_TEST, FETAL_TEST, 0, 1)
175
+REG32(CONTROL, 0x10)
176
+ FIELD(CONTROL, RX_WATERMARK, 0, 8)
177
+ FIELD(CONTROL, TX_WATERMARK, 1, 8)
178
+ FIELD(CONTROL, OUTPUT_EN, 29, 1)
179
+ FIELD(CONTROL, SW_RST, 30, 1)
180
+ FIELD(CONTROL, SPIEN, 31, 1)
181
+REG32(STATUS, 0x14)
182
+ FIELD(STATUS, TXQD, 0, 8)
183
+ FIELD(STATUS, RXQD, 18, 8)
184
+ FIELD(STATUS, CMDQD, 16, 3)
185
+ FIELD(STATUS, RXWM, 20, 1)
186
+ FIELD(STATUS, BYTEORDER, 22, 1)
187
+ FIELD(STATUS, RXSTALL, 23, 1)
188
+ FIELD(STATUS, RXEMPTY, 24, 1)
189
+ FIELD(STATUS, RXFULL, 25, 1)
190
+ FIELD(STATUS, TXWM, 26, 1)
191
+ FIELD(STATUS, TXSTALL, 27, 1)
192
+ FIELD(STATUS, TXEMPTY, 28, 1)
193
+ FIELD(STATUS, TXFULL, 29, 1)
194
+ FIELD(STATUS, ACTIVE, 30, 1)
195
+ FIELD(STATUS, READY, 31, 1)
196
+REG32(CONFIGOPTS, 0x18)
197
+ FIELD(CONFIGOPTS, CLKDIV_0, 0, 16)
198
+ FIELD(CONFIGOPTS, CSNIDLE_0, 16, 4)
199
+ FIELD(CONFIGOPTS, CSNTRAIL_0, 20, 4)
200
+ FIELD(CONFIGOPTS, CSNLEAD_0, 24, 4)
201
+ FIELD(CONFIGOPTS, FULLCYC_0, 29, 1)
202
+ FIELD(CONFIGOPTS, CPHA_0, 30, 1)
203
+ FIELD(CONFIGOPTS, CPOL_0, 31, 1)
204
+REG32(CSID, 0x1c)
205
+ FIELD(CSID, CSID, 0, 32)
206
+REG32(COMMAND, 0x20)
207
+ FIELD(COMMAND, LEN, 0, 8)
208
+ FIELD(COMMAND, CSAAT, 9, 1)
209
+ FIELD(COMMAND, SPEED, 10, 2)
210
+ FIELD(COMMAND, DIRECTION, 12, 2)
211
+REG32(ERROR_ENABLE, 0x2c)
212
+ FIELD(ERROR_ENABLE, CMDBUSY, 0, 1)
213
+ FIELD(ERROR_ENABLE, OVERFLOW, 1, 1)
214
+ FIELD(ERROR_ENABLE, UNDERFLOW, 2, 1)
215
+ FIELD(ERROR_ENABLE, CMDINVAL, 3, 1)
216
+ FIELD(ERROR_ENABLE, CSIDINVAL, 4, 1)
217
+REG32(ERROR_STATUS, 0x30)
218
+ FIELD(ERROR_STATUS, CMDBUSY, 0, 1)
219
+ FIELD(ERROR_STATUS, OVERFLOW, 1, 1)
220
+ FIELD(ERROR_STATUS, UNDERFLOW, 2, 1)
221
+ FIELD(ERROR_STATUS, CMDINVAL, 3, 1)
222
+ FIELD(ERROR_STATUS, CSIDINVAL, 4, 1)
223
+ FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1)
224
+REG32(EVENT_ENABLE, 0x30)
225
+ FIELD(EVENT_ENABLE, RXFULL, 0, 1)
226
+ FIELD(EVENT_ENABLE, TXEMPTY, 1, 1)
227
+ FIELD(EVENT_ENABLE, RXWM, 2, 1)
228
+ FIELD(EVENT_ENABLE, TXWM, 3, 1)
229
+ FIELD(EVENT_ENABLE, READY, 4, 1)
230
+ FIELD(EVENT_ENABLE, IDLE, 5, 1)
231
+
232
+static inline uint8_t div4_round_up(uint8_t dividend)
233
+{
234
+ return (dividend + 3) / 4;
235
+}
236
+
237
+static void ibex_spi_rxfifo_reset(IbexSPIHostState *s)
238
+{
239
+ /* Empty the RX FIFO and assert RXEMPTY */
240
+ fifo8_reset(&s->rx_fifo);
241
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXFULL_MASK;
242
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXEMPTY_MASK;
243
+}
244
+
245
+static void ibex_spi_txfifo_reset(IbexSPIHostState *s)
246
+{
247
+ /* Empty the TX FIFO and assert TXEMPTY */
248
+ fifo8_reset(&s->tx_fifo);
249
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXFULL_MASK;
250
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXEMPTY_MASK;
251
+}
252
+
253
+static void ibex_spi_host_reset(DeviceState *dev)
254
+{
255
+ IbexSPIHostState *s = IBEX_SPI_HOST(dev);
256
+ trace_ibex_spi_host_reset("Resetting Ibex SPI");
257
+
258
+ /* SPI Host Register Reset */
259
+ s->regs[IBEX_SPI_HOST_INTR_STATE] = 0x00;
260
+ s->regs[IBEX_SPI_HOST_INTR_ENABLE] = 0x00;
261
+ s->regs[IBEX_SPI_HOST_INTR_TEST] = 0x00;
262
+ s->regs[IBEX_SPI_HOST_ALERT_TEST] = 0x00;
263
+ s->regs[IBEX_SPI_HOST_CONTROL] = 0x7f;
264
+ s->regs[IBEX_SPI_HOST_STATUS] = 0x00;
265
+ s->regs[IBEX_SPI_HOST_CONFIGOPTS] = 0x00;
266
+ s->regs[IBEX_SPI_HOST_CSID] = 0x00;
267
+ s->regs[IBEX_SPI_HOST_COMMAND] = 0x00;
268
+ /* RX/TX Modelled by FIFO */
269
+ s->regs[IBEX_SPI_HOST_RXDATA] = 0x00;
270
+ s->regs[IBEX_SPI_HOST_TXDATA] = 0x00;
271
+
272
+ s->regs[IBEX_SPI_HOST_ERROR_ENABLE] = 0x1F;
273
+ s->regs[IBEX_SPI_HOST_ERROR_STATUS] = 0x00;
274
+ s->regs[IBEX_SPI_HOST_EVENT_ENABLE] = 0x00;
275
+
276
+ ibex_spi_rxfifo_reset(s);
277
+ ibex_spi_txfifo_reset(s);
278
+
279
+ s->init_status = true;
280
+ return;
281
+}
282
+
283
+/*
284
+ * Check if we need to trigger an interrupt.
285
+ * The two interrupts lines (host_err and event) can
286
+ * be enabled separately in 'IBEX_SPI_HOST_INTR_ENABLE'.
287
+ *
288
+ * Interrupts are triggered based on the ones
289
+ * enabled in the `IBEX_SPI_HOST_EVENT_ENABLE` and `IBEX_SPI_HOST_ERROR_ENABLE`.
290
+ */
291
+static void ibex_spi_host_irq(IbexSPIHostState *s)
292
+{
293
+ bool error_en = s->regs[IBEX_SPI_HOST_INTR_ENABLE]
294
+ & R_INTR_ENABLE_ERROR_MASK;
295
+ bool event_en = s->regs[IBEX_SPI_HOST_INTR_ENABLE]
296
+ & R_INTR_ENABLE_SPI_EVENT_MASK;
297
+ bool err_pending = s->regs[IBEX_SPI_HOST_INTR_STATE]
298
+ & R_INTR_STATE_ERROR_MASK;
299
+ bool status_pending = s->regs[IBEX_SPI_HOST_INTR_STATE]
300
+ & R_INTR_STATE_SPI_EVENT_MASK;
301
+ int err_irq = 0, event_irq = 0;
302
+
303
+ /* Error IRQ enabled and Error IRQ Cleared*/
304
+ if (error_en && !err_pending) {
305
+ /* Event enabled, Interrupt Test Error */
306
+ if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) {
307
+ err_irq = 1;
308
+ } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
309
+ & R_ERROR_ENABLE_CMDBUSY_MASK) &&
310
+ s->regs[IBEX_SPI_HOST_ERROR_STATUS]
311
+ & R_ERROR_STATUS_CMDBUSY_MASK) {
312
+ /* Wrote to COMMAND when not READY */
313
+ err_irq = 1;
314
+ } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
315
+ & R_ERROR_ENABLE_CMDINVAL_MASK) &&
316
+ s->regs[IBEX_SPI_HOST_ERROR_STATUS]
317
+ & R_ERROR_STATUS_CMDINVAL_MASK) {
318
+ /* Invalid command segment */
319
+ err_irq = 1;
320
+ } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE]
321
+ & R_ERROR_ENABLE_CSIDINVAL_MASK) &&
322
+ s->regs[IBEX_SPI_HOST_ERROR_STATUS]
323
+ & R_ERROR_STATUS_CSIDINVAL_MASK) {
324
+ /* Invalid value for CSID */
325
+ err_irq = 1;
326
+ }
327
+ if (err_irq) {
328
+ s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_ERROR_MASK;
329
+ }
330
+ qemu_set_irq(s->host_err, err_irq);
130
+ }
331
+ }
131
+
332
+
132
+ return s->reg[addr / sizeof(uint32_t)];
333
+ /* Event IRQ Enabled and Event IRQ Cleared */
133
+}
334
+ if (event_en && !status_pending) {
134
+
335
+ if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_SPI_EVENT_MASK) {
135
+static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
336
+ /* Event enabled, Interrupt Test Event */
136
+ uint64_t value, unsigned size)
337
+ event_irq = 1;
137
+{
338
+ } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
138
+ MchpPfSoCMMUartState *s = opaque;
339
+ & R_EVENT_ENABLE_READY_MASK) &&
139
+ uint32_t val32 = (uint32_t)value;
340
+ (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) {
140
+
341
+ /* SPI Host ready for next command */
141
+ if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
342
+ event_irq = 1;
142
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
343
+ } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
143
+ " v=0x%x\n", __func__, addr, val32);
344
+ & R_EVENT_ENABLE_TXEMPTY_MASK) &&
144
+ return;
345
+ (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_TXEMPTY_MASK)) {
346
+ /* SPI TXEMPTY, TXFIFO drained */
347
+ event_irq = 1;
348
+ } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE]
349
+ & R_EVENT_ENABLE_RXFULL_MASK) &&
350
+ (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_RXFULL_MASK)) {
351
+ /* SPI RXFULL, RXFIFO full */
352
+ event_irq = 1;
353
+ }
354
+ if (event_irq) {
355
+ s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_SPI_EVENT_MASK;
356
+ }
357
+ qemu_set_irq(s->event, event_irq);
145
+ }
358
+ }
146
+
359
+}
147
+ s->reg[addr / sizeof(uint32_t)] = val32;
360
+
148
+}
361
+static void ibex_spi_host_transfer(IbexSPIHostState *s)
149
+
362
+{
150
+static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
363
+ uint32_t rx, tx;
151
+ .read = mchp_pfsoc_mmuart_read,
364
+ /* Get num of one byte transfers */
152
+ .write = mchp_pfsoc_mmuart_write,
365
+ uint8_t segment_len = ((s->regs[IBEX_SPI_HOST_COMMAND] & R_COMMAND_LEN_MASK)
366
+ >> R_COMMAND_LEN_SHIFT);
367
+ while (segment_len > 0) {
368
+ if (fifo8_is_empty(&s->tx_fifo)) {
369
+ /* Assert Stall */
370
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXSTALL_MASK;
371
+ break;
372
+ } else if (fifo8_is_full(&s->rx_fifo)) {
373
+ /* Assert Stall */
374
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXSTALL_MASK;
375
+ break;
376
+ } else {
377
+ tx = fifo8_pop(&s->tx_fifo);
378
+ }
379
+
380
+ rx = ssi_transfer(s->ssi, tx);
381
+
382
+ trace_ibex_spi_host_transfer(tx, rx);
383
+
384
+ if (!fifo8_is_full(&s->rx_fifo)) {
385
+ fifo8_push(&s->rx_fifo, rx);
386
+ } else {
387
+ /* Assert RXFULL */
388
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXFULL_MASK;
389
+ }
390
+ --segment_len;
391
+ }
392
+
393
+ /* Assert Ready */
394
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_READY_MASK;
395
+ /* Set RXQD */
396
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXQD_MASK;
397
+ s->regs[IBEX_SPI_HOST_STATUS] |= (R_STATUS_RXQD_MASK
398
+ & div4_round_up(segment_len));
399
+ /* Set TXQD */
400
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXQD_MASK;
401
+ s->regs[IBEX_SPI_HOST_STATUS] |= (fifo8_num_used(&s->tx_fifo) / 4)
402
+ & R_STATUS_TXQD_MASK;
403
+ /* Clear TXFULL */
404
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXFULL_MASK;
405
+ /* Assert TXEMPTY and drop remaining bytes that exceed segment_len */
406
+ ibex_spi_txfifo_reset(s);
407
+ /* Reset RXEMPTY */
408
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXEMPTY_MASK;
409
+
410
+ ibex_spi_host_irq(s);
411
+}
412
+
413
+static uint64_t ibex_spi_host_read(void *opaque, hwaddr addr,
414
+ unsigned int size)
415
+{
416
+ IbexSPIHostState *s = opaque;
417
+ uint32_t rc = 0;
418
+ uint8_t rx_byte = 0;
419
+
420
+ trace_ibex_spi_host_read(addr, size);
421
+
422
+ /* Match reg index */
423
+ addr = addr >> 2;
424
+ switch (addr) {
425
+ /* Skipping any W/O registers */
426
+ case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE:
427
+ case IBEX_SPI_HOST_CONTROL...IBEX_SPI_HOST_STATUS:
428
+ rc = s->regs[addr];
429
+ break;
430
+ case IBEX_SPI_HOST_CSID:
431
+ rc = s->regs[addr];
432
+ break;
433
+ case IBEX_SPI_HOST_CONFIGOPTS:
434
+ rc = s->config_opts[s->regs[IBEX_SPI_HOST_CSID]];
435
+ break;
436
+ case IBEX_SPI_HOST_TXDATA:
437
+ rc = s->regs[addr];
438
+ break;
439
+ case IBEX_SPI_HOST_RXDATA:
440
+ /* Clear RXFULL */
441
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXFULL_MASK;
442
+
443
+ for (int i = 0; i < 4; ++i) {
444
+ if (fifo8_is_empty(&s->rx_fifo)) {
445
+ /* Assert RXEMPTY, no IRQ */
446
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXEMPTY_MASK;
447
+ s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=
448
+ R_ERROR_STATUS_UNDERFLOW_MASK;
449
+ return rc;
450
+ }
451
+ rx_byte = fifo8_pop(&s->rx_fifo);
452
+ rc |= rx_byte << (i * 8);
453
+ }
454
+ break;
455
+ case IBEX_SPI_HOST_ERROR_ENABLE...IBEX_SPI_HOST_EVENT_ENABLE:
456
+ rc = s->regs[addr];
457
+ break;
458
+ default:
459
+ qemu_log_mask(LOG_GUEST_ERROR, "Bad offset 0x%" HWADDR_PRIx "\n",
460
+ addr << 2);
461
+ }
462
+ return rc;
463
+}
464
+
465
+
466
+static void ibex_spi_host_write(void *opaque, hwaddr addr,
467
+ uint64_t val64, unsigned int size)
468
+{
469
+ IbexSPIHostState *s = opaque;
470
+ uint32_t val32 = val64;
471
+ uint32_t shift_mask = 0xff;
472
+ uint8_t txqd_len;
473
+
474
+ trace_ibex_spi_host_write(addr, size, val64);
475
+
476
+ /* Match reg index */
477
+ addr = addr >> 2;
478
+
479
+ switch (addr) {
480
+ /* Skipping any R/O registers */
481
+ case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE:
482
+ s->regs[addr] = val32;
483
+ break;
484
+ case IBEX_SPI_HOST_INTR_TEST:
485
+ s->regs[addr] = val32;
486
+ ibex_spi_host_irq(s);
487
+ break;
488
+ case IBEX_SPI_HOST_ALERT_TEST:
489
+ s->regs[addr] = val32;
490
+ qemu_log_mask(LOG_UNIMP,
491
+ "%s: SPI_ALERT_TEST is not supported\n", __func__);
492
+ break;
493
+ case IBEX_SPI_HOST_CONTROL:
494
+ s->regs[addr] = val32;
495
+
496
+ if (val32 & R_CONTROL_SW_RST_MASK) {
497
+ ibex_spi_host_reset((DeviceState *)s);
498
+ /* Clear active if any */
499
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_ACTIVE_MASK;
500
+ }
501
+
502
+ if (val32 & R_CONTROL_OUTPUT_EN_MASK) {
503
+ qemu_log_mask(LOG_UNIMP,
504
+ "%s: CONTROL_OUTPUT_EN is not supported\n", __func__);
505
+ }
506
+ break;
507
+ case IBEX_SPI_HOST_CONFIGOPTS:
508
+ /* Update the respective config-opts register based on CSIDth index */
509
+ s->config_opts[s->regs[IBEX_SPI_HOST_CSID]] = val32;
510
+ qemu_log_mask(LOG_UNIMP,
511
+ "%s: CONFIGOPTS Hardware settings not supported\n",
512
+ __func__);
513
+ break;
514
+ case IBEX_SPI_HOST_CSID:
515
+ if (val32 >= s->num_cs) {
516
+ /* CSID exceeds max num_cs */
517
+ s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=
518
+ R_ERROR_STATUS_CSIDINVAL_MASK;
519
+ ibex_spi_host_irq(s);
520
+ return;
521
+ }
522
+ s->regs[addr] = val32;
523
+ break;
524
+ case IBEX_SPI_HOST_COMMAND:
525
+ s->regs[addr] = val32;
526
+
527
+ /* STALL, IP not enabled */
528
+ if (!(s->regs[IBEX_SPI_HOST_CONTROL] & R_CONTROL_SPIEN_MASK)) {
529
+ return;
530
+ }
531
+
532
+ /* SPI not ready, IRQ Error */
533
+ if (!(s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) {
534
+ s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= R_ERROR_STATUS_CMDBUSY_MASK;
535
+ ibex_spi_host_irq(s);
536
+ return;
537
+ }
538
+ /* Assert Not Ready */
539
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_READY_MASK;
540
+
541
+ if (((val32 & R_COMMAND_DIRECTION_MASK) >> R_COMMAND_DIRECTION_SHIFT)
542
+ != BIDIRECTIONAL_TRANSFER) {
543
+ qemu_log_mask(LOG_UNIMP,
544
+ "%s: Rx Only/Tx Only are not supported\n", __func__);
545
+ }
546
+
547
+ if (val32 & R_COMMAND_CSAAT_MASK) {
548
+ qemu_log_mask(LOG_UNIMP,
549
+ "%s: CSAAT is not supported\n", __func__);
550
+ }
551
+ if (val32 & R_COMMAND_SPEED_MASK) {
552
+ qemu_log_mask(LOG_UNIMP,
553
+ "%s: SPEED is not supported\n", __func__);
554
+ }
555
+
556
+ /* Set Transfer Callback */
557
+ timer_mod(s->fifo_trigger_handle,
558
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
559
+ (TX_INTERRUPT_TRIGGER_DELAY_NS));
560
+
561
+ break;
562
+ case IBEX_SPI_HOST_TXDATA:
563
+ /*
564
+ * This is a hardware `feature` where
565
+ * the first word written TXDATA after init is omitted entirely
566
+ */
567
+ if (s->init_status) {
568
+ s->init_status = false;
569
+ return;
570
+ }
571
+
572
+ for (int i = 0; i < 4; ++i) {
573
+ /* Attempting to write when TXFULL */
574
+ if (fifo8_is_full(&s->tx_fifo)) {
575
+ /* Assert RXEMPTY, no IRQ */
576
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXFULL_MASK;
577
+ s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=
578
+ R_ERROR_STATUS_OVERFLOW_MASK;
579
+ ibex_spi_host_irq(s);
580
+ return;
581
+ }
582
+ /* Byte ordering is set by the IP */
583
+ if ((s->regs[IBEX_SPI_HOST_STATUS] &
584
+ R_STATUS_BYTEORDER_MASK) == 0) {
585
+ /* LE: LSB transmitted first (default for ibex processor) */
586
+ shift_mask = 0xff << (i * 8);
587
+ } else {
588
+ /* BE: MSB transmitted first */
589
+ qemu_log_mask(LOG_UNIMP,
590
+ "%s: Big endian is not supported\n", __func__);
591
+ }
592
+
593
+ fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8));
594
+ }
595
+
596
+ /* Reset TXEMPTY */
597
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXEMPTY_MASK;
598
+ /* Update TXQD */
599
+ txqd_len = (s->regs[IBEX_SPI_HOST_STATUS] &
600
+ R_STATUS_TXQD_MASK) >> R_STATUS_TXQD_SHIFT;
601
+ /* Partial bytes (size < 4) are padded, in words. */
602
+ txqd_len += 1;
603
+ s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_TXQD_MASK;
604
+ s->regs[IBEX_SPI_HOST_STATUS] |= txqd_len;
605
+ /* Assert Ready */
606
+ s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_READY_MASK;
607
+ break;
608
+ case IBEX_SPI_HOST_ERROR_ENABLE:
609
+ s->regs[addr] = val32;
610
+
611
+ if (val32 & R_ERROR_ENABLE_CMDINVAL_MASK) {
612
+ qemu_log_mask(LOG_UNIMP,
613
+ "%s: Segment Length is not supported\n", __func__);
614
+ }
615
+ break;
616
+ case IBEX_SPI_HOST_ERROR_STATUS:
617
+ /*
618
+ * Indicates that any errors that have occurred.
619
+ * When an error occurs, the corresponding bit must be cleared
620
+ * here before issuing any further commands
621
+ */
622
+ s->regs[addr] = val32;
623
+ break;
624
+ case IBEX_SPI_HOST_EVENT_ENABLE:
625
+ /* Controls which classes of SPI events raise an interrupt. */
626
+ s->regs[addr] = val32;
627
+
628
+ if (val32 & R_EVENT_ENABLE_RXWM_MASK) {
629
+ qemu_log_mask(LOG_UNIMP,
630
+ "%s: RXWM is not supported\n", __func__);
631
+ }
632
+ if (val32 & R_EVENT_ENABLE_TXWM_MASK) {
633
+ qemu_log_mask(LOG_UNIMP,
634
+ "%s: TXWM is not supported\n", __func__);
635
+ }
636
+
637
+ if (val32 & R_EVENT_ENABLE_IDLE_MASK) {
638
+ qemu_log_mask(LOG_UNIMP,
639
+ "%s: IDLE is not supported\n", __func__);
640
+ }
641
+ break;
642
+ default:
643
+ qemu_log_mask(LOG_GUEST_ERROR, "Bad offset 0x%" HWADDR_PRIx "\n",
644
+ addr << 2);
645
+ }
646
+}
647
+
648
+static const MemoryRegionOps ibex_spi_ops = {
649
+ .read = ibex_spi_host_read,
650
+ .write = ibex_spi_host_write,
651
+ /* Ibex default LE */
153
+ .endianness = DEVICE_LITTLE_ENDIAN,
652
+ .endianness = DEVICE_LITTLE_ENDIAN,
154
+ .impl = {
155
+ .min_access_size = 4,
156
+ .max_access_size = 4,
157
+ },
158
+};
653
+};
159
+
654
+
160
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
655
+static Property ibex_spi_properties[] = {
161
+ hwaddr base, qemu_irq irq, Chardev *chr)
656
+ DEFINE_PROP_UINT32("num_cs", IbexSPIHostState, num_cs, 1),
162
+{
657
+ DEFINE_PROP_END_OF_LIST(),
163
+ MchpPfSoCMMUartState *s;
658
+};
164
+
659
+
165
+ s = g_new0(MchpPfSoCMMUartState, 1);
660
+static const VMStateDescription vmstate_ibex = {
166
+
661
+ .name = TYPE_IBEX_SPI_HOST,
167
+ memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
662
+ .version_id = 1,
168
+ "mchp.pfsoc.mmuart", 0x1000);
663
+ .minimum_version_id = 1,
169
+
664
+ .fields = (VMStateField[]) {
170
+ s->base = base;
665
+ VMSTATE_UINT32_ARRAY(regs, IbexSPIHostState, IBEX_SPI_HOST_MAX_REGS),
171
+ s->irq = irq;
666
+ VMSTATE_VARRAY_UINT32(config_opts, IbexSPIHostState,
172
+
667
+ num_cs, 0, vmstate_info_uint32, uint32_t),
173
+ s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
668
+ VMSTATE_FIFO8(rx_fifo, IbexSPIHostState),
174
+ DEVICE_LITTLE_ENDIAN);
669
+ VMSTATE_FIFO8(tx_fifo, IbexSPIHostState),
175
+
670
+ VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexSPIHostState),
176
+ memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
671
+ VMSTATE_BOOL(init_status, IbexSPIHostState),
177
+
672
+ VMSTATE_END_OF_LIST()
178
+ return s;
673
+ }
179
+}
674
+};
180
diff --git a/MAINTAINERS b/MAINTAINERS
675
+
676
+static void fifo_trigger_update(void *opaque)
677
+{
678
+ IbexSPIHostState *s = opaque;
679
+ ibex_spi_host_transfer(s);
680
+}
681
+
682
+static void ibex_spi_host_realize(DeviceState *dev, Error **errp)
683
+{
684
+ IbexSPIHostState *s = IBEX_SPI_HOST(dev);
685
+ int i;
686
+
687
+ s->ssi = ssi_create_bus(dev, "ssi");
688
+ s->cs_lines = g_new0(qemu_irq, s->num_cs);
689
+
690
+ for (i = 0; i < s->num_cs; ++i) {
691
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
692
+ }
693
+
694
+ /* Setup CONFIGOPTS Multi-register */
695
+ s->config_opts = g_new0(uint32_t, s->num_cs);
696
+
697
+ /* Setup FIFO Interrupt Timer */
698
+ s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
699
+ fifo_trigger_update, s);
700
+
701
+ /* FIFO sizes as per OT Spec */
702
+ fifo8_create(&s->tx_fifo, IBEX_SPI_HOST_TXFIFO_LEN);
703
+ fifo8_create(&s->rx_fifo, IBEX_SPI_HOST_RXFIFO_LEN);
704
+}
705
+
706
+static void ibex_spi_host_init(Object *obj)
707
+{
708
+ IbexSPIHostState *s = IBEX_SPI_HOST(obj);
709
+
710
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->host_err);
711
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->event);
712
+
713
+ memory_region_init_io(&s->mmio, obj, &ibex_spi_ops, s,
714
+ TYPE_IBEX_SPI_HOST, 0x1000);
715
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
716
+}
717
+
718
+static void ibex_spi_host_class_init(ObjectClass *klass, void *data)
719
+{
720
+ DeviceClass *dc = DEVICE_CLASS(klass);
721
+ dc->realize = ibex_spi_host_realize;
722
+ dc->reset = ibex_spi_host_reset;
723
+ dc->vmsd = &vmstate_ibex;
724
+ device_class_set_props(dc, ibex_spi_properties);
725
+}
726
+
727
+static const TypeInfo ibex_spi_host_info = {
728
+ .name = TYPE_IBEX_SPI_HOST,
729
+ .parent = TYPE_SYS_BUS_DEVICE,
730
+ .instance_size = sizeof(IbexSPIHostState),
731
+ .instance_init = ibex_spi_host_init,
732
+ .class_init = ibex_spi_host_class_init,
733
+};
734
+
735
+static void ibex_spi_host_register_types(void)
736
+{
737
+ type_register_static(&ibex_spi_host_info);
738
+}
739
+
740
+type_init(ibex_spi_host_register_types)
741
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
181
index XXXXXXX..XXXXXXX 100644
742
index XXXXXXX..XXXXXXX 100644
182
--- a/MAINTAINERS
743
--- a/hw/ssi/meson.build
183
+++ b/MAINTAINERS
744
+++ b/hw/ssi/meson.build
184
@@ -XXX,XX +XXX,XX @@ M: Bin Meng <bin.meng@windriver.com>
745
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XILINX_SPIPS', if_true: files('xilinx_spips.c'))
185
L: qemu-riscv@nongnu.org
746
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-ospi.c'))
186
S: Supported
747
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_spi.c'))
187
F: hw/riscv/microchip_pfsoc.c
748
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_spi.c'))
188
+F: hw/char/mchp_pfsoc_mmuart.c
749
+softmmu_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_spi_host.c'))
189
F: include/hw/riscv/microchip_pfsoc.h
750
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
190
+F: include/hw/char/mchp_pfsoc_mmuart.h
191
192
RX Machines
193
-----------
194
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
195
index XXXXXXX..XXXXXXX 100644
751
index XXXXXXX..XXXXXXX 100644
196
--- a/hw/char/Kconfig
752
--- a/hw/ssi/trace-events
197
+++ b/hw/char/Kconfig
753
+++ b/hw/ssi/trace-events
198
@@ -XXX,XX +XXX,XX @@ config RENESAS_SCI
754
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset:
199
755
npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
200
config AVR_USART
756
npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
201
bool
757
npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
202
+
758
+
203
+config MCHP_PFSOC_MMUART
759
+# ibex_spi_host.c
204
+ bool
760
+
205
diff --git a/hw/char/meson.build b/hw/char/meson.build
761
+ibex_spi_host_reset(const char *msg) "%s"
206
index XXXXXXX..XXXXXXX 100644
762
+ibex_spi_host_transfer(uint32_t tx_data, uint32_t rx_data) "tx_data: 0x%" PRIx32 " rx_data: @0x%" PRIx32
207
--- a/hw/char/meson.build
763
+ibex_spi_host_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx64 " size %u: 0x%" PRIx64
208
+++ b/hw/char/meson.build
764
+ibex_spi_host_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size %u:"
209
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
210
softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
211
softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
212
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
213
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
214
215
specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
216
specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
217
--
765
--
218
2.28.0
766
2.35.1
219
220
diff view generated by jsdifflib
[PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
[PULL v2 02/31] riscv: opentitan: Connect opentitan SPI Host
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
2
2
3
Microchip PolarFire SoC integrates one Cadence SDHCI controller.
3
Connect spi host[1/0] to opentitan.
4
On the Icicle Kit board, one eMMC chip and an external SD card
5
connect to this controller depending on different configuration.
6
4
7
As QEMU does not support eMMC yet, we just emulate the SD card
5
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
8
configuration. To test this, the Hart Software Services (HSS)
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
should choose the SD card configuration:
10
11
$ cp boards/icicle-kit-es/def_config.sdcard .config
12
$ make BOARD=icicle-kit-es
13
14
The SD card image can be built from the Yocto BSP at:
15
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp
16
17
Note the generated SD card image should be resized before use:
18
$ qemu-img resize /path/to/sdcard.img 4G
19
20
Launch QEMU with the following command:
21
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img
22
23
Signed-off-by: Bin Meng <bin.meng@windriver.com>
24
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com>
26
Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
27
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
28
---
10
---
29
include/hw/riscv/microchip_pfsoc.h | 4 ++++
11
include/hw/riscv/opentitan.h | 30 +++++++++++++++++++++---------
30
hw/riscv/microchip_pfsoc.c | 23 +++++++++++++++++++++++
12
hw/riscv/opentitan.c | 36 ++++++++++++++++++++++++++++++++----
31
hw/riscv/Kconfig | 1 +
13
2 files changed, 53 insertions(+), 13 deletions(-)
32
3 files changed, 28 insertions(+)
33
14
34
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
15
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
35
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/riscv/microchip_pfsoc.h
17
--- a/include/hw/riscv/opentitan.h
37
+++ b/include/hw/riscv/microchip_pfsoc.h
18
+++ b/include/hw/riscv/opentitan.h
38
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
39
#define HW_MICROCHIP_PFSOC_H
20
#include "hw/intc/sifive_plic.h"
40
21
#include "hw/char/ibex_uart.h"
41
#include "hw/char/mchp_pfsoc_mmuart.h"
22
#include "hw/timer/ibex_timer.h"
42
+#include "hw/sd/cadence_sdhci.h"
23
+#include "hw/ssi/ibex_spi_host.h"
43
24
#include "qom/object.h"
44
typedef struct MicrochipPFSoCState {
25
26
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
27
OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
28
29
+enum {
30
+ OPENTITAN_SPI_HOST0,
31
+ OPENTITAN_SPI_HOST1,
32
+ OPENTITAN_NUM_SPI_HOSTS,
33
+};
34
+
35
struct LowRISCIbexSoCState {
45
/*< private >*/
36
/*< private >*/
46
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
37
SysBusDevice parent_obj;
47
MchpPfSoCMMUartState *serial2;
38
@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
48
MchpPfSoCMMUartState *serial3;
39
SiFivePLICState plic;
49
MchpPfSoCMMUartState *serial4;
40
IbexUartState uart;
50
+ CadenceSDHCIState sdhci;
41
IbexTimerState timer;
51
} MicrochipPFSoCState;
42
+ IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
52
43
53
#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
44
MemoryRegion flash_mem;
54
@@ -XXX,XX +XXX,XX @@ enum {
45
MemoryRegion rom;
55
MICROCHIP_PFSOC_MMUART0,
56
MICROCHIP_PFSOC_SYSREG,
57
MICROCHIP_PFSOC_MPUCFG,
58
+ MICROCHIP_PFSOC_EMMC_SD,
59
MICROCHIP_PFSOC_MMUART1,
60
MICROCHIP_PFSOC_MMUART2,
61
MICROCHIP_PFSOC_MMUART3,
62
@@ -XXX,XX +XXX,XX @@ enum {
46
@@ -XXX,XX +XXX,XX @@ enum {
63
};
47
};
64
48
65
enum {
49
enum {
66
+ MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
50
- IBEX_TIMER_TIMEREXPIRED0_0 = 126,
67
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
51
- IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
68
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
52
- IBEX_UART0_RX_TIMEOUT_IRQ = 7,
69
MICROCHIP_PFSOC_MMUART2_IRQ = 92,
53
- IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
70
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
54
- IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
55
- IBEX_UART0_RX_OVERFLOW_IRQ = 4,
56
- IBEX_UART0_TX_EMPTY_IRQ = 3,
57
- IBEX_UART0_RX_WATERMARK_IRQ = 2,
58
- IBEX_UART0_TX_WATERMARK_IRQ = 1,
59
+ IBEX_UART0_TX_WATERMARK_IRQ = 1,
60
+ IBEX_UART0_RX_WATERMARK_IRQ = 2,
61
+ IBEX_UART0_TX_EMPTY_IRQ = 3,
62
+ IBEX_UART0_RX_OVERFLOW_IRQ = 4,
63
+ IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
64
+ IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
65
+ IBEX_UART0_RX_TIMEOUT_IRQ = 7,
66
+ IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
67
+ IBEX_TIMER_TIMEREXPIRED0_0 = 126,
68
+ IBEX_SPI_HOST0_ERR_IRQ = 150,
69
+ IBEX_SPI_HOST0_SPI_EVENT_IRQ = 151,
70
+ IBEX_SPI_HOST1_ERR_IRQ = 152,
71
+ IBEX_SPI_HOST1_SPI_EVENT_IRQ = 153,
72
};
73
74
#endif
75
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
71
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/riscv/microchip_pfsoc.c
77
--- a/hw/riscv/opentitan.c
73
+++ b/hw/riscv/microchip_pfsoc.c
78
+++ b/hw/riscv/opentitan.c
74
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_init(Object *obj)
75
* 1) PLIC (Platform Level Interrupt Controller)
80
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
76
* 2) eNVM (Embedded Non-Volatile Memory)
81
77
* 3) MMUARTs (Multi-Mode UART)
82
object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
78
+ * 4) Cadence eMMC/SDHC controller and an SD card connected to it
79
*
80
* This board currently generates devicetree dynamically that indicates at least
81
* two harts and up to five harts.
82
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
83
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
84
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
85
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
86
+ [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
87
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
88
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
89
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
90
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
91
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
92
TYPE_RISCV_CPU_SIFIVE_U54);
93
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
94
+
83
+
95
+ object_initialize_child(obj, "sd-controller", &s->sdhci,
84
+ for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
96
+ TYPE_CADENCE_SDHCI);
85
+ object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
97
}
86
+ TYPE_IBEX_SPI_HOST);
98
99
static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
100
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
101
memmap[MICROCHIP_PFSOC_MPUCFG].base,
102
memmap[MICROCHIP_PFSOC_MPUCFG].size);
103
104
+ /* SDHCI */
105
+ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
106
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
107
+ memmap[MICROCHIP_PFSOC_EMMC_SD].base);
108
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
109
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
110
+
111
/* MMUARTs */
112
s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
113
memmap[MICROCHIP_PFSOC_MMUART0].base,
114
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
115
MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
116
MemoryRegion *system_memory = get_system_memory();
117
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
118
+ DriveInfo *dinfo = drive_get_next(IF_SD);
119
120
/* Sanity check on RAM size */
121
if (machine->ram_size < mc->default_ram_size) {
122
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
123
124
/* Load the firmware */
125
riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
126
+
127
+ /* Attach an SD card */
128
+ if (dinfo) {
129
+ CadenceSDHCIState *sdhci = &(s->soc.sdhci);
130
+ DeviceState *card = qdev_new(TYPE_SD_CARD);
131
+
132
+ qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
133
+ &error_fatal);
134
+ qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
135
+ }
87
+ }
136
}
88
}
137
89
138
static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
90
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
139
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
91
{
140
index XXXXXXX..XXXXXXX 100644
92
const MemMapEntry *memmap = ibex_memmap;
141
--- a/hw/riscv/Kconfig
93
+ DeviceState *dev;
142
+++ b/hw/riscv/Kconfig
94
+ SysBusDevice *busdev;
143
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
95
MachineState *ms = MACHINE(qdev_get_machine());
144
select SIFIVE
96
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
145
select UNIMP
97
MemoryRegion *sys_mem = get_system_memory();
146
select MCHP_PFSOC_MMUART
98
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
147
+ select CADENCE_SDHCI
99
qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
100
IRQ_M_TIMER));
101
102
+ /* SPI-Hosts */
103
+ for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
104
+ dev = DEVICE(&(s->spi_host[i]));
105
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
106
+ return;
107
+ }
108
+ busdev = SYS_BUS_DEVICE(dev);
109
+ sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
110
+
111
+ switch (i) {
112
+ case OPENTITAN_SPI_HOST0:
113
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
114
+ IBEX_SPI_HOST0_ERR_IRQ));
115
+ sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
116
+ IBEX_SPI_HOST0_SPI_EVENT_IRQ));
117
+ break;
118
+ case OPENTITAN_SPI_HOST1:
119
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
120
+ IBEX_SPI_HOST1_ERR_IRQ));
121
+ sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
122
+ IBEX_SPI_HOST1_SPI_EVENT_IRQ));
123
+ break;
124
+ }
125
+ }
126
+
127
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
128
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
129
create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
130
memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
131
- create_unimplemented_device("riscv.lowrisc.ibex.spi_host0",
132
- memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size);
133
- create_unimplemented_device("riscv.lowrisc.ibex.spi_host1",
134
- memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size);
135
create_unimplemented_device("riscv.lowrisc.ibex.i2c",
136
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
137
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
148
--
138
--
149
2.28.0
139
2.35.1
150
151
diff view generated by jsdifflib
[PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order
[PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Atish Patra <atishp@rivosinc.com>
2
2
3
At present the Kconfig file is in disorder. Let's sort the options.
3
Currently, the privileged specification version are defined in
4
a complex manner for no benefit.
4
5
5
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Simplify it by changing it to a simple enum based on.
7
8
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Message-Id: <20220303185440.512391-2-atishp@rivosinc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
---
13
---
10
hw/riscv/Kconfig | 58 ++++++++++++++++++++++++------------------------
14
target/riscv/cpu.h | 7 +++++--
11
1 file changed, 29 insertions(+), 29 deletions(-)
15
1 file changed, 5 insertions(+), 2 deletions(-)
12
16
13
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
17
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/riscv/Kconfig
19
--- a/target/riscv/cpu.h
16
+++ b/hw/riscv/Kconfig
20
+++ b/target/riscv/cpu.h
17
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ enum {
18
config IBEX
22
RISCV_FEATURE_AIA
19
bool
23
};
20
24
21
-config SIFIVE_E
25
-#define PRIV_VERSION_1_10_0 0x00011000
22
- bool
26
-#define PRIV_VERSION_1_11_0 0x00011100
23
- select MSI_NONBROKEN
27
+/* Privileged specification version */
24
- select SIFIVE_CLINT
28
+enum {
25
- select SIFIVE_GPIO
29
+ PRIV_VERSION_1_10_0 = 0,
26
- select SIFIVE_PLIC
30
+ PRIV_VERSION_1_11_0,
27
- select SIFIVE_UART
31
+};
28
- select SIFIVE_E_PRCI
32
29
- select UNIMP
33
#define VEXT_VERSION_1_00_0 0x00010000
30
-
34
31
-config SIFIVE_U
32
+config MICROCHIP_PFSOC
33
bool
34
- select CADENCE
35
+ select CADENCE_SDHCI
36
+ select MCHP_PFSOC_MMUART
37
select MSI_NONBROKEN
38
select SIFIVE_CLINT
39
- select SIFIVE_GPIO
40
select SIFIVE_PDMA
41
select SIFIVE_PLIC
42
- select SIFIVE_UART
43
- select SIFIVE_U_OTP
44
- select SIFIVE_U_PRCI
45
select UNIMP
46
47
-config SPIKE
48
- bool
49
- select HTIF
50
- select MSI_NONBROKEN
51
- select SIFIVE_CLINT
52
- select SIFIVE_PLIC
53
-
54
config OPENTITAN
55
bool
56
select IBEX
57
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
58
bool
59
imply PCI_DEVICES
60
imply TEST_DEVICES
61
+ select GOLDFISH_RTC
62
select MSI_NONBROKEN
63
select PCI
64
- select SERIAL
65
- select GOLDFISH_RTC
66
- select VIRTIO_MMIO
67
select PCI_EXPRESS_GENERIC_BRIDGE
68
select PFLASH_CFI01
69
+ select SERIAL
70
select SIFIVE_CLINT
71
select SIFIVE_PLIC
72
select SIFIVE_TEST
73
+ select VIRTIO_MMIO
74
75
-config MICROCHIP_PFSOC
76
+config SIFIVE_E
77
bool
78
select MSI_NONBROKEN
79
select SIFIVE_CLINT
80
+ select SIFIVE_GPIO
81
+ select SIFIVE_PLIC
82
+ select SIFIVE_UART
83
+ select SIFIVE_E_PRCI
84
select UNIMP
85
- select MCHP_PFSOC_MMUART
86
+
87
+config SIFIVE_U
88
+ bool
89
+ select CADENCE
90
+ select MSI_NONBROKEN
91
+ select SIFIVE_CLINT
92
+ select SIFIVE_GPIO
93
select SIFIVE_PDMA
94
select SIFIVE_PLIC
95
- select CADENCE_SDHCI
96
+ select SIFIVE_UART
97
+ select SIFIVE_U_OTP
98
+ select SIFIVE_U_PRCI
99
+ select UNIMP
100
+
101
+config SPIKE
102
+ bool
103
+ select HTIF
104
+ select MSI_NONBROKEN
105
+ select SIFIVE_CLINT
106
+ select SIFIVE_PLIC
107
--
35
--
108
2.28.0
36
2.35.1
109
110
diff view generated by jsdifflib
[PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE
[PULL v2 04/31] target/riscv: Add the privileged spec version 1.12.0
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Atish Patra <atishp@rivosinc.com>
2
2
3
The name SIFIVE is too vague to convey the required component of
3
Add the definition for ratified privileged specification version v1.12
4
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
5
each machine instead.
6
4
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com>
6
Signed-off-by: Atish Patra <atishp@rivosinc.com>
7
Message-Id: <20220303185440.512391-3-atishp@rivosinc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
9
---
12
hw/riscv/Kconfig | 14 +++++---------
10
target/riscv/cpu.h | 1 +
13
1 file changed, 5 insertions(+), 9 deletions(-)
11
1 file changed, 1 insertion(+)
14
12
15
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
13
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/riscv/Kconfig
15
--- a/target/riscv/cpu.h
18
+++ b/hw/riscv/Kconfig
16
+++ b/target/riscv/cpu.h
19
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ enum {
20
config IBEX
18
enum {
21
bool
19
PRIV_VERSION_1_10_0 = 0,
22
20
PRIV_VERSION_1_11_0,
23
-config SIFIVE
21
+ PRIV_VERSION_1_12_0,
24
- bool
22
};
25
- select MSI_NONBROKEN
23
26
-
24
#define VEXT_VERSION_1_00_0 0x00010000
27
config SIFIVE_E
28
bool
29
- select SIFIVE
30
+ select MSI_NONBROKEN
31
select SIFIVE_CLINT
32
select SIFIVE_GPIO
33
select SIFIVE_PLIC
34
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
35
config SIFIVE_U
36
bool
37
select CADENCE
38
- select SIFIVE
39
+ select MSI_NONBROKEN
40
select SIFIVE_CLINT
41
select SIFIVE_GPIO
42
select SIFIVE_PDMA
43
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
44
config SPIKE
45
bool
46
select HTIF
47
- select SIFIVE
48
+ select MSI_NONBROKEN
49
select SIFIVE_CLINT
50
select SIFIVE_PLIC
51
52
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
53
bool
54
imply PCI_DEVICES
55
imply TEST_DEVICES
56
+ select MSI_NONBROKEN
57
select PCI
58
select SERIAL
59
select GOLDFISH_RTC
60
select VIRTIO_MMIO
61
select PCI_EXPRESS_GENERIC_BRIDGE
62
select PFLASH_CFI01
63
- select SIFIVE
64
select SIFIVE_CLINT
65
select SIFIVE_PLIC
66
select SIFIVE_TEST
67
68
config MICROCHIP_PFSOC
69
bool
70
- select SIFIVE
71
+ select MSI_NONBROKEN
72
select SIFIVE_CLINT
73
select UNIMP
74
select MCHP_PFSOC_MMUART
75
--
25
--
76
2.28.0
26
2.35.1
77
78
diff view generated by jsdifflib
[PULL 28/30] hw/riscv: Always build riscv_hart.c
[PULL v2 05/31] target/riscv: Introduce privilege version field in the CSR ops.
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Atish Patra <atishp@rivosinc.com>
2
2
3
Every RISC-V machine needs riscv_hart hence there is no need to
3
To allow/disallow the CSR access based on the privilege spec, a new field
4
have a dedicated Kconfig option for it. Drop the Kconfig option
4
in the csr_ops is introduced. It also adds the privileged specification
5
and always build riscv_hart.c.
5
version (v1.12) for the CSRs introduced in the v1.12. This includes the
6
new ratified extensions such as Vector, Hypervisor and secconfig CSR.
7
However, it doesn't enforce the privilege version in this commit.
6
8
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
10
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Message-Id: <20220303185440.512391-4-atishp@rivosinc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
13
---
12
hw/riscv/Kconfig | 9 ---------
14
target/riscv/cpu.h | 2 +
13
hw/riscv/meson.build | 2 +-
15
target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++---------------
14
2 files changed, 1 insertion(+), 10 deletions(-)
16
2 files changed, 70 insertions(+), 35 deletions(-)
15
17
16
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
18
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/riscv/Kconfig
20
--- a/target/riscv/cpu.h
19
+++ b/hw/riscv/Kconfig
21
+++ b/target/riscv/cpu.h
20
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ typedef struct {
21
-config HART
23
riscv_csr_op_fn op;
22
- bool
24
riscv_csr_read128_fn read128;
25
riscv_csr_write128_fn write128;
26
+ /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */
27
+ uint32_t min_priv_ver;
28
} riscv_csr_operations;
29
30
/* CSR function table constants */
31
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/riscv/csr.c
34
+++ b/target/riscv/csr.c
35
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
36
[CSR_FRM] = { "frm", fs, read_frm, write_frm },
37
[CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
38
/* Vector CSRs */
39
- [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
40
- [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
41
- [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
42
- [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
43
- [CSR_VL] = { "vl", vs, read_vl },
44
- [CSR_VTYPE] = { "vtype", vs, read_vtype },
45
- [CSR_VLENB] = { "vlenb", vs, read_vlenb },
46
+ [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
47
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
48
+ [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
49
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
50
+ [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
51
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
52
+ [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
53
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
54
+ [CSR_VL] = { "vl", vs, read_vl,
55
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
56
+ [CSR_VTYPE] = { "vtype", vs, read_vtype,
57
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
58
+ [CSR_VLENB] = { "vlenb", vs, read_vlenb,
59
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
60
/* User Timers and Counters */
61
[CSR_CYCLE] = { "cycle", ctr, read_instret },
62
[CSR_INSTRET] = { "instret", ctr, read_instret },
63
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
64
[CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
65
[CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
66
67
- [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus },
68
- [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg },
69
- [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg },
70
- [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip },
71
- [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip },
72
- [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie },
73
- [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren },
74
- [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie },
75
- [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval },
76
- [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst },
77
- [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL },
78
- [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp },
79
- [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta },
80
- [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
23
-
81
-
24
config IBEX
82
- [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus },
25
bool
83
- [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip },
26
84
- [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie },
27
@@ -XXX,XX +XXX,XX @@ config SIFIVE
85
- [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec },
28
86
- [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch },
29
config SIFIVE_E
87
- [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc },
30
bool
88
- [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause },
31
- select HART
89
- [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval },
32
select SIFIVE
90
- [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp },
33
select SIFIVE_CLINT
91
-
34
select SIFIVE_GPIO
92
- [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2 },
35
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
93
- [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
36
config SIFIVE_U
94
+ [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus, write_hstatus,
37
bool
95
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
38
select CADENCE
96
+ [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg, write_hedeleg,
39
- select HART
97
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
40
select SIFIVE
98
+ [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL, rmw_hideleg,
41
select SIFIVE_CLINT
99
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
42
select SIFIVE_GPIO
100
+ [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip,
43
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
101
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
44
102
+ [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip,
45
config SPIKE
103
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
46
bool
104
+ [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie,
47
- select HART
105
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
48
select HTIF
106
+ [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren, write_hcounteren,
49
select SIFIVE
107
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
50
select SIFIVE_CLINT
108
+ [CSR_HGEIE] = { "hgeie", hmode, read_hgeie, write_hgeie,
51
@@ -XXX,XX +XXX,XX @@ config SPIKE
109
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
52
config OPENTITAN
110
+ [CSR_HTVAL] = { "htval", hmode, read_htval, write_htval,
53
bool
111
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
54
select IBEX
112
+ [CSR_HTINST] = { "htinst", hmode, read_htinst, write_htinst,
55
- select HART
113
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
56
select UNIMP
114
+ [CSR_HGEIP] = { "hgeip", hmode, read_hgeip,
57
115
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
58
config RISCV_VIRT
116
+ [CSR_HGATP] = { "hgatp", hmode, read_hgatp, write_hgatp,
59
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
117
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
60
imply PCI_DEVICES
118
+ [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta, write_htimedelta,
61
imply TEST_DEVICES
119
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
62
select PCI
120
+ [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah,
63
- select HART
121
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
64
select SERIAL
122
+
65
select GOLDFISH_RTC
123
+ [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus, write_vsstatus,
66
select VIRTIO_MMIO
124
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
67
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
125
+ [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip,
68
126
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
69
config MICROCHIP_PFSOC
127
+ [CSR_VSIE] = { "vsie", hmode, NULL, NULL, rmw_vsie ,
70
bool
128
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
71
- select HART
129
+ [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec, write_vstvec,
72
select SIFIVE
130
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
73
select SIFIVE_CLINT
131
+ [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch, write_vsscratch,
74
select UNIMP
132
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
75
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
133
+ [CSR_VSEPC] = { "vsepc", hmode, read_vsepc, write_vsepc,
76
index XXXXXXX..XXXXXXX 100644
134
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
77
--- a/hw/riscv/meson.build
135
+ [CSR_VSCAUSE] = { "vscause", hmode, read_vscause, write_vscause,
78
+++ b/hw/riscv/meson.build
136
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
79
@@ -XXX,XX +XXX,XX @@
137
+ [CSR_VSTVAL] = { "vstval", hmode, read_vstval, write_vstval,
80
riscv_ss = ss.source_set()
138
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
81
riscv_ss.add(files('boot.c'), fdt)
139
+ [CSR_VSATP] = { "vsatp", hmode, read_vsatp, write_vsatp,
82
riscv_ss.add(files('numa.c'))
140
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
83
-riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
141
+
84
+riscv_ss.add(files('riscv_hart.c'))
142
+ [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2, write_mtval2,
85
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
143
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
86
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
144
+ [CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst,
87
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
145
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
146
147
/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
148
[CSR_HVIEN] = { "hvien", aia_hmode, read_zero, write_ignore },
149
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
150
[CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL, rmw_vsiph },
151
152
/* Physical Memory Protection */
153
- [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
154
+ [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
155
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
156
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
157
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
158
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
88
--
159
--
89
2.28.0
160
2.35.1
90
91
diff view generated by jsdifflib
[PULL 27/30] hw/riscv: Move sifive_test model to hw/misc
[PULL v2 06/31] target/riscv: Add support for mconfigptr
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Atish Patra <atishp@rivosinc.com>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
RISC-V privileged specification v1.12 introduced a mconfigptr
4
should only contain the RISC-V SoC / machine codes plus generic
4
which will hold the physical address of a configuration data
5
codes. Let's move sifive_test model to hw/misc directory.
5
structure. As Qemu doesn't have a configuration data structure,
6
is read as zero which is valid as per the priv spec.
6
7
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
9
Signed-off-by: Atish Patra <atishp@rivosinc.com>
10
Message-Id: <20220303185440.512391-5-atishp@rivosinc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
---
12
include/hw/{riscv => misc}/sifive_test.h | 0
13
target/riscv/cpu_bits.h | 1 +
13
hw/{riscv => misc}/sifive_test.c | 2 +-
14
target/riscv/csr.c | 2 ++
14
hw/riscv/virt.c | 2 +-
15
2 files changed, 3 insertions(+)
15
hw/misc/Kconfig | 3 +++
16
hw/misc/meson.build | 1 +
17
hw/riscv/Kconfig | 1 +
18
hw/riscv/meson.build | 1 -
19
7 files changed, 7 insertions(+), 3 deletions(-)
20
rename include/hw/{riscv => misc}/sifive_test.h (100%)
21
rename hw/{riscv => misc}/sifive_test.c (98%)
22
16
23
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
17
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
24
similarity index 100%
25
rename from include/hw/riscv/sifive_test.h
26
rename to include/hw/misc/sifive_test.h
27
diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
28
similarity index 98%
29
rename from hw/riscv/sifive_test.c
30
rename to hw/misc/sifive_test.c
31
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/sifive_test.c
19
--- a/target/riscv/cpu_bits.h
33
+++ b/hw/misc/sifive_test.c
20
+++ b/target/riscv/cpu_bits.h
34
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
35
#include "qemu/module.h"
22
#define CSR_MARCHID 0xf12
36
#include "sysemu/runstate.h"
23
#define CSR_MIMPID 0xf13
37
#include "hw/hw.h"
24
#define CSR_MHARTID 0xf14
38
-#include "hw/riscv/sifive_test.h"
25
+#define CSR_MCONFIGPTR 0xf15
39
+#include "hw/misc/sifive_test.h"
26
40
27
/* Machine Trap Setup */
41
static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
28
#define CSR_MSTATUS 0x300
42
{
29
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
43
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
44
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/riscv/virt.c
31
--- a/target/riscv/csr.c
46
+++ b/hw/riscv/virt.c
32
+++ b/target/riscv/csr.c
47
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
48
#include "hw/char/serial.h"
34
[CSR_MIMPID] = { "mimpid", any, read_zero },
49
#include "target/riscv/cpu.h"
35
[CSR_MHARTID] = { "mhartid", any, read_mhartid },
50
#include "hw/riscv/riscv_hart.h"
36
51
-#include "hw/riscv/sifive_test.h"
37
+ [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
52
#include "hw/riscv/virt.h"
38
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
53
#include "hw/riscv/boot.h"
39
/* Machine Trap Setup */
54
#include "hw/riscv/numa.h"
40
[CSR_MSTATUS] = { "mstatus", any, read_mstatus, write_mstatus, NULL,
55
#include "hw/intc/sifive_clint.h"
41
read_mstatus_i128 },
56
#include "hw/intc/sifive_plic.h"
57
+#include "hw/misc/sifive_test.h"
58
#include "chardev/char.h"
59
#include "sysemu/arch_init.h"
60
#include "sysemu/device_tree.h"
61
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/misc/Kconfig
64
+++ b/hw/misc/Kconfig
65
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
66
config AVR_POWER
67
bool
68
69
+config SIFIVE_TEST
70
+ bool
71
+
72
config SIFIVE_E_PRCI
73
bool
74
75
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
76
index XXXXXXX..XXXXXXX 100644
77
--- a/hw/misc/meson.build
78
+++ b/hw/misc/meson.build
79
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
80
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
81
82
# RISC-V devices
83
+softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
84
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
85
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
86
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
87
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
88
index XXXXXXX..XXXXXXX 100644
89
--- a/hw/riscv/Kconfig
90
+++ b/hw/riscv/Kconfig
91
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
92
select SIFIVE
93
select SIFIVE_CLINT
94
select SIFIVE_PLIC
95
+ select SIFIVE_TEST
96
97
config MICROCHIP_PFSOC
98
bool
99
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
100
index XXXXXXX..XXXXXXX 100644
101
--- a/hw/riscv/meson.build
102
+++ b/hw/riscv/meson.build
103
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
104
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
105
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
106
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
107
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
108
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
109
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
110
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
111
--
42
--
112
2.28.0
43
2.35.1
113
114
diff view generated by jsdifflib
[PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region
[PULL v2 07/31] target/riscv: Add *envcfg* CSRs support
1
From: Nathan Chancellor <natechancellor@gmail.com>
1
From: Atish Patra <atishp@rivosinc.com>
2
2
3
When shutting down the machine running a mainline Linux kernel, the
3
The RISC-V privileged specification v1.12 defines few execution
4
following error happens:
4
environment configuration CSRs that can be used enable/disable
5
5
extensions per privilege levels.
6
$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
6
7
-display none -initrd rootfs.cpio -kernel Image -m 512m \
7
Add the basic support for these CSRs.
8
-nodefaults -serial mon:stdio
8
9
...
10
Requesting system poweroff
11
[ 4.999630] reboot: Power down
12
sbi_trap_error: hart0: trap handler failed (error -2)
13
sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
14
sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
15
sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
16
sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
17
sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
18
sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
19
sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
20
sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
21
sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
22
sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
23
sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
24
sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
25
sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
26
sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
27
sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
28
sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
29
sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
30
sbi_trap_error: hart0: t6=0x0000000000000000
31
32
The kernel does a 16-bit write when powering off the machine, which
33
was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
34
mismatching sizes in memory_region_access_valid""). Make min_access_size
35
match reality so that the machine can shut down properly now.
36
37
Cc: qemu-stable@nongnu.org
38
Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
39
Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"")
40
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
41
Acked-by: Michael S. Tsirkin <mst@redhat.com>
42
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
43
Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com>
10
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Message-Id: <20220303185440.512391-6-atishp@rivosinc.com>
44
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
45
---
13
---
46
hw/riscv/sifive_test.c | 2 +-
14
target/riscv/cpu.h | 5 ++
47
1 file changed, 1 insertion(+), 1 deletion(-)
15
target/riscv/cpu_bits.h | 39 +++++++++++++++
48
16
target/riscv/csr.c | 107 ++++++++++++++++++++++++++++++++++++++++
49
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
17
target/riscv/machine.c | 23 +++++++++
50
index XXXXXXX..XXXXXXX 100644
18
4 files changed, 174 insertions(+)
51
--- a/hw/riscv/sifive_test.c
19
52
+++ b/hw/riscv/sifive_test.c
20
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
53
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_test_ops = {
21
index XXXXXXX..XXXXXXX 100644
54
.write = sifive_test_write,
22
--- a/target/riscv/cpu.h
55
.endianness = DEVICE_NATIVE_ENDIAN,
23
+++ b/target/riscv/cpu.h
56
.valid = {
24
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
57
- .min_access_size = 4,
25
target_ulong spmbase;
58
+ .min_access_size = 2,
26
target_ulong upmmask;
59
.max_access_size = 4
27
target_ulong upmbase;
28
+
29
+ /* CSRs for execution enviornment configuration */
30
+ uint64_t menvcfg;
31
+ target_ulong senvcfg;
32
+ uint64_t henvcfg;
33
#endif
34
target_ulong cur_pmmask;
35
target_ulong cur_pmbase;
36
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/riscv/cpu_bits.h
39
+++ b/target/riscv/cpu_bits.h
40
@@ -XXX,XX +XXX,XX @@
41
#define CSR_STVEC 0x105
42
#define CSR_SCOUNTEREN 0x106
43
44
+/* Supervisor Configuration CSRs */
45
+#define CSR_SENVCFG 0x10A
46
+
47
/* Supervisor Trap Handling */
48
#define CSR_SSCRATCH 0x140
49
#define CSR_SEPC 0x141
50
@@ -XXX,XX +XXX,XX @@
51
#define CSR_HTIMEDELTA 0x605
52
#define CSR_HTIMEDELTAH 0x615
53
54
+/* Hypervisor Configuration CSRs */
55
+#define CSR_HENVCFG 0x60A
56
+#define CSR_HENVCFGH 0x61A
57
+
58
/* Virtual CSRs */
59
#define CSR_VSSTATUS 0x200
60
#define CSR_VSIE 0x204
61
@@ -XXX,XX +XXX,XX @@
62
#define CSR_VSIEH 0x214
63
#define CSR_VSIPH 0x254
64
65
+/* Machine Configuration CSRs */
66
+#define CSR_MENVCFG 0x30A
67
+#define CSR_MENVCFGH 0x31A
68
+
69
/* Enhanced Physical Memory Protection (ePMP) */
70
#define CSR_MSECCFG 0x747
71
#define CSR_MSECCFGH 0x757
72
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
73
#define PM_EXT_CLEAN 0x00000002ULL
74
#define PM_EXT_DIRTY 0x00000003ULL
75
76
+/* Execution enviornment configuration bits */
77
+#define MENVCFG_FIOM BIT(0)
78
+#define MENVCFG_CBIE (3UL << 4)
79
+#define MENVCFG_CBCFE BIT(6)
80
+#define MENVCFG_CBZE BIT(7)
81
+#define MENVCFG_PBMTE (1ULL << 62)
82
+#define MENVCFG_STCE (1ULL << 63)
83
+
84
+/* For RV32 */
85
+#define MENVCFGH_PBMTE BIT(30)
86
+#define MENVCFGH_STCE BIT(31)
87
+
88
+#define SENVCFG_FIOM MENVCFG_FIOM
89
+#define SENVCFG_CBIE MENVCFG_CBIE
90
+#define SENVCFG_CBCFE MENVCFG_CBCFE
91
+#define SENVCFG_CBZE MENVCFG_CBZE
92
+
93
+#define HENVCFG_FIOM MENVCFG_FIOM
94
+#define HENVCFG_CBIE MENVCFG_CBIE
95
+#define HENVCFG_CBCFE MENVCFG_CBCFE
96
+#define HENVCFG_CBZE MENVCFG_CBZE
97
+#define HENVCFG_PBMTE MENVCFG_PBMTE
98
+#define HENVCFG_STCE MENVCFG_STCE
99
+
100
+/* For RV32 */
101
+#define HENVCFGH_PBMTE MENVCFGH_PBMTE
102
+#define HENVCFGH_STCE MENVCFGH_STCE
103
+
104
/* Offsets for every pair of control bits per each priv level */
105
#define XS_OFFSET 0ULL
106
#define U_OFFSET 2ULL
107
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/riscv/csr.c
110
+++ b/target/riscv/csr.c
111
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
112
return RISCV_EXCP_NONE;
113
}
114
115
+/* Execution environment configuration setup */
116
+static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
117
+ target_ulong *val)
118
+{
119
+ *val = env->menvcfg;
120
+ return RISCV_EXCP_NONE;
121
+}
122
+
123
+static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
124
+ target_ulong val)
125
+{
126
+ uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
127
+
128
+ if (riscv_cpu_mxl(env) == MXL_RV64) {
129
+ mask |= MENVCFG_PBMTE | MENVCFG_STCE;
130
+ }
131
+ env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
132
+
133
+ return RISCV_EXCP_NONE;
134
+}
135
+
136
+static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
137
+ target_ulong *val)
138
+{
139
+ *val = env->menvcfg >> 32;
140
+ return RISCV_EXCP_NONE;
141
+}
142
+
143
+static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
144
+ target_ulong val)
145
+{
146
+ uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
147
+ uint64_t valh = (uint64_t)val << 32;
148
+
149
+ env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
150
+
151
+ return RISCV_EXCP_NONE;
152
+}
153
+
154
+static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
155
+ target_ulong *val)
156
+{
157
+ *val = env->senvcfg;
158
+ return RISCV_EXCP_NONE;
159
+}
160
+
161
+static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
162
+ target_ulong val)
163
+{
164
+ uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
165
+
166
+ env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
167
+
168
+ return RISCV_EXCP_NONE;
169
+}
170
+
171
+static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
172
+ target_ulong *val)
173
+{
174
+ *val = env->henvcfg;
175
+ return RISCV_EXCP_NONE;
176
+}
177
+
178
+static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
179
+ target_ulong val)
180
+{
181
+ uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
182
+
183
+ if (riscv_cpu_mxl(env) == MXL_RV64) {
184
+ mask |= HENVCFG_PBMTE | HENVCFG_STCE;
185
+ }
186
+
187
+ env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
188
+
189
+ return RISCV_EXCP_NONE;
190
+}
191
+
192
+static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
193
+ target_ulong *val)
194
+{
195
+ *val = env->henvcfg >> 32;
196
+ return RISCV_EXCP_NONE;
197
+}
198
+
199
+static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
200
+ target_ulong val)
201
+{
202
+ uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
203
+ uint64_t valh = (uint64_t)val << 32;
204
+
205
+ env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
206
+
207
+ return RISCV_EXCP_NONE;
208
+}
209
+
210
static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
211
uint64_t *ret_val,
212
uint64_t new_val, uint64_t wr_mask)
213
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
214
[CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore },
215
[CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
216
217
+ /* Execution environment configuration */
218
+ [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg,
219
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
220
+ [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh,
221
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
222
+ [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg,
223
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
224
+ [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg,
225
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
226
+ [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
227
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
228
+
229
/* Supervisor Trap Setup */
230
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL,
231
read_sstatus_i128 },
232
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
233
index XXXXXXX..XXXXXXX 100644
234
--- a/target/riscv/machine.c
235
+++ b/target/riscv/machine.c
236
@@ -XXX,XX +XXX,XX @@ static int riscv_cpu_post_load(void *opaque, int version_id)
237
return 0;
238
}
239
240
+static bool envcfg_needed(void *opaque)
241
+{
242
+ RISCVCPU *cpu = opaque;
243
+ CPURISCVState *env = &cpu->env;
244
+
245
+ return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
246
+}
247
+
248
+static const VMStateDescription vmstate_envcfg = {
249
+ .name = "cpu/envcfg",
250
+ .version_id = 1,
251
+ .minimum_version_id = 1,
252
+ .needed = envcfg_needed,
253
+ .fields = (VMStateField[]) {
254
+ VMSTATE_UINT64(env.menvcfg, RISCVCPU),
255
+ VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
256
+ VMSTATE_UINT64(env.henvcfg, RISCVCPU),
257
+
258
+ VMSTATE_END_OF_LIST()
259
+ }
260
+};
261
+
262
const VMStateDescription vmstate_riscv_cpu = {
263
.name = "cpu",
264
.version_id = 3,
265
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
266
&vmstate_pointermasking,
267
&vmstate_rv128,
268
&vmstate_kvmtimer,
269
+ &vmstate_envcfg,
270
NULL
60
}
271
}
61
};
272
};
62
--
273
--
63
2.28.0
274
2.35.1
64
65
diff view generated by jsdifflib
[PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value
[PULL v2 08/31] target/riscv: Enable privileged spec version 1.12
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Atish Patra <atishp@rivosinc.com>
2
2
3
Now that we have the newly introduced 'resetvec' property in the
3
Virt machine uses privileged specification version 1.12 now.
4
RISC-V CPU and HART, instead of hard-coding the reset vector addr
4
All other machine continue to use the default one defined for that
5
in the CPU's instance_init(), move that to riscv_cpu_realize()
5
machine unless changed to 1.12 by the user explicitly.
6
based on the configured property value from the RISC-V machines.
7
6
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
This commit enforces the privilege version for csrs introduced in
8
v1.12 or after.
9
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Signed-off-by: Atish Patra <atishp@rivosinc.com>
11
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
12
Message-Id: <20220303185440.512391-7-atishp@rivosinc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
---
14
hw/riscv/opentitan.c | 1 +
15
target/riscv/cpu.c | 8 +++++---
15
hw/riscv/sifive_e.c | 1 +
16
target/riscv/csr.c | 5 +++++
16
hw/riscv/sifive_u.c | 2 ++
17
2 files changed, 10 insertions(+), 3 deletions(-)
17
target/riscv/cpu.c | 7 ++-----
18
4 files changed, 6 insertions(+), 5 deletions(-)
19
18
20
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/riscv/opentitan.c
23
+++ b/hw/riscv/opentitan.c
24
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
25
&error_abort);
26
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
27
&error_abort);
28
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
29
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
30
31
/* Boot ROM */
32
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/riscv/sifive_e.c
35
+++ b/hw/riscv/sifive_e.c
36
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_init(Object *obj)
37
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
38
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
39
&error_abort);
40
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
41
object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
42
TYPE_SIFIVE_GPIO);
43
}
44
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/riscv/sifive_u.c
47
+++ b/hw/riscv/sifive_u.c
48
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
49
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
50
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
51
qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
52
+ qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
53
54
object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
55
qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
56
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
57
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
58
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
59
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
60
+ qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
61
62
object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
63
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
64
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
19
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
65
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
66
--- a/target/riscv/cpu.c
21
--- a/target/riscv/cpu.c
67
+++ b/target/riscv/cpu.c
22
+++ b/target/riscv/cpu.c
68
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
23
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
69
CPURISCVState *env = &RISCV_CPU(obj)->env;
24
#elif defined(TARGET_RISCV64)
70
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
25
set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
71
set_priv_version(env, PRIV_VERSION_1_11_0);
26
#endif
72
- set_resetvec(env, DEFAULT_RSTVEC);
27
- set_priv_version(env, PRIV_VERSION_1_11_0);
28
+ set_priv_version(env, PRIV_VERSION_1_12_0);
73
}
29
}
74
30
75
static void riscv_base_cpu_init(Object *obj)
31
#if defined(TARGET_RISCV64)
76
@@ -XXX,XX +XXX,XX @@ static void riscv_base_cpu_init(Object *obj)
32
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
77
CPURISCVState *env = &RISCV_CPU(obj)->env;
33
}
78
/* We set this in the realise function */
34
79
set_misa(env, 0);
35
if (cpu->cfg.priv_spec) {
80
- set_resetvec(env, DEFAULT_RSTVEC);
36
- if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
37
+ if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
38
+ priv_version = PRIV_VERSION_1_12_0;
39
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
40
priv_version = PRIV_VERSION_1_11_0;
41
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
42
priv_version = PRIV_VERSION_1_10_0;
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
44
if (priv_version) {
45
set_priv_version(env, priv_version);
46
} else if (!env->priv_ver) {
47
- set_priv_version(env, PRIV_VERSION_1_11_0);
48
+ set_priv_version(env, PRIV_VERSION_1_12_0);
49
}
50
51
if (cpu->cfg.mmu) {
52
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/riscv/csr.c
55
+++ b/target/riscv/csr.c
56
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
57
{
58
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
59
int read_only = get_field(csrno, 0xC00) == 3;
60
+ int csr_min_priv = csr_ops[csrno].min_priv_ver;
61
#if !defined(CONFIG_USER_ONLY)
62
int effective_priv = env->priv;
63
64
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
65
return RISCV_EXCP_ILLEGAL_INST;
66
}
67
68
+ if (env->priv_ver < csr_min_priv) {
69
+ return RISCV_EXCP_ILLEGAL_INST;
70
+ }
71
+
72
return csr_ops[csrno].predicate(env, csrno);
81
}
73
}
82
74
83
static void rvxx_sifive_u_cpu_init(Object *obj)
84
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_u_cpu_init(Object *obj)
85
CPURISCVState *env = &RISCV_CPU(obj)->env;
86
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
87
set_priv_version(env, PRIV_VERSION_1_10_0);
88
- set_resetvec(env, 0x1004);
89
}
90
91
static void rvxx_sifive_e_cpu_init(Object *obj)
92
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_e_cpu_init(Object *obj)
93
CPURISCVState *env = &RISCV_CPU(obj)->env;
94
set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
95
set_priv_version(env, PRIV_VERSION_1_10_0);
96
- set_resetvec(env, 0x1004);
97
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
98
}
99
100
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
101
CPURISCVState *env = &RISCV_CPU(obj)->env;
102
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
103
set_priv_version(env, PRIV_VERSION_1_10_0);
104
- set_resetvec(env, 0x8090);
105
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
106
}
107
108
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
109
set_feature(env, RISCV_FEATURE_PMP);
110
}
111
112
+ set_resetvec(env, cpu->cfg.resetvec);
113
+
114
/* If misa isn't set (rv32 and rv64 machines) set it here */
115
if (!env->misa) {
116
/* Do some ISA extension error checking */
117
--
75
--
118
2.28.0
76
2.35.1
119
120
diff view generated by jsdifflib
New patch
[PULL v2 09/31] target/riscv: cpu: Fixup indentation
1
From: Alistair Francis <alistair.francis@wdc.com>
1
2
3
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
4
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-Id: <20220317061817.3856850-2-alistair.francis@opensource.wdc.com>
7
---
8
target/riscv/cpu.c | 20 ++++++++++----------
9
1 file changed, 10 insertions(+), 10 deletions(-)
10
11
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/riscv/cpu.c
14
+++ b/target/riscv/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
16
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
17
error_setg(errp,
18
"I and E extensions are incompatible");
19
- return;
20
- }
21
+ return;
22
+ }
23
24
if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
25
error_setg(errp,
26
"Either I or E extension must be set");
27
- return;
28
- }
29
+ return;
30
+ }
31
32
- if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
33
- cpu->cfg.ext_a & cpu->cfg.ext_f &
34
- cpu->cfg.ext_d)) {
35
+ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
36
+ cpu->cfg.ext_a & cpu->cfg.ext_f &
37
+ cpu->cfg.ext_d)) {
38
warn_report("Setting G will also set IMAFD");
39
cpu->cfg.ext_i = true;
40
cpu->cfg.ext_m = true;
41
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
42
case IRQ_S_EXT:
43
case IRQ_VS_EXT:
44
case IRQ_M_EXT:
45
- if (kvm_enabled()) {
46
+ if (kvm_enabled()) {
47
kvm_riscv_set_irq(cpu, irq, level);
48
- } else {
49
+ } else {
50
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
51
- }
52
+ }
53
break;
54
default:
55
g_assert_not_reached();
56
--
57
2.35.1
diff view generated by jsdifflib
[PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
[PULL v2 10/31] target/riscv: Allow software access to MIP SEIP
1
From: Yifei Jiang <jiangyifei@huawei.com>
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
When the cause number is equal to or greater than 23, print "(unknown)" in
3
The RISC-V specification states that:
4
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
4
"Supervisor-level external interrupts are made pending based on the
5
excpetion "guest_store_page_fault" can not be printed.
5
logical-OR of the software-writable SEIP bit and the signal from the
6
external interrupt controller."
6
7
7
In addition, the current check of cause is invalid for riscv_intr_names. So
8
We currently only allow either the interrupt controller or software to
8
introduce riscv_cpu_get_trap_name to get the trap cause name.
9
set the bit, which is incorrect.
9
10
10
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
11
This patch removes the miclaim mask when writing MIP to allow M-mode
11
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
12
software to inject interrupts, even with an interrupt controller.
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
13
Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
14
We then also need to keep track of which source is setting MIP_SEIP. The
15
final value is a OR of both, so we add two bools and use that to keep
16
track of the current state. This way either source can change without
17
losing the correct value.
18
19
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
21
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-Id: <20220317061817.3856850-3-alistair.francis@opensource.wdc.com>
15
---
24
---
16
target/riscv/cpu.h | 1 +
25
target/riscv/cpu.h | 8 ++++++++
17
target/riscv/cpu.c | 11 +++++++++++
26
target/riscv/cpu.c | 10 +++++++++-
18
target/riscv/cpu_helper.c | 4 ++--
27
target/riscv/csr.c | 8 ++++++--
19
3 files changed, 14 insertions(+), 2 deletions(-)
28
3 files changed, 23 insertions(+), 3 deletions(-)
20
29
21
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
30
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
22
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
23
--- a/target/riscv/cpu.h
32
--- a/target/riscv/cpu.h
24
+++ b/target/riscv/cpu.h
33
+++ b/target/riscv/cpu.h
25
@@ -XXX,XX +XXX,XX @@ extern const char * const riscv_fpr_regnames[];
34
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
26
extern const char * const riscv_excp_names[];
35
uint64_t mstatus;
27
extern const char * const riscv_intr_names[];
36
28
37
uint64_t mip;
29
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
38
+ /*
30
void riscv_cpu_do_interrupt(CPUState *cpu);
39
+ * MIP contains the software writable version of SEIP ORed with the
31
int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
40
+ * external interrupt value. The MIP register is always up-to-date.
32
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
41
+ * To keep track of the current source, we also save booleans of the values
42
+ * here.
43
+ */
44
+ bool external_seip;
45
+ bool software_seip;
46
47
uint64_t miclaim;
48
33
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
49
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
34
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
35
--- a/target/riscv/cpu.c
51
--- a/target/riscv/cpu.c
36
+++ b/target/riscv/cpu.c
52
+++ b/target/riscv/cpu.c
37
@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
53
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
38
"reserved"
54
case IRQ_VS_TIMER:
39
};
55
case IRQ_M_TIMER:
40
56
case IRQ_U_EXT:
41
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
57
- case IRQ_S_EXT:
42
+{
58
case IRQ_VS_EXT:
43
+ if (async) {
59
case IRQ_M_EXT:
44
+ return (cause < ARRAY_SIZE(riscv_intr_names)) ?
60
if (kvm_enabled()) {
45
+ riscv_intr_names[cause] : "(unknown)";
61
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
46
+ } else {
62
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
47
+ return (cause < ARRAY_SIZE(riscv_excp_names)) ?
63
}
48
+ riscv_excp_names[cause] : "(unknown)";
64
break;
65
+ case IRQ_S_EXT:
66
+ if (kvm_enabled()) {
67
+ kvm_riscv_set_irq(cpu, irq, level);
68
+ } else {
69
+ env->external_seip = level;
70
+ riscv_cpu_update_mip(cpu, 1 << irq,
71
+ BOOL_TO_MASK(level | env->software_seip));
72
+ }
73
+ break;
74
default:
75
g_assert_not_reached();
76
}
77
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/riscv/csr.c
80
+++ b/target/riscv/csr.c
81
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
82
uint64_t new_val, uint64_t wr_mask)
83
{
84
RISCVCPU *cpu = env_archcpu(env);
85
- /* Allow software control of delegable interrupts not claimed by hardware */
86
- uint64_t old_mip, mask = wr_mask & delegable_ints & ~env->miclaim;
87
+ uint64_t old_mip, mask = wr_mask & delegable_ints;
88
uint32_t gin;
89
90
+ if (mask & MIP_SEIP) {
91
+ env->software_seip = new_val & MIP_SEIP;
92
+ new_val |= env->external_seip * MIP_SEIP;
49
+ }
93
+ }
50
+}
51
+
94
+
52
static void set_misa(CPURISCVState *env, target_ulong misa)
95
if (mask) {
53
{
96
old_mip = riscv_cpu_update_mip(cpu, mask, (new_val & mask));
54
env->misa_mask = env->misa = misa;
97
} else {
55
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/riscv/cpu_helper.c
58
+++ b/target/riscv/cpu_helper.c
59
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
60
}
61
}
62
63
- trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
64
- (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
65
+ trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
66
+ riscv_cpu_get_trap_name(cause, async));
67
68
if (env->priv <= PRV_S &&
69
cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
70
--
98
--
71
2.28.0
99
2.35.1
72
73
diff view generated by jsdifflib
[PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
[PULL v2 11/31] target/riscv: Add initial support for the Sdtrig extension
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
This is an initial support for Microchip PolarFire SoC Icicle Kit.
3
This adds initial support for the Sdtrig extension via the Trigger
4
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
4
Module, as defined in the RISC-V Debug Specification [1].
5
E51 plus four U54 cores and many on-chip peripherals and an FPGA.
6
5
7
For more details about Microchip PolarFire Soc, please see:
6
Only "Address / Data Match" trigger (type 2) is implemented as of now,
8
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
7
which is mainly used for hardware breakpoint and watchpoint. The number
8
of type 2 triggers implemented is 2, which is the number that we can
9
find in the SiFive U54/U74 cores.
9
10
10
Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
11
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
11
The following perepherals are created as an unimplemented device:
12
13
- Bus Error Uint 0/1/2/3/4
14
- L2 cache controller
15
- SYSREG
16
- MPUCFG
17
- IOSCBCFG
18
19
More devices will be added later.
20
21
The BIOS image used by this machine is hss.bin, aka Hart Software
22
Services, which can be built from:
23
https://github.com/polarfire-soc/hart-software-services
24
25
To launch this machine:
26
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit
27
28
The memory is set to 1 GiB by default to match the hardware.
29
A sanity check on ram size is performed in the machine init routine
30
to prompt user to increase the RAM size to > 1 GiB when less than
31
1 GiB ram is detected.
32
12
33
Signed-off-by: Bin Meng <bin.meng@windriver.com>
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
34
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
35
Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
15
Message-Id: <20220315065529.62198-2-bmeng.cn@gmail.com>
36
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
37
---
17
---
38
default-configs/riscv64-softmmu.mak | 1 +
18
target/riscv/cpu.h | 5 +
39
include/hw/riscv/microchip_pfsoc.h | 88 ++++++++
19
target/riscv/debug.h | 108 +++++++++++++
40
hw/riscv/microchip_pfsoc.c | 312 ++++++++++++++++++++++++++++
20
target/riscv/debug.c | 339 +++++++++++++++++++++++++++++++++++++++
41
MAINTAINERS | 7 +
21
target/riscv/meson.build | 1 +
42
hw/riscv/Kconfig | 6 +
22
4 files changed, 453 insertions(+)
43
hw/riscv/meson.build | 1 +
23
create mode 100644 target/riscv/debug.h
44
6 files changed, 415 insertions(+)
24
create mode 100644 target/riscv/debug.c
45
create mode 100644 include/hw/riscv/microchip_pfsoc.h
46
create mode 100644 hw/riscv/microchip_pfsoc.c
47
25
48
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
26
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
49
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
50
--- a/default-configs/riscv64-softmmu.mak
28
--- a/target/riscv/cpu.h
51
+++ b/default-configs/riscv64-softmmu.mak
29
+++ b/target/riscv/cpu.h
52
@@ -XXX,XX +XXX,XX @@ CONFIG_SPIKE=y
30
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState CPURISCVState;
53
CONFIG_SIFIVE_E=y
31
54
CONFIG_SIFIVE_U=y
32
#if !defined(CONFIG_USER_ONLY)
55
CONFIG_RISCV_VIRT=y
33
#include "pmp.h"
56
+CONFIG_MICROCHIP_PFSOC=y
34
+#include "debug.h"
57
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
35
#endif
36
37
#define RV_VLEN_MAX 1024
38
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
39
pmp_table_t pmp_state;
40
target_ulong mseccfg;
41
42
+ /* trigger module */
43
+ target_ulong trigger_cur;
44
+ type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM];
45
+
46
/* machine specific rdtime callback */
47
uint64_t (*rdtime_fn)(uint32_t);
48
uint32_t rdtime_fn_arg;
49
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
58
new file mode 100644
50
new file mode 100644
59
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
60
--- /dev/null
52
--- /dev/null
61
+++ b/include/hw/riscv/microchip_pfsoc.h
53
+++ b/target/riscv/debug.h
62
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
63
+/*
55
+/*
64
+ * Microchip PolarFire SoC machine interface
56
+ * QEMU RISC-V Native Debug Support
65
+ *
57
+ *
66
+ * Copyright (c) 2020 Wind River Systems, Inc.
58
+ * Copyright (c) 2022 Wind River Systems, Inc.
67
+ *
59
+ *
68
+ * Author:
60
+ * Author:
69
+ * Bin Meng <bin.meng@windriver.com>
61
+ * Bin Meng <bin.meng@windriver.com>
70
+ *
62
+ *
71
+ * This program is free software; you can redistribute it and/or modify it
63
+ * This program is free software; you can redistribute it and/or modify it
...
...
79
+ *
71
+ *
80
+ * You should have received a copy of the GNU General Public License along with
72
+ * You should have received a copy of the GNU General Public License along with
81
+ * this program. If not, see <http://www.gnu.org/licenses/>.
73
+ * this program. If not, see <http://www.gnu.org/licenses/>.
82
+ */
74
+ */
83
+
75
+
84
+#ifndef HW_MICROCHIP_PFSOC_H
76
+#ifndef RISCV_DEBUG_H
85
+#define HW_MICROCHIP_PFSOC_H
77
+#define RISCV_DEBUG_H
86
+
78
+
87
+typedef struct MicrochipPFSoCState {
79
+/* trigger indexes implemented */
88
+ /*< private >*/
89
+ DeviceState parent_obj;
90
+
91
+ /*< public >*/
92
+ CPUClusterState e_cluster;
93
+ CPUClusterState u_cluster;
94
+ RISCVHartArrayState e_cpus;
95
+ RISCVHartArrayState u_cpus;
96
+ DeviceState *plic;
97
+} MicrochipPFSoCState;
98
+
99
+#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
100
+#define MICROCHIP_PFSOC(obj) \
101
+ OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
102
+
103
+typedef struct MicrochipIcicleKitState {
104
+ /*< private >*/
105
+ MachineState parent_obj;
106
+
107
+ /*< public >*/
108
+ MicrochipPFSoCState soc;
109
+} MicrochipIcicleKitState;
110
+
111
+#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
112
+ MACHINE_TYPE_NAME("microchip-icicle-kit")
113
+#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
114
+ OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
115
+ TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
116
+
117
+enum {
80
+enum {
118
+ MICROCHIP_PFSOC_DEBUG,
81
+ TRIGGER_TYPE2_IDX_0 = 0,
119
+ MICROCHIP_PFSOC_E51_DTIM,
82
+ TRIGGER_TYPE2_IDX_1,
120
+ MICROCHIP_PFSOC_BUSERR_UNIT0,
83
+ TRIGGER_TYPE2_NUM,
121
+ MICROCHIP_PFSOC_BUSERR_UNIT1,
84
+ TRIGGER_NUM = TRIGGER_TYPE2_NUM
122
+ MICROCHIP_PFSOC_BUSERR_UNIT2,
85
+};
123
+ MICROCHIP_PFSOC_BUSERR_UNIT3,
86
+
124
+ MICROCHIP_PFSOC_BUSERR_UNIT4,
87
+/* register index of tdata CSRs */
125
+ MICROCHIP_PFSOC_CLINT,
88
+enum {
126
+ MICROCHIP_PFSOC_L2CC,
89
+ TDATA1 = 0,
127
+ MICROCHIP_PFSOC_L2LIM,
90
+ TDATA2,
128
+ MICROCHIP_PFSOC_PLIC,
91
+ TDATA3,
129
+ MICROCHIP_PFSOC_SYSREG,
92
+ TDATA_NUM
130
+ MICROCHIP_PFSOC_MPUCFG,
93
+};
131
+ MICROCHIP_PFSOC_ENVM_CFG,
94
+
132
+ MICROCHIP_PFSOC_ENVM_DATA,
95
+typedef enum {
133
+ MICROCHIP_PFSOC_IOSCB_CFG,
96
+ TRIGGER_TYPE_NO_EXIST = 0, /* trigger does not exist */
134
+ MICROCHIP_PFSOC_DRAM,
97
+ TRIGGER_TYPE_AD_MATCH = 2, /* address/data match trigger */
135
+};
98
+ TRIGGER_TYPE_INST_CNT = 3, /* instruction count trigger */
136
+
99
+ TRIGGER_TYPE_INT = 4, /* interrupt trigger */
137
+#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
100
+ TRIGGER_TYPE_EXCP = 5, /* exception trigger */
138
+#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
101
+ TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */
139
+
102
+ TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */
140
+#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
103
+ TRIGGER_TYPE_UNAVAIL = 15 /* trigger exists, but unavailable */
141
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
104
+} trigger_type_t;
142
+#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
105
+
143
+#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
106
+typedef struct {
144
+#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000
107
+ target_ulong mcontrol;
145
+#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000
108
+ target_ulong maddress;
146
+#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80
109
+ struct CPUBreakpoint *bp;
147
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000
110
+ struct CPUWatchpoint *wp;
148
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000
111
+} type2_trigger_t;
149
+
112
+
150
+#endif /* HW_MICROCHIP_PFSOC_H */
113
+/* tdata field masks */
151
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
114
+
115
+#define RV32_TYPE(t) ((uint32_t)(t) << 28)
116
+#define RV32_TYPE_MASK (0xf << 28)
117
+#define RV32_DMODE BIT(27)
118
+#define RV64_TYPE(t) ((uint64_t)(t) << 60)
119
+#define RV64_TYPE_MASK (0xfULL << 60)
120
+#define RV64_DMODE BIT_ULL(59)
121
+
122
+/* mcontrol field masks */
123
+
124
+#define TYPE2_LOAD BIT(0)
125
+#define TYPE2_STORE BIT(1)
126
+#define TYPE2_EXEC BIT(2)
127
+#define TYPE2_U BIT(3)
128
+#define TYPE2_S BIT(4)
129
+#define TYPE2_M BIT(6)
130
+#define TYPE2_MATCH (0xf << 7)
131
+#define TYPE2_CHAIN BIT(11)
132
+#define TYPE2_ACTION (0xf << 12)
133
+#define TYPE2_SIZELO (0x3 << 16)
134
+#define TYPE2_TIMING BIT(18)
135
+#define TYPE2_SELECT BIT(19)
136
+#define TYPE2_HIT BIT(20)
137
+#define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */
138
+
139
+/* access size */
140
+enum {
141
+ SIZE_ANY = 0,
142
+ SIZE_1B,
143
+ SIZE_2B,
144
+ SIZE_4B,
145
+ SIZE_6B,
146
+ SIZE_8B,
147
+ SIZE_10B,
148
+ SIZE_12B,
149
+ SIZE_14B,
150
+ SIZE_16B,
151
+ SIZE_NUM = 16
152
+};
153
+
154
+bool tdata_available(CPURISCVState *env, int tdata_index);
155
+
156
+target_ulong tselect_csr_read(CPURISCVState *env);
157
+void tselect_csr_write(CPURISCVState *env, target_ulong val);
158
+
159
+target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
160
+void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
161
+
162
+#endif /* RISCV_DEBUG_H */
163
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
152
new file mode 100644
164
new file mode 100644
153
index XXXXXXX..XXXXXXX
165
index XXXXXXX..XXXXXXX
154
--- /dev/null
166
--- /dev/null
155
+++ b/hw/riscv/microchip_pfsoc.c
167
+++ b/target/riscv/debug.c
156
@@ -XXX,XX +XXX,XX @@
168
@@ -XXX,XX +XXX,XX @@
157
+/*
169
+/*
158
+ * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
170
+ * QEMU RISC-V Native Debug Support
159
+ *
171
+ *
160
+ * Copyright (c) 2020 Wind River Systems, Inc.
172
+ * Copyright (c) 2022 Wind River Systems, Inc.
161
+ *
173
+ *
162
+ * Author:
174
+ * Author:
163
+ * Bin Meng <bin.meng@windriver.com>
175
+ * Bin Meng <bin.meng@windriver.com>
164
+ *
176
+ *
165
+ * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
177
+ * This provides the native debug support via the Trigger Module, as defined
166
+ *
178
+ * in the RISC-V Debug Specification:
167
+ * 0) CLINT (Core Level Interruptor)
179
+ * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
168
+ * 1) PLIC (Platform Level Interrupt Controller)
169
+ * 2) eNVM (Embedded Non-Volatile Memory)
170
+ *
171
+ * This board currently generates devicetree dynamically that indicates at least
172
+ * two harts and up to five harts.
173
+ *
180
+ *
174
+ * This program is free software; you can redistribute it and/or modify it
181
+ * This program is free software; you can redistribute it and/or modify it
175
+ * under the terms and conditions of the GNU General Public License,
182
+ * under the terms and conditions of the GNU General Public License,
176
+ * version 2 or later, as published by the Free Software Foundation.
183
+ * version 2 or later, as published by the Free Software Foundation.
177
+ *
184
+ *
...
...
183
+ * You should have received a copy of the GNU General Public License along with
190
+ * You should have received a copy of the GNU General Public License along with
184
+ * this program. If not, see <http://www.gnu.org/licenses/>.
191
+ * this program. If not, see <http://www.gnu.org/licenses/>.
185
+ */
192
+ */
186
+
193
+
187
+#include "qemu/osdep.h"
194
+#include "qemu/osdep.h"
188
+#include "qemu/error-report.h"
189
+#include "qemu/log.h"
195
+#include "qemu/log.h"
190
+#include "qemu/units.h"
191
+#include "qemu/cutils.h"
192
+#include "qapi/error.h"
196
+#include "qapi/error.h"
193
+#include "hw/boards.h"
197
+#include "cpu.h"
194
+#include "hw/irq.h"
198
+#include "trace.h"
195
+#include "hw/loader.h"
199
+#include "exec/exec-all.h"
196
+#include "hw/sysbus.h"
197
+#include "hw/cpu/cluster.h"
198
+#include "target/riscv/cpu.h"
199
+#include "hw/misc/unimp.h"
200
+#include "hw/riscv/boot.h"
201
+#include "hw/riscv/riscv_hart.h"
202
+#include "hw/riscv/sifive_clint.h"
203
+#include "hw/riscv/sifive_plic.h"
204
+#include "hw/riscv/microchip_pfsoc.h"
205
+
200
+
206
+/*
201
+/*
207
+ * The BIOS image used by this machine is called Hart Software Services (HSS).
202
+ * The following M-mode trigger CSRs are implemented:
208
+ * See https://github.com/polarfire-soc/hart-software-services
203
+ *
204
+ * - tselect
205
+ * - tdata1
206
+ * - tdata2
207
+ * - tdata3
208
+ *
209
+ * We don't support writable 'type' field in the tdata1 register, so there is
210
+ * no need to implement the "tinfo" CSR.
211
+ *
212
+ * The following triggers are implemented:
213
+ *
214
+ * Index | Type | tdata mapping | Description
215
+ * ------+------+------------------------+------------
216
+ * 0 | 2 | tdata1, tdata2 | Address / Data Match
217
+ * 1 | 2 | tdata1, tdata2 | Address / Data Match
209
+ */
218
+ */
210
+#define BIOS_FILENAME "hss.bin"
219
+
211
+#define RESET_VECTOR 0x20220000
220
+/* tdata availability of a trigger */
212
+
221
+typedef bool tdata_avail[TDATA_NUM];
213
+static const struct MemmapEntry {
222
+
214
+ hwaddr base;
223
+static tdata_avail tdata_mapping[TRIGGER_NUM] = {
215
+ hwaddr size;
224
+ [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = { true, true, false },
216
+} microchip_pfsoc_memmap[] = {
225
+};
217
+ [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 },
226
+
218
+ [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
227
+/* only breakpoint size 1/2/4/8 supported */
219
+ [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
228
+static int access_size[SIZE_NUM] = {
220
+ [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
229
+ [SIZE_ANY] = 0,
221
+ [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
230
+ [SIZE_1B] = 1,
222
+ [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
231
+ [SIZE_2B] = 2,
223
+ [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
232
+ [SIZE_4B] = 4,
224
+ [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
233
+ [SIZE_6B] = -1,
225
+ [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
234
+ [SIZE_8B] = 8,
226
+ [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
235
+ [6 ... 15] = -1,
227
+ [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
236
+};
228
+ [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
237
+
229
+ [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
238
+static inline target_ulong trigger_type(CPURISCVState *env,
230
+ [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
239
+ trigger_type_t type)
231
+ [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
240
+{
232
+ [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
241
+ target_ulong tdata1;
233
+ [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
242
+
234
+};
243
+ switch (riscv_cpu_mxl(env)) {
235
+
244
+ case MXL_RV32:
236
+static void microchip_pfsoc_soc_instance_init(Object *obj)
245
+ tdata1 = RV32_TYPE(type);
237
+{
246
+ break;
238
+ MachineState *ms = MACHINE(qdev_get_machine());
247
+ case MXL_RV64:
239
+ MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
248
+ tdata1 = RV64_TYPE(type);
240
+
249
+ break;
241
+ object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
250
+ default:
242
+ qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
251
+ g_assert_not_reached();
243
+
252
+ }
244
+ object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
253
+
245
+ TYPE_RISCV_HART_ARRAY);
254
+ return tdata1;
246
+ qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
255
+}
247
+ qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
256
+
248
+ qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
257
+bool tdata_available(CPURISCVState *env, int tdata_index)
249
+ TYPE_RISCV_CPU_SIFIVE_E51);
258
+{
250
+ qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
259
+ if (unlikely(tdata_index >= TDATA_NUM)) {
251
+
260
+ return false;
252
+ object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
261
+ }
253
+ qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
262
+
254
+
263
+ if (unlikely(env->trigger_cur >= TRIGGER_NUM)) {
255
+ object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
264
+ return false;
256
+ TYPE_RISCV_HART_ARRAY);
265
+ }
257
+ qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
266
+
258
+ qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
267
+ return tdata_mapping[env->trigger_cur][tdata_index];
259
+ qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
268
+}
260
+ TYPE_RISCV_CPU_SIFIVE_U54);
269
+
261
+ qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
270
+target_ulong tselect_csr_read(CPURISCVState *env)
262
+}
271
+{
263
+
272
+ return env->trigger_cur;
264
+static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
273
+}
265
+{
274
+
266
+ MachineState *ms = MACHINE(qdev_get_machine());
275
+void tselect_csr_write(CPURISCVState *env, target_ulong val)
267
+ MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
276
+{
268
+ const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
277
+ /* all target_ulong bits of tselect are implemented */
269
+ MemoryRegion *system_memory = get_system_memory();
278
+ env->trigger_cur = val;
270
+ MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
279
+}
271
+ MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
280
+
272
+ MemoryRegion *envm_data = g_new(MemoryRegion, 1);
281
+static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
273
+ char *plic_hart_config;
282
+ trigger_type_t t)
274
+ size_t plic_hart_config_len;
283
+{
275
+ int i;
284
+ uint32_t type, dmode;
276
+
285
+ target_ulong tdata1;
277
+ sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
286
+
278
+ sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
287
+ switch (riscv_cpu_mxl(env)) {
279
+ /*
288
+ case MXL_RV32:
280
+ * The cluster must be realized after the RISC-V hart array container,
289
+ type = extract32(val, 28, 4);
281
+ * as the container's CPU object is only created on realize, and the
290
+ dmode = extract32(val, 27, 1);
282
+ * CPU must exist and have been parented into the cluster before the
291
+ tdata1 = RV32_TYPE(t);
283
+ * cluster is realized.
292
+ break;
284
+ */
293
+ case MXL_RV64:
285
+ qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
294
+ type = extract64(val, 60, 4);
286
+ qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
295
+ dmode = extract64(val, 59, 1);
287
+
296
+ tdata1 = RV64_TYPE(t);
288
+ /* E51 DTIM */
297
+ break;
289
+ memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
298
+ default:
290
+ memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
299
+ g_assert_not_reached();
291
+ memory_region_add_subregion(system_memory,
300
+ }
292
+ memmap[MICROCHIP_PFSOC_E51_DTIM].base,
301
+
293
+ e51_dtim_mem);
302
+ if (type != t) {
294
+
303
+ qemu_log_mask(LOG_GUEST_ERROR,
295
+ /* Bus Error Units */
304
+ "ignoring type write to tdata1 register\n");
296
+ create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
305
+ }
297
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
306
+ if (dmode != 0) {
298
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
307
+ qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n");
299
+ create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
308
+ }
300
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
309
+
301
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
310
+ return tdata1;
302
+ create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
311
+}
303
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
312
+
304
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
313
+static inline void warn_always_zero_bit(target_ulong val, target_ulong mask,
305
+ create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
314
+ const char *msg)
306
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
315
+{
307
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
316
+ if (val & mask) {
308
+ create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
317
+ qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg);
309
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
318
+ }
310
+ memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
319
+}
311
+
320
+
312
+ /* CLINT */
321
+static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
313
+ sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
322
+{
314
+ memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
323
+ uint32_t size, sizelo, sizehi = 0;
315
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
324
+
316
+
325
+ if (riscv_cpu_mxl(env) == MXL_RV64) {
317
+ /* L2 cache controller */
326
+ sizehi = extract32(ctrl, 21, 2);
318
+ create_unimplemented_device("microchip.pfsoc.l2cc",
327
+ }
319
+ memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
328
+ sizelo = extract32(ctrl, 16, 2);
320
+
329
+ size = (sizehi << 2) | sizelo;
321
+ /*
330
+
322
+ * Add L2-LIM at reset size.
331
+ return size;
323
+ * This should be reduced in size as the L2 Cache Controller WayEnable
332
+}
324
+ * register is incremented. Unfortunately I don't see a nice (or any) way
333
+
325
+ * to handle reducing or blocking out the L2 LIM while still allowing it
334
+static inline bool type2_breakpoint_enabled(target_ulong ctrl)
326
+ * be re returned to all enabled after a reset. For the time being, just
335
+{
327
+ * leave it enabled all the time. This won't break anything, but will be
336
+ bool mode = !!(ctrl & (TYPE2_U | TYPE2_S | TYPE2_M));
328
+ * too generous to misbehaving guests.
337
+ bool rwx = !!(ctrl & (TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC));
329
+ */
338
+
330
+ memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
339
+ return mode && rwx;
331
+ memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
340
+}
332
+ memory_region_add_subregion(system_memory,
341
+
333
+ memmap[MICROCHIP_PFSOC_L2LIM].base,
342
+static target_ulong type2_mcontrol_validate(CPURISCVState *env,
334
+ l2lim_mem);
343
+ target_ulong ctrl)
335
+
344
+{
336
+ /* create PLIC hart topology configuration string */
345
+ target_ulong val;
337
+ plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
346
+ uint32_t size;
338
+ ms->smp.cpus;
347
+
339
+ plic_hart_config = g_malloc0(plic_hart_config_len);
348
+ /* validate the generic part first */
340
+ for (i = 0; i < ms->smp.cpus; i++) {
349
+ val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH);
341
+ if (i != 0) {
350
+
342
+ strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
351
+ /* validate unimplemented (always zero) bits */
343
+ plic_hart_config_len);
352
+ warn_always_zero_bit(ctrl, TYPE2_MATCH, "match");
353
+ warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain");
354
+ warn_always_zero_bit(ctrl, TYPE2_ACTION, "action");
355
+ warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing");
356
+ warn_always_zero_bit(ctrl, TYPE2_SELECT, "select");
357
+ warn_always_zero_bit(ctrl, TYPE2_HIT, "hit");
358
+
359
+ /* validate size encoding */
360
+ size = type2_breakpoint_size(env, ctrl);
361
+ if (access_size[size] == -1) {
362
+ qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
363
+ size);
364
+ } else {
365
+ val |= (ctrl & TYPE2_SIZELO);
366
+ if (riscv_cpu_mxl(env) == MXL_RV64) {
367
+ val |= (ctrl & TYPE2_SIZEHI);
368
+ }
369
+ }
370
+
371
+ /* keep the mode and attribute bits */
372
+ val |= (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M |
373
+ TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC));
374
+
375
+ return val;
376
+}
377
+
378
+static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
379
+{
380
+ target_ulong ctrl = env->type2_trig[index].mcontrol;
381
+ target_ulong addr = env->type2_trig[index].maddress;
382
+ bool enabled = type2_breakpoint_enabled(ctrl);
383
+ CPUState *cs = env_cpu(env);
384
+ int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
385
+ uint32_t size;
386
+
387
+ if (!enabled) {
388
+ return;
389
+ }
390
+
391
+ if (ctrl & TYPE2_EXEC) {
392
+ cpu_breakpoint_insert(cs, addr, flags, &env->type2_trig[index].bp);
393
+ }
394
+
395
+ if (ctrl & TYPE2_LOAD) {
396
+ flags |= BP_MEM_READ;
397
+ }
398
+ if (ctrl & TYPE2_STORE) {
399
+ flags |= BP_MEM_WRITE;
400
+ }
401
+
402
+ if (flags & BP_MEM_ACCESS) {
403
+ size = type2_breakpoint_size(env, ctrl);
404
+ if (size != 0) {
405
+ cpu_watchpoint_insert(cs, addr, size, flags,
406
+ &env->type2_trig[index].wp);
344
+ } else {
407
+ } else {
345
+ strncat(plic_hart_config, "M", plic_hart_config_len);
408
+ cpu_watchpoint_insert(cs, addr, 8, flags,
409
+ &env->type2_trig[index].wp);
346
+ }
410
+ }
347
+ plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
411
+ }
348
+ }
412
+}
349
+
413
+
350
+ /* PLIC */
414
+static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index)
351
+ s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
415
+{
352
+ plic_hart_config, 0,
416
+ CPUState *cs = env_cpu(env);
353
+ MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
417
+
354
+ MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
418
+ if (env->type2_trig[index].bp) {
355
+ MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
419
+ cpu_breakpoint_remove_by_ref(cs, env->type2_trig[index].bp);
356
+ MICROCHIP_PFSOC_PLIC_PENDING_BASE,
420
+ env->type2_trig[index].bp = NULL;
357
+ MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
421
+ }
358
+ MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
422
+
359
+ MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
423
+ if (env->type2_trig[index].wp) {
360
+ MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
424
+ cpu_watchpoint_remove_by_ref(cs, env->type2_trig[index].wp);
361
+ memmap[MICROCHIP_PFSOC_PLIC].size);
425
+ env->type2_trig[index].wp = NULL;
362
+ g_free(plic_hart_config);
426
+ }
363
+
427
+}
364
+ /* SYSREG */
428
+
365
+ create_unimplemented_device("microchip.pfsoc.sysreg",
429
+static target_ulong type2_reg_read(CPURISCVState *env,
366
+ memmap[MICROCHIP_PFSOC_SYSREG].base,
430
+ target_ulong trigger_index, int tdata_index)
367
+ memmap[MICROCHIP_PFSOC_SYSREG].size);
431
+{
368
+
432
+ uint32_t index = trigger_index - TRIGGER_TYPE2_IDX_0;
369
+ /* MPUCFG */
433
+ target_ulong tdata;
370
+ create_unimplemented_device("microchip.pfsoc.mpucfg",
434
+
371
+ memmap[MICROCHIP_PFSOC_MPUCFG].base,
435
+ switch (tdata_index) {
372
+ memmap[MICROCHIP_PFSOC_MPUCFG].size);
436
+ case TDATA1:
373
+
437
+ tdata = env->type2_trig[index].mcontrol;
374
+ /* eNVM */
438
+ break;
375
+ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
439
+ case TDATA2:
376
+ memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
440
+ tdata = env->type2_trig[index].maddress;
377
+ &error_fatal);
441
+ break;
378
+ memory_region_add_subregion(system_memory,
442
+ default:
379
+ memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
443
+ g_assert_not_reached();
380
+ envm_data);
444
+ }
381
+
445
+
382
+ /* IOSCBCFG */
446
+ return tdata;
383
+ create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
447
+}
384
+ memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
448
+
385
+ memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
449
+static void type2_reg_write(CPURISCVState *env, target_ulong trigger_index,
386
+}
450
+ int tdata_index, target_ulong val)
387
+
451
+{
388
+static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
452
+ uint32_t index = trigger_index - TRIGGER_TYPE2_IDX_0;
389
+{
453
+ target_ulong new_val;
390
+ DeviceClass *dc = DEVICE_CLASS(oc);
454
+
391
+
455
+ switch (tdata_index) {
392
+ dc->realize = microchip_pfsoc_soc_realize;
456
+ case TDATA1:
393
+ /* Reason: Uses serial_hds in realize function, thus can't be used twice */
457
+ new_val = type2_mcontrol_validate(env, val);
394
+ dc->user_creatable = false;
458
+ if (new_val != env->type2_trig[index].mcontrol) {
395
+}
459
+ env->type2_trig[index].mcontrol = new_val;
396
+
460
+ type2_breakpoint_remove(env, index);
397
+static const TypeInfo microchip_pfsoc_soc_type_info = {
461
+ type2_breakpoint_insert(env, index);
398
+ .name = TYPE_MICROCHIP_PFSOC,
462
+ }
399
+ .parent = TYPE_DEVICE,
463
+ break;
400
+ .instance_size = sizeof(MicrochipPFSoCState),
464
+ case TDATA2:
401
+ .instance_init = microchip_pfsoc_soc_instance_init,
465
+ if (val != env->type2_trig[index].maddress) {
402
+ .class_init = microchip_pfsoc_soc_class_init,
466
+ env->type2_trig[index].maddress = val;
403
+};
467
+ type2_breakpoint_remove(env, index);
404
+
468
+ type2_breakpoint_insert(env, index);
405
+static void microchip_pfsoc_soc_register_types(void)
469
+ }
406
+{
470
+ break;
407
+ type_register_static(&microchip_pfsoc_soc_type_info);
471
+ default:
408
+}
472
+ g_assert_not_reached();
409
+
473
+ }
410
+type_init(microchip_pfsoc_soc_register_types)
474
+
411
+
475
+ return;
412
+static void microchip_icicle_kit_machine_init(MachineState *machine)
476
+}
413
+{
477
+
414
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
478
+typedef target_ulong (*tdata_read_func)(CPURISCVState *env,
415
+ const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
479
+ target_ulong trigger_index,
416
+ MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
480
+ int tdata_index);
417
+ MemoryRegion *system_memory = get_system_memory();
481
+
418
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
482
+static tdata_read_func trigger_read_funcs[TRIGGER_NUM] = {
419
+
483
+ [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = type2_reg_read,
420
+ /* Sanity check on RAM size */
484
+};
421
+ if (machine->ram_size < mc->default_ram_size) {
485
+
422
+ char *sz = size_to_str(mc->default_ram_size);
486
+typedef void (*tdata_write_func)(CPURISCVState *env,
423
+ error_report("Invalid RAM size, should be bigger than %s", sz);
487
+ target_ulong trigger_index,
424
+ g_free(sz);
488
+ int tdata_index,
425
+ exit(EXIT_FAILURE);
489
+ target_ulong val);
426
+ }
490
+
427
+
491
+static tdata_write_func trigger_write_funcs[TRIGGER_NUM] = {
428
+ /* Initialize SoC */
492
+ [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] = type2_reg_write,
429
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
493
+};
430
+ TYPE_MICROCHIP_PFSOC);
494
+
431
+ qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
495
+target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
432
+
496
+{
433
+ /* Register RAM */
497
+ tdata_read_func read_func = trigger_read_funcs[env->trigger_cur];
434
+ memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
498
+
435
+ machine->ram_size, &error_fatal);
499
+ return read_func(env, env->trigger_cur, tdata_index);
436
+ memory_region_add_subregion(system_memory,
500
+}
437
+ memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
501
+
438
+
502
+void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
439
+ /* Load the firmware */
503
+{
440
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
504
+ tdata_write_func write_func = trigger_write_funcs[env->trigger_cur];
441
+}
505
+
442
+
506
+ return write_func(env, env->trigger_cur, tdata_index, val);
443
+static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
507
+}
444
+{
508
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
445
+ MachineClass *mc = MACHINE_CLASS(oc);
446
+
447
+ mc->desc = "Microchip PolarFire SoC Icicle Kit";
448
+ mc->init = microchip_icicle_kit_machine_init;
449
+ mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
450
+ MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
451
+ mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
452
+ mc->default_cpus = mc->min_cpus;
453
+ mc->default_ram_size = 1 * GiB;
454
+}
455
+
456
+static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
457
+ .name = MACHINE_TYPE_NAME("microchip-icicle-kit"),
458
+ .parent = TYPE_MACHINE,
459
+ .class_init = microchip_icicle_kit_machine_class_init,
460
+ .instance_size = sizeof(MicrochipIcicleKitState),
461
+};
462
+
463
+static void microchip_icicle_kit_machine_init_register_types(void)
464
+{
465
+ type_register_static(&microchip_icicle_kit_machine_typeinfo);
466
+}
467
+
468
+type_init(microchip_icicle_kit_machine_init_register_types)
469
diff --git a/MAINTAINERS b/MAINTAINERS
470
index XXXXXXX..XXXXXXX 100644
509
index XXXXXXX..XXXXXXX 100644
471
--- a/MAINTAINERS
510
--- a/target/riscv/meson.build
472
+++ b/MAINTAINERS
511
+++ b/target/riscv/meson.build
473
@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/opentitan.h
512
@@ -XXX,XX +XXX,XX @@ riscv_softmmu_ss = ss.source_set()
474
F: include/hw/char/ibex_uart.h
513
riscv_softmmu_ss.add(files(
475
F: include/hw/intc/ibex_plic.h
514
'arch_dump.c',
476
515
'pmp.c',
477
+Microchip PolarFire SoC Icicle Kit
516
+ 'debug.c',
478
+M: Bin Meng <bin.meng@windriver.com>
517
'monitor.c',
479
+L: qemu-riscv@nongnu.org
518
'machine.c'
480
+S: Supported
519
))
481
+F: hw/riscv/microchip_pfsoc.c
482
+F: include/hw/riscv/microchip_pfsoc.h
483
+
484
RX Machines
485
-----------
486
rx-gdbsim
487
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
488
index XXXXXXX..XXXXXXX 100644
489
--- a/hw/riscv/Kconfig
490
+++ b/hw/riscv/Kconfig
491
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
492
select PCI_EXPRESS_GENERIC_BRIDGE
493
select PFLASH_CFI01
494
select SIFIVE
495
+
496
+config MICROCHIP_PFSOC
497
+ bool
498
+ select HART
499
+ select SIFIVE
500
+ select UNIMP
501
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
502
index XXXXXXX..XXXXXXX 100644
503
--- a/hw/riscv/meson.build
504
+++ b/hw/riscv/meson.build
505
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
506
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
507
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
508
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
509
+riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
510
511
hw_arch += {'riscv': riscv_ss}
512
--
520
--
513
2.28.0
521
2.35.1
514
515
diff view generated by jsdifflib
[PULL 26/30] hw/riscv: Move sifive_uart model to hw/char
[PULL v2 12/31] target/riscv: optimize condition assign for scale < 0
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
for some cases, scale is always equal or less than 0, since lmul is not larger than 3
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move sifive_uart model to hw/char directory.
6
4
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
5
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
9
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
7
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <20220325085902.29500-1-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
11
---
12
include/hw/{riscv => char}/sifive_uart.h | 0
12
target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
13
hw/{riscv => char}/sifive_uart.c | 2 +-
13
1 file changed, 3 insertions(+), 5 deletions(-)
14
hw/riscv/sifive_e.c | 2 +-
15
hw/riscv/sifive_u.c | 2 +-
16
hw/char/Kconfig | 3 +++
17
hw/char/meson.build | 1 +
18
hw/riscv/Kconfig | 2 ++
19
hw/riscv/meson.build | 1 -
20
8 files changed, 9 insertions(+), 4 deletions(-)
21
rename include/hw/{riscv => char}/sifive_uart.h (100%)
22
rename hw/{riscv => char}/sifive_uart.c (99%)
23
14
24
diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
15
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
25
similarity index 100%
26
rename from include/hw/riscv/sifive_uart.h
27
rename to include/hw/char/sifive_uart.h
28
diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
29
similarity index 99%
30
rename from hw/riscv/sifive_uart.c
31
rename to hw/char/sifive_uart.c
32
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/riscv/sifive_uart.c
17
--- a/target/riscv/insn_trans/trans_rvv.c.inc
34
+++ b/hw/char/sifive_uart.c
18
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
35
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
36
#include "chardev/char-fe.h"
20
static inline uint32_t MAXSZ(DisasContext *s)
37
#include "hw/hw.h"
21
{
38
#include "hw/irq.h"
22
int scale = s->lmul - 3;
39
-#include "hw/riscv/sifive_uart.h"
23
- return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
40
+#include "hw/char/sifive_uart.h"
24
+ return s->cfg_ptr->vlen >> -scale;
41
25
}
42
/*
26
43
* Not yet implemented:
27
static bool opivv_check(DisasContext *s, arg_rmrr *a)
44
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
28
@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
45
index XXXXXXX..XXXXXXX 100644
29
46
--- a/hw/riscv/sifive_e.c
30
if (a->vm && s->vl_eq_vlmax) {
47
+++ b/hw/riscv/sifive_e.c
31
int scale = s->lmul - (s->sew + 3);
48
@@ -XXX,XX +XXX,XX @@
32
- int vlmax = scale < 0 ?
49
#include "hw/misc/unimp.h"
33
- s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
50
#include "target/riscv/cpu.h"
34
+ int vlmax = s->cfg_ptr->vlen >> -scale;
51
#include "hw/riscv/riscv_hart.h"
35
TCGv_i64 dest = tcg_temp_new_i64();
52
-#include "hw/riscv/sifive_uart.h"
36
53
#include "hw/riscv/sifive_e.h"
37
if (a->rs1 == 0) {
54
#include "hw/riscv/boot.h"
38
@@ -XXX,XX +XXX,XX @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
55
+#include "hw/char/sifive_uart.h"
39
56
#include "hw/intc/sifive_clint.h"
40
if (a->vm && s->vl_eq_vlmax) {
57
#include "hw/intc/sifive_plic.h"
41
int scale = s->lmul - (s->sew + 3);
58
#include "hw/misc/sifive_e_prci.h"
42
- int vlmax = scale < 0 ?
59
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
43
- s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
60
index XXXXXXX..XXXXXXX 100644
44
+ int vlmax = s->cfg_ptr->vlen >> -scale;
61
--- a/hw/riscv/sifive_u.c
45
if (a->rs1 >= vlmax) {
62
+++ b/hw/riscv/sifive_u.c
46
tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
63
@@ -XXX,XX +XXX,XX @@
47
MAXSZ(s), MAXSZ(s), 0);
64
#include "hw/misc/unimp.h"
65
#include "target/riscv/cpu.h"
66
#include "hw/riscv/riscv_hart.h"
67
-#include "hw/riscv/sifive_uart.h"
68
#include "hw/riscv/sifive_u.h"
69
#include "hw/riscv/boot.h"
70
+#include "hw/char/sifive_uart.h"
71
#include "hw/intc/sifive_clint.h"
72
#include "hw/intc/sifive_plic.h"
73
#include "chardev/char.h"
74
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/char/Kconfig
77
+++ b/hw/char/Kconfig
78
@@ -XXX,XX +XXX,XX @@ config AVR_USART
79
80
config MCHP_PFSOC_MMUART
81
bool
82
+
83
+config SIFIVE_UART
84
+ bool
85
diff --git a/hw/char/meson.build b/hw/char/meson.build
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/char/meson.build
88
+++ b/hw/char/meson.build
89
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
90
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
91
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
92
softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
93
+softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
94
softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
95
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
96
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
97
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
98
index XXXXXXX..XXXXXXX 100644
99
--- a/hw/riscv/Kconfig
100
+++ b/hw/riscv/Kconfig
101
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
102
select SIFIVE_CLINT
103
select SIFIVE_GPIO
104
select SIFIVE_PLIC
105
+ select SIFIVE_UART
106
select SIFIVE_E_PRCI
107
select UNIMP
108
109
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
110
select SIFIVE_GPIO
111
select SIFIVE_PDMA
112
select SIFIVE_PLIC
113
+ select SIFIVE_UART
114
select SIFIVE_U_OTP
115
select SIFIVE_U_PRCI
116
select UNIMP
117
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
118
index XXXXXXX..XXXXXXX 100644
119
--- a/hw/riscv/meson.build
120
+++ b/hw/riscv/meson.build
121
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
122
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
123
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
124
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
125
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
126
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
127
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
128
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
129
--
48
--
130
2.28.0
49
2.35.1
131
132
diff view generated by jsdifflib
[PULL 21/30] hw/riscv: Move sifive_u_otp model to hw/misc
[PULL v2 13/31] target/riscv: optimize helper for vmv<nr>r.v
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmv<nr>r.v can share
4
should only contain the RISC-V SoC / machine codes plus generic
4
the same helper
5
codes. Let's move sifive_u_otp model to hw/misc directory.
6
5
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
7
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
8
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
10
Message-Id: <20220325085902.29500-2-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
12
---
12
include/hw/{riscv => misc}/sifive_u_otp.h | 0
13
target/riscv/helper.h | 5 +----
13
include/hw/riscv/sifive_u.h | 2 +-
14
target/riscv/vector_helper.c | 29 ++++++++++---------------
14
hw/{riscv => misc}/sifive_u_otp.c | 2 +-
15
target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++----------
15
hw/misc/Kconfig | 3 +++
16
3 files changed, 18 insertions(+), 33 deletions(-)
16
hw/misc/meson.build | 1 +
17
hw/riscv/Kconfig | 1 +
18
hw/riscv/meson.build | 1 -
19
7 files changed, 7 insertions(+), 3 deletions(-)
20
rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
21
rename hw/{riscv => misc}/sifive_u_otp.c (99%)
22
17
23
diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
18
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
24
similarity index 100%
25
rename from include/hw/riscv/sifive_u_otp.h
26
rename to include/hw/misc/sifive_u_otp.h
27
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
28
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/riscv/sifive_u.h
20
--- a/target/riscv/helper.h
30
+++ b/include/hw/riscv/sifive_u.h
21
+++ b/target/riscv/helper.h
31
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
32
#include "hw/riscv/riscv_hart.h"
23
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
33
#include "hw/riscv/sifive_cpu.h"
24
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
34
#include "hw/riscv/sifive_gpio.h"
25
35
-#include "hw/riscv/sifive_u_otp.h"
26
-DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32)
36
+#include "hw/misc/sifive_u_otp.h"
27
-DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32)
37
#include "hw/misc/sifive_u_prci.h"
28
-DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32)
38
29
-DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32)
39
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
30
+DEF_HELPER_4(vmvr_v, void, ptr, ptr, env, i32)
40
diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
31
41
similarity index 99%
32
DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
42
rename from hw/riscv/sifive_u_otp.c
33
DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
43
rename to hw/misc/sifive_u_otp.c
34
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
44
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/riscv/sifive_u_otp.c
36
--- a/target/riscv/vector_helper.c
46
+++ b/hw/misc/sifive_u_otp.c
37
+++ b/target/riscv/vector_helper.c
47
@@ -XXX,XX +XXX,XX @@
38
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
48
#include "hw/sysbus.h"
39
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
49
#include "qemu/log.h"
40
50
#include "qemu/module.h"
41
/* Vector Whole Register Move */
51
-#include "hw/riscv/sifive_u_otp.h"
42
-#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \
52
+#include "hw/misc/sifive_u_otp.h"
43
-void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
53
44
- uint32_t desc) \
54
static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
45
-{ \
46
- /* EEW = 8 */ \
47
- uint32_t maxsz = simd_maxsz(desc); \
48
- uint32_t i = env->vstart; \
49
- \
50
- memcpy((uint8_t *)vd + H1(i), \
51
- (uint8_t *)vs2 + H1(i), \
52
- maxsz - env->vstart); \
53
- \
54
- env->vstart = 0; \
55
-}
56
+void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
57
+{
58
+ /* EEW = 8 */
59
+ uint32_t maxsz = simd_maxsz(desc);
60
+ uint32_t i = env->vstart;
61
+
62
+ memcpy((uint8_t *)vd + H1(i),
63
+ (uint8_t *)vs2 + H1(i),
64
+ maxsz - env->vstart);
65
66
-GEN_VEXT_VMV_WHOLE(vmv1r_v, 1)
67
-GEN_VEXT_VMV_WHOLE(vmv2r_v, 2)
68
-GEN_VEXT_VMV_WHOLE(vmv4r_v, 4)
69
-GEN_VEXT_VMV_WHOLE(vmv8r_v, 8)
70
+ env->vstart = 0;
71
+}
72
73
/* Vector Integer Extension */
74
#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
75
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/riscv/insn_trans/trans_rvv.c.inc
78
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
80
* Whole Vector Register Move Instructions ignore vtype and vl setting.
81
* Thus, we don't need to check vill bit. (Section 16.6)
82
*/
83
-#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \
84
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
85
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
86
{ \
87
if (require_rvv(s) && \
88
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
89
} else { \
90
TCGLabel *over = gen_new_label(); \
91
tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
92
- \
93
- static gen_helper_gvec_2_ptr * const fns[4] = { \
94
- gen_helper_vmv1r_v, gen_helper_vmv2r_v, \
95
- gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
96
- }; \
97
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
98
- cpu_env, maxsz, maxsz, 0, fns[SEQ]); \
99
+ cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
100
mark_vs_dirty(s); \
101
gen_set_label(over); \
102
} \
103
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
104
return false; \
105
}
106
107
-GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0)
108
-GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1)
109
-GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2)
110
-GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3)
111
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
112
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
113
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
114
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
115
116
static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
55
{
117
{
56
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/Kconfig
59
+++ b/hw/misc/Kconfig
60
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
61
config SIFIVE_E_PRCI
62
bool
63
64
+config SIFIVE_U_OTP
65
+ bool
66
+
67
config SIFIVE_U_PRCI
68
bool
69
70
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/misc/meson.build
73
+++ b/hw/misc/meson.build
74
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
75
76
# RISC-V devices
77
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
78
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
79
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
80
81
# PKUnity SoC devices
82
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
83
index XXXXXXX..XXXXXXX 100644
84
--- a/hw/riscv/Kconfig
85
+++ b/hw/riscv/Kconfig
86
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
87
select HART
88
select SIFIVE
89
select SIFIVE_PDMA
90
+ select SIFIVE_U_OTP
91
select SIFIVE_U_PRCI
92
select UNIMP
93
94
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
95
index XXXXXXX..XXXXXXX 100644
96
--- a/hw/riscv/meson.build
97
+++ b/hw/riscv/meson.build
98
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
99
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
100
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
101
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
102
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
103
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
104
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
105
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
106
--
118
--
107
2.28.0
119
2.35.1
108
109
diff view generated by jsdifflib
[PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio
[PULL v2 14/31] target/riscv: misa to ISA string conversion fix
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Tsukasa OI <research_trasio@irq.a4lg.com>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
Some bits in RISC-V `misa' CSR should not be reflected in the ISA
4
should only contain the RISC-V SoC / machine codes plus generic
4
string. For instance, `S' and `U' (represents existence of supervisor
5
codes. Let's move sifive_gpio model to hw/gpio directory.
5
and user mode, respectively) in `misa' CSR must not be copied since
6
neither `S' nor `U' are valid single-letter extensions.
6
7
7
Note this also removes the trace-events in the hw/riscv directory,
8
This commit also removes all reserved/dropped single-letter "extensions"
8
since gpio is the only supported trace target in that directory.
9
from the list.
9
10
10
Signed-off-by: Bin Meng <bin.meng@windriver.com>
11
- "B": Not going to be a single-letter extension (misa.B is reserved).
12
- "J": Not going to be a single-letter extension (misa.J is reserved).
13
- "K": Not going to be a single-letter extension (misa.K is reserved).
14
- "L": Dropped.
15
- "N": Dropped.
16
- "T": Dropped.
17
18
It also clarifies that the variable `riscv_single_letter_exts' is a
19
single-letter extension order list.
20
21
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
22
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
23
Message-Id: <4a4c11213a161a7eedabe46abe58b351bb0e2ef2.1648473008.git.research_trasio@irq.a4lg.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
25
---
15
hw/riscv/trace.h | 1 -
26
target/riscv/cpu.c | 10 +++++-----
16
include/hw/{riscv => gpio}/sifive_gpio.h | 0
27
1 file changed, 5 insertions(+), 5 deletions(-)
17
include/hw/riscv/sifive_e.h | 2 +-
18
include/hw/riscv/sifive_u.h | 2 +-
19
hw/{riscv => gpio}/sifive_gpio.c | 2 +-
20
hw/gpio/Kconfig | 3 +++
21
hw/gpio/meson.build | 1 +
22
hw/gpio/trace-events | 6 ++++++
23
hw/riscv/Kconfig | 2 ++
24
hw/riscv/meson.build | 1 -
25
hw/riscv/trace-events | 7 -------
26
meson.build | 1 -
27
12 files changed, 15 insertions(+), 13 deletions(-)
28
delete mode 100644 hw/riscv/trace.h
29
rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
30
rename hw/{riscv => gpio}/sifive_gpio.c (99%)
31
delete mode 100644 hw/riscv/trace-events
32
28
33
diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
29
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
34
deleted file mode 100644
35
index XXXXXXX..XXXXXXX
36
--- a/hw/riscv/trace.h
37
+++ /dev/null
38
@@ -1 +0,0 @@
39
-#include "trace/trace-hw_riscv.h"
40
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
41
similarity index 100%
42
rename from include/hw/riscv/sifive_gpio.h
43
rename to include/hw/gpio/sifive_gpio.h
44
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
45
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
46
--- a/include/hw/riscv/sifive_e.h
31
--- a/target/riscv/cpu.c
47
+++ b/include/hw/riscv/sifive_e.h
32
+++ b/target/riscv/cpu.c
48
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@
49
34
50
#include "hw/riscv/riscv_hart.h"
35
/* RISC-V CPU definitions */
51
#include "hw/riscv/sifive_cpu.h"
36
52
-#include "hw/riscv/sifive_gpio.h"
37
-static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
53
+#include "hw/gpio/sifive_gpio.h"
38
+static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
54
39
55
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
40
const char * const riscv_int_regnames[] = {
56
#define RISCV_E_SOC(obj) \
41
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
57
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
42
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
58
index XXXXXXX..XXXXXXX 100644
43
char *riscv_isa_string(RISCVCPU *cpu)
59
--- a/include/hw/riscv/sifive_u.h
44
{
60
+++ b/include/hw/riscv/sifive_u.h
45
int i;
61
@@ -XXX,XX +XXX,XX @@
46
- const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
62
#include "hw/net/cadence_gem.h"
47
+ const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
63
#include "hw/riscv/riscv_hart.h"
48
char *isa_str = g_new(char, maxlen);
64
#include "hw/riscv/sifive_cpu.h"
49
char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
65
-#include "hw/riscv/sifive_gpio.h"
50
- for (i = 0; i < sizeof(riscv_exts); i++) {
66
+#include "hw/gpio/sifive_gpio.h"
51
- if (cpu->env.misa_ext & RV(riscv_exts[i])) {
67
#include "hw/misc/sifive_u_otp.h"
52
- *p++ = qemu_tolower(riscv_exts[i]);
68
#include "hw/misc/sifive_u_prci.h"
53
+ for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
69
54
+ if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
70
diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
55
+ *p++ = qemu_tolower(riscv_single_letter_exts[i]);
71
similarity index 99%
56
}
72
rename from hw/riscv/sifive_gpio.c
57
}
73
rename to hw/gpio/sifive_gpio.c
58
*p = '\0';
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/riscv/sifive_gpio.c
76
+++ b/hw/gpio/sifive_gpio.c
77
@@ -XXX,XX +XXX,XX @@
78
#include "qemu/log.h"
79
#include "hw/irq.h"
80
#include "hw/qdev-properties.h"
81
-#include "hw/riscv/sifive_gpio.h"
82
+#include "hw/gpio/sifive_gpio.h"
83
#include "migration/vmstate.h"
84
#include "trace.h"
85
86
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/gpio/Kconfig
89
+++ b/hw/gpio/Kconfig
90
@@ -XXX,XX +XXX,XX @@ config PL061
91
92
config GPIO_KEY
93
bool
94
+
95
+config SIFIVE_GPIO
96
+ bool
97
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
98
index XXXXXXX..XXXXXXX 100644
99
--- a/hw/gpio/meson.build
100
+++ b/hw/gpio/meson.build
101
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
102
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
103
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
104
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
105
+softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
106
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
107
index XXXXXXX..XXXXXXX 100644
108
--- a/hw/gpio/trace-events
109
+++ b/hw/gpio/trace-events
110
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
111
nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
112
nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
113
nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
114
+
115
+# sifive_gpio.c
116
+sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
117
+sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
118
+sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
119
+sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
120
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
121
index XXXXXXX..XXXXXXX 100644
122
--- a/hw/riscv/Kconfig
123
+++ b/hw/riscv/Kconfig
124
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
125
bool
126
select HART
127
select SIFIVE
128
+ select SIFIVE_GPIO
129
select SIFIVE_E_PRCI
130
select UNIMP
131
132
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
133
select CADENCE
134
select HART
135
select SIFIVE
136
+ select SIFIVE_GPIO
137
select SIFIVE_PDMA
138
select SIFIVE_U_OTP
139
select SIFIVE_U_PRCI
140
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
141
index XXXXXXX..XXXXXXX 100644
142
--- a/hw/riscv/meson.build
143
+++ b/hw/riscv/meson.build
144
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
145
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
146
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
147
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
148
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
149
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
150
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
151
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
152
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
153
deleted file mode 100644
154
index XXXXXXX..XXXXXXX
155
--- a/hw/riscv/trace-events
156
+++ /dev/null
157
@@ -XXX,XX +XXX,XX @@
158
-# See docs/devel/tracing.txt for syntax documentation.
159
-
160
-# hw/gpio/sifive_gpio.c
161
-sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
162
-sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
163
-sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
164
-sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
165
diff --git a/meson.build b/meson.build
166
index XXXXXXX..XXXXXXX 100644
167
--- a/meson.build
168
+++ b/meson.build
169
@@ -XXX,XX +XXX,XX @@ if have_system
170
'hw/watchdog',
171
'hw/xen',
172
'hw/gpio',
173
- 'hw/riscv',
174
'migration',
175
'net',
176
'ui',
177
--
59
--
178
2.28.0
60
2.35.1
179
180
diff view generated by jsdifflib
[PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
[PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Atish Patra <atishp@rivosinc.com>
2
2
3
Microchip PolarFire SoC integrates 2 Candence GEMs to provide
3
The Linux kernel parses the ISA extensions from "riscv,isa" DT
4
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
4
property. It used to parse only the single letter base extensions
5
until now. A generic ISA extension parsing framework was proposed[1]
6
recently that can parse multi-letter ISA extensions as well.
5
7
6
On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
8
Generate the extended ISA string by appending the available ISA extensions
7
GEM1 connects to a PHY at address 9.
9
to the "riscv,isa" string if it is enabled so that kernel can process it.
8
10
9
The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
11
[1] https://lkml.org/lkml/2022/2/15/263
10
must specify 2 '-nic' options from the command line in order to get
11
a working ethernet.
12
12
13
Signed-off-by: Bin Meng <bin.meng@windriver.com>
13
Reviewed-by: Anup Patel <anup@brainfault.org>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Reviewed-by: Frank Chang <frank.chang@sifive.com>
16
Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
16
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
17
Tested-by: Bin Meng <bmeng.cn@gmail.com>
18
Signed-off-by: Atish Patra <atishp@rivosinc.com>
19
Suggested-by: Heiko Stubner <heiko@sntech.de>
20
Signed-off-by: Atish Patra <atishp@rivosinc.com>
21
Message-Id: <20220329195657.1725425-1-atishp@rivosinc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
22
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
23
---
19
include/hw/riscv/microchip_pfsoc.h | 7 ++++++
24
target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++
20
hw/riscv/microchip_pfsoc.c | 39 ++++++++++++++++++++++++++++++
25
1 file changed, 60 insertions(+)
21
2 files changed, 46 insertions(+)
22
26
23
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
27
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
24
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/riscv/microchip_pfsoc.h
29
--- a/target/riscv/cpu.c
26
+++ b/include/hw/riscv/microchip_pfsoc.h
30
+++ b/target/riscv/cpu.c
27
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@
28
32
29
#include "hw/char/mchp_pfsoc_mmuart.h"
33
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
30
#include "hw/dma/sifive_pdma.h"
34
31
+#include "hw/net/cadence_gem.h"
35
+struct isa_ext_data {
32
#include "hw/sd/cadence_sdhci.h"
36
+ const char *name;
33
37
+ bool enabled;
34
typedef struct MicrochipPFSoCState {
38
+};
35
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
36
MchpPfSoCMMUartState *serial3;
37
MchpPfSoCMMUartState *serial4;
38
SiFivePDMAState dma;
39
+ CadenceGEMState gem0;
40
+ CadenceGEMState gem1;
41
CadenceSDHCIState sdhci;
42
} MicrochipPFSoCState;
43
44
@@ -XXX,XX +XXX,XX @@ enum {
45
MICROCHIP_PFSOC_MMUART2,
46
MICROCHIP_PFSOC_MMUART3,
47
MICROCHIP_PFSOC_MMUART4,
48
+ MICROCHIP_PFSOC_GEM0,
49
+ MICROCHIP_PFSOC_GEM1,
50
MICROCHIP_PFSOC_ENVM_CFG,
51
MICROCHIP_PFSOC_ENVM_DATA,
52
MICROCHIP_PFSOC_IOSCB_CFG,
53
@@ -XXX,XX +XXX,XX @@ enum {
54
MICROCHIP_PFSOC_DMA_IRQ5 = 10,
55
MICROCHIP_PFSOC_DMA_IRQ6 = 11,
56
MICROCHIP_PFSOC_DMA_IRQ7 = 12,
57
+ MICROCHIP_PFSOC_GEM0_IRQ = 64,
58
+ MICROCHIP_PFSOC_GEM1_IRQ = 70,
59
MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
60
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
61
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
62
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/hw/riscv/microchip_pfsoc.c
65
+++ b/hw/riscv/microchip_pfsoc.c
66
@@ -XXX,XX +XXX,XX @@
67
* 3) MMUARTs (Multi-Mode UART)
68
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
69
* 5) SiFive Platform DMA (Direct Memory Access Controller)
70
+ * 6) GEM (Gigabit Ethernet MAC Controller)
71
*
72
* This board currently generates devicetree dynamically that indicates at least
73
* two harts and up to five harts.
74
@@ -XXX,XX +XXX,XX @@
75
#define BIOS_FILENAME "hss.bin"
76
#define RESET_VECTOR 0x20220000
77
78
+/* GEM version */
79
+#define GEM_REVISION 0x0107010c
80
+
39
+
81
static const struct MemmapEntry {
40
const char * const riscv_int_regnames[] = {
82
hwaddr base;
41
"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
83
hwaddr size;
42
"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
84
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
43
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
85
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
44
device_class_set_props(dc, riscv_cpu_properties);
86
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
45
}
87
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
46
88
+ [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
47
+#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
89
+ [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
90
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
91
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
92
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
93
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
94
object_initialize_child(obj, "dma-controller", &s->dma,
95
TYPE_SIFIVE_PDMA);
96
97
+ object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
98
+ object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
99
+
48
+
100
object_initialize_child(obj, "sd-controller", &s->sdhci,
49
+static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
101
TYPE_CADENCE_SDHCI);
50
+{
102
}
51
+ char *old = *isa_str;
103
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
52
+ char *new = *isa_str;
104
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
53
+ int i;
105
char *plic_hart_config;
106
size_t plic_hart_config_len;
107
+ NICInfo *nd;
108
int i;
109
110
sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
111
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
112
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
113
serial_hd(4));
114
115
+ /* GEMs */
116
+
54
+
117
+ nd = &nd_table[0];
55
+ /**
118
+ if (nd->used) {
56
+ * Here are the ordering rules of extension naming defined by RISC-V
119
+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
57
+ * specification :
120
+ qdev_set_nic_properties(DEVICE(&s->gem0), nd);
58
+ * 1. All extensions should be separated from other multi-letter extensions
121
+ }
59
+ * by an underscore.
122
+ nd = &nd_table[1];
60
+ * 2. The first letter following the 'Z' conventionally indicates the most
123
+ if (nd->used) {
61
+ * closely related alphabetical extension category, IMAFDQLCBKJTPVH.
124
+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
62
+ * If multiple 'Z' extensions are named, they should be ordered first
125
+ qdev_set_nic_properties(DEVICE(&s->gem1), nd);
63
+ * by category, then alphabetically within a category.
64
+ * 3. Standard supervisor-level extensions (starts with 'S') should be
65
+ * listed after standard unprivileged extensions. If multiple
66
+ * supervisor-level extensions are listed, they should be ordered
67
+ * alphabetically.
68
+ * 4. Non-standard extensions (starts with 'X') must be listed after all
69
+ * standard extensions. They must be separated from other multi-letter
70
+ * extensions by an underscore.
71
+ */
72
+ struct isa_ext_data isa_edata_arr[] = {
73
+ ISA_EDATA_ENTRY(zfh, ext_zfh),
74
+ ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
75
+ ISA_EDATA_ENTRY(zfinx, ext_zfinx),
76
+ ISA_EDATA_ENTRY(zhinx, ext_zhinx),
77
+ ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
78
+ ISA_EDATA_ENTRY(zdinx, ext_zdinx),
79
+ ISA_EDATA_ENTRY(zba, ext_zba),
80
+ ISA_EDATA_ENTRY(zbb, ext_zbb),
81
+ ISA_EDATA_ENTRY(zbc, ext_zbc),
82
+ ISA_EDATA_ENTRY(zbs, ext_zbs),
83
+ ISA_EDATA_ENTRY(zve32f, ext_zve32f),
84
+ ISA_EDATA_ENTRY(zve64f, ext_zve64f),
85
+ ISA_EDATA_ENTRY(svinval, ext_svinval),
86
+ ISA_EDATA_ENTRY(svnapot, ext_svnapot),
87
+ ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
88
+ };
89
+
90
+ for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
91
+ if (isa_edata_arr[i].enabled) {
92
+ new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
93
+ g_free(old);
94
+ old = new;
95
+ }
126
+ }
96
+ }
127
+
97
+
128
+ object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
98
+ *isa_str = new;
129
+ object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
99
+}
130
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
131
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
132
+ memmap[MICROCHIP_PFSOC_GEM0].base);
133
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
134
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
135
+
100
+
136
+ object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
101
char *riscv_isa_string(RISCVCPU *cpu)
137
+ object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
102
{
138
+ sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
103
int i;
139
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
104
@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
140
+ memmap[MICROCHIP_PFSOC_GEM1].base);
105
}
141
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
106
}
142
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
107
*p = '\0';
143
+
108
+ riscv_isa_string_ext(cpu, &isa_str, maxlen);
144
/* eNVM */
109
return isa_str;
145
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
110
}
146
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
111
147
--
112
--
148
2.28.0
113
2.35.1
149
150
diff view generated by jsdifflib
[PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc
[PULL v2 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Weiwei Li <liweiwei@iscas.ac.cn>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW,
4
should only contain the RISC-V SoC / machine codes plus generic
4
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
5
codes. Let's move sifive_u_prci model to hw/misc directory.
6
5
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
So the start byte for vstart != 0 should take sew into account
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
9
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
8
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
9
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
10
Acked-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20220330021316.18223-1-liweiwei@iscas.ac.cn>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
13
---
12
include/hw/{riscv => misc}/sifive_u_prci.h | 0
14
target/riscv/vector_helper.c | 8 +++++---
13
include/hw/riscv/sifive_u.h | 2 +-
15
1 file changed, 5 insertions(+), 3 deletions(-)
14
hw/{riscv => misc}/sifive_u_prci.c | 2 +-
15
hw/misc/Kconfig | 3 +++
16
hw/misc/meson.build | 1 +
17
hw/riscv/Kconfig | 1 +
18
hw/riscv/meson.build | 1 -
19
7 files changed, 7 insertions(+), 3 deletions(-)
20
rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
21
rename hw/{riscv => misc}/sifive_u_prci.c (99%)
22
16
23
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
17
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
24
similarity index 100%
25
rename from include/hw/riscv/sifive_u_prci.h
26
rename to include/hw/misc/sifive_u_prci.h
27
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
28
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
29
--- a/include/hw/riscv/sifive_u.h
19
--- a/target/riscv/vector_helper.c
30
+++ b/include/hw/riscv/sifive_u.h
20
+++ b/target/riscv/vector_helper.c
31
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
32
#include "hw/riscv/riscv_hart.h"
22
/* Vector Whole Register Move */
33
#include "hw/riscv/sifive_cpu.h"
23
void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
34
#include "hw/riscv/sifive_gpio.h"
35
-#include "hw/riscv/sifive_u_prci.h"
36
#include "hw/riscv/sifive_u_otp.h"
37
+#include "hw/misc/sifive_u_prci.h"
38
39
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
40
#define RISCV_U_SOC(obj) \
41
diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
42
similarity index 99%
43
rename from hw/riscv/sifive_u_prci.c
44
rename to hw/misc/sifive_u_prci.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/riscv/sifive_u_prci.c
47
+++ b/hw/misc/sifive_u_prci.c
48
@@ -XXX,XX +XXX,XX @@
49
#include "hw/sysbus.h"
50
#include "qemu/log.h"
51
#include "qemu/module.h"
52
-#include "hw/riscv/sifive_u_prci.h"
53
+#include "hw/misc/sifive_u_prci.h"
54
55
static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
56
{
24
{
57
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
25
- /* EEW = 8 */
58
index XXXXXXX..XXXXXXX 100644
26
+ /* EEW = SEW */
59
--- a/hw/misc/Kconfig
27
uint32_t maxsz = simd_maxsz(desc);
60
+++ b/hw/misc/Kconfig
28
- uint32_t i = env->vstart;
61
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
29
+ uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
62
config SIFIVE_E_PRCI
30
+ uint32_t startb = env->vstart * sewb;
63
bool
31
+ uint32_t i = startb;
64
32
65
+config SIFIVE_U_PRCI
33
memcpy((uint8_t *)vd + H1(i),
66
+ bool
34
(uint8_t *)vs2 + H1(i),
67
+
35
- maxsz - env->vstart);
68
source macio/Kconfig
36
+ maxsz - startb);
69
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
37
70
index XXXXXXX..XXXXXXX 100644
38
env->vstart = 0;
71
--- a/hw/misc/meson.build
39
}
72
+++ b/hw/misc/meson.build
73
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
74
75
# RISC-V devices
76
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
77
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
78
79
# PKUnity SoC devices
80
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
81
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
82
index XXXXXXX..XXXXXXX 100644
83
--- a/hw/riscv/Kconfig
84
+++ b/hw/riscv/Kconfig
85
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
86
select HART
87
select SIFIVE
88
select SIFIVE_PDMA
89
+ select SIFIVE_U_PRCI
90
select UNIMP
91
92
config SPIKE
93
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
94
index XXXXXXX..XXXXXXX 100644
95
--- a/hw/riscv/meson.build
96
+++ b/hw/riscv/meson.build
97
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
98
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
99
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
100
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
101
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
102
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
103
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
104
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
105
--
40
--
106
2.28.0
41
2.35.1
107
108
diff view generated by jsdifflib
[PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller
[PULL v2 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
3
The riscv_raise_exception function stores its argument into
4
channels. This connects the exsiting SiFive PDMA model to the SoC,
4
exception_index and then exits to the main loop. When we
5
and adds its device tree data as well.
5
have already set exception_index, we can just exit directly.
6
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
9
Message-Id: <20220401125948.79292-2-richard.henderson@linaro.org>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
11
---
12
include/hw/riscv/sifive_u.h | 11 +++++++++++
12
target/riscv/cpu_helper.c | 6 +++---
13
hw/riscv/sifive_u.c | 30 ++++++++++++++++++++++++++++++
13
1 file changed, 3 insertions(+), 3 deletions(-)
14
hw/riscv/Kconfig | 1 +
15
3 files changed, 42 insertions(+)
16
14
17
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
15
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/sifive_u.h
17
--- a/target/riscv/cpu_helper.c
20
+++ b/include/hw/riscv/sifive_u.h
18
+++ b/target/riscv/cpu_helper.c
21
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
22
#ifndef HW_SIFIVE_U_H
20
env->badaddr = addr;
23
#define HW_SIFIVE_U_H
21
env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
24
22
riscv_cpu_two_stage_lookup(mmu_idx);
25
+#include "hw/dma/sifive_pdma.h"
23
- riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
26
#include "hw/net/cadence_gem.h"
24
+ cpu_loop_exit_restore(cs, retaddr);
27
#include "hw/riscv/riscv_hart.h"
28
#include "hw/riscv/sifive_cpu.h"
29
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUSoCState {
30
SiFiveUPRCIState prci;
31
SIFIVEGPIOState gpio;
32
SiFiveUOTPState otp;
33
+ SiFivePDMAState dma;
34
CadenceGEMState gem;
35
36
uint32_t serial;
37
@@ -XXX,XX +XXX,XX @@ enum {
38
SIFIVE_U_MROM,
39
SIFIVE_U_CLINT,
40
SIFIVE_U_L2CC,
41
+ SIFIVE_U_PDMA,
42
SIFIVE_U_L2LIM,
43
SIFIVE_U_PLIC,
44
SIFIVE_U_PRCI,
45
@@ -XXX,XX +XXX,XX @@ enum {
46
SIFIVE_U_GPIO_IRQ13 = 20,
47
SIFIVE_U_GPIO_IRQ14 = 21,
48
SIFIVE_U_GPIO_IRQ15 = 22,
49
+ SIFIVE_U_PDMA_IRQ0 = 23,
50
+ SIFIVE_U_PDMA_IRQ1 = 24,
51
+ SIFIVE_U_PDMA_IRQ2 = 25,
52
+ SIFIVE_U_PDMA_IRQ3 = 26,
53
+ SIFIVE_U_PDMA_IRQ4 = 27,
54
+ SIFIVE_U_PDMA_IRQ5 = 28,
55
+ SIFIVE_U_PDMA_IRQ6 = 29,
56
+ SIFIVE_U_PDMA_IRQ7 = 30,
57
SIFIVE_U_GEM_IRQ = 0x35
58
};
59
60
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/riscv/sifive_u.c
63
+++ b/hw/riscv/sifive_u.c
64
@@ -XXX,XX +XXX,XX @@
65
* 4) GPIO (General Purpose Input/Output Controller)
66
* 5) OTP (One-Time Programmable) memory with stored serial number
67
* 6) GEM (Gigabit Ethernet Controller) and management block
68
+ * 7) DMA (Direct Memory Access Controller)
69
*
70
* This board currently generates devicetree dynamically that indicates at least
71
* two harts and up to five harts.
72
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
73
[SIFIVE_U_MROM] = { 0x1000, 0xf000 },
74
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
75
[SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
76
+ [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
77
[SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
78
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
79
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
80
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
81
qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
82
g_free(nodename);
83
84
+ nodename = g_strdup_printf("/soc/dma@%lx",
85
+ (long)memmap[SIFIVE_U_PDMA].base);
86
+ qemu_fdt_add_subnode(fdt, nodename);
87
+ qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
88
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
89
+ SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
90
+ SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
91
+ SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
92
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
93
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
94
+ 0x0, memmap[SIFIVE_U_PDMA].base,
95
+ 0x0, memmap[SIFIVE_U_PDMA].size);
96
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
97
+ "sifive,fu540-c000-pdma");
98
+ g_free(nodename);
99
+
100
nodename = g_strdup_printf("/soc/cache-controller@%lx",
101
(long)memmap[SIFIVE_U_L2CC].base);
102
qemu_fdt_add_subnode(fdt, nodename);
103
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
104
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
105
object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
106
object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
107
+ object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
108
}
25
}
109
26
110
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
27
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
111
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
28
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
112
SIFIVE_U_GPIO_IRQ0 + i));
29
env->badaddr = addr;
30
env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
31
riscv_cpu_two_stage_lookup(mmu_idx);
32
- riscv_raise_exception(env, cs->exception_index, retaddr);
33
+ cpu_loop_exit_restore(cs, retaddr);
34
}
35
36
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
37
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
38
first_stage_error,
39
riscv_cpu_virt_enabled(env) ||
40
riscv_cpu_two_stage_lookup(mmu_idx));
41
- riscv_raise_exception(env, cs->exception_index, retaddr);
42
+ cpu_loop_exit_restore(cs, retaddr);
113
}
43
}
114
44
115
+ /* PDMA */
45
return true;
116
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
117
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
118
+
119
+ /* Connect PDMA interrupts to the PLIC */
120
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
121
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
122
+ qdev_get_gpio_in(DEVICE(s->plic),
123
+ SIFIVE_U_PDMA_IRQ0 + i));
124
+ }
125
+
126
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
127
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
128
return;
129
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
130
index XXXXXXX..XXXXXXX 100644
131
--- a/hw/riscv/Kconfig
132
+++ b/hw/riscv/Kconfig
133
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
134
select CADENCE
135
select HART
136
select SIFIVE
137
+ select SIFIVE_PDMA
138
select UNIMP
139
140
config SPIKE
141
--
46
--
142
2.28.0
47
2.35.1
143
144
diff view generated by jsdifflib
[PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc
[PULL v2 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
The -bios option is silently ignored if used in combination with -enable-kvm.
4
should only contain the RISC-V SoC / machine codes plus generic
4
The reason is that the machine starts in S-Mode, and the bios typically runs in
5
codes. Let's move sifive_plic model to hw/intc directory.
5
M-Mode.
6
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Better exit in that case to not confuse the user.
8
9
Signed-off-by: Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
11
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
12
Reviewed-by: Anup Patel <anup@brainfault.org>
13
Message-Id: <20220401121842.2791796-1-ralf.ramsauer@oth-regensburg.de>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
15
---
12
{include/hw/riscv => hw/intc}/sifive_plic.h | 0
16
hw/riscv/virt.c | 14 ++++++++++----
13
hw/{riscv => intc}/sifive_plic.c | 2 +-
17
1 file changed, 10 insertions(+), 4 deletions(-)
14
hw/riscv/microchip_pfsoc.c | 2 +-
15
hw/riscv/sifive_e.c | 2 +-
16
hw/riscv/sifive_u.c | 2 +-
17
hw/riscv/virt.c | 2 +-
18
hw/intc/Kconfig | 3 +++
19
hw/intc/meson.build | 1 +
20
hw/riscv/Kconfig | 5 +++++
21
hw/riscv/meson.build | 1 -
22
10 files changed, 14 insertions(+), 6 deletions(-)
23
rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
24
rename hw/{riscv => intc}/sifive_plic.c (99%)
25
18
26
diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
27
similarity index 100%
28
rename from include/hw/riscv/sifive_plic.h
29
rename to hw/intc/sifive_plic.h
30
diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
31
similarity index 99%
32
rename from hw/riscv/sifive_plic.c
33
rename to hw/intc/sifive_plic.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/riscv/sifive_plic.c
36
+++ b/hw/intc/sifive_plic.c
37
@@ -XXX,XX +XXX,XX @@
38
#include "hw/pci/msi.h"
39
#include "hw/boards.h"
40
#include "hw/qdev-properties.h"
41
+#include "hw/intc/sifive_plic.h"
42
#include "target/riscv/cpu.h"
43
#include "sysemu/sysemu.h"
44
-#include "hw/riscv/sifive_plic.h"
45
46
#define RISCV_DEBUG_PLIC 0
47
48
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/riscv/microchip_pfsoc.c
51
+++ b/hw/riscv/microchip_pfsoc.c
52
@@ -XXX,XX +XXX,XX @@
53
#include "hw/misc/unimp.h"
54
#include "hw/riscv/boot.h"
55
#include "hw/riscv/riscv_hart.h"
56
-#include "hw/riscv/sifive_plic.h"
57
#include "hw/riscv/microchip_pfsoc.h"
58
#include "hw/intc/sifive_clint.h"
59
+#include "hw/intc/sifive_plic.h"
60
#include "sysemu/sysemu.h"
61
62
/*
63
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/riscv/sifive_e.c
66
+++ b/hw/riscv/sifive_e.c
67
@@ -XXX,XX +XXX,XX @@
68
#include "hw/misc/unimp.h"
69
#include "target/riscv/cpu.h"
70
#include "hw/riscv/riscv_hart.h"
71
-#include "hw/riscv/sifive_plic.h"
72
#include "hw/riscv/sifive_uart.h"
73
#include "hw/riscv/sifive_e.h"
74
#include "hw/riscv/boot.h"
75
#include "hw/intc/sifive_clint.h"
76
+#include "hw/intc/sifive_plic.h"
77
#include "hw/misc/sifive_e_prci.h"
78
#include "chardev/char.h"
79
#include "sysemu/arch_init.h"
80
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/riscv/sifive_u.c
83
+++ b/hw/riscv/sifive_u.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "hw/misc/unimp.h"
86
#include "target/riscv/cpu.h"
87
#include "hw/riscv/riscv_hart.h"
88
-#include "hw/riscv/sifive_plic.h"
89
#include "hw/riscv/sifive_uart.h"
90
#include "hw/riscv/sifive_u.h"
91
#include "hw/riscv/boot.h"
92
#include "hw/intc/sifive_clint.h"
93
+#include "hw/intc/sifive_plic.h"
94
#include "chardev/char.h"
95
#include "net/eth.h"
96
#include "sysemu/arch_init.h"
97
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
19
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
98
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
99
--- a/hw/riscv/virt.c
21
--- a/hw/riscv/virt.c
100
+++ b/hw/riscv/virt.c
22
+++ b/hw/riscv/virt.c
101
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
102
#include "hw/char/serial.h"
24
103
#include "target/riscv/cpu.h"
25
/*
104
#include "hw/riscv/riscv_hart.h"
26
* Only direct boot kernel is currently supported for KVM VM,
105
-#include "hw/riscv/sifive_plic.h"
27
- * so the "-bios" parameter is ignored and treated like "-bios none"
106
#include "hw/riscv/sifive_test.h"
28
- * when KVM is enabled.
107
#include "hw/riscv/virt.h"
29
+ * so the "-bios" parameter is not supported when KVM is enabled.
108
#include "hw/riscv/boot.h"
30
*/
109
#include "hw/riscv/numa.h"
31
if (kvm_enabled()) {
110
#include "hw/intc/sifive_clint.h"
32
- g_free(machine->firmware);
111
+#include "hw/intc/sifive_plic.h"
33
- machine->firmware = g_strdup("none");
112
#include "chardev/char.h"
34
+ if (machine->firmware) {
113
#include "sysemu/arch_init.h"
35
+ if (strcmp(machine->firmware, "none")) {
114
#include "sysemu/device_tree.h"
36
+ error_report("Machine mode firmware is not supported in "
115
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
37
+ "combination with KVM.");
116
index XXXXXXX..XXXXXXX 100644
38
+ exit(1);
117
--- a/hw/intc/Kconfig
39
+ }
118
+++ b/hw/intc/Kconfig
40
+ } else {
119
@@ -XXX,XX +XXX,XX @@ config LOONGSON_LIOINTC
41
+ machine->firmware = g_strdup("none");
120
42
+ }
121
config SIFIVE_CLINT
43
}
122
bool
44
123
+
45
if (riscv_is_32bit(&s->soc[0])) {
124
+config SIFIVE_PLIC
125
+ bool
126
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/intc/meson.build
129
+++ b/hw/intc/meson.build
130
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
131
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
132
specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
133
specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
134
+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
135
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
136
specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
137
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
138
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
139
index XXXXXXX..XXXXXXX 100644
140
--- a/hw/riscv/Kconfig
141
+++ b/hw/riscv/Kconfig
142
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
143
select SIFIVE
144
select SIFIVE_CLINT
145
select SIFIVE_GPIO
146
+ select SIFIVE_PLIC
147
select SIFIVE_E_PRCI
148
select UNIMP
149
150
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
151
select SIFIVE_CLINT
152
select SIFIVE_GPIO
153
select SIFIVE_PDMA
154
+ select SIFIVE_PLIC
155
select SIFIVE_U_OTP
156
select SIFIVE_U_PRCI
157
select UNIMP
158
@@ -XXX,XX +XXX,XX @@ config SPIKE
159
select HTIF
160
select SIFIVE
161
select SIFIVE_CLINT
162
+ select SIFIVE_PLIC
163
164
config OPENTITAN
165
bool
166
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
167
select PFLASH_CFI01
168
select SIFIVE
169
select SIFIVE_CLINT
170
+ select SIFIVE_PLIC
171
172
config MICROCHIP_PFSOC
173
bool
174
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
175
select UNIMP
176
select MCHP_PFSOC_MMUART
177
select SIFIVE_PDMA
178
+ select SIFIVE_PLIC
179
select CADENCE_SDHCI
180
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
181
index XXXXXXX..XXXXXXX 100644
182
--- a/hw/riscv/meson.build
183
+++ b/hw/riscv/meson.build
184
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
185
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
186
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
187
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
188
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
189
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
190
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
191
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
192
--
46
--
193
2.28.0
47
2.35.1
194
195
diff view generated by jsdifflib
[PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc
[PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Nicolas Pitre <nico@fluxnic.net>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
There is an overflow with the current code where a pmpaddr value of
4
should only contain the RISC-V SoC / machine codes plus generic
4
0x1fffffff is decoded as sa=0 and ea=0 whereas it should be sa=0 and
5
codes. Let's move sifive_e_prci model to hw/misc directory.
5
ea=0xffffffff.
6
6
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Fix that by simplifying the computation. There is in fact no need for
8
ctz64() nor special case for -1 to achieve proper results.
9
10
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
12
Message-Id: <rq81o86n-17ps-92no-p65o-79o88476266@syhkavp.arg>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
14
---
12
include/hw/{riscv => misc}/sifive_e_prci.h | 0
15
target/riscv/pmp.c | 14 +++-----------
13
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
16
1 file changed, 3 insertions(+), 11 deletions(-)
14
hw/riscv/sifive_e.c | 2 +-
15
hw/misc/Kconfig | 3 +++
16
hw/misc/meson.build | 3 +++
17
hw/riscv/Kconfig | 1 +
18
hw/riscv/meson.build | 1 -
19
7 files changed, 9 insertions(+), 3 deletions(-)
20
rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
21
rename hw/{riscv => misc}/sifive_e_prci.c (99%)
22
17
23
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
18
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
24
similarity index 100%
25
rename from include/hw/riscv/sifive_e_prci.h
26
rename to include/hw/misc/sifive_e_prci.h
27
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
28
similarity index 99%
29
rename from hw/riscv/sifive_e_prci.c
30
rename to hw/misc/sifive_e_prci.c
31
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/sifive_e_prci.c
20
--- a/target/riscv/pmp.c
33
+++ b/hw/misc/sifive_e_prci.c
21
+++ b/target/riscv/pmp.c
34
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea)
35
#include "qemu/log.h"
23
0111...1111 2^(XLEN+2)-byte NAPOT range
36
#include "qemu/module.h"
24
1111...1111 Reserved
37
#include "hw/hw.h"
25
*/
38
-#include "hw/riscv/sifive_e_prci.h"
26
- if (a == -1) {
39
+#include "hw/misc/sifive_e_prci.h"
27
- *sa = 0u;
40
28
- *ea = -1;
41
static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
29
- return;
42
{
30
- } else {
43
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
31
- target_ulong t1 = ctz64(~a);
44
index XXXXXXX..XXXXXXX 100644
32
- target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2;
45
--- a/hw/riscv/sifive_e.c
33
- target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1;
46
+++ b/hw/riscv/sifive_e.c
34
- *sa = base;
47
@@ -XXX,XX +XXX,XX @@
35
- *ea = base + range;
48
#include "hw/riscv/sifive_clint.h"
36
- }
49
#include "hw/riscv/sifive_uart.h"
37
+ a = (a << 2) | 0x3;
50
#include "hw/riscv/sifive_e.h"
38
+ *sa = a & (a + 1);
51
-#include "hw/riscv/sifive_e_prci.h"
39
+ *ea = a | (a + 1);
52
#include "hw/riscv/boot.h"
40
}
53
+#include "hw/misc/sifive_e_prci.h"
41
54
#include "chardev/char.h"
42
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
55
#include "sysemu/arch_init.h"
56
#include "sysemu/sysemu.h"
57
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/misc/Kconfig
60
+++ b/hw/misc/Kconfig
61
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
62
config AVR_POWER
63
bool
64
65
+config SIFIVE_E_PRCI
66
+ bool
67
+
68
source macio/Kconfig
69
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/misc/meson.build
72
+++ b/hw/misc/meson.build
73
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
74
# Mac devices
75
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
76
77
+# RISC-V devices
78
+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
79
+
80
# PKUnity SoC devices
81
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
82
83
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/riscv/Kconfig
86
+++ b/hw/riscv/Kconfig
87
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
88
bool
89
select HART
90
select SIFIVE
91
+ select SIFIVE_E_PRCI
92
select UNIMP
93
94
config SIFIVE_U
95
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/riscv/meson.build
98
+++ b/hw/riscv/meson.build
99
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
100
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
101
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
102
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
103
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
104
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
105
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
106
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
107
--
43
--
108
2.28.0
44
2.35.1
109
110
diff view generated by jsdifflib
[PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc
[PULL v2 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Niklas Cassel <niklas.cassel@wdc.com>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
The device tree property "mmu-type" is currently exported as either
4
should only contain the RISC-V SoC / machine codes plus generic
4
"riscv,sv32" or "riscv,sv48".
5
codes. Let's move sifive_clint model to hw/intc directory.
6
5
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
However, the riscv cpu device tree binding [1] has a specific value
7
"riscv,none" for a HART without a MMU.
8
9
Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu
10
option is disabled using rv32,mmu=off or rv64,mmu=off.
11
12
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/cpus.yaml?h=v5.17
13
14
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
15
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
16
Reviewed-by: Frank Chang <frank.chang@sifive.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
18
Message-Id: <20220414155510.1364147-1-niklas.cassel@wdc.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
20
---
12
include/hw/{riscv => intc}/sifive_clint.h | 0
21
hw/riscv/virt.c | 10 ++++++++--
13
hw/{riscv => intc}/sifive_clint.c | 2 +-
22
1 file changed, 8 insertions(+), 2 deletions(-)
14
hw/riscv/microchip_pfsoc.c | 2 +-
15
hw/riscv/sifive_e.c | 2 +-
16
hw/riscv/sifive_u.c | 2 +-
17
hw/riscv/spike.c | 2 +-
18
hw/riscv/virt.c | 2 +-
19
hw/intc/Kconfig | 3 +++
20
hw/intc/meson.build | 1 +
21
hw/riscv/Kconfig | 5 +++++
22
hw/riscv/meson.build | 1 -
23
11 files changed, 15 insertions(+), 7 deletions(-)
24
rename include/hw/{riscv => intc}/sifive_clint.h (100%)
25
rename hw/{riscv => intc}/sifive_clint.c (99%)
26
23
27
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
28
similarity index 100%
29
rename from include/hw/riscv/sifive_clint.h
30
rename to include/hw/intc/sifive_clint.h
31
diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
32
similarity index 99%
33
rename from hw/riscv/sifive_clint.c
34
rename to hw/intc/sifive_clint.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/riscv/sifive_clint.c
37
+++ b/hw/intc/sifive_clint.c
38
@@ -XXX,XX +XXX,XX @@
39
#include "hw/sysbus.h"
40
#include "target/riscv/cpu.h"
41
#include "hw/qdev-properties.h"
42
-#include "hw/riscv/sifive_clint.h"
43
+#include "hw/intc/sifive_clint.h"
44
#include "qemu/timer.h"
45
46
static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
47
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/riscv/microchip_pfsoc.c
50
+++ b/hw/riscv/microchip_pfsoc.c
51
@@ -XXX,XX +XXX,XX @@
52
#include "hw/misc/unimp.h"
53
#include "hw/riscv/boot.h"
54
#include "hw/riscv/riscv_hart.h"
55
-#include "hw/riscv/sifive_clint.h"
56
#include "hw/riscv/sifive_plic.h"
57
#include "hw/riscv/microchip_pfsoc.h"
58
+#include "hw/intc/sifive_clint.h"
59
#include "sysemu/sysemu.h"
60
61
/*
62
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/hw/riscv/sifive_e.c
65
+++ b/hw/riscv/sifive_e.c
66
@@ -XXX,XX +XXX,XX @@
67
#include "target/riscv/cpu.h"
68
#include "hw/riscv/riscv_hart.h"
69
#include "hw/riscv/sifive_plic.h"
70
-#include "hw/riscv/sifive_clint.h"
71
#include "hw/riscv/sifive_uart.h"
72
#include "hw/riscv/sifive_e.h"
73
#include "hw/riscv/boot.h"
74
+#include "hw/intc/sifive_clint.h"
75
#include "hw/misc/sifive_e_prci.h"
76
#include "chardev/char.h"
77
#include "sysemu/arch_init.h"
78
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/riscv/sifive_u.c
81
+++ b/hw/riscv/sifive_u.c
82
@@ -XXX,XX +XXX,XX @@
83
#include "target/riscv/cpu.h"
84
#include "hw/riscv/riscv_hart.h"
85
#include "hw/riscv/sifive_plic.h"
86
-#include "hw/riscv/sifive_clint.h"
87
#include "hw/riscv/sifive_uart.h"
88
#include "hw/riscv/sifive_u.h"
89
#include "hw/riscv/boot.h"
90
+#include "hw/intc/sifive_clint.h"
91
#include "chardev/char.h"
92
#include "net/eth.h"
93
#include "sysemu/arch_init.h"
94
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/hw/riscv/spike.c
97
+++ b/hw/riscv/spike.c
98
@@ -XXX,XX +XXX,XX @@
99
#include "target/riscv/cpu.h"
100
#include "hw/riscv/riscv_htif.h"
101
#include "hw/riscv/riscv_hart.h"
102
-#include "hw/riscv/sifive_clint.h"
103
#include "hw/riscv/spike.h"
104
#include "hw/riscv/boot.h"
105
#include "hw/riscv/numa.h"
106
+#include "hw/intc/sifive_clint.h"
107
#include "chardev/char.h"
108
#include "sysemu/arch_init.h"
109
#include "sysemu/device_tree.h"
110
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
24
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
111
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
112
--- a/hw/riscv/virt.c
26
--- a/hw/riscv/virt.c
113
+++ b/hw/riscv/virt.c
27
+++ b/hw/riscv/virt.c
114
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
115
#include "target/riscv/cpu.h"
29
cpu_name = g_strdup_printf("/cpus/cpu@%d",
116
#include "hw/riscv/riscv_hart.h"
30
s->soc[socket].hartid_base + cpu);
117
#include "hw/riscv/sifive_plic.h"
31
qemu_fdt_add_subnode(mc->fdt, cpu_name);
118
-#include "hw/riscv/sifive_clint.h"
32
- qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
119
#include "hw/riscv/sifive_test.h"
33
- (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
120
#include "hw/riscv/virt.h"
34
+ if (riscv_feature(&s->soc[socket].harts[cpu].env,
121
#include "hw/riscv/boot.h"
35
+ RISCV_FEATURE_MMU)) {
122
#include "hw/riscv/numa.h"
36
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
123
+#include "hw/intc/sifive_clint.h"
37
+ (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
124
#include "chardev/char.h"
38
+ } else {
125
#include "sysemu/arch_init.h"
39
+ qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
126
#include "sysemu/device_tree.h"
40
+ "riscv,none");
127
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
41
+ }
128
index XXXXXXX..XXXXXXX 100644
42
name = riscv_isa_string(&s->soc[socket].harts[cpu]);
129
--- a/hw/intc/Kconfig
43
qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
130
+++ b/hw/intc/Kconfig
44
g_free(name);
131
@@ -XXX,XX +XXX,XX @@ config RX_ICU
132
133
config LOONGSON_LIOINTC
134
bool
135
+
136
+config SIFIVE_CLINT
137
+ bool
138
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
139
index XXXXXXX..XXXXXXX 100644
140
--- a/hw/intc/meson.build
141
+++ b/hw/intc/meson.build
142
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
143
specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
144
specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
145
specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
146
+specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
147
specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
148
specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
149
specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
150
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
151
index XXXXXXX..XXXXXXX 100644
152
--- a/hw/riscv/Kconfig
153
+++ b/hw/riscv/Kconfig
154
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
155
bool
156
select HART
157
select SIFIVE
158
+ select SIFIVE_CLINT
159
select SIFIVE_GPIO
160
select SIFIVE_E_PRCI
161
select UNIMP
162
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
163
select CADENCE
164
select HART
165
select SIFIVE
166
+ select SIFIVE_CLINT
167
select SIFIVE_GPIO
168
select SIFIVE_PDMA
169
select SIFIVE_U_OTP
170
@@ -XXX,XX +XXX,XX @@ config SPIKE
171
select HART
172
select HTIF
173
select SIFIVE
174
+ select SIFIVE_CLINT
175
176
config OPENTITAN
177
bool
178
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
179
select PCI_EXPRESS_GENERIC_BRIDGE
180
select PFLASH_CFI01
181
select SIFIVE
182
+ select SIFIVE_CLINT
183
184
config MICROCHIP_PFSOC
185
bool
186
select HART
187
select SIFIVE
188
+ select SIFIVE_CLINT
189
select UNIMP
190
select MCHP_PFSOC_MMUART
191
select SIFIVE_PDMA
192
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
193
index XXXXXXX..XXXXXXX 100644
194
--- a/hw/riscv/meson.build
195
+++ b/hw/riscv/meson.build
196
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
197
riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
198
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
199
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
200
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
201
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
202
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
203
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
204
--
45
--
205
2.28.0
46
2.35.1
206
207
diff view generated by jsdifflib
[PULL 04/30] hw/riscv: hart: Add a new 'resetvec' property
[PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Frank Chang <frank.chang@sifive.com>
2
2
3
RISC-V machines do not instantiate RISC-V CPUs directly, instead
3
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
4
they do that via the hart array. Add a new property for the reset
4
declaration, the default access_size_min would be 1 byte and
5
vector address to allow the value to be passed to the CPU, before
5
access_size_max would be 4 bytes (see: softmmu/memory.c).
6
CPU is realized.
6
This will cause a 64-bit memory access to ACLINT to be splitted into
7
two 32-bit memory accesses.
7
8
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Signed-off-by: Frank Chang <frank.chang@sifive.com>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Jim Shu <jim.shu@sifive.com>
11
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
12
Message-Id: <20220420080901.14655-2-frank.chang@sifive.com>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
---
14
include/hw/riscv/riscv_hart.h | 1 +
15
hw/intc/riscv_aclint.c | 4 ++++
15
hw/riscv/riscv_hart.c | 3 +++
16
1 file changed, 4 insertions(+)
16
2 files changed, 4 insertions(+)
17
17
18
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
18
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
19
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/riscv/riscv_hart.h
20
--- a/hw/intc/riscv_aclint.c
21
+++ b/include/hw/riscv/riscv_hart.h
21
+++ b/hw/intc/riscv_aclint.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVHartArrayState {
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps riscv_aclint_mtimer_ops = {
23
uint32_t num_harts;
23
.valid = {
24
uint32_t hartid_base;
24
.min_access_size = 4,
25
char *cpu_type;
25
.max_access_size = 8
26
+ uint64_t resetvec;
26
+ },
27
RISCVCPU *harts;
27
+ .impl = {
28
} RISCVHartArrayState;
28
+ .min_access_size = 4,
29
29
+ .max_access_size = 8,
30
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
30
}
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/riscv_hart.c
33
+++ b/hw/riscv/riscv_hart.c
34
@@ -XXX,XX +XXX,XX @@ static Property riscv_harts_props[] = {
35
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
36
DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
37
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
38
+ DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
39
+ DEFAULT_RSTVEC),
40
DEFINE_PROP_END_OF_LIST(),
41
};
31
};
42
32
43
@@ -XXX,XX +XXX,XX @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
44
char *cpu_type, Error **errp)
45
{
46
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
47
+ qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
48
s->harts[idx].env.mhartid = s->hartid_base + idx;
49
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
50
return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
51
--
33
--
52
2.28.0
34
2.35.1
53
54
diff view generated by jsdifflib
[PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
[PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Frank Chang <frank.chang@sifive.com>
2
2
3
When cadence_gem model was created for Xilinx boards, the PHY address
3
RISC-V privilege spec defines that:
4
was hard-coded to 23 in the GEM model. Now that we have introduced a
5
property we can use that to tell GEM model what our PHY address is.
6
Change all boards' GEM 'phy-addr' property value to 23, and set the
7
PHY address default value to 0 in the GEM model.
8
4
9
Signed-off-by: Bin Meng <bin.meng@windriver.com>
5
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
of the register.
7
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
8
mtimecmp registers are additionally supported and are atomic.
9
10
It's possible to perform both 32/64-bit read/write accesses to both
11
mtimecmp and mtime registers.
12
13
Signed-off-by: Frank Chang <frank.chang@sifive.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
15
Reviewed-by: Jim Shu <jim.shu@sifive.com>
16
Message-Id: <20220420080901.14655-3-frank.chang@sifive.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
18
---
15
hw/arm/xilinx_zynq.c | 1 +
19
hw/intc/riscv_aclint.c | 42 +++++++++++++++++++++++++++---------------
16
hw/arm/xlnx-versal.c | 1 +
20
1 file changed, 27 insertions(+), 15 deletions(-)
17
hw/arm/xlnx-zynqmp.c | 2 ++
18
hw/net/cadence_gem.c | 6 +++---
19
4 files changed, 7 insertions(+), 3 deletions(-)
20
21
21
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
22
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
22
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/xilinx_zynq.c
24
--- a/hw/intc/riscv_aclint.c
24
+++ b/hw/arm/xilinx_zynq.c
25
+++ b/hw/intc/riscv_aclint.c
25
@@ -XXX,XX +XXX,XX @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
26
@@ -XXX,XX +XXX,XX @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
26
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
27
qemu_log_mask(LOG_GUEST_ERROR,
27
qdev_set_nic_properties(dev, nd);
28
"aclint-mtimer: invalid hartid: %zu", hartid);
28
}
29
} else if ((addr & 0x7) == 0) {
29
+ object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
30
- /* timecmp_lo */
30
s = SYS_BUS_DEVICE(dev);
31
+ /* timecmp_lo for RV32/RV64 or timecmp for RV64 */
31
sysbus_realize_and_unref(s, &error_fatal);
32
uint64_t timecmp = env->timecmp;
32
sysbus_mmio_map(s, 0, base);
33
- return timecmp & 0xFFFFFFFF;
33
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
34
+ return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp;
34
index XXXXXXX..XXXXXXX 100644
35
} else if ((addr & 0x7) == 4) {
35
--- a/hw/arm/xlnx-versal.c
36
/* timecmp_hi */
36
+++ b/hw/arm/xlnx-versal.c
37
uint64_t timecmp = env->timecmp;
37
@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
38
@@ -XXX,XX +XXX,XX @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
38
qemu_check_nic_model(nd, "cadence_gem");
39
return 0;
39
qdev_set_nic_properties(dev, nd);
40
}
40
}
41
+ object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
41
} else if (addr == mtimer->time_base) {
42
object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
42
- /* time_lo */
43
&error_abort);
43
- return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0xFFFFFFFF;
44
object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
44
+ /* time_lo for RV32/RV64 or timecmp for RV64 */
45
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
45
+ uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq);
46
index XXXXXXX..XXXXXXX 100644
46
+ return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc;
47
--- a/hw/arm/xlnx-zynqmp.c
47
} else if (addr == mtimer->time_base + 4) {
48
+++ b/hw/arm/xlnx-zynqmp.c
48
/* time_hi */
49
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
49
return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF;
50
}
50
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
51
object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
51
qemu_log_mask(LOG_GUEST_ERROR,
52
&error_abort);
52
"aclint-mtimer: invalid hartid: %zu", hartid);
53
+ object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
53
} else if ((addr & 0x7) == 0) {
54
+ &error_abort);
54
- /* timecmp_lo */
55
object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
55
- uint64_t timecmp_hi = env->timecmp >> 32;
56
&error_abort);
56
- riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
57
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
57
- timecmp_hi << 32 | (value & 0xFFFFFFFF),
58
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
58
- mtimer->timebase_freq);
59
index XXXXXXX..XXXXXXX 100644
59
- return;
60
--- a/hw/net/cadence_gem.c
60
+ if (size == 4) {
61
+++ b/hw/net/cadence_gem.c
61
+ /* timecmp_lo for RV32/RV64 */
62
@@ -XXX,XX +XXX,XX @@
62
+ uint64_t timecmp_hi = env->timecmp >> 32;
63
#define GEM_PHYMNTNC_REG_SHIFT 18
63
+ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
64
64
+ timecmp_hi << 32 | (value & 0xFFFFFFFF),
65
/* Marvell PHY definitions */
65
+ mtimer->timebase_freq);
66
-#define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
66
+ } else {
67
+#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */
67
+ /* timecmp for RV64 */
68
68
+ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
69
#define PHY_REG_CONTROL 0
69
+ value, mtimer->timebase_freq);
70
#define PHY_REG_STATUS 1
70
+ }
71
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
71
} else if ((addr & 0x7) == 4) {
72
uint32_t phy_addr, reg_num;
72
- /* timecmp_hi */
73
73
- uint64_t timecmp_lo = env->timecmp;
74
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
74
- riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
75
- if (phy_addr == s->phy_addr || phy_addr == 0) {
75
- value << 32 | (timecmp_lo & 0xFFFFFFFF),
76
+ if (phy_addr == s->phy_addr) {
76
- mtimer->timebase_freq);
77
reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
77
+ if (size == 4) {
78
retval &= 0xFFFF0000;
78
+ /* timecmp_hi for RV32/RV64 */
79
retval |= gem_phy_read(s, reg_num);
79
+ uint64_t timecmp_lo = env->timecmp;
80
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
80
+ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
81
uint32_t phy_addr, reg_num;
81
+ value << 32 | (timecmp_lo & 0xFFFFFFFF),
82
82
+ mtimer->timebase_freq);
83
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
83
+ } else {
84
- if (phy_addr == s->phy_addr || phy_addr == 0) {
84
+ qemu_log_mask(LOG_GUEST_ERROR,
85
+ if (phy_addr == s->phy_addr) {
85
+ "aclint-mtimer: invalid timecmp_hi write: %08x",
86
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
86
+ (uint32_t)addr);
87
gem_phy_write(s, reg_num, val);
87
+ }
88
}
88
} else {
89
qemu_log_mask(LOG_UNIMP,
90
"aclint-mtimer: invalid timecmp write: %08x",
89
--
91
--
90
2.28.0
92
2.35.1
91
92
diff view generated by jsdifflib
[PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency
[PULL v2 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Frank Chang <frank.chang@sifive.com>
2
2
3
At present the CLINT timestamp is using a hard-coded timebase
3
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
4
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
4
machine-mode read-write register. However, as QEMU uses host monotonic
5
true for all boards.
5
timer as timer source, this makes mtime to be read-only in RISC-V
6
6
ACLINT.
7
Add a new 'timebase-freq' property to the CLINT device, and
7
8
update various functions to accept this as a parameter.
8
This patch makes mtime to be writable by recording the time delta value
9
9
between the mtime value to be written and the timer value at the time
10
Signed-off-by: Bin Meng <bin.meng@windriver.com>
10
mtime is written. Time delta value is then added back whenever the timer
11
value is retrieved.
12
13
Signed-off-by: Frank Chang <frank.chang@sifive.com>
14
Reviewed-by: Jim Shu <jim.shu@sifive.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com>
16
Message-Id: <20220420080901.14655-4-frank.chang@sifive.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
18
---
15
include/hw/riscv/sifive_clint.h | 4 +++-
19
include/hw/intc/riscv_aclint.h | 1 +
16
target/riscv/cpu.h | 6 ++++--
20
target/riscv/cpu.h | 8 ++--
17
hw/riscv/microchip_pfsoc.c | 6 +++++-
21
hw/intc/riscv_aclint.c | 71 ++++++++++++++++++++++++----------
18
hw/riscv/sifive_clint.c | 26 +++++++++++++++-----------
22
target/riscv/cpu_helper.c | 4 +-
19
hw/riscv/sifive_e.c | 3 ++-
23
4 files changed, 57 insertions(+), 27 deletions(-)
20
hw/riscv/sifive_u.c | 3 ++-
24
21
hw/riscv/spike.c | 3 ++-
25
diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h
22
hw/riscv/virt.c | 3 ++-
26
index XXXXXXX..XXXXXXX 100644
23
target/riscv/cpu_helper.c | 4 +++-
27
--- a/include/hw/intc/riscv_aclint.h
24
target/riscv/csr.c | 4 ++--
28
+++ b/include/hw/intc/riscv_aclint.h
25
10 files changed, 40 insertions(+), 22 deletions(-)
29
@@ -XXX,XX +XXX,XX @@
26
30
typedef struct RISCVAclintMTimerState {
27
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
31
/*< private >*/
28
index XXXXXXX..XXXXXXX 100644
32
SysBusDevice parent_obj;
29
--- a/include/hw/riscv/sifive_clint.h
33
+ uint64_t time_delta;
30
+++ b/include/hw/riscv/sifive_clint.h
34
31
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
35
/*< public >*/
32
uint32_t timecmp_base;
36
MemoryRegion mmio;
33
uint32_t time_base;
34
uint32_t aperture_size;
35
+ uint32_t timebase_freq;
36
} SiFiveCLINTState;
37
38
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
39
uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
40
- uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
41
+ uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
42
+ bool provide_rdtime);
43
44
enum {
45
SIFIVE_SIP_BASE = 0x0,
46
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
37
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
47
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
48
--- a/target/riscv/cpu.h
39
--- a/target/riscv/cpu.h
49
+++ b/target/riscv/cpu.h
40
+++ b/target/riscv/cpu.h
50
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
41
@@ -XXX,XX +XXX,XX @@ struct CPUArchState {
51
pmp_table_t pmp_state;
42
type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM];
52
43
53
/* machine specific rdtime callback */
44
/* machine specific rdtime callback */
54
- uint64_t (*rdtime_fn)(void);
45
- uint64_t (*rdtime_fn)(uint32_t);
55
+ uint64_t (*rdtime_fn)(uint32_t);
46
- uint32_t rdtime_fn_arg;
56
+ uint32_t rdtime_fn_arg;
47
+ uint64_t (*rdtime_fn)(void *);
57
48
+ void *rdtime_fn_arg;
58
/* True if in debugger mode. */
49
59
bool debugger;
50
/* machine specific AIA ireg read-modify-write callback */
51
#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
60
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
52
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
61
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
53
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
62
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
54
uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
63
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
55
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
64
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
56
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
65
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
57
- uint32_t arg);
66
+ uint32_t arg);
58
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
67
#endif
59
+ void *arg);
68
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
60
void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
69
61
int (*rmw_fn)(void *arg,
70
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
62
target_ulong reg,
71
index XXXXXXX..XXXXXXX 100644
63
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
72
--- a/hw/riscv/microchip_pfsoc.c
64
index XXXXXXX..XXXXXXX 100644
73
+++ b/hw/riscv/microchip_pfsoc.c
65
--- a/hw/intc/riscv_aclint.c
74
@@ -XXX,XX +XXX,XX @@
66
+++ b/hw/intc/riscv_aclint.c
75
#define BIOS_FILENAME "hss.bin"
67
@@ -XXX,XX +XXX,XX @@ typedef struct riscv_aclint_mtimer_callback {
76
#define RESET_VECTOR 0x20220000
68
int num;
77
69
} riscv_aclint_mtimer_callback;
78
+/* CLINT timebase frequency */
70
79
+#define CLINT_TIMEBASE_FREQ 1000000
71
-static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
72
+static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq)
73
{
74
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
75
timebase_freq, NANOSECONDS_PER_SECOND);
76
}
77
78
+static uint64_t cpu_riscv_read_rtc(void *opaque)
79
+{
80
+ RISCVAclintMTimerState *mtimer = opaque;
81
+ return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta;
82
+}
80
+
83
+
81
/* GEM version */
82
#define GEM_REVISION 0x0107010c
83
84
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
85
/* CLINT */
86
sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
87
memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
88
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
89
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
90
+ CLINT_TIMEBASE_FREQ, false);
91
92
/* L2 cache controller */
93
create_unimplemented_device("microchip.pfsoc.l2cc",
94
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/hw/riscv/sifive_clint.c
97
+++ b/hw/riscv/sifive_clint.c
98
@@ -XXX,XX +XXX,XX @@
99
#include "hw/riscv/sifive_clint.h"
100
#include "qemu/timer.h"
101
102
-static uint64_t cpu_riscv_read_rtc(void)
103
+static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
104
{
105
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
106
- SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
107
+ timebase_freq, NANOSECONDS_PER_SECOND);
108
}
109
110
/*
84
/*
111
* Called when timecmp is written to update the QEMU timer or immediately
85
* Called when timecmp is written to update the QEMU timer or immediately
112
* trigger timer interrupt if mtimecmp <= current timer value.
86
* trigger timer interrupt if mtimecmp <= current timer value.
113
*/
87
@@ -XXX,XX +XXX,XX @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
114
-static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
88
static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
115
+static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
89
RISCVCPU *cpu,
116
+ uint32_t timebase_freq)
90
int hartid,
117
{
91
- uint64_t value,
92
- uint32_t timebase_freq)
93
+ uint64_t value)
94
{
95
+ uint32_t timebase_freq = mtimer->timebase_freq;
118
uint64_t next;
96
uint64_t next;
119
uint64_t diff;
97
uint64_t diff;
120
98
121
- uint64_t rtc_r = cpu_riscv_read_rtc();
99
- uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
122
+ uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
100
+ uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);
123
101
124
cpu->env.timecmp = value;
102
cpu->env.timecmp = value;
125
if (cpu->env.timecmp <= rtc_r) {
103
if (cpu->env.timecmp <= rtc_r) {
126
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
104
@@ -XXX,XX +XXX,XX @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
127
diff = cpu->env.timecmp - rtc_r;
105
}
128
/* back to ns (note args switched in muldiv64) */
106
} else if (addr == mtimer->time_base) {
129
next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
107
/* time_lo for RV32/RV64 or timecmp for RV64 */
130
- muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
108
- uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq);
131
+ muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
109
+ uint64_t rtc = cpu_riscv_read_rtc(mtimer);
132
timer_mod(cpu->env.timer, next);
110
return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc;
133
}
111
} else if (addr == mtimer->time_base + 4) {
134
135
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
136
}
137
} else if (addr == clint->time_base) {
138
/* time_lo */
139
- return cpu_riscv_read_rtc() & 0xFFFFFFFF;
140
+ return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF;
141
} else if (addr == clint->time_base + 4) {
142
/* time_hi */
112
/* time_hi */
143
- return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
113
- return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF;
144
+ return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF;
114
+ return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF;
145
}
115
}
146
116
147
error_report("clint: invalid read: %08x", (uint32_t)addr);
117
qemu_log_mask(LOG_UNIMP,
148
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
118
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
149
/* timecmp_lo */
119
uint64_t value, unsigned size)
150
uint64_t timecmp_hi = env->timecmp >> 32;
120
{
151
sifive_clint_write_timecmp(RISCV_CPU(cpu),
121
RISCVAclintMTimerState *mtimer = opaque;
152
- timecmp_hi << 32 | (value & 0xFFFFFFFF));
122
+ int i;
153
+ timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq);
123
154
return;
124
if (addr >= mtimer->timecmp_base &&
125
addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
126
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
127
/* timecmp_lo for RV32/RV64 */
128
uint64_t timecmp_hi = env->timecmp >> 32;
129
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
130
- timecmp_hi << 32 | (value & 0xFFFFFFFF),
131
- mtimer->timebase_freq);
132
+ timecmp_hi << 32 | (value & 0xFFFFFFFF));
133
} else {
134
/* timecmp for RV64 */
135
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
136
- value, mtimer->timebase_freq);
137
+ value);
138
}
155
} else if ((addr & 0x7) == 4) {
139
} else if ((addr & 0x7) == 4) {
156
/* timecmp_hi */
140
if (size == 4) {
157
uint64_t timecmp_lo = env->timecmp;
141
/* timecmp_hi for RV32/RV64 */
158
sifive_clint_write_timecmp(RISCV_CPU(cpu),
142
uint64_t timecmp_lo = env->timecmp;
159
- value << 32 | (timecmp_lo & 0xFFFFFFFF));
143
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
160
+ value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq);
144
- value << 32 | (timecmp_lo & 0xFFFFFFFF),
161
} else {
145
- mtimer->timebase_freq);
162
error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
146
+ value << 32 | (timecmp_lo & 0xFFFFFFFF));
163
}
147
} else {
164
@@ -XXX,XX +XXX,XX @@ static Property sifive_clint_properties[] = {
148
qemu_log_mask(LOG_GUEST_ERROR,
165
DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
149
"aclint-mtimer: invalid timecmp_hi write: %08x",
166
DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
150
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
167
DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
151
(uint32_t)addr);
168
+ DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
152
}
169
DEFINE_PROP_END_OF_LIST(),
153
return;
170
};
154
- } else if (addr == mtimer->time_base) {
171
155
- /* time_lo */
172
@@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types)
156
- qemu_log_mask(LOG_UNIMP,
173
*/
157
- "aclint-mtimer: time_lo write not implemented");
174
DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
158
- return;
175
uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
159
- } else if (addr == mtimer->time_base + 4) {
176
- uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
160
- /* time_hi */
177
+ uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
161
- qemu_log_mask(LOG_UNIMP,
178
+ bool provide_rdtime)
162
- "aclint-mtimer: time_hi write not implemented");
179
{
163
+ } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
180
int i;
164
+ uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
181
for (i = 0; i < num_harts; i++) {
165
+
182
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
166
+ if (addr == mtimer->time_base) {
167
+ if (size == 4) {
168
+ /* time_lo for RV32/RV64 */
169
+ mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r;
170
+ } else {
171
+ /* time for RV64 */
172
+ mtimer->time_delta = value - rtc_r;
173
+ }
174
+ } else {
175
+ if (size == 4) {
176
+ /* time_hi for RV32/RV64 */
177
+ mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r;
178
+ } else {
179
+ qemu_log_mask(LOG_GUEST_ERROR,
180
+ "aclint-mtimer: invalid time_hi write: %08x",
181
+ (uint32_t)addr);
182
+ return;
183
+ }
184
+ }
185
+
186
+ /* Check if timer interrupt is triggered for each hart. */
187
+ for (i = 0; i < mtimer->num_harts; i++) {
188
+ CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i);
189
+ CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
190
+ if (!env) {
191
+ continue;
192
+ }
193
+ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
194
+ i, env->timecmp);
195
+ }
196
return;
197
}
198
199
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
183
continue;
200
continue;
184
}
201
}
185
if (provide_rdtime) {
202
if (provide_rdtime) {
186
- riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
203
- riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
187
+ riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
204
+ riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev);
188
}
205
}
189
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
206
190
&sifive_clint_timer_cb, cpu);
207
cb->s = RISCV_ACLINT_MTIMER(dev);
191
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
192
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
193
qdev_prop_set_uint32(dev, "time-base", time_base);
194
qdev_prop_set_uint32(dev, "aperture-size", size);
195
+ qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
196
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
197
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
198
return dev;
199
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/riscv/sifive_e.c
202
+++ b/hw/riscv/sifive_e.c
203
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
204
memmap[SIFIVE_E_PLIC].size);
205
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
206
memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
207
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
208
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
209
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
210
create_unimplemented_device("riscv.sifive.e.aon",
211
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
212
sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
213
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
214
index XXXXXXX..XXXXXXX 100644
215
--- a/hw/riscv/sifive_u.c
216
+++ b/hw/riscv/sifive_u.c
217
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
218
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
219
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
220
memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
221
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
222
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
223
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
224
225
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
226
return;
227
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/hw/riscv/spike.c
230
+++ b/hw/riscv/spike.c
231
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
232
sifive_clint_create(
233
memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
234
memmap[SPIKE_CLINT].size, base_hartid, hart_count,
235
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
236
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
237
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
238
}
239
240
/* register system main memory (actual RAM) */
241
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/riscv/virt.c
244
+++ b/hw/riscv/virt.c
245
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
246
sifive_clint_create(
247
memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
248
memmap[VIRT_CLINT].size, base_hartid, hart_count,
249
- SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
250
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
251
+ SIFIVE_CLINT_TIMEBASE_FREQ, true);
252
253
/* Per-socket PLIC hart topology configuration string */
254
plic_hart_config_len =
255
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
208
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
256
index XXXXXXX..XXXXXXX 100644
209
index XXXXXXX..XXXXXXX 100644
257
--- a/target/riscv/cpu_helper.c
210
--- a/target/riscv/cpu_helper.c
258
+++ b/target/riscv/cpu_helper.c
211
+++ b/target/riscv/cpu_helper.c
259
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
212
@@ -XXX,XX +XXX,XX @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
260
return old;
213
return old;
261
}
214
}
262
215
263
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
216
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
264
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
217
- uint32_t arg)
265
+ uint32_t arg)
218
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
219
+ void *arg)
266
{
220
{
267
env->rdtime_fn = fn;
221
env->rdtime_fn = fn;
268
+ env->rdtime_fn_arg = arg;
222
env->rdtime_fn_arg = arg;
269
}
270
271
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
272
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
273
index XXXXXXX..XXXXXXX 100644
274
--- a/target/riscv/csr.c
275
+++ b/target/riscv/csr.c
276
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
277
return -RISCV_EXCP_ILLEGAL_INST;
278
}
279
280
- *val = env->rdtime_fn() + delta;
281
+ *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
282
return 0;
283
}
284
285
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
286
return -RISCV_EXCP_ILLEGAL_INST;
287
}
288
289
- *val = (env->rdtime_fn() + delta) >> 32;
290
+ *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
291
return 0;
292
}
293
#endif
294
--
223
--
295
2.28.0
224
2.35.1
296
297
diff view generated by jsdifflib
[PULL 09/30] hw/sd: Add Cadence SDHCI emulation
[PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Jim Shu <jim.shu@sifive.com>
2
2
3
Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
3
This commit implements reset function of all ACLINT devices.
4
controller. The SDHCI compatible registers start from offset 0x200,
4
ACLINT device reset will clear MTIME and MSIP register to 0.
5
which are called Slot Register Set (SRS) in its datasheet.
6
5
7
This creates a Cadence SDHCI model built on top of the existing
6
Depend on RISC-V ACLINT spec v1.0-rc4:
8
generic SDHCI model. Cadence specific Host Register Set (HRS) is
7
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
9
implemented to make guest software happy.
10
8
11
Signed-off-by: Bin Meng <bin.meng@windriver.com>
9
Signed-off-by: Jim Shu <jim.shu@sifive.com>
12
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Frank Chang <frank.chang@sifive.com>
13
Acked-by: Alistair Francis <alistair.francis@wdc.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
12
Message-Id: <20220420080901.14655-5-frank.chang@sifive.com>
15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
16
---
14
---
17
include/hw/sd/cadence_sdhci.h | 47 +++++++++
15
hw/intc/riscv_aclint.c | 39 +++++++++++++++++++++++++++++++++++++++
18
hw/sd/cadence_sdhci.c | 193 ++++++++++++++++++++++++++++++++++
16
1 file changed, 39 insertions(+)
19
hw/sd/Kconfig | 4 +
20
hw/sd/meson.build | 1 +
21
4 files changed, 245 insertions(+)
22
create mode 100644 include/hw/sd/cadence_sdhci.h
23
create mode 100644 hw/sd/cadence_sdhci.c
24
17
25
diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h
18
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
26
new file mode 100644
19
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX
20
--- a/hw/intc/riscv_aclint.c
28
--- /dev/null
21
+++ b/hw/intc/riscv_aclint.c
29
+++ b/include/hw/sd/cadence_sdhci.h
22
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp)
30
@@ -XXX,XX +XXX,XX @@
23
}
31
+/*
24
}
32
+ * Cadence SDHCI emulation
25
33
+ *
26
+static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type)
34
+ * Copyright (c) 2020 Wind River Systems, Inc.
27
+{
35
+ *
28
+ /*
36
+ * Author:
29
+ * According to RISC-V ACLINT spec:
37
+ * Bin Meng <bin.meng@windriver.com>
30
+ * - On MTIMER device reset, the MTIME register is cleared to zero.
38
+ *
31
+ * - On MTIMER device reset, the MTIMECMP registers are in unknown state.
39
+ * This program is free software; you can redistribute it and/or
32
+ */
40
+ * modify it under the terms of the GNU General Public License as
33
+ RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj);
41
+ * published by the Free Software Foundation; either version 2 or
42
+ * (at your option) version 3 of the License.
43
+ *
44
+ * This program is distributed in the hope that it will be useful,
45
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
46
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
47
+ * GNU General Public License for more details.
48
+ *
49
+ * You should have received a copy of the GNU General Public License along
50
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
51
+ */
52
+
34
+
53
+#ifndef CADENCE_SDHCI_H
35
+ /*
54
+#define CADENCE_SDHCI_H
36
+ * Clear mtime register by writing to 0 it.
55
+
37
+ * Pending mtime interrupts will also be cleared at the same time.
56
+#include "hw/sd/sdhci.h"
38
+ */
57
+
39
+ riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8);
58
+#define CADENCE_SDHCI_REG_SIZE 0x100
59
+#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
60
+
61
+typedef struct CadenceSDHCIState {
62
+ SysBusDevice parent;
63
+
64
+ MemoryRegion container;
65
+ MemoryRegion iomem;
66
+ BusState *bus;
67
+
68
+ uint32_t regs[CADENCE_SDHCI_NUM_REGS];
69
+
70
+ SDHCIState sdhci;
71
+} CadenceSDHCIState;
72
+
73
+#define TYPE_CADENCE_SDHCI "cadence.sdhci"
74
+#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \
75
+ TYPE_CADENCE_SDHCI)
76
+
77
+#endif /* CADENCE_SDHCI_H */
78
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
79
new file mode 100644
80
index XXXXXXX..XXXXXXX
81
--- /dev/null
82
+++ b/hw/sd/cadence_sdhci.c
83
@@ -XXX,XX +XXX,XX @@
84
+/*
85
+ * Cadence SDHCI emulation
86
+ *
87
+ * Copyright (c) 2020 Wind River Systems, Inc.
88
+ *
89
+ * Author:
90
+ * Bin Meng <bin.meng@windriver.com>
91
+ *
92
+ * This program is free software; you can redistribute it and/or
93
+ * modify it under the terms of the GNU General Public License as
94
+ * published by the Free Software Foundation; either version 2 or
95
+ * (at your option) version 3 of the License.
96
+ *
97
+ * This program is distributed in the hope that it will be useful,
98
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
99
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
100
+ * GNU General Public License for more details.
101
+ *
102
+ * You should have received a copy of the GNU General Public License along
103
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
104
+ */
105
+
106
+#include "qemu/osdep.h"
107
+#include "qemu/bitops.h"
108
+#include "qemu/error-report.h"
109
+#include "qemu/log.h"
110
+#include "qapi/error.h"
111
+#include "migration/vmstate.h"
112
+#include "hw/irq.h"
113
+#include "hw/sd/cadence_sdhci.h"
114
+#include "sdhci-internal.h"
115
+
116
+/* HRS - Host Register Set (specific to Cadence) */
117
+
118
+#define CADENCE_SDHCI_HRS00 0x00 /* general information */
119
+#define CADENCE_SDHCI_HRS00_SWR BIT(0)
120
+#define CADENCE_SDHCI_HRS00_POR_VAL 0x00010000
121
+
122
+#define CADENCE_SDHCI_HRS04 0x10 /* PHY access port */
123
+#define CADENCE_SDHCI_HRS04_WR BIT(24)
124
+#define CADENCE_SDHCI_HRS04_RD BIT(25)
125
+#define CADENCE_SDHCI_HRS04_ACK BIT(26)
126
+
127
+#define CADENCE_SDHCI_HRS06 0x18 /* eMMC control */
128
+#define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15)
129
+
130
+/* SRS - Slot Register Set (SDHCI-compatible) */
131
+
132
+#define CADENCE_SDHCI_SRS_BASE 0x200
133
+
134
+#define TO_REG(addr) ((addr) / sizeof(uint32_t))
135
+
136
+static void cadence_sdhci_instance_init(Object *obj)
137
+{
138
+ CadenceSDHCIState *s = CADENCE_SDHCI(obj);
139
+
140
+ object_initialize_child(OBJECT(s), "generic-sdhci",
141
+ &s->sdhci, TYPE_SYSBUS_SDHCI);
142
+}
40
+}
143
+
41
+
144
+static void cadence_sdhci_reset(DeviceState *dev)
42
static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data)
43
{
44
DeviceClass *dc = DEVICE_CLASS(klass);
45
dc->realize = riscv_aclint_mtimer_realize;
46
device_class_set_props(dc, riscv_aclint_mtimer_properties);
47
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
48
+ rc->phases.enter = riscv_aclint_mtimer_reset_enter;
49
}
50
51
static const TypeInfo riscv_aclint_mtimer_info = {
52
@@ -XXX,XX +XXX,XX @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp)
53
}
54
}
55
56
+static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type)
145
+{
57
+{
146
+ CadenceSDHCIState *s = CADENCE_SDHCI(dev);
58
+ /*
59
+ * According to RISC-V ACLINT spec:
60
+ * - On MSWI device reset, each MSIP register is cleared to zero.
61
+ *
62
+ * p.s. SSWI device reset does nothing since SETSIP register always reads 0.
63
+ */
64
+ RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj);
65
+ int i;
147
+
66
+
148
+ memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE);
67
+ if (!swi->sswi) {
149
+ s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL;
68
+ for (i = 0; i < swi->num_harts; i++) {
150
+
69
+ /* Clear MSIP registers by lowering software interrupts. */
151
+ device_cold_reset(DEVICE(&s->sdhci));
70
+ qemu_irq_lower(swi->soft_irqs[i]);
152
+}
153
+
154
+static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
155
+{
156
+ CadenceSDHCIState *s = opaque;
157
+ uint32_t val;
158
+
159
+ val = s->regs[TO_REG(addr)];
160
+
161
+ return (uint64_t)val;
162
+}
163
+
164
+static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
165
+ unsigned int size)
166
+{
167
+ CadenceSDHCIState *s = opaque;
168
+ uint32_t val32 = (uint32_t)val;
169
+
170
+ switch (addr) {
171
+ case CADENCE_SDHCI_HRS00:
172
+ /*
173
+ * The only writable bit is SWR (software reset) and it automatically
174
+ * clears to zero, so essentially this register remains unchanged.
175
+ */
176
+ if (val32 & CADENCE_SDHCI_HRS00_SWR) {
177
+ cadence_sdhci_reset(DEVICE(s));
178
+ }
71
+ }
179
+
180
+ break;
181
+ case CADENCE_SDHCI_HRS04:
182
+ /*
183
+ * Only emulate the ACK bit behavior when read or write transaction
184
+ * are requested.
185
+ */
186
+ if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) {
187
+ val32 |= CADENCE_SDHCI_HRS04_ACK;
188
+ } else {
189
+ val32 &= ~CADENCE_SDHCI_HRS04_ACK;
190
+ }
191
+
192
+ s->regs[TO_REG(addr)] = val32;
193
+ break;
194
+ case CADENCE_SDHCI_HRS06:
195
+ if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) {
196
+ val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP;
197
+ }
198
+
199
+ s->regs[TO_REG(addr)] = val32;
200
+ break;
201
+ default:
202
+ s->regs[TO_REG(addr)] = val32;
203
+ break;
204
+ }
72
+ }
205
+}
73
+}
206
+
74
+
207
+static const MemoryRegionOps cadence_sdhci_ops = {
75
static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data)
208
+ .read = cadence_sdhci_read,
76
{
209
+ .write = cadence_sdhci_write,
77
DeviceClass *dc = DEVICE_CLASS(klass);
210
+ .endianness = DEVICE_NATIVE_ENDIAN,
78
dc->realize = riscv_aclint_swi_realize;
211
+ .impl = {
79
device_class_set_props(dc, riscv_aclint_swi_properties);
212
+ .min_access_size = 4,
80
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
213
+ .max_access_size = 4,
81
+ rc->phases.enter = riscv_aclint_swi_reset_enter;
214
+ },
82
}
215
+ .valid = {
83
216
+ .min_access_size = 4,
84
static const TypeInfo riscv_aclint_swi_info = {
217
+ .max_access_size = 4,
218
+ }
219
+};
220
+
221
+static void cadence_sdhci_realize(DeviceState *dev, Error **errp)
222
+{
223
+ CadenceSDHCIState *s = CADENCE_SDHCI(dev);
224
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
225
+ SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
226
+
227
+ memory_region_init(&s->container, OBJECT(s),
228
+ "cadence.sdhci-container", 0x1000);
229
+ sysbus_init_mmio(sbd, &s->container);
230
+
231
+ memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops,
232
+ s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE);
233
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
234
+
235
+ sysbus_realize(sbd_sdhci, errp);
236
+ memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE,
237
+ sysbus_mmio_get_region(sbd_sdhci, 0));
238
+
239
+ /* propagate irq and "sd-bus" from generic-sdhci */
240
+ sysbus_pass_irq(sbd, sbd_sdhci);
241
+ s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
242
+}
243
+
244
+static const VMStateDescription vmstate_cadence_sdhci = {
245
+ .name = TYPE_CADENCE_SDHCI,
246
+ .version_id = 1,
247
+ .fields = (VMStateField[]) {
248
+ VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS),
249
+ VMSTATE_END_OF_LIST(),
250
+ },
251
+};
252
+
253
+static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
254
+{
255
+ DeviceClass *dc = DEVICE_CLASS(classp);
256
+
257
+ dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)";
258
+ dc->realize = cadence_sdhci_realize;
259
+ dc->reset = cadence_sdhci_reset;
260
+ dc->vmsd = &vmstate_cadence_sdhci;
261
+}
262
+
263
+static TypeInfo cadence_sdhci_info = {
264
+ .name = TYPE_CADENCE_SDHCI,
265
+ .parent = TYPE_SYS_BUS_DEVICE,
266
+ .instance_size = sizeof(CadenceSDHCIState),
267
+ .instance_init = cadence_sdhci_instance_init,
268
+ .class_init = cadence_sdhci_class_init,
269
+};
270
+
271
+static void cadence_sdhci_register_types(void)
272
+{
273
+ type_register_static(&cadence_sdhci_info);
274
+}
275
+
276
+type_init(cadence_sdhci_register_types)
277
diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig
278
index XXXXXXX..XXXXXXX 100644
279
--- a/hw/sd/Kconfig
280
+++ b/hw/sd/Kconfig
281
@@ -XXX,XX +XXX,XX @@ config SDHCI_PCI
282
default y if PCI_DEVICES
283
depends on PCI
284
select SDHCI
285
+
286
+config CADENCE_SDHCI
287
+ bool
288
+ select SDHCI
289
diff --git a/hw/sd/meson.build b/hw/sd/meson.build
290
index XXXXXXX..XXXXXXX 100644
291
--- a/hw/sd/meson.build
292
+++ b/hw/sd/meson.build
293
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c'))
294
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
295
softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
296
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
297
+softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
298
--
85
--
299
2.28.0
86
2.35.1
300
301
diff view generated by jsdifflib
[PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller
[PULL v2 25/31] target/riscv: debug: Implement debug related TCGCPUOps
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
3
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
4
controller to move the 2nd stage bootloader in the system memory.
4
TCGCPUOps and hook them into riscv_tcg_ops.
5
Let's connect a DMA controller to Microchip PolarFire SoC.
6
5
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
8
Message-Id: <20220421003324.1134983-2-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
10
---
12
include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
11
target/riscv/debug.h | 4 +++
13
hw/riscv/microchip_pfsoc.c | 15 +++++++++++++++
12
target/riscv/cpu.c | 3 ++
14
hw/riscv/Kconfig | 1 +
13
target/riscv/debug.c | 75 ++++++++++++++++++++++++++++++++++++++++++++
15
3 files changed, 27 insertions(+)
14
3 files changed, 82 insertions(+)
16
15
17
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
16
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/riscv/microchip_pfsoc.h
18
--- a/target/riscv/debug.h
20
+++ b/include/hw/riscv/microchip_pfsoc.h
19
+++ b/target/riscv/debug.h
21
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ void tselect_csr_write(CPURISCVState *env, target_ulong val);
22
#define HW_MICROCHIP_PFSOC_H
21
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
23
22
void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
24
#include "hw/char/mchp_pfsoc_mmuart.h"
23
25
+#include "hw/dma/sifive_pdma.h"
24
+void riscv_cpu_debug_excp_handler(CPUState *cs);
26
#include "hw/sd/cadence_sdhci.h"
25
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
27
26
+bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
28
typedef struct MicrochipPFSoCState {
27
+
29
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
28
#endif /* RISCV_DEBUG_H */
30
MchpPfSoCMMUartState *serial2;
29
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
31
MchpPfSoCMMUartState *serial3;
30
index XXXXXXX..XXXXXXX 100644
32
MchpPfSoCMMUartState *serial4;
31
--- a/target/riscv/cpu.c
33
+ SiFivePDMAState dma;
32
+++ b/target/riscv/cpu.c
34
CadenceSDHCIState sdhci;
33
@@ -XXX,XX +XXX,XX @@ static const struct TCGCPUOps riscv_tcg_ops = {
35
} MicrochipPFSoCState;
34
.do_interrupt = riscv_cpu_do_interrupt,
36
35
.do_transaction_failed = riscv_cpu_do_transaction_failed,
37
@@ -XXX,XX +XXX,XX @@ enum {
36
.do_unaligned_access = riscv_cpu_do_unaligned_access,
38
MICROCHIP_PFSOC_BUSERR_UNIT4,
37
+ .debug_excp_handler = riscv_cpu_debug_excp_handler,
39
MICROCHIP_PFSOC_CLINT,
38
+ .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
40
MICROCHIP_PFSOC_L2CC,
39
+ .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
41
+ MICROCHIP_PFSOC_DMA,
40
#endif /* !CONFIG_USER_ONLY */
42
MICROCHIP_PFSOC_L2LIM,
43
MICROCHIP_PFSOC_PLIC,
44
MICROCHIP_PFSOC_MMUART0,
45
@@ -XXX,XX +XXX,XX @@ enum {
46
};
41
};
47
42
48
enum {
43
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
49
+ MICROCHIP_PFSOC_DMA_IRQ0 = 5,
50
+ MICROCHIP_PFSOC_DMA_IRQ1 = 6,
51
+ MICROCHIP_PFSOC_DMA_IRQ2 = 7,
52
+ MICROCHIP_PFSOC_DMA_IRQ3 = 8,
53
+ MICROCHIP_PFSOC_DMA_IRQ4 = 9,
54
+ MICROCHIP_PFSOC_DMA_IRQ5 = 10,
55
+ MICROCHIP_PFSOC_DMA_IRQ6 = 11,
56
+ MICROCHIP_PFSOC_DMA_IRQ7 = 12,
57
MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
58
MICROCHIP_PFSOC_MMUART0_IRQ = 90,
59
MICROCHIP_PFSOC_MMUART1_IRQ = 91,
60
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
61
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/riscv/microchip_pfsoc.c
45
--- a/target/riscv/debug.c
63
+++ b/hw/riscv/microchip_pfsoc.c
46
+++ b/target/riscv/debug.c
64
@@ -XXX,XX +XXX,XX @@
47
@@ -XXX,XX +XXX,XX @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
65
* 2) eNVM (Embedded Non-Volatile Memory)
48
66
* 3) MMUARTs (Multi-Mode UART)
49
return write_func(env, env->trigger_cur, tdata_index, val);
67
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
50
}
68
+ * 5) SiFive Platform DMA (Direct Memory Access Controller)
69
*
70
* This board currently generates devicetree dynamically that indicates at least
71
* two harts and up to five harts.
72
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
73
[MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
74
[MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
75
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
76
+ [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
77
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
78
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
79
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
80
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
81
TYPE_RISCV_CPU_SIFIVE_U54);
82
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
83
84
+ object_initialize_child(obj, "dma-controller", &s->dma,
85
+ TYPE_SIFIVE_PDMA);
86
+
51
+
87
object_initialize_child(obj, "sd-controller", &s->sdhci,
52
+void riscv_cpu_debug_excp_handler(CPUState *cs)
88
TYPE_CADENCE_SDHCI);
53
+{
89
}
54
+ RISCVCPU *cpu = RISCV_CPU(cs);
90
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
55
+ CPURISCVState *env = &cpu->env;
91
memmap[MICROCHIP_PFSOC_PLIC].size);
56
+
92
g_free(plic_hart_config);
57
+ if (cs->watchpoint_hit) {
93
58
+ if (cs->watchpoint_hit->flags & BP_CPU) {
94
+ /* DMA */
59
+ cs->watchpoint_hit = NULL;
95
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
60
+ riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
96
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
61
+ }
97
+ memmap[MICROCHIP_PFSOC_DMA].base);
62
+ } else {
98
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
63
+ if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
99
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
64
+ riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
100
+ qdev_get_gpio_in(DEVICE(s->plic),
65
+ }
101
+ MICROCHIP_PFSOC_DMA_IRQ0 + i));
66
+ }
67
+}
68
+
69
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
70
+{
71
+ RISCVCPU *cpu = RISCV_CPU(cs);
72
+ CPURISCVState *env = &cpu->env;
73
+ CPUBreakpoint *bp;
74
+ target_ulong ctrl;
75
+ target_ulong pc;
76
+ int i;
77
+
78
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
79
+ for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
80
+ ctrl = env->type2_trig[i].mcontrol;
81
+ pc = env->type2_trig[i].maddress;
82
+
83
+ if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
84
+ /* check U/S/M bit against current privilege level */
85
+ if ((ctrl >> 3) & BIT(env->priv)) {
86
+ return true;
87
+ }
88
+ }
89
+ }
102
+ }
90
+ }
103
+
91
+
104
/* SYSREG */
92
+ return false;
105
create_unimplemented_device("microchip.pfsoc.sysreg",
93
+}
106
memmap[MICROCHIP_PFSOC_SYSREG].base,
94
+
107
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
95
+bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
108
index XXXXXXX..XXXXXXX 100644
96
+{
109
--- a/hw/riscv/Kconfig
97
+ RISCVCPU *cpu = RISCV_CPU(cs);
110
+++ b/hw/riscv/Kconfig
98
+ CPURISCVState *env = &cpu->env;
111
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
99
+ target_ulong ctrl;
112
select SIFIVE
100
+ target_ulong addr;
113
select UNIMP
101
+ int flags;
114
select MCHP_PFSOC_MMUART
102
+ int i;
115
+ select SIFIVE_PDMA
103
+
116
select CADENCE_SDHCI
104
+ for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
105
+ ctrl = env->type2_trig[i].mcontrol;
106
+ addr = env->type2_trig[i].maddress;
107
+ flags = 0;
108
+
109
+ if (ctrl & TYPE2_LOAD) {
110
+ flags |= BP_MEM_READ;
111
+ }
112
+ if (ctrl & TYPE2_STORE) {
113
+ flags |= BP_MEM_WRITE;
114
+ }
115
+
116
+ if ((wp->flags & flags) && (wp->vaddr == addr)) {
117
+ /* check U/S/M bit against current privilege level */
118
+ if ((ctrl >> 3) & BIT(env->priv)) {
119
+ return true;
120
+ }
121
+ }
122
+ }
123
+
124
+ return false;
125
+}
117
--
126
--
118
2.28.0
127
2.35.1
119
120
diff view generated by jsdifflib
[PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property
[PULL v2 26/31] target/riscv: cpu: Add a config option for native debug
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Currently the reset vector address is hard-coded in a RISC-V CPU's
3
Add a config option to enable support for native M-mode debug.
4
instance_init() routine. In a real world we can have 2 exact same
4
This is disabled by default and can be enabled with 'debug=true'.
5
CPUs except for the reset vector address, which is pretty common in
6
the RISC-V core IP licensing business.
7
8
Normally reset vector address is a configurable parameter. Let's
9
create a 64-bit property to store the reset vector address which
10
covers both 32-bit and 64-bit CPUs.
11
5
12
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-Id: <20220421003324.1134983-3-bmeng.cn@gmail.com>
15
Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
16
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
17
---
10
---
18
target/riscv/cpu.h | 1 +
11
target/riscv/cpu.h | 4 +++-
19
target/riscv/cpu.c | 1 +
12
target/riscv/cpu.c | 5 +++++
20
2 files changed, 2 insertions(+)
13
2 files changed, 8 insertions(+), 1 deletion(-)
21
14
22
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
15
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
23
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
24
--- a/target/riscv/cpu.h
17
--- a/target/riscv/cpu.h
25
+++ b/target/riscv/cpu.h
18
+++ b/target/riscv/cpu.h
26
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPU {
19
@@ -XXX,XX +XXX,XX @@ enum {
27
uint16_t elen;
20
RISCV_FEATURE_PMP,
28
bool mmu;
21
RISCV_FEATURE_EPMP,
29
bool pmp;
22
RISCV_FEATURE_MISA,
30
+ uint64_t resetvec;
23
- RISCV_FEATURE_AIA
31
} cfg;
24
+ RISCV_FEATURE_AIA,
32
} RISCVCPU;
25
+ RISCV_FEATURE_DEBUG
26
};
27
28
/* Privileged specification version */
29
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
30
bool pmp;
31
bool epmp;
32
bool aia;
33
+ bool debug;
34
uint64_t resetvec;
35
};
33
36
34
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
37
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
35
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
36
--- a/target/riscv/cpu.c
39
--- a/target/riscv/cpu.c
37
+++ b/target/riscv/cpu.c
40
+++ b/target/riscv/cpu.c
41
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
42
riscv_set_feature(env, RISCV_FEATURE_AIA);
43
}
44
45
+ if (cpu->cfg.debug) {
46
+ riscv_set_feature(env, RISCV_FEATURE_DEBUG);
47
+ }
48
+
49
set_resetvec(env, cpu->cfg.resetvec);
50
51
/* Validate that MISA_MXL is set properly. */
38
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
52
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
39
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
53
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
40
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
54
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
41
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
55
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
42
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
56
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
43
DEFINE_PROP_END_OF_LIST(),
57
44
};
58
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
45
59
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
46
--
60
--
47
2.28.0
61
2.35.1
48
49
diff view generated by jsdifflib
[PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation
[PULL v2 27/31] target/riscv: csr: Hook debug CSR read/write
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Microchip PolarFire SoC integrates a DMA engine that supports:
3
This adds debug CSR read/write support to the RISC-V CSR RW table.
4
* Independent concurrent DMA transfers using 4 DMA channels
5
* Generation of interrupts on various conditions during execution
6
which is actually an IP reused from the SiFive FU540 chip.
7
8
This creates a model to support both polling and interrupt modes.
9
4
10
Signed-off-by: Bin Meng <bin.meng@windriver.com>
5
Signed-off-by: Bin Meng <bin.meng@windriver.com>
11
Acked-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
7
Message-Id: <20220421003324.1134983-4-bmeng.cn@gmail.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
9
---
15
include/hw/dma/sifive_pdma.h | 57 +++++++
10
target/riscv/debug.h | 2 ++
16
hw/dma/sifive_pdma.c | 313 +++++++++++++++++++++++++++++++++++
11
target/riscv/cpu.c | 4 ++++
17
hw/dma/Kconfig | 3 +
12
target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++
18
hw/dma/meson.build | 1 +
13
target/riscv/debug.c | 27 +++++++++++++++++++++
19
4 files changed, 374 insertions(+)
14
4 files changed, 90 insertions(+)
20
create mode 100644 include/hw/dma/sifive_pdma.h
21
create mode 100644 hw/dma/sifive_pdma.c
22
15
23
diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h
16
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
24
new file mode 100644
17
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX
18
--- a/target/riscv/debug.h
26
--- /dev/null
19
+++ b/target/riscv/debug.h
27
+++ b/include/hw/dma/sifive_pdma.h
20
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
28
@@ -XXX,XX +XXX,XX @@
21
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
29
+/*
22
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
30
+ * SiFive Platform DMA emulation
23
31
+ *
24
+void riscv_trigger_init(CPURISCVState *env);
32
+ * Copyright (c) 2020 Wind River Systems, Inc.
33
+ *
34
+ * Author:
35
+ * Bin Meng <bin.meng@windriver.com>
36
+ *
37
+ * This program is free software; you can redistribute it and/or
38
+ * modify it under the terms of the GNU General Public License as
39
+ * published by the Free Software Foundation; either version 2 or
40
+ * (at your option) version 3 of the License.
41
+ *
42
+ * This program is distributed in the hope that it will be useful,
43
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
44
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45
+ * GNU General Public License for more details.
46
+ *
47
+ * You should have received a copy of the GNU General Public License along
48
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
49
+ */
50
+
25
+
51
+#ifndef SIFIVE_PDMA_H
26
#endif /* RISCV_DEBUG_H */
52
+#define SIFIVE_PDMA_H
27
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
53
+
28
index XXXXXXX..XXXXXXX 100644
54
+struct sifive_pdma_chan {
29
--- a/target/riscv/cpu.c
55
+ uint32_t control;
30
+++ b/target/riscv/cpu.c
56
+ uint32_t next_config;
31
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
57
+ uint64_t next_bytes;
32
set_default_nan_mode(1, &env->fp_status);
58
+ uint64_t next_dst;
33
59
+ uint64_t next_src;
34
#ifndef CONFIG_USER_ONLY
60
+ uint32_t exec_config;
35
+ if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
61
+ uint64_t exec_bytes;
36
+ riscv_trigger_init(env);
62
+ uint64_t exec_dst;
63
+ uint64_t exec_src;
64
+ int state;
65
+};
66
+
67
+#define SIFIVE_PDMA_CHANS 4
68
+#define SIFIVE_PDMA_IRQS (SIFIVE_PDMA_CHANS * 2)
69
+#define SIFIVE_PDMA_REG_SIZE 0x100000
70
+#define SIFIVE_PDMA_CHAN_NO(reg) ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
71
+
72
+typedef struct SiFivePDMAState {
73
+ SysBusDevice parent;
74
+ MemoryRegion iomem;
75
+ qemu_irq irq[SIFIVE_PDMA_IRQS];
76
+
77
+ struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
78
+} SiFivePDMAState;
79
+
80
+#define TYPE_SIFIVE_PDMA "sifive.pdma"
81
+
82
+#define SIFIVE_PDMA(obj) \
83
+ OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
84
+
85
+#endif /* SIFIVE_PDMA_H */
86
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
87
new file mode 100644
88
index XXXXXXX..XXXXXXX
89
--- /dev/null
90
+++ b/hw/dma/sifive_pdma.c
91
@@ -XXX,XX +XXX,XX @@
92
+/*
93
+ * SiFive Platform DMA emulation
94
+ *
95
+ * Copyright (c) 2020 Wind River Systems, Inc.
96
+ *
97
+ * Author:
98
+ * Bin Meng <bin.meng@windriver.com>
99
+ *
100
+ * This program is free software; you can redistribute it and/or
101
+ * modify it under the terms of the GNU General Public License as
102
+ * published by the Free Software Foundation; either version 2 or
103
+ * (at your option) version 3 of the License.
104
+ *
105
+ * This program is distributed in the hope that it will be useful,
106
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
107
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
108
+ * GNU General Public License for more details.
109
+ *
110
+ * You should have received a copy of the GNU General Public License along
111
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
112
+ */
113
+
114
+#include "qemu/osdep.h"
115
+#include "qemu/bitops.h"
116
+#include "qemu/log.h"
117
+#include "qapi/error.h"
118
+#include "hw/hw.h"
119
+#include "hw/irq.h"
120
+#include "hw/qdev-properties.h"
121
+#include "hw/sysbus.h"
122
+#include "migration/vmstate.h"
123
+#include "sysemu/dma.h"
124
+#include "hw/dma/sifive_pdma.h"
125
+
126
+#define DMA_CONTROL 0x000
127
+#define CONTROL_CLAIM BIT(0)
128
+#define CONTROL_RUN BIT(1)
129
+#define CONTROL_DONE_IE BIT(14)
130
+#define CONTROL_ERR_IE BIT(15)
131
+#define CONTROL_DONE BIT(30)
132
+#define CONTROL_ERR BIT(31)
133
+
134
+#define DMA_NEXT_CONFIG 0x004
135
+#define CONFIG_REPEAT BIT(2)
136
+#define CONFIG_ORDER BIT(3)
137
+#define CONFIG_WRSZ_SHIFT 24
138
+#define CONFIG_RDSZ_SHIFT 28
139
+#define CONFIG_SZ_MASK 0xf
140
+
141
+#define DMA_NEXT_BYTES 0x008
142
+#define DMA_NEXT_DST 0x010
143
+#define DMA_NEXT_SRC 0x018
144
+#define DMA_EXEC_CONFIG 0x104
145
+#define DMA_EXEC_BYTES 0x108
146
+#define DMA_EXEC_DST 0x110
147
+#define DMA_EXEC_SRC 0x118
148
+
149
+enum dma_chan_state {
150
+ DMA_CHAN_STATE_IDLE,
151
+ DMA_CHAN_STATE_STARTED,
152
+ DMA_CHAN_STATE_ERROR,
153
+ DMA_CHAN_STATE_DONE
154
+};
155
+
156
+static void sifive_pdma_run(SiFivePDMAState *s, int ch)
157
+{
158
+ uint64_t bytes = s->chan[ch].next_bytes;
159
+ uint64_t dst = s->chan[ch].next_dst;
160
+ uint64_t src = s->chan[ch].next_src;
161
+ uint32_t config = s->chan[ch].next_config;
162
+ int wsize, rsize, size;
163
+ uint8_t buf[64];
164
+ int n;
165
+
166
+ /* do nothing if bytes to transfer is zero */
167
+ if (!bytes) {
168
+ goto error;
169
+ }
37
+ }
170
+
38
+
171
+ /*
39
if (kvm_enabled()) {
172
+ * The manual does not describe how the hardware behaviors when
40
kvm_riscv_reset_vcpu(cpu);
173
+ * config.wsize and config.rsize are given different values.
41
}
174
+ * A common case is memory to memory DMA, and in this case they
42
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
175
+ * are normally the same. Abort if this expectation fails.
43
index XXXXXXX..XXXXXXX 100644
176
+ */
44
--- a/target/riscv/csr.c
177
+ wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
45
+++ b/target/riscv/csr.c
178
+ rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
46
@@ -XXX,XX +XXX,XX @@ static RISCVException epmp(CPURISCVState *env, int csrno)
179
+ if (wsize != rsize) {
47
180
+ goto error;
48
return RISCV_EXCP_ILLEGAL_INST;
49
}
50
+
51
+static RISCVException debug(CPURISCVState *env, int csrno)
52
+{
53
+ if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
54
+ return RISCV_EXCP_NONE;
181
+ }
55
+ }
182
+
56
+
183
+ /*
57
+ return RISCV_EXCP_ILLEGAL_INST;
184
+ * Calculate the transaction size
58
+}
185
+ *
59
#endif
186
+ * size field is base 2 logarithm of DMA transaction size,
60
187
+ * but there is an upper limit of 64 bytes per transaction.
61
/* User Floating-Point CSRs */
188
+ */
62
@@ -XXX,XX +XXX,XX @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
189
+ size = wsize;
63
return RISCV_EXCP_NONE;
190
+ if (size > 6) {
64
}
191
+ size = 6;
65
192
+ }
66
+static RISCVException read_tselect(CPURISCVState *env, int csrno,
193
+ size = 1 << size;
67
+ target_ulong *val)
68
+{
69
+ *val = tselect_csr_read(env);
70
+ return RISCV_EXCP_NONE;
71
+}
194
+
72
+
195
+ /* the bytes to transfer should be multiple of transaction size */
73
+static RISCVException write_tselect(CPURISCVState *env, int csrno,
196
+ if (bytes % size) {
74
+ target_ulong val)
197
+ goto error;
75
+{
76
+ tselect_csr_write(env, val);
77
+ return RISCV_EXCP_NONE;
78
+}
79
+
80
+static RISCVException read_tdata(CPURISCVState *env, int csrno,
81
+ target_ulong *val)
82
+{
83
+ /* return 0 in tdata1 to end the trigger enumeration */
84
+ if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) {
85
+ *val = 0;
86
+ return RISCV_EXCP_NONE;
198
+ }
87
+ }
199
+
88
+
200
+ /* indicate a DMA transfer is started */
89
+ if (!tdata_available(env, csrno - CSR_TDATA1)) {
201
+ s->chan[ch].state = DMA_CHAN_STATE_STARTED;
90
+ return RISCV_EXCP_ILLEGAL_INST;
202
+ s->chan[ch].control &= ~CONTROL_DONE;
203
+ s->chan[ch].control &= ~CONTROL_ERR;
204
+
205
+ /* load the next_ registers into their exec_ counterparts */
206
+ s->chan[ch].exec_config = config;
207
+ s->chan[ch].exec_bytes = bytes;
208
+ s->chan[ch].exec_dst = dst;
209
+ s->chan[ch].exec_src = src;
210
+
211
+ for (n = 0; n < bytes / size; n++) {
212
+ cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);
213
+ cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);
214
+ s->chan[ch].exec_src += size;
215
+ s->chan[ch].exec_dst += size;
216
+ s->chan[ch].exec_bytes -= size;
217
+ }
91
+ }
218
+
92
+
219
+ /* indicate a DMA transfer is done */
93
+ *val = tdata_csr_read(env, csrno - CSR_TDATA1);
220
+ s->chan[ch].state = DMA_CHAN_STATE_DONE;
94
+ return RISCV_EXCP_NONE;
221
+ s->chan[ch].control &= ~CONTROL_RUN;
95
+}
222
+ s->chan[ch].control |= CONTROL_DONE;
223
+
96
+
224
+ /* reload exec_ registers if repeat is required */
97
+static RISCVException write_tdata(CPURISCVState *env, int csrno,
225
+ if (s->chan[ch].next_config & CONFIG_REPEAT) {
98
+ target_ulong val)
226
+ s->chan[ch].exec_bytes = bytes;
99
+{
227
+ s->chan[ch].exec_dst = dst;
100
+ if (!tdata_available(env, csrno - CSR_TDATA1)) {
228
+ s->chan[ch].exec_src = src;
101
+ return RISCV_EXCP_ILLEGAL_INST;
229
+ }
102
+ }
230
+
103
+
231
+ return;
104
+ tdata_csr_write(env, csrno - CSR_TDATA1, val);
232
+
105
+ return RISCV_EXCP_NONE;
233
+error:
234
+ s->chan[ch].state = DMA_CHAN_STATE_ERROR;
235
+ s->chan[ch].control |= CONTROL_ERR;
236
+ return;
237
+}
106
+}
238
+
107
+
239
+static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
108
/*
109
* Functions to access Pointer Masking feature registers
110
* We have to check if current priv lvl could modify
111
@@ -XXX,XX +XXX,XX @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
112
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
113
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
114
115
+ /* Debug CSRs */
116
+ [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect },
117
+ [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata },
118
+ [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
119
+ [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
120
+
121
/* User Pointer Masking */
122
[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
123
[CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
124
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
125
index XXXXXXX..XXXXXXX 100644
126
--- a/target/riscv/debug.c
127
+++ b/target/riscv/debug.c
128
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
129
130
return false;
131
}
132
+
133
+void riscv_trigger_init(CPURISCVState *env)
240
+{
134
+{
241
+ bool done_ie, err_ie;
135
+ target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
136
+ int i;
242
+
137
+
243
+ done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);
138
+ /* type 2 triggers */
244
+ err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);
139
+ for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
245
+
140
+ /*
246
+ if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {
141
+ * type = TRIGGER_TYPE_AD_MATCH
247
+ qemu_irq_raise(s->irq[ch * 2]);
142
+ * dmode = 0 (both debug and M-mode can write tdata)
248
+ } else {
143
+ * maskmax = 0 (unimplemented, always 0)
249
+ qemu_irq_lower(s->irq[ch * 2]);
144
+ * sizehi = 0 (match against any size, RV64 only)
250
+ }
145
+ * hit = 0 (unimplemented, always 0)
251
+
146
+ * select = 0 (always 0, perform match on address)
252
+ if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {
147
+ * timing = 0 (always 0, trigger before instruction)
253
+ qemu_irq_raise(s->irq[ch * 2 + 1]);
148
+ * sizelo = 0 (match against any size)
254
+ } else {
149
+ * action = 0 (always 0, raise a breakpoint exception)
255
+ qemu_irq_lower(s->irq[ch * 2 + 1]);
150
+ * chain = 0 (unimplemented, always 0)
256
+ }
151
+ * match = 0 (always 0, when any compare value equals tdata2)
257
+
152
+ */
258
+ s->chan[ch].state = DMA_CHAN_STATE_IDLE;
153
+ env->type2_trig[i].mcontrol = type2;
259
+}
154
+ env->type2_trig[i].maddress = 0;
260
+
155
+ env->type2_trig[i].bp = NULL;
261
+static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned size)
156
+ env->type2_trig[i].wp = NULL;
262
+{
263
+ SiFivePDMAState *s = opaque;
264
+ int ch = SIFIVE_PDMA_CHAN_NO(offset);
265
+ uint64_t val = 0;
266
+
267
+ if (ch >= SIFIVE_PDMA_CHANS) {
268
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
269
+ __func__, ch);
270
+ return 0;
271
+ }
272
+
273
+ offset &= 0xfff;
274
+ switch (offset) {
275
+ case DMA_CONTROL:
276
+ val = s->chan[ch].control;
277
+ break;
278
+ case DMA_NEXT_CONFIG:
279
+ val = s->chan[ch].next_config;
280
+ break;
281
+ case DMA_NEXT_BYTES:
282
+ val = s->chan[ch].next_bytes;
283
+ break;
284
+ case DMA_NEXT_DST:
285
+ val = s->chan[ch].next_dst;
286
+ break;
287
+ case DMA_NEXT_SRC:
288
+ val = s->chan[ch].next_src;
289
+ break;
290
+ case DMA_EXEC_CONFIG:
291
+ val = s->chan[ch].exec_config;
292
+ break;
293
+ case DMA_EXEC_BYTES:
294
+ val = s->chan[ch].exec_bytes;
295
+ break;
296
+ case DMA_EXEC_DST:
297
+ val = s->chan[ch].exec_dst;
298
+ break;
299
+ case DMA_EXEC_SRC:
300
+ val = s->chan[ch].exec_src;
301
+ break;
302
+ default:
303
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
304
+ __func__, offset);
305
+ break;
306
+ }
307
+
308
+ return val;
309
+}
310
+
311
+static void sifive_pdma_write(void *opaque, hwaddr offset,
312
+ uint64_t value, unsigned size)
313
+{
314
+ SiFivePDMAState *s = opaque;
315
+ int ch = SIFIVE_PDMA_CHAN_NO(offset);
316
+
317
+ if (ch >= SIFIVE_PDMA_CHANS) {
318
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
319
+ __func__, ch);
320
+ return;
321
+ }
322
+
323
+ offset &= 0xfff;
324
+ switch (offset) {
325
+ case DMA_CONTROL:
326
+ s->chan[ch].control = value;
327
+
328
+ if (value & CONTROL_RUN) {
329
+ sifive_pdma_run(s, ch);
330
+ }
331
+
332
+ sifive_pdma_update_irq(s, ch);
333
+ break;
334
+ case DMA_NEXT_CONFIG:
335
+ s->chan[ch].next_config = value;
336
+ break;
337
+ case DMA_NEXT_BYTES:
338
+ s->chan[ch].next_bytes = value;
339
+ break;
340
+ case DMA_NEXT_DST:
341
+ s->chan[ch].next_dst = value;
342
+ break;
343
+ case DMA_NEXT_SRC:
344
+ s->chan[ch].next_src = value;
345
+ break;
346
+ case DMA_EXEC_CONFIG:
347
+ case DMA_EXEC_BYTES:
348
+ case DMA_EXEC_DST:
349
+ case DMA_EXEC_SRC:
350
+ /* these are read-only registers */
351
+ break;
352
+ default:
353
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
354
+ __func__, offset);
355
+ break;
356
+ }
157
+ }
357
+}
158
+}
358
+
359
+static const MemoryRegionOps sifive_pdma_ops = {
360
+ .read = sifive_pdma_read,
361
+ .write = sifive_pdma_write,
362
+ .endianness = DEVICE_LITTLE_ENDIAN,
363
+ /* there are 32-bit and 64-bit wide registers */
364
+ .impl = {
365
+ .min_access_size = 4,
366
+ .max_access_size = 8,
367
+ }
368
+};
369
+
370
+static void sifive_pdma_realize(DeviceState *dev, Error **errp)
371
+{
372
+ SiFivePDMAState *s = SIFIVE_PDMA(dev);
373
+ int i;
374
+
375
+ memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,
376
+ TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE);
377
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
378
+
379
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
380
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
381
+ }
382
+}
383
+
384
+static void sifive_pdma_class_init(ObjectClass *klass, void *data)
385
+{
386
+ DeviceClass *dc = DEVICE_CLASS(klass);
387
+
388
+ dc->desc = "SiFive Platform DMA controller";
389
+ dc->realize = sifive_pdma_realize;
390
+}
391
+
392
+static const TypeInfo sifive_pdma_info = {
393
+ .name = TYPE_SIFIVE_PDMA,
394
+ .parent = TYPE_SYS_BUS_DEVICE,
395
+ .instance_size = sizeof(SiFivePDMAState),
396
+ .class_init = sifive_pdma_class_init,
397
+};
398
+
399
+static void sifive_pdma_register_types(void)
400
+{
401
+ type_register_static(&sifive_pdma_info);
402
+}
403
+
404
+type_init(sifive_pdma_register_types)
405
diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
406
index XXXXXXX..XXXXXXX 100644
407
--- a/hw/dma/Kconfig
408
+++ b/hw/dma/Kconfig
409
@@ -XXX,XX +XXX,XX @@ config ZYNQ_DEVCFG
410
411
config STP2000
412
bool
413
+
414
+config SIFIVE_PDMA
415
+ bool
416
diff --git a/hw/dma/meson.build b/hw/dma/meson.build
417
index XXXXXXX..XXXXXXX 100644
418
--- a/hw/dma/meson.build
419
+++ b/hw/dma/meson.build
420
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
421
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
422
softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
423
softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
424
+softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c'))
425
--
159
--
426
2.28.0
160
2.35.1
427
428
diff view generated by jsdifflib
[PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
[PULL v2 28/31] target/riscv: machine: Add debug state description
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
3
Add a subsection to machine.c to migrate debug CSR state.
4
wires 4 of them out. Let's connect all 5 MMUARTs.
5
4
6
Signed-off-by: Bin Meng <bin.meng@windriver.com>
5
Signed-off-by: Bin Meng <bin.meng@windriver.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com>
7
Message-Id: <20220421003324.1134983-5-bmeng.cn@gmail.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
10
---
9
---
11
include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
10
target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++
12
hw/riscv/microchip_pfsoc.c | 30 ++++++++++++++++++++++++++++++
11
1 file changed, 32 insertions(+)
13
hw/riscv/Kconfig | 1 +
14
3 files changed, 51 insertions(+)
15
12
16
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
13
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/riscv/microchip_pfsoc.h
15
--- a/target/riscv/machine.c
19
+++ b/include/hw/riscv/microchip_pfsoc.h
16
+++ b/target/riscv/machine.c
20
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_kvmtimer = {
21
#ifndef HW_MICROCHIP_PFSOC_H
18
VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
22
#define HW_MICROCHIP_PFSOC_H
19
VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
23
20
VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
24
+#include "hw/char/mchp_pfsoc_mmuart.h"
21
+ VMSTATE_END_OF_LIST()
25
+
22
+ }
26
typedef struct MicrochipPFSoCState {
27
/*< private >*/
28
DeviceState parent_obj;
29
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
30
RISCVHartArrayState e_cpus;
31
RISCVHartArrayState u_cpus;
32
DeviceState *plic;
33
+ MchpPfSoCMMUartState *serial0;
34
+ MchpPfSoCMMUartState *serial1;
35
+ MchpPfSoCMMUartState *serial2;
36
+ MchpPfSoCMMUartState *serial3;
37
+ MchpPfSoCMMUartState *serial4;
38
} MicrochipPFSoCState;
39
40
#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
41
@@ -XXX,XX +XXX,XX @@ enum {
42
MICROCHIP_PFSOC_L2CC,
43
MICROCHIP_PFSOC_L2LIM,
44
MICROCHIP_PFSOC_PLIC,
45
+ MICROCHIP_PFSOC_MMUART0,
46
MICROCHIP_PFSOC_SYSREG,
47
MICROCHIP_PFSOC_MPUCFG,
48
+ MICROCHIP_PFSOC_MMUART1,
49
+ MICROCHIP_PFSOC_MMUART2,
50
+ MICROCHIP_PFSOC_MMUART3,
51
+ MICROCHIP_PFSOC_MMUART4,
52
MICROCHIP_PFSOC_ENVM_CFG,
53
MICROCHIP_PFSOC_ENVM_DATA,
54
MICROCHIP_PFSOC_IOSCB_CFG,
55
MICROCHIP_PFSOC_DRAM,
56
};
57
58
+enum {
59
+ MICROCHIP_PFSOC_MMUART0_IRQ = 90,
60
+ MICROCHIP_PFSOC_MMUART1_IRQ = 91,
61
+ MICROCHIP_PFSOC_MMUART2_IRQ = 92,
62
+ MICROCHIP_PFSOC_MMUART3_IRQ = 93,
63
+ MICROCHIP_PFSOC_MMUART4_IRQ = 94,
64
+};
23
+};
65
+
24
+
66
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
25
+static bool debug_needed(void *opaque)
67
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
26
+{
68
27
+ RISCVCPU *cpu = opaque;
69
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
28
+ CPURISCVState *env = &cpu->env;
70
index XXXXXXX..XXXXXXX 100644
71
--- a/hw/riscv/microchip_pfsoc.c
72
+++ b/hw/riscv/microchip_pfsoc.c
73
@@ -XXX,XX +XXX,XX @@
74
* 0) CLINT (Core Level Interruptor)
75
* 1) PLIC (Platform Level Interrupt Controller)
76
* 2) eNVM (Embedded Non-Volatile Memory)
77
+ * 3) MMUARTs (Multi-Mode UART)
78
*
79
* This board currently generates devicetree dynamically that indicates at least
80
* two harts and up to five harts.
81
@@ -XXX,XX +XXX,XX @@
82
#include "hw/irq.h"
83
#include "hw/loader.h"
84
#include "hw/sysbus.h"
85
+#include "chardev/char.h"
86
#include "hw/cpu/cluster.h"
87
#include "target/riscv/cpu.h"
88
#include "hw/misc/unimp.h"
89
@@ -XXX,XX +XXX,XX @@
90
#include "hw/riscv/sifive_clint.h"
91
#include "hw/riscv/sifive_plic.h"
92
#include "hw/riscv/microchip_pfsoc.h"
93
+#include "sysemu/sysemu.h"
94
95
/*
96
* The BIOS image used by this machine is called Hart Software Services (HSS).
97
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
98
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
99
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
100
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
101
+ [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
102
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
103
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
104
+ [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
105
+ [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
106
+ [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
107
+ [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
108
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
109
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
110
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
111
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
112
memmap[MICROCHIP_PFSOC_MPUCFG].base,
113
memmap[MICROCHIP_PFSOC_MPUCFG].size);
114
115
+ /* MMUARTs */
116
+ s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
117
+ memmap[MICROCHIP_PFSOC_MMUART0].base,
118
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
119
+ serial_hd(0));
120
+ s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
121
+ memmap[MICROCHIP_PFSOC_MMUART1].base,
122
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
123
+ serial_hd(1));
124
+ s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
125
+ memmap[MICROCHIP_PFSOC_MMUART2].base,
126
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
127
+ serial_hd(2));
128
+ s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
129
+ memmap[MICROCHIP_PFSOC_MMUART3].base,
130
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
131
+ serial_hd(3));
132
+ s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
133
+ memmap[MICROCHIP_PFSOC_MMUART4].base,
134
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
135
+ serial_hd(4));
136
+
29
+
137
/* eNVM */
30
+ return riscv_feature(env, RISCV_FEATURE_DEBUG);
138
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
31
+}
139
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
32
140
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
33
+static const VMStateDescription vmstate_debug_type2 = {
141
index XXXXXXX..XXXXXXX 100644
34
+ .name = "cpu/debug/type2",
142
--- a/hw/riscv/Kconfig
35
+ .version_id = 1,
143
+++ b/hw/riscv/Kconfig
36
+ .minimum_version_id = 1,
144
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
37
+ .fields = (VMStateField[]) {
145
select HART
38
+ VMSTATE_UINTTL(mcontrol, type2_trigger_t),
146
select SIFIVE
39
+ VMSTATE_UINTTL(maddress, type2_trigger_t),
147
select UNIMP
40
+ VMSTATE_END_OF_LIST()
148
+ select MCHP_PFSOC_MMUART
41
+ }
42
+};
43
+
44
+static const VMStateDescription vmstate_debug = {
45
+ .name = "cpu/debug",
46
+ .version_id = 1,
47
+ .minimum_version_id = 1,
48
+ .needed = debug_needed,
49
+ .fields = (VMStateField[]) {
50
+ VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
51
+ VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
52
+ 0, vmstate_debug_type2, type2_trigger_t),
53
VMSTATE_END_OF_LIST()
54
}
55
};
56
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
57
&vmstate_rv128,
58
&vmstate_kvmtimer,
59
&vmstate_envcfg,
60
+ &vmstate_debug,
61
NULL
62
}
63
};
149
--
64
--
150
2.28.0
65
2.35.1
151
152
diff view generated by jsdifflib
[PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers
[PULL v2 29/31] target/riscv: cpu: Enable native debug feature
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
3
Turn on native debug feature by default for all CPUs.
4
enough to create unimplemented devices to cover their register
5
spaces at this point.
6
7
With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
8
all the way to the Linux shell login prompt, with a modified HSS
9
(1st stage bootloader).
10
11
For detailed instructions on how to create images for the Icicle
12
Kit board, please check QEMU RISC-V WiKi page at:
13
https://wiki.qemu.org/Documentation/Platforms/RISCV
14
4
15
Signed-off-by: Bin Meng <bin.meng@windriver.com>
5
Signed-off-by: Bin Meng <bin.meng@windriver.com>
16
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-Id: <20220421003324.1134983-6-bmeng.cn@gmail.com>
18
Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com>
19
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
20
---
9
---
21
include/hw/riscv/microchip_pfsoc.h | 3 +++
10
target/riscv/cpu.c | 2 +-
22
hw/riscv/microchip_pfsoc.c | 14 ++++++++++++++
11
1 file changed, 1 insertion(+), 1 deletion(-)
23
2 files changed, 17 insertions(+)
24
12
25
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
13
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
26
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/riscv/microchip_pfsoc.h
15
--- a/target/riscv/cpu.c
28
+++ b/include/hw/riscv/microchip_pfsoc.h
16
+++ b/target/riscv/cpu.c
29
@@ -XXX,XX +XXX,XX @@ enum {
17
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
30
MICROCHIP_PFSOC_MMUART4,
18
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
31
MICROCHIP_PFSOC_GEM0,
19
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
32
MICROCHIP_PFSOC_GEM1,
20
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
33
+ MICROCHIP_PFSOC_GPIO0,
21
- DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
34
+ MICROCHIP_PFSOC_GPIO1,
22
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
35
+ MICROCHIP_PFSOC_GPIO2,
23
36
MICROCHIP_PFSOC_ENVM_CFG,
24
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
37
MICROCHIP_PFSOC_ENVM_DATA,
25
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
38
MICROCHIP_PFSOC_IOSCB_CFG,
39
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/riscv/microchip_pfsoc.c
42
+++ b/hw/riscv/microchip_pfsoc.c
43
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
44
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
45
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
46
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
47
+ [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
48
+ [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
49
+ [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
50
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
51
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
52
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
53
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
54
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
55
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
56
57
+ /* GPIOs */
58
+ create_unimplemented_device("microchip.pfsoc.gpio0",
59
+ memmap[MICROCHIP_PFSOC_GPIO0].base,
60
+ memmap[MICROCHIP_PFSOC_GPIO0].size);
61
+ create_unimplemented_device("microchip.pfsoc.gpio1",
62
+ memmap[MICROCHIP_PFSOC_GPIO1].base,
63
+ memmap[MICROCHIP_PFSOC_GPIO1].size);
64
+ create_unimplemented_device("microchip.pfsoc.gpio2",
65
+ memmap[MICROCHIP_PFSOC_GPIO2].base,
66
+ memmap[MICROCHIP_PFSOC_GPIO2].size);
67
+
68
/* eNVM */
69
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
70
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
71
--
26
--
72
2.28.0
27
2.35.1
73
74
diff view generated by jsdifflib
[PULL 25/30] hw/riscv: Move riscv_htif model to hw/char
[PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Bin Meng <bin.meng@windriver.com>
2
2
3
This is an effort to clean up the hw/riscv directory. Ideally it
3
This is now used by RISC-V as well. Update the comments.
4
should only contain the RISC-V SoC / machine codes plus generic
5
codes. Let's move riscv_htif model to hw/char directory.
6
4
7
Signed-off-by: Bin Meng <bin.meng@windriver.com>
5
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
8
Message-Id: <20220421003324.1134983-7-bmeng.cn@gmail.com>
10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11
---
10
---
12
include/hw/{riscv => char}/riscv_htif.h | 0
11
include/hw/core/tcg-cpu-ops.h | 1 +
13
hw/{riscv => char}/riscv_htif.c | 2 +-
12
1 file changed, 1 insertion(+)
14
hw/riscv/spike.c | 2 +-
15
hw/char/Kconfig | 3 +++
16
hw/char/meson.build | 1 +
17
hw/riscv/Kconfig | 3 ---
18
hw/riscv/meson.build | 1 -
19
7 files changed, 6 insertions(+), 6 deletions(-)
20
rename include/hw/{riscv => char}/riscv_htif.h (100%)
21
rename hw/{riscv => char}/riscv_htif.c (99%)
22
13
23
diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
14
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
24
similarity index 100%
25
rename from include/hw/riscv/riscv_htif.h
26
rename to include/hw/char/riscv_htif.h
27
diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
28
similarity index 99%
29
rename from hw/riscv/riscv_htif.c
30
rename to hw/char/riscv_htif.c
31
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/riscv/riscv_htif.c
16
--- a/include/hw/core/tcg-cpu-ops.h
33
+++ b/hw/char/riscv_htif.c
17
+++ b/include/hw/core/tcg-cpu-ops.h
34
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ struct TCGCPUOps {
35
#include "qapi/error.h"
19
/**
36
#include "qemu/log.h"
20
* @debug_check_watchpoint: return true if the architectural
37
#include "hw/sysbus.h"
21
* watchpoint whose address has matched should really fire, used by ARM
38
+#include "hw/char/riscv_htif.h"
22
+ * and RISC-V
39
#include "hw/char/serial.h"
23
*/
40
#include "chardev/char.h"
24
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
41
#include "chardev/char-fe.h"
42
-#include "hw/riscv/riscv_htif.h"
43
#include "qemu/timer.h"
44
#include "qemu/error-report.h"
45
46
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/riscv/spike.c
49
+++ b/hw/riscv/spike.c
50
@@ -XXX,XX +XXX,XX @@
51
#include "hw/loader.h"
52
#include "hw/sysbus.h"
53
#include "target/riscv/cpu.h"
54
-#include "hw/riscv/riscv_htif.h"
55
#include "hw/riscv/riscv_hart.h"
56
#include "hw/riscv/spike.h"
57
#include "hw/riscv/boot.h"
58
#include "hw/riscv/numa.h"
59
+#include "hw/char/riscv_htif.h"
60
#include "hw/intc/sifive_clint.h"
61
#include "chardev/char.h"
62
#include "sysemu/arch_init.h"
63
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/char/Kconfig
66
+++ b/hw/char/Kconfig
67
@@ -XXX,XX +XXX,XX @@
68
config ESCC
69
bool
70
71
+config HTIF
72
+ bool
73
+
74
config PARALLEL
75
bool
76
default y
77
diff --git a/hw/char/meson.build b/hw/char/meson.build
78
index XXXXXXX..XXXXXXX 100644
79
--- a/hw/char/meson.build
80
+++ b/hw/char/meson.build
81
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
82
softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
83
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
84
85
+specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
86
specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
87
specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
88
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
89
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
90
index XXXXXXX..XXXXXXX 100644
91
--- a/hw/riscv/Kconfig
92
+++ b/hw/riscv/Kconfig
93
@@ -XXX,XX +XXX,XX @@
94
-config HTIF
95
- bool
96
-
97
config HART
98
bool
99
100
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
101
index XXXXXXX..XXXXXXX 100644
102
--- a/hw/riscv/meson.build
103
+++ b/hw/riscv/meson.build
104
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
105
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
106
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
107
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
108
-riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
109
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
110
riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
111
25
112
--
26
--
113
2.28.0
27
2.35.1
114
115
diff view generated by jsdifflib
[PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property
[PULL v2 31/31] hw/riscv: boot: Support 64bit fdt address.
1
From: Bin Meng <bin.meng@windriver.com>
1
From: Dylan Jhong <dylan@andestech.com>
2
2
3
At present the PHY address of the PHY connected to GEM is hard-coded
3
The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram address within 3GB,
4
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
4
but not all platforms have dram_base within 3GB.
5
all boards. Add a new 'phy-addr' property so that board can specify
6
the PHY address for each GEM instance.
7
5
8
Signed-off-by: Bin Meng <bin.meng@windriver.com>
6
This patch adds an exception for dram base not within 3GB,
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
which will place fdt at dram_end align 16MB.
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
9
riscv_setup_rom_reset_vec() also needs to be modified
10
11
Signed-off-by: Dylan Jhong <dylan@andestech.com>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
13
Message-Id: <20220419115945.37945-1-dylan@andestech.com>
13
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
14
---
15
---
15
include/hw/net/cadence_gem.h | 2 ++
16
include/hw/riscv/boot.h | 4 ++--
16
hw/net/cadence_gem.c | 5 +++--
17
hw/riscv/boot.c | 12 +++++++-----
17
2 files changed, 5 insertions(+), 2 deletions(-)
18
2 files changed, 9 insertions(+), 7 deletions(-)
18
19
19
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
20
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
20
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/net/cadence_gem.h
22
--- a/include/hw/riscv/boot.h
22
+++ b/include/hw/net/cadence_gem.h
23
+++ b/include/hw/riscv/boot.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
24
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_load_kernel(const char *kernel_filename,
24
/* Mask of register bits which are write 1 to clear */
25
symbol_fn_t sym_cb);
25
uint32_t regs_w1c[CADENCE_GEM_MAXREG];
26
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
26
27
uint64_t kernel_entry, hwaddr *start);
27
+ /* PHY address */
28
-uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
28
+ uint8_t phy_addr;
29
+uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
29
/* PHY registers backing store */
30
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
30
uint16_t phy_regs[32];
31
hwaddr saddr,
31
32
hwaddr rom_base, hwaddr rom_size,
32
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
33
uint64_t kernel_entry,
34
- uint32_t fdt_load_addr, void *fdt);
35
+ uint64_t fdt_load_addr, void *fdt);
36
void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
37
hwaddr rom_size,
38
uint32_t reset_vec_size,
39
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
33
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/net/cadence_gem.c
41
--- a/hw/riscv/boot.c
35
+++ b/hw/net/cadence_gem.c
42
+++ b/hw/riscv/boot.c
36
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
43
@@ -XXX,XX +XXX,XX @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
37
uint32_t phy_addr, reg_num;
44
return *start + size;
38
45
}
39
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
46
40
- if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
47
-uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
41
+ if (phy_addr == s->phy_addr || phy_addr == 0) {
48
+uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
42
reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
49
{
43
retval &= 0xFFFF0000;
50
- uint32_t temp, fdt_addr;
44
retval |= gem_phy_read(s, reg_num);
51
+ uint64_t temp, fdt_addr;
45
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
52
hwaddr dram_end = dram_base + mem_size;
46
uint32_t phy_addr, reg_num;
53
int ret, fdtsize = fdt_totalsize(fdt);
47
54
48
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
55
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
49
- if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
56
* Thus, put it at an 16MB aligned address that less than fdt size from the
50
+ if (phy_addr == s->phy_addr || phy_addr == 0) {
57
* end of dram or 3GB whichever is lesser.
51
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
58
*/
52
gem_phy_write(s, reg_num, val);
59
- temp = MIN(dram_end, 3072 * MiB);
53
}
60
+ temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
54
@@ -XXX,XX +XXX,XX @@ static Property gem_properties[] = {
61
fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
55
DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
62
56
DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
63
ret = fdt_pack(fdt);
57
GEM_MODID_VALUE),
64
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
58
+ DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
65
hwaddr start_addr,
59
DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
66
hwaddr rom_base, hwaddr rom_size,
60
num_priority_queues, 1),
67
uint64_t kernel_entry,
61
DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
68
- uint32_t fdt_load_addr, void *fdt)
69
+ uint64_t fdt_load_addr, void *fdt)
70
{
71
int i;
72
uint32_t start_addr_hi32 = 0x00000000;
73
+ uint32_t fdt_load_addr_hi32 = 0x00000000;
74
75
if (!riscv_is_32bit(harts)) {
76
start_addr_hi32 = start_addr >> 32;
77
+ fdt_load_addr_hi32 = fdt_load_addr >> 32;
78
}
79
/* reset vector */
80
uint32_t reset_vec[10] = {
81
@@ -XXX,XX +XXX,XX @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
82
start_addr, /* start: .dword */
83
start_addr_hi32,
84
fdt_load_addr, /* fdt_laddr: .dword */
85
- 0x00000000,
86
+ fdt_load_addr_hi32,
87
/* fw_dyn: */
88
};
89
if (riscv_is_32bit(harts)) {
62
--
90
--
63
2.28.0
91
2.35.1
64
65
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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