[PULL 00/30] riscv-to-apply queue
[PULL 0/2] riscv-to-apply queue
1
The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:
1
From: Alistair Francis <alistair.francis@wdc.com>
2
2
3
Merge remote-tracking branch 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging (2020-09-08 21:21:13 +0100)
3
The following changes since commit c5fbdd60cf1fb52f01bdfe342b6fa65d5343e1b1:
4
5
Merge tag 'qemu-sparc-20211121' of git://github.com/mcayland/qemu into staging (2021-11-21 14:12:25 +0100)
4
6
5
are available in the Git repository at:
7
are available in the Git repository at:
6
8
7
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
9
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211122
8
10
9
for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:
11
for you to fetch changes up to 526e7443027c71fe7b04c29df529e1f9f425f9e3:
10
12
11
hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19 -0700)
13
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset (2021-11-22 10:46:22 +1000)
12
14
13
----------------------------------------------------------------
15
----------------------------------------------------------------
14
This PR includes multiple fixes and features for RISC-V:
16
Seventh RISC-V PR for QEMU 6.2
15
- Fixes a bug in printing trap causes
17
16
- Allows 16-bit writes to the SiFive test device. This fixes the
18
- Deprecate IF_NONE for SiFive OTP
17
failure to reboot the RISC-V virt machine
19
- Don't reset SiFive OTP content
18
- Support for the Microchip PolarFire SoC and Icicle Kit
19
- A reafactor of RISC-V code out of hw/riscv
20
20
21
----------------------------------------------------------------
21
----------------------------------------------------------------
22
Bin Meng (28):
22
Philippe Mathieu-Daudé (1):
23
target/riscv: cpu: Add a new 'resetvec' property
23
hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
24
hw/riscv: hart: Add a new 'resetvec' property
25
target/riscv: cpu: Set reset vector based on the configured property value
26
hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
27
hw/char: Add Microchip PolarFire SoC MMUART emulation
28
hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
29
hw/sd: Add Cadence SDHCI emulation
30
hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
31
hw/dma: Add SiFive platform DMA controller emulation
32
hw/riscv: microchip_pfsoc: Connect a DMA controller
33
hw/net: cadence_gem: Add a new 'phy-addr' property
34
hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
35
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
36
hw/riscv: microchip_pfsoc: Hook GPIO controllers
37
hw/riscv: clint: Avoid using hard-coded timebase frequency
38
hw/riscv: sifive_u: Connect a DMA controller
39
hw/riscv: Move sifive_e_prci model to hw/misc
40
hw/riscv: Move sifive_u_prci model to hw/misc
41
hw/riscv: Move sifive_u_otp model to hw/misc
42
hw/riscv: Move sifive_gpio model to hw/gpio
43
hw/riscv: Move sifive_clint model to hw/intc
44
hw/riscv: Move sifive_plic model to hw/intc
45
hw/riscv: Move riscv_htif model to hw/char
46
hw/riscv: Move sifive_uart model to hw/char
47
hw/riscv: Move sifive_test model to hw/misc
48
hw/riscv: Always build riscv_hart.c
49
hw/riscv: Drop CONFIG_SIFIVE
50
hw/riscv: Sort the Kconfig options in alphabetical order
51
24
52
Nathan Chancellor (1):
25
Thomas Huth (1):
53
riscv: sifive_test: Allow 16-bit writes to memory region
26
hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
54
27
55
Yifei Jiang (1):
28
docs/about/deprecated.rst | 6 ++++++
56
target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
29
hw/misc/sifive_u_otp.c | 22 +++++++++++++---------
30
2 files changed, 19 insertions(+), 9 deletions(-)
57
31
58
default-configs/riscv64-softmmu.mak | 1 +
59
{include/hw/riscv => hw/intc}/sifive_plic.h | 0
60
hw/riscv/trace.h | 1 -
61
include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++
62
include/hw/{riscv => char}/riscv_htif.h | 0
63
include/hw/{riscv => char}/sifive_uart.h | 0
64
include/hw/dma/sifive_pdma.h | 57 ++++
65
include/hw/{riscv => gpio}/sifive_gpio.h | 0
66
include/hw/{riscv => intc}/sifive_clint.h | 4 +-
67
include/hw/{riscv => misc}/sifive_e_prci.h | 0
68
include/hw/{riscv => misc}/sifive_test.h | 0
69
include/hw/{riscv => misc}/sifive_u_otp.h | 0
70
include/hw/{riscv => misc}/sifive_u_prci.h | 0
71
include/hw/net/cadence_gem.h | 2 +
72
include/hw/riscv/microchip_pfsoc.h | 133 +++++++++
73
include/hw/riscv/riscv_hart.h | 1 +
74
include/hw/riscv/sifive_e.h | 2 +-
75
include/hw/riscv/sifive_u.h | 17 +-
76
include/hw/sd/cadence_sdhci.h | 47 +++
77
target/riscv/cpu.h | 8 +-
78
hw/arm/xilinx_zynq.c | 1 +
79
hw/arm/xlnx-versal.c | 1 +
80
hw/arm/xlnx-zynqmp.c | 2 +
81
hw/char/mchp_pfsoc_mmuart.c | 86 ++++++
82
hw/{riscv => char}/riscv_htif.c | 2 +-
83
hw/{riscv => char}/sifive_uart.c | 2 +-
84
hw/dma/sifive_pdma.c | 313 ++++++++++++++++++++
85
hw/{riscv => gpio}/sifive_gpio.c | 2 +-
86
hw/{riscv => intc}/sifive_clint.c | 28 +-
87
hw/{riscv => intc}/sifive_plic.c | 2 +-
88
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
89
hw/{riscv => misc}/sifive_test.c | 4 +-
90
hw/{riscv => misc}/sifive_u_otp.c | 2 +-
91
hw/{riscv => misc}/sifive_u_prci.c | 2 +-
92
hw/net/cadence_gem.c | 7 +-
93
hw/riscv/microchip_pfsoc.c | 437 ++++++++++++++++++++++++++++
94
hw/riscv/opentitan.c | 1 +
95
hw/riscv/riscv_hart.c | 3 +
96
hw/riscv/sifive_e.c | 12 +-
97
hw/riscv/sifive_u.c | 41 ++-
98
hw/riscv/spike.c | 7 +-
99
hw/riscv/virt.c | 9 +-
100
hw/sd/cadence_sdhci.c | 193 ++++++++++++
101
target/riscv/cpu.c | 19 +-
102
target/riscv/cpu_helper.c | 8 +-
103
target/riscv/csr.c | 4 +-
104
MAINTAINERS | 9 +
105
hw/char/Kconfig | 9 +
106
hw/char/meson.build | 3 +
107
hw/dma/Kconfig | 3 +
108
hw/dma/meson.build | 1 +
109
hw/gpio/Kconfig | 3 +
110
hw/gpio/meson.build | 1 +
111
hw/gpio/trace-events | 6 +
112
hw/intc/Kconfig | 6 +
113
hw/intc/meson.build | 2 +
114
hw/misc/Kconfig | 12 +
115
hw/misc/meson.build | 6 +
116
hw/riscv/Kconfig | 70 +++--
117
hw/riscv/meson.build | 12 +-
118
hw/riscv/trace-events | 7 -
119
hw/sd/Kconfig | 4 +
120
hw/sd/meson.build | 1 +
121
meson.build | 1 -
122
64 files changed, 1575 insertions(+), 105 deletions(-)
123
rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
124
delete mode 100644 hw/riscv/trace.h
125
create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
126
rename include/hw/{riscv => char}/riscv_htif.h (100%)
127
rename include/hw/{riscv => char}/sifive_uart.h (100%)
128
create mode 100644 include/hw/dma/sifive_pdma.h
129
rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
130
rename include/hw/{riscv => intc}/sifive_clint.h (92%)
131
rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
132
rename include/hw/{riscv => misc}/sifive_test.h (100%)
133
rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
134
rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
135
create mode 100644 include/hw/riscv/microchip_pfsoc.h
136
create mode 100644 include/hw/sd/cadence_sdhci.h
137
create mode 100644 hw/char/mchp_pfsoc_mmuart.c
138
rename hw/{riscv => char}/riscv_htif.c (99%)
139
rename hw/{riscv => char}/sifive_uart.c (99%)
140
create mode 100644 hw/dma/sifive_pdma.c
141
rename hw/{riscv => gpio}/sifive_gpio.c (99%)
142
rename hw/{riscv => intc}/sifive_clint.c (90%)
143
rename hw/{riscv => intc}/sifive_plic.c (99%)
144
rename hw/{riscv => misc}/sifive_e_prci.c (99%)
145
rename hw/{riscv => misc}/sifive_test.c (97%)
146
rename hw/{riscv => misc}/sifive_u_otp.c (99%)
147
rename hw/{riscv => misc}/sifive_u_prci.c (99%)
148
create mode 100644 hw/riscv/microchip_pfsoc.c
149
create mode 100644 hw/sd/cadence_sdhci.c
150
delete mode 100644 hw/riscv/trace-events
151
diff view generated by jsdifflib
New patch
[PULL 1/2] hw/misc/sifive_u_otp: Use IF_PFLASH for the OTP device instead of IF_NONE
1
From: Thomas Huth <thuth@redhat.com>
1
2
3
Configuring a drive with "if=none" is meant for creation of a backend
4
only, it should not get automatically assigned to a device frontend.
5
Use "if=pflash" for the One-Time-Programmable device instead (like
6
it is e.g. also done for the efuse device in hw/arm/xlnx-zcu102.c).
7
8
Since the old way of configuring the device has already been published
9
with the previous QEMU versions, we cannot remove this immediately, but
10
have to deprecate it and support it for at least two more releases.
11
12
Signed-off-by: Thomas Huth <thuth@redhat.com>
13
Acked-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Markus Armbruster <armbru@redhat.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20211119102549.217755-1-thuth@redhat.com
17
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
18
---
19
docs/about/deprecated.rst | 6 ++++++
20
hw/misc/sifive_u_otp.c | 9 ++++++++-
21
2 files changed, 14 insertions(+), 1 deletion(-)
22
23
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
24
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/about/deprecated.rst
26
+++ b/docs/about/deprecated.rst
27
@@ -XXX,XX +XXX,XX @@ as short-form boolean values, and passed to plugins as ``arg_name=on``.
28
However, short-form booleans are deprecated and full explicit ``arg_name=on``
29
form is preferred.
30
31
+``-drive if=none`` for the sifive_u OTP device (since 6.2)
32
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
33
+
34
+Using ``-drive if=none`` to configure the OTP device of the sifive_u
35
+RISC-V machine is deprecated. Use ``-drive if=pflash`` instead.
36
+
37
38
QEMU Machine Protocol (QMP) commands
39
------------------------------------
40
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/misc/sifive_u_otp.c
43
+++ b/hw/misc/sifive_u_otp.c
44
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
45
TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE);
46
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
47
48
- dinfo = drive_get_next(IF_NONE);
49
+ dinfo = drive_get_next(IF_PFLASH);
50
+ if (!dinfo) {
51
+ dinfo = drive_get_next(IF_NONE);
52
+ if (dinfo) {
53
+ warn_report("using \"-drive if=none\" for the OTP is deprecated, "
54
+ "use \"-drive if=pflash\" instead.");
55
+ }
56
+ }
57
if (dinfo) {
58
int ret;
59
uint64_t perm;
60
--
61
2.31.1
62
63
diff view generated by jsdifflib
New patch
[PULL 2/2] hw/misc/sifive_u_otp: Do not reset OTP content on hardware reset
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Once a "One Time Programmable" is programmed, it shouldn't be reset.
4
5
Do not re-initialize the OTP content in the DeviceReset handler,
6
initialize it once in the DeviceRealize one.
7
8
Fixes: 9fb45c62ae8 ("riscv: sifive: Implement a model for SiFive FU540 OTP")
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-Id: <20211119104757.331579-1-f4bug@amsat.org>
12
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
13
---
14
hw/misc/sifive_u_otp.c | 13 +++++--------
15
1 file changed, 5 insertions(+), 8 deletions(-)
16
17
diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/sifive_u_otp.c
20
+++ b/hw/misc/sifive_u_otp.c
21
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp)
22
23
if (blk_pread(s->blk, 0, s->fuse, filesize) != filesize) {
24
error_setg(errp, "failed to read the initial flash content");
25
+ return;
26
}
27
}
28
}
29
-}
30
-
31
-static void sifive_u_otp_reset(DeviceState *dev)
32
-{
33
- SiFiveUOTPState *s = SIFIVE_U_OTP(dev);
34
35
/* Initialize all fuses' initial value to 0xFFs */
36
memset(s->fuse, 0xff, sizeof(s->fuse));
37
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_reset(DeviceState *dev)
38
serial_data = s->serial;
39
if (blk_pwrite(s->blk, index * SIFIVE_U_OTP_FUSE_WORD,
40
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
41
- error_report("write error index<%d>", index);
42
+ error_setg(errp, "failed to write index<%d>", index);
43
+ return;
44
}
45
46
serial_data = ~(s->serial);
47
if (blk_pwrite(s->blk, (index + 1) * SIFIVE_U_OTP_FUSE_WORD,
48
&serial_data, SIFIVE_U_OTP_FUSE_WORD, 0) < 0) {
49
- error_report("write error index<%d>", index + 1);
50
+ error_setg(errp, "failed to write index<%d>", index + 1);
51
+ return;
52
}
53
}
54
55
@@ -XXX,XX +XXX,XX @@ static void sifive_u_otp_class_init(ObjectClass *klass, void *data)
56
57
device_class_set_props(dc, sifive_u_otp_properties);
58
dc->realize = sifive_u_otp_realize;
59
- dc->reset = sifive_u_otp_reset;
60
}
61
62
static const TypeInfo sifive_u_otp_info = {
63
--
64
2.31.1
65
66
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.