The mx25l25635e returns the JEDEC ID twice when issuing a RDID command :

[ 2.512027] aspeed-smc 1e630000.spi: reading JEDEC ID C2:20:19:C2:20:19

This can break some firmware testing for this condition on the

supermicrox11-bmc machine.

Reported-by: Erik Smit <erik.lucas.smit@gmail.com>

Message-Id: <20200819100956.2216690-2-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/block/m25p80.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/block/m25p80.c

+++ b/hw/block/m25p80.c

@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {

{ INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },

{ INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },

{ INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },

- { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },

+ { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) },

{ INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },

{ INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },

{ INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },

--

2.25.4

Datasheet available here :

https://www.micron.com/-/media/client/global/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_512mb_1ce_3v_65nm.pdf

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-4-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/block/m25p80.c | 1 +

1 file changed, 1 insertion(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/block/m25p80.c

+++ b/hw/block/m25p80.c

@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {

{ INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },

{ INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },

{ INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },

+ { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },

{ INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },

{ INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },

{ INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },

--

2.25.4

The read access size of the SCU registers can be 1/2/4 bytes and write

is 4 bytes and all Aspeed models would need a .valid.accepts() handler.

For the moment, set the min access size to 1 byte to cover both read

and write operations on the AST2400 but keep the min access size of

the other SoCs to 4 bytes as this is an unusual access size.

This fixes support for some old firmware doing 2 bytes reads on the

AST2400 SoC.

Reported-by: Erik Smit <erik.lucas.smit@gmail.com>

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-5-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/misc/aspeed_scu.c | 7 ++++---

1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_scu.c

+++ b/hw/misc/aspeed_scu.c

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_ast2400_scu_ops = {

.read = aspeed_scu_read,

.write = aspeed_ast2400_scu_write,

.endianness = DEVICE_LITTLE_ENDIAN,

- .valid.min_access_size = 4,

- .valid.max_access_size = 4,

- .valid.unaligned = false,

+ .valid = {

+ .min_access_size = 1,

+ .max_access_size = 4,

+ },

};

static const MemoryRegionOps aspeed_ast2500_scu_ops = {

--

2.25.4

Unaligned access support is a leftover from the initial commit. There

is no such need on this device register mapping. Remove it.

Cc: Michael S. Tsirkin <mst@redhat.com>

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-7-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/ssi/aspeed_smc.c | 2 --

1 file changed, 2 deletions(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/ssi/aspeed_smc.c

+++ b/hw/ssi/aspeed_smc.c

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_smc_ops = {

.read = aspeed_smc_read,

.write = aspeed_smc_write,

.endianness = DEVICE_LITTLE_ENDIAN,

- .valid.unaligned = true,

};

-

/*

* Initialize the custom address spaces for DMAs

*/

--

2.25.4

The legacy controller only has one slave.

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-8-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/ssi/aspeed_smc.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/ssi/aspeed_smc.c

+++ b/hw/ssi/aspeed_smc.c

@@ -XXX,XX +XXX,XX @@ static const AspeedSMCController controllers[] = {

.r_timings = R_TIMINGS,

.nregs_timings = 1,

.conf_enable_w0 = CONF_ENABLE_W0,

- .max_slaves = 5,

+ .max_slaves = 1,

.segments = aspeed_segments_legacy,

.flash_window_base = ASPEED_SOC_SMC_FLASH_BASE,

.flash_window_size = 0x6000000,

--

2.25.4

BIT(0) of the ASPEED_SDHCI_INFO register is set by SW and polled until

the bit is cleared by HW.

Use the number of supported slots to define the default value of this

register (The AST2600 eMMC Controller only has one). Fix the reset

sequence by clearing automatically the RESET bit.

Cc: Eddie James <eajames@linux.ibm.com>

Fixes: 2bea128c3d0b ("hw/sd/aspeed_sdhci: New device")

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-9-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/sd/aspeed_sdhci.c | 14 ++++++++++++--

1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/sd/aspeed_sdhci.c

+++ b/hw/sd/aspeed_sdhci.c

@@ -XXX,XX +XXX,XX @@

#include "hw/qdev-properties.h"

#define ASPEED_SDHCI_INFO 0x00

-#define ASPEED_SDHCI_INFO_RESET 0x00030000

+#define ASPEED_SDHCI_INFO_SLOT1 (1 << 17)

+#define ASPEED_SDHCI_INFO_SLOT0 (1 << 16)

+#define ASPEED_SDHCI_INFO_RESET (1 << 0)

#define ASPEED_SDHCI_DEBOUNCE 0x04

#define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005

#define ASPEED_SDHCI_BUS 0x08

@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val,

AspeedSDHCIState *sdhci = opaque;

switch (addr) {

+ case ASPEED_SDHCI_INFO:

+ /* The RESET bit automatically clears. */

+ sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET;

+ break;

case ASPEED_SDHCI_SDIO_140:

sdhci->slots[0].capareg = (uint64_t)(uint32_t)val;

break;

@@ -XXX,XX +XXX,XX @@ static void aspeed_sdhci_reset(DeviceState *dev)

AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev);

memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE);

- sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_RESET;

+

+ sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0;

+ if (sdhci->num_slots == 2) {

+ sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1;

+ }

sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET;

}

--

2.25.4

Receive Ring Base Address Register (RXR_BADR) and the Normal Priority

Transmit Receive Ring Base Address Register (NPTXR_BADR) can also be

read.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-10-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/net/ftgmac100.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/net/ftgmac100.c

+++ b/hw/net/ftgmac100.c

@@ -XXX,XX +XXX,XX @@ static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)

return s->math[0];

case FTGMAC100_MATH1:

return s->math[1];

+ case FTGMAC100_RXR_BADR:

+ return s->rx_ring;

+ case FTGMAC100_NPTXR_BADR:

+ return s->tx_ring;

case FTGMAC100_ITC:

return s->itc;

case FTGMAC100_DBLAC:

--

2.25.4

The second field of the TX descriptor has a set of flags to choose

when the transmit interrupt is raised : after the packet has been sent

on the ethernet or after it has been moved into the TX FIFO. But we

don't model that today.

Simply raise the "Packet transmitted on ethernet" interrupt status bit

as soon as the packet is sent by QEMU.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-11-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/net/ftgmac100.c | 4 +---

1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/net/ftgmac100.c

+++ b/hw/net/ftgmac100.c

@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,

qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);

ptr = s->frame;

frame_size = 0;

- if (flags & FTGMAC100_TXDES1_TXIC) {

- s->isr |= FTGMAC100_INT_XPKT_ETH;

- }

+ s->isr |= FTGMAC100_INT_XPKT_ETH;

}

if (flags & FTGMAC100_TXDES1_TX2FIC) {

--

2.25.4

The model uses today the "Normal priority transmit buffer unavailable"

interrupt status which it is not appropriate. According to the Aspeed

specs, no interrupts are raised in that case. An "AHB error" status

seems like a better modeling choice for all implementations since it

is covered by the Linux kernel.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-13-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/net/ftgmac100.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/net/ftgmac100.c

+++ b/hw/net/ftgmac100.c

@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,

if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {

qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",

__func__, bd.des3);

- s->isr |= FTGMAC100_INT_NO_NPTXBUF;

+ s->isr |= FTGMAC100_INT_AHB_ERR;

break;

}

--

2.25.4

According to the Aspeed specs, no interrupts are raised in that case

but a "Tx-packets lost" status seems like a good modeling choice for

all implementations. It is covered by the Linux kernel.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-14-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/net/ftgmac100.c | 9 +++++++++

1 file changed, 9 insertions(+)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/net/ftgmac100.c

+++ b/hw/net/ftgmac100.c

@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,

}

len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);

+ if (!len) {

+ /*

+ * 0 is an invalid size, however the HW does not raise any

+ * interrupt. Flag an error because the guest is buggy.

+ */

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid segment size\n",

+ __func__);

+ }

+

if (frame_size + len > sizeof(s->frame)) {

qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",

__func__, len);

--

2.25.4

When inserting the VLAN tag in packets, memmove() can generate an

integer overflow for packets whose length is less than 12 bytes.

Move the VLAN insertion when the last segment of the frame is reached

and check length against the size of the ethernet header (14 bytes) to

avoid the crash. Return FTGMAC100_INT_XPKT_LOST status if the frame is

too small. This seems like a good modeling choice even if Aspeed does

not specify anything in that case.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>

Cc: Mauro Matteo Cascella <mcascell@redhat.com>

Reported-by: Ziming Zhang <ezrakiez@gmail.com>

Message-Id: <20200819100956.2216690-15-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/net/ftgmac100.c | 55 ++++++++++++++++++++++++++++++++--------------

1 file changed, 39 insertions(+), 16 deletions(-)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/net/ftgmac100.c

+++ b/hw/net/ftgmac100.c

@@ -XXX,XX +XXX,XX @@ static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)

return 0;

}

+static int ftgmac100_insert_vlan(FTGMAC100State *s, int frame_size,

+ uint8_t vlan_tci)

+{

+ uint8_t *vlan_hdr = s->frame + (ETH_ALEN * 2);

+ uint8_t *payload = vlan_hdr + sizeof(struct vlan_header);

+

+ if (frame_size < sizeof(struct eth_header)) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: frame too small for VLAN insertion : %d bytes\n",

+ __func__, frame_size);

+ s->isr |= FTGMAC100_INT_XPKT_LOST;

+ goto out;

+ }

+

+ if (frame_size + sizeof(struct vlan_header) > sizeof(s->frame)) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: frame too big : %d bytes\n",

+ __func__, frame_size);

+ s->isr |= FTGMAC100_INT_XPKT_LOST;

+ frame_size -= sizeof(struct vlan_header);

+ }

+

+ memmove(payload, vlan_hdr, frame_size - (ETH_ALEN * 2));

+ stw_be_p(vlan_hdr, ETH_P_VLAN);

+ stw_be_p(vlan_hdr + 2, vlan_tci);

+ frame_size += sizeof(struct vlan_header);

+

+out:

+ return frame_size;

+}

+

static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,

uint32_t tx_descriptor)

{

@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,

break;

}

- /* Check for VLAN */

- if (bd.des0 & FTGMAC100_TXDES0_FTS &&

- bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG &&

- be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) {

- if (frame_size + len + 4 > sizeof(s->frame)) {

- qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",

- __func__, len);

- s->isr |= FTGMAC100_INT_XPKT_LOST;

- len = sizeof(s->frame) - frame_size - 4;

- }

- memmove(ptr + 16, ptr + 12, len - 12);

- stw_be_p(ptr + 12, ETH_P_VLAN);

- stw_be_p(ptr + 14, bd.des1);

- len += 4;

- }

-

ptr += len;

frame_size += len;

if (bd.des0 & FTGMAC100_TXDES0_LTS) {

+

+ /* Check for VLAN */

+ if (flags & FTGMAC100_TXDES1_INS_VLANTAG &&

+ be16_to_cpu(PKT_GET_ETH_HDR(s->frame)->h_proto) != ETH_P_VLAN) {

+ frame_size = ftgmac100_insert_vlan(s, frame_size,

+ FTGMAC100_TXDES1_VLANTAG_CI(flags));

+ }

+

if (flags & FTGMAC100_TXDES1_IP_CHKSUM) {

net_checksum_calculate(s->frame, frame_size);

}

--

2.25.4

The software reset of the MAC needs a finer granularity. Some settings

in MACCR are kept.

Cc: Frederic Konrad <konrad.frederic@yahoo.fr>

Fixes: bd44300d1afc ("net: add FTGMAC100 support")

Message-Id: <20200819100956.2216690-16-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/net/ftgmac100.c | 18 +++++++++++++-----

1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/net/ftgmac100.c

+++ b/hw/net/ftgmac100.c

@@ -XXX,XX +XXX,XX @@ static uint32_t ftgmac100_rxpoll(FTGMAC100State *s)

return cnt / div[speed];

}

-static void ftgmac100_reset(DeviceState *d)

+static void ftgmac100_do_reset(FTGMAC100State *s, bool sw_reset)

{

- FTGMAC100State *s = FTGMAC100(d);

-

/* Reset the FTGMAC100 */

s->isr = 0;

s->ier = 0;

@@ -XXX,XX +XXX,XX @@ static void ftgmac100_reset(DeviceState *d)

s->fear1 = 0;

s->tpafcr = 0xf1;

- s->maccr = 0;

+ if (sw_reset) {

+ s->maccr &= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FAST_MODE;

+ } else {

+ s->maccr = 0;

+ }

+

s->phycr = 0;

s->phydata = 0;

s->fcr = 0x400;

@@ -XXX,XX +XXX,XX @@ static void ftgmac100_reset(DeviceState *d)

phy_reset(s);

}

+static void ftgmac100_reset(DeviceState *d)

+{

+ ftgmac100_do_reset(FTGMAC100(d), false);

+}

+

static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)

{

FTGMAC100State *s = FTGMAC100(opaque);

@@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr,

case FTGMAC100_MACCR: /* MAC Device control */

s->maccr = value;

if (value & FTGMAC100_MACCR_SW_RST) {

- ftgmac100_reset(DEVICE(s));

+ ftgmac100_do_reset(s, true);

}

if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {

--

2.25.4

From: Joel Stanley <joel@jms.id.au>

A subset of registers are not protected by the lock behaviour, so allow

unconditionally writing to those.

Signed-off-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-18-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/misc/aspeed_sdmc.c | 27 +++++++++++++++++++++++++++

1 file changed, 27 insertions(+)

diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_sdmc.c

+++ b/hw/misc/aspeed_sdmc.c

@@ -XXX,XX +XXX,XX @@

/* Configuration Register */

#define R_CONF (0x04 / 4)

+/* Interrupt control/status */

+#define R_ISR (0x50 / 4)

+

/* Control/Status Register #1 (ast2500) */

#define R_STATUS1 (0x60 / 4)

#define PHY_BUSY_STATE BIT(0)

#define PHY_PLL_LOCK_STATUS BIT(4)

+/* Reserved */

+#define R_MCR6C (0x6c / 4)

+

#define R_ECC_TEST_CTRL (0x70 / 4)

#define ECC_TEST_FINISHED BIT(12)

#define ECC_TEST_FAIL BIT(13)

+#define R_TEST_START_LEN (0x74 / 4)

+#define R_TEST_FAIL_DQ (0x78 / 4)

+#define R_TEST_INIT_VAL (0x7c / 4)

+#define R_DRAM_SW (0x88 / 4)

+#define R_DRAM_TIME (0x8c / 4)

+#define R_ECC_ERR_INJECT (0xb4 / 4)

+

/*

* Configuration register Ox4 (for Aspeed AST2400 SOC)

*

@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)

static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,

uint32_t data)

{

+ /* Unprotected registers */

+ switch (reg) {

+ case R_ISR:

+ case R_MCR6C:

+ case R_TEST_START_LEN:

+ case R_TEST_FAIL_DQ:

+ case R_TEST_INIT_VAL:

+ case R_DRAM_SW:

+ case R_DRAM_TIME:

+ case R_ECC_ERR_INJECT:

+ s->regs[reg] = data;

+ return;

+ }

+

if (s->regs[R_PROT] == PROT_HARDLOCKED) {

qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked until system reset!\n",

__func__);

--

2.25.4

Changes in commit 533eb415df2e ("arm/aspeed: actually check RAM size")

introduced a 'valid_ram_sizes' array which can be used to compute the

associated bit field value encoding the RAM size. The field is simply

the index of the array.

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-19-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/misc/aspeed_sdmc.c | 79 ++++++++++++++-----------------------------

1 file changed, 25 insertions(+), 54 deletions(-)

diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/aspeed_sdmc.c

+++ b/hw/misc/aspeed_sdmc.c

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_sdmc_ops = {

.valid.max_access_size = 4,

};

-static int ast2400_rambits(AspeedSDMCState *s)

-{

- switch (s->ram_size >> 20) {

- case 64:

- return ASPEED_SDMC_DRAM_64MB;

- case 128:

- return ASPEED_SDMC_DRAM_128MB;

- case 256:

- return ASPEED_SDMC_DRAM_256MB;

- case 512:

- return ASPEED_SDMC_DRAM_512MB;

- default:

- g_assert_not_reached();

- break;

- }

-}

-

-static int ast2500_rambits(AspeedSDMCState *s)

-{

- switch (s->ram_size >> 20) {

- case 128:

- return ASPEED_SDMC_AST2500_128MB;

- case 256:

- return ASPEED_SDMC_AST2500_256MB;

- case 512:

- return ASPEED_SDMC_AST2500_512MB;

- case 1024:

- return ASPEED_SDMC_AST2500_1024MB;

- default:

- g_assert_not_reached();

- break;

- }

-}

-

-static int ast2600_rambits(AspeedSDMCState *s)

-{

- switch (s->ram_size >> 20) {

- case 256:

- return ASPEED_SDMC_AST2600_256MB;

- case 512:

- return ASPEED_SDMC_AST2600_512MB;

- case 1024:

- return ASPEED_SDMC_AST2600_1024MB;

- case 2048:

- return ASPEED_SDMC_AST2600_2048MB;

- default:

- g_assert_not_reached();

- break;

- }

-}

-

static void aspeed_sdmc_reset(DeviceState *dev)

{

AspeedSDMCState *s = ASPEED_SDMC(dev);

@@ -XXX,XX +XXX,XX @@ static const TypeInfo aspeed_sdmc_info = {

.abstract = true,

};

+static int aspeed_sdmc_get_ram_bits(AspeedSDMCState *s)

+{

+ AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);

+ int i;

+

+ /*

+ * The bitfield value encoding the RAM size is the index of the

+ * possible RAM size array

+ */

+ for (i = 0; asc->valid_ram_sizes[i]; i++) {

+ if (s->ram_size == asc->valid_ram_sizes[i]) {

+ return i;

+ }

+ }

+

+ /*

+ * Invalid RAM sizes should have been excluded when setting the

+ * SoC RAM size.

+ */

+ g_assert_not_reached();

+}

+

static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)

{

uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |

- ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s));

+ ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));

/* Make sure readonly bits are kept */

data &= ~ASPEED_SDMC_READONLY_MASK;

@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)

uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |

ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |

ASPEED_SDMC_CACHE_INITIAL_DONE |

- ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s));

+ ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));

/* Make sure readonly bits are kept */

data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;

@@ -XXX,XX +XXX,XX @@ static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)

{

uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |

ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |

- ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s));

+ ASPEED_SDMC_DRAM_SIZE(aspeed_sdmc_get_ram_bits(s));

/* Make sure readonly bits are kept (use ast2500 mask) */

data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;

--

2.25.4

This change works around the HW default values to be able to test the

Tacoma board with -kernel command line option. This was required when

we had both flash chips enabled in the device tree, otherwise Linux

would fail to probe the entire controller leaving it with no rootfs.

Reviewed-by: Joel Stanley <joel@jms.id.au>

Message-Id: <20200819100956.2216690-20-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/ssi/aspeed_smc.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/ssi/aspeed_smc.c

+++ b/hw/ssi/aspeed_smc.c

@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg,

static const AspeedSegments aspeed_segments_ast2600_fmc[] = {

{ 0x0, 128 * MiB }, /* start address is readonly */

- { 0x0, 0 }, /* disabled */

+ { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */

{ 0x0, 0 }, /* disabled */

};

--

2.25.4

From: Igor Kononenko <i.kononenko@yadro.com>

Provide a definition for the "25Hz reference clock input mode" strap

Signed-off-by: Igor Kononenko <i.kononenko@yadro.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-Id: <20200811203502.20382-1-i.kononenko@yadro.com>

Message-Id: <20200819100956.2216690-21-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

include/hw/misc/aspeed_scu.h | 1 +

1 file changed, 1 insertion(+)

diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/misc/aspeed_scu.h

+++ b/include/hw/misc/aspeed_scu.h

@@ -XXX,XX +XXX,XX @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);

#define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26)

#define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25)

#define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24)

+#define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23)

#define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19)

#define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18)

--

2.25.4

From: Igor Kononenko <i.kononenko@yadro.com>

Support a following SPI flashes:

* mx66l51235f

* mt25ql512ab

Signed-off-by: Igor Kononenko <i.kononenko@yadro.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-Id: <20200811203724.20699-1-i.kononenko@yadro.com>

Message-Id: <20200819100956.2216690-22-clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

---

hw/block/m25p80.c | 2 ++

1 file changed, 2 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/block/m25p80.c

+++ b/hw/block/m25p80.c

@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {

{ INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },

{ INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) },

{ INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },

+ { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },

{ INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },

{ INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },

{ INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },

@@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = {

{ INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },

{ INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },

{ INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },

+ { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },

{ INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },

{ INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },

{ INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },

--

2.25.4