1
Nothing earth-shaking in here, just a lot of refactoring and cleanup
1
Some arm patches; my to-review queue is by no means empty, but
2
and a few bugfixes. I suspect I'll have another pullreq to come in
2
this is a big enough set of patches to be getting on with...
3
the early part of next week...
4
3
5
The following changes since commit 19591e9e0938ea5066984553c256a043bd5d822f:
4
-- PMM
6
5
7
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-08-27 16:59:02 +0100)
6
The following changes since commit cb9c6a8e5ad6a1f0ce164d352e3102df46986e22:
7
8
.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobs (2023-01-04 18:58:33 +0000)
8
9
9
are available in the Git repository at:
10
are available in the Git repository at:
10
11
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200828
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230105
12
13
13
for you to fetch changes up to ed78849d9711805bda37ee026018d6ee7a606d0e:
14
for you to fetch changes up to 93c9678de9dc7d2e68f9e8477da072bac30ef132:
14
15
15
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd (2020-08-28 10:02:50 +0100)
16
hw/net: Fix read of uninitialized memory in imx_fec. (2023-01-05 15:33:00 +0000)
16
17
17
----------------------------------------------------------------
18
----------------------------------------------------------------
18
target-arm queue:
19
target-arm queue:
19
* target/arm: Cleanup and refactoring preparatory to SVE2
20
* Implement AArch32 ARMv8-R support
20
* armsse: Define ARMSSEClass correctly
21
* Add Cortex-R52 CPU
21
* hw/misc/unimp: Improve information provided in log messages
22
* fix handling of HLT semihosting in system mode
22
* hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
23
* hw/timer/ixm_epit: cleanup and fix bug in compare handling
23
* hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
24
* target/arm: Coding style fixes
24
* hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
25
* target/arm: Clean up includes
25
* hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
26
* nseries: minor code cleanups
26
* target/arm: Fill in the WnR syndrome bit in mte_check_fail
27
* target/arm: align exposed ID registers with Linux
27
* target/arm: Clarify HCR_EL2 ARMCPRegInfo type
28
* hw/arm/smmu-common: remove unnecessary inlines
28
* hw/arm/musicpal: Use AddressSpace for DMA transfers
29
* i.MX7D: Handle GPT timers
29
* hw/clock: Minor cleanups
30
* i.MX7D: Connect IRQs to GPIO devices
30
* hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
31
* i.MX6UL: Add a specific GPT timer instance
32
* hw/net: Fix read of uninitialized memory in imx_fec
31
33
32
----------------------------------------------------------------
34
----------------------------------------------------------------
33
Eduardo Habkost (1):
35
Alex Bennée (1):
34
armsse: Define ARMSSEClass correctly
36
target/arm: fix handling of HLT semihosting in system mode
35
37
36
Graeme Gregory (1):
38
Axel Heider (8):
37
hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
39
hw/timer/imx_epit: improve comments
40
hw/timer/imx_epit: cleanup CR defines
41
hw/timer/imx_epit: define SR_OCIF
42
hw/timer/imx_epit: update interrupt state on CR write access
43
hw/timer/imx_epit: hard reset initializes CR with 0
44
hw/timer/imx_epit: factor out register write handlers
45
hw/timer/imx_epit: remove explicit fields cnt and freq
46
hw/timer/imx_epit: fix compare timer handling
38
47
39
Philippe Mathieu-Daudé (14):
48
Claudio Fontana (1):
40
hw/clock: Remove unused clock_init*() functions
49
target/arm: cleanup cpu includes
41
hw/clock: Let clock_set() return boolean value
42
hw/clock: Only propagate clock changes if the clock is changed
43
hw/arm/musicpal: Use AddressSpace for DMA transfers
44
target/arm: Clarify HCR_EL2 ARMCPRegInfo type
45
hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
46
hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
47
hw/arm/xilinx_zynq: Uninline cadence_uart_create()
48
hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
49
hw/qdev-clock: Uninline qdev_connect_clock_in()
50
hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
51
hw/misc/unimp: Display value after offset
52
hw/misc/unimp: Display the value with width of the access size
53
hw/misc/unimp: Display the offset with width of the region size
54
50
55
Richard Henderson (19):
51
Fabiano Rosas (5):
56
target/arm: Pass the entire mte descriptor to mte_check_fail
52
target/arm: Fix checkpatch comment style warnings in helper.c
57
target/arm: Fill in the WnR syndrome bit in mte_check_fail
53
target/arm: Fix checkpatch space errors in helper.c
58
qemu/int128: Add int128_lshift
54
target/arm: Fix checkpatch brace errors in helper.c
59
target/arm: Split out gen_gvec_fn_zz
55
target/arm: Remove unused includes from m_helper.c
60
target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
56
target/arm: Remove unused includes from helper.c
61
target/arm: Rearrange {sve,fp}_check_access assert
62
target/arm: Merge do_vector2_p into do_mov_p
63
target/arm: Clean up 4-operand predicate expansion
64
target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
65
target/arm: Split out gen_gvec_ool_zzzp
66
target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
67
target/arm: Split out gen_gvec_ool_zzp
68
target/arm: Split out gen_gvec_ool_zzz
69
target/arm: Split out gen_gvec_ool_zz
70
target/arm: Tidy SVE tszimm shift formats
71
target/arm: Generalize inl_qrdmlah_* helper functions
72
target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
73
target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
74
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
75
57
76
include/hw/arm/armsse.h | 2 +-
58
Jean-Christophe Dubois (4):
77
include/hw/char/cadence_uart.h | 17 --
59
i.MX7D: Connect GPT timers to IRQ
78
include/hw/clock.h | 30 +--
60
i.MX7D: Compute clock frequency for the fixed frequency clocks.
79
include/hw/misc/unimp.h | 1 +
61
i.MX6UL: Add a specific GPT timer instance for the i.MX6UL
80
include/hw/net/allwinner-sun8i-emac.h | 6 +
62
i.MX7D: Connect IRQs to GPIO devices.
81
include/hw/qdev-clock.h | 8 +-
82
include/hw/sd/allwinner-sdhost.h | 6 +
83
include/qemu/int128.h | 16 ++
84
target/arm/helper-sve.h | 5 -
85
target/arm/helper.h | 28 +++
86
target/arm/translate.h | 1 +
87
target/arm/sve.decode | 35 ++-
88
hw/arm/allwinner-a10.c | 2 +
89
hw/arm/allwinner-h3.c | 4 +
90
hw/arm/armsse.c | 1 +
91
hw/arm/musicpal.c | 45 ++--
92
hw/arm/sbsa-ref.c | 2 +-
93
hw/arm/xilinx_zynq.c | 24 +-
94
hw/core/clock.c | 7 +-
95
hw/core/qdev-clock.c | 6 +
96
hw/misc/unimp.c | 14 +-
97
hw/net/allwinner-sun8i-emac.c | 46 ++--
98
hw/sd/allwinner-sdhost.c | 37 +++-
99
target/arm/helper.c | 1 -
100
target/arm/mte_helper.c | 19 +-
101
target/arm/sve_helper.c | 70 ++----
102
target/arm/translate-a64.c | 110 ++++++++--
103
target/arm/translate-sve.c | 399 ++++++++++++++--------------------
104
target/arm/vec_helper.c | 182 +++++++++++-----
105
29 files changed, 629 insertions(+), 495 deletions(-)
106
63
64
Peter Maydell (1):
65
target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it
66
67
Philippe Mathieu-Daudé (5):
68
hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg
69
hw/arm/nseries: Constify various read-only arrays
70
hw/arm/nseries: Silent -Wmissing-field-initializers warning
71
hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope
72
hw/arm/smmu-common: Avoid using inlined functions with external linkage
73
74
Stephen Longfield (1):
75
hw/net: Fix read of uninitialized memory in imx_fec.
76
77
Tobias Röhmel (7):
78
target/arm: Don't add all MIDR aliases for cores that implement PMSA
79
target/arm: Make RVBAR available for all ARMv8 CPUs
80
target/arm: Make stage_2_format for cache attributes optional
81
target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
82
target/arm: Add PMSAv8r registers
83
target/arm: Add PMSAv8r functionality
84
target/arm: Add ARM Cortex-R52 CPU
85
86
Zhuojia Shen (1):
87
target/arm: align exposed ID registers with Linux
88
89
include/hw/arm/fsl-imx7.h | 20 +
90
include/hw/arm/smmu-common.h | 3 -
91
include/hw/input/tsc2xxx.h | 4 +-
92
include/hw/timer/imx_epit.h | 8 +-
93
include/hw/timer/imx_gpt.h | 1 +
94
target/arm/cpu.h | 6 +
95
target/arm/internals.h | 4 +
96
hw/arm/fsl-imx6ul.c | 2 +-
97
hw/arm/fsl-imx7.c | 41 +-
98
hw/arm/nseries.c | 28 +-
99
hw/arm/smmu-common.c | 15 +-
100
hw/input/tsc2005.c | 2 +-
101
hw/input/tsc210x.c | 3 +-
102
hw/misc/imx6ul_ccm.c | 6 -
103
hw/misc/imx7_ccm.c | 49 ++-
104
hw/net/imx_fec.c | 8 +-
105
hw/timer/imx_epit.c | 376 +++++++++-------
106
hw/timer/imx_gpt.c | 25 ++
107
target/arm/cpu.c | 35 +-
108
target/arm/cpu64.c | 6 -
109
target/arm/cpu_tcg.c | 42 ++
110
target/arm/debug_helper.c | 3 +
111
target/arm/helper.c | 871 +++++++++++++++++++++++++++++---------
112
target/arm/m_helper.c | 16 -
113
target/arm/machine.c | 28 ++
114
target/arm/ptw.c | 152 +++++--
115
target/arm/tlb_helper.c | 4 +
116
target/arm/translate.c | 2 +-
117
tests/tcg/aarch64/sysregs.c | 24 +-
118
tests/tcg/aarch64/Makefile.target | 7 +-
119
30 files changed, 1330 insertions(+), 461 deletions(-)
120
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In get_phys_addr_twostage() we set the lg_page_size of the result to
2
the maximum of the stage 1 and stage 2 page sizes. This works for
3
the case where we do want to create a TLB entry, because we know the
4
common TLB code only creates entries of the TARGET_PAGE_SIZE and
5
asking for a size larger than that only means that invalidations
6
invalidate the whole larger area. However, if lg_page_size is
7
smaller than TARGET_PAGE_SIZE this effectively means "don't create a
8
TLB entry"; in this case if either S1 or S2 said "this covers less
9
than a page and can't go in a TLB" then the final result also should
10
be marked that way. Set the resulting page size to 0 if either
11
stage asked for a less-than-a-page entry, and expand the comment
12
to explain what's going on.
2
13
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
This has no effect for VMSA because currently the VMSA lookup always
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
returns results that cover at least TARGET_PAGE_SIZE; however when we
5
Message-id: 20200815013145.539409-21-richard.henderson@linaro.org
16
add v8R support it will reuse this code path, and for v8R the S1 and
17
S2 results can be smaller than TARGET_PAGE_SIZE.
18
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20221212142708.610090-1-peter.maydell@linaro.org
7
---
22
---
8
target/arm/helper.h | 10 ++++++++
23
target/arm/ptw.c | 16 +++++++++++++---
9
target/arm/translate-a64.c | 33 ++++++++++++++++++--------
24
1 file changed, 13 insertions(+), 3 deletions(-)
10
target/arm/vec_helper.c | 48 ++++++++++++++++++++++++++++++++++++++
11
3 files changed, 81 insertions(+), 10 deletions(-)
12
25
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
26
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
14
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.h
28
--- a/target/arm/ptw.c
16
+++ b/target/arm/helper.h
29
+++ b/target/arm/ptw.c
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
18
DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
31
}
19
void, ptr, ptr, ptr, ptr, i32)
32
20
33
/*
21
+DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG,
34
- * Use the maximum of the S1 & S2 page size, so that invalidation
22
+ void, ptr, ptr, ptr, ptr, i32)
35
- * of pages > TARGET_PAGE_SIZE works correctly.
23
+DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG,
36
+ * If either S1 or S2 returned a result smaller than TARGET_PAGE_SIZE,
24
+ void, ptr, ptr, ptr, ptr, i32)
37
+ * this means "don't put this in the TLB"; in this case, return a
25
+
38
+ * result with lg_page_size == 0 to achieve that. Otherwise,
26
+DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG,
39
+ * use the maximum of the S1 & S2 page size, so that invalidation
27
+ void, ptr, ptr, ptr, ptr, i32)
40
+ * of pages > TARGET_PAGE_SIZE works correctly. (This works even though
28
+DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG,
41
+ * we know the combined result permissions etc only cover the minimum
29
+ void, ptr, ptr, ptr, ptr, i32)
42
+ * of the S1 and S2 page size, because we know that the common TLB code
30
+
43
+ * never actually creates TLB entries bigger than TARGET_PAGE_SIZE,
31
#ifdef TARGET_AARCH64
44
+ * and passing a larger page size value only affects invalidations.)
32
#include "helper-a64.h"
45
*/
33
#include "helper-sve.h"
46
- if (result->f.lg_page_size < s1_lgpgsz) {
34
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
47
+ if (result->f.lg_page_size < TARGET_PAGE_BITS ||
35
index XXXXXXX..XXXXXXX 100644
48
+ s1_lgpgsz < TARGET_PAGE_BITS) {
36
--- a/target/arm/translate-a64.c
49
+ result->f.lg_page_size = 0;
37
+++ b/target/arm/translate-a64.c
50
+ } else if (result->f.lg_page_size < s1_lgpgsz) {
38
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
51
result->f.lg_page_size = s1_lgpgsz;
39
tcg_temp_free_ptr(fpst);
52
}
40
}
53
41
42
+/* Expand a 3-operand + qc + operation using an out-of-line helper. */
43
+static void gen_gvec_op3_qc(DisasContext *s, bool is_q, int rd, int rn,
44
+ int rm, gen_helper_gvec_3_ptr *fn)
45
+{
46
+ TCGv_ptr qc_ptr = tcg_temp_new_ptr();
47
+
48
+ tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc));
49
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
50
+ vec_full_reg_offset(s, rn),
51
+ vec_full_reg_offset(s, rm), qc_ptr,
52
+ is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
53
+ tcg_temp_free_ptr(qc_ptr);
54
+}
55
+
56
/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
57
* than the 32 bit equivalent.
58
*/
59
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
60
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size);
61
}
62
return;
63
+ case 0x16: /* SQDMULH, SQRDMULH */
64
+ {
65
+ static gen_helper_gvec_3_ptr * const fns[2][2] = {
66
+ { gen_helper_neon_sqdmulh_h, gen_helper_neon_sqrdmulh_h },
67
+ { gen_helper_neon_sqdmulh_s, gen_helper_neon_sqrdmulh_s },
68
+ };
69
+ gen_gvec_op3_qc(s, is_q, rd, rn, rm, fns[size - 1][u]);
70
+ }
71
+ return;
72
case 0x11:
73
if (!u) { /* CMTST */
74
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size);
75
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
76
genenvfn = fns[size][u];
77
break;
78
}
79
- case 0x16: /* SQDMULH, SQRDMULH */
80
- {
81
- static NeonGenTwoOpEnvFn * const fns[2][2] = {
82
- { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
83
- { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
84
- };
85
- assert(size == 1 || size == 2);
86
- genenvfn = fns[size - 1][u];
87
- break;
88
- }
89
default:
90
g_assert_not_reached();
91
}
92
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/vec_helper.c
95
+++ b/target/arm/vec_helper.c
96
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
97
clear_tail(d, opr_sz, simd_maxsz(desc));
98
}
99
100
+void HELPER(neon_sqdmulh_h)(void *vd, void *vn, void *vm,
101
+ void *vq, uint32_t desc)
102
+{
103
+ intptr_t i, opr_sz = simd_oprsz(desc);
104
+ int16_t *d = vd, *n = vn, *m = vm;
105
+
106
+ for (i = 0; i < opr_sz / 2; ++i) {
107
+ d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, false, vq);
108
+ }
109
+ clear_tail(d, opr_sz, simd_maxsz(desc));
110
+}
111
+
112
+void HELPER(neon_sqrdmulh_h)(void *vd, void *vn, void *vm,
113
+ void *vq, uint32_t desc)
114
+{
115
+ intptr_t i, opr_sz = simd_oprsz(desc);
116
+ int16_t *d = vd, *n = vn, *m = vm;
117
+
118
+ for (i = 0; i < opr_sz / 2; ++i) {
119
+ d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, true, vq);
120
+ }
121
+ clear_tail(d, opr_sz, simd_maxsz(desc));
122
+}
123
+
124
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
125
static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
126
bool neg, bool round, uint32_t *sat)
127
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
128
clear_tail(d, opr_sz, simd_maxsz(desc));
129
}
130
131
+void HELPER(neon_sqdmulh_s)(void *vd, void *vn, void *vm,
132
+ void *vq, uint32_t desc)
133
+{
134
+ intptr_t i, opr_sz = simd_oprsz(desc);
135
+ int32_t *d = vd, *n = vn, *m = vm;
136
+
137
+ for (i = 0; i < opr_sz / 4; ++i) {
138
+ d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, false, vq);
139
+ }
140
+ clear_tail(d, opr_sz, simd_maxsz(desc));
141
+}
142
+
143
+void HELPER(neon_sqrdmulh_s)(void *vd, void *vn, void *vm,
144
+ void *vq, uint32_t desc)
145
+{
146
+ intptr_t i, opr_sz = simd_oprsz(desc);
147
+ int32_t *d = vd, *n = vn, *m = vm;
148
+
149
+ for (i = 0; i < opr_sz / 4; ++i) {
150
+ d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, true, vq);
151
+ }
152
+ clear_tail(d, opr_sz, simd_maxsz(desc));
153
+}
154
+
155
/* Integer 8 and 16-bit dot-product.
156
*
157
* Note that for the loops herein, host endianness does not matter
158
--
54
--
159
2.20.1
55
2.25.1
160
161
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Rather than require the user to fill in the immediate (shl or shr),
3
Cores with PMSA have the MPUIR register which has the
4
create full formats that include the immediate.
4
same encoding as the MIDR alias with opc2=4. So we only
5
add that alias if we are not realizing a core that
6
implements PMSA.
5
7
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200815013145.539409-14-richard.henderson@linaro.org
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/sve.decode | 35 ++++++++++++++++-------------------
14
target/arm/helper.c | 13 +++++++++----
12
1 file changed, 16 insertions(+), 19 deletions(-)
15
1 file changed, 9 insertions(+), 4 deletions(-)
13
16
14
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve.decode
19
--- a/target/arm/helper.c
17
+++ b/target/arm/sve.decode
20
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
19
@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
22
.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
20
23
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
21
# Two register operand, one immediate operand, with predicate,
24
.readfn = midr_read },
22
-# element size encoded as TSZHL. User must fill in imm.
25
- /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
23
-@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
26
- { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
24
- &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
27
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
25
+# element size encoded as TSZHL.
28
- .access = PL1_R, .resetvalue = cpu->midr },
26
+@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
29
+ /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
27
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
30
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
28
+@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
31
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
29
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
32
.access = PL1_R, .resetvalue = cpu->midr },
30
33
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
31
# Similarly without predicate.
34
.accessfn = access_aa64_tid1,
32
-@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
35
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
33
- &rri_esz esz=%tszimm16_esz
36
};
34
+@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
37
+ ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
35
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
38
+ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
36
+@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
39
+ .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
37
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
40
+ .access = PL1_R, .resetvalue = cpu->midr
38
41
+ };
39
# Two register operand, one immediate operand, with 4-bit predicate.
42
ARMCPRegInfo id_cp_reginfo[] = {
40
# User must fill in imm.
43
/* These are common to v8 and pre-v8 */
41
@@ -XXX,XX +XXX,XX @@ UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
44
{ .name = "CTR",
42
### SVE Shift by Immediate - Predicated Group
45
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
43
46
}
44
# SVE bitwise shift by immediate (predicated)
47
if (arm_feature(env, ARM_FEATURE_V8)) {
45
-ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
48
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
46
- @rdn_pg_tszimm imm=%tszimm_shr
49
+ if (!arm_feature(env, ARM_FEATURE_PMSA)) {
47
-LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
50
+ define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo);
48
- @rdn_pg_tszimm imm=%tszimm_shr
51
+ }
49
-LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
52
} else {
50
- @rdn_pg_tszimm imm=%tszimm_shl
53
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
51
-ASRD 00000100 .. 000 100 100 ... .. ... ..... \
54
}
52
- @rdn_pg_tszimm imm=%tszimm_shr
53
+ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
54
+LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
55
+LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
56
+ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
57
58
# SVE bitwise shift by vector (predicated)
59
ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
60
@@ -XXX,XX +XXX,XX @@ RDVL 00000100 101 11111 01010 imm:s6 rd:5
61
### SVE Bitwise Shift - Unpredicated Group
62
63
# SVE bitwise shift by immediate (unpredicated)
64
-ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
65
- @rd_rn_tszimm imm=%tszimm16_shr
66
-LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
67
- @rd_rn_tszimm imm=%tszimm16_shr
68
-LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
69
- @rd_rn_tszimm imm=%tszimm16_shl
70
+ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
71
+LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
72
+LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
73
74
# SVE bitwise shift by wide elements (unpredicated)
75
# Note esz != 3
76
--
55
--
77
2.20.1
56
2.25.1
78
57
79
58
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
We need more information than just the mmu_idx in order
3
RVBAR shadows RVBAR_ELx where x is the highest exception
4
to create the proper exception syndrome. Only change the
4
level if the highest EL is not EL3. This patch also allows
5
function signature so far.
5
ARMv8 CPUs to change the reset address with
6
the rvbar property.
6
7
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
8
Message-id: 20200813200816.3037186-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20221206102504.165775-3-tobias.roehmel@rwth-aachen.de
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/mte_helper.c | 10 +++++-----
13
target/arm/cpu.c | 6 +++++-
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
target/arm/helper.c | 21 ++++++++++++++-------
15
2 files changed, 19 insertions(+), 8 deletions(-)
14
16
15
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
17
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/mte_helper.c
19
--- a/target/arm/cpu.c
18
+++ b/target/arm/mte_helper.c
20
+++ b/target/arm/cpu.c
19
@@ -XXX,XX +XXX,XX @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
21
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
20
}
22
env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
21
23
CPACR, CP11, 3);
22
/* Record a tag check failure. */
24
#endif
23
-static void mte_check_fail(CPUARMState *env, int mmu_idx,
25
+ if (arm_feature(env, ARM_FEATURE_V8)) {
24
+static void mte_check_fail(CPUARMState *env, uint32_t desc,
26
+ env->cp15.rvbar = cpu->rvbar_prop;
25
uint64_t dirty_ptr, uintptr_t ra)
27
+ env->regs[15] = cpu->rvbar_prop;
26
{
28
+ }
27
+ int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
28
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
29
int el, reg_el, tcf, select;
30
uint64_t sctlr;
31
@@ -XXX,XX +XXX,XX @@ uint64_t mte_check1(CPUARMState *env, uint32_t desc,
32
}
29
}
33
30
34
if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) {
31
#if defined(CONFIG_USER_ONLY)
35
- int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
32
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
36
- mte_check_fail(env, mmu_idx, ptr, ra);
33
qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
37
+ mte_check_fail(env, desc, ptr, ra);
38
}
34
}
39
35
40
return useronly_clean_ptr(ptr);
36
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
41
@@ -XXX,XX +XXX,XX @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc,
37
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
42
38
object_property_add_uint64_ptr(obj, "rvbar",
43
fail_ofs = tag_first + n * TAG_GRANULE - ptr;
39
&cpu->rvbar_prop,
44
fail_ofs = ROUND_UP(fail_ofs, esize);
40
OBJ_PROP_FLAG_READWRITE);
45
- mte_check_fail(env, mmu_idx, ptr + fail_ofs, ra);
41
diff --git a/target/arm/helper.c b/target/arm/helper.c
46
+ mte_check_fail(env, desc, ptr + fail_ofs, ra);
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/helper.c
44
+++ b/target/arm/helper.c
45
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
46
if (!arm_feature(env, ARM_FEATURE_EL3) &&
47
!arm_feature(env, ARM_FEATURE_EL2)) {
48
ARMCPRegInfo rvbar = {
49
- .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
50
+ .name = "RVBAR_EL1", .state = ARM_CP_STATE_BOTH,
51
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
52
.access = PL1_R,
53
.fieldoffset = offsetof(CPUARMState, cp15.rvbar),
54
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
55
}
56
/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
57
if (!arm_feature(env, ARM_FEATURE_EL3)) {
58
- ARMCPRegInfo rvbar = {
59
- .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
60
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
61
- .access = PL2_R,
62
- .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
63
+ ARMCPRegInfo rvbar[] = {
64
+ {
65
+ .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
66
+ .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
67
+ .access = PL2_R,
68
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
69
+ },
70
+ { .name = "RVBAR", .type = ARM_CP_ALIAS,
71
+ .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
72
+ .access = PL2_R,
73
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
74
+ },
75
};
76
- define_one_arm_cp_reg(cpu, &rvbar);
77
+ define_arm_cp_regs(cpu, rvbar);
78
}
47
}
79
}
48
80
49
done:
50
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr)
51
fail:
52
/* Locate the first nibble that differs. */
53
i = ctz64(mem_tag ^ ptr_tag) >> 4;
54
- mte_check_fail(env, mmu_idx, align_ptr + i * TAG_GRANULE, ra);
55
+ mte_check_fail(env, desc, align_ptr + i * TAG_GRANULE, ra);
56
57
done:
58
return useronly_clean_ptr(ptr);
59
--
81
--
60
2.20.1
82
2.25.1
61
83
62
84
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
The v8R PMSAv8 has a two-stage MPU translation process, but, unlike
4
VMSAv8, the stage 2 attributes are in the same format as the stage 1
5
attributes (8-bit MAIR format). Rather than converting the MAIR
6
format to the format used for VMSA stage 2 (bits [5:2] of a VMSA
7
stage 2 descriptor) and then converting back to do the attribute
8
combination, allow combined_attrs_nofwb() to accept s2 attributes
9
that are already in the MAIR format.
10
11
We move the assert() to combined_attrs_fwb(), because that function
12
really does require a VMSA stage 2 attribute format. (We will never
13
get there for v8R, because PMSAv8 does not implement FEAT_S2FWB.)
14
15
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-13-richard.henderson@linaro.org
17
Message-id: 20221206102504.165775-4-tobias.roehmel@rwth-aachen.de
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
19
---
8
target/arm/translate-sve.c | 20 ++++++++++++--------
20
target/arm/ptw.c | 10 ++++++++--
9
1 file changed, 12 insertions(+), 8 deletions(-)
21
1 file changed, 8 insertions(+), 2 deletions(-)
10
22
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
23
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
12
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
25
--- a/target/arm/ptw.c
14
+++ b/target/arm/translate-sve.c
26
+++ b/target/arm/ptw.c
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
27
@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_nofwb(uint64_t hcr,
16
return size_for_gvec(pred_full_reg_size(s));
28
{
17
}
29
uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
18
30
19
+/* Invoke an out-of-line helper on 2 Zregs. */
31
- s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
20
+static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
32
+ if (s2.is_s2_format) {
21
+ int rd, int rn, int data)
33
+ s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
22
+{
34
+ } else {
23
+ unsigned vsz = vec_full_reg_size(s);
35
+ s2_mair_attrs = s2.attrs;
24
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
36
+ }
25
+ vec_full_reg_offset(s, rn),
37
26
+ vsz, vsz, data, fn);
38
s1lo = extract32(s1.attrs, 0, 4);
27
+}
39
s2lo = extract32(s2_mair_attrs, 0, 4);
40
@@ -XXX,XX +XXX,XX @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
41
*/
42
static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
43
{
44
+ assert(s2.is_s2_format && !s1.is_s2_format);
28
+
45
+
29
/* Invoke an out-of-line helper on 3 Zregs. */
46
switch (s2.attrs) {
30
static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
47
case 7:
31
int rd, int rn, int rm, int data)
48
/* Use stage 1 attributes */
32
@@ -XXX,XX +XXX,XX @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
49
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
33
return false;
50
ARMCacheAttrs ret;
34
}
51
bool tagged = false;
35
if (sve_access_check(s)) {
52
36
- unsigned vsz = vec_full_reg_size(s);
53
- assert(s2.is_s2_format && !s1.is_s2_format);
37
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
54
+ assert(!s1.is_s2_format);
38
- vec_full_reg_offset(s, a->rn),
55
ret.is_s2_format = false;
39
- vsz, vsz, 0, fns[a->esz]);
56
40
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
57
if (s1.attrs == 0xf0) {
41
}
42
return true;
43
}
44
@@ -XXX,XX +XXX,XX @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
45
};
46
47
if (sve_access_check(s)) {
48
- unsigned vsz = vec_full_reg_size(s);
49
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
50
- vec_full_reg_offset(s, a->rn),
51
- vsz, vsz, 0, fns[a->esz]);
52
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
53
}
54
return true;
55
}
56
--
58
--
57
2.20.1
59
2.25.1
58
60
59
61
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Model after gen_gvec_fn_zzz et al.
3
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
4
tough they don't have the TTBCR register.
5
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
6
AArch32 architecture profile Version:A.c section C1.2.
4
7
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-9-richard.henderson@linaro.org
10
Message-id: 20221206102504.165775-5-tobias.roehmel@rwth-aachen.de
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/translate-sve.c | 35 ++++++++++++++++-------------------
13
target/arm/internals.h | 4 ++++
11
1 file changed, 16 insertions(+), 19 deletions(-)
14
target/arm/debug_helper.c | 3 +++
15
target/arm/tlb_helper.c | 4 ++++
16
3 files changed, 11 insertions(+)
12
17
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
20
--- a/target/arm/internals.h
16
+++ b/target/arm/translate-sve.c
21
+++ b/target/arm/internals.h
17
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
22
@@ -XXX,XX +XXX,XX @@ unsigned int arm_pamax(ARMCPU *cpu);
18
return size_for_gvec(pred_full_reg_size(s));
23
static inline bool extended_addresses_enabled(CPUARMState *env)
24
{
25
uint64_t tcr = env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
26
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
27
+ arm_feature(env, ARM_FEATURE_V8)) {
28
+ return true;
29
+ }
30
return arm_el_is_aa64(env, 1) ||
31
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr & TTBCR_EAE));
19
}
32
}
20
33
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
21
-/* Invoke a vector expander on two Zregs. */
34
index XXXXXXX..XXXXXXX 100644
22
+/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
35
--- a/target/arm/debug_helper.c
23
+static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
36
+++ b/target/arm/debug_helper.c
24
+ int rd, int rn, int rm, int pg, int data)
37
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
25
+{
38
26
+ unsigned vsz = vec_full_reg_size(s);
39
if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
27
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
40
using_lpae = true;
28
+ vec_full_reg_offset(s, rn),
41
+ } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
29
+ vec_full_reg_offset(s, rm),
42
+ arm_feature(env, ARM_FEATURE_V8)) {
30
+ pred_full_reg_offset(s, pg),
43
+ using_lpae = true;
31
+ vsz, vsz, data, fn);
44
} else {
32
+}
45
if (arm_feature(env, ARM_FEATURE_LPAE) &&
33
46
(env->cp15.tcr_el[target_el] & TTBCR_EAE)) {
34
+/* Invoke a vector expander on two Zregs. */
47
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
35
static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
48
index XXXXXXX..XXXXXXX 100644
36
int esz, int rd, int rn)
49
--- a/target/arm/tlb_helper.c
37
{
50
+++ b/target/arm/tlb_helper.c
38
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
51
@@ -XXX,XX +XXX,XX @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
39
52
if (el == 2 || arm_el_is_aa64(env, el)) {
40
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
53
return true;
41
{
42
- unsigned vsz = vec_full_reg_size(s);
43
if (fn == NULL) {
44
return false;
45
}
54
}
46
if (sve_access_check(s)) {
55
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
47
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
56
+ arm_feature(env, ARM_FEATURE_V8)) {
48
- vec_full_reg_offset(s, a->rn),
57
+ return true;
49
- vec_full_reg_offset(s, a->rm),
58
+ }
50
- pred_full_reg_offset(s, a->pg),
59
if (arm_feature(env, ARM_FEATURE_LPAE)
51
- vsz, vsz, 0, fn);
60
&& (regime_tcr(env, mmu_idx) & TTBCR_EAE)) {
52
+ gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
61
return true;
53
}
54
return true;
55
}
56
@@ -XXX,XX +XXX,XX @@ static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
57
gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
58
gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
59
};
60
- unsigned vsz = vec_full_reg_size(s);
61
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
62
- vec_full_reg_offset(s, rn),
63
- vec_full_reg_offset(s, rm),
64
- pred_full_reg_offset(s, pg),
65
- vsz, vsz, 0, fns[esz]);
66
+ gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
67
}
68
69
#define DO_ZPZZ(NAME, name) \
70
@@ -XXX,XX +XXX,XX @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
71
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
72
{
73
if (sve_access_check(s)) {
74
- unsigned vsz = vec_full_reg_size(s);
75
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
76
- vec_full_reg_offset(s, a->rn),
77
- vec_full_reg_offset(s, a->rm),
78
- pred_full_reg_offset(s, a->pg),
79
- vsz, vsz, a->esz, gen_helper_sve_splice);
80
+ gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
81
+ a->rd, a->rn, a->rm, a->pg, 0);
82
}
83
return true;
84
}
85
--
62
--
86
2.20.1
63
2.25.1
87
64
88
65
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Allow the device to execute the DMA transfers in a different
3
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
4
AddressSpace.
4
Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de
5
6
The H3 SoC keeps using the system_memory address space,
7
but via the proper dma_memory_access() API.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Message-id: 20200814122907.27732-1-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
6
---
16
include/hw/net/allwinner-sun8i-emac.h | 6 ++++
7
target/arm/cpu.h | 6 +
17
hw/arm/allwinner-h3.c | 2 ++
8
target/arm/cpu.c | 28 +++-
18
hw/net/allwinner-sun8i-emac.c | 46 +++++++++++++++++----------
9
target/arm/helper.c | 302 +++++++++++++++++++++++++++++++++++++++++++
19
3 files changed, 38 insertions(+), 16 deletions(-)
10
target/arm/machine.c | 28 ++++
11
4 files changed, 360 insertions(+), 4 deletions(-)
20
12
21
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/net/allwinner-sun8i-emac.h
15
--- a/target/arm/cpu.h
24
+++ b/include/hw/net/allwinner-sun8i-emac.h
16
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AwSun8iEmacState {
17
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
26
/** Interrupt output signal to notify CPU */
18
};
27
qemu_irq irq;
19
uint64_t sctlr_el[4];
28
20
};
29
+ /** Memory region where DMA transfers are done */
21
+ uint64_t vsctlr; /* Virtualization System control register. */
30
+ MemoryRegion *dma_mr;
22
uint64_t cpacr_el1; /* Architectural feature access control register */
31
+
23
uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
32
+ /** Address space used internally for DMA transfers */
24
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
33
+ AddressSpace dma_as;
25
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
34
+
26
*/
35
/** Generic Network Interface Controller (NIC) for networking API */
27
uint32_t *rbar[M_REG_NUM_BANKS];
36
NICState *nic;
28
uint32_t *rlar[M_REG_NUM_BANKS];
37
29
+ uint32_t *hprbar;
38
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
30
+ uint32_t *hprlar;
31
uint32_t mair0[M_REG_NUM_BANKS];
32
uint32_t mair1[M_REG_NUM_BANKS];
33
+ uint32_t hprselr;
34
} pmsav8;
35
36
/* v8M SAU */
37
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
38
bool has_mpu;
39
/* PMSAv7 MPU number of supported regions */
40
uint32_t pmsav7_dregion;
41
+ /* PMSAv8 MPU number of supported hyp regions */
42
+ uint32_t pmsav8r_hdregion;
43
/* v8M SAU number of supported regions */
44
uint32_t sau_sregion;
45
46
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
39
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/allwinner-h3.c
48
--- a/target/arm/cpu.c
41
+++ b/hw/arm/allwinner-h3.c
49
+++ b/target/arm/cpu.c
42
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
50
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj)
43
qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
51
sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
44
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
52
}
53
}
54
+
55
+ if (cpu->pmsav8r_hdregion > 0) {
56
+ memset(env->pmsav8.hprbar, 0,
57
+ sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
58
+ memset(env->pmsav8.hprlar, 0,
59
+ sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
60
+ }
61
+
62
env->pmsav7.rnr[M_REG_NS] = 0;
63
env->pmsav7.rnr[M_REG_S] = 0;
64
env->pmsav8.mair0[M_REG_NS] = 0;
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
66
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
67
* to false or by setting pmsav7-dregion to 0.
68
*/
69
- if (!cpu->has_mpu) {
70
- cpu->pmsav7_dregion = 0;
71
- }
72
- if (cpu->pmsav7_dregion == 0) {
73
+ if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
74
cpu->has_mpu = false;
75
+ cpu->pmsav7_dregion = 0;
76
+ cpu->pmsav8r_hdregion = 0;
45
}
77
}
46
+ object_property_set_link(OBJECT(&s->emac), "dma-memory",
78
47
+ OBJECT(get_system_memory()), &error_fatal);
79
if (arm_feature(env, ARM_FEATURE_PMSA) &&
48
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
80
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
81
env->pmsav7.dracr = g_new0(uint32_t, nr);
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
82
}
51
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
83
}
84
+
85
+ if (cpu->pmsav8r_hdregion > 0xff) {
86
+ error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
87
+ cpu->pmsav8r_hdregion);
88
+ return;
89
+ }
90
+
91
+ if (cpu->pmsav8r_hdregion) {
92
+ env->pmsav8.hprbar = g_new0(uint32_t,
93
+ cpu->pmsav8r_hdregion);
94
+ env->pmsav8.hprlar = g_new0(uint32_t,
95
+ cpu->pmsav8r_hdregion);
96
+ }
97
}
98
99
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
100
diff --git a/target/arm/helper.c b/target/arm/helper.c
52
index XXXXXXX..XXXXXXX 100644
101
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/net/allwinner-sun8i-emac.c
102
--- a/target/arm/helper.c
54
+++ b/hw/net/allwinner-sun8i-emac.c
103
+++ b/target/arm/helper.c
55
@@ -XXX,XX +XXX,XX @@
104
@@ -XXX,XX +XXX,XX @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
56
105
raw_write(env, ri, value);
57
#include "qemu/osdep.h"
58
#include "qemu/units.h"
59
+#include "qapi/error.h"
60
#include "hw/sysbus.h"
61
#include "migration/vmstate.h"
62
#include "net/net.h"
63
@@ -XXX,XX +XXX,XX @@
64
#include "net/checksum.h"
65
#include "qemu/module.h"
66
#include "exec/cpu-common.h"
67
+#include "sysemu/dma.h"
68
#include "hw/net/allwinner-sun8i-emac.h"
69
70
/* EMAC register offsets */
71
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
72
qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
73
}
106
}
74
107
75
-static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
108
+static void prbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
76
+static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
109
+ uint64_t value)
77
+ FrameDescriptor *desc,
110
+{
78
size_t min_size)
111
+ ARMCPU *cpu = env_archcpu(env);
79
{
112
+
80
uint32_t paddr = desc->next;
113
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
81
114
+ env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
82
- cpu_physical_memory_read(paddr, desc, sizeof(*desc));
115
+}
83
+ dma_memory_read(&s->dma_as, paddr, desc, sizeof(*desc));
116
+
84
117
+static uint64_t prbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
85
if ((desc->status & DESC_STATUS_CTL) &&
118
+{
86
(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
119
+ return env->pmsav8.rbar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
87
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
120
+}
121
+
122
+static void prlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
123
+ uint64_t value)
124
+{
125
+ ARMCPU *cpu = env_archcpu(env);
126
+
127
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
128
+ env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]] = value;
129
+}
130
+
131
+static uint64_t prlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
132
+{
133
+ return env->pmsav8.rlar[M_REG_NS][env->pmsav7.rnr[M_REG_NS]];
134
+}
135
+
136
+static void prselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
137
+ uint64_t value)
138
+{
139
+ ARMCPU *cpu = env_archcpu(env);
140
+
141
+ /*
142
+ * Ignore writes that would select not implemented region.
143
+ * This is architecturally UNPREDICTABLE.
144
+ */
145
+ if (value >= cpu->pmsav7_dregion) {
146
+ return;
147
+ }
148
+
149
+ env->pmsav7.rnr[M_REG_NS] = value;
150
+}
151
+
152
+static void hprbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
153
+ uint64_t value)
154
+{
155
+ ARMCPU *cpu = env_archcpu(env);
156
+
157
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
158
+ env->pmsav8.hprbar[env->pmsav8.hprselr] = value;
159
+}
160
+
161
+static uint64_t hprbar_read(CPUARMState *env, const ARMCPRegInfo *ri)
162
+{
163
+ return env->pmsav8.hprbar[env->pmsav8.hprselr];
164
+}
165
+
166
+static void hprlar_write(CPUARMState *env, const ARMCPRegInfo *ri,
167
+ uint64_t value)
168
+{
169
+ ARMCPU *cpu = env_archcpu(env);
170
+
171
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
172
+ env->pmsav8.hprlar[env->pmsav8.hprselr] = value;
173
+}
174
+
175
+static uint64_t hprlar_read(CPUARMState *env, const ARMCPRegInfo *ri)
176
+{
177
+ return env->pmsav8.hprlar[env->pmsav8.hprselr];
178
+}
179
+
180
+static void hprenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
181
+ uint64_t value)
182
+{
183
+ uint32_t n;
184
+ uint32_t bit;
185
+ ARMCPU *cpu = env_archcpu(env);
186
+
187
+ /* Ignore writes to unimplemented regions */
188
+ int rmax = MIN(cpu->pmsav8r_hdregion, 32);
189
+ value &= MAKE_64BIT_MASK(0, rmax);
190
+
191
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
192
+
193
+ /* Register alias is only valid for first 32 indexes */
194
+ for (n = 0; n < rmax; ++n) {
195
+ bit = extract32(value, n, 1);
196
+ env->pmsav8.hprlar[n] = deposit32(
197
+ env->pmsav8.hprlar[n], 0, 1, bit);
198
+ }
199
+}
200
+
201
+static uint64_t hprenr_read(CPUARMState *env, const ARMCPRegInfo *ri)
202
+{
203
+ uint32_t n;
204
+ uint32_t result = 0x0;
205
+ ARMCPU *cpu = env_archcpu(env);
206
+
207
+ /* Register alias is only valid for first 32 indexes */
208
+ for (n = 0; n < MIN(cpu->pmsav8r_hdregion, 32); ++n) {
209
+ if (env->pmsav8.hprlar[n] & 0x1) {
210
+ result |= (0x1 << n);
211
+ }
212
+ }
213
+ return result;
214
+}
215
+
216
+static void hprselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
217
+ uint64_t value)
218
+{
219
+ ARMCPU *cpu = env_archcpu(env);
220
+
221
+ /*
222
+ * Ignore writes that would select not implemented region.
223
+ * This is architecturally UNPREDICTABLE.
224
+ */
225
+ if (value >= cpu->pmsav8r_hdregion) {
226
+ return;
227
+ }
228
+
229
+ env->pmsav8.hprselr = value;
230
+}
231
+
232
+static void pmsav8r_regn_write(CPUARMState *env, const ARMCPRegInfo *ri,
233
+ uint64_t value)
234
+{
235
+ ARMCPU *cpu = env_archcpu(env);
236
+ uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
237
+ (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
238
+
239
+ tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
240
+
241
+ if (ri->opc1 & 4) {
242
+ if (index >= cpu->pmsav8r_hdregion) {
243
+ return;
244
+ }
245
+ if (ri->opc2 & 0x1) {
246
+ env->pmsav8.hprlar[index] = value;
247
+ } else {
248
+ env->pmsav8.hprbar[index] = value;
249
+ }
250
+ } else {
251
+ if (index >= cpu->pmsav7_dregion) {
252
+ return;
253
+ }
254
+ if (ri->opc2 & 0x1) {
255
+ env->pmsav8.rlar[M_REG_NS][index] = value;
256
+ } else {
257
+ env->pmsav8.rbar[M_REG_NS][index] = value;
258
+ }
259
+ }
260
+}
261
+
262
+static uint64_t pmsav8r_regn_read(CPUARMState *env, const ARMCPRegInfo *ri)
263
+{
264
+ ARMCPU *cpu = env_archcpu(env);
265
+ uint8_t index = (extract32(ri->opc0, 0, 1) << 4) |
266
+ (extract32(ri->crm, 0, 3) << 1) | extract32(ri->opc2, 2, 1);
267
+
268
+ if (ri->opc1 & 4) {
269
+ if (index >= cpu->pmsav8r_hdregion) {
270
+ return 0x0;
271
+ }
272
+ if (ri->opc2 & 0x1) {
273
+ return env->pmsav8.hprlar[index];
274
+ } else {
275
+ return env->pmsav8.hprbar[index];
276
+ }
277
+ } else {
278
+ if (index >= cpu->pmsav7_dregion) {
279
+ return 0x0;
280
+ }
281
+ if (ri->opc2 & 0x1) {
282
+ return env->pmsav8.rlar[M_REG_NS][index];
283
+ } else {
284
+ return env->pmsav8.rbar[M_REG_NS][index];
285
+ }
286
+ }
287
+}
288
+
289
+static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
290
+ { .name = "PRBAR",
291
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 0,
292
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
293
+ .accessfn = access_tvm_trvm,
294
+ .readfn = prbar_read, .writefn = prbar_write },
295
+ { .name = "PRLAR",
296
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 3, .opc2 = 1,
297
+ .access = PL1_RW, .type = ARM_CP_NO_RAW,
298
+ .accessfn = access_tvm_trvm,
299
+ .readfn = prlar_read, .writefn = prlar_write },
300
+ { .name = "PRSELR", .resetvalue = 0,
301
+ .cp = 15, .opc1 = 0, .crn = 6, .crm = 2, .opc2 = 1,
302
+ .access = PL1_RW, .accessfn = access_tvm_trvm,
303
+ .writefn = prselr_write,
304
+ .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]) },
305
+ { .name = "HPRBAR", .resetvalue = 0,
306
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 0,
307
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
308
+ .readfn = hprbar_read, .writefn = hprbar_write },
309
+ { .name = "HPRLAR",
310
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 3, .opc2 = 1,
311
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
312
+ .readfn = hprlar_read, .writefn = hprlar_write },
313
+ { .name = "HPRSELR", .resetvalue = 0,
314
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 2, .opc2 = 1,
315
+ .access = PL2_RW,
316
+ .writefn = hprselr_write,
317
+ .fieldoffset = offsetof(CPUARMState, pmsav8.hprselr) },
318
+ { .name = "HPRENR",
319
+ .cp = 15, .opc1 = 4, .crn = 6, .crm = 1, .opc2 = 1,
320
+ .access = PL2_RW, .type = ARM_CP_NO_RAW,
321
+ .readfn = hprenr_read, .writefn = hprenr_write },
322
+};
323
+
324
static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
325
/* Reset for all these registers is handled in arm_cpu_reset(),
326
* because the PMSAv7 is also used by M-profile CPUs, which do
327
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
328
.access = PL1_R, .type = ARM_CP_CONST,
329
.resetvalue = cpu->pmsav7_dregion << 8
330
};
331
+ /* HMPUIR is specific to PMSA V8 */
332
+ ARMCPRegInfo id_hmpuir_reginfo = {
333
+ .name = "HMPUIR",
334
+ .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 4,
335
+ .access = PL2_R, .type = ARM_CP_CONST,
336
+ .resetvalue = cpu->pmsav8r_hdregion
337
+ };
338
static const ARMCPRegInfo crn0_wi_reginfo = {
339
.name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
340
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
341
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
342
define_arm_cp_regs(cpu, id_cp_reginfo);
343
if (!arm_feature(env, ARM_FEATURE_PMSA)) {
344
define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
345
+ } else if (arm_feature(env, ARM_FEATURE_PMSA) &&
346
+ arm_feature(env, ARM_FEATURE_V8)) {
347
+ uint32_t i = 0;
348
+ char *tmp_string;
349
+
350
+ define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
351
+ define_one_arm_cp_reg(cpu, &id_hmpuir_reginfo);
352
+ define_arm_cp_regs(cpu, pmsav8r_cp_reginfo);
353
+
354
+ /* Register alias is only valid for first 32 indexes */
355
+ for (i = 0; i < MIN(cpu->pmsav7_dregion, 32); ++i) {
356
+ uint8_t crm = 0b1000 | extract32(i, 1, 3);
357
+ uint8_t opc1 = extract32(i, 4, 1);
358
+ uint8_t opc2 = extract32(i, 0, 1) << 2;
359
+
360
+ tmp_string = g_strdup_printf("PRBAR%u", i);
361
+ ARMCPRegInfo tmp_prbarn_reginfo = {
362
+ .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
363
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
364
+ .access = PL1_RW, .resetvalue = 0,
365
+ .accessfn = access_tvm_trvm,
366
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
367
+ };
368
+ define_one_arm_cp_reg(cpu, &tmp_prbarn_reginfo);
369
+ g_free(tmp_string);
370
+
371
+ opc2 = extract32(i, 0, 1) << 2 | 0x1;
372
+ tmp_string = g_strdup_printf("PRLAR%u", i);
373
+ ARMCPRegInfo tmp_prlarn_reginfo = {
374
+ .name = tmp_string, .type = ARM_CP_ALIAS | ARM_CP_NO_RAW,
375
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
376
+ .access = PL1_RW, .resetvalue = 0,
377
+ .accessfn = access_tvm_trvm,
378
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
379
+ };
380
+ define_one_arm_cp_reg(cpu, &tmp_prlarn_reginfo);
381
+ g_free(tmp_string);
382
+ }
383
+
384
+ /* Register alias is only valid for first 32 indexes */
385
+ for (i = 0; i < MIN(cpu->pmsav8r_hdregion, 32); ++i) {
386
+ uint8_t crm = 0b1000 | extract32(i, 1, 3);
387
+ uint8_t opc1 = 0b100 | extract32(i, 4, 1);
388
+ uint8_t opc2 = extract32(i, 0, 1) << 2;
389
+
390
+ tmp_string = g_strdup_printf("HPRBAR%u", i);
391
+ ARMCPRegInfo tmp_hprbarn_reginfo = {
392
+ .name = tmp_string,
393
+ .type = ARM_CP_NO_RAW,
394
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
395
+ .access = PL2_RW, .resetvalue = 0,
396
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
397
+ };
398
+ define_one_arm_cp_reg(cpu, &tmp_hprbarn_reginfo);
399
+ g_free(tmp_string);
400
+
401
+ opc2 = extract32(i, 0, 1) << 2 | 0x1;
402
+ tmp_string = g_strdup_printf("HPRLAR%u", i);
403
+ ARMCPRegInfo tmp_hprlarn_reginfo = {
404
+ .name = tmp_string,
405
+ .type = ARM_CP_NO_RAW,
406
+ .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2,
407
+ .access = PL2_RW, .resetvalue = 0,
408
+ .writefn = pmsav8r_regn_write, .readfn = pmsav8r_regn_read
409
+ };
410
+ define_one_arm_cp_reg(cpu, &tmp_hprlarn_reginfo);
411
+ g_free(tmp_string);
412
+ }
413
} else if (arm_feature(env, ARM_FEATURE_V7)) {
414
define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
415
}
416
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
417
sctlr.type |= ARM_CP_SUPPRESS_TB_END;
418
}
419
define_one_arm_cp_reg(cpu, &sctlr);
420
+
421
+ if (arm_feature(env, ARM_FEATURE_PMSA) &&
422
+ arm_feature(env, ARM_FEATURE_V8)) {
423
+ ARMCPRegInfo vsctlr = {
424
+ .name = "VSCTLR", .state = ARM_CP_STATE_AA32,
425
+ .cp = 15, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
426
+ .access = PL2_RW, .resetvalue = 0x0,
427
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.vsctlr),
428
+ };
429
+ define_one_arm_cp_reg(cpu, &vsctlr);
430
+ }
88
}
431
}
432
433
if (cpu_isar_feature(aa64_lor, cpu)) {
434
diff --git a/target/arm/machine.c b/target/arm/machine.c
435
index XXXXXXX..XXXXXXX 100644
436
--- a/target/arm/machine.c
437
+++ b/target/arm/machine.c
438
@@ -XXX,XX +XXX,XX @@ static bool pmsav8_needed(void *opaque)
439
arm_feature(env, ARM_FEATURE_V8);
89
}
440
}
90
441
91
-static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
442
+static bool pmsav8r_needed(void *opaque)
92
+static uint32_t allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
443
+{
93
+ FrameDescriptor *desc,
444
+ ARMCPU *cpu = opaque;
94
uint32_t start_addr,
445
+ CPUARMState *env = &cpu->env;
95
size_t min_size)
446
+
96
{
447
+ return arm_feature(env, ARM_FEATURE_PMSA) &&
97
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
448
+ arm_feature(env, ARM_FEATURE_V8) &&
98
449
+ !arm_feature(env, ARM_FEATURE_M);
99
/* Note that the list is a cycle. Last entry points back to the head. */
450
+}
100
while (desc_addr != 0) {
451
+
101
- cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
452
+static const VMStateDescription vmstate_pmsav8r = {
102
+ dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
453
+ .name = "cpu/pmsav8/pmsav8r",
103
454
+ .version_id = 1,
104
if ((desc->status & DESC_STATUS_CTL) &&
455
+ .minimum_version_id = 1,
105
(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
456
+ .needed = pmsav8r_needed,
106
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
457
+ .fields = (VMStateField[]) {
107
FrameDescriptor *desc,
458
+ VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU,
108
size_t min_size)
459
+ pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
109
{
460
+ VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU,
110
- return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
461
+ pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t),
111
+ return allwinner_sun8i_emac_get_desc(s, desc, s->rx_desc_curr, min_size);
462
+ VMSTATE_END_OF_LIST()
112
}
463
+ },
113
464
+};
114
static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
465
+
115
FrameDescriptor *desc,
466
static const VMStateDescription vmstate_pmsav8 = {
116
size_t min_size)
467
.name = "cpu/pmsav8",
117
{
468
.version_id = 1,
118
- return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
469
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pmsav8 = {
119
+ return allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_head, min_size);
470
VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU),
120
}
471
VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU),
121
472
VMSTATE_END_OF_LIST()
122
-static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
473
+ },
123
+static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s,
474
+ .subsections = (const VMStateDescription * []) {
124
+ FrameDescriptor *desc,
475
+ &vmstate_pmsav8r,
125
uint32_t phys_addr)
476
+ NULL
126
{
127
- cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
128
+ dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc));
129
}
130
131
static bool allwinner_sun8i_emac_can_receive(NetClientState *nc)
132
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
133
<< RX_DESC_STATUS_FRM_LEN_SHIFT;
134
}
135
136
- cpu_physical_memory_write(desc.addr, buf, desc_bytes);
137
- allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
138
+ dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes);
139
+ allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr);
140
trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
141
desc_bytes);
142
143
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
144
bytes_left -= desc_bytes;
145
146
/* Move to the next descriptor */
147
- s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
148
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 64);
149
if (!s->rx_desc_curr) {
150
/* Not enough buffer space available */
151
s->int_sta |= INT_STA_RX_BUF_UA;
152
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
153
desc.status |= TX_DESC_STATUS_LENGTH_ERR;
154
break;
155
}
156
- cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
157
+ dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, bytes);
158
packet_bytes += bytes;
159
desc.status &= ~DESC_STATUS_CTL;
160
- allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
161
+ allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr);
162
163
/* After the last descriptor, send the packet */
164
if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
165
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
166
packet_bytes = 0;
167
transmitted++;
168
}
169
- s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
170
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 0);
171
}
477
}
172
173
/* Raise transmit completed interrupt */
174
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
175
break;
176
case REG_TX_CUR_BUF: /* Transmit Current Buffer */
177
if (s->tx_desc_curr != 0) {
178
- cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
179
+ dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc));
180
value = desc.addr;
181
} else {
182
value = 0;
183
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
184
break;
185
case REG_RX_CUR_BUF: /* Receive Current Buffer */
186
if (s->rx_desc_curr != 0) {
187
- cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
188
+ dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc));
189
value = desc.addr;
190
} else {
191
value = 0;
192
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
193
{
194
AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
195
196
+ if (!s->dma_mr) {
197
+ error_setg(errp, TYPE_AW_SUN8I_EMAC " 'dma-memory' link not set");
198
+ return;
199
+ }
200
+
201
+ address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
202
+
203
qemu_macaddr_default_if_unset(&s->conf.macaddr);
204
s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
205
object_get_typename(OBJECT(dev)), dev->id, s);
206
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
207
static Property allwinner_sun8i_emac_properties[] = {
208
DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
209
DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
210
+ DEFINE_PROP_LINK("dma-memory", AwSun8iEmacState, dma_mr,
211
+ TYPE_MEMORY_REGION, MemoryRegion *),
212
DEFINE_PROP_END_OF_LIST(),
213
};
478
};
214
479
215
--
480
--
216
2.20.1
481
2.25.1
217
482
218
483
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but
3
Add PMSAv8r translation.
4
indicating which kind of register and in which order.
4
5
5
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
6
Model do_zzz_fn on the other do_foo functions that take an
7
argument set and verify sve enabled.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200815013145.539409-4-richard.henderson@linaro.org
7
Message-id: 20221206102504.165775-7-tobias.roehmel@rwth-aachen.de
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
9
---
14
target/arm/translate-sve.c | 43 +++++++++++++++++++++-----------------
10
target/arm/ptw.c | 126 ++++++++++++++++++++++++++++++++++++++---------
15
1 file changed, 24 insertions(+), 19 deletions(-)
11
1 file changed, 104 insertions(+), 22 deletions(-)
16
12
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
15
--- a/target/arm/ptw.c
20
+++ b/target/arm/translate-sve.c
16
+++ b/target/arm/ptw.c
21
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
17
@@ -XXX,XX +XXX,XX @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx,
18
19
if (arm_feature(env, ARM_FEATURE_M)) {
20
return env->v7m.mpu_ctrl[is_secure] & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
21
- } else {
22
- return regime_sctlr(env, mmu_idx) & SCTLR_BR;
23
}
24
+
25
+ if (mmu_idx == ARMMMUIdx_Stage2) {
26
+ return false;
27
+ }
28
+
29
+ return regime_sctlr(env, mmu_idx) & SCTLR_BR;
22
}
30
}
23
31
24
/* Invoke a vector expander on three Zregs. */
32
static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
25
-static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
33
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
26
- int esz, int rd, int rn, int rm)
34
return !(result->f.prot & (1 << access_type));
27
+static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
28
+ int esz, int rd, int rn, int rm)
29
{
30
- if (sve_access_check(s)) {
31
- unsigned vsz = vec_full_reg_size(s);
32
- gvec_fn(esz, vec_full_reg_offset(s, rd),
33
- vec_full_reg_offset(s, rn),
34
- vec_full_reg_offset(s, rm), vsz, vsz);
35
- }
36
- return true;
37
+ unsigned vsz = vec_full_reg_size(s);
38
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
39
+ vec_full_reg_offset(s, rn),
40
+ vec_full_reg_offset(s, rm), vsz, vsz);
41
}
35
}
42
36
43
/* Invoke a vector move on two Zregs. */
37
+static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx,
44
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
38
+ uint32_t secure)
45
*** SVE Logical - Unpredicated Group
46
*/
47
48
+static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
49
+{
39
+{
50
+ if (sve_access_check(s)) {
40
+ if (regime_el(env, mmu_idx) == 2) {
51
+ gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
41
+ return env->pmsav8.hprbar;
52
+ }
42
+ } else {
53
+ return true;
43
+ return env->pmsav8.rbar[secure];
44
+ }
54
+}
45
+}
55
+
46
+
56
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
47
+static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx,
57
{
48
+ uint32_t secure)
58
- return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
49
+{
59
+ return do_zzz_fn(s, a, tcg_gen_gvec_and);
50
+ if (regime_el(env, mmu_idx) == 2) {
51
+ return env->pmsav8.hprlar;
52
+ } else {
53
+ return env->pmsav8.rlar[secure];
54
+ }
55
+}
56
+
57
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
58
MMUAccessType access_type, ARMMMUIdx mmu_idx,
59
bool secure, GetPhysAddrResult *result,
60
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
61
bool hit = false;
62
uint32_t addr_page_base = address & TARGET_PAGE_MASK;
63
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
64
+ int region_counter;
65
+
66
+ if (regime_el(env, mmu_idx) == 2) {
67
+ region_counter = cpu->pmsav8r_hdregion;
68
+ } else {
69
+ region_counter = cpu->pmsav7_dregion;
70
+ }
71
72
result->f.lg_page_size = TARGET_PAGE_BITS;
73
result->f.phys_addr = address;
74
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
75
*mregion = -1;
76
}
77
78
+ if (mmu_idx == ARMMMUIdx_Stage2) {
79
+ fi->stage2 = true;
80
+ }
81
+
82
/*
83
* Unlike the ARM ARM pseudocode, we don't need to check whether this
84
* was an exception vector read from the vector table (which is always
85
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
86
hit = true;
87
}
88
89
- for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
90
+ uint32_t bitmask;
91
+ if (arm_feature(env, ARM_FEATURE_M)) {
92
+ bitmask = 0x1f;
93
+ } else {
94
+ bitmask = 0x3f;
95
+ fi->level = 0;
96
+ }
97
+
98
+ for (n = region_counter - 1; n >= 0; n--) {
99
/* region search */
100
/*
101
- * Note that the base address is bits [31:5] from the register
102
- * with bits [4:0] all zeroes, but the limit address is bits
103
- * [31:5] from the register with bits [4:0] all ones.
104
+ * Note that the base address is bits [31:x] from the register
105
+ * with bits [x-1:0] all zeroes, but the limit address is bits
106
+ * [31:x] from the register with bits [x:0] all ones. Where x is
107
+ * 5 for Cortex-M and 6 for Cortex-R
108
*/
109
- uint32_t base = env->pmsav8.rbar[secure][n] & ~0x1f;
110
- uint32_t limit = env->pmsav8.rlar[secure][n] | 0x1f;
111
+ uint32_t base = regime_rbar(env, mmu_idx, secure)[n] & ~bitmask;
112
+ uint32_t limit = regime_rlar(env, mmu_idx, secure)[n] | bitmask;
113
114
- if (!(env->pmsav8.rlar[secure][n] & 0x1)) {
115
+ if (!(regime_rlar(env, mmu_idx, secure)[n] & 0x1)) {
116
/* Region disabled */
117
continue;
118
}
119
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
120
* PMSAv7 where highest-numbered-region wins)
121
*/
122
fi->type = ARMFault_Permission;
123
- fi->level = 1;
124
+ if (arm_feature(env, ARM_FEATURE_M)) {
125
+ fi->level = 1;
126
+ }
127
return true;
128
}
129
130
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
131
}
132
133
if (!hit) {
134
- /* background fault */
135
- fi->type = ARMFault_Background;
136
+ if (arm_feature(env, ARM_FEATURE_M)) {
137
+ fi->type = ARMFault_Background;
138
+ } else {
139
+ fi->type = ARMFault_Permission;
140
+ }
141
return true;
142
}
143
144
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
145
/* hit using the background region */
146
get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
147
} else {
148
- uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
149
- uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
150
+ uint32_t matched_rbar = regime_rbar(env, mmu_idx, secure)[matchregion];
151
+ uint32_t matched_rlar = regime_rlar(env, mmu_idx, secure)[matchregion];
152
+ uint32_t ap = extract32(matched_rbar, 1, 2);
153
+ uint32_t xn = extract32(matched_rbar, 0, 1);
154
bool pxn = false;
155
156
if (arm_feature(env, ARM_FEATURE_V8_1M)) {
157
- pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
158
+ pxn = extract32(matched_rlar, 4, 1);
159
}
160
161
if (m_is_system_region(env, address)) {
162
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
163
xn = 1;
164
}
165
166
- result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
167
+ if (regime_el(env, mmu_idx) == 2) {
168
+ result->f.prot = simple_ap_to_rw_prot_is_user(ap,
169
+ mmu_idx != ARMMMUIdx_E2);
170
+ } else {
171
+ result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
172
+ }
173
+
174
+ if (!arm_feature(env, ARM_FEATURE_M)) {
175
+ uint8_t attrindx = extract32(matched_rlar, 1, 3);
176
+ uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
177
+ uint8_t sh = extract32(matched_rlar, 3, 2);
178
+
179
+ if (regime_sctlr(env, mmu_idx) & SCTLR_WXN &&
180
+ result->f.prot & PAGE_WRITE && mmu_idx != ARMMMUIdx_Stage2) {
181
+ xn = 0x1;
182
+ }
183
+
184
+ if ((regime_el(env, mmu_idx) == 1) &&
185
+ regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap == 0x1) {
186
+ pxn = 0x1;
187
+ }
188
+
189
+ result->cacheattrs.is_s2_format = false;
190
+ result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
191
+ result->cacheattrs.shareability = sh;
192
+ }
193
+
194
if (result->f.prot && !xn && !(pxn && !is_user)) {
195
result->f.prot |= PAGE_EXEC;
196
}
197
- /*
198
- * We don't need to look the attribute up in the MAIR0/MAIR1
199
- * registers because that only tells us about cacheability.
200
- */
201
+
202
if (mregion) {
203
*mregion = matchregion;
204
}
205
}
206
207
fi->type = ARMFault_Permission;
208
- fi->level = 1;
209
+ if (arm_feature(env, ARM_FEATURE_M)) {
210
+ fi->level = 1;
211
+ }
212
return !(result->f.prot & (1 << access_type));
60
}
213
}
61
214
62
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
215
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
63
{
216
cacheattrs1 = result->cacheattrs;
64
- return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
217
memset(result, 0, sizeof(*result));
65
+ return do_zzz_fn(s, a, tcg_gen_gvec_or);
218
66
}
219
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type, is_el0, result, fi);
67
220
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
68
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
221
+ ret = get_phys_addr_pmsav8(env, ipa, access_type,
69
{
222
+ ptw->in_mmu_idx, is_secure, result, fi);
70
- return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
223
+ } else {
71
+ return do_zzz_fn(s, a, tcg_gen_gvec_xor);
224
+ ret = get_phys_addr_lpae(env, ptw, ipa, access_type,
72
}
225
+ is_el0, result, fi);
73
226
+ }
74
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
227
fi->s2addr = ipa;
75
{
228
76
- return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
229
/* Combine the S1 and S2 perms. */
77
+ return do_zzz_fn(s, a, tcg_gen_gvec_andc);
78
}
79
80
/*
81
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
82
83
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
84
{
85
- return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
86
+ return do_zzz_fn(s, a, tcg_gen_gvec_add);
87
}
88
89
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
90
{
91
- return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
92
+ return do_zzz_fn(s, a, tcg_gen_gvec_sub);
93
}
94
95
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
96
{
97
- return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
98
+ return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
99
}
100
101
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
102
{
103
- return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
104
+ return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
105
}
106
107
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
108
{
109
- return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
110
+ return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
111
}
112
113
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
114
{
115
- return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
116
+ return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
117
}
118
119
/*
120
--
230
--
121
2.20.1
231
2.25.1
122
232
123
233
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
4
5
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-12-richard.henderson@linaro.org
7
Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
9
---
8
target/arm/translate-sve.c | 53 +++++++++++++-------------------------
10
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
9
1 file changed, 18 insertions(+), 35 deletions(-)
11
1 file changed, 42 insertions(+)
10
12
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
15
--- a/target/arm/cpu_tcg.c
14
+++ b/target/arm/translate-sve.c
16
+++ b/target/arm/cpu_tcg.c
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
17
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
16
return size_for_gvec(pred_full_reg_size(s));
18
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
17
}
19
}
18
20
19
+/* Invoke an out-of-line helper on 3 Zregs. */
21
+static void cortex_r52_initfn(Object *obj)
20
+static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
21
+ int rd, int rn, int rm, int data)
22
+{
22
+{
23
+ unsigned vsz = vec_full_reg_size(s);
23
+ ARMCPU *cpu = ARM_CPU(obj);
24
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
24
+
25
+ vec_full_reg_offset(s, rn),
25
+ set_feature(&cpu->env, ARM_FEATURE_V8);
26
+ vec_full_reg_offset(s, rm),
26
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
27
+ vsz, vsz, data, fn);
27
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
28
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
29
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
30
+ cpu->midr = 0x411fd133; /* r1p3 */
31
+ cpu->revidr = 0x00000000;
32
+ cpu->reset_fpsid = 0x41034023;
33
+ cpu->isar.mvfr0 = 0x10110222;
34
+ cpu->isar.mvfr1 = 0x12111111;
35
+ cpu->isar.mvfr2 = 0x00000043;
36
+ cpu->ctr = 0x8144c004;
37
+ cpu->reset_sctlr = 0x30c50838;
38
+ cpu->isar.id_pfr0 = 0x00000131;
39
+ cpu->isar.id_pfr1 = 0x10111001;
40
+ cpu->isar.id_dfr0 = 0x03010006;
41
+ cpu->id_afr0 = 0x00000000;
42
+ cpu->isar.id_mmfr0 = 0x00211040;
43
+ cpu->isar.id_mmfr1 = 0x40000000;
44
+ cpu->isar.id_mmfr2 = 0x01200000;
45
+ cpu->isar.id_mmfr3 = 0xf0102211;
46
+ cpu->isar.id_mmfr4 = 0x00000010;
47
+ cpu->isar.id_isar0 = 0x02101110;
48
+ cpu->isar.id_isar1 = 0x13112111;
49
+ cpu->isar.id_isar2 = 0x21232142;
50
+ cpu->isar.id_isar3 = 0x01112131;
51
+ cpu->isar.id_isar4 = 0x00010142;
52
+ cpu->isar.id_isar5 = 0x00010001;
53
+ cpu->isar.dbgdidr = 0x77168000;
54
+ cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
55
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
56
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
57
+
58
+ cpu->pmsav7_dregion = 16;
59
+ cpu->pmsav8r_hdregion = 16;
28
+}
60
+}
29
+
61
+
30
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
62
static void cortex_r5f_initfn(Object *obj)
31
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
32
int rd, int rn, int pg, int data)
33
@@ -XXX,XX +XXX,XX @@ static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
34
return false;
35
}
36
if (sve_access_check(s)) {
37
- unsigned vsz = vec_full_reg_size(s);
38
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
39
- vec_full_reg_offset(s, a->rn),
40
- vec_full_reg_offset(s, a->rm),
41
- vsz, vsz, 0, fn);
42
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
43
}
44
return true;
45
}
46
@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
47
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
48
{
63
{
49
if (sve_access_check(s)) {
64
ARMCPU *cpu = ARM_CPU(obj);
50
- unsigned vsz = vec_full_reg_size(s);
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_tcg_cpus[] = {
51
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
66
.class_init = arm_v7m_class_init },
52
- vec_full_reg_offset(s, a->rn),
67
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
53
- vec_full_reg_offset(s, a->rm),
68
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
54
- vsz, vsz, a->imm, fn);
69
+ { .name = "cortex-r52", .initfn = cortex_r52_initfn },
55
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
70
{ .name = "ti925t", .initfn = ti925t_initfn },
56
}
71
{ .name = "sa1100", .initfn = sa1100_initfn },
57
return true;
72
{ .name = "sa1110", .initfn = sa1110_initfn },
58
}
59
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
60
return false;
61
}
62
if (sve_access_check(s)) {
63
- unsigned vsz = vec_full_reg_size(s);
64
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
65
- vec_full_reg_offset(s, a->rn),
66
- vec_full_reg_offset(s, a->rm),
67
- vsz, vsz, 0, fns[a->esz]);
68
+ gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
69
}
70
return true;
71
}
72
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
73
};
74
75
if (sve_access_check(s)) {
76
- unsigned vsz = vec_full_reg_size(s);
77
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
78
- vec_full_reg_offset(s, a->rn),
79
- vec_full_reg_offset(s, a->rm),
80
- vsz, vsz, 0, fns[a->esz]);
81
+ gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
82
}
83
return true;
84
}
85
@@ -XXX,XX +XXX,XX @@ static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
86
gen_helper_gvec_3 *fn)
87
{
88
if (sve_access_check(s)) {
89
- unsigned vsz = vec_full_reg_size(s);
90
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
91
- vec_full_reg_offset(s, a->rn),
92
- vec_full_reg_offset(s, a->rm),
93
- vsz, vsz, data, fn);
94
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
95
}
96
return true;
97
}
98
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a)
99
};
100
101
if (sve_access_check(s)) {
102
- unsigned vsz = vec_full_reg_size(s);
103
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
104
- vec_full_reg_offset(s, a->rn),
105
- vec_full_reg_offset(s, a->rm),
106
- vsz, vsz, 0, fns[a->u][a->sz]);
107
+ gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, 0);
108
}
109
return true;
110
}
111
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a)
112
};
113
114
if (sve_access_check(s)) {
115
- unsigned vsz = vec_full_reg_size(s);
116
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
117
- vec_full_reg_offset(s, a->rn),
118
- vec_full_reg_offset(s, a->rm),
119
- vsz, vsz, a->index, fns[a->u][a->sz]);
120
+ gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->index);
121
}
122
return true;
123
}
124
--
73
--
125
2.20.1
74
2.25.1
126
75
127
76
diff view generated by jsdifflib
1
From: Graeme Gregory <graeme@nuviainc.com>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Fixing a typo in a previous patch that translated an "i" to a 1
3
The check semihosting_enabled() wants to know if the guest is
4
and therefore breaking the allocation of PCIe interrupts. This was
4
currently in user mode. Unlike the other cases the test was inverted
5
discovered when virtio-net-pci devices ceased to function correctly.
5
causing us to block semihosting calls in non-EL0 modes.
6
6
7
Cc: qemu-stable@nongnu.org
7
Cc: qemu-stable@nongnu.org
8
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state")
8
Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on)
9
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200821083853.356490-1-graeme@nuviainc.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
12
---
14
hw/arm/sbsa-ref.c | 2 +-
13
target/arm/translate.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
16
15
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/sbsa-ref.c
18
--- a/target/arm/translate.c
20
+++ b/hw/arm/sbsa-ref.c
19
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ static void create_pcie(SBSAMachineState *sms)
20
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
22
21
* semihosting, to provide some semblance of security
23
for (i = 0; i < GPEX_NUM_IRQS; i++) {
22
* (and for consistency with our 32-bit semihosting).
24
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
23
*/
25
- qdev_get_gpio_in(sms->gic, irq + 1));
24
- if (semihosting_enabled(s->current_el != 0) &&
26
+ qdev_get_gpio_in(sms->gic, irq + i));
25
+ if (semihosting_enabled(s->current_el == 0) &&
27
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
26
(imm == (s->thumb ? 0x3c : 0xf000))) {
28
}
27
gen_exception_internal_insn(s, EXCP_SEMIHOST);
29
28
return;
30
--
29
--
31
2.20.1
30
2.25.1
32
31
33
32
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
The gvec operation was added after the initial implementation
3
Fix typos, add background information
4
of the SEL instruction and was missed in the conversion.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200815013145.539409-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
target/arm/translate-sve.c | 31 ++++++++-----------------------
9
hw/timer/imx_epit.c | 20 ++++++++++++++++----
12
1 file changed, 8 insertions(+), 23 deletions(-)
10
1 file changed, 16 insertions(+), 4 deletions(-)
13
11
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
14
--- a/hw/timer/imx_epit.c
17
+++ b/target/arm/translate-sve.c
15
+++ b/hw/timer/imx_epit.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
16
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
19
return do_pppp_flags(s, a, &op);
17
}
20
}
18
}
21
19
22
-static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
20
+/*
23
-{
21
+ * This is called both on hardware (device) reset and software reset.
24
- tcg_gen_and_i64(pn, pn, pg);
22
+ */
25
- tcg_gen_andc_i64(pm, pm, pg);
23
static void imx_epit_reset(DeviceState *dev)
26
- tcg_gen_or_i64(pd, pn, pm);
27
-}
28
-
29
-static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn,
30
- TCGv_vec pm, TCGv_vec pg)
31
-{
32
- tcg_gen_and_vec(vece, pn, pn, pg);
33
- tcg_gen_andc_vec(vece, pm, pm, pg);
34
- tcg_gen_or_vec(vece, pd, pn, pm);
35
-}
36
-
37
static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
38
{
24
{
39
- static const GVecGen4 op = {
25
IMXEPITState *s = IMX_EPIT(dev);
40
- .fni8 = gen_sel_pg_i64,
26
41
- .fniv = gen_sel_pg_vec,
27
- /*
42
- .fno = gen_helper_sve_sel_pppp,
28
- * Soft reset doesn't touch some bits; hard reset clears them
43
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
29
- */
44
- };
30
+ /* Soft reset doesn't touch some bits; hard reset clears them */
45
-
31
s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
46
if (a->s) {
32
s->sr = 0;
47
return false;
33
s->lr = EPIT_TIMER_MAX;
48
}
34
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
49
- return do_pppp_flags(s, a, &op);
35
ptimer_transaction_begin(s->timer_cmp);
50
+ if (sve_access_check(s)) {
36
ptimer_transaction_begin(s->timer_reload);
51
+ unsigned psz = pred_gvec_reg_size(s);
37
52
+ tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd),
38
+ /* Update the frequency. Has been done already in case of a reset. */
53
+ pred_full_reg_offset(s, a->pg),
39
if (!(s->cr & CR_SWR)) {
54
+ pred_full_reg_offset(s, a->rn),
40
imx_epit_set_freq(s);
55
+ pred_full_reg_offset(s, a->rm), psz, psz);
41
}
56
+ }
42
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
57
+ return true;
43
break;
44
45
case 1: /* SR - ACK*/
46
- /* writing 1 to OCIF clear the OCIF bit */
47
+ /* writing 1 to OCIF clears the OCIF bit */
48
if (value & 0x01) {
49
s->sr = 0;
50
imx_epit_update_int(s);
51
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
52
0x00001000);
53
sysbus_init_mmio(sbd, &s->iomem);
54
55
+ /*
56
+ * The reload timer keeps running when the peripheral is enabled. It is a
57
+ * kind of wall clock that does not generate any interrupts. The callback
58
+ * needs to be provided, but it does nothing as the ptimer already supports
59
+ * all necessary reloading functionality.
60
+ */
61
s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
62
63
+ /*
64
+ * The compare timer is running only when the peripheral configuration is
65
+ * in a state that will generate compare interrupts.
66
+ */
67
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
58
}
68
}
59
69
60
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
61
--
70
--
62
2.20.1
71
2.25.1
63
64
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
This is the only user of the function.
3
remove unused defines, add needed defines
4
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
8
---
10
target/arm/translate-sve.c | 19 ++++++-------------
9
include/hw/timer/imx_epit.h | 4 ++--
11
1 file changed, 6 insertions(+), 13 deletions(-)
10
hw/timer/imx_epit.c | 4 ++--
11
2 files changed, 4 insertions(+), 4 deletions(-)
12
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
15
--- a/include/hw/timer/imx_epit.h
16
+++ b/target/arm/translate-sve.c
16
+++ b/include/hw/timer/imx_epit.h
17
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
17
@@ -XXX,XX +XXX,XX @@
18
tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
18
#define CR_OCIEN (1 << 2)
19
}
19
#define CR_RLD (1 << 3)
20
20
#define CR_PRESCALE_SHIFT (4)
21
-/* Invoke a vector expander on two Pregs. */
21
-#define CR_PRESCALE_MASK (0xfff)
22
-static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn,
22
+#define CR_PRESCALE_BITS (12)
23
- int esz, int rd, int rn)
23
#define CR_SWR (1 << 16)
24
-{
24
#define CR_IOVW (1 << 17)
25
- if (sve_access_check(s)) {
25
#define CR_DBGEN (1 << 18)
26
- unsigned psz = pred_gvec_reg_size(s);
26
@@ -XXX,XX +XXX,XX @@
27
- gvec_fn(esz, pred_full_reg_offset(s, rd),
27
#define CR_DOZEN (1 << 20)
28
- pred_full_reg_offset(s, rn), psz, psz);
28
#define CR_STOPEN (1 << 21)
29
- }
29
#define CR_CLKSRC_SHIFT (24)
30
- return true;
30
-#define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
31
-}
31
+#define CR_CLKSRC_BITS (2)
32
-
32
33
/* Invoke a vector expander on three Pregs. */
33
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
34
static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
34
35
int esz, int rd, int rn, int rm)
35
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
36
@@ -XXX,XX +XXX,XX @@ static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op,
36
index XXXXXXX..XXXXXXX 100644
37
/* Invoke a vector move on two Pregs. */
37
--- a/hw/timer/imx_epit.c
38
static bool do_mov_p(DisasContext *s, int rd, int rn)
38
+++ b/hw/timer/imx_epit.c
39
{
39
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
40
- return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn);
40
uint32_t clksrc;
41
+ if (sve_access_check(s)) {
41
uint32_t prescaler;
42
+ unsigned psz = pred_gvec_reg_size(s);
42
43
+ tcg_gen_gvec_mov(MO_8, pred_full_reg_offset(s, rd),
43
- clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
44
+ pred_full_reg_offset(s, rn), psz, psz);
44
- prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
45
+ }
45
+ clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
46
+ return true;
46
+ prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
47
}
47
48
48
s->freq = imx_ccm_get_clock_frequency(s->ccm,
49
/* Set the cpu flags as per a return from an SVE helper. */
49
imx_epit_clocks[clksrc]) / prescaler;
50
--
50
--
51
2.20.1
51
2.25.1
52
53
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
We want to ensure that access is checked by the time we ask
4
for a specific fp/vector register. We want to ensure that
5
we do not emit two lots of code to raise an exception.
6
7
But sometimes it's difficult to cleanly organize the code
8
such that we never pass through sve_check_access exactly once.
9
Allow multiple calls so long as the result is true, that is,
10
no exception to be raised.
11
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20200815013145.539409-5-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
5
---
17
target/arm/translate.h | 1 +
6
include/hw/timer/imx_epit.h | 2 ++
18
target/arm/translate-a64.c | 27 ++++++++++++++++-----------
7
hw/timer/imx_epit.c | 12 ++++++------
19
2 files changed, 17 insertions(+), 11 deletions(-)
8
2 files changed, 8 insertions(+), 6 deletions(-)
20
9
21
diff --git a/target/arm/translate.h b/target/arm/translate.h
10
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
22
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/translate.h
12
--- a/include/hw/timer/imx_epit.h
24
+++ b/target/arm/translate.h
13
+++ b/include/hw/timer/imx_epit.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
14
@@ -XXX,XX +XXX,XX @@
26
* that it is set at the point where we actually touch the FP regs.
15
#define CR_CLKSRC_SHIFT (24)
27
*/
16
#define CR_CLKSRC_BITS (2)
28
bool fp_access_checked;
17
29
+ bool sve_access_checked;
18
+#define SR_OCIF (1 << 0)
30
/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
19
+
31
* single-step support).
20
#define EPIT_TIMER_MAX 0XFFFFFFFFUL
32
*/
21
33
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
22
#define TYPE_IMX_EPIT "imx.epit"
23
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
34
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-a64.c
25
--- a/hw/timer/imx_epit.c
36
+++ b/target/arm/translate-a64.c
26
+++ b/hw/timer/imx_epit.c
37
@@ -XXX,XX +XXX,XX @@ static void do_vec_ld(DisasContext *s, int destidx, int element,
27
@@ -XXX,XX +XXX,XX @@ static const IMXClk imx_epit_clocks[] = {
38
* unallocated-encoding checks (otherwise the syndrome information
39
* for the resulting exception will be incorrect).
40
*/
28
*/
41
-static inline bool fp_access_check(DisasContext *s)
29
static void imx_epit_update_int(IMXEPITState *s)
42
+static bool fp_access_check(DisasContext *s)
43
{
30
{
44
- assert(!s->fp_access_checked);
31
- if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
45
- s->fp_access_checked = true;
32
+ if ((s->sr & SR_OCIF) && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
46
+ if (s->fp_excp_el) {
33
qemu_irq_raise(s->irq);
47
+ assert(!s->fp_access_checked);
34
} else {
48
+ s->fp_access_checked = true;
35
qemu_irq_lower(s->irq);
49
36
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
50
- if (!s->fp_excp_el) {
37
break;
51
- return true;
38
52
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
39
case 1: /* SR - ACK*/
53
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
40
- /* writing 1 to OCIF clears the OCIF bit */
54
+ return false;
41
- if (value & 0x01) {
55
}
42
- s->sr = 0;
43
+ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
44
+ if (value & SR_OCIF) {
45
+ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
46
imx_epit_update_int(s);
47
}
48
break;
49
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
50
IMXEPITState *s = IMX_EPIT(opaque);
51
52
DPRINTF("sr was %d\n", s->sr);
56
-
53
-
57
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
54
- s->sr = 1;
58
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
55
+ /* Set interrupt status bit SR.OCIF and update the interrupt state */
59
- return false;
56
+ s->sr |= SR_OCIF;
60
+ s->fp_access_checked = true;
57
imx_epit_update_int(s);
61
+ return true;
62
}
58
}
63
59
64
/* Check that SVE access is enabled. If it is, return true.
65
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
66
bool sve_access_check(DisasContext *s)
67
{
68
if (s->sve_excp_el) {
69
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
70
- s->sve_excp_el);
71
+ assert(!s->sve_access_checked);
72
+ s->sve_access_checked = true;
73
+
74
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
75
+ syn_sve_access_trap(), s->sve_excp_el);
76
return false;
77
}
78
+ s->sve_access_checked = true;
79
return fp_access_check(s);
80
}
81
82
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
83
s->base.pc_next += 4;
84
85
s->fp_access_checked = false;
86
+ s->sve_access_checked = false;
87
88
if (dc_isar_feature(aa64_bti, s)) {
89
if (s->base.num_insns == 1) {
90
--
60
--
91
2.20.1
61
2.25.1
92
93
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
As we want to call qdev_connect_clock_in() before the device
3
The interrupt state can change due to:
4
is realized, we need to uninline cadence_uart_create() first.
4
- reset clears both SR.OCIF and CR.OCIE
5
- write to CR.EN or CR.OCIE
5
6
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200803105647.22223-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
include/hw/char/cadence_uart.h | 17 -----------------
11
hw/timer/imx_epit.c | 16 ++++++++++++----
12
hw/arm/xilinx_zynq.c | 14 ++++++++++++--
12
1 file changed, 12 insertions(+), 4 deletions(-)
13
2 files changed, 12 insertions(+), 19 deletions(-)
14
13
15
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
14
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/char/cadence_uart.h
16
--- a/hw/timer/imx_epit.c
18
+++ b/include/hw/char/cadence_uart.h
17
+++ b/hw/timer/imx_epit.c
19
@@ -XXX,XX +XXX,XX @@ typedef struct {
18
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
20
Clock *refclk;
19
if (s->cr & CR_SWR) {
21
} CadenceUARTState;
20
/* handle the reset */
22
21
imx_epit_reset(DEVICE(s));
23
-static inline DeviceState *cadence_uart_create(hwaddr addr,
22
- /*
24
- qemu_irq irq,
23
- * TODO: could we 'break' here? following operations appear
25
- Chardev *chr)
24
- * to duplicate the work imx_epit_reset() already did.
26
-{
25
- */
27
- DeviceState *dev;
26
}
28
- SysBusDevice *s;
27
29
-
28
+ /*
30
- dev = qdev_new(TYPE_CADENCE_UART);
29
+ * The interrupt state can change due to:
31
- s = SYS_BUS_DEVICE(dev);
30
+ * - reset clears both SR.OCIF and CR.OCIE
32
- qdev_prop_set_chr(dev, "chardev", chr);
31
+ * - write to CR.EN or CR.OCIE
33
- sysbus_realize_and_unref(s, &error_fatal);
32
+ */
34
- sysbus_mmio_map(s, 0, addr);
33
+ imx_epit_update_int(s);
35
- sysbus_connect_irq(s, 0, irq);
34
+
36
-
35
+ /*
37
- return dev;
36
+ * TODO: could we 'break' here for reset? following operations appear
38
-}
37
+ * to duplicate the work imx_epit_reset() already did.
39
-
38
+ */
40
#endif
39
+
41
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
40
ptimer_transaction_begin(s->timer_cmp);
42
index XXXXXXX..XXXXXXX 100644
41
ptimer_transaction_begin(s->timer_reload);
43
--- a/hw/arm/xilinx_zynq.c
44
+++ b/hw/arm/xilinx_zynq.c
45
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
46
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
47
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
48
49
- dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
50
+ dev = qdev_new(TYPE_CADENCE_UART);
51
+ busdev = SYS_BUS_DEVICE(dev);
52
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
53
+ sysbus_realize_and_unref(busdev, &error_fatal);
54
+ sysbus_mmio_map(busdev, 0, 0xE0000000);
55
+ sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
56
qdev_connect_clock_in(dev, "refclk",
57
qdev_get_clock_out(slcr, "uart0_ref_clk"));
58
- dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
59
+ dev = qdev_new(TYPE_CADENCE_UART);
60
+ busdev = SYS_BUS_DEVICE(dev);
61
+ qdev_prop_set_chr(dev, "chardev", serial_hd(1));
62
+ sysbus_realize_and_unref(busdev, &error_fatal);
63
+ sysbus_mmio_map(busdev, 0, 0xE0001000);
64
+ sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
65
qdev_connect_clock_in(dev, "refclk",
66
qdev_get_clock_out(slcr, "uart1_ref_clk"));
67
42
68
--
43
--
69
2.20.1
44
2.25.1
70
71
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
Model after gen_gvec_fn_zzz et al.
3
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-11-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
6
---
10
target/arm/translate-sve.c | 29 ++++++++++++++---------------
7
hw/timer/imx_epit.c | 20 ++++++++++++++------
11
1 file changed, 14 insertions(+), 15 deletions(-)
8
1 file changed, 14 insertions(+), 6 deletions(-)
12
9
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
10
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
12
--- a/hw/timer/imx_epit.c
16
+++ b/target/arm/translate-sve.c
13
+++ b/hw/timer/imx_epit.c
17
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
14
@@ -XXX,XX +XXX,XX @@ static void imx_epit_set_freq(IMXEPITState *s)
18
return size_for_gvec(pred_full_reg_size(s));
15
/*
16
* This is called both on hardware (device) reset and software reset.
17
*/
18
-static void imx_epit_reset(DeviceState *dev)
19
+static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
20
{
21
- IMXEPITState *s = IMX_EPIT(dev);
22
-
23
/* Soft reset doesn't touch some bits; hard reset clears them */
24
- s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
25
+ if (is_hard_reset) {
26
+ s->cr = 0;
27
+ } else {
28
+ s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
29
+ }
30
s->sr = 0;
31
s->lr = EPIT_TIMER_MAX;
32
s->cmp = 0;
33
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
34
s->cr = value & 0x03ffffff;
35
if (s->cr & CR_SWR) {
36
/* handle the reset */
37
- imx_epit_reset(DEVICE(s));
38
+ imx_epit_reset(s, false);
39
}
40
41
/*
42
@@ -XXX,XX +XXX,XX @@ static void imx_epit_realize(DeviceState *dev, Error **errp)
43
s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
19
}
44
}
20
45
21
+/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
46
+static void imx_epit_dev_reset(DeviceState *dev)
22
+static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
23
+ int rd, int rn, int pg, int data)
24
+{
47
+{
25
+ unsigned vsz = vec_full_reg_size(s);
48
+ IMXEPITState *s = IMX_EPIT(dev);
26
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
49
+ imx_epit_reset(s, true);
27
+ vec_full_reg_offset(s, rn),
28
+ pred_full_reg_offset(s, pg),
29
+ vsz, vsz, data, fn);
30
+}
50
+}
31
+
51
+
32
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
52
static void imx_epit_class_init(ObjectClass *klass, void *data)
33
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
34
int rd, int rn, int rm, int pg, int data)
35
@@ -XXX,XX +XXX,XX @@ static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
36
return false;
37
}
38
if (sve_access_check(s)) {
39
- unsigned vsz = vec_full_reg_size(s);
40
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
41
- vec_full_reg_offset(s, a->rn),
42
- pred_full_reg_offset(s, a->pg),
43
- vsz, vsz, 0, fn);
44
+ gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
45
}
46
return true;
47
}
48
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
49
};
50
51
if (sve_access_check(s)) {
52
- unsigned vsz = vec_full_reg_size(s);
53
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
54
- vec_full_reg_offset(s, rn),
55
- pred_full_reg_offset(s, pg),
56
- vsz, vsz, invert, fns[esz]);
57
+ gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
58
}
59
return true;
60
}
61
@@ -XXX,XX +XXX,XX @@ static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
62
gen_helper_gvec_3 *fn)
63
{
53
{
64
if (sve_access_check(s)) {
54
DeviceClass *dc = DEVICE_CLASS(klass);
65
- unsigned vsz = vec_full_reg_size(s);
55
66
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
56
dc->realize = imx_epit_realize;
67
- vec_full_reg_offset(s, a->rn),
57
- dc->reset = imx_epit_reset;
68
- pred_full_reg_offset(s, a->pg),
58
+ dc->reset = imx_epit_dev_reset;
69
- vsz, vsz, a->imm, fn);
59
dc->vmsd = &vmstate_imx_timer_epit;
70
+ gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
60
dc->desc = "i.MX periodic timer";
71
}
72
return true;
73
}
61
}
74
--
62
--
75
2.20.1
63
2.25.1
76
77
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
The existing clr functions have only one vector argument, and so
3
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
4
can only clear in place. The existing movz functions have two
5
vector arguments, and so can clear while moving. Merge them, with
6
a flag that controls the sense of active vs inactive elements
7
being cleared.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200815013145.539409-10-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
6
---
14
target/arm/helper-sve.h | 5 ---
7
hw/timer/imx_epit.c | 215 ++++++++++++++++++++++++--------------------
15
target/arm/sve_helper.c | 70 ++++++++------------------------------
8
1 file changed, 117 insertions(+), 98 deletions(-)
16
target/arm/translate-sve.c | 53 +++++++++++------------------
17
3 files changed, 34 insertions(+), 94 deletions(-)
18
9
19
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
10
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper-sve.h
12
--- a/hw/timer/imx_epit.c
22
+++ b/target/arm/helper-sve.h
13
+++ b/hw/timer/imx_epit.c
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sve_uminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
14
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
24
DEF_HELPER_FLAGS_3(sve_uminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
25
DEF_HELPER_FLAGS_3(sve_uminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
26
27
-DEF_HELPER_FLAGS_3(sve_clr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
28
-DEF_HELPER_FLAGS_3(sve_clr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
29
-DEF_HELPER_FLAGS_3(sve_clr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
30
-DEF_HELPER_FLAGS_3(sve_clr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
31
-
32
DEF_HELPER_FLAGS_4(sve_movz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
DEF_HELPER_FLAGS_4(sve_movz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(sve_movz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
35
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/sve_helper.c
38
+++ b/target/arm/sve_helper.c
39
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc)
40
return flags;
41
}
42
43
-/* Store zero into every active element of Zd. We will use this for two
44
- * and three-operand predicated instructions for which logic dictates a
45
- * zero result. In particular, logical shift by element size, which is
46
- * otherwise undefined on the host.
47
- *
48
- * For element sizes smaller than uint64_t, we use tables to expand
49
- * the N bits of the controlling predicate to a byte mask, and clear
50
- * those bytes.
51
+/*
52
+ * Copy Zn into Zd, and store zero into inactive elements.
53
+ * If inv, store zeros into the active elements.
54
*/
55
-void HELPER(sve_clr_b)(void *vd, void *vg, uint32_t desc)
56
-{
57
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
58
- uint64_t *d = vd;
59
- uint8_t *pg = vg;
60
- for (i = 0; i < opr_sz; i += 1) {
61
- d[i] &= ~expand_pred_b(pg[H1(i)]);
62
- }
63
-}
64
-
65
-void HELPER(sve_clr_h)(void *vd, void *vg, uint32_t desc)
66
-{
67
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
68
- uint64_t *d = vd;
69
- uint8_t *pg = vg;
70
- for (i = 0; i < opr_sz; i += 1) {
71
- d[i] &= ~expand_pred_h(pg[H1(i)]);
72
- }
73
-}
74
-
75
-void HELPER(sve_clr_s)(void *vd, void *vg, uint32_t desc)
76
-{
77
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
78
- uint64_t *d = vd;
79
- uint8_t *pg = vg;
80
- for (i = 0; i < opr_sz; i += 1) {
81
- d[i] &= ~expand_pred_s(pg[H1(i)]);
82
- }
83
-}
84
-
85
-void HELPER(sve_clr_d)(void *vd, void *vg, uint32_t desc)
86
-{
87
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
88
- uint64_t *d = vd;
89
- uint8_t *pg = vg;
90
- for (i = 0; i < opr_sz; i += 1) {
91
- if (pg[H1(i)] & 1) {
92
- d[i] = 0;
93
- }
94
- }
95
-}
96
-
97
-/* Copy Zn into Zd, and store zero into inactive elements. */
98
void HELPER(sve_movz_b)(void *vd, void *vn, void *vg, uint32_t desc)
99
{
100
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
101
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
102
uint64_t *d = vd, *n = vn;
103
uint8_t *pg = vg;
104
+
105
for (i = 0; i < opr_sz; i += 1) {
106
- d[i] = n[i] & expand_pred_b(pg[H1(i)]);
107
+ d[i] = n[i] & (expand_pred_b(pg[H1(i)]) ^ inv);
108
}
15
}
109
}
16
}
110
17
111
void HELPER(sve_movz_h)(void *vd, void *vn, void *vg, uint32_t desc)
18
+static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
19
+{
20
+ uint32_t oldcr = s->cr;
21
+
22
+ s->cr = value & 0x03ffffff;
23
+
24
+ if (s->cr & CR_SWR) {
25
+ /* handle the reset */
26
+ imx_epit_reset(s, false);
27
+ }
28
+
29
+ /*
30
+ * The interrupt state can change due to:
31
+ * - reset clears both SR.OCIF and CR.OCIE
32
+ * - write to CR.EN or CR.OCIE
33
+ */
34
+ imx_epit_update_int(s);
35
+
36
+ /*
37
+ * TODO: could we 'break' here for reset? following operations appear
38
+ * to duplicate the work imx_epit_reset() already did.
39
+ */
40
+
41
+ ptimer_transaction_begin(s->timer_cmp);
42
+ ptimer_transaction_begin(s->timer_reload);
43
+
44
+ /* Update the frequency. Has been done already in case of a reset. */
45
+ if (!(s->cr & CR_SWR)) {
46
+ imx_epit_set_freq(s);
47
+ }
48
+
49
+ if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
50
+ if (s->cr & CR_ENMOD) {
51
+ if (s->cr & CR_RLD) {
52
+ ptimer_set_limit(s->timer_reload, s->lr, 1);
53
+ ptimer_set_limit(s->timer_cmp, s->lr, 1);
54
+ } else {
55
+ ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
56
+ ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
57
+ }
58
+ }
59
+
60
+ imx_epit_reload_compare_timer(s);
61
+ ptimer_run(s->timer_reload, 0);
62
+ if (s->cr & CR_OCIEN) {
63
+ ptimer_run(s->timer_cmp, 0);
64
+ } else {
65
+ ptimer_stop(s->timer_cmp);
66
+ }
67
+ } else if (!(s->cr & CR_EN)) {
68
+ /* stop both timers */
69
+ ptimer_stop(s->timer_reload);
70
+ ptimer_stop(s->timer_cmp);
71
+ } else if (s->cr & CR_OCIEN) {
72
+ if (!(oldcr & CR_OCIEN)) {
73
+ imx_epit_reload_compare_timer(s);
74
+ ptimer_run(s->timer_cmp, 0);
75
+ }
76
+ } else {
77
+ ptimer_stop(s->timer_cmp);
78
+ }
79
+
80
+ ptimer_transaction_commit(s->timer_cmp);
81
+ ptimer_transaction_commit(s->timer_reload);
82
+}
83
+
84
+static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
85
+{
86
+ /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
87
+ if (value & SR_OCIF) {
88
+ s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
89
+ imx_epit_update_int(s);
90
+ }
91
+}
92
+
93
+static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
94
+{
95
+ s->lr = value;
96
+
97
+ ptimer_transaction_begin(s->timer_cmp);
98
+ ptimer_transaction_begin(s->timer_reload);
99
+ if (s->cr & CR_RLD) {
100
+ /* Also set the limit if the LRD bit is set */
101
+ /* If IOVW bit is set then set the timer value */
102
+ ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
103
+ ptimer_set_limit(s->timer_cmp, s->lr, 0);
104
+ } else if (s->cr & CR_IOVW) {
105
+ /* If IOVW bit is set then set the timer value */
106
+ ptimer_set_count(s->timer_reload, s->lr);
107
+ }
108
+ /*
109
+ * Commit the change to s->timer_reload, so it can propagate. Otherwise
110
+ * the timer interrupt may not fire properly. The commit must happen
111
+ * before calling imx_epit_reload_compare_timer(), which reads
112
+ * s->timer_reload internally again.
113
+ */
114
+ ptimer_transaction_commit(s->timer_reload);
115
+ imx_epit_reload_compare_timer(s);
116
+ ptimer_transaction_commit(s->timer_cmp);
117
+}
118
+
119
+static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
120
+{
121
+ s->cmp = value;
122
+
123
+ ptimer_transaction_begin(s->timer_cmp);
124
+ imx_epit_reload_compare_timer(s);
125
+ ptimer_transaction_commit(s->timer_cmp);
126
+}
127
+
128
static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
129
unsigned size)
112
{
130
{
113
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
131
IMXEPITState *s = IMX_EPIT(opaque);
114
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
132
- uint64_t oldcr;
115
uint64_t *d = vd, *n = vn;
133
116
uint8_t *pg = vg;
134
DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
117
+
135
(uint32_t)value);
118
for (i = 0; i < opr_sz; i += 1) {
136
119
- d[i] = n[i] & expand_pred_h(pg[H1(i)]);
137
switch (offset >> 2) {
120
+ d[i] = n[i] & (expand_pred_h(pg[H1(i)]) ^ inv);
138
case 0: /* CR */
139
-
140
- oldcr = s->cr;
141
- s->cr = value & 0x03ffffff;
142
- if (s->cr & CR_SWR) {
143
- /* handle the reset */
144
- imx_epit_reset(s, false);
145
- }
146
-
147
- /*
148
- * The interrupt state can change due to:
149
- * - reset clears both SR.OCIF and CR.OCIE
150
- * - write to CR.EN or CR.OCIE
151
- */
152
- imx_epit_update_int(s);
153
-
154
- /*
155
- * TODO: could we 'break' here for reset? following operations appear
156
- * to duplicate the work imx_epit_reset() already did.
157
- */
158
-
159
- ptimer_transaction_begin(s->timer_cmp);
160
- ptimer_transaction_begin(s->timer_reload);
161
-
162
- /* Update the frequency. Has been done already in case of a reset. */
163
- if (!(s->cr & CR_SWR)) {
164
- imx_epit_set_freq(s);
165
- }
166
-
167
- if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
168
- if (s->cr & CR_ENMOD) {
169
- if (s->cr & CR_RLD) {
170
- ptimer_set_limit(s->timer_reload, s->lr, 1);
171
- ptimer_set_limit(s->timer_cmp, s->lr, 1);
172
- } else {
173
- ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
174
- ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
175
- }
176
- }
177
-
178
- imx_epit_reload_compare_timer(s);
179
- ptimer_run(s->timer_reload, 0);
180
- if (s->cr & CR_OCIEN) {
181
- ptimer_run(s->timer_cmp, 0);
182
- } else {
183
- ptimer_stop(s->timer_cmp);
184
- }
185
- } else if (!(s->cr & CR_EN)) {
186
- /* stop both timers */
187
- ptimer_stop(s->timer_reload);
188
- ptimer_stop(s->timer_cmp);
189
- } else if (s->cr & CR_OCIEN) {
190
- if (!(oldcr & CR_OCIEN)) {
191
- imx_epit_reload_compare_timer(s);
192
- ptimer_run(s->timer_cmp, 0);
193
- }
194
- } else {
195
- ptimer_stop(s->timer_cmp);
196
- }
197
-
198
- ptimer_transaction_commit(s->timer_cmp);
199
- ptimer_transaction_commit(s->timer_reload);
200
+ imx_epit_write_cr(s, (uint32_t)value);
201
break;
202
203
- case 1: /* SR - ACK*/
204
- /* writing 1 to SR.OCIF clears this bit and turns the interrupt off */
205
- if (value & SR_OCIF) {
206
- s->sr = 0; /* SR.OCIF is the only bit in this register anyway */
207
- imx_epit_update_int(s);
208
- }
209
+ case 1: /* SR */
210
+ imx_epit_write_sr(s, (uint32_t)value);
211
break;
212
213
- case 2: /* LR - set ticks */
214
- s->lr = value;
215
-
216
- ptimer_transaction_begin(s->timer_cmp);
217
- ptimer_transaction_begin(s->timer_reload);
218
- if (s->cr & CR_RLD) {
219
- /* Also set the limit if the LRD bit is set */
220
- /* If IOVW bit is set then set the timer value */
221
- ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
222
- ptimer_set_limit(s->timer_cmp, s->lr, 0);
223
- } else if (s->cr & CR_IOVW) {
224
- /* If IOVW bit is set then set the timer value */
225
- ptimer_set_count(s->timer_reload, s->lr);
226
- }
227
- /*
228
- * Commit the change to s->timer_reload, so it can propagate. Otherwise
229
- * the timer interrupt may not fire properly. The commit must happen
230
- * before calling imx_epit_reload_compare_timer(), which reads
231
- * s->timer_reload internally again.
232
- */
233
- ptimer_transaction_commit(s->timer_reload);
234
- imx_epit_reload_compare_timer(s);
235
- ptimer_transaction_commit(s->timer_cmp);
236
+ case 2: /* LR */
237
+ imx_epit_write_lr(s, (uint32_t)value);
238
break;
239
240
case 3: /* CMP */
241
- s->cmp = value;
242
-
243
- ptimer_transaction_begin(s->timer_cmp);
244
- imx_epit_reload_compare_timer(s);
245
- ptimer_transaction_commit(s->timer_cmp);
246
-
247
+ imx_epit_write_cmp(s, (uint32_t)value);
248
break;
249
250
default:
251
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
252
HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
253
-
254
break;
121
}
255
}
122
}
256
}
123
257
+
124
void HELPER(sve_movz_s)(void *vd, void *vn, void *vg, uint32_t desc)
258
static void imx_epit_cmp(void *opaque)
125
{
259
{
126
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
260
IMXEPITState *s = IMX_EPIT(opaque);
127
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
128
uint64_t *d = vd, *n = vn;
129
uint8_t *pg = vg;
130
+
131
for (i = 0; i < opr_sz; i += 1) {
132
- d[i] = n[i] & expand_pred_s(pg[H1(i)]);
133
+ d[i] = n[i] & (expand_pred_s(pg[H1(i)]) ^ inv);
134
}
135
}
136
137
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_movz_d)(void *vd, void *vn, void *vg, uint32_t desc)
138
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
139
uint64_t *d = vd, *n = vn;
140
uint8_t *pg = vg;
141
+ uint8_t inv = simd_data(desc);
142
+
143
for (i = 0; i < opr_sz; i += 1) {
144
- d[i] = n[i] & -(uint64_t)(pg[H1(i)] & 1);
145
+ d[i] = n[i] & -(uint64_t)((pg[H1(i)] ^ inv) & 1);
146
}
147
}
148
149
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-sve.c
152
+++ b/target/arm/translate-sve.c
153
@@ -XXX,XX +XXX,XX @@ static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a)
154
*** SVE Shift by Immediate - Predicated Group
155
*/
156
157
-/* Store zero into every active element of Zd. We will use this for two
158
- * and three-operand predicated instructions for which logic dictates a
159
- * zero result.
160
+/*
161
+ * Copy Zn into Zd, storing zeros into inactive elements.
162
+ * If invert, store zeros into the active elements.
163
*/
164
-static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz)
165
-{
166
- static gen_helper_gvec_2 * const fns[4] = {
167
- gen_helper_sve_clr_b, gen_helper_sve_clr_h,
168
- gen_helper_sve_clr_s, gen_helper_sve_clr_d,
169
- };
170
- if (sve_access_check(s)) {
171
- unsigned vsz = vec_full_reg_size(s);
172
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
173
- pred_full_reg_offset(s, pg),
174
- vsz, vsz, 0, fns[esz]);
175
- }
176
- return true;
177
-}
178
-
179
-/* Copy Zn into Zd, storing zeros into inactive elements. */
180
-static void do_movz_zpz(DisasContext *s, int rd, int rn, int pg, int esz)
181
+static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
182
+ int esz, bool invert)
183
{
184
static gen_helper_gvec_3 * const fns[4] = {
185
gen_helper_sve_movz_b, gen_helper_sve_movz_h,
186
gen_helper_sve_movz_s, gen_helper_sve_movz_d,
187
};
188
- unsigned vsz = vec_full_reg_size(s);
189
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
190
- vec_full_reg_offset(s, rn),
191
- pred_full_reg_offset(s, pg),
192
- vsz, vsz, 0, fns[esz]);
193
+
194
+ if (sve_access_check(s)) {
195
+ unsigned vsz = vec_full_reg_size(s);
196
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
197
+ vec_full_reg_offset(s, rn),
198
+ pred_full_reg_offset(s, pg),
199
+ vsz, vsz, invert, fns[esz]);
200
+ }
201
+ return true;
202
}
203
204
static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
205
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
206
/* Shift by element size is architecturally valid.
207
For logical shifts, it is a zeroing operation. */
208
if (a->imm >= (8 << a->esz)) {
209
- return do_clr_zp(s, a->rd, a->pg, a->esz);
210
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
211
} else {
212
return do_zpzi_ool(s, a, fns[a->esz]);
213
}
214
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
215
/* Shift by element size is architecturally valid.
216
For logical shifts, it is a zeroing operation. */
217
if (a->imm >= (8 << a->esz)) {
218
- return do_clr_zp(s, a->rd, a->pg, a->esz);
219
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
220
} else {
221
return do_zpzi_ool(s, a, fns[a->esz]);
222
}
223
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
224
/* Shift by element size is architecturally valid. For arithmetic
225
right shift for division, it is a zeroing operation. */
226
if (a->imm >= (8 << a->esz)) {
227
- return do_clr_zp(s, a->rd, a->pg, a->esz);
228
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
229
} else {
230
return do_zpzi_ool(s, a, fns[a->esz]);
231
}
232
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
233
234
/* Zero the inactive elements. */
235
gen_set_label(over);
236
- do_movz_zpz(s, a->rd, a->rd, a->pg, esz);
237
- return true;
238
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, esz, false);
239
}
240
241
static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
242
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
243
244
static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
245
{
246
- if (sve_access_check(s)) {
247
- do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz);
248
- }
249
- return true;
250
+ return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false);
251
}
252
--
261
--
253
2.20.1
262
2.25.1
254
255
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
To have a better idea of how big is the region where the offset
3
The CNT register is a read-only register. There is no need to
4
belongs, display the value with the width of the region size
4
store it's value, it can be calculated on demand.
5
(i.e. a region of 0x1000 bytes uses 0x000 format).
5
The calculated frequency is needed temporarily only.
6
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Note that this is a migration compatibility break for all boards
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
types that use the EPIT peripheral.
9
Message-id: 20200812190206.31595-4-f4bug@amsat.org
9
10
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
include/hw/misc/unimp.h | 1 +
14
include/hw/timer/imx_epit.h | 2 -
13
hw/misc/unimp.c | 10 ++++++----
15
hw/timer/imx_epit.c | 73 ++++++++++++++-----------------------
14
2 files changed, 7 insertions(+), 4 deletions(-)
16
2 files changed, 28 insertions(+), 47 deletions(-)
15
17
16
diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
18
diff --git a/include/hw/timer/imx_epit.h b/include/hw/timer/imx_epit.h
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/misc/unimp.h
20
--- a/include/hw/timer/imx_epit.h
19
+++ b/include/hw/misc/unimp.h
21
+++ b/include/hw/timer/imx_epit.h
20
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ struct IMXEPITState {
21
typedef struct {
23
uint32_t sr;
22
SysBusDevice parent_obj;
24
uint32_t lr;
23
MemoryRegion iomem;
25
uint32_t cmp;
24
+ unsigned offset_fmt_width;
26
- uint32_t cnt;
25
char *name;
27
26
uint64_t size;
28
- uint32_t freq;
27
} UnimplementedDeviceState;
29
qemu_irq irq;
28
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
30
};
31
32
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
29
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/misc/unimp.c
34
--- a/hw/timer/imx_epit.c
31
+++ b/hw/misc/unimp.c
35
+++ b/hw/timer/imx_epit.c
32
@@ -XXX,XX +XXX,XX @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
36
@@ -XXX,XX +XXX,XX @@ static void imx_epit_update_int(IMXEPITState *s)
33
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
37
}
34
35
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
36
- "(size %d, offset 0x%" HWADDR_PRIx ")\n",
37
- s->name, size, offset);
38
+ "(size %d, offset 0x%0*" HWADDR_PRIx ")\n",
39
+ s->name, size, s->offset_fmt_width, offset);
40
return 0;
41
}
38
}
42
39
43
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
40
-/*
44
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
41
- * Must be called from within a ptimer_transaction_begin/commit block
45
42
- * for both s->timer_cmp and s->timer_reload.
46
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
43
- */
47
- "(size %d, offset 0x%" HWADDR_PRIx
44
-static void imx_epit_set_freq(IMXEPITState *s)
48
+ "(size %d, offset 0x%0*" HWADDR_PRIx
45
+static uint32_t imx_epit_get_freq(IMXEPITState *s)
49
", value 0x%0*" PRIx64 ")\n",
46
{
50
- s->name, size, offset, size << 1, value);
47
- uint32_t clksrc;
51
+ s->name, size, s->offset_fmt_width, offset, size << 1, value);
48
- uint32_t prescaler;
49
-
50
- clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
51
- prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
52
-
53
- s->freq = imx_ccm_get_clock_frequency(s->ccm,
54
- imx_epit_clocks[clksrc]) / prescaler;
55
-
56
- DPRINTF("Setting ptimer frequency to %u\n", s->freq);
57
-
58
- if (s->freq) {
59
- ptimer_set_freq(s->timer_reload, s->freq);
60
- ptimer_set_freq(s->timer_cmp, s->freq);
61
- }
62
+ uint32_t clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, CR_CLKSRC_BITS);
63
+ uint32_t prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, CR_PRESCALE_BITS);
64
+ uint32_t f_in = imx_ccm_get_clock_frequency(s->ccm, imx_epit_clocks[clksrc]);
65
+ uint32_t freq = f_in / prescaler;
66
+ DPRINTF("ptimer frequency is %u\n", freq);
67
+ return freq;
52
}
68
}
53
69
54
static const MemoryRegionOps unimp_ops = {
70
/*
55
@@ -XXX,XX +XXX,XX @@ static void unimp_realize(DeviceState *dev, Error **errp)
71
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reset(IMXEPITState *s, bool is_hard_reset)
56
return;
72
s->sr = 0;
73
s->lr = EPIT_TIMER_MAX;
74
s->cmp = 0;
75
- s->cnt = 0;
76
ptimer_transaction_begin(s->timer_cmp);
77
ptimer_transaction_begin(s->timer_reload);
78
- /* stop both timers */
79
+
80
+ /*
81
+ * The reset switches off the input clock, so even if the CR.EN is still
82
+ * set, the timers are no longer running.
83
+ */
84
+ assert(imx_epit_get_freq(s) == 0);
85
ptimer_stop(s->timer_cmp);
86
ptimer_stop(s->timer_reload);
87
- /* compute new frequency */
88
- imx_epit_set_freq(s);
89
/* init both timers to EPIT_TIMER_MAX */
90
ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
91
ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
92
- if (s->freq && (s->cr & CR_EN)) {
93
- /* if the timer is still enabled, restart it */
94
- ptimer_run(s->timer_reload, 0);
95
- }
96
ptimer_transaction_commit(s->timer_cmp);
97
ptimer_transaction_commit(s->timer_reload);
98
}
99
100
-static uint32_t imx_epit_update_count(IMXEPITState *s)
101
-{
102
- s->cnt = ptimer_get_count(s->timer_reload);
103
-
104
- return s->cnt;
105
-}
106
-
107
static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
108
{
109
IMXEPITState *s = IMX_EPIT(opaque);
110
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
111
break;
112
113
case 4: /* CNT */
114
- imx_epit_update_count(s);
115
- reg_value = s->cnt;
116
+ reg_value = ptimer_get_count(s->timer_reload);
117
break;
118
119
default:
120
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
121
{
122
if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
123
/* if the compare feature is on and timers are running */
124
- uint32_t tmp = imx_epit_update_count(s);
125
+ uint32_t tmp = ptimer_get_count(s->timer_reload);
126
uint64_t next;
127
if (tmp > s->cmp) {
128
/* It'll fire in this round of the timer */
129
@@ -XXX,XX +XXX,XX @@ static void imx_epit_reload_compare_timer(IMXEPITState *s)
130
131
static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
132
{
133
+ uint32_t freq = 0;
134
uint32_t oldcr = s->cr;
135
136
s->cr = value & 0x03ffffff;
137
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
138
ptimer_transaction_begin(s->timer_cmp);
139
ptimer_transaction_begin(s->timer_reload);
140
141
- /* Update the frequency. Has been done already in case of a reset. */
142
+ /*
143
+ * Update the frequency. In case of a reset the input clock was
144
+ * switched off, so this can be skipped.
145
+ */
146
if (!(s->cr & CR_SWR)) {
147
- imx_epit_set_freq(s);
148
+ freq = imx_epit_get_freq(s);
149
+ if (freq) {
150
+ ptimer_set_freq(s->timer_reload, freq);
151
+ ptimer_set_freq(s->timer_cmp, freq);
152
+ }
57
}
153
}
58
154
59
+ s->offset_fmt_width = DIV_ROUND_UP(64 - clz64(s->size - 1), 4);
155
- if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
60
+
156
+ if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
61
memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
157
if (s->cr & CR_ENMOD) {
62
s->name, s->size);
158
if (s->cr & CR_RLD) {
63
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
159
ptimer_set_limit(s->timer_reload, s->lr, 1);
160
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps imx_epit_ops = {
161
162
static const VMStateDescription vmstate_imx_timer_epit = {
163
.name = TYPE_IMX_EPIT,
164
- .version_id = 2,
165
- .minimum_version_id = 2,
166
+ .version_id = 3,
167
+ .minimum_version_id = 3,
168
.fields = (VMStateField[]) {
169
VMSTATE_UINT32(cr, IMXEPITState),
170
VMSTATE_UINT32(sr, IMXEPITState),
171
VMSTATE_UINT32(lr, IMXEPITState),
172
VMSTATE_UINT32(cmp, IMXEPITState),
173
- VMSTATE_UINT32(cnt, IMXEPITState),
174
- VMSTATE_UINT32(freq, IMXEPITState),
175
VMSTATE_PTIMER(timer_reload, IMXEPITState),
176
VMSTATE_PTIMER(timer_cmp, IMXEPITState),
177
VMSTATE_END_OF_LIST()
64
--
178
--
65
2.20.1
179
2.25.1
66
67
diff view generated by jsdifflib
1
From: Eduardo Habkost <ehabkost@redhat.com>
1
From: Axel Heider <axel.heider@hensoldt.net>
2
2
3
TYPE_ARM_SSE is a TYPE_SYS_BUS_DEVICE subclass, but
3
- fix #1263 for CR writes
4
ARMSSEClass::parent_class is declared as DeviceClass.
4
- rework compare time handling
5
- The compare timer has to run even if CR.OCIEN is not set,
6
as SR.OCIF must be updated.
7
- The compare timer fires exactly once when the
8
compare value is less than the current value, but the
9
reload values is less than the compare value.
10
- The compare timer will never fire if the reload value is
11
less than the compare value. Disable it in this case.
5
12
6
It never caused any problems by pure luck:
13
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
7
14
[PMM: fixed minor style nits]
8
We were not setting class_size for TYPE_ARM_SSE, so class_size of
9
TYPE_SYS_BUS_DEVICE was being used (sizeof(SysBusDeviceClass)).
10
This made the system allocate enough memory for TYPE_ARM_SSE
11
devices even though ARMSSEClass was too small for a sysbus
12
device.
13
14
Additionally, the ARMSSEClass::info field ended up at the same
15
offset as SysBusDeviceClass::explicit_ofw_unit_address. This
16
would make sysbus_get_fw_dev_path() crash for the device.
17
Luckily, sysbus_get_fw_dev_path() never gets called for
18
TYPE_ARM_SSE devices, because qdev_get_fw_dev_path() is only used
19
by the boot device code, and TYPE_ARM_SSE devices don't appear at
20
the fw_boot_order list.
21
22
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
23
Message-id: 20200826181006.4097163-1-ehabkost@redhat.com
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
17
---
27
include/hw/arm/armsse.h | 2 +-
18
hw/timer/imx_epit.c | 192 ++++++++++++++++++++++++++------------------
28
hw/arm/armsse.c | 1 +
19
1 file changed, 116 insertions(+), 76 deletions(-)
29
2 files changed, 2 insertions(+), 1 deletion(-)
30
20
31
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
21
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
32
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/armsse.h
23
--- a/hw/timer/imx_epit.c
34
+++ b/include/hw/arm/armsse.h
24
+++ b/hw/timer/imx_epit.c
35
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
25
@@ -XXX,XX +XXX,XX @@
36
typedef struct ARMSSEInfo ARMSSEInfo;
26
* Originally written by Hans Jiang
37
27
* Updated by Peter Chubb
38
typedef struct ARMSSEClass {
28
* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
39
- DeviceClass parent_class;
29
+ * Updated by Axel Heider
40
+ SysBusDeviceClass parent_class;
30
*
41
const ARMSSEInfo *info;
31
* This code is licensed under GPL version 2 or later. See
42
} ARMSSEClass;
32
* the COPYING file in the top-level directory.
43
33
@@ -XXX,XX +XXX,XX @@ static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
44
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
34
return reg_value;
45
index XXXXXXX..XXXXXXX 100644
35
}
46
--- a/hw/arm/armsse.c
36
47
+++ b/hw/arm/armsse.c
37
-/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */
48
@@ -XXX,XX +XXX,XX @@ static const TypeInfo armsse_info = {
38
-static void imx_epit_reload_compare_timer(IMXEPITState *s)
49
.name = TYPE_ARMSSE,
39
+/*
50
.parent = TYPE_SYS_BUS_DEVICE,
40
+ * Must be called from a ptimer_transaction_begin/commit block for
51
.instance_size = sizeof(ARMSSE),
41
+ * s->timer_cmp, but outside of a transaction block of s->timer_reload,
52
+ .class_size = sizeof(ARMSSEClass),
42
+ * so the proper counter value is read.
53
.instance_init = armsse_init,
43
+ */
54
.abstract = true,
44
+static void imx_epit_update_compare_timer(IMXEPITState *s)
55
.interfaces = (InterfaceInfo[]) {
45
{
46
- if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
47
- /* if the compare feature is on and timers are running */
48
- uint32_t tmp = ptimer_get_count(s->timer_reload);
49
- uint64_t next;
50
- if (tmp > s->cmp) {
51
- /* It'll fire in this round of the timer */
52
- next = tmp - s->cmp;
53
- } else { /* catch it next time around */
54
- next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
55
+ uint64_t counter = 0;
56
+ bool is_oneshot = false;
57
+ /*
58
+ * The compare timer only has to run if the timer peripheral is active
59
+ * and there is an input clock, Otherwise it can be switched off.
60
+ */
61
+ bool is_active = (s->cr & CR_EN) && imx_epit_get_freq(s);
62
+ if (is_active) {
63
+ /*
64
+ * Calculate next timeout for compare timer. Reading the reload
65
+ * counter returns proper results only if pending transactions
66
+ * on it are committed here. Otherwise stale values are be read.
67
+ */
68
+ counter = ptimer_get_count(s->timer_reload);
69
+ uint64_t limit = ptimer_get_limit(s->timer_cmp);
70
+ /*
71
+ * The compare timer is a periodic timer if the limit is at least
72
+ * the compare value. Otherwise it may fire at most once in the
73
+ * current round.
74
+ */
75
+ bool is_oneshot = (limit >= s->cmp);
76
+ if (counter >= s->cmp) {
77
+ /* The compare timer fires in the current round. */
78
+ counter -= s->cmp;
79
+ } else if (!is_oneshot) {
80
+ /*
81
+ * The compare timer fires after a reload, as it is below the
82
+ * compare value already in this round. Note that the counter
83
+ * value calculated below can be above the 32-bit limit, which
84
+ * is legal here because the compare timer is an internal
85
+ * helper ptimer only.
86
+ */
87
+ counter += limit - s->cmp;
88
+ } else {
89
+ /*
90
+ * The compare timer won't fire in this round, and the limit is
91
+ * set to a value below the compare value. This practically means
92
+ * it will never fire, so it can be switched off.
93
+ */
94
+ is_active = false;
95
}
96
- ptimer_set_count(s->timer_cmp, next);
97
}
98
+
99
+ /*
100
+ * Set the compare timer and let it run, or stop it. This is agnostic
101
+ * of CR.OCIEN bit, as this bit affects interrupt generation only. The
102
+ * compare timer needs to run even if no interrupts are to be generated,
103
+ * because the SR.OCIF bit must be updated also.
104
+ * Note that the timer might already be stopped or be running with
105
+ * counter values. However, finding out when an update is needed and
106
+ * when not is not trivial. It's much easier applying the setting again,
107
+ * as this does not harm either and the overhead is negligible.
108
+ */
109
+ if (is_active) {
110
+ ptimer_set_count(s->timer_cmp, counter);
111
+ ptimer_run(s->timer_cmp, is_oneshot ? 1 : 0);
112
+ } else {
113
+ ptimer_stop(s->timer_cmp);
114
+ }
115
+
116
}
117
118
static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
119
{
120
- uint32_t freq = 0;
121
uint32_t oldcr = s->cr;
122
123
s->cr = value & 0x03ffffff;
124
125
if (s->cr & CR_SWR) {
126
- /* handle the reset */
127
+ /*
128
+ * Reset clears CR.SWR again. It does not touch CR.EN, but the timers
129
+ * are still stopped because the input clock is disabled.
130
+ */
131
imx_epit_reset(s, false);
132
+ } else {
133
+ uint32_t freq;
134
+ uint32_t toggled_cr_bits = oldcr ^ s->cr;
135
+ /* re-initialize the limits if CR.RLD has changed */
136
+ bool set_limit = toggled_cr_bits & CR_RLD;
137
+ /* set the counter if the timer got just enabled and CR.ENMOD is set */
138
+ bool is_switched_on = (toggled_cr_bits & s->cr) & CR_EN;
139
+ bool set_counter = is_switched_on && (s->cr & CR_ENMOD);
140
+
141
+ ptimer_transaction_begin(s->timer_cmp);
142
+ ptimer_transaction_begin(s->timer_reload);
143
+ freq = imx_epit_get_freq(s);
144
+ if (freq) {
145
+ ptimer_set_freq(s->timer_reload, freq);
146
+ ptimer_set_freq(s->timer_cmp, freq);
147
+ }
148
+
149
+ if (set_limit || set_counter) {
150
+ uint64_t limit = (s->cr & CR_RLD) ? s->lr : EPIT_TIMER_MAX;
151
+ ptimer_set_limit(s->timer_reload, limit, set_counter ? 1 : 0);
152
+ if (set_limit) {
153
+ ptimer_set_limit(s->timer_cmp, limit, 0);
154
+ }
155
+ }
156
+ /*
157
+ * If there is an input clock and the peripheral is enabled, then
158
+ * ensure the wall clock timer is ticking. Otherwise stop the timers.
159
+ * The compare timer will be updated later.
160
+ */
161
+ if (freq && (s->cr & CR_EN)) {
162
+ ptimer_run(s->timer_reload, 0);
163
+ } else {
164
+ ptimer_stop(s->timer_reload);
165
+ }
166
+ /* Commit changes to reload timer, so they can propagate. */
167
+ ptimer_transaction_commit(s->timer_reload);
168
+ /* Update compare timer based on the committed reload timer value. */
169
+ imx_epit_update_compare_timer(s);
170
+ ptimer_transaction_commit(s->timer_cmp);
171
}
172
173
/*
174
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cr(IMXEPITState *s, uint32_t value)
175
* - write to CR.EN or CR.OCIE
176
*/
177
imx_epit_update_int(s);
178
-
179
- /*
180
- * TODO: could we 'break' here for reset? following operations appear
181
- * to duplicate the work imx_epit_reset() already did.
182
- */
183
-
184
- ptimer_transaction_begin(s->timer_cmp);
185
- ptimer_transaction_begin(s->timer_reload);
186
-
187
- /*
188
- * Update the frequency. In case of a reset the input clock was
189
- * switched off, so this can be skipped.
190
- */
191
- if (!(s->cr & CR_SWR)) {
192
- freq = imx_epit_get_freq(s);
193
- if (freq) {
194
- ptimer_set_freq(s->timer_reload, freq);
195
- ptimer_set_freq(s->timer_cmp, freq);
196
- }
197
- }
198
-
199
- if (freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
200
- if (s->cr & CR_ENMOD) {
201
- if (s->cr & CR_RLD) {
202
- ptimer_set_limit(s->timer_reload, s->lr, 1);
203
- ptimer_set_limit(s->timer_cmp, s->lr, 1);
204
- } else {
205
- ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
206
- ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
207
- }
208
- }
209
-
210
- imx_epit_reload_compare_timer(s);
211
- ptimer_run(s->timer_reload, 0);
212
- if (s->cr & CR_OCIEN) {
213
- ptimer_run(s->timer_cmp, 0);
214
- } else {
215
- ptimer_stop(s->timer_cmp);
216
- }
217
- } else if (!(s->cr & CR_EN)) {
218
- /* stop both timers */
219
- ptimer_stop(s->timer_reload);
220
- ptimer_stop(s->timer_cmp);
221
- } else if (s->cr & CR_OCIEN) {
222
- if (!(oldcr & CR_OCIEN)) {
223
- imx_epit_reload_compare_timer(s);
224
- ptimer_run(s->timer_cmp, 0);
225
- }
226
- } else {
227
- ptimer_stop(s->timer_cmp);
228
- }
229
-
230
- ptimer_transaction_commit(s->timer_cmp);
231
- ptimer_transaction_commit(s->timer_reload);
232
}
233
234
static void imx_epit_write_sr(IMXEPITState *s, uint32_t value)
235
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_lr(IMXEPITState *s, uint32_t value)
236
/* If IOVW bit is set then set the timer value */
237
ptimer_set_count(s->timer_reload, s->lr);
238
}
239
- /*
240
- * Commit the change to s->timer_reload, so it can propagate. Otherwise
241
- * the timer interrupt may not fire properly. The commit must happen
242
- * before calling imx_epit_reload_compare_timer(), which reads
243
- * s->timer_reload internally again.
244
- */
245
+ /* Commit the changes to s->timer_reload, so they can propagate. */
246
ptimer_transaction_commit(s->timer_reload);
247
- imx_epit_reload_compare_timer(s);
248
+ /* Update the compare timer based on the committed reload timer value. */
249
+ imx_epit_update_compare_timer(s);
250
ptimer_transaction_commit(s->timer_cmp);
251
}
252
253
@@ -XXX,XX +XXX,XX @@ static void imx_epit_write_cmp(IMXEPITState *s, uint32_t value)
254
{
255
s->cmp = value;
256
257
+ /* Update the compare timer based on the committed reload timer value. */
258
ptimer_transaction_begin(s->timer_cmp);
259
- imx_epit_reload_compare_timer(s);
260
+ imx_epit_update_compare_timer(s);
261
ptimer_transaction_commit(s->timer_cmp);
262
}
263
264
@@ -XXX,XX +XXX,XX @@ static void imx_epit_cmp(void *opaque)
265
{
266
IMXEPITState *s = IMX_EPIT(opaque);
267
268
+ /* The cmp ptimer can't be running when the peripheral is disabled */
269
+ assert(s->cr & CR_EN);
270
+
271
DPRINTF("sr was %d\n", s->sr);
272
/* Set interrupt status bit SR.OCIF and update the interrupt state */
273
s->sr |= SR_OCIF;
56
--
274
--
57
2.20.1
275
2.25.1
58
59
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Allow the device to execute the DMA transfers in a different
3
Fix these:
4
AddressSpace.
5
4
6
We keep using the system_memory address space, but via the
5
WARNING: Block comments use a leading /* on a separate line
7
proper dma_memory_access() API.
6
WARNING: Block comments use * on subsequent lines
7
WARNING: Block comments use a trailing */ on a separate line
8
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Claudio Fontana <cfontana@suse.de>
11
Message-id: 20200814125533.4047-1-f4bug@amsat.org
11
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
12
Message-id: 20221213190537.511-2-farosas@suse.de
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
---
14
hw/arm/musicpal.c | 45 +++++++++++++++++++++++++++++++--------------
15
target/arm/helper.c | 323 +++++++++++++++++++++++++++++---------------
15
1 file changed, 31 insertions(+), 14 deletions(-)
16
1 file changed, 215 insertions(+), 108 deletions(-)
16
17
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/musicpal.c
20
--- a/target/arm/helper.c
20
+++ b/hw/arm/musicpal.c
21
+++ b/target/arm/helper.c
21
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
22
#include "hw/audio/wm8750.h"
23
static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
23
#include "sysemu/block-backend.h"
24
uint64_t v)
24
#include "sysemu/runstate.h"
25
{
25
+#include "sysemu/dma.h"
26
- /* Raw write of a coprocessor register (as needed for migration, etc).
26
#include "exec/address-spaces.h"
27
+ /*
27
#include "ui/pixel_ops.h"
28
+ * Raw write of a coprocessor register (as needed for migration, etc).
28
#include "qemu/cutils.h"
29
* Note that constant registers are treated as write-ignored; the
29
@@ -XXX,XX +XXX,XX @@ typedef struct mv88w8618_eth_state {
30
* caller should check for success by whether a readback gives the
30
31
* value written.
31
MemoryRegion iomem;
32
@@ -XXX,XX +XXX,XX @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
32
qemu_irq irq;
33
33
+ MemoryRegion *dma_mr;
34
static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
34
+ AddressSpace dma_as;
35
{
35
uint32_t smir;
36
- /* Return true if the regdef would cause an assertion if you called
36
uint32_t icr;
37
+ /*
37
uint32_t imr;
38
+ * Return true if the regdef would cause an assertion if you called
38
@@ -XXX,XX +XXX,XX @@ typedef struct mv88w8618_eth_state {
39
* read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
39
NICConf conf;
40
* program bug for it not to have the NO_RAW flag).
40
} mv88w8618_eth_state;
41
* NB that returning false here doesn't necessarily mean that calling
41
42
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu)
42
-static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
43
if (ri->type & ARM_CP_NO_RAW) {
43
+static void eth_rx_desc_put(AddressSpace *dma_as, uint32_t addr,
44
+ mv88w8618_rx_desc *desc)
45
{
46
cpu_to_le32s(&desc->cmdstat);
47
cpu_to_le16s(&desc->bytes);
48
cpu_to_le16s(&desc->buffer_size);
49
cpu_to_le32s(&desc->buffer);
50
cpu_to_le32s(&desc->next);
51
- cpu_physical_memory_write(addr, desc, sizeof(*desc));
52
+ dma_memory_write(dma_as, addr, desc, sizeof(*desc));
53
}
54
55
-static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
56
+static void eth_rx_desc_get(AddressSpace *dma_as, uint32_t addr,
57
+ mv88w8618_rx_desc *desc)
58
{
59
- cpu_physical_memory_read(addr, desc, sizeof(*desc));
60
+ dma_memory_read(dma_as, addr, desc, sizeof(*desc));
61
le32_to_cpus(&desc->cmdstat);
62
le16_to_cpus(&desc->bytes);
63
le16_to_cpus(&desc->buffer_size);
64
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
65
continue;
44
continue;
66
}
45
}
67
do {
46
- /* Write value and confirm it reads back as written
68
- eth_rx_desc_get(desc_addr, &desc);
47
+ /*
69
+ eth_rx_desc_get(&s->dma_as, desc_addr, &desc);
48
+ * Write value and confirm it reads back as written
70
if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
49
* (to catch read-only registers and partially read-only
71
- cpu_physical_memory_write(desc.buffer + s->vlan_header,
50
* registers where the incoming migration value doesn't match)
72
+ dma_memory_write(&s->dma_as, desc.buffer + s->vlan_header,
51
*/
73
buf, size);
52
@@ -XXX,XX +XXX,XX @@ static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
74
desc.bytes = size + s->vlan_header;
53
75
desc.cmdstat &= ~MP_ETH_RX_OWN;
54
void init_cpreg_list(ARMCPU *cpu)
76
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
55
{
77
if (s->icr & s->imr) {
56
- /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
78
qemu_irq_raise(s->irq);
57
+ /*
79
}
58
+ * Initialise the cpreg_tuples[] array based on the cp_regs hash.
80
- eth_rx_desc_put(desc_addr, &desc);
59
* Note that we require cpreg_tuples[] to be sorted by key ID.
81
+ eth_rx_desc_put(&s->dma_as, desc_addr, &desc);
60
*/
82
return size;
61
GList *keys;
62
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_el3_aa32ns(CPUARMState *env,
63
return CP_ACCESS_OK;
64
}
65
66
-/* Some secure-only AArch32 registers trap to EL3 if used from
67
+/*
68
+ * Some secure-only AArch32 registers trap to EL3 if used from
69
* Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
70
* Note that an access from Secure EL1 can only happen if EL3 is AArch64.
71
* We assume that the .access field is set to PL1_RW.
72
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
73
return CP_ACCESS_TRAP_UNCATEGORIZED;
74
}
75
76
-/* Check for traps to performance monitor registers, which are controlled
77
+/*
78
+ * Check for traps to performance monitor registers, which are controlled
79
* by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
80
*/
81
static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
82
@@ -XXX,XX +XXX,XX @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
83
ARMCPU *cpu = env_archcpu(env);
84
85
if (raw_read(env, ri) != value) {
86
- /* Unlike real hardware the qemu TLB uses virtual addresses,
87
+ /*
88
+ * Unlike real hardware the qemu TLB uses virtual addresses,
89
* not modified virtual addresses, so this causes a TLB flush.
90
*/
91
tlb_flush(CPU(cpu));
92
@@ -XXX,XX +XXX,XX @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
93
94
if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
95
&& !extended_addresses_enabled(env)) {
96
- /* For VMSA (when not using the LPAE long descriptor page table
97
+ /*
98
+ * For VMSA (when not using the LPAE long descriptor page table
99
* format) this register includes the ASID, so do a TLB flush.
100
* For PMSA it is purely a process ID and no action is needed.
101
*/
102
@@ -XXX,XX +XXX,XX @@ static void tlbiipas2is_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
103
}
104
105
static const ARMCPRegInfo cp_reginfo[] = {
106
- /* Define the secure and non-secure FCSE identifier CP registers
107
+ /*
108
+ * Define the secure and non-secure FCSE identifier CP registers
109
* separately because there is no secure bank in V8 (no _EL3). This allows
110
* the secure register to be properly reset and migrated. There is also no
111
* v8 EL1 version of the register so the non-secure instance stands alone.
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
113
.access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
114
.fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
115
.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
116
- /* Define the secure and non-secure context identifier CP registers
117
+ /*
118
+ * Define the secure and non-secure context identifier CP registers
119
* separately because there is no secure bank in V8 (no _EL3). This allows
120
* the secure register to be properly reset and migrated. In the
121
* non-secure case, the 32-bit register will have reset and migration
122
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cp_reginfo[] = {
123
};
124
125
static const ARMCPRegInfo not_v8_cp_reginfo[] = {
126
- /* NB: Some of these registers exist in v8 but with more precise
127
+ /*
128
+ * NB: Some of these registers exist in v8 but with more precise
129
* definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
130
*/
131
/* MMU Domain access control / MPU write buffer control */
132
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
133
.writefn = dacr_write, .raw_writefn = raw_write,
134
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
135
offsetoflow32(CPUARMState, cp15.dacr_ns) } },
136
- /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
137
+ /*
138
+ * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
139
* For v6 and v5, these mappings are overly broad.
140
*/
141
{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
142
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
143
};
144
145
static const ARMCPRegInfo not_v6_cp_reginfo[] = {
146
- /* Not all pre-v6 cores implemented this WFI, so this is slightly
147
+ /*
148
+ * Not all pre-v6 cores implemented this WFI, so this is slightly
149
* over-broad.
150
*/
151
{ .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
152
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
153
};
154
155
static const ARMCPRegInfo not_v7_cp_reginfo[] = {
156
- /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
157
+ /*
158
+ * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
159
* is UNPREDICTABLE; we choose to NOP as most implementations do).
160
*/
161
{ .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
162
.access = PL1_W, .type = ARM_CP_WFI },
163
- /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
164
+ /*
165
+ * L1 cache lockdown. Not architectural in v6 and earlier but in practice
166
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
167
* OMAPCP will override this space.
168
*/
169
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
170
{ .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
171
.access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
172
.resetvalue = 0 },
173
- /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
174
+ /*
175
+ * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
176
* implementing it as RAZ means the "debug architecture version" bits
177
* will read as a reserved value, which should cause Linux to not try
178
* to use the debug hardware.
179
*/
180
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
181
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
182
- /* MMU TLB control. Note that the wildcarding means we cover not just
183
+ /*
184
+ * MMU TLB control. Note that the wildcarding means we cover not just
185
* the unified TLB ops but also the dside/iside/inner-shareable variants.
186
*/
187
{ .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
188
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
189
190
/* In ARMv8 most bits of CPACR_EL1 are RES0. */
191
if (!arm_feature(env, ARM_FEATURE_V8)) {
192
- /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
193
+ /*
194
+ * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
195
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
196
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
197
*/
198
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
199
value |= R_CPACR_ASEDIS_MASK;
83
}
200
}
84
desc_addr = desc.next;
201
85
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
202
- /* VFPv3 and upwards with NEON implement 32 double precision
86
return size;
203
+ /*
87
}
204
+ * VFPv3 and upwards with NEON implement 32 double precision
88
205
* registers (D0-D31).
89
-static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
206
*/
90
+static void eth_tx_desc_put(AddressSpace *dma_as, uint32_t addr,
207
if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) {
91
+ mv88w8618_tx_desc *desc)
208
@@ -XXX,XX +XXX,XX @@ static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri)
92
{
209
93
cpu_to_le32s(&desc->cmdstat);
210
static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
94
cpu_to_le16s(&desc->res);
211
{
95
cpu_to_le16s(&desc->bytes);
212
- /* Call cpacr_write() so that we reset with the correct RAO bits set
96
cpu_to_le32s(&desc->buffer);
213
+ /*
97
cpu_to_le32s(&desc->next);
214
+ * Call cpacr_write() so that we reset with the correct RAO bits set
98
- cpu_physical_memory_write(addr, desc, sizeof(*desc));
215
* for our CPU features.
99
+ dma_memory_write(dma_as, addr, desc, sizeof(*desc));
216
*/
100
}
217
cpacr_write(env, ri, 0);
101
218
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
102
-static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
219
{ .name = "MVA_prefetch",
103
+static void eth_tx_desc_get(AddressSpace *dma_as, uint32_t addr,
220
.cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
104
+ mv88w8618_tx_desc *desc)
221
.access = PL1_W, .type = ARM_CP_NOP },
105
{
222
- /* We need to break the TB after ISB to execute self-modifying code
106
- cpu_physical_memory_read(addr, desc, sizeof(*desc));
223
+ /*
107
+ dma_memory_read(dma_as, addr, desc, sizeof(*desc));
224
+ * We need to break the TB after ISB to execute self-modifying code
108
le32_to_cpus(&desc->cmdstat);
225
* correctly and also to take any pending interrupts immediately.
109
le16_to_cpus(&desc->res);
226
* So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
110
le16_to_cpus(&desc->bytes);
227
*/
111
@@ -XXX,XX +XXX,XX @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
228
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
112
int len;
229
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
113
230
offsetof(CPUARMState, cp15.ifar_ns) },
114
do {
231
.resetvalue = 0, },
115
- eth_tx_desc_get(desc_addr, &desc);
232
- /* Watchpoint Fault Address Register : should actually only be present
116
+ eth_tx_desc_get(&s->dma_as, desc_addr, &desc);
233
+ /*
117
next_desc = desc.next;
234
+ * Watchpoint Fault Address Register : should actually only be present
118
if (desc.cmdstat & MP_ETH_TX_OWN) {
235
* for 1136, 1176, 11MPCore.
119
len = desc.bytes;
236
*/
120
if (len < 2048) {
237
{ .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
121
- cpu_physical_memory_read(desc.buffer, buf, len);
238
@@ -XXX,XX +XXX,XX @@ static bool event_supported(uint16_t number)
122
+ dma_memory_read(&s->dma_as, desc.buffer, buf, len);
239
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
123
qemu_send_packet(qemu_get_queue(s->nic), buf, len);
240
bool isread)
241
{
242
- /* Performance monitor registers user accessibility is controlled
243
+ /*
244
+ * Performance monitor registers user accessibility is controlled
245
* by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
246
* trapping to EL2 or EL3 for other accesses.
247
*/
248
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
249
(MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
250
#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
251
252
-/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
253
+/*
254
+ * Returns true if the counter (pass 31 for PMCCNTR) should count events using
255
* the current EL, security state, and register configuration.
256
*/
257
static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
258
@@ -XXX,XX +XXX,XX @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
259
static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
260
uint64_t value)
261
{
262
- /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
263
+ /*
264
+ * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
265
* PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
266
* meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
267
* accessed.
268
@@ -XXX,XX +XXX,XX @@ static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
269
env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
270
pmevcntr_op_finish(env, counter);
271
}
272
- /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
273
+ /*
274
+ * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
275
* PMSELR value is equal to or greater than the number of implemented
276
* counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
277
*/
278
@@ -XXX,XX +XXX,XX @@ static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
279
}
280
return ret;
281
} else {
282
- /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
283
- * are CONSTRAINED UNPREDICTABLE. */
284
+ /*
285
+ * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
286
+ * are CONSTRAINED UNPREDICTABLE.
287
+ */
288
return 0;
289
}
290
}
291
@@ -XXX,XX +XXX,XX @@ static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
292
static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
293
uint64_t value)
294
{
295
- /* Note that even though the AArch64 view of this register has bits
296
+ /*
297
+ * Note that even though the AArch64 view of this register has bits
298
* [10:0] all RES0 we can only mask the bottom 5, to comply with the
299
* architectural requirements for bits which are RES0 only in some
300
* contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
301
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
302
if (!arm_feature(env, ARM_FEATURE_EL2)) {
303
valid_mask &= ~SCR_HCE;
304
305
- /* On ARMv7, SMD (or SCD as it is called in v7) is only
306
+ /*
307
+ * On ARMv7, SMD (or SCD as it is called in v7) is only
308
* supported if EL2 exists. The bit is UNK/SBZP when
309
* EL2 is unavailable. In QEMU ARMv7, we force it to always zero
310
* when EL2 is unavailable.
311
@@ -XXX,XX +XXX,XX @@ static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
312
{
313
ARMCPU *cpu = env_archcpu(env);
314
315
- /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
316
+ /*
317
+ * Acquire the CSSELR index from the bank corresponding to the CCSIDR
318
* bank
319
*/
320
uint32_t index = A32_BANKED_REG_GET(env, csselr,
321
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
322
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
323
{ .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
324
.access = PL1_W, .type = ARM_CP_NOP },
325
- /* Performance monitors are implementation defined in v7,
326
+ /*
327
+ * Performance monitors are implementation defined in v7,
328
* but with an ARM recommended set of registers, which we
329
* follow.
330
*
331
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
332
.writefn = csselr_write, .resetvalue = 0,
333
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
334
offsetof(CPUARMState, cp15.csselr_ns) } },
335
- /* Auxiliary ID register: this actually has an IMPDEF value but for now
336
+ /*
337
+ * Auxiliary ID register: this actually has an IMPDEF value but for now
338
* just RAZ for all cores:
339
*/
340
{ .name = "AIDR", .state = ARM_CP_STATE_BOTH,
341
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
342
.access = PL1_R, .type = ARM_CP_CONST,
343
.accessfn = access_aa64_tid1,
344
.resetvalue = 0 },
345
- /* Auxiliary fault status registers: these also are IMPDEF, and we
346
+ /*
347
+ * Auxiliary fault status registers: these also are IMPDEF, and we
348
* choose to RAZ/WI for all cores.
349
*/
350
{ .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
351
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
352
.opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
353
.access = PL1_RW, .accessfn = access_tvm_trvm,
354
.type = ARM_CP_CONST, .resetvalue = 0 },
355
- /* MAIR can just read-as-written because we don't implement caches
356
+ /*
357
+ * MAIR can just read-as-written because we don't implement caches
358
* and so don't need to care about memory attributes.
359
*/
360
{ .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
361
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
362
.opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
363
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
364
.resetvalue = 0 },
365
- /* For non-long-descriptor page tables these are PRRR and NMRR;
366
+ /*
367
+ * For non-long-descriptor page tables these are PRRR and NMRR;
368
* regardless they still act as reads-as-written for QEMU.
369
*/
370
- /* MAIR0/1 are defined separately from their 64-bit counterpart which
371
+ /*
372
+ * MAIR0/1 are defined separately from their 64-bit counterpart which
373
* allows them to assign the correct fieldoffset based on the endianness
374
* handled in the field definitions.
375
*/
376
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
377
static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
378
bool isread)
379
{
380
- /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
381
+ /*
382
+ * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
383
* Writable only at the highest implemented exception level.
384
*/
385
int el = arm_current_el(env);
386
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
387
const ARMCPRegInfo *ri,
388
bool isread)
389
{
390
- /* The AArch64 register view of the secure physical timer is
391
+ /*
392
+ * The AArch64 register view of the secure physical timer is
393
* always accessible from EL3, and configurably accessible from
394
* Secure EL1.
395
*/
396
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
397
ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
398
399
if (gt->ctl & 1) {
400
- /* Timer enabled: calculate and set current ISTATUS, irq, and
401
+ /*
402
+ * Timer enabled: calculate and set current ISTATUS, irq, and
403
* reset timer to when ISTATUS next has to change
404
*/
405
uint64_t offset = timeridx == GTIMER_VIRT ?
406
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
407
/* Next transition is when we hit cval */
408
nexttick = gt->cval + offset;
409
}
410
- /* Note that the desired next expiry time might be beyond the
411
+ /*
412
+ * Note that the desired next expiry time might be beyond the
413
* signed-64-bit range of a QEMUTimer -- in this case we just
414
* set the timer for as far in the future as possible. When the
415
* timer expires we will reset the timer for any remaining period.
416
@@ -XXX,XX +XXX,XX @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
417
/* Enable toggled */
418
gt_recalc_timer(cpu, timeridx);
419
} else if ((oldval ^ value) & 2) {
420
- /* IMASK toggled: don't need to recalculate,
421
+ /*
422
+ * IMASK toggled: don't need to recalculate,
423
* just set the interrupt line based on ISTATUS
424
*/
425
int irqstate = (oldval & 4) && !(value & 2);
426
@@ -XXX,XX +XXX,XX @@ static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
427
}
428
429
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
430
- /* Note that CNTFRQ is purely reads-as-written for the benefit
431
+ /*
432
+ * Note that CNTFRQ is purely reads-as-written for the benefit
433
* of software; writing it doesn't actually change the timer frequency.
434
* Our reset value matches the fixed frequency we implement the timer at.
435
*/
436
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
437
.readfn = gt_virt_redir_cval_read, .raw_readfn = raw_read,
438
.writefn = gt_virt_redir_cval_write, .raw_writefn = raw_write,
439
},
440
- /* Secure timer -- this is actually restricted to only EL3
441
+ /*
442
+ * Secure timer -- this is actually restricted to only EL3
443
* and configurably Secure-EL1 via the accessfn.
444
*/
445
{ .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
446
@@ -XXX,XX +XXX,XX @@ static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
447
448
#else
449
450
-/* In user-mode most of the generic timer registers are inaccessible
451
+/*
452
+ * In user-mode most of the generic timer registers are inaccessible
453
* however modern kernels (4.12+) allow access to cntvct_el0
454
*/
455
456
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
457
{
458
ARMCPU *cpu = env_archcpu(env);
459
460
- /* Currently we have no support for QEMUTimer in linux-user so we
461
+ /*
462
+ * Currently we have no support for QEMUTimer in linux-user so we
463
* can't call gt_get_countervalue(env), instead we directly
464
* call the lower level functions.
465
*/
466
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
467
bool isread)
468
{
469
if (ri->opc2 & 4) {
470
- /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
471
+ /*
472
+ * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
473
* Secure EL1 (which can only happen if EL3 is AArch64).
474
* They are simply UNDEF if executed from NS EL1.
475
* They function normally from EL2 or EL3.
476
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
124
}
477
}
125
desc.cmdstat &= ~MP_ETH_TX_OWN;
126
s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
127
- eth_tx_desc_put(desc_addr, &desc);
128
+ eth_tx_desc_put(&s->dma_as, desc_addr, &desc);
129
}
478
}
130
desc_addr = next_desc;
479
} else {
131
} while (desc_addr != s->tx_queue[queue_index]);
480
- /* fsr is a DFSR/IFSR value for the short descriptor
132
@@ -XXX,XX +XXX,XX @@ static void mv88w8618_eth_realize(DeviceState *dev, Error **errp)
481
+ /*
133
{
482
+ * fsr is a DFSR/IFSR value for the short descriptor
134
mv88w8618_eth_state *s = MV88W8618_ETH(dev);
483
* translation table format (with WnR always clear).
135
484
* Convert it to a 32-bit PAR.
136
+ if (!s->dma_mr) {
485
*/
137
+ error_setg(errp, TYPE_MV88W8618_ETH " 'dma-memory' link not set");
486
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pmsav8r_cp_reginfo[] = {
138
+ return;
139
+ }
140
+
141
+ address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
142
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
143
object_get_typename(OBJECT(dev)), dev->id, s);
144
}
145
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mv88w8618_eth_vmsd = {
146
147
static Property mv88w8618_eth_properties[] = {
148
DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
149
+ DEFINE_PROP_LINK("dma-memory", mv88w8618_eth_state, dma_mr,
150
+ TYPE_MEMORY_REGION, MemoryRegion *),
151
DEFINE_PROP_END_OF_LIST(),
152
};
487
};
153
488
154
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
489
static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
155
qemu_check_nic_model(&nd_table[0], "mv88w8618");
490
- /* Reset for all these registers is handled in arm_cpu_reset(),
156
dev = qdev_new(TYPE_MV88W8618_ETH);
491
+ /*
157
qdev_set_nic_properties(dev, &nd_table[0]);
492
+ * Reset for all these registers is handled in arm_cpu_reset(),
158
+ object_property_set_link(OBJECT(dev), "dma-memory",
493
* because the PMSAv7 is also used by M-profile CPUs, which do
159
+ OBJECT(get_system_memory()), &error_fatal);
494
* not register cpregs but still need the state to be reset.
160
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
495
*/
161
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
496
@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
162
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
497
}
498
499
if (arm_feature(env, ARM_FEATURE_LPAE)) {
500
- /* With LPAE the TTBCR could result in a change of ASID
501
+ /*
502
+ * With LPAE the TTBCR could result in a change of ASID
503
* via the TTBCR.A1 bit, so do a TLB flush.
504
*/
505
tlb_flush(CPU(cpu));
506
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
507
offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
508
};
509
510
-/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
511
+/*
512
+ * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
513
* qemu tlbs nor adjusting cached masks.
514
*/
515
static const ARMCPRegInfo ttbcr2_reginfo = {
516
@@ -XXX,XX +XXX,XX @@ static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
517
static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
518
uint64_t value)
519
{
520
- /* On OMAP there are registers indicating the max/min index of dcache lines
521
+ /*
522
+ * On OMAP there are registers indicating the max/min index of dcache lines
523
* containing a dirty line; cache flush operations have to reset these.
524
*/
525
env->cp15.c15_i_max = 0x000;
526
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo omap_cp_reginfo[] = {
527
.crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
528
.type = ARM_CP_NO_RAW,
529
.readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
530
- /* TODO: Peripheral port remap register:
531
+ /*
532
+ * TODO: Peripheral port remap register:
533
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
534
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
535
* when MMU is off.
536
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
537
.cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
538
.fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
539
.resetvalue = 0, },
540
- /* XScale specific cache-lockdown: since we have no cache we NOP these
541
+ /*
542
+ * XScale specific cache-lockdown: since we have no cache we NOP these
543
* and hope the guest does not really rely on cache behaviour.
544
*/
545
{ .name = "XSCALE_LOCK_ICACHE_LINE",
546
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo xscale_cp_reginfo[] = {
547
};
548
549
static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
550
- /* RAZ/WI the whole crn=15 space, when we don't have a more specific
551
+ /*
552
+ * RAZ/WI the whole crn=15 space, when we don't have a more specific
553
* implementation of this implementation-defined space.
554
* Ideally this should eventually disappear in favour of actually
555
* implementing the correct behaviour for all cores.
556
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
557
};
558
559
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
560
- /* The cache test-and-clean instructions always return (1 << 30)
561
+ /*
562
+ * The cache test-and-clean instructions always return (1 << 30)
563
* to indicate that there are no dirty cache lines.
564
*/
565
{ .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
566
@@ -XXX,XX +XXX,XX @@ static uint64_t mpidr_read_val(CPUARMState *env)
567
568
if (arm_feature(env, ARM_FEATURE_V7MP)) {
569
mpidr |= (1U << 31);
570
- /* Cores which are uniprocessor (non-coherent)
571
+ /*
572
+ * Cores which are uniprocessor (non-coherent)
573
* but still implement the MP extensions set
574
* bit 30. (For instance, Cortex-R5).
575
*/
576
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
577
return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
578
}
579
580
-/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
581
+/*
582
+ * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
583
* Page D4-1736 (DDI0487A.b)
584
*/
585
586
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
587
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
588
uint64_t value)
589
{
590
- /* Invalidate by VA, EL2
591
+ /*
592
+ * Invalidate by VA, EL2
593
* Currently handles both VAE2 and VALE2, since we don't support
594
* flush-last-level-only.
595
*/
596
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
597
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
598
uint64_t value)
599
{
600
- /* Invalidate by VA, EL3
601
+ /*
602
+ * Invalidate by VA, EL3
603
* Currently handles both VAE3 and VALE3, since we don't support
604
* flush-last-level-only.
605
*/
606
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
607
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
608
uint64_t value)
609
{
610
- /* Invalidate by VA, EL1&0 (AArch64 version).
611
+ /*
612
+ * Invalidate by VA, EL1&0 (AArch64 version).
613
* Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
614
* since we don't support flush-for-specific-ASID-only or
615
* flush-last-level-only.
616
@@ -XXX,XX +XXX,XX @@ static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
617
bool isread)
618
{
619
if (!(env->pstate & PSTATE_SP)) {
620
- /* Access to SP_EL0 is undefined if it's being used as
621
+ /*
622
+ * Access to SP_EL0 is undefined if it's being used as
623
* the stack pointer.
624
*/
625
return CP_ACCESS_TRAP_UNCATEGORIZED;
626
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
627
}
628
629
if (raw_read(env, ri) == value) {
630
- /* Skip the TLB flush if nothing actually changed; Linux likes
631
+ /*
632
+ * Skip the TLB flush if nothing actually changed; Linux likes
633
* to do a lot of pointless SCTLR writes.
634
*/
635
return;
636
@@ -XXX,XX +XXX,XX @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
637
}
638
639
static const ARMCPRegInfo v8_cp_reginfo[] = {
640
- /* Minimal set of EL0-visible registers. This will need to be expanded
641
+ /*
642
+ * Minimal set of EL0-visible registers. This will need to be expanded
643
* significantly for system emulation of AArch64 CPUs.
644
*/
645
{ .name = "NZCV", .state = ARM_CP_STATE_AA64,
646
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
647
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
648
.access = PL1_RW,
649
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
650
- /* We rely on the access checks not allowing the guest to write to the
651
+ /*
652
+ * We rely on the access checks not allowing the guest to write to the
653
* state field when SPSel indicates that it's being used as the stack
654
* pointer.
655
*/
656
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
657
if (arm_feature(env, ARM_FEATURE_EL3)) {
658
valid_mask &= ~HCR_HCD;
659
} else if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
660
- /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
661
+ /*
662
+ * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
663
* However, if we're using the SMC PSCI conduit then QEMU is
664
* effectively acting like EL3 firmware and so the guest at
665
* EL2 should retain the ability to prevent EL1 from being
666
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
667
.access = PL2_W, .type = ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF,
668
.writefn = tlbi_aa64_vae2is_write },
669
#ifndef CONFIG_USER_ONLY
670
- /* Unlike the other EL2-related AT operations, these must
671
+ /*
672
+ * Unlike the other EL2-related AT operations, these must
673
* UNDEF from EL3 if EL2 is not implemented, which is why we
674
* define them here rather than with the rest of the AT ops.
675
*/
676
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
677
.access = PL2_W, .accessfn = at_s1e2_access,
678
.type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDEF,
679
.writefn = ats_write64 },
680
- /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
681
+ /*
682
+ * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
683
* if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
684
* with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
685
* to behave as if SCR.NS was 1.
686
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
687
.writefn = ats1h_write, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC },
688
{ .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
689
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
690
- /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
691
+ /*
692
+ * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
693
* reset values as IMPDEF. We choose to reset to 3 to comply with
694
* both ARMv7 and ARMv8.
695
*/
696
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
697
static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
698
bool isread)
699
{
700
- /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
701
+ /*
702
+ * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
703
* At Secure EL1 it traps to EL3 or EL2.
704
*/
705
if (arm_current_el(env) == 3) {
706
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
707
}
708
}
709
710
-/* We don't know until after realize whether there's a GICv3
711
+/*
712
+ * We don't know until after realize whether there's a GICv3
713
* attached, and that is what registers the gicv3 sysregs.
714
* So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
715
* at runtime.
716
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
717
}
718
#endif
719
720
-/* Shared logic between LORID and the rest of the LOR* registers.
721
+/*
722
+ * Shared logic between LORID and the rest of the LOR* registers.
723
* Secure state exclusion has already been dealt with.
724
*/
725
static CPAccessResult access_lor_ns(CPUARMState *env,
726
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
727
728
define_arm_cp_regs(cpu, cp_reginfo);
729
if (!arm_feature(env, ARM_FEATURE_V8)) {
730
- /* Must go early as it is full of wildcards that may be
731
+ /*
732
+ * Must go early as it is full of wildcards that may be
733
* overridden by later definitions.
734
*/
735
define_arm_cp_regs(cpu, not_v8_cp_reginfo);
736
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
737
.access = PL1_R, .type = ARM_CP_CONST,
738
.accessfn = access_aa32_tid3,
739
.resetvalue = cpu->isar.id_pfr0 },
740
- /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
741
+ /*
742
+ * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
743
* the value of the GIC field until after we define these regs.
744
*/
745
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
746
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
747
748
define_arm_cp_regs(cpu, el3_regs);
749
}
750
- /* The behaviour of NSACR is sufficiently various that we don't
751
+ /*
752
+ * The behaviour of NSACR is sufficiently various that we don't
753
* try to describe it in a single reginfo:
754
* if EL3 is 64 bit, then trap to EL3 from S EL1,
755
* reads as constant 0xc00 from NS EL1 and NS EL2
756
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
757
if (cpu_isar_feature(aa32_jazelle, cpu)) {
758
define_arm_cp_regs(cpu, jazelle_regs);
759
}
760
- /* Slightly awkwardly, the OMAP and StrongARM cores need all of
761
+ /*
762
+ * Slightly awkwardly, the OMAP and StrongARM cores need all of
763
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
764
* be read-only (ie write causes UNDEF exception).
765
*/
766
{
767
ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
768
- /* Pre-v8 MIDR space.
769
+ /*
770
+ * Pre-v8 MIDR space.
771
* Note that the MIDR isn't a simple constant register because
772
* of the TI925 behaviour where writes to another register can
773
* cause the MIDR value to change.
774
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
775
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
776
arm_feature(env, ARM_FEATURE_STRONGARM)) {
777
size_t i;
778
- /* Register the blanket "writes ignored" value first to cover the
779
+ /*
780
+ * Register the blanket "writes ignored" value first to cover the
781
* whole space. Then update the specific ID registers to allow write
782
* access, so that they ignore writes rather than causing them to
783
* UNDEF.
784
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
785
.raw_writefn = raw_write,
786
};
787
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
788
- /* Normally we would always end the TB on an SCTLR write, but Linux
789
+ /*
790
+ * Normally we would always end the TB on an SCTLR write, but Linux
791
* arch/arm/mach-pxa/sleep.S expects two instructions following
792
* an MMU enable to execute from cache. Imitate this behaviour.
793
*/
794
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
795
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
796
const ARMCPRegInfo *r, void *opaque)
797
{
798
- /* Define implementations of coprocessor registers.
799
+ /*
800
+ * Define implementations of coprocessor registers.
801
* We store these in a hashtable because typically
802
* there are less than 150 registers in a space which
803
* is 16*16*16*8*8 = 262144 in size.
804
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
805
default:
806
g_assert_not_reached();
807
}
808
- /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
809
+ /*
810
+ * The AArch64 pseudocode CheckSystemAccess() specifies that op1
811
* encodes a minimum access level for the register. We roll this
812
* runtime check into our general permission check code, so check
813
* here that the reginfo's specified permissions are strict enough
814
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
815
assert((r->access & ~mask) == 0);
816
}
817
818
- /* Check that the register definition has enough info to handle
819
+ /*
820
+ * Check that the register definition has enough info to handle
821
* reads and writes if they are permitted.
822
*/
823
if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) {
824
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
825
continue;
826
}
827
if (state == ARM_CP_STATE_AA32) {
828
- /* Under AArch32 CP registers can be common
829
+ /*
830
+ * Under AArch32 CP registers can be common
831
* (same for secure and non-secure world) or banked.
832
*/
833
char *name;
834
@@ -XXX,XX +XXX,XX @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
835
g_assert_not_reached();
836
}
837
} else {
838
- /* AArch64 registers get mapped to non-secure instance
839
- * of AArch32 */
840
+ /*
841
+ * AArch64 registers get mapped to non-secure instance
842
+ * of AArch32
843
+ */
844
add_cpreg_to_hashtable(cpu, r, opaque, state,
845
ARM_CP_SECSTATE_NS,
846
crm, opc1, opc2, r->name);
847
@@ -XXX,XX +XXX,XX @@ void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
848
849
static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
850
{
851
- /* Return true if it is not valid for us to switch to
852
+ /*
853
+ * Return true if it is not valid for us to switch to
854
* this CPU mode (ie all the UNPREDICTABLE cases in
855
* the ARM ARM CPSRWriteByInstr pseudocode).
856
*/
857
@@ -XXX,XX +XXX,XX @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
858
case ARM_CPU_MODE_UND:
859
case ARM_CPU_MODE_IRQ:
860
case ARM_CPU_MODE_FIQ:
861
- /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
862
+ /*
863
+ * Note that we don't implement the IMPDEF NSACR.RFR which in v7
864
* allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
865
*/
866
- /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
867
+ /*
868
+ * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
869
* and CPS are treated as illegal mode changes.
870
*/
871
if (write_type == CPSRWriteByInstr &&
872
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
873
env->GE = (val >> 16) & 0xf;
874
}
875
876
- /* In a V7 implementation that includes the security extensions but does
877
+ /*
878
+ * In a V7 implementation that includes the security extensions but does
879
* not include Virtualization Extensions the SCR.FW and SCR.AW bits control
880
* whether non-secure software is allowed to change the CPSR_F and CPSR_A
881
* bits respectively.
882
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
883
changed_daif = (env->daif ^ val) & mask;
884
885
if (changed_daif & CPSR_A) {
886
- /* Check to see if we are allowed to change the masking of async
887
+ /*
888
+ * Check to see if we are allowed to change the masking of async
889
* abort exceptions from a non-secure state.
890
*/
891
if (!(env->cp15.scr_el3 & SCR_AW)) {
892
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
893
}
894
895
if (changed_daif & CPSR_F) {
896
- /* Check to see if we are allowed to change the masking of FIQ
897
+ /*
898
+ * Check to see if we are allowed to change the masking of FIQ
899
* exceptions from a non-secure state.
900
*/
901
if (!(env->cp15.scr_el3 & SCR_FW)) {
902
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
903
mask &= ~CPSR_F;
904
}
905
906
- /* Check whether non-maskable FIQ (NMFI) support is enabled.
907
+ /*
908
+ * Check whether non-maskable FIQ (NMFI) support is enabled.
909
* If this bit is set software is not allowed to mask
910
* FIQs, but is allowed to set CPSR_F to 0.
911
*/
912
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
913
if (write_type != CPSRWriteRaw &&
914
((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
915
if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
916
- /* Note that we can only get here in USR mode if this is a
917
+ /*
918
+ * Note that we can only get here in USR mode if this is a
919
* gdb stub write; for this case we follow the architectural
920
* behaviour for guest writes in USR mode of ignoring an attempt
921
* to switch mode. (Those are caught by translate.c for writes
922
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
923
*/
924
mask &= ~CPSR_M;
925
} else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
926
- /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
927
+ /*
928
+ * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
929
* v7, and has defined behaviour in v8:
930
* + leave CPSR.M untouched
931
* + allow changes to the other CPSR fields
932
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
933
env->regs[14] = env->banked_r14[r14_bank_number(mode)];
934
}
935
936
-/* Physical Interrupt Target EL Lookup Table
937
+/*
938
+ * Physical Interrupt Target EL Lookup Table
939
*
940
* [ From ARM ARM section G1.13.4 (Table G1-15) ]
941
*
942
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
943
if (arm_feature(env, ARM_FEATURE_EL3)) {
944
rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
945
} else {
946
- /* Either EL2 is the highest EL (and so the EL2 register width
947
+ /*
948
+ * Either EL2 is the highest EL (and so the EL2 register width
949
* is given by is64); or there is no EL2 or EL3, in which case
950
* the value of 'rw' does not affect the table lookup anyway.
951
*/
952
@@ -XXX,XX +XXX,XX @@ void aarch64_sync_64_to_32(CPUARMState *env)
953
env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
954
}
955
956
- /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
957
+ /*
958
+ * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
959
* mode, then we can copy to r8-r14. Otherwise, we copy to the
960
* FIQ bank for r8-r14.
961
*/
962
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
963
/* High vectors. When enabled, base address cannot be remapped. */
964
addr += 0xffff0000;
965
} else {
966
- /* ARM v7 architectures provide a vector base address register to remap
967
+ /*
968
+ * ARM v7 architectures provide a vector base address register to remap
969
* the interrupt vector table.
970
* This register is only followed in non-monitor mode, and is banked.
971
* Note: only bits 31:5 are valid.
972
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
973
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
974
975
if (cur_el < new_el) {
976
- /* Entry vector offset depends on whether the implemented EL
977
+ /*
978
+ * Entry vector offset depends on whether the implemented EL
979
* immediately lower than the target level is using AArch32 or AArch64
980
*/
981
bool is_aa64;
982
@@ -XXX,XX +XXX,XX @@ static void handle_semihosting(CPUState *cs)
983
}
984
#endif
985
986
-/* Handle a CPU exception for A and R profile CPUs.
987
+/*
988
+ * Handle a CPU exception for A and R profile CPUs.
989
* Do any appropriate logging, handle PSCI calls, and then hand off
990
* to the AArch64-entry or AArch32-entry function depending on the
991
* target exception level's register width.
992
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
993
}
994
#endif
995
996
- /* Hooks may change global state so BQL should be held, also the
997
+ /*
998
+ * Hooks may change global state so BQL should be held, also the
999
* BQL needs to be held for any modification of
1000
* cs->interrupt_request.
1001
*/
1002
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
1003
};
1004
}
1005
1006
-/* Note that signed overflow is undefined in C. The following routines are
1007
- careful to use unsigned types where modulo arithmetic is required.
1008
- Failure to do so _will_ break on newer gcc. */
1009
+/*
1010
+ * Note that signed overflow is undefined in C. The following routines are
1011
+ * careful to use unsigned types where modulo arithmetic is required.
1012
+ * Failure to do so _will_ break on newer gcc.
1013
+ */
1014
1015
/* Signed saturating arithmetic. */
1016
1017
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
1018
return (a & mask) | (b & ~mask);
1019
}
1020
1021
-/* CRC helpers.
1022
+/*
1023
+ * CRC helpers.
1024
* The upper bytes of val (above the number specified by 'bytes') must have
1025
* been zeroed out by the caller.
1026
*/
1027
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
1028
return crc32c(acc, buf, bytes) ^ 0xffffffff;
1029
}
1030
1031
-/* Return the exception level to which FP-disabled exceptions should
1032
+/*
1033
+ * Return the exception level to which FP-disabled exceptions should
1034
* be taken, or 0 if FP is enabled.
1035
*/
1036
int fp_exception_el(CPUARMState *env, int cur_el)
1037
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
1038
#ifndef CONFIG_USER_ONLY
1039
uint64_t hcr_el2;
1040
1041
- /* CPACR and the CPTR registers don't exist before v6, so FP is
1042
+ /*
1043
+ * CPACR and the CPTR registers don't exist before v6, so FP is
1044
* always accessible
1045
*/
1046
if (!arm_feature(env, ARM_FEATURE_V6)) {
1047
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
1048
1049
hcr_el2 = arm_hcr_el2_eff(env);
1050
1051
- /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
1052
+ /*
1053
+ * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
1054
* 0, 2 : trap EL0 and EL1/PL1 accesses
1055
* 1 : trap only EL0 accesses
1056
* 3 : trap no accesses
163
--
1057
--
164
2.20.1
1058
2.25.1
165
166
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Add left-shift to match the existing right-shift.
3
Fix the following:
4
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
ERROR: spaces required around that '|' (ctx:VxV)
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
ERROR: space required before the open parenthesis '('
7
Message-id: 20200815013145.539409-2-richard.henderson@linaro.org
7
ERROR: spaces required around that '+' (ctx:VxB)
8
ERROR: space prohibited between function name and open parenthesis '('
9
10
(the last two still have some occurrences in macros which I left
11
behind because it might impact readability)
12
13
Signed-off-by: Fabiano Rosas <farosas@suse.de>
14
Reviewed-by: Claudio Fontana <cfontana@suse.de>
15
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
16
Message-id: 20221213190537.511-3-farosas@suse.de
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
18
---
10
include/qemu/int128.h | 16 ++++++++++++++++
19
target/arm/helper.c | 42 +++++++++++++++++++++---------------------
11
1 file changed, 16 insertions(+)
20
1 file changed, 21 insertions(+), 21 deletions(-)
12
21
13
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
15
--- a/include/qemu/int128.h
24
--- a/target/arm/helper.c
16
+++ b/include/qemu/int128.h
25
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_rshift(Int128 a, int n)
26
@@ -XXX,XX +XXX,XX @@ static void add_cpreg_to_list(gpointer key, gpointer opaque)
18
return a >> n;
27
uint32_t regidx = (uintptr_t)key;
19
}
28
const ARMCPRegInfo *ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
20
29
21
+static inline Int128 int128_lshift(Int128 a, int n)
30
- if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
22
+{
31
+ if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
23
+ return a << n;
32
cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
24
+}
33
/* The value array need not be initialized at this point */
25
+
34
cpu->cpreg_array_len++;
26
static inline Int128 int128_add(Int128 a, Int128 b)
35
@@ -XXX,XX +XXX,XX @@ static void count_cpreg(gpointer key, gpointer opaque)
27
{
36
28
return a + b;
37
ri = g_hash_table_lookup(cpu->cp_regs, key);
29
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_rshift(Int128 a, int n)
38
39
- if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
40
+ if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) {
41
cpu->cpreg_array_len++;
30
}
42
}
31
}
43
}
32
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
33
+static inline Int128 int128_lshift(Int128 a, int n)
45
.resetfn = arm_cp_reset_ignore },
34
+{
46
{ .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
35
+ uint64_t l = a.lo << (n & 63);
47
.opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
36
+ if (n >= 64) {
48
- .access = PL0_R|PL1_W,
37
+ return int128_make128(0, l);
49
+ .access = PL0_R | PL1_W,
38
+ } else if (n > 0) {
50
.fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
39
+ return int128_make128(l, (a.hi << n) | (a.lo >> (64 - n)));
51
.resetvalue = 0},
40
+ }
52
{ .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
41
+ return a;
53
- .access = PL0_R|PL1_W,
42
+}
54
+ .access = PL0_R | PL1_W,
43
+
55
.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
44
static inline Int128 int128_add(Int128 a, Int128 b)
56
offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
45
{
57
.resetfn = arm_cp_reset_ignore },
46
uint64_t lo = a.lo + b.lo;
58
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
59
.resetvalue = 0 },
60
/* The cache ops themselves: these all NOP for QEMU */
61
{ .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
62
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
63
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
64
{ .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
65
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
66
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
67
{ .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
68
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
69
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
70
{ .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
71
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
72
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
73
{ .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
74
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
75
+ .access = PL0_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
76
{ .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
77
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
78
+ .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_64BIT },
79
};
80
81
static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
82
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
83
ARMCPRegInfo cbar = {
84
.name = "CBAR",
85
.cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
86
- .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
87
+ .access = PL1_R | PL3_W, .resetvalue = cpu->reset_cbar,
88
.fieldoffset = offsetof(CPUARMState,
89
cp15.c15_config_base_address)
90
};
91
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
92
return;
93
94
if (old_mode == ARM_CPU_MODE_FIQ) {
95
- memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
96
- memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
97
+ memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
98
+ memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
99
} else if (mode == ARM_CPU_MODE_FIQ) {
100
- memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
101
- memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
102
+ memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
103
+ memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
104
}
105
106
i = bank_number(old_mode);
107
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
108
RESULT(sum, n, 16); \
109
if (sum >= 0) \
110
ge |= 3 << (n * 2); \
111
- } while(0)
112
+ } while (0)
113
114
#define SARITH8(a, b, n, op) do { \
115
int32_t sum; \
116
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
117
RESULT(sum, n, 8); \
118
if (sum >= 0) \
119
ge |= 1 << n; \
120
- } while(0)
121
+ } while (0)
122
123
124
#define ADD16(a, b, n) SARITH16(a, b, n, +)
125
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
126
RESULT(sum, n, 16); \
127
if ((sum >> 16) == 1) \
128
ge |= 3 << (n * 2); \
129
- } while(0)
130
+ } while (0)
131
132
#define ADD8(a, b, n) do { \
133
uint32_t sum; \
134
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
135
RESULT(sum, n, 8); \
136
if ((sum >> 8) == 1) \
137
ge |= 1 << n; \
138
- } while(0)
139
+ } while (0)
140
141
#define SUB16(a, b, n) do { \
142
uint32_t sum; \
143
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
144
RESULT(sum, n, 16); \
145
if ((sum >> 16) == 0) \
146
ge |= 3 << (n * 2); \
147
- } while(0)
148
+ } while (0)
149
150
#define SUB8(a, b, n) do { \
151
uint32_t sum; \
152
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
153
RESULT(sum, n, 8); \
154
if ((sum >> 8) == 0) \
155
ge |= 1 << n; \
156
- } while(0)
157
+ } while (0)
158
159
#define PFX u
160
#define ARITH_GE
47
--
161
--
48
2.20.1
162
2.25.1
49
50
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Move the check for !S into do_pppp_flags, which allows to merge in
3
Fix this:
4
do_vecop4_p. Split out gen_gvec_fn_ppp without sve_access_check,
4
ERROR: braces {} are necessary for all arms of this statement
5
to mirror gen_gvec_fn_zzz.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Fabiano Rosas <farosas@suse.de>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Claudio Fontana <cfontana@suse.de>
9
Message-id: 20200815013145.539409-7-richard.henderson@linaro.org
8
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
9
Message-id: 20221213190537.511-4-farosas@suse.de
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/translate-sve.c | 111 ++++++++++++++-----------------------
12
target/arm/helper.c | 67 ++++++++++++++++++++++++++++-----------------
13
1 file changed, 43 insertions(+), 68 deletions(-)
13
1 file changed, 42 insertions(+), 25 deletions(-)
14
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
17
--- a/target/arm/helper.c
18
+++ b/target/arm/translate-sve.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
19
@@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
20
env->CF = (val >> 29) & 1;
21
env->VF = (val << 3) & 0x80000000;
22
}
23
- if (mask & CPSR_Q)
24
+ if (mask & CPSR_Q) {
25
env->QF = ((val & CPSR_Q) != 0);
26
- if (mask & CPSR_T)
27
+ }
28
+ if (mask & CPSR_T) {
29
env->thumb = ((val & CPSR_T) != 0);
30
+ }
31
if (mask & CPSR_IT_0_1) {
32
env->condexec_bits &= ~3;
33
env->condexec_bits |= (val >> 25) & 3;
34
@@ -XXX,XX +XXX,XX @@ static void switch_mode(CPUARMState *env, int mode)
35
int i;
36
37
old_mode = env->uncached_cpsr & CPSR_M;
38
- if (mode == old_mode)
39
+ if (mode == old_mode) {
40
return;
41
+ }
42
43
if (old_mode == ARM_CPU_MODE_FIQ) {
44
memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
45
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
46
new_mode = ARM_CPU_MODE_UND;
47
addr = 0x04;
48
mask = CPSR_I;
49
- if (env->thumb)
50
+ if (env->thumb) {
51
offset = 2;
52
- else
53
+ } else {
54
offset = 4;
55
+ }
56
break;
57
case EXCP_SWI:
58
new_mode = ARM_CPU_MODE_SVC;
59
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_sat(uint16_t a, uint16_t b)
60
61
res = a + b;
62
if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
63
- if (a & 0x8000)
64
+ if (a & 0x8000) {
65
res = 0x8000;
66
- else
67
+ } else {
68
res = 0x7fff;
69
+ }
70
}
71
return res;
20
}
72
}
21
73
@@ -XXX,XX +XXX,XX @@ static inline uint8_t add8_sat(uint8_t a, uint8_t b)
22
/* Invoke a vector expander on three Pregs. */
74
23
-static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
75
res = a + b;
24
- int esz, int rd, int rn, int rm)
76
if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
25
+static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
77
- if (a & 0x80)
26
+ int rd, int rn, int rm)
78
+ if (a & 0x80) {
79
res = 0x80;
80
- else
81
+ } else {
82
res = 0x7f;
83
+ }
84
}
85
return res;
86
}
87
@@ -XXX,XX +XXX,XX @@ static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
88
89
res = a - b;
90
if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
91
- if (a & 0x8000)
92
+ if (a & 0x8000) {
93
res = 0x8000;
94
- else
95
+ } else {
96
res = 0x7fff;
97
+ }
98
}
99
return res;
100
}
101
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
102
103
res = a - b;
104
if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
105
- if (a & 0x80)
106
+ if (a & 0x80) {
107
res = 0x80;
108
- else
109
+ } else {
110
res = 0x7f;
111
+ }
112
}
113
return res;
114
}
115
@@ -XXX,XX +XXX,XX @@ static inline uint16_t add16_usat(uint16_t a, uint16_t b)
27
{
116
{
28
- if (sve_access_check(s)) {
117
uint16_t res;
29
- unsigned psz = pred_gvec_reg_size(s);
118
res = a + b;
30
- gvec_fn(esz, pred_full_reg_offset(s, rd),
119
- if (res < a)
31
- pred_full_reg_offset(s, rn),
120
+ if (res < a) {
32
- pred_full_reg_offset(s, rm), psz, psz);
121
res = 0xffff;
33
- }
122
+ }
34
- return true;
123
return res;
35
-}
36
-
37
-/* Invoke a vector operation on four Pregs. */
38
-static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op,
39
- int rd, int rn, int rm, int rg)
40
-{
41
- if (sve_access_check(s)) {
42
- unsigned psz = pred_gvec_reg_size(s);
43
- tcg_gen_gvec_4(pred_full_reg_offset(s, rd),
44
- pred_full_reg_offset(s, rn),
45
- pred_full_reg_offset(s, rm),
46
- pred_full_reg_offset(s, rg),
47
- psz, psz, gvec_op);
48
- }
49
- return true;
50
+ unsigned psz = pred_gvec_reg_size(s);
51
+ gvec_fn(MO_64, pred_full_reg_offset(s, rd),
52
+ pred_full_reg_offset(s, rn),
53
+ pred_full_reg_offset(s, rm), psz, psz);
54
}
124
}
55
125
56
/* Invoke a vector move on two Pregs. */
126
static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
57
@@ -XXX,XX +XXX,XX @@ static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a,
127
{
58
int mofs = pred_full_reg_offset(s, a->rm);
128
- if (a > b)
59
int gofs = pred_full_reg_offset(s, a->pg);
129
+ if (a > b) {
60
130
return a - b;
61
+ if (!a->s) {
131
- else
62
+ tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op);
132
+ } else {
63
+ return true;
133
return 0;
64
+ }
134
+ }
65
+
66
if (psz == 8) {
67
/* Do the operation and the flags generation in temps. */
68
TCGv_i64 pd = tcg_temp_new_i64();
69
@@ -XXX,XX +XXX,XX @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
70
.fno = gen_helper_sve_and_pppp,
71
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
72
};
73
- if (a->s) {
74
- return do_pppp_flags(s, a, &op);
75
- } else if (a->rn == a->rm) {
76
- if (a->pg == a->rn) {
77
- return do_mov_p(s, a->rd, a->rn);
78
- } else {
79
- return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->pg);
80
+
81
+ if (!a->s) {
82
+ if (!sve_access_check(s)) {
83
+ return true;
84
+ }
85
+ if (a->rn == a->rm) {
86
+ if (a->pg == a->rn) {
87
+ do_mov_p(s, a->rd, a->rn);
88
+ } else {
89
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
90
+ }
91
+ return true;
92
+ } else if (a->pg == a->rn || a->pg == a->rm) {
93
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
94
+ return true;
95
}
96
- } else if (a->pg == a->rn || a->pg == a->rm) {
97
- return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
98
- } else {
99
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
100
}
101
+ return do_pppp_flags(s, a, &op);
102
}
135
}
103
136
104
static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
137
static inline uint8_t add8_usat(uint8_t a, uint8_t b)
105
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
138
{
106
.fno = gen_helper_sve_bic_pppp,
139
uint8_t res;
107
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
140
res = a + b;
108
};
141
- if (res < a)
109
- if (a->s) {
142
+ if (res < a) {
110
- return do_pppp_flags(s, a, &op);
143
res = 0xff;
111
- } else if (a->pg == a->rn) {
144
+ }
112
- return do_vector3_p(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
145
return res;
113
- } else {
114
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
115
+
116
+ if (!a->s && a->pg == a->rn) {
117
+ if (sve_access_check(s)) {
118
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
119
+ }
120
+ return true;
121
}
122
+ return do_pppp_flags(s, a, &op);
123
}
146
}
124
147
125
static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
148
static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
126
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
149
{
127
.fno = gen_helper_sve_eor_pppp,
150
- if (a > b)
128
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
151
+ if (a > b) {
129
};
152
return a - b;
130
- if (a->s) {
153
- else
131
- return do_pppp_flags(s, a, &op);
154
+ } else {
132
- } else {
155
return 0;
133
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
156
+ }
134
- }
135
+ return do_pppp_flags(s, a, &op);
136
}
157
}
137
158
138
static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
159
#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
139
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
160
@@ -XXX,XX +XXX,XX @@ static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
140
.fno = gen_helper_sve_sel_pppp,
161
141
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
162
static inline uint8_t do_usad(uint8_t a, uint8_t b)
142
};
163
{
143
+
164
- if (a > b)
144
if (a->s) {
165
+ if (a > b) {
145
return false;
166
return a - b;
146
- } else {
167
- else
147
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
168
+ } else {
148
}
169
return b - a;
149
+ return do_pppp_flags(s, a, &op);
170
+ }
150
}
171
}
151
172
152
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
173
/* Unsigned sum of absolute byte differences. */
153
@@ -XXX,XX +XXX,XX @@ static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a)
174
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
154
.fno = gen_helper_sve_orr_pppp,
175
uint32_t mask;
155
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
176
156
};
177
mask = 0;
157
- if (a->s) {
178
- if (flags & 1)
158
- return do_pppp_flags(s, a, &op);
179
+ if (flags & 1) {
159
- } else if (a->pg == a->rn && a->rn == a->rm) {
180
mask |= 0xff;
160
+
181
- if (flags & 2)
161
+ if (!a->s && a->pg == a->rn && a->rn == a->rm) {
182
+ }
162
return do_mov_p(s, a->rd, a->rn);
183
+ if (flags & 2) {
163
- } else {
184
mask |= 0xff00;
164
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
185
- if (flags & 4)
165
}
186
+ }
166
+ return do_pppp_flags(s, a, &op);
187
+ if (flags & 4) {
188
mask |= 0xff0000;
189
- if (flags & 8)
190
+ }
191
+ if (flags & 8) {
192
mask |= 0xff000000;
193
+ }
194
return (a & mask) | (b & ~mask);
167
}
195
}
168
196
169
static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
170
@@ -XXX,XX +XXX,XX @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a)
171
.fno = gen_helper_sve_orn_pppp,
172
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
173
};
174
- if (a->s) {
175
- return do_pppp_flags(s, a, &op);
176
- } else {
177
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
178
- }
179
+ return do_pppp_flags(s, a, &op);
180
}
181
182
static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
183
@@ -XXX,XX +XXX,XX @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a)
184
.fno = gen_helper_sve_nor_pppp,
185
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
186
};
187
- if (a->s) {
188
- return do_pppp_flags(s, a, &op);
189
- } else {
190
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
191
- }
192
+ return do_pppp_flags(s, a, &op);
193
}
194
195
static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
196
@@ -XXX,XX +XXX,XX @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a)
197
.fno = gen_helper_sve_nand_pppp,
198
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
199
};
200
- if (a->s) {
201
- return do_pppp_flags(s, a, &op);
202
- } else {
203
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
204
- }
205
+ return do_pppp_flags(s, a, &op);
206
}
207
208
/*
209
--
197
--
210
2.20.1
198
2.25.1
211
212
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Fabiano Rosas <farosas@suse.de>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Claudio Fontana <cfontana@suse.de>
5
Message-id: 20200815013145.539409-19-richard.henderson@linaro.org
5
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
6
Message-id: 20221213190537.511-5-farosas@suse.de
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
---
8
target/arm/helper.h | 4 ++++
9
target/arm/m_helper.c | 16 ----------------
9
target/arm/translate-a64.c | 16 ++++++++++++++++
10
1 file changed, 16 deletions(-)
10
target/arm/vec_helper.c | 29 +++++++++++++++++++++++++----
11
3 files changed, 45 insertions(+), 4 deletions(-)
12
11
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
12
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.h
14
--- a/target/arm/m_helper.c
16
+++ b/target/arm/helper.h
15
+++ b/target/arm/m_helper.c
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
16
@@ -XXX,XX +XXX,XX @@
18
DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
19
DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
20
21
+DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
22
+DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
23
+DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
24
+
25
#ifdef TARGET_AARCH64
26
#include "helper-a64.h"
27
#include "helper-sve.h"
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate-a64.c
31
+++ b/target/arm/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
33
data, gen_helper_gvec_fmlal_idx_a64);
34
}
35
return;
36
+
37
+ case 0x08: /* MUL */
38
+ if (!is_long && !is_scalar) {
39
+ static gen_helper_gvec_3 * const fns[3] = {
40
+ gen_helper_gvec_mul_idx_h,
41
+ gen_helper_gvec_mul_idx_s,
42
+ gen_helper_gvec_mul_idx_d,
43
+ };
44
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
45
+ vec_full_reg_offset(s, rn),
46
+ vec_full_reg_offset(s, rm),
47
+ is_q ? 16 : 8, vec_full_reg_size(s),
48
+ index, fns[size - 1]);
49
+ return;
50
+ }
51
+ break;
52
}
53
54
if (size == 3) {
55
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/vec_helper.c
58
+++ b/target/arm/vec_helper.c
59
@@ -XXX,XX +XXX,XX @@ DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
60
*/
17
*/
61
18
62
#define DO_MUL_IDX(NAME, TYPE, H) \
19
#include "qemu/osdep.h"
63
+void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
20
-#include "qemu/units.h"
64
+{ \
21
-#include "target/arm/idau.h"
65
+ intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
22
-#include "trace.h"
66
+ intptr_t idx = simd_data(desc); \
23
#include "cpu.h"
67
+ TYPE *d = vd, *n = vn, *m = vm; \
24
#include "internals.h"
68
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
25
-#include "exec/gdbstub.h"
69
+ TYPE mm = m[H(i + idx)]; \
26
#include "exec/helper-proto.h"
70
+ for (j = 0; j < segment; j++) { \
27
-#include "qemu/host-utils.h"
71
+ d[i + j] = n[i + j] * mm; \
28
#include "qemu/main-loop.h"
72
+ } \
29
#include "qemu/bitops.h"
73
+ } \
30
-#include "qemu/crc32c.h"
74
+ clear_tail(d, oprsz, simd_maxsz(desc)); \
31
-#include "qemu/qemu-print.h"
75
+}
32
#include "qemu/log.h"
76
+
33
#include "exec/exec-all.h"
77
+DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2)
34
-#include <zlib.h> /* For crc32 */
78
+DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4)
35
-#include "semihosting/semihost.h"
79
+DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
36
-#include "sysemu/cpus.h"
80
+
37
-#include "sysemu/kvm.h"
81
+#undef DO_MUL_IDX
38
-#include "qemu/range.h"
82
+
39
-#include "qapi/qapi-commands-machine-target.h"
83
+#define DO_FMUL_IDX(NAME, TYPE, H) \
40
-#include "qapi/error.h"
84
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
41
-#include "qemu/guest-random.h"
85
{ \
42
#ifdef CONFIG_TCG
86
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
43
-#include "arm_ldst.h"
87
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
44
#include "exec/cpu_ldst.h"
88
clear_tail(d, oprsz, simd_maxsz(desc)); \
45
#include "semihosting/common-semi.h"
89
}
46
#endif
90
91
-DO_MUL_IDX(gvec_fmul_idx_h, float16, H2)
92
-DO_MUL_IDX(gvec_fmul_idx_s, float32, H4)
93
-DO_MUL_IDX(gvec_fmul_idx_d, float64, )
94
+DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2)
95
+DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4)
96
+DO_FMUL_IDX(gvec_fmul_idx_d, float64, )
97
98
-#undef DO_MUL_IDX
99
+#undef DO_FMUL_IDX
100
101
#define DO_FMLA_IDX(NAME, TYPE, H) \
102
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
103
--
47
--
104
2.20.1
48
2.25.1
105
106
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Fabiano Rosas <farosas@suse.de>
2
2
3
In commit ce4afed839 ("target/arm: Implement AArch32 HCR and HCR2")
3
Signed-off-by: Fabiano Rosas <farosas@suse.de>
4
the HCR_EL2 register has been changed from type NO_RAW (no underlying
4
Reviewed-by: Claudio Fontana <cfontana@suse.de>
5
state and does not support raw access for state saving/loading) to
5
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
6
type CONST (TCG can assume the value to be constant), removing the
6
Message-id: 20221213190537.511-6-farosas@suse.de
7
read/write accessors.
8
We forgot to remove the previous type ARM_CP_NO_RAW. This is not
9
really a problem since the field is overwritten. However it makes
10
code review confuse, so remove it.
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200812111223.7787-1-f4bug@amsat.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
8
---
18
target/arm/helper.c | 1 -
9
target/arm/helper.c | 7 -------
19
1 file changed, 1 deletion(-)
10
1 file changed, 7 deletions(-)
20
11
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
14
--- a/target/arm/helper.c
24
+++ b/target/arm/helper.c
15
+++ b/target/arm/helper.c
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
16
@@ -XXX,XX +XXX,XX @@
26
.access = PL2_RW,
17
*/
27
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
18
28
{ .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
19
#include "qemu/osdep.h"
29
- .type = ARM_CP_NO_RAW,
20
-#include "qemu/units.h"
30
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
21
#include "qemu/log.h"
31
.access = PL2_RW,
22
#include "trace.h"
32
.type = ARM_CP_CONST, .resetvalue = 0 },
23
#include "cpu.h"
24
#include "internals.h"
25
#include "exec/helper-proto.h"
26
-#include "qemu/host-utils.h"
27
#include "qemu/main-loop.h"
28
#include "qemu/timer.h"
29
#include "qemu/bitops.h"
30
@@ -XXX,XX +XXX,XX @@
31
#include "exec/exec-all.h"
32
#include <zlib.h> /* For crc32 */
33
#include "hw/irq.h"
34
-#include "semihosting/semihost.h"
35
-#include "sysemu/cpus.h"
36
#include "sysemu/cpu-timers.h"
37
#include "sysemu/kvm.h"
38
-#include "qemu/range.h"
39
#include "qapi/qapi-commands-machine-target.h"
40
#include "qapi/error.h"
41
#include "qemu/guest-random.h"
42
#ifdef CONFIG_TCG
43
-#include "arm_ldst.h"
44
-#include "exec/cpu_ldst.h"
45
#include "semihosting/common-semi.h"
46
#endif
47
#include "cpregs.h"
33
--
48
--
34
2.20.1
49
2.25.1
35
36
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Claudio Fontana <cfontana@suse.de>
2
2
3
To quickly notice the access size, display the value with the
3
Remove some unused headers.
4
width of the access (i.e. 16-bit access is displayed 0x0000,
5
while 8-bit access 0x00).
6
4
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Claudio Fontana <cfontana@suse.de>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Acked-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200812190206.31595-3-f4bug@amsat.org
7
Reviewed-by: Claudio Fontana <cfontana@suse.de>
8
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
9
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Message-id: 20221213190537.511-7-farosas@suse.de
11
[added back some includes that are still needed at this point]
12
Signed-off-by: Fabiano Rosas <farosas@suse.de>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
hw/misc/unimp.c | 4 ++--
15
target/arm/cpu.c | 1 -
13
1 file changed, 2 insertions(+), 2 deletions(-)
16
target/arm/cpu64.c | 6 ------
17
2 files changed, 7 deletions(-)
14
18
15
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
19
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/misc/unimp.c
21
--- a/target/arm/cpu.c
18
+++ b/hw/misc/unimp.c
22
+++ b/target/arm/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
23
@@ -XXX,XX +XXX,XX @@
20
24
#include "target/arm/idau.h"
21
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
25
#include "qemu/module.h"
22
"(size %d, offset 0x%" HWADDR_PRIx
26
#include "qapi/error.h"
23
- ", value 0x%" PRIx64 ")\n",
27
-#include "qapi/visitor.h"
24
- s->name, size, offset, value);
28
#include "cpu.h"
25
+ ", value 0x%0*" PRIx64 ")\n",
29
#ifdef CONFIG_TCG
26
+ s->name, size, offset, size << 1, value);
30
#include "hw/core/tcg-cpu-ops.h"
27
}
31
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
28
32
index XXXXXXX..XXXXXXX 100644
29
static const MemoryRegionOps unimp_ops = {
33
--- a/target/arm/cpu64.c
34
+++ b/target/arm/cpu64.c
35
@@ -XXX,XX +XXX,XX @@
36
#include "qemu/osdep.h"
37
#include "qapi/error.h"
38
#include "cpu.h"
39
-#ifdef CONFIG_TCG
40
-#include "hw/core/tcg-cpu-ops.h"
41
-#endif /* CONFIG_TCG */
42
#include "qemu/module.h"
43
-#if !defined(CONFIG_USER_ONLY)
44
-#include "hw/loader.h"
45
-#endif
46
#include "sysemu/kvm.h"
47
#include "sysemu/hvf.h"
48
#include "kvm_arm.h"
30
--
49
--
31
2.20.1
50
2.25.1
32
33
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Clock canonical name is set in device_set_realized (see the block
3
The pointed MouseTransformInfo structure is accessed read-only.
4
added to hw/core/qdev.c in commit 0e6934f264).
5
If we connect a clock after the device is realized, this code is
6
not executed. This is currently not a problem as this name is only
7
used for trace events, however this disrupt tracing.
8
4
9
Add a comment to document qdev_connect_clock_in() must be called
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
before the device is realized, and assert this condition.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
7
Message-id: 20221220142520.24094-2-philmd@linaro.org
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-id: 20200803105647.22223-5-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
9
---
17
include/hw/qdev-clock.h | 2 ++
10
include/hw/input/tsc2xxx.h | 4 ++--
18
hw/core/qdev-clock.c | 1 +
11
hw/input/tsc2005.c | 2 +-
19
2 files changed, 3 insertions(+)
12
hw/input/tsc210x.c | 3 +--
13
3 files changed, 4 insertions(+), 5 deletions(-)
20
14
21
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
15
diff --git a/include/hw/input/tsc2xxx.h b/include/hw/input/tsc2xxx.h
22
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/qdev-clock.h
17
--- a/include/hw/input/tsc2xxx.h
24
+++ b/include/hw/qdev-clock.h
18
+++ b/include/hw/input/tsc2xxx.h
25
@@ -XXX,XX +XXX,XX @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
19
@@ -XXX,XX +XXX,XX @@ uWireSlave *tsc2102_init(qemu_irq pint);
26
*
20
uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav);
27
* Set the source clock of input clock @name of device @dev to @source.
21
I2SCodec *tsc210x_codec(uWireSlave *chip);
28
* @source period update will be propagated to @name clock.
22
uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len);
29
+ *
23
-void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info);
30
+ * Must be called before @dev is realized.
24
+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info);
25
void tsc210x_key_event(uWireSlave *chip, int key, int down);
26
27
/* tsc2005.c */
28
void *tsc2005_init(qemu_irq pintdav);
29
uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len);
30
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info);
31
+void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info);
32
33
#endif
34
diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/input/tsc2005.c
37
+++ b/hw/input/tsc2005.c
38
@@ -XXX,XX +XXX,XX @@ void *tsc2005_init(qemu_irq pintdav)
39
* from the touchscreen. Assuming 12-bit precision was used during
40
* tslib calibration.
31
*/
41
*/
32
void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source);
42
-void tsc2005_set_transform(void *opaque, MouseTransformInfo *info)
33
43
+void tsc2005_set_transform(void *opaque, const MouseTransformInfo *info)
34
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
44
{
45
TSC2005State *s = (TSC2005State *) opaque;
46
47
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
35
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/core/qdev-clock.c
49
--- a/hw/input/tsc210x.c
37
+++ b/hw/core/qdev-clock.c
50
+++ b/hw/input/tsc210x.c
38
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
51
@@ -XXX,XX +XXX,XX @@ I2SCodec *tsc210x_codec(uWireSlave *chip)
39
52
* from the touchscreen. Assuming 12-bit precision was used during
40
void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source)
53
* tslib calibration.
54
*/
55
-void tsc210x_set_transform(uWireSlave *chip,
56
- MouseTransformInfo *info)
57
+void tsc210x_set_transform(uWireSlave *chip, const MouseTransformInfo *info)
41
{
58
{
42
+ assert(!dev->realized);
59
TSC210xState *s = (TSC210xState *) chip->opaque;
43
clock_set_source(qdev_get_clock_in(dev, name), source);
60
#if 0
44
}
45
--
61
--
46
2.20.1
62
2.25.1
47
63
48
64
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Clock canonical name is set in device_set_realized (see the block
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
added to hw/core/qdev.c in commit 0e6934f264).
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
If we connect a clock after the device is realized, this code is
5
Message-id: 20221220142520.24094-3-philmd@linaro.org
6
not executed. This is currently not a problem as this name is only
7
used for trace events, however this disrupt tracing.
8
9
Fix by calling qdev_connect_clock_in() before realizing.
10
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20200803105647.22223-3-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
7
---
16
hw/arm/xilinx_zynq.c | 18 +++++++++---------
8
hw/arm/nseries.c | 18 +++++++++---------
17
1 file changed, 9 insertions(+), 9 deletions(-)
9
1 file changed, 9 insertions(+), 9 deletions(-)
18
10
19
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
11
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
20
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/xilinx_zynq.c
13
--- a/hw/arm/nseries.c
22
+++ b/hw/arm/xilinx_zynq.c
14
+++ b/hw/arm/nseries.c
23
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
15
@@ -XXX,XX +XXX,XX @@ static void n8x0_i2c_setup(struct n800_s *s)
24
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
16
}
25
0);
17
26
18
/* Touchscreen and keypad controller */
27
- /* Create slcr, keep a pointer to connect clocks */
19
-static MouseTransformInfo n800_pointercal = {
28
- slcr = qdev_new("xilinx,zynq_slcr");
20
+static const MouseTransformInfo n800_pointercal = {
29
- sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
21
.x = 800,
30
- sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
22
.y = 480,
31
-
23
.a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 },
32
/* Create the main clock source, and feed slcr with it */
24
};
33
zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
25
34
object_property_add_child(OBJECT(zynq_machine), "ps_clk",
26
-static MouseTransformInfo n810_pointercal = {
35
OBJECT(zynq_machine->ps_clk));
27
+static const MouseTransformInfo n810_pointercal = {
36
object_unref(OBJECT(zynq_machine->ps_clk));
28
.x = 800,
37
clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
29
.y = 480,
38
+
30
.a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 },
39
+ /* Create slcr, keep a pointer to connect clocks */
31
@@ -XXX,XX +XXX,XX @@ static void n810_key_event(void *opaque, int keycode)
40
+ slcr = qdev_new("xilinx,zynq_slcr");
32
41
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
33
#define M    0
42
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
34
43
+ sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
35
-static int n810_keys[0x80] = {
44
36
+static const int n810_keys[0x80] = {
45
dev = qdev_new(TYPE_A9MPCORE_PRIV);
37
[0x01] = 16,    /* Q */
46
qdev_prop_set_uint32(dev, "num-cpu", 1);
38
[0x02] = 37,    /* K */
47
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
39
[0x03] = 24,    /* O */
48
dev = qdev_new(TYPE_CADENCE_UART);
40
@@ -XXX,XX +XXX,XX @@ static void n8x0_usb_setup(struct n800_s *s)
49
busdev = SYS_BUS_DEVICE(dev);
41
/* Setup done before the main bootloader starts by some early setup code
50
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
42
* - used when we want to run the main bootloader in emulation. This
51
+ qdev_connect_clock_in(dev, "refclk",
43
* isn't documented. */
52
+ qdev_get_clock_out(slcr, "uart0_ref_clk"));
44
-static uint32_t n800_pinout[104] = {
53
sysbus_realize_and_unref(busdev, &error_fatal);
45
+static const uint32_t n800_pinout[104] = {
54
sysbus_mmio_map(busdev, 0, 0xE0000000);
46
0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0,
55
sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
47
0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808,
56
- qdev_connect_clock_in(dev, "refclk",
48
0x08080808, 0x180800c4, 0x00b80000, 0x08080808,
57
- qdev_get_clock_out(slcr, "uart0_ref_clk"));
49
@@ -XXX,XX +XXX,XX @@ static void n8x0_boot_init(void *opaque)
58
dev = qdev_new(TYPE_CADENCE_UART);
50
#define OMAP_TAG_CBUS        0x4e03
59
busdev = SYS_BUS_DEVICE(dev);
51
#define OMAP_TAG_EM_ASIC_BB5    0x4e04
60
qdev_prop_set_chr(dev, "chardev", serial_hd(1));
52
61
+ qdev_connect_clock_in(dev, "refclk",
53
-static struct omap_gpiosw_info_s {
62
+ qdev_get_clock_out(slcr, "uart1_ref_clk"));
54
+static const struct omap_gpiosw_info_s {
63
sysbus_realize_and_unref(busdev, &error_fatal);
55
const char *name;
64
sysbus_mmio_map(busdev, 0, 0xE0001000);
56
int line;
65
sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
57
int type;
66
- qdev_connect_clock_in(dev, "refclk",
58
@@ -XXX,XX +XXX,XX @@ static struct omap_gpiosw_info_s {
67
- qdev_get_clock_out(slcr, "uart1_ref_clk"));
59
{ NULL }
68
60
};
69
sysbus_create_varargs("cadence_ttc", 0xF8001000,
61
70
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
62
-static struct omap_partition_info_s {
63
+static const struct omap_partition_info_s {
64
uint32_t offset;
65
uint32_t size;
66
int mask;
67
@@ -XXX,XX +XXX,XX @@ static struct omap_partition_info_s {
68
{ 0, 0, 0, NULL }
69
};
70
71
-static uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
72
+static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
73
74
static int n8x0_atag_setup(void *p, int model)
75
{
76
uint8_t *b;
77
uint16_t *w;
78
uint32_t *l;
79
- struct omap_gpiosw_info_s *gpiosw;
80
- struct omap_partition_info_s *partition;
81
+ const struct omap_gpiosw_info_s *gpiosw;
82
+ const struct omap_partition_info_s *partition;
83
const char *tag;
84
85
w = p;
71
--
86
--
72
2.20.1
87
2.25.1
73
88
74
89
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
We want to assert the device is not realized. To avoid overloading
3
Silent when compiling with -Wextra:
4
this header including "hw/qdev-core.h", uninline the function first.
5
4
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
../hw/arm/nseries.c:1081:12: warning: missing field 'line' initializer [-Wmissing-field-initializers]
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
{ NULL }
8
Message-id: 20200803105647.22223-4-f4bug@amsat.org
7
^
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Message-id: 20221220142520.24094-4-philmd@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
include/hw/qdev-clock.h | 6 +-----
14
hw/arm/nseries.c | 10 ++++------
12
hw/core/qdev-clock.c | 5 +++++
15
1 file changed, 4 insertions(+), 6 deletions(-)
13
2 files changed, 6 insertions(+), 5 deletions(-)
14
16
15
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/qdev-clock.h
19
--- a/hw/arm/nseries.c
18
+++ b/include/hw/qdev-clock.h
20
+++ b/hw/arm/nseries.c
19
@@ -XXX,XX +XXX,XX @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
21
@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
20
* Set the source clock of input clock @name of device @dev to @source.
22
"headphone", N8X0_HEADPHONE_GPIO,
21
* @source period update will be propagated to @name clock.
23
OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED,
22
*/
24
},
23
-static inline void qdev_connect_clock_in(DeviceState *dev, const char *name,
25
- { NULL }
24
- Clock *source)
26
+ { /* end of list */ }
25
-{
27
}, n810_gpiosw_info[] = {
26
- clock_set_source(qdev_get_clock_in(dev, name), source);
28
{
27
-}
29
"gps_reset", N810_GPS_RESET_GPIO,
28
+void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source);
30
@@ -XXX,XX +XXX,XX @@ static const struct omap_gpiosw_info_s {
29
31
"slide", N810_SLIDE_GPIO,
30
/**
32
OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED,
31
* qdev_alias_clock:
33
},
32
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
34
- { NULL }
33
index XXXXXXX..XXXXXXX 100644
35
+ { /* end of list */ }
34
--- a/hw/core/qdev-clock.c
36
};
35
+++ b/hw/core/qdev-clock.c
37
36
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
38
static const struct omap_partition_info_s {
37
39
@@ -XXX,XX +XXX,XX @@ static const struct omap_partition_info_s {
38
return ncl->clock;
40
{ 0x00080000, 0x00200000, 0x0, "kernel" },
39
}
41
{ 0x00280000, 0x00200000, 0x3, "initfs" },
40
+
42
{ 0x00480000, 0x0fb80000, 0x3, "rootfs" },
41
+void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source)
43
-
42
+{
44
- { 0, 0, 0, NULL }
43
+ clock_set_source(qdev_get_clock_in(dev, name), source);
45
+ { /* end of list */ }
44
+}
46
}, n810_part_info[] = {
47
{ 0x00000000, 0x00020000, 0x3, "bootloader" },
48
{ 0x00020000, 0x00060000, 0x0, "config" },
49
{ 0x00080000, 0x00220000, 0x0, "kernel" },
50
{ 0x002a0000, 0x00400000, 0x0, "initfs" },
51
{ 0x006a0000, 0x0f960000, 0x0, "rootfs" },
52
-
53
- { 0, 0, 0, NULL }
54
+ { /* end of list */ }
55
};
56
57
static const uint8_t n8x0_bd_addr[6] = { N8X0_BD_ADDR };
45
--
58
--
46
2.20.1
59
2.25.1
47
60
48
61
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Zhuojia Shen <chaosdefinition@hotmail.com>
2
2
3
Unify add/sub helpers and add a parameter for rounding.
3
In CPUID registers exposed to userspace, some registers were missing
4
This will allow saturating non-rounding to reuse this code.
4
and some fields were not exposed. This patch aligns exposed ID
5
5
registers and their fields with what the upstream kernel currently
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
exposes.
7
[PMM: fixed accidental use of '=' rather than '+=' in do_sqrdmlah_s]
7
8
Specifically, the following new ID registers/fields are exposed to
9
userspace:
10
11
ID_AA64PFR1_EL1.BT: bits 3-0
12
ID_AA64PFR1_EL1.MTE: bits 11-8
13
ID_AA64PFR1_EL1.SME: bits 27-24
14
15
ID_AA64ZFR0_EL1.SVEver: bits 3-0
16
ID_AA64ZFR0_EL1.AES: bits 7-4
17
ID_AA64ZFR0_EL1.BitPerm: bits 19-16
18
ID_AA64ZFR0_EL1.BF16: bits 23-20
19
ID_AA64ZFR0_EL1.SHA3: bits 35-32
20
ID_AA64ZFR0_EL1.SM4: bits 43-40
21
ID_AA64ZFR0_EL1.I8MM: bits 47-44
22
ID_AA64ZFR0_EL1.F32MM: bits 55-52
23
ID_AA64ZFR0_EL1.F64MM: bits 59-56
24
25
ID_AA64SMFR0_EL1.F32F32: bit 32
26
ID_AA64SMFR0_EL1.B16F32: bit 34
27
ID_AA64SMFR0_EL1.F16F32: bit 35
28
ID_AA64SMFR0_EL1.I8I32: bits 39-36
29
ID_AA64SMFR0_EL1.F64F64: bit 48
30
ID_AA64SMFR0_EL1.I16I64: bits 55-52
31
ID_AA64SMFR0_EL1.FA64: bit 63
32
33
ID_AA64MMFR0_EL1.ECV: bits 63-60
34
35
ID_AA64MMFR1_EL1.AFP: bits 47-44
36
37
ID_AA64MMFR2_EL1.AT: bits 35-32
38
39
ID_AA64ISAR0_EL1.RNDR: bits 63-60
40
41
ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
42
ID_AA64ISAR1_EL1.BF16: bits 47-44
43
ID_AA64ISAR1_EL1.DGH: bits 51-48
44
ID_AA64ISAR1_EL1.I8MM: bits 55-52
45
46
ID_AA64ISAR2_EL1.WFxT: bits 3-0
47
ID_AA64ISAR2_EL1.RPRES: bits 7-4
48
ID_AA64ISAR2_EL1.GPA3: bits 11-8
49
ID_AA64ISAR2_EL1.APA3: bits 15-12
50
51
The code is also refactored to use symbolic names for ID register fields
52
for better readability and maintainability.
53
54
The test case in tests/tcg/aarch64/sysregs.c is also updated to match
55
the intended behavior.
56
57
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
58
Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
59
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-15-richard.henderson@linaro.org
60
[PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers
61
that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
62
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
63
---
12
target/arm/vec_helper.c | 80 +++++++++++++++--------------------------
64
target/arm/helper.c | 96 +++++++++++++++++++++++++------
13
1 file changed, 29 insertions(+), 51 deletions(-)
65
tests/tcg/aarch64/sysregs.c | 24 ++++++--
14
66
tests/tcg/aarch64/Makefile.target | 7 ++-
15
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
67
3 files changed, 103 insertions(+), 24 deletions(-)
68
69
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
70
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vec_helper.c
71
--- a/target/arm/helper.c
18
+++ b/target/arm/vec_helper.c
72
+++ b/target/arm/helper.c
73
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
74
#ifdef CONFIG_USER_ONLY
75
static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
76
{ .name = "ID_AA64PFR0_EL1",
77
- .exported_bits = 0x000f000f00ff0000,
78
- .fixed_bits = 0x0000000000000011 },
79
+ .exported_bits = R_ID_AA64PFR0_FP_MASK |
80
+ R_ID_AA64PFR0_ADVSIMD_MASK |
81
+ R_ID_AA64PFR0_SVE_MASK |
82
+ R_ID_AA64PFR0_DIT_MASK,
83
+ .fixed_bits = (0x1u << R_ID_AA64PFR0_EL0_SHIFT) |
84
+ (0x1u << R_ID_AA64PFR0_EL1_SHIFT) },
85
{ .name = "ID_AA64PFR1_EL1",
86
- .exported_bits = 0x00000000000000f0 },
87
+ .exported_bits = R_ID_AA64PFR1_BT_MASK |
88
+ R_ID_AA64PFR1_SSBS_MASK |
89
+ R_ID_AA64PFR1_MTE_MASK |
90
+ R_ID_AA64PFR1_SME_MASK },
91
{ .name = "ID_AA64PFR*_EL1_RESERVED",
92
- .is_glob = true },
93
- { .name = "ID_AA64ZFR0_EL1" },
94
+ .is_glob = true },
95
+ { .name = "ID_AA64ZFR0_EL1",
96
+ .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
97
+ R_ID_AA64ZFR0_AES_MASK |
98
+ R_ID_AA64ZFR0_BITPERM_MASK |
99
+ R_ID_AA64ZFR0_BFLOAT16_MASK |
100
+ R_ID_AA64ZFR0_SHA3_MASK |
101
+ R_ID_AA64ZFR0_SM4_MASK |
102
+ R_ID_AA64ZFR0_I8MM_MASK |
103
+ R_ID_AA64ZFR0_F32MM_MASK |
104
+ R_ID_AA64ZFR0_F64MM_MASK },
105
+ { .name = "ID_AA64SMFR0_EL1",
106
+ .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
107
+ R_ID_AA64SMFR0_B16F32_MASK |
108
+ R_ID_AA64SMFR0_F16F32_MASK |
109
+ R_ID_AA64SMFR0_I8I32_MASK |
110
+ R_ID_AA64SMFR0_F64F64_MASK |
111
+ R_ID_AA64SMFR0_I16I64_MASK |
112
+ R_ID_AA64SMFR0_FA64_MASK },
113
{ .name = "ID_AA64MMFR0_EL1",
114
- .fixed_bits = 0x00000000ff000000 },
115
- { .name = "ID_AA64MMFR1_EL1" },
116
+ .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
117
+ .fixed_bits = (0xfu << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
118
+ (0xfu << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
119
+ { .name = "ID_AA64MMFR1_EL1",
120
+ .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
121
+ { .name = "ID_AA64MMFR2_EL1",
122
+ .exported_bits = R_ID_AA64MMFR2_AT_MASK },
123
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
124
- .is_glob = true },
125
+ .is_glob = true },
126
{ .name = "ID_AA64DFR0_EL1",
127
- .fixed_bits = 0x0000000000000006 },
128
- { .name = "ID_AA64DFR1_EL1" },
129
+ .fixed_bits = (0x6u << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
130
+ { .name = "ID_AA64DFR1_EL1" },
131
{ .name = "ID_AA64DFR*_EL1_RESERVED",
132
- .is_glob = true },
133
+ .is_glob = true },
134
{ .name = "ID_AA64AFR*",
135
- .is_glob = true },
136
+ .is_glob = true },
137
{ .name = "ID_AA64ISAR0_EL1",
138
- .exported_bits = 0x00fffffff0fffff0 },
139
+ .exported_bits = R_ID_AA64ISAR0_AES_MASK |
140
+ R_ID_AA64ISAR0_SHA1_MASK |
141
+ R_ID_AA64ISAR0_SHA2_MASK |
142
+ R_ID_AA64ISAR0_CRC32_MASK |
143
+ R_ID_AA64ISAR0_ATOMIC_MASK |
144
+ R_ID_AA64ISAR0_RDM_MASK |
145
+ R_ID_AA64ISAR0_SHA3_MASK |
146
+ R_ID_AA64ISAR0_SM3_MASK |
147
+ R_ID_AA64ISAR0_SM4_MASK |
148
+ R_ID_AA64ISAR0_DP_MASK |
149
+ R_ID_AA64ISAR0_FHM_MASK |
150
+ R_ID_AA64ISAR0_TS_MASK |
151
+ R_ID_AA64ISAR0_RNDR_MASK },
152
{ .name = "ID_AA64ISAR1_EL1",
153
- .exported_bits = 0x000000f0ffffffff },
154
+ .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
155
+ R_ID_AA64ISAR1_APA_MASK |
156
+ R_ID_AA64ISAR1_API_MASK |
157
+ R_ID_AA64ISAR1_JSCVT_MASK |
158
+ R_ID_AA64ISAR1_FCMA_MASK |
159
+ R_ID_AA64ISAR1_LRCPC_MASK |
160
+ R_ID_AA64ISAR1_GPA_MASK |
161
+ R_ID_AA64ISAR1_GPI_MASK |
162
+ R_ID_AA64ISAR1_FRINTTS_MASK |
163
+ R_ID_AA64ISAR1_SB_MASK |
164
+ R_ID_AA64ISAR1_BF16_MASK |
165
+ R_ID_AA64ISAR1_DGH_MASK |
166
+ R_ID_AA64ISAR1_I8MM_MASK },
167
+ { .name = "ID_AA64ISAR2_EL1",
168
+ .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
169
+ R_ID_AA64ISAR2_RPRES_MASK |
170
+ R_ID_AA64ISAR2_GPA3_MASK |
171
+ R_ID_AA64ISAR2_APA3_MASK },
172
{ .name = "ID_AA64ISAR*_EL1_RESERVED",
173
- .is_glob = true },
174
+ .is_glob = true },
175
};
176
modify_arm_cp_regs(v8_idregs, v8_user_idregs);
177
#endif
178
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
179
#ifdef CONFIG_USER_ONLY
180
static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
181
{ .name = "MIDR_EL1",
182
- .exported_bits = 0x00000000ffffffff },
183
- { .name = "REVIDR_EL1" },
184
+ .exported_bits = R_MIDR_EL1_REVISION_MASK |
185
+ R_MIDR_EL1_PARTNUM_MASK |
186
+ R_MIDR_EL1_ARCHITECTURE_MASK |
187
+ R_MIDR_EL1_VARIANT_MASK |
188
+ R_MIDR_EL1_IMPLEMENTER_MASK },
189
+ { .name = "REVIDR_EL1" },
190
};
191
modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
192
#endif
193
diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c
194
index XXXXXXX..XXXXXXX 100644
195
--- a/tests/tcg/aarch64/sysregs.c
196
+++ b/tests/tcg/aarch64/sysregs.c
19
@@ -XXX,XX +XXX,XX @@
197
@@ -XXX,XX +XXX,XX @@
198
#define HWCAP_CPUID (1 << 11)
20
#endif
199
#endif
21
200
22
/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
201
+/*
23
-static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
202
+ * Older assemblers don't recognize newer system register names,
24
- int16_t src3, uint32_t *sat)
203
+ * but we can still access them by the Sn_n_Cn_Cn_n syntax.
25
+static int16_t do_sqrdmlah_h(int16_t src1, int16_t src2, int16_t src3,
204
+ */
26
+ bool neg, bool round, uint32_t *sat)
205
+#define SYS_ID_AA64ISAR2_EL1 S3_0_C0_C6_2
27
{
206
+#define SYS_ID_AA64MMFR2_EL1 S3_0_C0_C7_2
28
- /* Simplify:
207
+
29
+ /*
208
int failed_bit_count;
30
+ * Simplify:
209
31
* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
210
/* Read and print system register `id' value */
32
* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
211
@@ -XXX,XX +XXX,XX @@ int main(void)
212
* minimum valid fields - for the purposes of this check allowed
213
* to have non-zero values.
33
*/
214
*/
34
int32_t ret = (int32_t)src1 * src2;
215
- get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0));
35
- ret = ((int32_t)src3 << 15) + ret + (1 << 14);
216
- get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff));
36
+ if (neg) {
217
+ get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0));
37
+ ret = -ret;
218
+ get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff));
38
+ }
219
+ get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff));
39
+ ret += ((int32_t)src3 << 15) + (round << 14);
220
/* TGran4 & TGran64 as pegged to -1 */
40
ret >>= 15;
221
- get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000));
41
+
222
- get_cpu_reg_check_zero(id_aa64mmfr1_el1);
42
if (ret != (int16_t)ret) {
223
+ get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000));
43
*sat = 1;
224
+ get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000));
44
- ret = (ret < 0 ? -0x8000 : 0x7fff);
225
+ get_cpu_reg_check_mask(SYS_ID_AA64MMFR2_EL1, _m(0000,000f,0000,0000));
45
+ ret = (ret < 0 ? INT16_MIN : INT16_MAX);
226
/* EL1/EL0 reported as AA64 only */
46
}
227
get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011));
47
return ret;
228
- get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0));
48
}
229
+ get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0f00,0fff));
49
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
230
/* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */
50
uint32_t src2, uint32_t src3)
231
get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006));
51
{
232
get_cpu_reg_check_zero(id_aa64dfr1_el1);
52
uint32_t *sat = &env->vfp.qc[0];
233
- get_cpu_reg_check_zero(id_aa64zfr0_el1);
53
- uint16_t e1 = inl_qrdmlah_s16(src1, src2, src3, sat);
234
+ get_cpu_reg_check_mask(id_aa64zfr0_el1, _m(0ff0,ff0f,00ff,00ff));
54
- uint16_t e2 = inl_qrdmlah_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
235
+#ifdef HAS_ARMV9_SME
55
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, false, true, sat);
236
+ get_cpu_reg_check_mask(id_aa64smfr0_el1, _m(80f1,00fd,0000,0000));
56
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
237
+#endif
57
+ false, true, sat);
238
58
return deposit32(e1, 16, 16, e2);
239
get_cpu_reg_check_zero(id_aa64afr0_el1);
59
}
240
get_cpu_reg_check_zero(id_aa64afr1_el1);
60
241
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
61
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
242
index XXXXXXX..XXXXXXX 100644
62
uintptr_t i;
243
--- a/tests/tcg/aarch64/Makefile.target
63
244
+++ b/tests/tcg/aarch64/Makefile.target
64
for (i = 0; i < opr_sz / 2; ++i) {
245
@@ -XXX,XX +XXX,XX @@ config-cc.mak: Makefile
65
- d[i] = inl_qrdmlah_s16(n[i], m[i], d[i], vq);
246
     $(call cc-option,-march=armv8.1-a+sve2, CROSS_CC_HAS_SVE2); \
66
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], false, true, vq);
247
     $(call cc-option,-march=armv8.3-a, CROSS_CC_HAS_ARMV8_3); \
67
}
248
     $(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
68
clear_tail(d, opr_sz, simd_maxsz(desc));
249
-     $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE)) 3> config-cc.mak
69
}
250
+     $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
70
251
+     $(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
71
-/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
252
-include config-cc.mak
72
-static int16_t inl_qrdmlsh_s16(int16_t src1, int16_t src2,
253
73
- int16_t src3, uint32_t *sat)
254
# Pauth Tests
74
-{
255
@@ -XXX,XX +XXX,XX @@ endif
75
- /* Similarly, using subtraction:
256
ifneq ($(CROSS_CC_HAS_SVE),)
76
- * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
257
# System Registers Tests
77
- * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
258
AARCH64_TESTS += sysregs
78
- */
259
+ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
79
- int32_t ret = (int32_t)src1 * src2;
260
+sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
80
- ret = ((int32_t)src3 << 15) - ret + (1 << 14);
261
+else
81
- ret >>= 15;
262
sysregs: CFLAGS+=-march=armv8.1-a+sve
82
- if (ret != (int16_t)ret) {
263
+endif
83
- *sat = 1;
264
84
- ret = (ret < 0 ? -0x8000 : 0x7fff);
265
# SVE ioctl test
85
- }
266
AARCH64_TESTS += sve-ioctls
86
- return ret;
87
-}
88
-
89
uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
90
uint32_t src2, uint32_t src3)
91
{
92
uint32_t *sat = &env->vfp.qc[0];
93
- uint16_t e1 = inl_qrdmlsh_s16(src1, src2, src3, sat);
94
- uint16_t e2 = inl_qrdmlsh_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
95
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, true, true, sat);
96
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
97
+ true, true, sat);
98
return deposit32(e1, 16, 16, e2);
99
}
100
101
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
102
uintptr_t i;
103
104
for (i = 0; i < opr_sz / 2; ++i) {
105
- d[i] = inl_qrdmlsh_s16(n[i], m[i], d[i], vq);
106
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], true, true, vq);
107
}
108
clear_tail(d, opr_sz, simd_maxsz(desc));
109
}
110
111
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
112
-static int32_t inl_qrdmlah_s32(int32_t src1, int32_t src2,
113
- int32_t src3, uint32_t *sat)
114
+static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
115
+ bool neg, bool round, uint32_t *sat)
116
{
117
/* Simplify similarly to int_qrdmlah_s16 above. */
118
int64_t ret = (int64_t)src1 * src2;
119
- ret = ((int64_t)src3 << 31) + ret + (1 << 30);
120
+ if (neg) {
121
+ ret = -ret;
122
+ }
123
+ ret += ((int64_t)src3 << 31) + (round << 30);
124
ret >>= 31;
125
+
126
if (ret != (int32_t)ret) {
127
*sat = 1;
128
ret = (ret < 0 ? INT32_MIN : INT32_MAX);
129
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
130
int32_t src2, int32_t src3)
131
{
132
uint32_t *sat = &env->vfp.qc[0];
133
- return inl_qrdmlah_s32(src1, src2, src3, sat);
134
+ return do_sqrdmlah_s(src1, src2, src3, false, true, sat);
135
}
136
137
void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
138
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
139
uintptr_t i;
140
141
for (i = 0; i < opr_sz / 4; ++i) {
142
- d[i] = inl_qrdmlah_s32(n[i], m[i], d[i], vq);
143
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], false, true, vq);
144
}
145
clear_tail(d, opr_sz, simd_maxsz(desc));
146
}
147
148
-/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
149
-static int32_t inl_qrdmlsh_s32(int32_t src1, int32_t src2,
150
- int32_t src3, uint32_t *sat)
151
-{
152
- /* Simplify similarly to int_qrdmlsh_s16 above. */
153
- int64_t ret = (int64_t)src1 * src2;
154
- ret = ((int64_t)src3 << 31) - ret + (1 << 30);
155
- ret >>= 31;
156
- if (ret != (int32_t)ret) {
157
- *sat = 1;
158
- ret = (ret < 0 ? INT32_MIN : INT32_MAX);
159
- }
160
- return ret;
161
-}
162
-
163
uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
164
int32_t src2, int32_t src3)
165
{
166
uint32_t *sat = &env->vfp.qc[0];
167
- return inl_qrdmlsh_s32(src1, src2, src3, sat);
168
+ return do_sqrdmlah_s(src1, src2, src3, true, true, sat);
169
}
170
171
void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
172
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
173
uintptr_t i;
174
175
for (i = 0; i < opr_sz / 4; ++i) {
176
- d[i] = inl_qrdmlsh_s32(n[i], m[i], d[i], vq);
177
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], true, true, vq);
178
}
179
clear_tail(d, opr_sz, simd_maxsz(desc));
180
}
181
--
267
--
182
2.20.1
268
2.25.1
183
184
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
clock_init*() inlined funtions are simple wrappers around
3
This function is not used anywhere outside this file,
4
clock_set*() and are not used. Remove them in favor of clock_set*().
4
so we can make the function "static void".
5
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200806123858.30058-2-f4bug@amsat.org
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Message-id: 20221216214924.4711-2-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
include/hw/clock.h | 13 -------------
12
include/hw/arm/smmu-common.h | 3 ---
12
1 file changed, 13 deletions(-)
13
hw/arm/smmu-common.c | 2 +-
14
2 files changed, 1 insertion(+), 4 deletions(-)
13
15
14
diff --git a/include/hw/clock.h b/include/hw/clock.h
16
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/clock.h
18
--- a/include/hw/arm/smmu-common.h
17
+++ b/include/hw/clock.h
19
+++ b/include/hw/arm/smmu-common.h
18
@@ -XXX,XX +XXX,XX @@ static inline bool clock_is_enabled(const Clock *clk)
20
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
19
return clock_get(clk) != 0;
21
/* Unmap the range of all the notifiers registered to any IOMMU mr */
22
void smmu_inv_notifiers_all(SMMUState *s);
23
24
-/* Unmap the range of all the notifiers registered to @mr */
25
-void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr);
26
-
27
#endif /* HW_ARM_SMMU_COMMON_H */
28
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/smmu-common.c
31
+++ b/hw/arm/smmu-common.c
32
@@ -XXX,XX +XXX,XX @@ static void smmu_unmap_notifier_range(IOMMUNotifier *n)
20
}
33
}
21
34
22
-static inline void clock_init(Clock *clk, uint64_t value)
35
/* Unmap all notifiers attached to @mr */
23
-{
36
-inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
24
- clock_set(clk, value);
37
+static void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr)
25
-}
38
{
26
-static inline void clock_init_hz(Clock *clk, uint64_t value)
39
IOMMUNotifier *n;
27
-{
40
28
- clock_set_hz(clk, value);
29
-}
30
-static inline void clock_init_ns(Clock *clk, uint64_t value)
31
-{
32
- clock_set_ns(clk, value);
33
-}
34
-
35
#endif /* QEMU_HW_CLOCK_H */
36
--
41
--
37
2.20.1
42
2.25.1
38
43
39
44
diff view generated by jsdifflib
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Let clock_set() return a boolean value whether the clock
4
has been updated or not.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200806123858.30058-3-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/clock.h | 12 +++++++-----
12
hw/core/clock.c | 7 ++++++-
13
2 files changed, 13 insertions(+), 6 deletions(-)
14
15
diff --git a/include/hw/clock.h b/include/hw/clock.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/clock.h
18
+++ b/include/hw/clock.h
19
@@ -XXX,XX +XXX,XX @@ void clock_set_source(Clock *clk, Clock *src);
20
* @value: the clock's value, 0 means unclocked
21
*
22
* Set the local cached period value of @clk to @value.
23
+ *
24
+ * @return: true if the clock is changed.
25
*/
26
-void clock_set(Clock *clk, uint64_t value);
27
+bool clock_set(Clock *clk, uint64_t value);
28
29
-static inline void clock_set_hz(Clock *clk, unsigned hz)
30
+static inline bool clock_set_hz(Clock *clk, unsigned hz)
31
{
32
- clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
33
+ return clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
34
}
35
36
-static inline void clock_set_ns(Clock *clk, unsigned ns)
37
+static inline bool clock_set_ns(Clock *clk, unsigned ns)
38
{
39
- clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
40
+ return clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
41
}
42
43
/**
44
diff --git a/hw/core/clock.c b/hw/core/clock.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/core/clock.c
47
+++ b/hw/core/clock.c
48
@@ -XXX,XX +XXX,XX @@ void clock_clear_callback(Clock *clk)
49
clock_set_callback(clk, NULL, NULL);
50
}
51
52
-void clock_set(Clock *clk, uint64_t period)
53
+bool clock_set(Clock *clk, uint64_t period)
54
{
55
+ if (clk->period == period) {
56
+ return false;
57
+ }
58
trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
59
CLOCK_PERIOD_TO_NS(period));
60
clk->period = period;
61
+
62
+ return true;
63
}
64
65
static void clock_propagate_period(Clock *clk, bool call_callbacks)
66
--
67
2.20.1
68
69
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Model the new function on gen_gvec_fn2 in translate-a64.c, but
3
When using Clang ("Apple clang version 14.0.0 (clang-1400.0.29.202)")
4
indicating which kind of register and in which order. Since there
4
and building with -Wall we get:
5
is only one user of do_vector2_z, fold it into do_mov_z.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
hw/arm/smmu-common.c:173:33: warning: static function 'smmu_hash_remove_by_asid_iova' is used in an inline function with external linkage [-Wstatic-in-inline]
7
hw/arm/smmu-common.h:170:1: note: use 'static' to give inline function 'smmu_iotlb_inv_iova' internal linkage
8
void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
9
^
10
static
11
12
None of our code base require / use inlined functions with external
13
linkage. Some places use internal inlining in the hot path. These
14
two functions are certainly not in any hot path and don't justify
15
any inlining, so these are likely oversights rather than intentional.
16
17
Reported-by: Stefan Weil <sw@weilnetz.de>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-3-richard.henderson@linaro.org
19
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Reviewed-by: Eric Auger <eric.auger@redhat.com>
22
Message-id: 20221216214924.4711-3-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
24
---
12
target/arm/translate-sve.c | 19 ++++++++++---------
25
hw/arm/smmu-common.c | 13 ++++++-------
13
1 file changed, 10 insertions(+), 9 deletions(-)
26
1 file changed, 6 insertions(+), 7 deletions(-)
14
27
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
28
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
16
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
30
--- a/hw/arm/smmu-common.c
18
+++ b/target/arm/translate-sve.c
31
+++ b/hw/arm/smmu-common.c
19
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
32
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
33
g_hash_table_insert(bs->iotlb, key, new);
20
}
34
}
21
35
22
/* Invoke a vector expander on two Zregs. */
36
-inline void smmu_iotlb_inv_all(SMMUState *s)
23
-static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
37
+void smmu_iotlb_inv_all(SMMUState *s)
24
- int esz, int rd, int rn)
25
+
26
+static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
27
+ int esz, int rd, int rn)
28
{
38
{
29
- if (sve_access_check(s)) {
39
trace_smmu_iotlb_inv_all();
30
- unsigned vsz = vec_full_reg_size(s);
40
g_hash_table_remove_all(s->iotlb);
31
- gvec_fn(esz, vec_full_reg_offset(s, rd),
41
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
32
- vec_full_reg_offset(s, rn), vsz, vsz);
42
((entry->iova & ~info->mask) == info->iova);
33
- }
34
- return true;
35
+ unsigned vsz = vec_full_reg_size(s);
36
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
37
+ vec_full_reg_offset(s, rn), vsz, vsz);
38
}
43
}
39
44
40
/* Invoke a vector expander on three Zregs. */
45
-inline void
41
@@ -XXX,XX +XXX,XX @@ static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
46
-smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
42
/* Invoke a vector move on two Zregs. */
47
- uint8_t tg, uint64_t num_pages, uint8_t ttl)
43
static bool do_mov_z(DisasContext *s, int rd, int rn)
48
+void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
49
+ uint8_t tg, uint64_t num_pages, uint8_t ttl)
44
{
50
{
45
- return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
51
/* if tg is not set we use 4KB range invalidation */
46
+ if (sve_access_check(s)) {
52
uint8_t granule = tg ? tg * 2 + 10 : 12;
47
+ gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
53
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
48
+ }
54
&info);
49
+ return true;
50
}
55
}
51
56
52
/* Initialize a Zreg with replications of a 64-bit immediate. */
57
-inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
58
+void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
59
{
60
trace_smmu_iotlb_inv_asid(asid);
61
g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
62
@@ -XXX,XX +XXX,XX @@ error:
63
*
64
* return 0 on success
65
*/
66
-inline int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
67
- SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
68
+int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm,
69
+ SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info)
70
{
71
if (!cfg->aa64) {
72
/*
53
--
73
--
54
2.20.1
74
2.25.1
55
75
56
76
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
So far the GPT timers were unable to raise IRQs to the processor.
4
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-20-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
---
8
target/arm/helper.h | 14 ++++++++++++++
9
include/hw/arm/fsl-imx7.h | 5 +++++
9
target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++
10
hw/arm/fsl-imx7.c | 10 ++++++++++
10
target/arm/vec_helper.c | 25 +++++++++++++++++++++++++
11
2 files changed, 15 insertions(+)
11
3 files changed, 73 insertions(+)
12
12
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
13
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.h
15
--- a/include/hw/arm/fsl-imx7.h
16
+++ b/target/arm/helper.h
16
+++ b/include/hw/arm/fsl-imx7.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
17
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
18
DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
18
FSL_IMX7_USB2_IRQ = 42,
19
DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
19
FSL_IMX7_USB3_IRQ = 40,
20
20
21
+DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG,
21
+ FSL_IMX7_GPT1_IRQ = 55,
22
+ void, ptr, ptr, ptr, ptr, i32)
22
+ FSL_IMX7_GPT2_IRQ = 54,
23
+DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG,
23
+ FSL_IMX7_GPT3_IRQ = 53,
24
+ void, ptr, ptr, ptr, ptr, i32)
24
+ FSL_IMX7_GPT4_IRQ = 52,
25
+DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG,
26
+ void, ptr, ptr, ptr, ptr, i32)
27
+
25
+
28
+DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG,
26
FSL_IMX7_WDOG1_IRQ = 78,
29
+ void, ptr, ptr, ptr, ptr, i32)
27
FSL_IMX7_WDOG2_IRQ = 79,
30
+DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
28
FSL_IMX7_WDOG3_IRQ = 10,
31
+ void, ptr, ptr, ptr, ptr, i32)
29
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
32
+DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
30
index XXXXXXX..XXXXXXX 100644
33
+ void, ptr, ptr, ptr, ptr, i32)
31
--- a/hw/arm/fsl-imx7.c
32
+++ b/hw/arm/fsl-imx7.c
33
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
34
FSL_IMX7_GPT4_ADDR,
35
};
36
37
+ static const int FSL_IMX7_GPTn_IRQ[FSL_IMX7_NUM_GPTS] = {
38
+ FSL_IMX7_GPT1_IRQ,
39
+ FSL_IMX7_GPT2_IRQ,
40
+ FSL_IMX7_GPT3_IRQ,
41
+ FSL_IMX7_GPT4_IRQ,
42
+ };
34
+
43
+
35
#ifdef TARGET_AARCH64
44
s->gpt[i].ccm = IMX_CCM(&s->ccm);
36
#include "helper-a64.h"
45
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
37
#include "helper-sve.h"
46
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
38
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
47
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
39
index XXXXXXX..XXXXXXX 100644
48
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
40
--- a/target/arm/translate-a64.c
49
+ FSL_IMX7_GPTn_IRQ[i]));
41
+++ b/target/arm/translate-a64.c
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
43
return;
44
}
45
break;
46
+
47
+ case 0x10: /* MLA */
48
+ if (!is_long && !is_scalar) {
49
+ static gen_helper_gvec_4 * const fns[3] = {
50
+ gen_helper_gvec_mla_idx_h,
51
+ gen_helper_gvec_mla_idx_s,
52
+ gen_helper_gvec_mla_idx_d,
53
+ };
54
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
55
+ vec_full_reg_offset(s, rn),
56
+ vec_full_reg_offset(s, rm),
57
+ vec_full_reg_offset(s, rd),
58
+ is_q ? 16 : 8, vec_full_reg_size(s),
59
+ index, fns[size - 1]);
60
+ return;
61
+ }
62
+ break;
63
+
64
+ case 0x14: /* MLS */
65
+ if (!is_long && !is_scalar) {
66
+ static gen_helper_gvec_4 * const fns[3] = {
67
+ gen_helper_gvec_mls_idx_h,
68
+ gen_helper_gvec_mls_idx_s,
69
+ gen_helper_gvec_mls_idx_d,
70
+ };
71
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
72
+ vec_full_reg_offset(s, rn),
73
+ vec_full_reg_offset(s, rm),
74
+ vec_full_reg_offset(s, rd),
75
+ is_q ? 16 : 8, vec_full_reg_size(s),
76
+ index, fns[size - 1]);
77
+ return;
78
+ }
79
+ break;
80
}
50
}
81
51
82
if (size == 3) {
52
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
83
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/target/arm/vec_helper.c
86
+++ b/target/arm/vec_helper.c
87
@@ -XXX,XX +XXX,XX @@ DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
88
89
#undef DO_MUL_IDX
90
91
+#define DO_MLA_IDX(NAME, TYPE, OP, H) \
92
+void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
93
+{ \
94
+ intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
95
+ intptr_t idx = simd_data(desc); \
96
+ TYPE *d = vd, *n = vn, *m = vm, *a = va; \
97
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
98
+ TYPE mm = m[H(i + idx)]; \
99
+ for (j = 0; j < segment; j++) { \
100
+ d[i + j] = a[i + j] OP n[i + j] * mm; \
101
+ } \
102
+ } \
103
+ clear_tail(d, oprsz, simd_maxsz(desc)); \
104
+}
105
+
106
+DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2)
107
+DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4)
108
+DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, )
109
+
110
+DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2)
111
+DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4)
112
+DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, )
113
+
114
+#undef DO_MLA_IDX
115
+
116
#define DO_FMUL_IDX(NAME, TYPE, H) \
117
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
118
{ \
119
--
53
--
120
2.20.1
54
2.25.1
121
122
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
Avoid propagating the clock change when the clock does not change.
3
CCM derived clocks will have to be added later.
4
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200806123858.30058-4-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
8
---
10
include/hw/clock.h | 5 +++--
9
hw/misc/imx7_ccm.c | 49 +++++++++++++++++++++++++++++++++++++---------
11
1 file changed, 3 insertions(+), 2 deletions(-)
10
1 file changed, 40 insertions(+), 9 deletions(-)
12
11
13
diff --git a/include/hw/clock.h b/include/hw/clock.h
12
diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/clock.h
14
--- a/hw/misc/imx7_ccm.c
16
+++ b/include/hw/clock.h
15
+++ b/hw/misc/imx7_ccm.c
17
@@ -XXX,XX +XXX,XX @@ void clock_propagate(Clock *clk);
16
@@ -XXX,XX +XXX,XX @@
18
*/
17
#include "hw/misc/imx7_ccm.h"
19
static inline void clock_update(Clock *clk, uint64_t value)
18
#include "migration/vmstate.h"
19
20
+#include "trace.h"
21
+
22
+#define CKIH_FREQ 24000000 /* 24MHz crystal input */
23
+
24
static void imx7_analog_reset(DeviceState *dev)
20
{
25
{
21
- clock_set(clk, value);
26
IMX7AnalogState *s = IMX7_ANALOG(dev);
22
- clock_propagate(clk);
27
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx7_ccm = {
23
+ if (clock_set(clk, value)) {
28
static uint32_t imx7_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
24
+ clock_propagate(clk);
29
{
30
/*
31
- * This function is "consumed" by GPT emulation code, however on
32
- * i.MX7 each GPT block can have their own clock root. This means
33
- * that this functions needs somehow to know requester's identity
34
- * and the way to pass it: be it via additional IMXClk constants
35
- * or by adding another argument to this method needs to be
36
- * figured out
37
+ * This function is "consumed" by GPT emulation code. Some clocks
38
+ * have fixed frequencies and we can provide requested frequency
39
+ * easily. However for CCM provided clocks (like IPG) each GPT
40
+ * timer can have its own clock root.
41
+ * This means we need additionnal information when calling this
42
+ * function to know the requester's identity.
43
*/
44
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Not implemented\n",
45
- TYPE_IMX7_CCM, __func__);
46
- return 0;
47
+ uint32_t freq = 0;
48
+
49
+ switch (clock) {
50
+ case CLK_NONE:
51
+ break;
52
+ case CLK_32k:
53
+ freq = CKIL_FREQ;
54
+ break;
55
+ case CLK_HIGH:
56
+ freq = CKIH_FREQ;
57
+ break;
58
+ case CLK_IPG:
59
+ case CLK_IPG_HIGH:
60
+ /*
61
+ * For now we don't have a way to figure out the device this
62
+ * function is called for. Until then the IPG derived clocks
63
+ * are left unimplemented.
64
+ */
65
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Clock %d Not implemented\n",
66
+ TYPE_IMX7_CCM, __func__, clock);
67
+ break;
68
+ default:
69
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
70
+ TYPE_IMX7_CCM, __func__, clock);
71
+ break;
25
+ }
72
+ }
73
+
74
+ trace_ccm_clock_freq(clock, freq);
75
+
76
+ return freq;
26
}
77
}
27
78
28
static inline void clock_update_hz(Clock *clk, unsigned hz)
79
static void imx7_ccm_class_init(ObjectClass *klass, void *data)
29
--
80
--
30
2.20.1
81
2.25.1
31
32
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
Allow the device to execute the DMA transfers in a different
3
The i.MX6UL doesn't support CLK_HIGH ou CLK_HIGH_DIV clock source.
4
AddressSpace.
5
4
6
The A10 and H3 SoC keep using the system_memory address space,
5
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
but via the proper dma_memory_access() API.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Message-id: 20200814110057.307-1-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
8
---
15
include/hw/sd/allwinner-sdhost.h | 6 ++++++
9
include/hw/timer/imx_gpt.h | 1 +
16
hw/arm/allwinner-a10.c | 2 ++
10
hw/arm/fsl-imx6ul.c | 2 +-
17
hw/arm/allwinner-h3.c | 2 ++
11
hw/misc/imx6ul_ccm.c | 6 ------
18
hw/sd/allwinner-sdhost.c | 37 ++++++++++++++++++++++++++------
12
hw/timer/imx_gpt.c | 25 +++++++++++++++++++++++++
19
4 files changed, 41 insertions(+), 6 deletions(-)
13
4 files changed, 27 insertions(+), 7 deletions(-)
20
14
21
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
15
diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
22
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/sd/allwinner-sdhost.h
17
--- a/include/hw/timer/imx_gpt.h
24
+++ b/include/hw/sd/allwinner-sdhost.h
18
+++ b/include/hw/timer/imx_gpt.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AwSdHostState {
19
@@ -XXX,XX +XXX,XX @@
26
/** Interrupt output signal to notify CPU */
20
#define TYPE_IMX25_GPT "imx25.gpt"
27
qemu_irq irq;
21
#define TYPE_IMX31_GPT "imx31.gpt"
28
22
#define TYPE_IMX6_GPT "imx6.gpt"
29
+ /** Memory region where DMA transfers are done */
23
+#define TYPE_IMX6UL_GPT "imx6ul.gpt"
30
+ MemoryRegion *dma_mr;
24
#define TYPE_IMX7_GPT "imx7.gpt"
31
+
25
32
+ /** Address space used internally for DMA transfers */
26
#define TYPE_IMX_GPT TYPE_IMX25_GPT
33
+ AddressSpace dma_as;
27
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
34
+
35
/** Number of bytes left in current DMA transfer */
36
uint32_t transfer_cnt;
37
38
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
39
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/allwinner-a10.c
29
--- a/hw/arm/fsl-imx6ul.c
41
+++ b/hw/arm/allwinner-a10.c
30
+++ b/hw/arm/fsl-imx6ul.c
42
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
31
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
32
*/
33
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
34
snprintf(name, NAME_SIZE, "gpt%d", i);
35
- object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX7_GPT);
36
+ object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT);
43
}
37
}
44
38
45
/* SD/MMC */
39
/*
46
+ object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
40
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
47
+ OBJECT(get_system_memory()), &error_fatal);
48
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
51
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
52
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/allwinner-h3.c
42
--- a/hw/misc/imx6ul_ccm.c
54
+++ b/hw/arm/allwinner-h3.c
43
+++ b/hw/misc/imx6ul_ccm.c
55
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
44
@@ -XXX,XX +XXX,XX @@ static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
56
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
45
case CLK_32k:
57
46
freq = CKIL_FREQ;
58
/* SD/MMC */
47
break;
59
+ object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
48
- case CLK_HIGH:
60
+ OBJECT(get_system_memory()), &error_fatal);
49
- freq = CKIH_FREQ;
61
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
50
- break;
62
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
51
- case CLK_HIGH_DIV:
63
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
52
- freq = CKIH_FREQ / 8;
64
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
53
- break;
54
default:
55
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
56
TYPE_IMX6UL_CCM, __func__, clock);
57
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
65
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
66
--- a/hw/sd/allwinner-sdhost.c
59
--- a/hw/timer/imx_gpt.c
67
+++ b/hw/sd/allwinner-sdhost.c
60
+++ b/hw/timer/imx_gpt.c
68
@@ -XXX,XX +XXX,XX @@
61
@@ -XXX,XX +XXX,XX @@ static const IMXClk imx6_gpt_clocks[] = {
69
#include "qemu/log.h"
62
CLK_HIGH, /* 111 reference clock */
70
#include "qemu/module.h"
71
#include "qemu/units.h"
72
+#include "qapi/error.h"
73
#include "sysemu/blockdev.h"
74
+#include "sysemu/dma.h"
75
+#include "hw/qdev-properties.h"
76
#include "hw/irq.h"
77
#include "hw/sd/allwinner-sdhost.h"
78
#include "migration/vmstate.h"
79
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
80
uint8_t buf[1024];
81
82
/* Read descriptor */
83
- cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
84
+ dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
85
if (desc->size == 0) {
86
desc->size = klass->max_desc_size;
87
} else if (desc->size > klass->max_desc_size) {
88
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
89
90
/* Write to SD bus */
91
if (is_write) {
92
- cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
93
- buf, buf_bytes);
94
+ dma_memory_read(&s->dma_as,
95
+ (desc->addr & DESC_SIZE_MASK) + num_done,
96
+ buf, buf_bytes);
97
sdbus_write_data(&s->sdbus, buf, buf_bytes);
98
99
/* Read from SD bus */
100
} else {
101
sdbus_read_data(&s->sdbus, buf, buf_bytes);
102
- cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
103
- buf, buf_bytes);
104
+ dma_memory_write(&s->dma_as,
105
+ (desc->addr & DESC_SIZE_MASK) + num_done,
106
+ buf, buf_bytes);
107
}
108
num_done += buf_bytes;
109
}
110
111
/* Clear hold flag and flush descriptor */
112
desc->status &= ~DESC_STATUS_HOLD;
113
- cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
114
+ dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc));
115
116
return num_done;
117
}
118
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_allwinner_sdhost = {
119
}
120
};
63
};
121
64
122
+static Property allwinner_sdhost_properties[] = {
65
+static const IMXClk imx6ul_gpt_clocks[] = {
123
+ DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr,
66
+ CLK_NONE, /* 000 No clock source */
124
+ TYPE_MEMORY_REGION, MemoryRegion *),
67
+ CLK_IPG, /* 001 ipg_clk, 532MHz*/
125
+ DEFINE_PROP_END_OF_LIST(),
68
+ CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */
69
+ CLK_EXT, /* 011 External clock */
70
+ CLK_32k, /* 100 ipg_clk_32k */
71
+ CLK_NONE, /* 101 not defined */
72
+ CLK_NONE, /* 110 not defined */
73
+ CLK_NONE, /* 111 not defined */
126
+};
74
+};
127
+
75
+
128
static void allwinner_sdhost_init(Object *obj)
76
static const IMXClk imx7_gpt_clocks[] = {
129
{
77
CLK_NONE, /* 000 No clock source */
130
AwSdHostState *s = AW_SDHOST(obj);
78
CLK_IPG, /* 001 ipg_clk, 532MHz*/
131
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj)
79
@@ -XXX,XX +XXX,XX @@ static void imx6_gpt_init(Object *obj)
132
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
80
s->clocks = imx6_gpt_clocks;
133
}
81
}
134
82
135
+static void allwinner_sdhost_realize(DeviceState *dev, Error **errp)
83
+static void imx6ul_gpt_init(Object *obj)
136
+{
84
+{
137
+ AwSdHostState *s = AW_SDHOST(dev);
85
+ IMXGPTState *s = IMX_GPT(obj);
138
+
86
+
139
+ if (!s->dma_mr) {
87
+ s->clocks = imx6ul_gpt_clocks;
140
+ error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set");
141
+ return;
142
+ }
143
+
144
+ address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma");
145
+}
88
+}
146
+
89
+
147
static void allwinner_sdhost_reset(DeviceState *dev)
90
static void imx7_gpt_init(Object *obj)
148
{
91
{
149
AwSdHostState *s = AW_SDHOST(dev);
92
IMXGPTState *s = IMX_GPT(obj);
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
93
@@ -XXX,XX +XXX,XX @@ static const TypeInfo imx6_gpt_info = {
151
94
.instance_init = imx6_gpt_init,
152
dc->reset = allwinner_sdhost_reset;
95
};
153
dc->vmsd = &vmstate_allwinner_sdhost;
96
154
+ dc->realize = allwinner_sdhost_realize;
97
+static const TypeInfo imx6ul_gpt_info = {
155
+ device_class_set_props(dc, allwinner_sdhost_properties);
98
+ .name = TYPE_IMX6UL_GPT,
99
+ .parent = TYPE_IMX25_GPT,
100
+ .instance_init = imx6ul_gpt_init,
101
+};
102
+
103
static const TypeInfo imx7_gpt_info = {
104
.name = TYPE_IMX7_GPT,
105
.parent = TYPE_IMX25_GPT,
106
@@ -XXX,XX +XXX,XX @@ static void imx_gpt_register_types(void)
107
type_register_static(&imx25_gpt_info);
108
type_register_static(&imx31_gpt_info);
109
type_register_static(&imx6_gpt_info);
110
+ type_register_static(&imx6ul_gpt_info);
111
type_register_static(&imx7_gpt_info);
156
}
112
}
157
113
158
static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
159
--
114
--
160
2.20.1
115
2.25.1
161
162
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
According to AArch64.TagCheckFault, none of the other ISS values are
3
IRQs were not associated to the various GPIO devices inside i.MX7D.
4
provided, so we do not need to go so far as merge_syn_data_abort.
4
This patch brings the i.MX7D on par with i.MX6.
5
But we were missing the WnR bit.
6
5
7
Tested-by: Andrey Konovalov <andreyknvl@google.com>
6
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
8
Reported-by: Andrey Konovalov <andreyknvl@google.com>
7
Message-id: 20221226101418.415170-1-jcd@tribudubois.net
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200813200816.3037186-3-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
target/arm/mte_helper.c | 9 +++++----
11
include/hw/arm/fsl-imx7.h | 15 +++++++++++++++
15
1 file changed, 5 insertions(+), 4 deletions(-)
12
hw/arm/fsl-imx7.c | 31 ++++++++++++++++++++++++++++++-
13
2 files changed, 45 insertions(+), 1 deletion(-)
16
14
17
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
15
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/mte_helper.c
17
--- a/include/hw/arm/fsl-imx7.h
20
+++ b/target/arm/mte_helper.c
18
+++ b/include/hw/arm/fsl-imx7.h
21
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
19
@@ -XXX,XX +XXX,XX @@ enum FslIMX7IRQs {
22
{
20
FSL_IMX7_GPT3_IRQ = 53,
23
int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
21
FSL_IMX7_GPT4_IRQ = 52,
24
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
22
25
- int el, reg_el, tcf, select;
23
+ FSL_IMX7_GPIO1_LOW_IRQ = 64,
26
+ int el, reg_el, tcf, select, is_write, syn;
24
+ FSL_IMX7_GPIO1_HIGH_IRQ = 65,
27
uint64_t sctlr;
25
+ FSL_IMX7_GPIO2_LOW_IRQ = 66,
28
26
+ FSL_IMX7_GPIO2_HIGH_IRQ = 67,
29
reg_el = regime_el(env, arm_mmu_idx);
27
+ FSL_IMX7_GPIO3_LOW_IRQ = 68,
30
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
28
+ FSL_IMX7_GPIO3_HIGH_IRQ = 69,
31
*/
29
+ FSL_IMX7_GPIO4_LOW_IRQ = 70,
32
cpu_restore_state(env_cpu(env), ra, true);
30
+ FSL_IMX7_GPIO4_HIGH_IRQ = 71,
33
env->exception.vaddress = dirty_ptr;
31
+ FSL_IMX7_GPIO5_LOW_IRQ = 72,
34
- raise_exception(env, EXCP_DATA_ABORT,
32
+ FSL_IMX7_GPIO5_HIGH_IRQ = 73,
35
- syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0, 0x11),
33
+ FSL_IMX7_GPIO6_LOW_IRQ = 74,
36
- exception_target_el(env));
34
+ FSL_IMX7_GPIO6_HIGH_IRQ = 75,
35
+ FSL_IMX7_GPIO7_LOW_IRQ = 76,
36
+ FSL_IMX7_GPIO7_HIGH_IRQ = 77,
37
+
37
+
38
+ is_write = FIELD_EX32(desc, MTEDESC, WRITE);
38
FSL_IMX7_WDOG1_IRQ = 78,
39
+ syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11);
39
FSL_IMX7_WDOG2_IRQ = 79,
40
+ raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));
40
FSL_IMX7_WDOG3_IRQ = 10,
41
/* noreturn, but fall through to the assert anyway */
41
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
42
42
index XXXXXXX..XXXXXXX 100644
43
case 0:
43
--- a/hw/arm/fsl-imx7.c
44
+++ b/hw/arm/fsl-imx7.c
45
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
46
FSL_IMX7_GPIO7_ADDR,
47
};
48
49
+ static const int FSL_IMX7_GPIOn_LOW_IRQ[FSL_IMX7_NUM_GPIOS] = {
50
+ FSL_IMX7_GPIO1_LOW_IRQ,
51
+ FSL_IMX7_GPIO2_LOW_IRQ,
52
+ FSL_IMX7_GPIO3_LOW_IRQ,
53
+ FSL_IMX7_GPIO4_LOW_IRQ,
54
+ FSL_IMX7_GPIO5_LOW_IRQ,
55
+ FSL_IMX7_GPIO6_LOW_IRQ,
56
+ FSL_IMX7_GPIO7_LOW_IRQ,
57
+ };
58
+
59
+ static const int FSL_IMX7_GPIOn_HIGH_IRQ[FSL_IMX7_NUM_GPIOS] = {
60
+ FSL_IMX7_GPIO1_HIGH_IRQ,
61
+ FSL_IMX7_GPIO2_HIGH_IRQ,
62
+ FSL_IMX7_GPIO3_HIGH_IRQ,
63
+ FSL_IMX7_GPIO4_HIGH_IRQ,
64
+ FSL_IMX7_GPIO5_HIGH_IRQ,
65
+ FSL_IMX7_GPIO6_HIGH_IRQ,
66
+ FSL_IMX7_GPIO7_HIGH_IRQ,
67
+ };
68
+
69
sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort);
70
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
71
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
72
+ FSL_IMX7_GPIOn_ADDR[i]);
73
+
74
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
75
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
76
+ FSL_IMX7_GPIOn_LOW_IRQ[i]));
77
+
78
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
79
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
80
+ FSL_IMX7_GPIOn_HIGH_IRQ[i]));
81
}
82
83
/*
44
--
84
--
45
2.20.1
85
2.25.1
46
47
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Stephen Longfield <slongfield@google.com>
2
2
3
To better align the read/write accesses, display the value after
3
Size is used at lines 1088/1188 for the loop, which reads the last 4
4
the offset (read accesses only display the offset).
4
bytes from the crc_ptr so it does need to get increased, however it
5
shouldn't be increased before the buffer is passed to CRC computation,
6
or the crc32 function will access uninitialized memory.
5
7
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
This was pointed out to me by clg@kaod.org during the code review of
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
a similar patch to hw/net/ftgmac100.c
8
Message-id: 20200812190206.31595-2-f4bug@amsat.org
10
11
Change-Id: Ib0464303b191af1e28abeb2f5105eb25aadb5e9b
12
Signed-off-by: Stephen Longfield <slongfield@google.com>
13
Reviewed-by: Patrick Venture <venture@google.com>
14
Message-id: 20221221183202.3788132-1-slongfield@google.com
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
17
---
11
hw/misc/unimp.c | 8 ++++----
18
hw/net/imx_fec.c | 8 ++++----
12
1 file changed, 4 insertions(+), 4 deletions(-)
19
1 file changed, 4 insertions(+), 4 deletions(-)
13
20
14
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
21
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/unimp.c
23
--- a/hw/net/imx_fec.c
17
+++ b/hw/misc/unimp.c
24
+++ b/hw/net/imx_fec.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
25
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
19
{
26
return 0;
20
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
27
}
21
28
22
- qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
29
- /* 4 bytes for the CRC. */
23
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
30
- size += 4;
24
"(size %d, offset 0x%" HWADDR_PRIx ")\n",
31
crc = cpu_to_be32(crc32(~0, buf, size));
25
s->name, size, offset);
32
+ /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
26
return 0;
33
+ size += 4;
27
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
34
crc_ptr = (uint8_t *) &crc;
28
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
35
29
36
/* Huge frames are truncated. */
30
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
37
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
31
- "(size %d, value 0x%" PRIx64
38
return 0;
32
- ", offset 0x%" HWADDR_PRIx ")\n",
39
}
33
- s->name, size, value, offset);
40
34
+ "(size %d, offset 0x%" HWADDR_PRIx
41
- /* 4 bytes for the CRC. */
35
+ ", value 0x%" PRIx64 ")\n",
42
- size += 4;
36
+ s->name, size, offset, value);
43
crc = cpu_to_be32(crc32(~0, buf, size));
37
}
44
+ /* Increase size by 4, loop below reads the last 4 bytes from crc_ptr. */
38
45
+ size += 4;
39
static const MemoryRegionOps unimp_ops = {
46
crc_ptr = (uint8_t *) &crc;
47
48
if (shift16) {
40
--
49
--
41
2.20.1
50
2.25.1
42
43
diff view generated by jsdifflib