[PULL 00/35] target-arm queue
[PULL 00/24] target-arm queue
1
Nothing earth-shaking in here, just a lot of refactoring and cleanup
1
The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
2
and a few bugfixes. I suspect I'll have another pullreq to come in
3
the early part of next week...
4
2
5
The following changes since commit 19591e9e0938ea5066984553c256a043bd5d822f:
3
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
6
7
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-08-27 16:59:02 +0100)
8
4
9
are available in the Git repository at:
5
are available in the Git repository at:
10
6
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200828
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
12
8
13
for you to fetch changes up to ed78849d9711805bda37ee026018d6ee7a606d0e:
9
for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
14
10
15
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd (2020-08-28 10:02:50 +0100)
11
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
16
12
17
----------------------------------------------------------------
13
----------------------------------------------------------------
18
target-arm queue:
14
target-arm queue:
19
* target/arm: Cleanup and refactoring preparatory to SVE2
15
* more MVE instructions
20
* armsse: Define ARMSSEClass correctly
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
21
* hw/misc/unimp: Improve information provided in log messages
17
* target/arm: Check NaN mode before silencing NaN
22
* hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
23
* hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
19
* hw/arm: Add basic power management to raspi.
24
* hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
25
* hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
26
* target/arm: Fill in the WnR syndrome bit in mte_check_fail
27
* target/arm: Clarify HCR_EL2 ARMCPRegInfo type
28
* hw/arm/musicpal: Use AddressSpace for DMA transfers
29
* hw/clock: Minor cleanups
30
* hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
31
21
32
----------------------------------------------------------------
22
----------------------------------------------------------------
33
Eduardo Habkost (1):
23
Joe Komlodi (1):
34
armsse: Define ARMSSEClass correctly
24
target/arm: Check NaN mode before silencing NaN
35
25
36
Graeme Gregory (1):
26
Maxim Uvarov (1):
37
hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
27
hw/gpio/gpio_pwr: use shutdown function for reboot
38
28
39
Philippe Mathieu-Daudé (14):
29
Nolan Leake (1):
40
hw/clock: Remove unused clock_init*() functions
30
hw/arm: Add basic power management to raspi.
41
hw/clock: Let clock_set() return boolean value
42
hw/clock: Only propagate clock changes if the clock is changed
43
hw/arm/musicpal: Use AddressSpace for DMA transfers
44
target/arm: Clarify HCR_EL2 ARMCPRegInfo type
45
hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
46
hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
47
hw/arm/xilinx_zynq: Uninline cadence_uart_create()
48
hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
49
hw/qdev-clock: Uninline qdev_connect_clock_in()
50
hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
51
hw/misc/unimp: Display value after offset
52
hw/misc/unimp: Display the value with width of the access size
53
hw/misc/unimp: Display the offset with width of the region size
54
31
55
Richard Henderson (19):
32
Patrick Venture (2):
56
target/arm: Pass the entire mte descriptor to mte_check_fail
33
docs/system/arm: Add quanta-q7l1-bmc reference
57
target/arm: Fill in the WnR syndrome bit in mte_check_fail
34
docs/system/arm: Add quanta-gbs-bmc reference
58
qemu/int128: Add int128_lshift
59
target/arm: Split out gen_gvec_fn_zz
60
target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
61
target/arm: Rearrange {sve,fp}_check_access assert
62
target/arm: Merge do_vector2_p into do_mov_p
63
target/arm: Clean up 4-operand predicate expansion
64
target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
65
target/arm: Split out gen_gvec_ool_zzzp
66
target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
67
target/arm: Split out gen_gvec_ool_zzp
68
target/arm: Split out gen_gvec_ool_zzz
69
target/arm: Split out gen_gvec_ool_zz
70
target/arm: Tidy SVE tszimm shift formats
71
target/arm: Generalize inl_qrdmlah_* helper functions
72
target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
73
target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
74
target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
75
35
76
include/hw/arm/armsse.h | 2 +-
36
Peter Maydell (18):
77
include/hw/char/cadence_uart.h | 17 --
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
78
include/hw/clock.h | 30 +--
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
79
include/hw/misc/unimp.h | 1 +
39
target/arm: Make asimd_imm_const() public
80
include/hw/net/allwinner-sun8i-emac.h | 6 +
40
target/arm: Use asimd_imm_const for A64 decode
81
include/hw/qdev-clock.h | 8 +-
41
target/arm: Use dup_const() instead of bitfield_replicate()
82
include/hw/sd/allwinner-sdhost.h | 6 +
42
target/arm: Implement MVE logical immediate insns
83
include/qemu/int128.h | 16 ++
43
target/arm: Implement MVE vector shift left by immediate insns
84
target/arm/helper-sve.h | 5 -
44
target/arm: Implement MVE vector shift right by immediate insns
85
target/arm/helper.h | 28 +++
45
target/arm: Implement MVE VSHLL
86
target/arm/translate.h | 1 +
46
target/arm: Implement MVE VSRI, VSLI
87
target/arm/sve.decode | 35 ++-
47
target/arm: Implement MVE VSHRN, VRSHRN
88
hw/arm/allwinner-a10.c | 2 +
48
target/arm: Implement MVE saturating narrowing shifts
89
hw/arm/allwinner-h3.c | 4 +
49
target/arm: Implement MVE VSHLC
90
hw/arm/armsse.c | 1 +
50
target/arm: Implement MVE VADDLV
91
hw/arm/musicpal.c | 45 ++--
51
target/arm: Implement MVE long shifts by immediate
92
hw/arm/sbsa-ref.c | 2 +-
52
target/arm: Implement MVE long shifts by register
93
hw/arm/xilinx_zynq.c | 24 +-
53
target/arm: Implement MVE shifts by immediate
94
hw/core/clock.c | 7 +-
54
target/arm: Implement MVE shifts by register
95
hw/core/qdev-clock.c | 6 +
96
hw/misc/unimp.c | 14 +-
97
hw/net/allwinner-sun8i-emac.c | 46 ++--
98
hw/sd/allwinner-sdhost.c | 37 +++-
99
target/arm/helper.c | 1 -
100
target/arm/mte_helper.c | 19 +-
101
target/arm/sve_helper.c | 70 ++----
102
target/arm/translate-a64.c | 110 ++++++++--
103
target/arm/translate-sve.c | 399 ++++++++++++++--------------------
104
target/arm/vec_helper.c | 182 +++++++++++-----
105
29 files changed, 629 insertions(+), 495 deletions(-)
106
55
56
Philippe Mathieu-Daudé (1):
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
58
59
docs/system/arm/aspeed.rst | 1 +
60
docs/system/arm/nuvoton.rst | 5 +-
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
82
diff view generated by jsdifflib
[PULL 01/35] hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Graeme Gregory <graeme@nuviainc.com>
1
From: Patrick Venture <venture@google.com>
2
2
3
Fixing a typo in a previous patch that translated an "i" to a 1
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
and therefore breaking the allocation of PCIe interrupts. This was
4
entry.
5
discovered when virtio-net-pci devices ceased to function correctly.
6
5
7
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Patrick Venture <venture@google.com>
8
Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state")
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
9
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
8
Message-id: 20210615192848.1065297-2-venture@google.com
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20200821083853.356490-1-graeme@nuviainc.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/arm/sbsa-ref.c | 2 +-
11
docs/system/arm/aspeed.rst | 1 +
15
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 1 insertion(+)
16
13
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/sbsa-ref.c
16
--- a/docs/system/arm/aspeed.rst
20
+++ b/hw/arm/sbsa-ref.c
17
+++ b/docs/system/arm/aspeed.rst
21
@@ -XXX,XX +XXX,XX @@ static void create_pcie(SBSAMachineState *sms)
18
@@ -XXX,XX +XXX,XX @@ etc.
22
19
AST2400 SoC based machines :
23
for (i = 0; i < GPEX_NUM_IRQS; i++) {
20
24
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
25
- qdev_get_gpio_in(sms->gic, irq + 1));
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
26
+ qdev_get_gpio_in(sms->gic, irq + i));
23
27
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
24
AST2500 SoC based machines :
28
}
29
25
30
--
26
--
31
2.20.1
27
2.20.1
32
28
33
29
diff view generated by jsdifflib
[PULL 02/35] hw/clock: Remove unused clock_init*() functions
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
clock_init*() inlined funtions are simple wrappers around
4
clock_set*() and are not used. Remove them in favor of clock_set*().
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200806123858.30058-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/clock.h | 13 -------------
12
1 file changed, 13 deletions(-)
13
14
diff --git a/include/hw/clock.h b/include/hw/clock.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/clock.h
17
+++ b/include/hw/clock.h
18
@@ -XXX,XX +XXX,XX @@ static inline bool clock_is_enabled(const Clock *clk)
19
return clock_get(clk) != 0;
20
}
21
22
-static inline void clock_init(Clock *clk, uint64_t value)
23
-{
24
- clock_set(clk, value);
25
-}
26
-static inline void clock_init_hz(Clock *clk, uint64_t value)
27
-{
28
- clock_set_hz(clk, value);
29
-}
30
-static inline void clock_init_ns(Clock *clk, uint64_t value)
31
-{
32
- clock_set_ns(clk, value);
33
-}
34
-
35
#endif /* QEMU_HW_CLOCK_H */
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
[PULL 04/35] hw/clock: Only propagate clock changes if the clock is changed
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
Avoid propagating the clock change when the clock does not change.
3
Add line item reference to quanta-gbs-bmc machine.
4
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Patrick Venture <venture@google.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Message-id: 20200806123858.30058-4-f4bug@amsat.org
7
Message-id: 20210615192848.1065297-3-venture@google.com
8
[PMM: fixed underline Sphinx warning]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
include/hw/clock.h | 5 +++--
11
docs/system/arm/nuvoton.rst | 5 +++--
11
1 file changed, 3 insertions(+), 2 deletions(-)
12
1 file changed, 3 insertions(+), 2 deletions(-)
12
13
13
diff --git a/include/hw/clock.h b/include/hw/clock.h
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/clock.h
16
--- a/docs/system/arm/nuvoton.rst
16
+++ b/include/hw/clock.h
17
+++ b/docs/system/arm/nuvoton.rst
17
@@ -XXX,XX +XXX,XX @@ void clock_propagate(Clock *clk);
18
@@ -XXX,XX +XXX,XX @@
18
*/
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
19
static inline void clock_update(Clock *clk, uint64_t value)
20
-=====================================================
20
{
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
21
- clock_set(clk, value);
22
+================================================================
22
- clock_propagate(clk);
23
23
+ if (clock_set(clk, value)) {
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
24
+ clock_propagate(clk);
25
designed to be used as Baseboard Management Controllers (BMCs) in various
25
+ }
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
26
}
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
27
28
Hyperscale applications. The following machines are based on this chip :
28
static inline void clock_update_hz(Clock *clk, unsigned hz)
29
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
31
- ``quanta-gsj`` Quanta GSJ server BMC
32
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
29
--
34
--
30
2.20.1
35
2.20.1
31
36
32
37
diff view generated by jsdifflib
[PULL 05/35] hw/arm/musicpal: Use AddressSpace for DMA transfers
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
Allow the device to execute the DMA transfers in a different
3
This is just enough to make reboot and poweroff work. Works for
4
AddressSpace.
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
We keep using the system_memory address space, but via the
6
do what linux does for reset.
7
proper dma_memory_access() API.
7
8
8
The watchdog timer functionality is not yet implemented.
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Message-id: 20200814125533.4047-1-f4bug@amsat.org
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
18
---
14
hw/arm/musicpal.c | 45 +++++++++++++++++++++++++++++++--------------
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
15
1 file changed, 31 insertions(+), 14 deletions(-)
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
16
21
hw/arm/bcm2835_peripherals.c | 13 ++-
17
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
23
hw/misc/meson.build | 1 +
24
5 files changed, 204 insertions(+), 2 deletions(-)
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
26
create mode 100644 hw/misc/bcm2835_powermgt.c
27
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
18
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/musicpal.c
30
--- a/include/hw/arm/bcm2835_peripherals.h
20
+++ b/hw/arm/musicpal.c
31
+++ b/include/hw/arm/bcm2835_peripherals.h
21
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
22
#include "hw/audio/wm8750.h"
33
#include "hw/misc/bcm2835_mphi.h"
23
#include "sysemu/block-backend.h"
34
#include "hw/misc/bcm2835_thermal.h"
24
#include "sysemu/runstate.h"
35
#include "hw/misc/bcm2835_cprman.h"
25
+#include "sysemu/dma.h"
36
+#include "hw/misc/bcm2835_powermgt.h"
26
#include "exec/address-spaces.h"
37
#include "hw/sd/sdhci.h"
27
#include "ui/pixel_ops.h"
38
#include "hw/sd/bcm2835_sdhost.h"
28
#include "qemu/cutils.h"
39
#include "hw/gpio/bcm2835_gpio.h"
29
@@ -XXX,XX +XXX,XX @@ typedef struct mv88w8618_eth_state {
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
30
41
BCM2835MphiState mphi;
31
MemoryRegion iomem;
42
UnimplementedDeviceState txp;
32
qemu_irq irq;
43
UnimplementedDeviceState armtmr;
33
+ MemoryRegion *dma_mr;
44
- UnimplementedDeviceState powermgt;
34
+ AddressSpace dma_as;
45
+ BCM2835PowerMgtState powermgt;
35
uint32_t smir;
46
BCM2835CprmanState cprman;
36
uint32_t icr;
47
PL011State uart0;
37
uint32_t imr;
48
BCM2835AuxState aux;
38
@@ -XXX,XX +XXX,XX @@ typedef struct mv88w8618_eth_state {
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
39
NICConf conf;
50
new file mode 100644
40
} mv88w8618_eth_state;
51
index XXXXXXX..XXXXXXX
41
52
--- /dev/null
42
-static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
53
+++ b/include/hw/misc/bcm2835_powermgt.h
43
+static void eth_rx_desc_put(AddressSpace *dma_as, uint32_t addr,
54
@@ -XXX,XX +XXX,XX @@
44
+ mv88w8618_rx_desc *desc)
55
+/*
45
{
56
+ * BCM2835 Power Management emulation
46
cpu_to_le32s(&desc->cmdstat);
57
+ *
47
cpu_to_le16s(&desc->bytes);
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
48
cpu_to_le16s(&desc->buffer_size);
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
49
cpu_to_le32s(&desc->buffer);
60
+ *
50
cpu_to_le32s(&desc->next);
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
51
- cpu_physical_memory_write(addr, desc, sizeof(*desc));
62
+ * See the COPYING file in the top-level directory.
52
+ dma_memory_write(dma_as, addr, desc, sizeof(*desc));
63
+ */
64
+
65
+#ifndef BCM2835_POWERMGT_H
66
+#define BCM2835_POWERMGT_H
67
+
68
+#include "hw/sysbus.h"
69
+#include "qom/object.h"
70
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
73
+
74
+struct BCM2835PowerMgtState {
75
+ SysBusDevice busdev;
76
+ MemoryRegion iomem;
77
+
78
+ uint32_t rstc;
79
+ uint32_t rsts;
80
+ uint32_t wdog;
81
+};
82
+
83
+#endif
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/bcm2835_peripherals.c
87
+++ b/hw/arm/bcm2835_peripherals.c
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
89
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
91
OBJECT(&s->gpu_bus_mr));
92
+
93
+ /* Power Management */
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
95
+ TYPE_BCM2835_POWERMGT);
53
}
96
}
54
97
55
-static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
56
+static void eth_rx_desc_get(AddressSpace *dma_as, uint32_t addr,
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
57
+ mv88w8618_rx_desc *desc)
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
58
{
101
INTERRUPT_USB));
59
- cpu_physical_memory_read(addr, desc, sizeof(*desc));
102
60
+ dma_memory_read(dma_as, addr, desc, sizeof(*desc));
103
+ /* Power Management */
61
le32_to_cpus(&desc->cmdstat);
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
62
le16_to_cpus(&desc->bytes);
63
le16_to_cpus(&desc->buffer_size);
64
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
65
continue;
66
}
67
do {
68
- eth_rx_desc_get(desc_addr, &desc);
69
+ eth_rx_desc_get(&s->dma_as, desc_addr, &desc);
70
if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
71
- cpu_physical_memory_write(desc.buffer + s->vlan_header,
72
+ dma_memory_write(&s->dma_as, desc.buffer + s->vlan_header,
73
buf, size);
74
desc.bytes = size + s->vlan_header;
75
desc.cmdstat &= ~MP_ETH_RX_OWN;
76
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
77
if (s->icr & s->imr) {
78
qemu_irq_raise(s->irq);
79
}
80
- eth_rx_desc_put(desc_addr, &desc);
81
+ eth_rx_desc_put(&s->dma_as, desc_addr, &desc);
82
return size;
83
}
84
desc_addr = desc.next;
85
@@ -XXX,XX +XXX,XX @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
86
return size;
87
}
88
89
-static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
90
+static void eth_tx_desc_put(AddressSpace *dma_as, uint32_t addr,
91
+ mv88w8618_tx_desc *desc)
92
{
93
cpu_to_le32s(&desc->cmdstat);
94
cpu_to_le16s(&desc->res);
95
cpu_to_le16s(&desc->bytes);
96
cpu_to_le32s(&desc->buffer);
97
cpu_to_le32s(&desc->next);
98
- cpu_physical_memory_write(addr, desc, sizeof(*desc));
99
+ dma_memory_write(dma_as, addr, desc, sizeof(*desc));
100
}
101
102
-static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
103
+static void eth_tx_desc_get(AddressSpace *dma_as, uint32_t addr,
104
+ mv88w8618_tx_desc *desc)
105
{
106
- cpu_physical_memory_read(addr, desc, sizeof(*desc));
107
+ dma_memory_read(dma_as, addr, desc, sizeof(*desc));
108
le32_to_cpus(&desc->cmdstat);
109
le16_to_cpus(&desc->res);
110
le16_to_cpus(&desc->bytes);
111
@@ -XXX,XX +XXX,XX @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
112
int len;
113
114
do {
115
- eth_tx_desc_get(desc_addr, &desc);
116
+ eth_tx_desc_get(&s->dma_as, desc_addr, &desc);
117
next_desc = desc.next;
118
if (desc.cmdstat & MP_ETH_TX_OWN) {
119
len = desc.bytes;
120
if (len < 2048) {
121
- cpu_physical_memory_read(desc.buffer, buf, len);
122
+ dma_memory_read(&s->dma_as, desc.buffer, buf, len);
123
qemu_send_packet(qemu_get_queue(s->nic), buf, len);
124
}
125
desc.cmdstat &= ~MP_ETH_TX_OWN;
126
s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
127
- eth_tx_desc_put(desc_addr, &desc);
128
+ eth_tx_desc_put(&s->dma_as, desc_addr, &desc);
129
}
130
desc_addr = next_desc;
131
} while (desc_addr != s->tx_queue[queue_index]);
132
@@ -XXX,XX +XXX,XX @@ static void mv88w8618_eth_realize(DeviceState *dev, Error **errp)
133
{
134
mv88w8618_eth_state *s = MV88W8618_ETH(dev);
135
136
+ if (!s->dma_mr) {
137
+ error_setg(errp, TYPE_MV88W8618_ETH " 'dma-memory' link not set");
138
+ return;
105
+ return;
139
+ }
106
+ }
140
+
107
+
141
+ address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
142
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
143
object_get_typename(OBJECT(dev)), dev->id, s);
110
+
144
}
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
145
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription mv88w8618_eth_vmsd = {
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
146
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
147
static Property mv88w8618_eth_properties[] = {
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
148
DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
149
+ DEFINE_PROP_LINK("dma-memory", mv88w8618_eth_state, dma_mr,
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
150
+ TYPE_MEMORY_REGION, MemoryRegion *),
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
151
DEFINE_PROP_END_OF_LIST(),
118
new file mode 100644
152
};
119
index XXXXXXX..XXXXXXX
153
120
--- /dev/null
154
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
121
+++ b/hw/misc/bcm2835_powermgt.c
155
qemu_check_nic_model(&nd_table[0], "mv88w8618");
122
@@ -XXX,XX +XXX,XX @@
156
dev = qdev_new(TYPE_MV88W8618_ETH);
123
+/*
157
qdev_set_nic_properties(dev, &nd_table[0]);
124
+ * BCM2835 Power Management emulation
158
+ object_property_set_link(OBJECT(dev), "dma-memory",
125
+ *
159
+ OBJECT(get_system_memory()), &error_fatal);
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
160
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
161
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
128
+ *
162
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
130
+ * See the COPYING file in the top-level directory.
131
+ */
132
+
133
+#include "qemu/osdep.h"
134
+#include "qemu/log.h"
135
+#include "qemu/module.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
137
+#include "migration/vmstate.h"
138
+#include "sysemu/runstate.h"
139
+
140
+#define PASSWORD 0x5a000000
141
+#define PASSWORD_MASK 0xff000000
142
+
143
+#define R_RSTC 0x1c
144
+#define V_RSTC_RESET 0x20
145
+#define R_RSTS 0x20
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
147
+#define R_WDOG 0x24
148
+
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
150
+ unsigned size)
151
+{
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
153
+ uint32_t res = 0;
154
+
155
+ switch (offset) {
156
+ case R_RSTC:
157
+ res = s->rstc;
158
+ break;
159
+ case R_RSTS:
160
+ res = s->rsts;
161
+ break;
162
+ case R_WDOG:
163
+ res = s->wdog;
164
+ break;
165
+
166
+ default:
167
+ qemu_log_mask(LOG_UNIMP,
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
169
+ "\n", offset);
170
+ res = 0;
171
+ break;
172
+ }
173
+
174
+ return res;
175
+}
176
+
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
178
+ uint64_t value, unsigned size)
179
+{
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
181
+
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
183
+ qemu_log_mask(LOG_GUEST_ERROR,
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
186
+ value, offset);
187
+ return;
188
+ }
189
+
190
+ value = value & ~PASSWORD_MASK;
191
+
192
+ switch (offset) {
193
+ case R_RSTC:
194
+ s->rstc = value;
195
+ if (value & V_RSTC_RESET) {
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
198
+ } else {
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
200
+ }
201
+ }
202
+ break;
203
+ case R_RSTS:
204
+ qemu_log_mask(LOG_UNIMP,
205
+ "bcm2835_powermgt_write: RSTS\n");
206
+ s->rsts = value;
207
+ break;
208
+ case R_WDOG:
209
+ qemu_log_mask(LOG_UNIMP,
210
+ "bcm2835_powermgt_write: WDOG\n");
211
+ s->wdog = value;
212
+ break;
213
+
214
+ default:
215
+ qemu_log_mask(LOG_UNIMP,
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
217
+ "\n", offset);
218
+ break;
219
+ }
220
+}
221
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
223
+ .read = bcm2835_powermgt_read,
224
+ .write = bcm2835_powermgt_write,
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
226
+ .impl.min_access_size = 4,
227
+ .impl.max_access_size = 4,
228
+};
229
+
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
231
+ .name = TYPE_BCM2835_POWERMGT,
232
+ .version_id = 1,
233
+ .minimum_version_id = 1,
234
+ .fields = (VMStateField[]) {
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
238
+ VMSTATE_END_OF_LIST()
239
+ }
240
+};
241
+
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
262
+{
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
264
+
265
+ dc->reset = bcm2835_powermgt_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
267
+}
268
+
269
+static TypeInfo bcm2835_powermgt_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
273
+ .class_init = bcm2835_powermgt_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
275
+};
276
+
277
+static void bcm2835_powermgt_register_types(void)
278
+{
279
+ type_register_static(&bcm2835_powermgt_info);
280
+}
281
+
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
284
index XXXXXXX..XXXXXXX 100644
285
--- a/hw/misc/meson.build
286
+++ b/hw/misc/meson.build
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
288
'bcm2835_rng.c',
289
'bcm2835_thermal.c',
290
'bcm2835_cprman.c',
291
+ 'bcm2835_powermgt.c',
292
))
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
163
--
295
--
164
2.20.1
296
2.20.1
165
297
166
298
diff view generated by jsdifflib
[PULL 14/35] hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Clock canonical name is set in device_set_realized (see the block
3
Add a test booting and quickly shutdown a raspi2 machine,
4
added to hw/core/qdev.c in commit 0e6934f264).
4
to test the power management model:
5
If we connect a clock after the device is realized, this code is
6
not executed. This is currently not a problem as this name is only
7
used for trace events, however this disrupt tracing.
8
5
9
Add a comment to document qdev_connect_clock_in() must be called
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
10
before the device is realized, and assert this condition.
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
11
44
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
14
Message-id: 20200803105647.22223-5-f4bug@amsat.org
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
49
---
17
include/hw/qdev-clock.h | 2 ++
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
18
hw/core/qdev-clock.c | 1 +
51
1 file changed, 43 insertions(+)
19
2 files changed, 3 insertions(+)
20
52
21
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
22
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/qdev-clock.h
55
--- a/tests/acceptance/boot_linux_console.py
24
+++ b/include/hw/qdev-clock.h
56
+++ b/tests/acceptance/boot_linux_console.py
25
@@ -XXX,XX +XXX,XX @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
57
@@ -XXX,XX +XXX,XX @@
26
*
58
from avocado import skip
27
* Set the source clock of input clock @name of device @dev to @source.
59
from avocado import skipUnless
28
* @source period update will be propagated to @name clock.
60
from avocado_qemu import Test
29
+ *
61
+from avocado_qemu import exec_command
30
+ * Must be called before @dev is realized.
62
from avocado_qemu import exec_command_and_wait_for_pattern
31
*/
63
from avocado_qemu import interrupt_interactive_console_until_pattern
32
void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source);
64
from avocado_qemu import wait_for_console_pattern
33
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
34
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
66
"""
35
index XXXXXXX..XXXXXXX 100644
67
self.do_test_arm_raspi2(0)
36
--- a/hw/core/qdev-clock.c
68
37
+++ b/hw/core/qdev-clock.c
69
+ def test_arm_raspi2_initrd(self):
38
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
70
+ """
39
71
+ :avocado: tags=arch:arm
40
void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source)
72
+ :avocado: tags=machine:raspi2
41
{
73
+ """
42
+ assert(!dev->realized);
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
43
clock_set_source(qdev_get_clock_in(dev, name), source);
75
+ 'pool/main/r/raspberrypi-firmware/'
44
}
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
81
+
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
84
+ 'arm/rootfs-armv7a.cpio.gz')
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
89
+
90
+ self.vm.set_console()
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
93
+ 'panic=-1 noreboot ' +
94
+ 'dwc_otg.fiq_fsm_enable=0')
95
+ self.vm.add_args('-kernel', kernel_path,
96
+ '-dtb', dtb_path,
97
+ '-initrd', initrd_path,
98
+ '-append', kernel_command_line,
99
+ '-no-reboot')
100
+ self.vm.launch()
101
+ self.wait_for_console_pattern('Boot successful.')
102
+
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
104
+ 'BCM2835')
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
106
+ '/soc/cprman@7e101000')
107
+ exec_command(self, 'halt')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
110
+
111
def test_arm_exynos4210_initrd(self):
112
"""
113
:avocado: tags=arch:arm
45
--
114
--
46
2.20.1
115
2.20.1
47
116
48
117
diff view generated by jsdifflib
[PULL 18/35] armsse: Define ARMSSEClass correctly
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
From: Eduardo Habkost <ehabkost@redhat.com>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
TYPE_ARM_SSE is a TYPE_SYS_BUS_DEVICE subclass, but
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
ARMSSEClass::parent_class is declared as DeviceClass.
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
assert due to fpst->default_nan_mode being set.
5
6
6
It never caused any problems by pure luck:
7
To avoid this, we check to see what NaN mode we're running in before we call
8
floatxx_silence_nan().
7
9
8
We were not setting class_size for TYPE_ARM_SSE, so class_size of
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
9
TYPE_SYS_BUS_DEVICE was being used (sizeof(SysBusDeviceClass)).
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
This made the system allocate enough memory for TYPE_ARM_SSE
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
11
devices even though ARMSSEClass was too small for a sysbus
12
device.
13
14
Additionally, the ARMSSEClass::info field ended up at the same
15
offset as SysBusDeviceClass::explicit_ofw_unit_address. This
16
would make sysbus_get_fw_dev_path() crash for the device.
17
Luckily, sysbus_get_fw_dev_path() never gets called for
18
TYPE_ARM_SSE devices, because qdev_get_fw_dev_path() is only used
19
by the boot device code, and TYPE_ARM_SSE devices don't appear at
20
the fw_boot_order list.
21
22
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
23
Message-id: 20200826181006.4097163-1-ehabkost@redhat.com
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
15
---
27
include/hw/arm/armsse.h | 2 +-
16
target/arm/helper-a64.c | 12 +++++++++---
28
hw/arm/armsse.c | 1 +
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
29
2 files changed, 2 insertions(+), 1 deletion(-)
18
2 files changed, 27 insertions(+), 9 deletions(-)
30
19
31
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
32
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
33
--- a/include/hw/arm/armsse.h
22
--- a/target/arm/helper-a64.c
34
+++ b/include/hw/arm/armsse.h
23
+++ b/target/arm/helper-a64.c
35
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
36
typedef struct ARMSSEInfo ARMSSEInfo;
25
float16 nan = a;
37
26
if (float16_is_signaling_nan(a, fpst)) {
38
typedef struct ARMSSEClass {
27
float_raise(float_flag_invalid, fpst);
39
- DeviceClass parent_class;
28
- nan = float16_silence_nan(a, fpst);
40
+ SysBusDeviceClass parent_class;
29
+ if (!fpst->default_nan_mode) {
41
const ARMSSEInfo *info;
30
+ nan = float16_silence_nan(a, fpst);
42
} ARMSSEClass;
31
+ }
43
32
}
44
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
33
if (fpst->default_nan_mode) {
34
nan = float16_default_nan(fpst);
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
36
float32 nan = a;
37
if (float32_is_signaling_nan(a, fpst)) {
38
float_raise(float_flag_invalid, fpst);
39
- nan = float32_silence_nan(a, fpst);
40
+ if (!fpst->default_nan_mode) {
41
+ nan = float32_silence_nan(a, fpst);
42
+ }
43
}
44
if (fpst->default_nan_mode) {
45
nan = float32_default_nan(fpst);
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
47
float64 nan = a;
48
if (float64_is_signaling_nan(a, fpst)) {
49
float_raise(float_flag_invalid, fpst);
50
- nan = float64_silence_nan(a, fpst);
51
+ if (!fpst->default_nan_mode) {
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
54
}
55
if (fpst->default_nan_mode) {
56
nan = float64_default_nan(fpst);
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
45
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/armsse.c
59
--- a/target/arm/vfp_helper.c
47
+++ b/hw/arm/armsse.c
60
+++ b/target/arm/vfp_helper.c
48
@@ -XXX,XX +XXX,XX @@ static const TypeInfo armsse_info = {
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
49
.name = TYPE_ARMSSE,
62
float16 nan = f16;
50
.parent = TYPE_SYS_BUS_DEVICE,
63
if (float16_is_signaling_nan(f16, fpst)) {
51
.instance_size = sizeof(ARMSSE),
64
float_raise(float_flag_invalid, fpst);
52
+ .class_size = sizeof(ARMSSEClass),
65
- nan = float16_silence_nan(f16, fpst);
53
.instance_init = armsse_init,
66
+ if (!fpst->default_nan_mode) {
54
.abstract = true,
67
+ nan = float16_silence_nan(f16, fpst);
55
.interfaces = (InterfaceInfo[]) {
68
+ }
69
}
70
if (fpst->default_nan_mode) {
71
nan = float16_default_nan(fpst);
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
73
float32 nan = f32;
74
if (float32_is_signaling_nan(f32, fpst)) {
75
float_raise(float_flag_invalid, fpst);
76
- nan = float32_silence_nan(f32, fpst);
77
+ if (!fpst->default_nan_mode) {
78
+ nan = float32_silence_nan(f32, fpst);
79
+ }
80
}
81
if (fpst->default_nan_mode) {
82
nan = float32_default_nan(fpst);
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
84
float64 nan = f64;
85
if (float64_is_signaling_nan(f64, fpst)) {
86
float_raise(float_flag_invalid, fpst);
87
- nan = float64_silence_nan(f64, fpst);
88
+ if (!fpst->default_nan_mode) {
89
+ nan = float64_silence_nan(f64, fpst);
90
+ }
91
}
92
if (fpst->default_nan_mode) {
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
56
--
127
--
57
2.20.1
128
2.20.1
58
129
59
130
diff view generated by jsdifflib
[PULL 27/35] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
The existing clr functions have only one vector argument, and so
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
can only clear in place. The existing movz functions have two
4
function has to be used for machine shutdown. Otherwise we cause
5
vector arguments, and so can clear while moving. Merge them, with
5
a reset with a bogus "cause" value, when we intended a shutdown.
6
a flag that controls the sense of active vs inactive elements
7
being cleared.
8
6
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200815013145.539409-10-richard.henderson@linaro.org
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
10
[PMM: tweaked commit message]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
12
---
14
target/arm/helper-sve.h | 5 ---
13
hw/gpio/gpio_pwr.c | 2 +-
15
target/arm/sve_helper.c | 70 ++++++++------------------------------
14
1 file changed, 1 insertion(+), 1 deletion(-)
16
target/arm/translate-sve.c | 53 +++++++++++------------------
17
3 files changed, 34 insertions(+), 94 deletions(-)
18
15
19
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper-sve.h
18
--- a/hw/gpio/gpio_pwr.c
22
+++ b/target/arm/helper-sve.h
19
+++ b/hw/gpio/gpio_pwr.c
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sve_uminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
24
DEF_HELPER_FLAGS_3(sve_uminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
25
DEF_HELPER_FLAGS_3(sve_uminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
26
27
-DEF_HELPER_FLAGS_3(sve_clr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
28
-DEF_HELPER_FLAGS_3(sve_clr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
29
-DEF_HELPER_FLAGS_3(sve_clr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
30
-DEF_HELPER_FLAGS_3(sve_clr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
31
-
32
DEF_HELPER_FLAGS_4(sve_movz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
33
DEF_HELPER_FLAGS_4(sve_movz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(sve_movz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
35
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/sve_helper.c
38
+++ b/target/arm/sve_helper.c
39
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sve_pnext)(void *vd, void *vg, uint32_t pred_desc)
40
return flags;
41
}
42
43
-/* Store zero into every active element of Zd. We will use this for two
44
- * and three-operand predicated instructions for which logic dictates a
45
- * zero result. In particular, logical shift by element size, which is
46
- * otherwise undefined on the host.
47
- *
48
- * For element sizes smaller than uint64_t, we use tables to expand
49
- * the N bits of the controlling predicate to a byte mask, and clear
50
- * those bytes.
51
+/*
52
+ * Copy Zn into Zd, and store zero into inactive elements.
53
+ * If inv, store zeros into the active elements.
54
*/
55
-void HELPER(sve_clr_b)(void *vd, void *vg, uint32_t desc)
56
-{
57
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
58
- uint64_t *d = vd;
59
- uint8_t *pg = vg;
60
- for (i = 0; i < opr_sz; i += 1) {
61
- d[i] &= ~expand_pred_b(pg[H1(i)]);
62
- }
63
-}
64
-
65
-void HELPER(sve_clr_h)(void *vd, void *vg, uint32_t desc)
66
-{
67
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
68
- uint64_t *d = vd;
69
- uint8_t *pg = vg;
70
- for (i = 0; i < opr_sz; i += 1) {
71
- d[i] &= ~expand_pred_h(pg[H1(i)]);
72
- }
73
-}
74
-
75
-void HELPER(sve_clr_s)(void *vd, void *vg, uint32_t desc)
76
-{
77
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
78
- uint64_t *d = vd;
79
- uint8_t *pg = vg;
80
- for (i = 0; i < opr_sz; i += 1) {
81
- d[i] &= ~expand_pred_s(pg[H1(i)]);
82
- }
83
-}
84
-
85
-void HELPER(sve_clr_d)(void *vd, void *vg, uint32_t desc)
86
-{
87
- intptr_t i, opr_sz = simd_oprsz(desc) / 8;
88
- uint64_t *d = vd;
89
- uint8_t *pg = vg;
90
- for (i = 0; i < opr_sz; i += 1) {
91
- if (pg[H1(i)] & 1) {
92
- d[i] = 0;
93
- }
94
- }
95
-}
96
-
97
-/* Copy Zn into Zd, and store zero into inactive elements. */
98
void HELPER(sve_movz_b)(void *vd, void *vn, void *vg, uint32_t desc)
99
{
22
{
100
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
23
if (level) {
101
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
102
uint64_t *d = vd, *n = vn;
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
103
uint8_t *pg = vg;
104
+
105
for (i = 0; i < opr_sz; i += 1) {
106
- d[i] = n[i] & expand_pred_b(pg[H1(i)]);
107
+ d[i] = n[i] & (expand_pred_b(pg[H1(i)]) ^ inv);
108
}
26
}
109
}
27
}
110
28
111
void HELPER(sve_movz_h)(void *vd, void *vn, void *vg, uint32_t desc)
112
{
113
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
114
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
115
uint64_t *d = vd, *n = vn;
116
uint8_t *pg = vg;
117
+
118
for (i = 0; i < opr_sz; i += 1) {
119
- d[i] = n[i] & expand_pred_h(pg[H1(i)]);
120
+ d[i] = n[i] & (expand_pred_h(pg[H1(i)]) ^ inv);
121
}
122
}
123
124
void HELPER(sve_movz_s)(void *vd, void *vn, void *vg, uint32_t desc)
125
{
126
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
127
+ uint64_t inv = -(uint64_t)(simd_data(desc) & 1);
128
uint64_t *d = vd, *n = vn;
129
uint8_t *pg = vg;
130
+
131
for (i = 0; i < opr_sz; i += 1) {
132
- d[i] = n[i] & expand_pred_s(pg[H1(i)]);
133
+ d[i] = n[i] & (expand_pred_s(pg[H1(i)]) ^ inv);
134
}
135
}
136
137
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_movz_d)(void *vd, void *vn, void *vg, uint32_t desc)
138
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
139
uint64_t *d = vd, *n = vn;
140
uint8_t *pg = vg;
141
+ uint8_t inv = simd_data(desc);
142
+
143
for (i = 0; i < opr_sz; i += 1) {
144
- d[i] = n[i] & -(uint64_t)(pg[H1(i)] & 1);
145
+ d[i] = n[i] & -(uint64_t)((pg[H1(i)] ^ inv) & 1);
146
}
147
}
148
149
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-sve.c
152
+++ b/target/arm/translate-sve.c
153
@@ -XXX,XX +XXX,XX @@ static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a)
154
*** SVE Shift by Immediate - Predicated Group
155
*/
156
157
-/* Store zero into every active element of Zd. We will use this for two
158
- * and three-operand predicated instructions for which logic dictates a
159
- * zero result.
160
+/*
161
+ * Copy Zn into Zd, storing zeros into inactive elements.
162
+ * If invert, store zeros into the active elements.
163
*/
164
-static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz)
165
-{
166
- static gen_helper_gvec_2 * const fns[4] = {
167
- gen_helper_sve_clr_b, gen_helper_sve_clr_h,
168
- gen_helper_sve_clr_s, gen_helper_sve_clr_d,
169
- };
170
- if (sve_access_check(s)) {
171
- unsigned vsz = vec_full_reg_size(s);
172
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
173
- pred_full_reg_offset(s, pg),
174
- vsz, vsz, 0, fns[esz]);
175
- }
176
- return true;
177
-}
178
-
179
-/* Copy Zn into Zd, storing zeros into inactive elements. */
180
-static void do_movz_zpz(DisasContext *s, int rd, int rn, int pg, int esz)
181
+static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
182
+ int esz, bool invert)
183
{
184
static gen_helper_gvec_3 * const fns[4] = {
185
gen_helper_sve_movz_b, gen_helper_sve_movz_h,
186
gen_helper_sve_movz_s, gen_helper_sve_movz_d,
187
};
188
- unsigned vsz = vec_full_reg_size(s);
189
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
190
- vec_full_reg_offset(s, rn),
191
- pred_full_reg_offset(s, pg),
192
- vsz, vsz, 0, fns[esz]);
193
+
194
+ if (sve_access_check(s)) {
195
+ unsigned vsz = vec_full_reg_size(s);
196
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
197
+ vec_full_reg_offset(s, rn),
198
+ pred_full_reg_offset(s, pg),
199
+ vsz, vsz, invert, fns[esz]);
200
+ }
201
+ return true;
202
}
203
204
static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
205
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
206
/* Shift by element size is architecturally valid.
207
For logical shifts, it is a zeroing operation. */
208
if (a->imm >= (8 << a->esz)) {
209
- return do_clr_zp(s, a->rd, a->pg, a->esz);
210
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
211
} else {
212
return do_zpzi_ool(s, a, fns[a->esz]);
213
}
214
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
215
/* Shift by element size is architecturally valid.
216
For logical shifts, it is a zeroing operation. */
217
if (a->imm >= (8 << a->esz)) {
218
- return do_clr_zp(s, a->rd, a->pg, a->esz);
219
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
220
} else {
221
return do_zpzi_ool(s, a, fns[a->esz]);
222
}
223
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
224
/* Shift by element size is architecturally valid. For arithmetic
225
right shift for division, it is a zeroing operation. */
226
if (a->imm >= (8 << a->esz)) {
227
- return do_clr_zp(s, a->rd, a->pg, a->esz);
228
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
229
} else {
230
return do_zpzi_ool(s, a, fns[a->esz]);
231
}
232
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
233
234
/* Zero the inactive elements. */
235
gen_set_label(over);
236
- do_movz_zpz(s, a->rd, a->rd, a->pg, esz);
237
- return true;
238
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, esz, false);
239
}
240
241
static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr,
242
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
243
244
static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
245
{
246
- if (sve_access_check(s)) {
247
- do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz);
248
- }
249
- return true;
250
+ return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false);
251
}
252
--
29
--
253
2.20.1
30
2.20.1
254
31
255
32
diff view generated by jsdifflib
[PULL 17/35] hw/misc/unimp: Display the offset with width of the region size
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
In do_ldst(), the calculation of the offset needs to be based on the
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
2
5
3
To have a better idea of how big is the region where the offset
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
belongs, display the value with the width of the region size
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
(i.e. a region of 0x1000 bytes uses 0x000 format).
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
9
---
10
target/arm/translate-mve.c | 17 +++++++++--------
11
1 file changed, 9 insertions(+), 8 deletions(-)
6
12
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200812190206.31595-4-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/misc/unimp.h | 1 +
13
hw/misc/unimp.c | 10 ++++++----
14
2 files changed, 7 insertions(+), 4 deletions(-)
15
16
diff --git a/include/hw/misc/unimp.h b/include/hw/misc/unimp.h
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/misc/unimp.h
15
--- a/target/arm/translate-mve.c
19
+++ b/include/hw/misc/unimp.h
16
+++ b/target/arm/translate-mve.c
20
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
21
typedef struct {
18
}
22
SysBusDevice parent_obj;
23
MemoryRegion iomem;
24
+ unsigned offset_fmt_width;
25
char *name;
26
uint64_t size;
27
} UnimplementedDeviceState;
28
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/misc/unimp.c
31
+++ b/hw/misc/unimp.c
32
@@ -XXX,XX +XXX,XX @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
33
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
34
35
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
36
- "(size %d, offset 0x%" HWADDR_PRIx ")\n",
37
- s->name, size, offset);
38
+ "(size %d, offset 0x%0*" HWADDR_PRIx ")\n",
39
+ s->name, size, s->offset_fmt_width, offset);
40
return 0;
41
}
19
}
42
20
43
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
44
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
45
23
+ unsigned msize)
46
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
24
{
47
- "(size %d, offset 0x%" HWADDR_PRIx
25
TCGv_i32 addr;
48
+ "(size %d, offset 0x%0*" HWADDR_PRIx
26
uint32_t offset;
49
", value 0x%0*" PRIx64 ")\n",
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
50
- s->name, size, offset, size << 1, value);
28
return true;
51
+ s->name, size, s->offset_fmt_width, offset, size << 1, value);
29
}
30
31
- offset = a->imm << a->size;
32
+ offset = a->imm << msize;
33
if (!a->a) {
34
offset = -offset;
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
38
{ NULL, NULL }
39
};
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
52
}
42
}
53
43
54
static const MemoryRegionOps unimp_ops = {
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
55
@@ -XXX,XX +XXX,XX @@ static void unimp_realize(DeviceState *dev, Error **errp)
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
56
return;
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
57
}
54
}
58
55
59
+ s->offset_fmt_width = DIV_ROUND_UP(64 - clz64(s->size - 1), 4);
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
60
+
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
61
memory_region_init_io(&s->iomem, OBJECT(s), &unimp_ops, s,
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
62
s->name, s->size);
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
63
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
64
--
65
--
65
2.20.1
66
2.20.1
66
67
67
68
diff view generated by jsdifflib
[PULL 34/35] target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
insns had some bugs:
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
2
9
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
In particular, fixing the second of these allows us to recast
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
the implementation to avoid 128-bit arithmetic entirely.
5
Message-id: 20200815013145.539409-20-richard.henderson@linaro.org
12
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
7
---
20
---
8
target/arm/helper.h | 14 ++++++++++++++
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
9
target/arm/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++
22
1 file changed, 21 insertions(+), 17 deletions(-)
10
target/arm/vec_helper.c | 25 +++++++++++++++++++++++++
11
3 files changed, 73 insertions(+)
12
23
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
14
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.h
26
--- a/target/arm/mve_helper.c
16
+++ b/target/arm/helper.h
27
+++ b/target/arm/mve_helper.c
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
28
@@ -XXX,XX +XXX,XX @@
18
DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
29
*/
19
DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
30
20
31
#include "qemu/osdep.h"
21
+DEF_HELPER_FLAGS_5(gvec_mla_idx_h, TCG_CALL_NO_RWG,
32
-#include "qemu/int128.h"
22
+ void, ptr, ptr, ptr, ptr, i32)
33
#include "cpu.h"
23
+DEF_HELPER_FLAGS_5(gvec_mla_idx_s, TCG_CALL_NO_RWG,
34
#include "internals.h"
24
+ void, ptr, ptr, ptr, ptr, i32)
35
#include "vec_internal.h"
25
+DEF_HELPER_FLAGS_5(gvec_mla_idx_d, TCG_CALL_NO_RWG,
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
26
+ void, ptr, ptr, ptr, ptr, i32)
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
27
+
38
28
+DEF_HELPER_FLAGS_5(gvec_mls_idx_h, TCG_CALL_NO_RWG,
39
/*
29
+ void, ptr, ptr, ptr, ptr, i32)
40
- * Rounding multiply add long dual accumulate high: we must keep
30
+DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
41
- * a 72-bit internal accumulator value and return the top 64 bits.
31
+ void, ptr, ptr, ptr, ptr, i32)
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
32
+DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
43
+ * this is implemented with a 72-bit internal accumulator value of which
33
+ void, ptr, ptr, ptr, ptr, i32)
44
+ * the top 64 bits are returned. We optimize this to avoid having to
34
+
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
35
#ifdef TARGET_AARCH64
46
+ * is squashed back into 64-bits after each beat.
36
#include "helper-a64.h"
47
*/
37
#include "helper-sve.h"
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
38
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
39
index XXXXXXX..XXXXXXX 100644
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
40
--- a/target/arm/translate-a64.c
51
void *vm, uint64_t a) \
41
+++ b/target/arm/translate-a64.c
52
{ \
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
53
uint16_t mask = mve_element_mask(env); \
43
return;
54
unsigned e; \
44
}
55
TYPE *n = vn, *m = vm; \
45
break;
56
- Int128 acc = int128_lshift(TO128(a), 8); \
46
+
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
47
+ case 0x10: /* MLA */
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
48
+ if (!is_long && !is_scalar) {
59
if (mask & 1) { \
49
+ static gen_helper_gvec_4 * const fns[3] = {
60
+ LTYPE mul; \
50
+ gen_helper_gvec_mla_idx_h,
61
if (e & 1) { \
51
+ gen_helper_gvec_mla_idx_s,
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
52
+ gen_helper_gvec_mla_idx_d,
63
- m[H##ESIZE(e)])); \
53
+ };
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
54
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
65
+ if (SUB) { \
55
+ vec_full_reg_offset(s, rn),
66
+ mul = -mul; \
56
+ vec_full_reg_offset(s, rm),
67
+ } \
57
+ vec_full_reg_offset(s, rd),
68
} else { \
58
+ is_q ? 16 : 8, vec_full_reg_size(s),
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
59
+ index, fns[size - 1]);
70
- m[H##ESIZE(e)])); \
60
+ return;
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
61
+ }
72
} \
62
+ break;
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
63
+
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
64
+ case 0x14: /* MLS */
75
+ a += mul; \
65
+ if (!is_long && !is_scalar) {
76
} \
66
+ static gen_helper_gvec_4 * const fns[3] = {
77
} \
67
+ gen_helper_gvec_mls_idx_h,
78
mve_advance_vpt(env); \
68
+ gen_helper_gvec_mls_idx_s,
79
- return int128_getlo(int128_rshift(acc, 8)); \
69
+ gen_helper_gvec_mls_idx_d,
80
+ return a; \
70
+ };
71
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
72
+ vec_full_reg_offset(s, rn),
73
+ vec_full_reg_offset(s, rm),
74
+ vec_full_reg_offset(s, rd),
75
+ is_q ? 16 : 8, vec_full_reg_size(s),
76
+ index, fns[size - 1]);
77
+ return;
78
+ }
79
+ break;
80
}
81
}
81
82
82
if (size == 3) {
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
83
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
84
index XXXXXXX..XXXXXXX 100644
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
85
--- a/target/arm/vec_helper.c
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
86
+++ b/target/arm/vec_helper.c
87
87
@@ -XXX,XX +XXX,XX @@ DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
88
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
89
#undef DO_MUL_IDX
90
90
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
91
+#define DO_MLA_IDX(NAME, TYPE, OP, H) \
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
92
+void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
93
+{ \
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
94
+ intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
95
95
+ intptr_t idx = simd_data(desc); \
96
/* Vector add across vector */
96
+ TYPE *d = vd, *n = vn, *m = vm, *a = va; \
97
#define DO_VADDV(OP, ESIZE, TYPE) \
97
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
98
+ TYPE mm = m[H(i + idx)]; \
99
+ for (j = 0; j < segment; j++) { \
100
+ d[i + j] = a[i + j] OP n[i + j] * mm; \
101
+ } \
102
+ } \
103
+ clear_tail(d, oprsz, simd_maxsz(desc)); \
104
+}
105
+
106
+DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2)
107
+DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4)
108
+DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, )
109
+
110
+DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2)
111
+DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4)
112
+DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, )
113
+
114
+#undef DO_MLA_IDX
115
+
116
#define DO_FMUL_IDX(NAME, TYPE, H) \
117
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
118
{ \
119
--
98
--
120
2.20.1
99
2.20.1
121
100
122
101
diff view generated by jsdifflib
[PULL 32/35] target/arm: Generalize inl_qrdmlah_* helper functions
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The function asimd_imm_const() in translate-neon.c is an
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
2
5
3
Unify add/sub helpers and add a parameter for rounding.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
This will allow saturating non-rounding to reuse this code.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
9
---
10
target/arm/translate.h | 16 ++++++++++
11
target/arm/translate-neon.c | 63 -------------------------------------
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
5
14
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
7
[PMM: fixed accidental use of '=' rather than '+=' in do_sqrdmlah_s]
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-15-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/vec_helper.c | 80 +++++++++++++++--------------------------
13
1 file changed, 29 insertions(+), 51 deletions(-)
14
15
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/vec_helper.c
17
--- a/target/arm/translate.h
18
+++ b/target/arm/vec_helper.c
18
+++ b/target/arm/translate.h
19
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
20
#endif
20
return opc | s->be_data;
21
21
}
22
/* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
22
23
-static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2,
23
+/**
24
- int16_t src3, uint32_t *sat)
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
25
+static int16_t do_sqrdmlah_h(int16_t src1, int16_t src2, int16_t src3,
25
+ *
26
+ bool neg, bool round, uint32_t *sat)
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
27
{
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
28
- /* Simplify:
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ /*
29
+ *
30
+ * Simplify:
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
* = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
31
+ * callers must catch this.
32
* = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
32
+ *
33
*/
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
int32_t ret = (int32_t)src1 * src2;
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
- ret = ((int32_t)src3 << 15) + ret + (1 << 14);
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ if (neg) {
36
+ */
37
+ ret = -ret;
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+ }
39
+ ret += ((int32_t)src3 << 15) + (round << 14);
40
ret >>= 15;
41
+
38
+
42
if (ret != (int16_t)ret) {
39
#endif /* TARGET_ARM_TRANSLATE_H */
43
*sat = 1;
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
44
- ret = (ret < 0 ? -0x8000 : 0x7fff);
41
index XXXXXXX..XXXXXXX 100644
45
+ ret = (ret < 0 ? INT16_MIN : INT16_MAX);
42
--- a/target/arm/translate-neon.c
46
}
43
+++ b/target/arm/translate-neon.c
47
return ret;
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
48
}
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
49
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
50
uint32_t src2, uint32_t src3)
47
51
{
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
52
uint32_t *sat = &env->vfp.qc[0];
53
- uint16_t e1 = inl_qrdmlah_s16(src1, src2, src3, sat);
54
- uint16_t e2 = inl_qrdmlah_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
55
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, false, true, sat);
56
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
57
+ false, true, sat);
58
return deposit32(e1, 16, 16, e2);
59
}
60
61
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
62
uintptr_t i;
63
64
for (i = 0; i < opr_sz / 2; ++i) {
65
- d[i] = inl_qrdmlah_s16(n[i], m[i], d[i], vq);
66
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], false, true, vq);
67
}
68
clear_tail(d, opr_sz, simd_maxsz(desc));
69
}
70
71
-/* Signed saturating rounding doubling multiply-subtract high half, 16-bit */
72
-static int16_t inl_qrdmlsh_s16(int16_t src1, int16_t src2,
73
- int16_t src3, uint32_t *sat)
74
-{
49
-{
75
- /* Similarly, using subtraction:
50
- /*
76
- * = ((a3 << 16) - ((e1 * e2) << 1) + (1 << 15)) >> 16
51
- * Expand the encoded constant.
77
- * = ((a3 << 15) - (e1 * e2) + (1 << 14)) >> 15
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
78
- */
56
- */
79
- int32_t ret = (int32_t)src1 * src2;
57
- switch (cmode) {
80
- ret = ((int32_t)src3 << 15) - ret + (1 << 14);
58
- case 0: case 1:
81
- ret >>= 15;
59
- /* no-op */
82
- if (ret != (int16_t)ret) {
60
- break;
83
- *sat = 1;
61
- case 2: case 3:
84
- ret = (ret < 0 ? -0x8000 : 0x7fff);
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
85
- }
104
- }
86
- return ret;
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
87
-}
109
-}
88
-
110
-
89
uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
90
uint32_t src2, uint32_t src3)
112
GVecGen2iFn *fn)
91
{
113
{
92
uint32_t *sat = &env->vfp.qc[0];
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
93
- uint16_t e1 = inl_qrdmlsh_s16(src1, src2, src3, sat);
115
index XXXXXXX..XXXXXXX 100644
94
- uint16_t e2 = inl_qrdmlsh_s16(src1 >> 16, src2 >> 16, src3 >> 16, sat);
116
--- a/target/arm/translate.c
95
+ uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, true, true, sat);
117
+++ b/target/arm/translate.c
96
+ uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
97
+ true, true, sat);
119
a64_translate_init();
98
return deposit32(e1, 16, 16, e2);
99
}
120
}
100
121
101
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
102
uintptr_t i;
123
+{
103
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
104
for (i = 0; i < opr_sz / 2; ++i) {
125
+ switch (cmode) {
105
- d[i] = inl_qrdmlsh_s16(n[i], m[i], d[i], vq);
126
+ case 0: case 1:
106
+ d[i] = do_sqrdmlah_h(n[i], m[i], d[i], true, true, vq);
127
+ /* no-op */
107
}
128
+ break;
108
clear_tail(d, opr_sz, simd_maxsz(desc));
129
+ case 2: case 3:
109
}
130
+ imm <<= 8;
110
131
+ break;
111
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
132
+ case 4: case 5:
112
-static int32_t inl_qrdmlah_s32(int32_t src1, int32_t src2,
133
+ imm <<= 16;
113
- int32_t src3, uint32_t *sat)
134
+ break;
114
+static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
135
+ case 6: case 7:
115
+ bool neg, bool round, uint32_t *sat)
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
159
+ for (n = 0; n < 8; n++) {
160
+ if (imm & (1 << n)) {
161
+ imm64 |= (0xffULL << (n * 8));
162
+ }
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
116
{
181
{
117
/* Simplify similarly to int_qrdmlah_s16 above. */
118
int64_t ret = (int64_t)src1 * src2;
119
- ret = ((int64_t)src3 << 31) + ret + (1 << 30);
120
+ if (neg) {
121
+ ret = -ret;
122
+ }
123
+ ret += ((int64_t)src3 << 31) + (round << 30);
124
ret >>= 31;
125
+
126
if (ret != (int32_t)ret) {
127
*sat = 1;
128
ret = (ret < 0 ? INT32_MIN : INT32_MAX);
129
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
130
int32_t src2, int32_t src3)
131
{
132
uint32_t *sat = &env->vfp.qc[0];
133
- return inl_qrdmlah_s32(src1, src2, src3, sat);
134
+ return do_sqrdmlah_s(src1, src2, src3, false, true, sat);
135
}
136
137
void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
138
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
139
uintptr_t i;
140
141
for (i = 0; i < opr_sz / 4; ++i) {
142
- d[i] = inl_qrdmlah_s32(n[i], m[i], d[i], vq);
143
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], false, true, vq);
144
}
145
clear_tail(d, opr_sz, simd_maxsz(desc));
146
}
147
148
-/* Signed saturating rounding doubling multiply-subtract high half, 32-bit */
149
-static int32_t inl_qrdmlsh_s32(int32_t src1, int32_t src2,
150
- int32_t src3, uint32_t *sat)
151
-{
152
- /* Simplify similarly to int_qrdmlsh_s16 above. */
153
- int64_t ret = (int64_t)src1 * src2;
154
- ret = ((int64_t)src3 << 31) - ret + (1 << 30);
155
- ret >>= 31;
156
- if (ret != (int32_t)ret) {
157
- *sat = 1;
158
- ret = (ret < 0 ? INT32_MIN : INT32_MAX);
159
- }
160
- return ret;
161
-}
162
-
163
uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
164
int32_t src2, int32_t src3)
165
{
166
uint32_t *sat = &env->vfp.qc[0];
167
- return inl_qrdmlsh_s32(src1, src2, src3, sat);
168
+ return do_sqrdmlah_s(src1, src2, src3, true, true, sat);
169
}
170
171
void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
172
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
173
uintptr_t i;
174
175
for (i = 0; i < opr_sz / 4; ++i) {
176
- d[i] = inl_qrdmlsh_s32(n[i], m[i], d[i], vq);
177
+ d[i] = do_sqrdmlah_s(n[i], m[i], d[i], true, true, vq);
178
}
179
clear_tail(d, opr_sz, simd_maxsz(desc));
180
}
181
--
182
--
182
2.20.1
183
2.20.1
183
184
184
185
diff view generated by jsdifflib
[PULL 22/35] target/arm: Rearrange {sve,fp}_check_access assert
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
2
5
3
We want to ensure that access is checked by the time we ask
4
for a specific fp/vector register. We want to ensure that
5
we do not emit two lots of code to raise an exception.
6
7
But sometimes it's difficult to cleanly organize the code
8
such that we never pass through sve_check_access exactly once.
9
Allow multiple calls so long as the result is true, that is,
10
no exception to be raised.
11
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Message-id: 20200815013145.539409-5-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
16
---
9
---
17
target/arm/translate.h | 1 +
10
target/arm/translate.h | 3 +-
18
target/arm/translate-a64.c | 27 ++++++++++++++++-----------
11
target/arm/translate-a64.c | 86 ++++----------------------------------
19
2 files changed, 17 insertions(+), 11 deletions(-)
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
20
14
21
diff --git a/target/arm/translate.h b/target/arm/translate.h
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
22
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/translate.h
17
--- a/target/arm/translate.h
24
+++ b/target/arm/translate.h
18
+++ b/target/arm/translate.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
26
* that it is set at the point where we actually touch the FP regs.
20
* VMVN and VBIC (when cmode < 14 && op == 1).
27
*/
21
*
28
bool fp_access_checked;
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
29
+ bool sve_access_checked;
23
- * callers must catch this.
30
/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
24
+ * callers must catch this; we return the 64-bit constant value defined
31
* single-step support).
25
+ * for AArch64.
32
*/
26
*
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
33
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
34
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-a64.c
31
--- a/target/arm/translate-a64.c
36
+++ b/target/arm/translate-a64.c
32
+++ b/target/arm/translate-a64.c
37
@@ -XXX,XX +XXX,XX @@ static void do_vec_ld(DisasContext *s, int destidx, int element,
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
38
* unallocated-encoding checks (otherwise the syndrome information
39
* for the resulting exception will be incorrect).
40
*/
41
-static inline bool fp_access_check(DisasContext *s)
42
+static bool fp_access_check(DisasContext *s)
43
{
34
{
44
- assert(!s->fp_access_checked);
35
int rd = extract32(insn, 0, 5);
45
- s->fp_access_checked = true;
36
int cmode = extract32(insn, 12, 4);
46
+ if (s->fp_excp_el) {
37
- int cmode_3_1 = extract32(cmode, 1, 3);
47
+ assert(!s->fp_access_checked);
38
- int cmode_0 = extract32(cmode, 0, 1);
48
+ s->fp_access_checked = true;
39
int o2 = extract32(insn, 11, 1);
49
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
50
- if (!s->fp_excp_el) {
41
bool is_neg = extract32(insn, 29, 1);
51
- return true;
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
52
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
43
return;
53
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
54
+ return false;
55
}
44
}
45
46
- /* See AdvSIMDExpandImm() in ARM ARM */
47
- switch (cmode_3_1) {
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
52
- {
53
- int shift = cmode_3_1 * 8;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
55
- break;
56
- }
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
56
-
120
-
57
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
121
- if (cmode_3_1 != 7 && is_neg) {
58
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
122
- imm = ~imm;
59
- return false;
123
+ if (cmode == 15 && o2 && !is_neg) {
60
+ s->fp_access_checked = true;
124
+ /* FMOV (vector, immediate) - half-precision */
61
+ return true;
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
62
}
126
+ /* now duplicate across the lanes */
63
127
+ imm = bitfield_replicate(imm, 16);
64
/* Check that SVE access is enabled. If it is, return true.
128
+ } else {
65
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
66
bool sve_access_check(DisasContext *s)
67
{
68
if (s->sve_excp_el) {
69
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
70
- s->sve_excp_el);
71
+ assert(!s->sve_access_checked);
72
+ s->sve_access_checked = true;
73
+
74
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
75
+ syn_sve_access_trap(), s->sve_excp_el);
76
return false;
77
}
130
}
78
+ s->sve_access_checked = true;
131
79
return fp_access_check(s);
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
80
}
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
81
134
index XXXXXXX..XXXXXXX 100644
82
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
135
--- a/target/arm/translate.c
83
s->base.pc_next += 4;
136
+++ b/target/arm/translate.c
84
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
85
s->fp_access_checked = false;
138
case 14:
86
+ s->sve_access_checked = false;
139
if (op) {
87
140
/*
88
if (dc_isar_feature(aa64_bti, s)) {
141
- * This is the only case where the top and bottom 32 bits
89
if (s->base.num_insns == 1) {
142
- * of the encoded constant differ.
143
+ * This and cmode == 15 op == 1 are the only cases where
144
+ * the top and bottom 32 bits of the encoded constant differ.
145
*/
146
uint64_t imm64 = 0;
147
int n;
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
150
break;
151
case 15:
152
+ if (op) {
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
155
+ if (imm & 0x80) {
156
+ imm64 |= 0x8000000000000000ULL;
157
+ }
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
167
break;
90
--
168
--
91
2.20.1
169
2.20.1
92
170
93
171
diff view generated by jsdifflib
[PULL 33/35] target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Use dup_const() instead of bitfield_replicate() in
2
disas_simd_mod_imm().
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
(We can't replace the other use of bitfield_replicate() in this file,
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
in logic_imm_decode_wmask(), because that location needs to handle 2
5
Message-id: 20200815013145.539409-19-richard.henderson@linaro.org
6
and 4 bit elements, which dup_const() cannot.)
7
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
7
---
11
---
8
target/arm/helper.h | 4 ++++
12
target/arm/translate-a64.c | 2 +-
9
target/arm/translate-a64.c | 16 ++++++++++++++++
13
1 file changed, 1 insertion(+), 1 deletion(-)
10
target/arm/vec_helper.c | 29 +++++++++++++++++++++++++----
11
3 files changed, 45 insertions(+), 4 deletions(-)
12
14
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.h
16
+++ b/target/arm/helper.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(gvec_uaba_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
18
DEF_HELPER_FLAGS_4(gvec_uaba_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
19
DEF_HELPER_FLAGS_4(gvec_uaba_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
20
21
+DEF_HELPER_FLAGS_4(gvec_mul_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
22
+DEF_HELPER_FLAGS_4(gvec_mul_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
23
+DEF_HELPER_FLAGS_4(gvec_mul_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
24
+
25
#ifdef TARGET_AARCH64
26
#include "helper-a64.h"
27
#include "helper-sve.h"
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
31
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
33
data, gen_helper_gvec_fmlal_idx_a64);
20
/* FMOV (vector, immediate) - half-precision */
34
}
21
imm = vfp_expand_imm(MO_16, abcdefgh);
35
return;
22
/* now duplicate across the lanes */
36
+
23
- imm = bitfield_replicate(imm, 16);
37
+ case 0x08: /* MUL */
24
+ imm = dup_const(MO_16, imm);
38
+ if (!is_long && !is_scalar) {
25
} else {
39
+ static gen_helper_gvec_3 * const fns[3] = {
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
40
+ gen_helper_gvec_mul_idx_h,
41
+ gen_helper_gvec_mul_idx_s,
42
+ gen_helper_gvec_mul_idx_d,
43
+ };
44
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
45
+ vec_full_reg_offset(s, rn),
46
+ vec_full_reg_offset(s, rm),
47
+ is_q ? 16 : 8, vec_full_reg_size(s),
48
+ index, fns[size - 1]);
49
+ return;
50
+ }
51
+ break;
52
}
27
}
53
54
if (size == 3) {
55
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/vec_helper.c
58
+++ b/target/arm/vec_helper.c
59
@@ -XXX,XX +XXX,XX @@ DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
60
*/
61
62
#define DO_MUL_IDX(NAME, TYPE, H) \
63
+void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
64
+{ \
65
+ intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
66
+ intptr_t idx = simd_data(desc); \
67
+ TYPE *d = vd, *n = vn, *m = vm; \
68
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
69
+ TYPE mm = m[H(i + idx)]; \
70
+ for (j = 0; j < segment; j++) { \
71
+ d[i + j] = n[i + j] * mm; \
72
+ } \
73
+ } \
74
+ clear_tail(d, oprsz, simd_maxsz(desc)); \
75
+}
76
+
77
+DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2)
78
+DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4)
79
+DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
80
+
81
+#undef DO_MUL_IDX
82
+
83
+#define DO_FMUL_IDX(NAME, TYPE, H) \
84
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
85
{ \
86
intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
87
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
88
clear_tail(d, oprsz, simd_maxsz(desc)); \
89
}
90
91
-DO_MUL_IDX(gvec_fmul_idx_h, float16, H2)
92
-DO_MUL_IDX(gvec_fmul_idx_s, float32, H4)
93
-DO_MUL_IDX(gvec_fmul_idx_d, float64, )
94
+DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2)
95
+DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4)
96
+DO_FMUL_IDX(gvec_fmul_idx_d, float64, )
97
98
-#undef DO_MUL_IDX
99
+#undef DO_FMUL_IDX
100
101
#define DO_FMLA_IDX(NAME, TYPE, H) \
102
void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
103
--
28
--
104
2.20.1
29
2.20.1
105
30
106
31
diff view generated by jsdifflib
[PULL 13/35] hw/qdev-clock: Uninline qdev_connect_clock_in()
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
2
5
3
We want to assert the device is not realized. To avoid overloading
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
this header including "hw/qdev-core.h", uninline the function first.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 4 +++
11
target/arm/mve.decode | 17 +++++++++++++
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
5
15
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20200803105647.22223-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/qdev-clock.h | 6 +-----
12
hw/core/qdev-clock.c | 5 +++++
13
2 files changed, 6 insertions(+), 5 deletions(-)
14
15
diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/qdev-clock.h
18
--- a/target/arm/helper-mve.h
18
+++ b/include/hw/qdev-clock.h
19
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ Clock *qdev_get_clock_out(DeviceState *dev, const char *name);
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
20
* Set the source clock of input clock @name of device @dev to @source.
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
* @source period update will be propagated to @name clock.
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
*/
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
-static inline void qdev_connect_clock_in(DeviceState *dev, const char *name,
24
+
24
- Clock *source)
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
25
-{
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
26
- clock_set_source(qdev_get_clock_in(dev, name), source);
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
27
-}
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
28
+void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source);
29
30
/**
31
* qdev_alias_clock:
32
diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c
33
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/core/qdev-clock.c
30
--- a/target/arm/mve.decode
35
+++ b/hw/core/qdev-clock.c
31
+++ b/target/arm/mve.decode
36
@@ -XXX,XX +XXX,XX @@ Clock *qdev_alias_clock(DeviceState *dev, const char *name,
32
@@ -XXX,XX +XXX,XX @@
37
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
38
return ncl->clock;
34
%size_28 28:1 !function=plus_1
35
36
+# 1imm format immediate
37
+%imm_28_16_0 28:1 16:3 0:4
38
+
39
&vldr_vstr rn qd imm p a w size l u
40
&1op qd qm size
41
&2op qd qm qn size
42
&2scalar qd qn rm size
43
+&1imm qd imm cmode op
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/mve_helper.c
74
+++ b/target/arm/mve_helper.c
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
78
79
+/*
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
81
+ * All these insns work at 64-bit widths.
82
+ */
83
+#define DO_1OP_IMM(OP, FN) \
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
85
+ { \
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
93
+ }
94
+
95
+#define DO_MOVI(N, I) (I)
96
+#define DO_ANDI(N, I) ((N) & (I))
97
+#define DO_ORRI(N, I) ((N) | (I))
98
+
99
+DO_1OP_IMM(vmovi, DO_MOVI)
100
+DO_1OP_IMM(vandi, DO_ANDI)
101
+DO_1OP_IMM(vorri, DO_ORRI)
102
+
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
39
}
121
}
40
+
122
+
41
+void qdev_connect_clock_in(DeviceState *dev, const char *name, Clock *source)
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
42
+{
124
+{
43
+ clock_set_source(qdev_get_clock_in(dev, name), source);
125
+ TCGv_ptr qd;
126
+ uint64_t imm;
127
+
128
+ if (!dc_isar_feature(aa32_mve, s) ||
129
+ !mve_check_qreg_bank(s, a->qd) ||
130
+ !fn) {
131
+ return false;
132
+ }
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ return true;
135
+ }
136
+
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
138
+
139
+ qd = mve_qreg_ptr(a->qd);
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
141
+ tcg_temp_free_ptr(qd);
142
+ mve_update_eci(s);
143
+ return true;
144
+}
145
+
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
147
+{
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
150
+
151
+ if ((a->cmode & 1) && a->cmode < 12) {
152
+ if (a->op) {
153
+ /*
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
155
+ * so the VBIC becomes a logical AND operation.
156
+ */
157
+ fn = gen_helper_mve_vandi;
158
+ } else {
159
+ fn = gen_helper_mve_vorri;
160
+ }
161
+ } else {
162
+ /* There is one unallocated cmode/op combination in this space */
163
+ if (a->cmode == 15 && a->op == 1) {
164
+ return false;
165
+ }
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
167
+ fn = gen_helper_mve_vmovi;
168
+ }
169
+ return do_1imm(s, a, fn);
44
+}
170
+}
45
--
171
--
46
2.20.1
172
2.20.1
47
173
48
174
diff view generated by jsdifflib
[PULL 30/35] target/arm: Split out gen_gvec_ool_zz
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
2
and VQSHLU.
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
The size-and-immediate encoding here is the same as Neon, and we
5
Message-id: 20200815013145.539409-13-richard.henderson@linaro.org
5
handle it the same way neon-dp.decode does.
6
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
7
---
10
---
8
target/arm/translate-sve.c | 20 ++++++++++++--------
11
target/arm/helper-mve.h | 16 +++++++++++
9
1 file changed, 12 insertions(+), 8 deletions(-)
12
target/arm/mve.decode | 23 +++++++++++++++
10
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
12
index XXXXXXX..XXXXXXX 100644
15
4 files changed, 147 insertions(+)
13
--- a/target/arm/translate-sve.c
16
14
+++ b/target/arm/translate-sve.c
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
18
index XXXXXXX..XXXXXXX 100644
16
return size_for_gvec(pred_full_reg_size(s));
19
--- a/target/arm/helper-mve.h
20
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
25
+
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
17
}
173
}
18
174
+
19
+/* Invoke an out-of-line helper on 2 Zregs. */
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
20
+static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
176
+ bool negateshift)
21
+ int rd, int rn, int data)
22
+{
177
+{
23
+ unsigned vsz = vec_full_reg_size(s);
178
+ TCGv_ptr qd, qm;
24
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
179
+ int shift = a->shift;
25
+ vec_full_reg_offset(s, rn),
180
+
26
+ vsz, vsz, data, fn);
181
+ if (!dc_isar_feature(aa32_mve, s) ||
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
183
+ !fn) {
184
+ return false;
185
+ }
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
187
+ return true;
188
+ }
189
+
190
+ /*
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
194
+ */
195
+ if (negateshift) {
196
+ shift = -shift;
197
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
27
+}
206
+}
28
+
207
+
29
/* Invoke an out-of-line helper on 3 Zregs. */
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
30
static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
31
int rd, int rn, int rm, int data)
210
+ { \
32
@@ -XXX,XX +XXX,XX @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
33
return false;
212
+ gen_helper_mve_##FN##b, \
34
}
213
+ gen_helper_mve_##FN##h, \
35
if (sve_access_check(s)) {
214
+ gen_helper_mve_##FN##w, \
36
- unsigned vsz = vec_full_reg_size(s);
215
+ NULL, \
37
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
216
+ }; \
38
- vec_full_reg_offset(s, a->rn),
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
39
- vsz, vsz, 0, fns[a->esz]);
218
+ }
40
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
219
+
41
}
220
+DO_2SHIFT(VSHLI, vshli_u, false)
42
return true;
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
43
}
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
44
@@ -XXX,XX +XXX,XX @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
45
};
46
47
if (sve_access_check(s)) {
48
- unsigned vsz = vec_full_reg_size(s);
49
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
50
- vec_full_reg_offset(s, a->rn),
51
- vsz, vsz, 0, fns[a->esz]);
52
+ gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
53
}
54
return true;
55
}
56
--
224
--
57
2.20.1
225
2.20.1
58
226
59
227
diff view generated by jsdifflib
[PULL 35/35] target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-21-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
7
---
9
---
8
target/arm/helper.h | 10 ++++++++
10
target/arm/helper-mve.h | 12 ++++++++++++
9
target/arm/translate-a64.c | 33 ++++++++++++++++++--------
11
target/arm/translate.h | 20 ++++++++++++++++++++
10
target/arm/vec_helper.c | 48 ++++++++++++++++++++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
11
3 files changed, 81 insertions(+), 10 deletions(-)
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
12
17
13
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.h
20
--- a/target/arm/helper-mve.h
16
+++ b/target/arm/helper.h
21
+++ b/target/arm/helper-mve.h
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG,
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
18
DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG,
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
19
void, ptr, ptr, ptr, ptr, i32)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
20
25
21
+DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG,
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+ void, ptr, ptr, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG,
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+ void, ptr, ptr, ptr, ptr, i32)
25
+
29
+
26
+DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG,
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+ void, ptr, ptr, ptr, ptr, i32)
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG,
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+ void, ptr, ptr, ptr, ptr, i32)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+
37
+
31
#ifdef TARGET_AARCH64
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
#include "helper-a64.h"
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
#include "helper-sve.h"
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
35
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/translate-a64.c
47
--- a/target/arm/translate.h
37
+++ b/target/arm/translate-a64.c
48
+++ b/target/arm/translate.h
38
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
39
tcg_temp_free_ptr(fpst);
50
return x * 2 + 1;
40
}
51
}
41
52
42
+/* Expand a 3-operand + qc + operation using an out-of-line helper. */
53
+static inline int rsub_64(DisasContext *s, int x)
43
+static void gen_gvec_op3_qc(DisasContext *s, bool is_q, int rd, int rn,
44
+ int rm, gen_helper_gvec_3_ptr *fn)
45
+{
54
+{
46
+ TCGv_ptr qc_ptr = tcg_temp_new_ptr();
55
+ return 64 - x;
47
+
48
+ tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc));
49
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
50
+ vec_full_reg_offset(s, rn),
51
+ vec_full_reg_offset(s, rm), qc_ptr,
52
+ is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
53
+ tcg_temp_free_ptr(qc_ptr);
54
+}
56
+}
55
+
57
+
56
/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
58
+static inline int rsub_32(DisasContext *s, int x)
57
* than the 32 bit equivalent.
58
*/
59
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
60
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_mla, size);
61
}
62
return;
63
+ case 0x16: /* SQDMULH, SQRDMULH */
64
+ {
65
+ static gen_helper_gvec_3_ptr * const fns[2][2] = {
66
+ { gen_helper_neon_sqdmulh_h, gen_helper_neon_sqrdmulh_h },
67
+ { gen_helper_neon_sqdmulh_s, gen_helper_neon_sqrdmulh_s },
68
+ };
69
+ gen_gvec_op3_qc(s, is_q, rd, rn, rm, fns[size - 1][u]);
70
+ }
71
+ return;
72
case 0x11:
73
if (!u) { /* CMTST */
74
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_cmtst, size);
75
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
76
genenvfn = fns[size][u];
77
break;
78
}
79
- case 0x16: /* SQDMULH, SQRDMULH */
80
- {
81
- static NeonGenTwoOpEnvFn * const fns[2][2] = {
82
- { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
83
- { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
84
- };
85
- assert(size == 1 || size == 2);
86
- genenvfn = fns[size - 1][u];
87
- break;
88
- }
89
default:
90
g_assert_not_reached();
91
}
92
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/vec_helper.c
95
+++ b/target/arm/vec_helper.c
96
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
97
clear_tail(d, opr_sz, simd_maxsz(desc));
98
}
99
100
+void HELPER(neon_sqdmulh_h)(void *vd, void *vn, void *vm,
101
+ void *vq, uint32_t desc)
102
+{
59
+{
103
+ intptr_t i, opr_sz = simd_oprsz(desc);
60
+ return 32 - x;
104
+ int16_t *d = vd, *n = vn, *m = vm;
105
+
106
+ for (i = 0; i < opr_sz / 2; ++i) {
107
+ d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, false, vq);
108
+ }
109
+ clear_tail(d, opr_sz, simd_maxsz(desc));
110
+}
61
+}
111
+
62
+
112
+void HELPER(neon_sqrdmulh_h)(void *vd, void *vn, void *vm,
63
+static inline int rsub_16(DisasContext *s, int x)
113
+ void *vq, uint32_t desc)
114
+{
64
+{
115
+ intptr_t i, opr_sz = simd_oprsz(desc);
65
+ return 16 - x;
116
+ int16_t *d = vd, *n = vn, *m = vm;
117
+
118
+ for (i = 0; i < opr_sz / 2; ++i) {
119
+ d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, true, vq);
120
+ }
121
+ clear_tail(d, opr_sz, simd_maxsz(desc));
122
+}
66
+}
123
+
67
+
124
/* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
68
+static inline int rsub_8(DisasContext *s, int x)
125
static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
126
bool neg, bool round, uint32_t *sat)
127
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
128
clear_tail(d, opr_sz, simd_maxsz(desc));
129
}
130
131
+void HELPER(neon_sqdmulh_s)(void *vd, void *vn, void *vm,
132
+ void *vq, uint32_t desc)
133
+{
69
+{
134
+ intptr_t i, opr_sz = simd_oprsz(desc);
70
+ return 8 - x;
135
+ int32_t *d = vd, *n = vn, *m = vm;
136
+
137
+ for (i = 0; i < opr_sz / 4; ++i) {
138
+ d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, false, vq);
139
+ }
140
+ clear_tail(d, opr_sz, simd_maxsz(desc));
141
+}
71
+}
142
+
72
+
143
+void HELPER(neon_sqrdmulh_s)(void *vd, void *vn, void *vm,
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
144
+ void *vq, uint32_t desc)
74
{
145
+{
75
return (dc->features & (1ULL << feature)) != 0;
146
+ intptr_t i, opr_sz = simd_oprsz(desc);
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
147
+ int32_t *d = vd, *n = vn, *m = vm;
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/mve.decode
79
+++ b/target/arm/mve.decode
80
@@ -XXX,XX +XXX,XX @@
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
83
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
148
+
88
+
149
+ for (i = 0; i < opr_sz / 4; ++i) {
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
150
+ d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, true, vq);
90
+ size=0 shift=%rshift_i3
151
+ }
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
152
+ clear_tail(d, opr_sz, simd_maxsz(desc));
92
+ size=1 shift=%rshift_i4
153
+}
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
154
+
95
+
155
/* Integer 8 and 16-bit dot-product.
96
# Vector loads and stores
156
*
97
157
* Note that for the loops herein, host endianness does not matter
98
# Widening loads and narrowing stores:
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
163
}
164
165
-static inline int rsub_64(DisasContext *s, int x)
166
-{
167
- return 64 - x;
168
-}
169
-
170
-static inline int rsub_32(DisasContext *s, int x)
171
-{
172
- return 32 - x;
173
-}
174
-static inline int rsub_16(DisasContext *s, int x)
175
-{
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
181
-}
182
-
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
184
{
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
158
--
186
--
159
2.20.1
187
2.20.1
160
188
161
189
diff view generated by jsdifflib
[PULL 29/35] target/arm: Split out gen_gvec_ool_zzz
[PULL 15/24] target/arm: Implement MVE VSHLL
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
and the T2 encoding is a special case where the shift count is always
4
equal to the element size.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20200815013145.539409-12-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
7
---
9
---
8
target/arm/translate-sve.c | 53 +++++++++++++-------------------------
10
target/arm/helper-mve.h | 9 +++++++
9
1 file changed, 18 insertions(+), 35 deletions(-)
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
10
15
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
18
--- a/target/arm/helper-mve.h
14
+++ b/target/arm/translate-sve.c
19
+++ b/target/arm/helper-mve.h
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
16
return size_for_gvec(pred_full_reg_size(s));
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
17
}
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
+/* Invoke an out-of-line helper on 3 Zregs. */
24
+
20
+static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
+ int rd, int rn, int rm, int data)
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
40
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
43
+# VSHLL encoding T2 where shift == esize
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
45
+ qd=%qd qm=%qm size=0 shift=8
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
47
+ qd=%qd qm=%qm size=1 shift=16
48
+
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
50
%rshift_i5 16:5 !function=rsub_32
51
%rshift_i4 16:4 !function=rsub_16
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
55
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
59
+# overlaps what would be size=0b11 VMULH/VRMULH
22
+{
60
+{
23
+ unsigned vsz = vec_full_reg_size(s);
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
24
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
25
+ vec_full_reg_offset(s, rn),
63
26
+ vec_full_reg_offset(s, rm),
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
27
+ vsz, vsz, data, fn);
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
28
+}
67
+}
29
+
68
+
30
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
69
+{
31
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
32
int rd, int rn, int pg, int data)
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
33
@@ -XXX,XX +XXX,XX @@ static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
72
+
34
return false;
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
35
}
74
+}
36
if (sve_access_check(s)) {
75
+
37
- unsigned vsz = vec_full_reg_size(s);
76
+{
38
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
39
- vec_full_reg_offset(s, a->rn),
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
40
- vec_full_reg_offset(s, a->rm),
79
+
41
- vsz, vsz, 0, fn);
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
42
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
81
+}
43
}
82
+
44
return true;
83
+{
45
}
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
46
@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
47
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
86
+
48
{
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
49
if (sve_access_check(s)) {
88
+}
50
- unsigned vsz = vec_full_reg_size(s);
89
51
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
52
- vec_full_reg_offset(s, a->rn),
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
53
- vec_full_reg_offset(s, a->rm),
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
54
- vsz, vsz, a->imm, fn);
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
55
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
56
}
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
57
return true;
96
+
58
}
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
59
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
60
return false;
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
61
}
100
+
62
if (sve_access_check(s)) {
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
63
- unsigned vsz = vec_full_reg_size(s);
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
64
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
103
+
65
- vec_full_reg_offset(s, a->rn),
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
66
- vec_full_reg_offset(s, a->rm),
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
67
- vsz, vsz, 0, fns[a->esz]);
106
+
68
+ gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
69
}
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
70
return true;
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
71
}
110
index XXXXXXX..XXXXXXX 100644
72
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
111
--- a/target/arm/mve_helper.c
73
};
112
+++ b/target/arm/mve_helper.c
74
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
75
if (sve_access_check(s)) {
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
76
- unsigned vsz = vec_full_reg_size(s);
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
77
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
78
- vec_full_reg_offset(s, a->rn),
117
+
79
- vec_full_reg_offset(s, a->rm),
118
+/*
80
- vsz, vsz, 0, fns[a->esz]);
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
81
+ gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
82
}
121
+ * the input, and LESIZE, LTYPE for the output.
83
return true;
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
84
}
123
+ * because the long shift is strictly left-only.
85
@@ -XXX,XX +XXX,XX @@ static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
124
+ */
86
gen_helper_gvec_3 *fn)
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
87
{
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
88
if (sve_access_check(s)) {
127
+ void *vm, uint32_t shift) \
89
- unsigned vsz = vec_full_reg_size(s);
128
+ { \
90
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
129
+ LTYPE *d = vd; \
91
- vec_full_reg_offset(s, a->rn),
130
+ TYPE *m = vm; \
92
- vec_full_reg_offset(s, a->rm),
131
+ uint16_t mask = mve_element_mask(env); \
93
- vsz, vsz, data, fn);
132
+ unsigned le; \
94
+ gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
133
+ assert(shift <= 16); \
95
}
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
96
return true;
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
97
}
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
98
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzz(DisasContext *s, arg_DOT_zzz *a)
137
+ } \
99
};
138
+ mve_advance_vpt(env); \
100
139
+ }
101
if (sve_access_check(s)) {
140
+
102
- unsigned vsz = vec_full_reg_size(s);
141
+#define DO_VSHLL_ALL(OP, TOP) \
103
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
104
- vec_full_reg_offset(s, a->rn),
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
105
- vec_full_reg_offset(s, a->rm),
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
106
- vsz, vsz, 0, fns[a->u][a->sz]);
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
107
+ gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, 0);
146
+
108
}
147
+DO_VSHLL_ALL(vshllb, false)
109
return true;
148
+DO_VSHLL_ALL(vshllt, true)
110
}
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
111
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzx(DisasContext *s, arg_DOT_zzx *a)
150
index XXXXXXX..XXXXXXX 100644
112
};
151
--- a/target/arm/translate-mve.c
113
152
+++ b/target/arm/translate-mve.c
114
if (sve_access_check(s)) {
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
115
- unsigned vsz = vec_full_reg_size(s);
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
116
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
117
- vec_full_reg_offset(s, a->rn),
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
118
- vec_full_reg_offset(s, a->rm),
157
+
119
- vsz, vsz, a->index, fns[a->u][a->sz]);
158
+#define DO_VSHLL(INSN, FN) \
120
+ gen_gvec_ool_zzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->index);
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
121
}
160
+ { \
122
return true;
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
123
}
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
167
+
168
+DO_VSHLL(VSHLL_BS, vshllbs)
169
+DO_VSHLL(VSHLL_BU, vshllbu)
170
+DO_VSHLL(VSHLL_TS, vshllts)
171
+DO_VSHLL(VSHLL_TU, vshlltu)
124
--
172
--
125
2.20.1
173
2.20.1
126
174
127
175
diff view generated by jsdifflib
[PULL 07/35] target/arm: Pass the entire mte descriptor to mte_check_fail
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE VSRI and VSLI insns, which perform a
2
shift-and-insert operation.
2
3
3
We need more information than just the mmu_idx in order
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
to create the proper exception syndrome. Only change the
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
function signature so far.
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
7
---
8
target/arm/helper-mve.h | 8 ++++++++
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
6
13
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
Message-id: 20200813200816.3037186-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/mte_helper.c | 10 +++++-----
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
15
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/mte_helper.c
16
--- a/target/arm/helper-mve.h
18
+++ b/target/arm/mte_helper.c
17
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
}
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
/* Record a tag check failure. */
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
-static void mte_check_fail(CPUARMState *env, int mmu_idx,
22
+
24
+static void mte_check_fail(CPUARMState *env, uint32_t desc,
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
uint64_t dirty_ptr, uintptr_t ra)
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
{
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+ int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
26
+
28
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
int el, reg_el, tcf, select;
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
uint64_t sctlr;
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
@@ -XXX,XX +XXX,XX @@ uint64_t mte_check1(CPUARMState *env, uint32_t desc,
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
32
}
31
index XXXXXXX..XXXXXXX 100644
33
32
--- a/target/arm/mve.decode
34
if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) {
33
+++ b/target/arm/mve.decode
35
- int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
36
- mte_check_fail(env, mmu_idx, ptr, ra);
35
37
+ mte_check_fail(env, desc, ptr, ra);
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
38
}
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
39
38
+
40
return useronly_clean_ptr(ptr);
39
+# Shift-and-insert
41
@@ -XXX,XX +XXX,XX @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc,
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
42
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
43
fail_ofs = tag_first + n * TAG_GRANULE - ptr;
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
44
fail_ofs = ROUND_UP(fail_ofs, esize);
43
+
45
- mte_check_fail(env, mmu_idx, ptr + fail_ofs, ra);
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
46
+ mte_check_fail(env, desc, ptr + fail_ofs, ra);
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
47
}
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
48
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
49
done:
48
index XXXXXXX..XXXXXXX 100644
50
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr)
49
--- a/target/arm/mve_helper.c
51
fail:
50
+++ b/target/arm/mve_helper.c
52
/* Locate the first nibble that differs. */
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
53
i = ctz64(mem_tag ^ ptr_tag) >> 4;
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
54
- mte_check_fail(env, mmu_idx, align_ptr + i * TAG_GRANULE, ra);
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
55
+ mte_check_fail(env, desc, align_ptr + i * TAG_GRANULE, ra);
54
56
55
+/* Shift-and-insert; we always work with 64 bits at a time */
57
done:
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
58
return useronly_clean_ptr(ptr);
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
59
--
114
--
60
2.20.1
115
2.20.1
61
116
62
117
diff view generated by jsdifflib
[PULL 28/35] target/arm: Split out gen_gvec_ool_zzp
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
2
3
Model after gen_gvec_fn_zzz et al.
3
do_urshr() is borrowed from sve_helper.c.
4
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-11-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
9
---
8
---
10
target/arm/translate-sve.c | 29 ++++++++++++++---------------
9
target/arm/helper-mve.h | 10 ++++++++++
11
1 file changed, 14 insertions(+), 15 deletions(-)
10
target/arm/mve.decode | 11 +++++++++++
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
12
14
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
17
--- a/target/arm/helper-mve.h
16
+++ b/target/arm/translate-sve.c
18
+++ b/target/arm/helper-mve.h
17
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
return size_for_gvec(pred_full_reg_size(s));
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
}
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
+/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
23
+
22
+static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+ int rd, int rn, int pg, int data)
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/mve.decode
36
+++ b/target/arm/mve.decode
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
41
+
42
+# Narrowing shifts (which only support b and h sizes)
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
47
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
61
+/*
62
+ * Narrowing right shifts, taking a double sized input, shifting it
63
+ * and putting the result in either the top or bottom half of the output.
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
65
+ */
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
68
+ void *vm, uint32_t shift) \
69
+ { \
70
+ LTYPE *m = vm; \
71
+ TYPE *d = vd; \
72
+ uint16_t mask = mve_element_mask(env); \
73
+ unsigned le; \
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
79
+ }
80
+
81
+#define DO_VSHRN_ALL(OP, FN) \
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
86
+
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
24
+{
88
+{
25
+ unsigned vsz = vec_full_reg_size(s);
89
+ if (likely(sh < 64)) {
26
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
27
+ vec_full_reg_offset(s, rn),
91
+ } else if (sh == 64) {
28
+ pred_full_reg_offset(s, pg),
92
+ return x >> 63;
29
+ vsz, vsz, data, fn);
93
+ } else {
94
+ return 0;
95
+ }
30
+}
96
+}
31
+
97
+
32
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
33
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
34
int rd, int rn, int rm, int pg, int data)
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
35
@@ -XXX,XX +XXX,XX @@ static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
101
index XXXXXXX..XXXXXXX 100644
36
return false;
102
--- a/target/arm/translate-mve.c
37
}
103
+++ b/target/arm/translate-mve.c
38
if (sve_access_check(s)) {
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
39
- unsigned vsz = vec_full_reg_size(s);
105
DO_VSHLL(VSHLL_BU, vshllbu)
40
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
106
DO_VSHLL(VSHLL_TS, vshllts)
41
- vec_full_reg_offset(s, a->rn),
107
DO_VSHLL(VSHLL_TU, vshlltu)
42
- pred_full_reg_offset(s, a->pg),
108
+
43
- vsz, vsz, 0, fn);
109
+#define DO_2SHIFT_N(INSN, FN) \
44
+ gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
45
}
111
+ { \
46
return true;
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
47
}
113
+ gen_helper_mve_##FN##b, \
48
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
114
+ gen_helper_mve_##FN##h, \
49
};
115
+ }; \
50
116
+ return do_2shift(s, a, fns[a->size], false); \
51
if (sve_access_check(s)) {
117
+ }
52
- unsigned vsz = vec_full_reg_size(s);
118
+
53
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
54
- vec_full_reg_offset(s, rn),
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
55
- pred_full_reg_offset(s, pg),
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
56
- vsz, vsz, invert, fns[esz]);
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
57
+ gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
58
}
59
return true;
60
}
61
@@ -XXX,XX +XXX,XX @@ static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
62
gen_helper_gvec_3 *fn)
63
{
64
if (sve_access_check(s)) {
65
- unsigned vsz = vec_full_reg_size(s);
66
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
67
- vec_full_reg_offset(s, a->rn),
68
- pred_full_reg_offset(s, a->pg),
69
- vsz, vsz, a->imm, fn);
70
+ gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
71
}
72
return true;
73
}
74
--
123
--
75
2.20.1
124
2.20.1
76
125
77
126
diff view generated by jsdifflib
[PULL 19/35] qemu/int128: Add int128_lshift
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE saturating shift-right-and-narrow insns
2
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
Add left-shift to match the existing right-shift.
3
4
4
do_srshr() is borrowed from sve_helper.c.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
9
---
9
---
10
include/qemu/int128.h | 16 ++++++++++++++++
10
target/arm/helper-mve.h | 30 +++++++++++
11
1 file changed, 16 insertions(+)
11
target/arm/mve.decode | 28 ++++++++++
12
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
13
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
13
target/arm/translate-mve.c | 12 +++++
14
index XXXXXXX..XXXXXXX 100644
14
4 files changed, 174 insertions(+)
15
--- a/include/qemu/int128.h
15
16
+++ b/include/qemu/int128.h
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_rshift(Int128 a, int n)
17
index XXXXXXX..XXXXXXX 100644
18
return a >> n;
18
--- a/target/arm/helper-mve.h
19
}
19
+++ b/target/arm/helper-mve.h
20
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
+static inline Int128 int128_lshift(Int128 a, int n)
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+{
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+ return a << n;
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+}
24
+
25
+
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
static inline Int128 int128_add(Int128 a, Int128 b)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
{
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
return a + b;
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
@@ -XXX,XX +XXX,XX @@ static inline Int128 int128_rshift(Int128 a, int n)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
57
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
62
+
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
30
}
95
}
31
}
96
}
32
97
33
+static inline Int128 int128_lshift(Int128 a, int n)
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
34
+{
99
+{
35
+ uint64_t l = a.lo << (n & 63);
100
+ if (likely(sh < 64)) {
36
+ if (n >= 64) {
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
37
+ return int128_make128(0, l);
102
+ } else {
38
+ } else if (n > 0) {
103
+ /* Rounding the sign bit always produces 0. */
39
+ return int128_make128(l, (a.hi << n) | (a.lo >> (64 - n)));
104
+ return 0;
40
+ }
105
+ }
41
+ return a;
42
+}
106
+}
43
+
107
+
44
static inline Int128 int128_add(Int128 a, Int128 b)
108
DO_VSHRN_ALL(vshrn, DO_SHR)
45
{
109
DO_VSHRN_ALL(vrshrn, do_urshr)
46
uint64_t lo = a.lo + b.lo;
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
113
+{
114
+ if (val > max) {
115
+ *satp = true;
116
+ return max;
117
+ } else if (val < min) {
118
+ *satp = true;
119
+ return min;
120
+ } else {
121
+ return val;
122
+ }
123
+}
124
+
125
+/* Saturating narrowing right shifts */
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
128
+ void *vm, uint32_t shift) \
129
+ { \
130
+ LTYPE *m = vm; \
131
+ TYPE *d = vd; \
132
+ uint16_t mask = mve_element_mask(env); \
133
+ bool qc = false; \
134
+ unsigned le; \
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
136
+ bool sat = false; \
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
140
+ } \
141
+ if (qc) { \
142
+ env->vfp.qc[0] = qc; \
143
+ } \
144
+ mve_advance_vpt(env); \
145
+ }
146
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
150
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
154
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
47
--
224
--
48
2.20.1
225
2.20.1
49
226
50
227
diff view generated by jsdifflib
[PULL 03/35] hw/clock: Let clock_set() return boolean value
[PULL 19/24] target/arm: Implement MVE VSHLC
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
entire vector with carry in bits provided from a general purpose
3
register and carry out bits written back to that register.
2
4
3
Let clock_set() return a boolean value whether the clock
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
has been updated or not.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 2 ++
10
target/arm/mve.decode | 2 ++
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
5
14
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200806123858.30058-3-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/clock.h | 12 +++++++-----
12
hw/core/clock.c | 7 ++++++-
13
2 files changed, 13 insertions(+), 6 deletions(-)
14
15
diff --git a/include/hw/clock.h b/include/hw/clock.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/clock.h
17
--- a/target/arm/helper-mve.h
18
+++ b/include/hw/clock.h
18
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ void clock_set_source(Clock *clk, Clock *src);
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
* @value: the clock's value, 0 means unclocked
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
*
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
* Set the local cached period value of @clk to @value.
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+ *
23
+
24
+ * @return: true if the clock is changed.
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
25
*/
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
26
-void clock_set(Clock *clk, uint64_t value);
27
+bool clock_set(Clock *clk, uint64_t value);
28
29
-static inline void clock_set_hz(Clock *clk, unsigned hz)
30
+static inline bool clock_set_hz(Clock *clk, unsigned hz)
31
{
32
- clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
33
+ return clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz));
34
}
35
36
-static inline void clock_set_ns(Clock *clk, unsigned ns)
37
+static inline bool clock_set_ns(Clock *clk, unsigned ns)
38
{
39
- clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
40
+ return clock_set(clk, CLOCK_PERIOD_FROM_NS(ns));
41
}
42
43
/**
44
diff --git a/hw/core/clock.c b/hw/core/clock.c
45
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/core/clock.c
27
--- a/target/arm/mve.decode
47
+++ b/hw/core/clock.c
28
+++ b/target/arm/mve.decode
48
@@ -XXX,XX +XXX,XX @@ void clock_clear_callback(Clock *clk)
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
49
clock_set_callback(clk, NULL, NULL);
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
50
}
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
51
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
52
-void clock_set(Clock *clk, uint64_t period)
33
+
53
+bool clock_set(Clock *clk, uint64_t period)
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
54
{
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
55
+ if (clk->period == period) {
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/mve_helper.c
38
+++ b/target/arm/mve_helper.c
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
43
+
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
+ uint32_t shift)
46
+{
47
+ uint32_t *d = vd;
48
+ uint16_t mask = mve_element_mask(env);
49
+ unsigned e;
50
+ uint32_t r;
51
+
52
+ /*
53
+ * For each 32-bit element, we shift it left, bringing in the
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
55
+ * the top become the new rdm, if the predicate mask permits.
56
+ * The final rdm value is returned to update the register.
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
67
+ } else {
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
69
+
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
76
+ }
77
+ }
78
+ mve_advance_vpt(env);
79
+ return rdm;
80
+}
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
82
index XXXXXXX..XXXXXXX 100644
83
--- a/target/arm/translate-mve.c
84
+++ b/target/arm/translate-mve.c
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
89
+
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
91
+{
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
99
+
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
56
+ return false;
101
+ return false;
57
+ }
102
+ }
58
trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period),
103
+ if (a->rdm == 13 || a->rdm == 15) {
59
CLOCK_PERIOD_TO_NS(period));
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
60
clk->period = period;
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
109
+ }
61
+
110
+
111
+ qd = mve_qreg_ptr(a->qd);
112
+ rdm = load_reg(s, a->rdm);
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
114
+ store_reg(s, a->rdm, rdm);
115
+ tcg_temp_free_ptr(qd);
116
+ mve_update_eci(s);
62
+ return true;
117
+ return true;
63
}
118
+}
64
65
static void clock_propagate_period(Clock *clk, bool call_callbacks)
66
--
119
--
67
2.20.1
120
2.20.1
68
121
69
122
diff view generated by jsdifflib
[PULL 06/35] target/arm: Clarify HCR_EL2 ARMCPRegInfo type
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
In commit ce4afed839 ("target/arm: Implement AArch32 HCR and HCR2")
4
the HCR_EL2 register has been changed from type NO_RAW (no underlying
5
state and does not support raw access for state saving/loading) to
6
type CONST (TCG can assume the value to be constant), removing the
7
read/write accessors.
8
We forgot to remove the previous type ARM_CP_NO_RAW. This is not
9
really a problem since the field is overwritten. However it makes
10
code review confuse, so remove it.
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20200812111223.7787-1-f4bug@amsat.org
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
target/arm/helper.c | 1 -
19
1 file changed, 1 deletion(-)
20
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
24
+++ b/target/arm/helper.c
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
26
.access = PL2_RW,
27
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
28
{ .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH,
29
- .type = ARM_CP_NO_RAW,
30
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
31
.access = PL2_RW,
32
.type = ARM_CP_CONST, .resetvalue = 0 },
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
[PULL 08/35] target/arm: Fill in the WnR syndrome bit in mte_check_fail
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
According to AArch64.TagCheckFault, none of the other ISS values are
4
provided, so we do not need to go so far as merge_syn_data_abort.
5
But we were missing the WnR bit.
6
7
Tested-by: Andrey Konovalov <andreyknvl@google.com>
8
Reported-by: Andrey Konovalov <andreyknvl@google.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200813200816.3037186-3-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/mte_helper.c | 9 +++++----
15
1 file changed, 5 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/mte_helper.c
20
+++ b/target/arm/mte_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
22
{
23
int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
24
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
25
- int el, reg_el, tcf, select;
26
+ int el, reg_el, tcf, select, is_write, syn;
27
uint64_t sctlr;
28
29
reg_el = regime_el(env, arm_mmu_idx);
30
@@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
31
*/
32
cpu_restore_state(env_cpu(env), ra, true);
33
env->exception.vaddress = dirty_ptr;
34
- raise_exception(env, EXCP_DATA_ABORT,
35
- syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0, 0x11),
36
- exception_target_el(env));
37
+
38
+ is_write = FIELD_EX32(desc, MTEDESC, WRITE);
39
+ syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11);
40
+ raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));
41
/* noreturn, but fall through to the assert anyway */
42
43
case 0:
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
[PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
[PULL 20/24] target/arm: Implement MVE VADDLV
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
stored in a pair of general-purpose registers.
2
4
3
Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
indicating which kind of register and in which order.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 3 ++
10
target/arm/mve.decode | 6 +++-
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
5
14
6
Model do_zzz_fn on the other do_foo functions that take an
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
argument set and verify sve enabled.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20200815013145.539409-4-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate-sve.c | 43 +++++++++++++++++++++-----------------
15
1 file changed, 24 insertions(+), 19 deletions(-)
16
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
17
--- a/target/arm/helper-mve.h
20
+++ b/target/arm/translate-sve.c
18
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
25
+
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/mve.decode
32
+++ b/target/arm/mve.decode
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
22
}
82
}
23
83
24
/* Invoke a vector expander on three Zregs. */
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
25
-static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
26
- int esz, int rd, int rn, int rm)
27
+static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
28
+ int esz, int rd, int rn, int rm)
29
{
30
- if (sve_access_check(s)) {
31
- unsigned vsz = vec_full_reg_size(s);
32
- gvec_fn(esz, vec_full_reg_offset(s, rd),
33
- vec_full_reg_offset(s, rn),
34
- vec_full_reg_offset(s, rm), vsz, vsz);
35
- }
36
- return true;
37
+ unsigned vsz = vec_full_reg_size(s);
38
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
39
+ vec_full_reg_offset(s, rn),
40
+ vec_full_reg_offset(s, rm), vsz, vsz);
41
}
42
43
/* Invoke a vector move on two Zregs. */
44
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
45
*** SVE Logical - Unpredicated Group
46
*/
47
48
+static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
49
+{
85
+{
50
+ if (sve_access_check(s)) {
86
+ /*
51
+ gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
88
+ * elements of the vector into a 64-bit result stored in
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
91
+ */
92
+ TCGv_ptr qm;
93
+ TCGv_i64 rda;
94
+ TCGv_i32 rdalo, rdahi;
95
+
96
+ if (!dc_isar_feature(aa32_mve, s)) {
97
+ return false;
52
+ }
98
+ }
99
+ /*
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
102
+ */
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
104
+ return false;
105
+ }
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
107
+ return true;
108
+ }
109
+
110
+ /*
111
+ * This insn is subject to beat-wise execution. Partial execution
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
114
+ */
115
+ if (a->a || mve_skip_first_beat(s)) {
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
126
+ }
127
+
128
+ qm = mve_qreg_ptr(a->qm);
129
+ if (a->u) {
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
135
+
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
53
+ return true;
144
+ return true;
54
+}
145
+}
55
+
146
+
56
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
57
{
148
{
58
- return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
149
TCGv_ptr qd;
59
+ return do_zzz_fn(s, a, tcg_gen_gvec_and);
60
}
61
62
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
63
{
64
- return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
65
+ return do_zzz_fn(s, a, tcg_gen_gvec_or);
66
}
67
68
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
69
{
70
- return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
71
+ return do_zzz_fn(s, a, tcg_gen_gvec_xor);
72
}
73
74
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
75
{
76
- return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
77
+ return do_zzz_fn(s, a, tcg_gen_gvec_andc);
78
}
79
80
/*
81
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
82
83
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
84
{
85
- return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
86
+ return do_zzz_fn(s, a, tcg_gen_gvec_add);
87
}
88
89
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
90
{
91
- return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
92
+ return do_zzz_fn(s, a, tcg_gen_gvec_sub);
93
}
94
95
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
96
{
97
- return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
98
+ return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
99
}
100
101
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
102
{
103
- return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
104
+ return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
105
}
106
107
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
108
{
109
- return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
110
+ return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
111
}
112
113
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
114
{
115
- return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
116
+ return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
117
}
118
119
/*
120
--
150
--
121
2.20.1
151
2.20.1
122
152
123
153
diff view generated by jsdifflib
[PULL 26/35] target/arm: Split out gen_gvec_ool_zzzp
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The MVE extension to v8.1M includes some new shift instructions which
2
2
sit entirely within the non-coprocessor part of the encoding space
3
Model after gen_gvec_fn_zzz et al.
3
and which operate only on general-purpose registers. They take up
4
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
with Rm == 13 or 15.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
7
Message-id: 20200815013145.539409-9-richard.henderson@linaro.org
7
Implement the long shifts by immediate, which perform shifts on a
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
an immediate shift count between 1 and 32.
10
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
23
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
9
---
27
---
10
target/arm/translate-sve.c | 35 ++++++++++++++++-------------------
28
target/arm/helper-mve.h | 3 ++
11
1 file changed, 16 insertions(+), 19 deletions(-)
29
target/arm/translate.h | 1 +
12
30
target/arm/t32.decode | 28 +++++++++++++
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
31
target/arm/mve_helper.c | 10 +++++
14
index XXXXXXX..XXXXXXX 100644
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
15
--- a/target/arm/translate-sve.c
33
5 files changed, 132 insertions(+)
16
+++ b/target/arm/translate-sve.c
34
17
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
18
return size_for_gvec(pred_full_reg_size(s));
36
index XXXXXXX..XXXXXXX 100644
19
}
37
--- a/target/arm/helper-mve.h
20
38
+++ b/target/arm/helper-mve.h
21
-/* Invoke a vector expander on two Zregs. */
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
+/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
41
24
+ int rd, int rn, int rm, int pg, int data)
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
25
+{
43
+
26
+ unsigned vsz = vec_full_reg_size(s);
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
27
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
28
+ vec_full_reg_offset(s, rn),
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
29
+ vec_full_reg_offset(s, rm),
47
index XXXXXXX..XXXXXXX 100644
30
+ pred_full_reg_offset(s, pg),
48
--- a/target/arm/translate.h
31
+ vsz, vsz, data, fn);
49
+++ b/target/arm/translate.h
32
+}
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
33
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
34
+/* Invoke a vector expander on two Zregs. */
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
35
static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
36
int esz, int rd, int rn)
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
62
@@ -XXX,XX +XXX,XX @@
63
&mcr !extern cp opc1 crn crm opc2 rt
64
&mcrr !extern cp opc1 crm rt rt2
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
37
{
83
{
38
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
39
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
40
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
41
{
88
{
42
- unsigned vsz = vec_full_reg_size(s);
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
43
if (fn == NULL) {
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
44
return false;
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
45
}
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
46
if (sve_access_check(s)) {
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
47
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
48
- vec_full_reg_offset(s, a->rn),
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
49
- vec_full_reg_offset(s, a->rm),
96
+ [
50
- pred_full_reg_offset(s, a->pg),
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
51
- vsz, vsz, 0, fn);
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
52
+ gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
53
}
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
54
return true;
133
return true;
55
}
134
}
56
@@ -XXX,XX +XXX,XX @@ static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
135
57
gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
136
+/*
58
gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
137
+ * v8.1M MVE wide-shifts
59
};
138
+ */
60
- unsigned vsz = vec_full_reg_size(s);
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
61
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
140
+ WideShiftImmFn *fn)
62
- vec_full_reg_offset(s, rn),
141
+{
63
- vec_full_reg_offset(s, rm),
142
+ TCGv_i64 rda;
64
- pred_full_reg_offset(s, pg),
143
+ TCGv_i32 rdalo, rdahi;
65
- vsz, vsz, 0, fns[esz]);
144
+
66
+ gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
67
}
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
68
147
+ return false;
69
#define DO_ZPZZ(NAME, name) \
148
+ }
70
@@ -XXX,XX +XXX,XX @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
149
+ if (a->rdahi == 15) {
71
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
72
{
151
+ return false;
73
if (sve_access_check(s)) {
152
+ }
74
- unsigned vsz = vec_full_reg_size(s);
153
+ if (!dc_isar_feature(aa32_mve, s) ||
75
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
76
- vec_full_reg_offset(s, a->rn),
155
+ a->rdahi == 13) {
77
- vec_full_reg_offset(s, a->rm),
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
78
- pred_full_reg_offset(s, a->pg),
157
+ unallocated_encoding(s);
79
- vsz, vsz, a->esz, gen_helper_sve_splice);
158
+ return true;
80
+ gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
159
+ }
81
+ a->rd, a->rn, a->rm, a->pg, 0);
160
+
82
}
161
+ if (a->shim == 0) {
83
return true;
162
+ a->shim = 32;
84
}
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
226
/*
227
* Multiply and multiply accumulate
228
*/
85
--
229
--
86
2.20.1
230
2.20.1
87
231
88
232
diff view generated by jsdifflib
[PULL 24/35] target/arm: Clean up 4-operand predicate expansion
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the MVE long shifts by register, which perform shifts on a
2
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
Move the check for !S into do_pppp_flags, which allows to merge in
3
the shift count in another general-purpose register, which might be
4
do_vecop4_p. Split out gen_gvec_fn_ppp without sve_access_check,
4
either positive or negative.
5
to mirror gen_gvec_fn_zzz.
5
6
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
Message-id: 20200815013145.539409-7-richard.henderson@linaro.org
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
11
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
11
---
15
---
12
target/arm/translate-sve.c | 111 ++++++++++++++-----------------------
16
target/arm/helper-mve.h | 6 +++
13
1 file changed, 43 insertions(+), 68 deletions(-)
17
target/arm/translate.h | 1 +
14
18
target/arm/t32.decode | 16 +++++--
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
16
index XXXXXXX..XXXXXXX 100644
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
17
--- a/target/arm/translate-sve.c
21
5 files changed, 182 insertions(+), 3 deletions(-)
18
+++ b/target/arm/translate-sve.c
22
19
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
20
}
24
index XXXXXXX..XXXXXXX 100644
21
25
--- a/target/arm/helper-mve.h
22
/* Invoke a vector expander on three Pregs. */
26
+++ b/target/arm/helper-mve.h
23
-static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
- int esz, int rd, int rn, int rm)
28
25
+static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
26
+ int rd, int rn, int rm)
30
27
{
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
28
- if (sve_access_check(s)) {
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
29
- unsigned psz = pred_gvec_reg_size(s);
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
30
- gvec_fn(esz, pred_full_reg_offset(s, rd),
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
- pred_full_reg_offset(s, rn),
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
32
- pred_full_reg_offset(s, rm), psz, psz);
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
33
- }
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
34
- return true;
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
35
-}
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate.h
42
+++ b/target/arm/translate.h
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
48
49
/**
50
* arm_tbflags_from_tb:
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
54
+++ b/target/arm/t32.decode
55
@@ -XXX,XX +XXX,XX @@
56
&mcrr !extern cp opc1 crm rt rt2
57
58
&mve_shl_ri rdalo rdahi shim
59
+&mve_shl_rr rdalo rdahi rm
60
61
# rdahi: bits [3:1] from insn, bit 0 is 1
62
# rdalo: bits [3:1] from insn, bit 0 is 0
63
@@ -XXX,XX +XXX,XX @@
64
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
69
70
{
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
76
+
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
83
]
84
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
87
+
88
+ # v8.1M CSEL and friends
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
90
}
91
{
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
94
}
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
96
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
36
-
99
-
37
-/* Invoke a vector operation on four Pregs. */
100
# Data-processing (register-shifted register)
38
-static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op,
101
39
- int rd, int rn, int rm, int rg)
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
40
-{
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
41
- if (sve_access_check(s)) {
104
index XXXXXXX..XXXXXXX 100644
42
- unsigned psz = pred_gvec_reg_size(s);
105
--- a/target/arm/mve_helper.c
43
- tcg_gen_gvec_4(pred_full_reg_offset(s, rd),
106
+++ b/target/arm/mve_helper.c
44
- pred_full_reg_offset(s, rn),
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
45
- pred_full_reg_offset(s, rm),
108
return rdm;
46
- pred_full_reg_offset(s, rg),
109
}
47
- psz, psz, gvec_op);
110
48
- }
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
49
- return true;
112
+{
50
+ unsigned psz = pred_gvec_reg_size(s);
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
51
+ gvec_fn(MO_64, pred_full_reg_offset(s, rd),
114
+}
52
+ pred_full_reg_offset(s, rn),
115
+
53
+ pred_full_reg_offset(s, rm), psz, psz);
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
54
}
117
+{
55
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
56
/* Invoke a vector move on two Pregs. */
119
+}
57
@@ -XXX,XX +XXX,XX @@ static bool do_pppp_flags(DisasContext *s, arg_rprr_s *a,
120
+
58
int mofs = pred_full_reg_offset(s, a->rm);
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
59
int gofs = pred_full_reg_offset(s, a->pg);
122
{
60
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
61
+ if (!a->s) {
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
62
+ tcg_gen_gvec_4(dofs, nofs, mofs, gofs, psz, psz, gvec_op);
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
217
}
218
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
220
+{
221
+ TCGv_i64 rda;
222
+ TCGv_i32 rdalo, rdahi;
223
+
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
226
+ return false;
227
+ }
228
+ if (a->rdahi == 15) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
230
+ return false;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
63
+ return true;
238
+ return true;
64
+ }
239
+ }
65
+
240
+
66
if (psz == 8) {
241
+ rda = tcg_temp_new_i64();
67
/* Do the operation and the flags generation in temps. */
242
+ rdalo = load_reg(s, a->rdalo);
68
TCGv_i64 pd = tcg_temp_new_i64();
243
+ rdahi = load_reg(s, a->rdahi);
69
@@ -XXX,XX +XXX,XX @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
70
.fno = gen_helper_sve_and_pppp,
245
+
71
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
72
};
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
73
- if (a->s) {
248
+
74
- return do_pppp_flags(s, a, &op);
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
75
- } else if (a->rn == a->rm) {
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
76
- if (a->pg == a->rn) {
251
+ store_reg(s, a->rdalo, rdalo);
77
- return do_mov_p(s, a->rd, a->rn);
252
+ store_reg(s, a->rdahi, rdahi);
78
- } else {
253
+ tcg_temp_free_i64(rda);
79
- return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->pg);
254
+
80
+
255
+ return true;
81
+ if (!a->s) {
256
+}
82
+ if (!sve_access_check(s)) {
257
+
83
+ return true;
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
84
+ }
259
+{
85
+ if (a->rn == a->rm) {
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
86
+ if (a->pg == a->rn) {
261
+}
87
+ do_mov_p(s, a->rd, a->rn);
262
+
88
+ } else {
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
89
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
264
+{
90
+ }
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
91
+ return true;
266
+}
92
+ } else if (a->pg == a->rn || a->pg == a->rm) {
267
+
93
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
94
+ return true;
269
+{
95
}
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
96
- } else if (a->pg == a->rn || a->pg == a->rm) {
271
+}
97
- return do_vector3_p(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
272
+
98
- } else {
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
99
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
274
+{
100
}
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
101
+ return do_pppp_flags(s, a, &op);
276
+}
102
}
277
+
103
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
104
static void gen_bic_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
279
+{
105
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
106
.fno = gen_helper_sve_bic_pppp,
281
+}
107
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
282
+
108
};
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
109
- if (a->s) {
284
+{
110
- return do_pppp_flags(s, a, &op);
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
111
- } else if (a->pg == a->rn) {
286
+}
112
- return do_vector3_p(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
287
+
113
- } else {
114
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
115
+
116
+ if (!a->s && a->pg == a->rn) {
117
+ if (sve_access_check(s)) {
118
+ gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
119
+ }
120
+ return true;
121
}
122
+ return do_pppp_flags(s, a, &op);
123
}
124
125
static void gen_eor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
126
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
127
.fno = gen_helper_sve_eor_pppp,
128
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
129
};
130
- if (a->s) {
131
- return do_pppp_flags(s, a, &op);
132
- } else {
133
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
134
- }
135
+ return do_pppp_flags(s, a, &op);
136
}
137
138
static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
139
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
140
.fno = gen_helper_sve_sel_pppp,
141
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
142
};
143
+
144
if (a->s) {
145
return false;
146
- } else {
147
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
148
}
149
+ return do_pppp_flags(s, a, &op);
150
}
151
152
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
153
@@ -XXX,XX +XXX,XX @@ static bool trans_ORR_pppp(DisasContext *s, arg_rprr_s *a)
154
.fno = gen_helper_sve_orr_pppp,
155
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
156
};
157
- if (a->s) {
158
- return do_pppp_flags(s, a, &op);
159
- } else if (a->pg == a->rn && a->rn == a->rm) {
160
+
161
+ if (!a->s && a->pg == a->rn && a->rn == a->rm) {
162
return do_mov_p(s, a->rd, a->rn);
163
- } else {
164
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
165
}
166
+ return do_pppp_flags(s, a, &op);
167
}
168
169
static void gen_orn_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
170
@@ -XXX,XX +XXX,XX @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr_s *a)
171
.fno = gen_helper_sve_orn_pppp,
172
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
173
};
174
- if (a->s) {
175
- return do_pppp_flags(s, a, &op);
176
- } else {
177
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
178
- }
179
+ return do_pppp_flags(s, a, &op);
180
}
181
182
static void gen_nor_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
183
@@ -XXX,XX +XXX,XX @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr_s *a)
184
.fno = gen_helper_sve_nor_pppp,
185
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
186
};
187
- if (a->s) {
188
- return do_pppp_flags(s, a, &op);
189
- } else {
190
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
191
- }
192
+ return do_pppp_flags(s, a, &op);
193
}
194
195
static void gen_nand_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
196
@@ -XXX,XX +XXX,XX @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr_s *a)
197
.fno = gen_helper_sve_nand_pppp,
198
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
199
};
200
- if (a->s) {
201
- return do_pppp_flags(s, a, &op);
202
- } else {
203
- return do_vecop4_p(s, &op, a->rd, a->rn, a->rm, a->pg);
204
- }
205
+ return do_pppp_flags(s, a, &op);
206
}
207
208
/*
288
/*
289
* Multiply and multiply accumulate
290
*/
209
--
291
--
210
2.20.1
292
2.20.1
211
293
212
294
diff view generated by jsdifflib
[PULL 10/35] hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE shifts by immediate, which perform shifts
2
2
on a single general-purpose register.
3
Allow the device to execute the DMA transfers in a different
3
4
AddressSpace.
4
These patterns overlap with the long-shift-by-immediates,
5
5
so we have to rearrange the grouping a little here.
6
The H3 SoC keeps using the system_memory address space,
6
7
but via the proper dma_memory_access() API.
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
12
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Message-id: 20200814122907.27732-1-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
include/hw/net/allwinner-sun8i-emac.h | 6 ++++
11
target/arm/helper-mve.h | 3 ++
17
hw/arm/allwinner-h3.c | 2 ++
12
target/arm/translate.h | 1 +
18
hw/net/allwinner-sun8i-emac.c | 46 +++++++++++++++++----------
13
target/arm/t32.decode | 31 ++++++++++++++-----
19
3 files changed, 38 insertions(+), 16 deletions(-)
14
target/arm/mve_helper.c | 10 ++++++
20
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
21
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinner-sun8i-emac.h
16
5 files changed, 104 insertions(+), 9 deletions(-)
22
index XXXXXXX..XXXXXXX 100644
17
23
--- a/include/hw/net/allwinner-sun8i-emac.h
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
24
+++ b/include/hw/net/allwinner-sun8i-emac.h
19
index XXXXXXX..XXXXXXX 100644
25
@@ -XXX,XX +XXX,XX @@ typedef struct AwSun8iEmacState {
20
--- a/target/arm/helper-mve.h
26
/** Interrupt output signal to notify CPU */
21
+++ b/target/arm/helper-mve.h
27
qemu_irq irq;
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
28
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
29
+ /** Memory region where DMA transfers are done */
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
30
+ MemoryRegion *dma_mr;
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
+
26
+
32
+ /** Address space used internally for DMA transfers */
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
33
+ AddressSpace dma_as;
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
34
+
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
35
/** Generic Network Interface Controller (NIC) for networking API */
30
index XXXXXXX..XXXXXXX 100644
36
NICState *nic;
31
--- a/target/arm/translate.h
37
32
+++ b/target/arm/translate.h
38
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
39
index XXXXXXX..XXXXXXX 100644
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
40
--- a/hw/arm/allwinner-h3.c
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
41
+++ b/hw/arm/allwinner-h3.c
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
42
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
43
qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
38
44
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
39
/**
45
}
40
* arm_tbflags_from_tb:
46
+ object_property_set_link(OBJECT(&s->emac), "dma-memory",
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
47
+ OBJECT(get_system_memory()), &error_fatal);
42
index XXXXXXX..XXXXXXX 100644
48
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
43
--- a/target/arm/t32.decode
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
44
+++ b/target/arm/t32.decode
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
51
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/net/allwinner-sun8i-emac.c
54
+++ b/hw/net/allwinner-sun8i-emac.c
55
@@ -XXX,XX +XXX,XX @@
45
@@ -XXX,XX +XXX,XX @@
56
46
57
#include "qemu/osdep.h"
47
&mve_shl_ri rdalo rdahi shim
58
#include "qemu/units.h"
48
&mve_shl_rr rdalo rdahi rm
59
+#include "qapi/error.h"
49
+&mve_sh_ri rda shim
60
#include "hw/sysbus.h"
50
61
#include "migration/vmstate.h"
51
# rdahi: bits [3:1] from insn, bit 0 is 1
62
#include "net/net.h"
52
# rdalo: bits [3:1] from insn, bit 0 is 0
63
@@ -XXX,XX +XXX,XX @@
53
@@ -XXX,XX +XXX,XX @@
64
#include "net/checksum.h"
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
65
#include "qemu/module.h"
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
66
#include "exec/cpu-common.h"
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
67
+#include "sysemu/dma.h"
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
68
#include "hw/net/allwinner-sun8i-emac.h"
58
+ &mve_sh_ri shim=%imm5_12_6
69
59
70
/* EMAC register offsets */
60
{
71
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
qemu_set_irq(s->irq, (s->int_sta & s->int_en) != 0);
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
73
}
105
}
74
106
+
75
-static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
76
+static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s,
108
+{
77
+ FrameDescriptor *desc,
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
78
size_t min_size)
110
+}
79
{
111
+
80
uint32_t paddr = desc->next;
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
81
113
+{
82
- cpu_physical_memory_read(paddr, desc, sizeof(*desc));
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
83
+ dma_memory_read(&s->dma_as, paddr, desc, sizeof(*desc));
115
+}
84
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
85
if ((desc->status & DESC_STATUS_CTL) &&
117
index XXXXXXX..XXXXXXX 100644
86
(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
118
--- a/target/arm/translate.c
87
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
119
+++ b/target/arm/translate.c
88
}
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
121
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
123
{
124
- TCGv_i32 t = tcg_temp_new_i32();
125
+ TCGv_i32 t;
126
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
128
+ if (sh == 32) {
129
+ tcg_gen_movi_i32(d, 0);
130
+ return;
131
+ }
132
+ t = tcg_temp_new_i32();
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
134
tcg_gen_sari_i32(d, a, sh);
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
89
}
154
}
90
155
91
-static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
92
+static uint32_t allwinner_sun8i_emac_get_desc(AwSun8iEmacState *s,
157
+{
93
+ FrameDescriptor *desc,
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
94
uint32_t start_addr,
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
95
size_t min_size)
160
+ return false;
96
{
161
+ }
97
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
162
+ if (!dc_isar_feature(aa32_mve, s) ||
98
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
99
/* Note that the list is a cycle. Last entry points back to the head. */
164
+ a->rda == 13 || a->rda == 15) {
100
while (desc_addr != 0) {
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
101
- cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
166
+ unallocated_encoding(s);
102
+ dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
167
+ return true;
103
168
+ }
104
if ((desc->status & DESC_STATUS_CTL) &&
169
+
105
(desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >= min_size) {
170
+ if (a->shim == 0) {
106
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
171
+ a->shim = 32;
107
FrameDescriptor *desc,
172
+ }
108
size_t min_size)
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
109
{
174
+
110
- return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
175
+ return true;
111
+ return allwinner_sun8i_emac_get_desc(s, desc, s->rx_desc_curr, min_size);
176
+}
112
}
177
+
113
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
114
static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
179
+{
115
FrameDescriptor *desc,
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
116
size_t min_size)
181
+}
117
{
182
+
118
- return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
119
+ return allwinner_sun8i_emac_get_desc(s, desc, s->tx_desc_head, min_size);
184
+{
120
}
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
121
186
+}
122
-static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
187
+
123
+static void allwinner_sun8i_emac_flush_desc(AwSun8iEmacState *s,
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
124
+ FrameDescriptor *desc,
189
+{
125
uint32_t phys_addr)
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
126
{
191
+}
127
- cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
192
+
128
+ dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc));
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
129
}
194
+{
130
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
131
static bool allwinner_sun8i_emac_can_receive(NetClientState *nc)
196
+}
132
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
197
+
133
<< RX_DESC_STATUS_FRM_LEN_SHIFT;
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
134
}
199
+{
135
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
136
- cpu_physical_memory_write(desc.addr, buf, desc_bytes);
201
+}
137
- allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
202
+
138
+ dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes);
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
139
+ allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr);
204
+{
140
trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
141
desc_bytes);
206
+}
142
207
+
143
@@ -XXX,XX +XXX,XX @@ static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
208
/*
144
bytes_left -= desc_bytes;
209
* Multiply and multiply accumulate
145
210
*/
146
/* Move to the next descriptor */
147
- s->rx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 64);
148
+ s->rx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 64);
149
if (!s->rx_desc_curr) {
150
/* Not enough buffer space available */
151
s->int_sta |= INT_STA_RX_BUF_UA;
152
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
153
desc.status |= TX_DESC_STATUS_LENGTH_ERR;
154
break;
155
}
156
- cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, bytes);
157
+ dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, bytes);
158
packet_bytes += bytes;
159
desc.status &= ~DESC_STATUS_CTL;
160
- allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
161
+ allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr);
162
163
/* After the last descriptor, send the packet */
164
if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
165
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
166
packet_bytes = 0;
167
transmitted++;
168
}
169
- s->tx_desc_curr = allwinner_sun8i_emac_next_desc(&desc, 0);
170
+ s->tx_desc_curr = allwinner_sun8i_emac_next_desc(s, &desc, 0);
171
}
172
173
/* Raise transmit completed interrupt */
174
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
175
break;
176
case REG_TX_CUR_BUF: /* Transmit Current Buffer */
177
if (s->tx_desc_curr != 0) {
178
- cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
179
+ dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(desc));
180
value = desc.addr;
181
} else {
182
value = 0;
183
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
184
break;
185
case REG_RX_CUR_BUF: /* Receive Current Buffer */
186
if (s->rx_desc_curr != 0) {
187
- cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
188
+ dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(desc));
189
value = desc.addr;
190
} else {
191
value = 0;
192
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
193
{
194
AwSun8iEmacState *s = AW_SUN8I_EMAC(dev);
195
196
+ if (!s->dma_mr) {
197
+ error_setg(errp, TYPE_AW_SUN8I_EMAC " 'dma-memory' link not set");
198
+ return;
199
+ }
200
+
201
+ address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
202
+
203
qemu_macaddr_default_if_unset(&s->conf.macaddr);
204
s->nic = qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
205
object_get_typename(OBJECT(dev)), dev->id, s);
206
@@ -XXX,XX +XXX,XX @@ static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
207
static Property allwinner_sun8i_emac_properties[] = {
208
DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
209
DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
210
+ DEFINE_PROP_LINK("dma-memory", AwSun8iEmacState, dma_mr,
211
+ TYPE_MEMORY_REGION, MemoryRegion *),
212
DEFINE_PROP_END_OF_LIST(),
213
};
214
215
--
211
--
216
2.20.1
212
2.20.1
217
213
218
214
diff view generated by jsdifflib
[PULL 09/35] hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
[PULL 24/24] target/arm: Implement MVE shifts by register
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE shifts by register, which perform
2
shifts on a single general-purpose register.
2
3
3
Allow the device to execute the DMA transfers in a different
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
AddressSpace.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
7
---
8
target/arm/helper-mve.h | 2 ++
9
target/arm/translate.h | 1 +
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
5
14
6
The A10 and H3 SoC keep using the system_memory address space,
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
but via the proper dma_memory_access() API.
8
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Message-id: 20200814110057.307-1-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/sd/allwinner-sdhost.h | 6 ++++++
16
hw/arm/allwinner-a10.c | 2 ++
17
hw/arm/allwinner-h3.c | 2 ++
18
hw/sd/allwinner-sdhost.c | 37 ++++++++++++++++++++++++++------
19
4 files changed, 41 insertions(+), 6 deletions(-)
20
21
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdhost.h
22
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/sd/allwinner-sdhost.h
17
--- a/target/arm/helper-mve.h
24
+++ b/include/hw/sd/allwinner-sdhost.h
18
+++ b/target/arm/helper-mve.h
25
@@ -XXX,XX +XXX,XX @@ typedef struct AwSdHostState {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
/** Interrupt output signal to notify CPU */
20
27
qemu_irq irq;
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
28
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
29
+ /** Memory region where DMA transfers are done */
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
30
+ MemoryRegion *dma_mr;
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
31
+
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
32
+ /** Address space used internally for DMA transfers */
33
+ AddressSpace dma_as;
34
+
35
/** Number of bytes left in current DMA transfer */
36
uint32_t transfer_cnt;
37
38
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
39
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/allwinner-a10.c
27
--- a/target/arm/translate.h
41
+++ b/hw/arm/allwinner-a10.c
28
+++ b/target/arm/translate.h
42
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
41
@@ -XXX,XX +XXX,XX @@
42
&mve_shl_ri rdalo rdahi shim
43
&mve_shl_rr rdalo rdahi rm
44
&mve_sh_ri rda shim
45
+&mve_sh_rr rda rm
46
47
# rdahi: bits [3:1] from insn, bit 0 is 1
48
# rdalo: bits [3:1] from insn, bit 0 is 0
49
@@ -XXX,XX +XXX,XX @@
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
52
&mve_sh_ri shim=%imm5_12_6
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
54
55
{
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
43
}
59
}
44
60
45
/* SD/MMC */
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
46
+ object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
47
+ OBJECT(get_system_memory()), &error_fatal);
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
48
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
49
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
65
+ {
50
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
51
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
52
index XXXXXXX..XXXXXXX 100644
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
53
--- a/hw/arm/allwinner-h3.c
54
+++ b/hw/arm/allwinner-h3.c
55
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
56
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
57
58
/* SD/MMC */
59
+ object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
60
+ OBJECT(get_system_memory()), &error_fatal);
61
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
62
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
63
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
64
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/hw/sd/allwinner-sdhost.c
67
+++ b/hw/sd/allwinner-sdhost.c
68
@@ -XXX,XX +XXX,XX @@
69
#include "qemu/log.h"
70
#include "qemu/module.h"
71
#include "qemu/units.h"
72
+#include "qapi/error.h"
73
#include "sysemu/blockdev.h"
74
+#include "sysemu/dma.h"
75
+#include "hw/qdev-properties.h"
76
#include "hw/irq.h"
77
#include "hw/sd/allwinner-sdhost.h"
78
#include "migration/vmstate.h"
79
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
80
uint8_t buf[1024];
81
82
/* Read descriptor */
83
- cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
84
+ dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc));
85
if (desc->size == 0) {
86
desc->size = klass->max_desc_size;
87
} else if (desc->size > klass->max_desc_size) {
88
@@ -XXX,XX +XXX,XX @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
89
90
/* Write to SD bus */
91
if (is_write) {
92
- cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_done,
93
- buf, buf_bytes);
94
+ dma_memory_read(&s->dma_as,
95
+ (desc->addr & DESC_SIZE_MASK) + num_done,
96
+ buf, buf_bytes);
97
sdbus_write_data(&s->sdbus, buf, buf_bytes);
98
99
/* Read from SD bus */
100
} else {
101
sdbus_read_data(&s->sdbus, buf, buf_bytes);
102
- cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_done,
103
- buf, buf_bytes);
104
+ dma_memory_write(&s->dma_as,
105
+ (desc->addr & DESC_SIZE_MASK) + num_done,
106
+ buf, buf_bytes);
107
}
108
num_done += buf_bytes;
109
}
110
111
/* Clear hold flag and flush descriptor */
112
desc->status &= ~DESC_STATUS_HOLD;
113
- cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
114
+ dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc));
115
116
return num_done;
117
}
118
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_allwinner_sdhost = {
119
}
120
};
121
122
+static Property allwinner_sdhost_properties[] = {
123
+ DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr,
124
+ TYPE_MEMORY_REGION, MemoryRegion *),
125
+ DEFINE_PROP_END_OF_LIST(),
126
+};
127
+
128
static void allwinner_sdhost_init(Object *obj)
129
{
130
AwSdHostState *s = AW_SDHOST(obj);
131
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_init(Object *obj)
132
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
133
}
134
135
+static void allwinner_sdhost_realize(DeviceState *dev, Error **errp)
136
+{
137
+ AwSdHostState *s = AW_SDHOST(dev);
138
+
139
+ if (!s->dma_mr) {
140
+ error_setg(errp, TYPE_AW_SDHOST " 'dma-memory' link not set");
141
+ return;
142
+ }
69
+ }
143
+
70
+
144
+ address_space_init(&s->dma_as, s->dma_mr, "sdhost-dma");
71
+ {
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
75
+ }
76
+
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
88
+
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
90
+{
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
145
+}
92
+}
146
+
93
+
147
static void allwinner_sdhost_reset(DeviceState *dev)
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
148
{
95
+{
149
AwSdHostState *s = AW_SDHOST(dev);
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
150
@@ -XXX,XX +XXX,XX @@ static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
97
+}
151
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
152
dc->reset = allwinner_sdhost_reset;
99
index XXXXXXX..XXXXXXX 100644
153
dc->vmsd = &vmstate_allwinner_sdhost;
100
--- a/target/arm/translate.c
154
+ dc->realize = allwinner_sdhost_realize;
101
+++ b/target/arm/translate.c
155
+ device_class_set_props(dc, allwinner_sdhost_properties);
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
156
}
104
}
157
105
158
static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
119
+ }
120
+
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
123
+ return true;
124
+}
125
+
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
127
+{
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
129
+}
130
+
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
132
+{
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
134
+}
135
+
136
/*
137
* Multiply and multiply accumulate
138
*/
159
--
139
--
160
2.20.1
140
2.20.1
161
141
162
142
diff view generated by jsdifflib
[PULL 11/35] hw/arm/xilinx_zynq: Uninline cadence_uart_create()
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
As we want to call qdev_connect_clock_in() before the device
4
is realized, we need to uninline cadence_uart_create() first.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20200803105647.22223-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/char/cadence_uart.h | 17 -----------------
12
hw/arm/xilinx_zynq.c | 14 ++++++++++++--
13
2 files changed, 12 insertions(+), 19 deletions(-)
14
15
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/char/cadence_uart.h
18
+++ b/include/hw/char/cadence_uart.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct {
20
Clock *refclk;
21
} CadenceUARTState;
22
23
-static inline DeviceState *cadence_uart_create(hwaddr addr,
24
- qemu_irq irq,
25
- Chardev *chr)
26
-{
27
- DeviceState *dev;
28
- SysBusDevice *s;
29
-
30
- dev = qdev_new(TYPE_CADENCE_UART);
31
- s = SYS_BUS_DEVICE(dev);
32
- qdev_prop_set_chr(dev, "chardev", chr);
33
- sysbus_realize_and_unref(s, &error_fatal);
34
- sysbus_mmio_map(s, 0, addr);
35
- sysbus_connect_irq(s, 0, irq);
36
-
37
- return dev;
38
-}
39
-
40
#endif
41
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/arm/xilinx_zynq.c
44
+++ b/hw/arm/xilinx_zynq.c
45
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
46
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
47
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
48
49
- dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
50
+ dev = qdev_new(TYPE_CADENCE_UART);
51
+ busdev = SYS_BUS_DEVICE(dev);
52
+ qdev_prop_set_chr(dev, "chardev", serial_hd(0));
53
+ sysbus_realize_and_unref(busdev, &error_fatal);
54
+ sysbus_mmio_map(busdev, 0, 0xE0000000);
55
+ sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
56
qdev_connect_clock_in(dev, "refclk",
57
qdev_get_clock_out(slcr, "uart0_ref_clk"));
58
- dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
59
+ dev = qdev_new(TYPE_CADENCE_UART);
60
+ busdev = SYS_BUS_DEVICE(dev);
61
+ qdev_prop_set_chr(dev, "chardev", serial_hd(1));
62
+ sysbus_realize_and_unref(busdev, &error_fatal);
63
+ sysbus_mmio_map(busdev, 0, 0xE0001000);
64
+ sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
65
qdev_connect_clock_in(dev, "refclk",
66
qdev_get_clock_out(slcr, "uart1_ref_clk"));
67
68
--
69
2.20.1
70
71
diff view generated by jsdifflib
[PULL 12/35] hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Clock canonical name is set in device_set_realized (see the block
4
added to hw/core/qdev.c in commit 0e6934f264).
5
If we connect a clock after the device is realized, this code is
6
not executed. This is currently not a problem as this name is only
7
used for trace events, however this disrupt tracing.
8
9
Fix by calling qdev_connect_clock_in() before realizing.
10
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20200803105647.22223-3-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/xilinx_zynq.c | 18 +++++++++---------
17
1 file changed, 9 insertions(+), 9 deletions(-)
18
19
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/xilinx_zynq.c
22
+++ b/hw/arm/xilinx_zynq.c
23
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
24
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
25
0);
26
27
- /* Create slcr, keep a pointer to connect clocks */
28
- slcr = qdev_new("xilinx,zynq_slcr");
29
- sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
30
- sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
31
-
32
/* Create the main clock source, and feed slcr with it */
33
zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
34
object_property_add_child(OBJECT(zynq_machine), "ps_clk",
35
OBJECT(zynq_machine->ps_clk));
36
object_unref(OBJECT(zynq_machine->ps_clk));
37
clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
38
+
39
+ /* Create slcr, keep a pointer to connect clocks */
40
+ slcr = qdev_new("xilinx,zynq_slcr");
41
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
42
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
43
+ sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
44
45
dev = qdev_new(TYPE_A9MPCORE_PRIV);
46
qdev_prop_set_uint32(dev, "num-cpu", 1);
47
@@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine)
48
dev = qdev_new(TYPE_CADENCE_UART);
49
busdev = SYS_BUS_DEVICE(dev);
50
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
51
+ qdev_connect_clock_in(dev, "refclk",
52
+ qdev_get_clock_out(slcr, "uart0_ref_clk"));
53
sysbus_realize_and_unref(busdev, &error_fatal);
54
sysbus_mmio_map(busdev, 0, 0xE0000000);
55
sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
56
- qdev_connect_clock_in(dev, "refclk",
57
- qdev_get_clock_out(slcr, "uart0_ref_clk"));
58
dev = qdev_new(TYPE_CADENCE_UART);
59
busdev = SYS_BUS_DEVICE(dev);
60
qdev_prop_set_chr(dev, "chardev", serial_hd(1));
61
+ qdev_connect_clock_in(dev, "refclk",
62
+ qdev_get_clock_out(slcr, "uart1_ref_clk"));
63
sysbus_realize_and_unref(busdev, &error_fatal);
64
sysbus_mmio_map(busdev, 0, 0xE0001000);
65
sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
66
- qdev_connect_clock_in(dev, "refclk",
67
- qdev_get_clock_out(slcr, "uart1_ref_clk"));
68
69
sysbus_create_varargs("cadence_ttc", 0xF8001000,
70
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
71
--
72
2.20.1
73
74
diff view generated by jsdifflib
[PULL 15/35] hw/misc/unimp: Display value after offset
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
To better align the read/write accesses, display the value after
4
the offset (read accesses only display the offset).
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200812190206.31595-2-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/misc/unimp.c | 8 ++++----
12
1 file changed, 4 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/unimp.c
17
+++ b/hw/misc/unimp.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t unimp_read(void *opaque, hwaddr offset, unsigned size)
19
{
20
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
21
22
- qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
23
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
24
"(size %d, offset 0x%" HWADDR_PRIx ")\n",
25
s->name, size, offset);
26
return 0;
27
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
28
UnimplementedDeviceState *s = UNIMPLEMENTED_DEVICE(opaque);
29
30
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
31
- "(size %d, value 0x%" PRIx64
32
- ", offset 0x%" HWADDR_PRIx ")\n",
33
- s->name, size, value, offset);
34
+ "(size %d, offset 0x%" HWADDR_PRIx
35
+ ", value 0x%" PRIx64 ")\n",
36
+ s->name, size, offset, value);
37
}
38
39
static const MemoryRegionOps unimp_ops = {
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
[PULL 16/35] hw/misc/unimp: Display the value with width of the access size
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
To quickly notice the access size, display the value with the
4
width of the access (i.e. 16-bit access is displayed 0x0000,
5
while 8-bit access 0x00).
6
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200812190206.31595-3-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/unimp.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/misc/unimp.c
18
+++ b/hw/misc/unimp.c
19
@@ -XXX,XX +XXX,XX @@ static void unimp_write(void *opaque, hwaddr offset,
20
21
qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
22
"(size %d, offset 0x%" HWADDR_PRIx
23
- ", value 0x%" PRIx64 ")\n",
24
- s->name, size, offset, value);
25
+ ", value 0x%0*" PRIx64 ")\n",
26
+ s->name, size, offset, size << 1, value);
27
}
28
29
static const MemoryRegionOps unimp_ops = {
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
[PULL 20/35] target/arm: Split out gen_gvec_fn_zz
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Model the new function on gen_gvec_fn2 in translate-a64.c, but
4
indicating which kind of register and in which order. Since there
5
is only one user of do_vector2_z, fold it into do_mov_z.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200815013145.539409-3-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 19 ++++++++++---------
13
1 file changed, 10 insertions(+), 9 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
20
}
21
22
/* Invoke a vector expander on two Zregs. */
23
-static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
24
- int esz, int rd, int rn)
25
+
26
+static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
27
+ int esz, int rd, int rn)
28
{
29
- if (sve_access_check(s)) {
30
- unsigned vsz = vec_full_reg_size(s);
31
- gvec_fn(esz, vec_full_reg_offset(s, rd),
32
- vec_full_reg_offset(s, rn), vsz, vsz);
33
- }
34
- return true;
35
+ unsigned vsz = vec_full_reg_size(s);
36
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
37
+ vec_full_reg_offset(s, rn), vsz, vsz);
38
}
39
40
/* Invoke a vector expander on three Zregs. */
41
@@ -XXX,XX +XXX,XX @@ static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
42
/* Invoke a vector move on two Zregs. */
43
static bool do_mov_z(DisasContext *s, int rd, int rn)
44
{
45
- return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
46
+ if (sve_access_check(s)) {
47
+ gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
48
+ }
49
+ return true;
50
}
51
52
/* Initialize a Zreg with replications of a 64-bit immediate. */
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
[PULL 23/35] target/arm: Merge do_vector2_p into do_mov_p
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This is the only user of the function.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20200815013145.539409-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 19 ++++++-------------
11
1 file changed, 6 insertions(+), 13 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
18
tcg_gen_gvec_dup_imm(MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word);
19
}
20
21
-/* Invoke a vector expander on two Pregs. */
22
-static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn,
23
- int esz, int rd, int rn)
24
-{
25
- if (sve_access_check(s)) {
26
- unsigned psz = pred_gvec_reg_size(s);
27
- gvec_fn(esz, pred_full_reg_offset(s, rd),
28
- pred_full_reg_offset(s, rn), psz, psz);
29
- }
30
- return true;
31
-}
32
-
33
/* Invoke a vector expander on three Pregs. */
34
static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn,
35
int esz, int rd, int rn, int rm)
36
@@ -XXX,XX +XXX,XX @@ static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op,
37
/* Invoke a vector move on two Pregs. */
38
static bool do_mov_p(DisasContext *s, int rd, int rn)
39
{
40
- return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn);
41
+ if (sve_access_check(s)) {
42
+ unsigned psz = pred_gvec_reg_size(s);
43
+ tcg_gen_gvec_mov(MO_8, pred_full_reg_offset(s, rd),
44
+ pred_full_reg_offset(s, rn), psz, psz);
45
+ }
46
+ return true;
47
}
48
49
/* Set the cpu flags as per a return from an SVE helper. */
50
--
51
2.20.1
52
53
diff view generated by jsdifflib
[PULL 25/35] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The gvec operation was added after the initial implementation
4
of the SEL instruction and was missed in the conversion.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200815013145.539409-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 31 ++++++++-----------------------
12
1 file changed, 8 insertions(+), 23 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
19
return do_pppp_flags(s, a, &op);
20
}
21
22
-static void gen_sel_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
23
-{
24
- tcg_gen_and_i64(pn, pn, pg);
25
- tcg_gen_andc_i64(pm, pm, pg);
26
- tcg_gen_or_i64(pd, pn, pm);
27
-}
28
-
29
-static void gen_sel_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn,
30
- TCGv_vec pm, TCGv_vec pg)
31
-{
32
- tcg_gen_and_vec(vece, pn, pn, pg);
33
- tcg_gen_andc_vec(vece, pm, pm, pg);
34
- tcg_gen_or_vec(vece, pd, pn, pm);
35
-}
36
-
37
static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a)
38
{
39
- static const GVecGen4 op = {
40
- .fni8 = gen_sel_pg_i64,
41
- .fniv = gen_sel_pg_vec,
42
- .fno = gen_helper_sve_sel_pppp,
43
- .prefer_i64 = TCG_TARGET_REG_BITS == 64,
44
- };
45
-
46
if (a->s) {
47
return false;
48
}
49
- return do_pppp_flags(s, a, &op);
50
+ if (sve_access_check(s)) {
51
+ unsigned psz = pred_gvec_reg_size(s);
52
+ tcg_gen_gvec_bitsel(MO_8, pred_full_reg_offset(s, a->rd),
53
+ pred_full_reg_offset(s, a->pg),
54
+ pred_full_reg_offset(s, a->rn),
55
+ pred_full_reg_offset(s, a->rm), psz, psz);
56
+ }
57
+ return true;
58
}
59
60
static void gen_orr_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)
61
--
62
2.20.1
63
64
diff view generated by jsdifflib
[PULL 31/35] target/arm: Tidy SVE tszimm shift formats
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Rather than require the user to fill in the immediate (shl or shr),
4
create full formats that include the immediate.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200815013145.539409-14-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/sve.decode | 35 ++++++++++++++++-------------------
12
1 file changed, 16 insertions(+), 19 deletions(-)
13
14
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/sve.decode
17
+++ b/target/arm/sve.decode
18
@@ -XXX,XX +XXX,XX @@
19
@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
20
21
# Two register operand, one immediate operand, with predicate,
22
-# element size encoded as TSZHL. User must fill in imm.
23
-@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
24
- &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
25
+# element size encoded as TSZHL.
26
+@rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
27
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
28
+@rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
29
+ &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
30
31
# Similarly without predicate.
32
-@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
33
- &rri_esz esz=%tszimm16_esz
34
+@rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
35
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
36
+@rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
37
+ &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
38
39
# Two register operand, one immediate operand, with 4-bit predicate.
40
# User must fill in imm.
41
@@ -XXX,XX +XXX,XX @@ UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
42
### SVE Shift by Immediate - Predicated Group
43
44
# SVE bitwise shift by immediate (predicated)
45
-ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
46
- @rdn_pg_tszimm imm=%tszimm_shr
47
-LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
48
- @rdn_pg_tszimm imm=%tszimm_shr
49
-LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
50
- @rdn_pg_tszimm imm=%tszimm_shl
51
-ASRD 00000100 .. 000 100 100 ... .. ... ..... \
52
- @rdn_pg_tszimm imm=%tszimm_shr
53
+ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
54
+LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
55
+LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
56
+ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
57
58
# SVE bitwise shift by vector (predicated)
59
ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
60
@@ -XXX,XX +XXX,XX @@ RDVL 00000100 101 11111 01010 imm:s6 rd:5
61
### SVE Bitwise Shift - Unpredicated Group
62
63
# SVE bitwise shift by immediate (unpredicated)
64
-ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
65
- @rd_rn_tszimm imm=%tszimm16_shr
66
-LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
67
- @rd_rn_tszimm imm=%tszimm16_shr
68
-LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
69
- @rd_rn_tszimm imm=%tszimm16_shl
70
+ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
71
+LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
72
+LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
73
74
# SVE bitwise shift by wide elements (unpredicated)
75
# Note esz != 3
76
--
77
2.20.1
78
79
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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