[v4] support vector extension v1.0

[RFC v4 70/70] target/riscv: gdb: support vector registers for rv32

Posted by frank.chang@sifive.com 5 years, 5 months ago

From: Greentime Hu <greentime.hu@sifive.com>

This patch adds vector support for rv32 gdb. It allows gdb client to access
vector registers correctly.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 gdb-xml/riscv-32bit-csr.xml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
index 3d2031da7dc..bb98b927995 100644
--- a/gdb-xml/riscv-32bit-csr.xml
+++ b/gdb-xml/riscv-32bit-csr.xml
@@ -248,4 +248,11 @@
   <reg name="mucounteren" bitsize="32"/>
   <reg name="mscounteren" bitsize="32"/>
   <reg name="mhcounteren" bitsize="32"/>
+  <reg name="vstart" bitsize="32" group="vector"/>
+  <reg name="vxsat" bitsize="32" group="vector"/>
+  <reg name="vxrm" bitsize="32" group="vector"/>
+  <reg name="vcsr" bitsize="32" group="vector"/>
+  <reg name="vl" bitsize="32" group="vector"/>
+  <reg name="vtype" bitsize="32" group="vector"/>
+  <reg name="vlenb" bitsize="32" group="vector"/>
 </feature>
-- 
2.17.1

Re: [RFC v4 70/70] target/riscv: gdb: support vector registers for rv32

Posted by Richard Henderson 5 years, 5 months ago

On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> This patch adds vector support for rv32 gdb. It allows gdb client to access
> vector registers correctly.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  gdb-xml/riscv-32bit-csr.xml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml
> index 3d2031da7dc..bb98b927995 100644
> --- a/gdb-xml/riscv-32bit-csr.xml
> +++ b/gdb-xml/riscv-32bit-csr.xml
> @@ -248,4 +248,11 @@
>    <reg name="mucounteren" bitsize="32"/>
>    <reg name="mscounteren" bitsize="32"/>
>    <reg name="mhcounteren" bitsize="32"/>
> +  <reg name="vstart" bitsize="32" group="vector"/>
> +  <reg name="vxsat" bitsize="32" group="vector"/>
> +  <reg name="vxrm" bitsize="32" group="vector"/>
> +  <reg name="vcsr" bitsize="32" group="vector"/>
> +  <reg name="vl" bitsize="32" group="vector"/>
> +  <reg name="vtype" bitsize="32" group="vector"/>
> +  <reg name="vlenb" bitsize="32" group="vector"/>
>  </feature>
> 

As per comments in the previous patch, needs squashing.


r~