[v4] support vector extension v1.0

[RFC v4 55/70] target/riscv: rvv-1.0: single-width floating-point reduction

Posted by frank.chang@sifive.com 5 years, 5 months ago

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/vector_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 15a646af361..00743cbce34 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4432,14 +4432,14 @@ GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
 GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
 
 /* Maximum value */
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum)
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum)
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum)
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum_noprop)
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum_noprop)
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum_noprop)
 
 /* Minimum value */
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum)
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum)
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum)
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum_noprop)
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum_noprop)
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum_noprop)
 
 /* Vector Widening Floating-Point Reduction Instructions */
 /* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
-- 
2.17.1

Re: [RFC v4 55/70] target/riscv: rvv-1.0: single-width floating-point reduction

Posted by Richard Henderson 5 years, 5 months ago

On 8/17/20 1:49 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/vector_helper.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)

The one sentence in the manual is quite poor for this, and needs improvement:

> Floating-point max and min reductions should return the same final> value and raise the same exception flags regardless of operation
> order.

It doesn't actually say anything about the way in which we've implemented the
*_noprop functions.

Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [RFC v4 55/70] target/riscv: rvv-1.0: single-width floating-point reduction

Posted by Richard Henderson 5 years, 5 months ago

On 8/29/20 4:50 PM, Richard Henderson wrote:
> It doesn't actually say anything about the way in which we've implemented the
> *_noprop functions.

Ho hum.  It seems v2.2 has changed fmin/fmax for the fpu as well.

We really should fix that too...


r~

Re: [RFC v4 55/70] target/riscv: rvv-1.0: single-width floating-point reduction

Posted by Chih-Min Chao 5 years, 5 months ago

On Sun, Aug 30, 2020 at 7:58 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 8/29/20 4:50 PM, Richard Henderson wrote:
> > It doesn't actually say anything about the way in which we've
> implemented the
> > *_noprop functions.
>
> Ho hum.  It seems v2.2 has changed fmin/fmax for the fpu as well.
>
> We really should fix that too...
>
>
> r~
>
>
The noprop is implemented in below patch and could  be applied to scalar
part
https://patchew.org/QEMU/1597908641-6293-1-git-send-email-chihmin.chao@sifive.com/

Chih-Min Chao