The following changes since commit d0ed6a69d399ae193959225cdeaa9382746c91cc:

  Update version for v5.1.0 release (2020-08-11 17:07:03 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200814

for you to fetch changes up to f57d45853ead8f3ff2c295a6b93b386b56396020:

  hw/intc: ibex_plic: Honour source priorities (2020-08-13 14:20:03 -0700)

----------------------------------------------------------------
The first RISC-V PR for the 5.2 window.

This includes:
 - NaNBox fixes
 - Vector extension improvements
 - a L2 cache controller
 - PMP fixes
 - Upgrade to OpenSBI v0.8 and the generic platform
 - Fixes for the Ibex PLIC

----------------------------------------------------------------
Alistair Francis (3):
      hw/intc: ibex_plic: Update the pending irqs
      hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
      hw/intc: ibex_plic: Honour source priorities

Bin Meng (7):
      hw/riscv: sifive_u: Add a dummy L2 cache controller device
      configure: Create symbolic links for pc-bios/*.elf files
      roms/opensbi: Upgrade from v0.7 to v0.8
      roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
      hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
      hw/riscv: spike: Change the default bios to use generic platform image
      gitlab-ci/opensbi: Update GitLab CI to build generic platform

Hou Weiying (1):
      riscv: Fix bug in setting pmpcfg CSR for RISCV64

LIU Zhiwei (2):
      target/riscv: Clean up fmv.w.x
      target/riscv: check before allocating TCG temps

Richard Henderson (5):
      target/riscv: Generate nanboxed results from fp helpers
      target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
      target/riscv: Generate nanboxed results from trans_rvf.inc.c
      target/riscv: Check nanboxed inputs to fp helpers
      target/riscv: Check nanboxed inputs in trans_rvf.inc.c

Zong Li (2):
      target/riscv: Fix the translation of physical address
      target/riscv: Change the TLB page size depends on PMP entries.

 configure                                      |   1 +
 Makefile                                       |   4 +-
 include/hw/intc/ibex_plic.h                    |   1 +
 include/hw/riscv/sifive_u.h                    |   4 +
 target/riscv/internals.h                       |  16 ++++
 target/riscv/pmp.h                             |   2 +
 hw/intc/ibex_plic.c                            |  36 +++++++--
 hw/riscv/sifive_u.c                            |  26 ++++++-
 hw/riscv/spike.c                               |   9 ++-
 hw/riscv/virt.c                                |   4 +-
 target/riscv/cpu_helper.c                      |  15 +++-
 target/riscv/fpu_helper.c                      | 102 ++++++++++++++++---------
 target/riscv/insn_trans/trans_rvd.inc.c        |   8 +-
 target/riscv/insn_trans/trans_rvf.inc.c        |  99 +++++++++++++++---------
 target/riscv/pmp.c                             |  57 +++++++++++++-
 target/riscv/translate.c                       |  29 +++++++
 .gitlab-ci.d/opensbi.yml                       |  28 +++----
 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin | Bin 0 -> 62144 bytes
 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf | Bin 0 -> 558668 bytes
 pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin   | Bin 49520 -> 0 bytes
 pc-bios/opensbi-riscv32-virt-fw_jump.bin       | Bin 49504 -> 0 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin | Bin 0 -> 70792 bytes
 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf | Bin 0 -> 620424 bytes
 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin   | Bin 57936 -> 0 bytes
 pc-bios/opensbi-riscv64-virt-fw_jump.bin       | Bin 57920 -> 0 bytes
 roms/Makefile                                  |  32 +++-----
 roms/opensbi                                   |   2 +-
 27 files changed, 338 insertions(+), 137 deletions(-)
 create mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
 create mode 100644 pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
 delete mode 100644 pc-bios/opensbi-riscv32-sifive_u-fw_jump.bin
 delete mode 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin
 create mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
 create mode 100644 pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
 delete mode 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
 delete mode 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin

On Fri, 14 Aug 2020 at 16:18, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit d0ed6a69d399ae193959225cdeaa9382746c91cc:
>
>   Update version for v5.1.0 release (2020-08-11 17:07:03 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200814
>
> for you to fetch changes up to f57d45853ead8f3ff2c295a6b93b386b56396020:
>
>   hw/intc: ibex_plic: Honour source priorities (2020-08-13 14:20:03 -0700)
>
> ----------------------------------------------------------------
> The first RISC-V PR for the 5.2 window.
>
> This includes:
>  - NaNBox fixes
>  - Vector extension improvements
>  - a L2 cache controller
>  - PMP fixes
>  - Upgrade to OpenSBI v0.8 and the generic platform
>  - Fixes for the Ibex PLIC
>
Hi; this conflicts with the meson buildsystem merge, I'm
afraid -- can you rebase and resend, please?

thanks
-- PMM