QEMU does not model caches, so there is not much to do with the
Invalidate/Writeback opcodes. Make it explicit adding a comment.

Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/op_helper.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 92c399d8d4..2496d1dd71 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1578,16 +1578,19 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
     target_ulong index = addr & 0x1fffffff;
 
     switch (cache_operation) {
-    case 0b010:
-        /* Index Store Tag */
+    case 0b010: /* Index Store Tag */
         memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
                                      MO_64, MEMTXATTRS_UNSPECIFIED);
         break;
-    case 0b001:
-        /* Index Load Tag */
+    case 0b001: /* Index Load Tag */
         memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
                                     MO_64, MEMTXATTRS_UNSPECIFIED);
         break;
+    case 0b000: /* Index Invalidate */
+    case 0b100: /* Hit Invalidate */
+    case 0b110: /* Hit Writeback */
+        /* no-op */
+        break;
     default:
         break;
     }
-- 
2.21.3

在 2020/8/14 上午2:15, Philippe Mathieu-Daudé 写道:
> QEMU does not model caches, so there is not much to do with the
> Invalidate/Writeback opcodes. Make it explicit adding a comment.
>
> Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Thanks~

> ---
>   target/mips/op_helper.c | 11 +++++++----
>   1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 92c399d8d4..2496d1dd71 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -1578,16 +1578,19 @@ void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
>       target_ulong index = addr & 0x1fffffff;
>   
>       switch (cache_operation) {
> -    case 0b010:
> -        /* Index Store Tag */
> +    case 0b010: /* Index Store Tag */
>           memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
>                                        MO_64, MEMTXATTRS_UNSPECIFIED);
>           break;
> -    case 0b001:
> -        /* Index Load Tag */
> +    case 0b001: /* Index Load Tag */
>           memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
>                                       MO_64, MEMTXATTRS_UNSPECIFIED);
>           break;
> +    case 0b000: /* Index Invalidate */
> +    case 0b100: /* Hit Invalidate */
> +    case 0b110: /* Hit Writeback */
> +        /* no-op */
> +        break;
>       default:
>           break;
>       }

On 8/13/20 11:15 AM, Philippe Mathieu-Daudé wrote:
>      switch (cache_operation) {
> -    case 0b010:
> -        /* Index Store Tag */
> +    case 0b010: /* Index Store Tag */
>          memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
>                                       MO_64, MEMTXATTRS_UNSPECIFIED);
>          break;
> -    case 0b001:
> -        /* Index Load Tag */
> +    case 0b001: /* Index Load Tag */
>          memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
>                                      MO_64, MEMTXATTRS_UNSPECIFIED);
>          break;

Merge these lines back to patch 1.  With that, both 1/ and 2/,

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~