[RFC v3 49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions

From: Frank Chang <frank.chang@sifive.com>

Sign-extend vsaddu.vi immediate value.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 263f2535d8c..c2eda17c0ce 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2329,7 +2329,7 @@ GEN_OPIVX_TRANS(vsaddu_vx,  opivx_check)
 GEN_OPIVX_TRANS(vsadd_vx,  opivx_check)
 GEN_OPIVX_TRANS(vssubu_vx,  opivx_check)
 GEN_OPIVX_TRANS(vssub_vx,  opivx_check)
-GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check)
+GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check)
 GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
 
 /* Vector Single-Width Averaging Add and Subtract */
-- 
2.17.1

• [RFC v3 01/71] target/riscv: drop vector 0.7.1 and add 1.0 support
• [RFC v3 02/71] target/riscv: Use FIELD_EX32() to extract wd field
• [RFC v3 03/71] target/riscv: rvv-1.0: add mstatus VS field
• [RFC v3 04/71] target/riscv: rvv-1.0: add sstatus VS field
• [RFC v3 05/71] target/riscv: rvv-1.0: introduce writable misa.v field
• [RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status
• [RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register
• [RFC v3 08/71] target/riscv: rvv-1.0: add vcsr register
• [RFC v3 09/71] target/riscv: rvv-1.0: add vlenb register
• [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
• [RFC v3 11/71] target/riscv: rvv-1.0: remove MLEN calculations
• [RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL
• [RFC v3 13/71] target/riscv: rvv-1.0: add VMA and VTA
• [RFC v3 14/71] target/riscv: rvv-1.0: update check functions
• [RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions
• [RFC v3 16/71] target/riscv: add fp16 nan-box check generator function
• [RFC v3 17/71] target/riscv: rvv:1.0: add translation-time nan-box helper function
• [RFC v3 18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans
• [RFC v3 19/71] target/riscv: rvv-1.0: configure instructions
• [RFC v3 20/71] target/riscv: rvv-1.0: stride load and store instructions
• [RFC v3 21/71] target/riscv: rvv-1.0: index load and store instructions
• [RFC v3 22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
• [RFC v3 23/71] target/riscv: rvv-1.0: fault-only-first unit stride load
• [RFC v3 24/71] target/riscv: rvv-1.0: amo operations
• [RFC v3 25/71] target/riscv: rvv-1.0: load/store whole register instructions
• [RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
• [RFC v3 27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
• [RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction
• [RFC v3 29/71] target/riscv: rvv-1.0: floating-point classify instructions
• [RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction
• [RFC v3 31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction
• [RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions
• [RFC v3 33/71] target/riscv: rvv-1.0: iota instruction
• [RFC v3 34/71] target/riscv: rvv-1.0: element index instruction
• [RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended
• [RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions
• [RFC v3 37/71] target/riscv: rvv-1.0: integer scalar move instructions
• [RFC v3 38/71] target/riscv: rvv-1.0: floating-point move instruction
• [RFC v3 39/71] target/riscv: rvv-1.0: floating-point scalar move instructions
• [RFC v3 40/71] target/riscv: rvv-1.0: whole register move instructions
• [RFC v3 41/71] target/riscv: rvv-1.0: integer extension instructions
• [RFC v3 42/71] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
• [RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions
• [RFC v3 44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
• [RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions
• [RFC v3 46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions
• [RFC v3 47/71] target/riscv: rvv-1.0: add Zvqmac extension
• [RFC v3 48/71] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions
• [RFC v3 49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
• [RFC v3 50/71] target/riscv: rvv-1.0: integer comparison instructions
• [RFC v3 51/71] target/riscv: use softfloat lib float16 comparison functions
• [RFC v3 52/71] target/riscv: rvv-1.0: floating-point compare instructions
• [RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions
• [RFC v3 54/71] target/riscv: rvv-1.0: slide instructions
• [RFC v3 55/71] target/riscv: rvv-1.0: floating-point slide instructions
• [RFC v3 56/71] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
• [RFC v3 57/71] target/riscv: rvv-1.0: single-width floating-point reduction
• [RFC v3 58/71] target/riscv: rvv-1.0: widening floating-point reduction instructions
• [RFC v3 59/71] target/riscv: rvv-1.0: single-width scaling shift instructions
• [RFC v3 60/71] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
• [RFC v3 61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
• [RFC v3 62/71] target/riscv: rvv-1.0: remove integer extract instruction
• [RFC v3 63/71] target/riscv: rvv-1.0: floating-point min/max instructions
• [RFC v3 64/71] target/riscv: introduce floating-point rounding mode enum
• [RFC v3 65/71] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
• [RFC v3 66/71] target/riscv: rvv-1.0: widening floating-point/integer type-convert
• [RFC v3 67/71] target/riscv: add "set round to odd" rounding mode helper function
• [RFC v3 68/71] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
• [RFC v3 69/71] target/riscv: gdb: modify gdb csr xml file to align with csr register map
• [RFC v3 70/71] target/riscv: gdb: support vector registers for rv64
• [RFC v3 71/71] target/riscv: gdb: support vector registers for rv32