1
Couple of last-minute things for rc3...
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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we were using uninitialized data for the guarded bit when
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combining stage 1 and stage 2 attrs.
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4
5
thanks
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-- PMM
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-- PMM
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7
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The following changes since commit d15532d91be177e7528310e0110e39f915779a99:
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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9
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Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100)
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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13
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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15
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for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995:
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100)
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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19
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm: Fix bug where we weren't initializing
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* Fix decode of LDRA[AB] instructions
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guarded bit state when combining S1/S2 attrs
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* docs/devel: Document decodetree no-overlap groups
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23
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----------------------------------------------------------------
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----------------------------------------------------------------
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Peter Collingbourne (1):
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Richard Henderson (2):
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target/arm: Fix decode of LDRA[AB] instructions
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target/arm: PTE bit GP only applies to stage1
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target/arm: Copy guarded bit in combine_cacheattrs
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28
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Richard Henderson (1):
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target/arm/ptw.c | 11 ++++++-----
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docs/devel: Document decodetree no-overlap groups
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1 file changed, 6 insertions(+), 5 deletions(-)
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29
docs/devel/decodetree.rst | 29 ++++++++++++++++++-----------
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target/arm/translate-a64.c | 6 ++++--
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2 files changed, 22 insertions(+), 13 deletions(-)
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diff view generated by jsdifflib
1
From: Peter Collingbourne <pcc@google.com>
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From: Richard Henderson <richard.henderson@linaro.org>
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2
3
These instructions use zero as the discriminator, not SP.
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Only perform the extract of GP during the stage1 walk.
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4
5
Signed-off-by: Peter Collingbourne <pcc@google.com>
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20200804002849.30268-1-pcc@google.com
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
10
---
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target/arm/translate-a64.c | 6 ++++--
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 4 insertions(+), 2 deletions(-)
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1 file changed, 5 insertions(+), 5 deletions(-)
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13
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diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
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--- a/target/arm/ptw.c
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+++ b/target/arm/translate-a64.c
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+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
18
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
19
19
result->f.attrs.secure = false;
20
if (s->pauth_active) {
21
if (use_key_a) {
22
- gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
23
+ gen_helper_autda(dirty_addr, cpu_env, dirty_addr,
24
+ new_tmp_a64_zero(s));
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} else {
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- gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
27
+ gen_helper_autdb(dirty_addr, cpu_env, dirty_addr,
28
+ new_tmp_a64_zero(s));
29
}
30
}
20
}
31
21
22
- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
23
- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
24
- result->f.guarded = extract64(attrs, 50, 1); /* GP */
25
- }
26
-
27
if (regime_is_stage2(mmu_idx)) {
28
result->cacheattrs.is_s2_format = true;
29
result->cacheattrs.attrs = extract32(attrs, 2, 4);
30
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
31
assert(attrindx <= 7);
32
result->cacheattrs.is_s2_format = false;
33
result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
34
+
35
+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
36
+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
37
+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
38
+ }
39
}
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/*
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--
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--
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2.20.1
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2.34.1
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diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When support for this feature went in, the update to the
3
The guarded bit comes from the stage1 walk.
4
documentation was forgotten.
5
4
6
Fixes: 067e8b0f45d6
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Fixes: Coverity CID 1507929
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20200803205708.315829-1-richard.henderson@linaro.org
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
10
---
13
docs/devel/decodetree.rst | 29 ++++++++++++++++++-----------
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target/arm/ptw.c | 1 +
14
1 file changed, 18 insertions(+), 11 deletions(-)
12
1 file changed, 1 insertion(+)
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13
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diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/devel/decodetree.rst
16
--- a/target/arm/ptw.c
19
+++ b/docs/devel/decodetree.rst
17
+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ Pattern Groups
18
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
21
19
22
Syntax::
20
assert(!s1.is_s2_format);
23
21
ret.is_s2_format = false;
24
- group := '{' ( pat_def | group )+ '}'
22
+ ret.guarded = s1.guarded;
25
+ group := overlap_group | no_overlap_group
23
26
+ overlap_group := '{' ( pat_def | group )+ '}'
24
if (s1.attrs == 0xf0) {
27
+ no_overlap_group := '[' ( pat_def | group )+ ']'
25
tagged = true;
28
29
-A *group* begins with a lone open-brace, with all subsequent lines
30
-indented two spaces, and ending with a lone close-brace. Groups
31
-may be nested, increasing the required indentation of the lines
32
-within the nested group to two spaces per nesting level.
33
+A *group* begins with a lone open-brace or open-bracket, with all
34
+subsequent lines indented two spaces, and ending with a lone
35
+close-brace or close-bracket. Groups may be nested, increasing the
36
+required indentation of the lines within the nested group to two
37
+spaces per nesting level.
38
39
-Unlike ungrouped patterns, grouped patterns are allowed to overlap.
40
-Conflicts are resolved by selecting the patterns in order. If all
41
-of the fixedbits for a pattern match, its translate function will
42
-be called. If the translate function returns false, then subsequent
43
-patterns within the group will be matched.
44
+Patterns within overlap groups are allowed to overlap. Conflicts are
45
+resolved by selecting the patterns in order. If all of the fixedbits
46
+for a pattern match, its translate function will be called. If the
47
+translate function returns false, then subsequent patterns within the
48
+group will be matched.
49
+
50
+Patterns within no-overlap groups are not allowed to overlap, just
51
+the same as ungrouped patterns. Thus no-overlap groups are intended
52
+to be nested inside overlap groups.
53
54
The following example from PA-RISC shows specialization of the *or*
55
instruction::
56
@@ -XXX,XX +XXX,XX @@ instruction::
57
When the *cf* field is zero, the instruction has no side effects,
58
and may be specialized. When the *rt* field is zero, the output
59
is discarded and so the instruction has no effect. When the *rt2*
60
-field is zero, the operation is ``reg[rt] | 0`` and so encodes
61
+field is zero, the operation is ``reg[r1] | 0`` and so encodes
62
the canonical register copy operation.
63
64
The output from the generator might look like::
65
--
26
--
66
2.20.1
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2.34.1
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68
diff view generated by jsdifflib