1 | Couple of last-minute things for rc3... | 1 | This bug seemed worth fixing for 8.0 since we need an rc4 anyway: |
---|---|---|---|
2 | we were using uninitialized data for the guarded bit when | ||
3 | combining stage 1 and stage 2 attrs. | ||
2 | 4 | ||
5 | thanks | ||
3 | -- PMM | 6 | -- PMM |
4 | 7 | ||
5 | The following changes since commit d15532d91be177e7528310e0110e39f915779a99: | 8 | The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6: |
6 | 9 | ||
7 | Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100) | 10 | Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100) |
8 | 11 | ||
9 | are available in the Git repository at: | 12 | are available in the Git repository at: |
10 | 13 | ||
11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410 |
12 | 15 | ||
13 | for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995: | 16 | for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308: |
14 | 17 | ||
15 | target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100) | 18 | target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100) |
16 | 19 | ||
17 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
18 | target-arm queue: | 21 | target-arm: Fix bug where we weren't initializing |
19 | * Fix decode of LDRA[AB] instructions | 22 | guarded bit state when combining S1/S2 attrs |
20 | * docs/devel: Document decodetree no-overlap groups | ||
21 | 23 | ||
22 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
23 | Peter Collingbourne (1): | 25 | Richard Henderson (2): |
24 | target/arm: Fix decode of LDRA[AB] instructions | 26 | target/arm: PTE bit GP only applies to stage1 |
27 | target/arm: Copy guarded bit in combine_cacheattrs | ||
25 | 28 | ||
26 | Richard Henderson (1): | 29 | target/arm/ptw.c | 11 ++++++----- |
27 | docs/devel: Document decodetree no-overlap groups | 30 | 1 file changed, 6 insertions(+), 5 deletions(-) |
28 | |||
29 | docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- | ||
30 | target/arm/translate-a64.c | 6 ++++-- | ||
31 | 2 files changed, 22 insertions(+), 13 deletions(-) | ||
32 | diff view generated by jsdifflib |
1 | From: Peter Collingbourne <pcc@google.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These instructions use zero as the discriminator, not SP. | 3 | Only perform the extract of GP during the stage1 walk. |
4 | 4 | ||
5 | Signed-off-by: Peter Collingbourne <pcc@google.com> | 5 | Reported-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Message-id: 20200804002849.30268-1-pcc@google.com | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | target/arm/translate-a64.c | 6 ++++-- | 11 | target/arm/ptw.c | 10 +++++----- |
12 | 1 file changed, 4 insertions(+), 2 deletions(-) | 12 | 1 file changed, 5 insertions(+), 5 deletions(-) |
13 | 13 | ||
14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate-a64.c | 16 | --- a/target/arm/ptw.c |
17 | +++ b/target/arm/translate-a64.c | 17 | +++ b/target/arm/ptw.c |
18 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, | 18 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
19 | 19 | result->f.attrs.secure = false; | |
20 | if (s->pauth_active) { | ||
21 | if (use_key_a) { | ||
22 | - gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | ||
23 | + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, | ||
24 | + new_tmp_a64_zero(s)); | ||
25 | } else { | ||
26 | - gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | ||
27 | + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, | ||
28 | + new_tmp_a64_zero(s)); | ||
29 | } | ||
30 | } | 20 | } |
31 | 21 | ||
22 | - /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
23 | - if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
24 | - result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
25 | - } | ||
26 | - | ||
27 | if (regime_is_stage2(mmu_idx)) { | ||
28 | result->cacheattrs.is_s2_format = true; | ||
29 | result->cacheattrs.attrs = extract32(attrs, 2, 4); | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
31 | assert(attrindx <= 7); | ||
32 | result->cacheattrs.is_s2_format = false; | ||
33 | result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8); | ||
34 | + | ||
35 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ | ||
36 | + if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { | ||
37 | + result->f.guarded = extract64(attrs, 50, 1); /* GP */ | ||
38 | + } | ||
39 | } | ||
40 | |||
41 | /* | ||
32 | -- | 42 | -- |
33 | 2.20.1 | 43 | 2.34.1 |
34 | |||
35 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When support for this feature went in, the update to the | 3 | The guarded bit comes from the stage1 walk. |
4 | documentation was forgotten. | ||
5 | 4 | ||
6 | Fixes: 067e8b0f45d6 | 5 | Fixes: Coverity CID 1507929 |
7 | Reported-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Message-id: 20200803205708.315829-1-richard.henderson@linaro.org | 8 | Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 10 | --- |
13 | docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- | 11 | target/arm/ptw.c | 1 + |
14 | 1 file changed, 18 insertions(+), 11 deletions(-) | 12 | 1 file changed, 1 insertion(+) |
15 | 13 | ||
16 | diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
17 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/docs/devel/decodetree.rst | 16 | --- a/target/arm/ptw.c |
19 | +++ b/docs/devel/decodetree.rst | 17 | +++ b/target/arm/ptw.c |
20 | @@ -XXX,XX +XXX,XX @@ Pattern Groups | 18 | @@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, |
21 | 19 | ||
22 | Syntax:: | 20 | assert(!s1.is_s2_format); |
23 | 21 | ret.is_s2_format = false; | |
24 | - group := '{' ( pat_def | group )+ '}' | 22 | + ret.guarded = s1.guarded; |
25 | + group := overlap_group | no_overlap_group | 23 | |
26 | + overlap_group := '{' ( pat_def | group )+ '}' | 24 | if (s1.attrs == 0xf0) { |
27 | + no_overlap_group := '[' ( pat_def | group )+ ']' | 25 | tagged = true; |
28 | |||
29 | -A *group* begins with a lone open-brace, with all subsequent lines | ||
30 | -indented two spaces, and ending with a lone close-brace. Groups | ||
31 | -may be nested, increasing the required indentation of the lines | ||
32 | -within the nested group to two spaces per nesting level. | ||
33 | +A *group* begins with a lone open-brace or open-bracket, with all | ||
34 | +subsequent lines indented two spaces, and ending with a lone | ||
35 | +close-brace or close-bracket. Groups may be nested, increasing the | ||
36 | +required indentation of the lines within the nested group to two | ||
37 | +spaces per nesting level. | ||
38 | |||
39 | -Unlike ungrouped patterns, grouped patterns are allowed to overlap. | ||
40 | -Conflicts are resolved by selecting the patterns in order. If all | ||
41 | -of the fixedbits for a pattern match, its translate function will | ||
42 | -be called. If the translate function returns false, then subsequent | ||
43 | -patterns within the group will be matched. | ||
44 | +Patterns within overlap groups are allowed to overlap. Conflicts are | ||
45 | +resolved by selecting the patterns in order. If all of the fixedbits | ||
46 | +for a pattern match, its translate function will be called. If the | ||
47 | +translate function returns false, then subsequent patterns within the | ||
48 | +group will be matched. | ||
49 | + | ||
50 | +Patterns within no-overlap groups are not allowed to overlap, just | ||
51 | +the same as ungrouped patterns. Thus no-overlap groups are intended | ||
52 | +to be nested inside overlap groups. | ||
53 | |||
54 | The following example from PA-RISC shows specialization of the *or* | ||
55 | instruction:: | ||
56 | @@ -XXX,XX +XXX,XX @@ instruction:: | ||
57 | When the *cf* field is zero, the instruction has no side effects, | ||
58 | and may be specialized. When the *rt* field is zero, the output | ||
59 | is discarded and so the instruction has no effect. When the *rt2* | ||
60 | -field is zero, the operation is ``reg[rt] | 0`` and so encodes | ||
61 | +field is zero, the operation is ``reg[r1] | 0`` and so encodes | ||
62 | the canonical register copy operation. | ||
63 | |||
64 | The output from the generator might look like:: | ||
65 | -- | 26 | -- |
66 | 2.20.1 | 27 | 2.34.1 |
67 | |||
68 | diff view generated by jsdifflib |