Series comparison

-[PULL 0/2] target-arm queue
+[PULL 0/1] target-arm queue
-Couple of last-minute things for rc3...
+The following changes since commit e3debd5e7d0ce031356024878a0a18b9d109354a:
--- PMM
+  Merge tag 'pull-request-2023-03-24' of https://gitlab.com/thuth/qemu into staging (2023-03-24 16:08:46 +0000)
 The following changes since commit d15532d91be177e7528310e0110e39f915779a99:
   Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230328
-for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995:
+for you to fetch changes up to 46e3b237c52e0c48bfd81bce020b51fbe300b23a:
-  target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100)
+  target/arm/gdbstub: Only advertise M-profile features if TCG available (2023-03-28 10:53:40 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Fix decode of LDRA[AB] instructions
+ * fix part of the "TCG-disabled builds are broken" issue
  * docs/devel: Document decodetree no-overlap groups
 ----------------------------------------------------------------
-Peter Collingbourne (1):
+Philippe Mathieu-Daudé (1):
-      target/arm: Fix decode of LDRA[AB] instructions
+      target/arm/gdbstub: Only advertise M-profile features if TCG available
-Richard Henderson (1):
+ target/arm/gdbstub.c | 5 +++--
-      docs/devel: Document decodetree no-overlap groups
+file changed, 3 insertions(+), 2 deletions(-)
- docs/devel/decodetree.rst  | 29 ++++++++++++++++++-----------
- target/arm/translate-a64.c |  6 ++++--
-files changed, 22 insertions(+), 13 deletions(-)

-[PULL 1/2] docs/devel: Document decodetree no-overlap groups
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-When support for this feature went in, the update to the
-documentation was forgotten.
-Fixes: 067e8b0f45d6
-Reported-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20200803205708.315829-1-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- docs/devel/decodetree.rst | 29 ++++++++++++++++++-----------
-file changed, 18 insertions(+), 11 deletions(-)
-diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
-index XXXXXXX..XXXXXXX 100644
---- a/docs/devel/decodetree.rst
-+++ b/docs/devel/decodetree.rst
-@@ -XXX,XX +XXX,XX @@ Pattern Groups
- Syntax::
--  group    := '{' ( pat_def | group )+ '}'
-+  group            := overlap_group | no_overlap_group
-+  overlap_group    := '{' ( pat_def | group )+ '}'
-+  no_overlap_group := '[' ( pat_def | group )+ ']'
--A *group* begins with a lone open-brace, with all subsequent lines
--indented two spaces, and ending with a lone close-brace.  Groups
--may be nested, increasing the required indentation of the lines
--within the nested group to two spaces per nesting level.
-+A *group* begins with a lone open-brace or open-bracket, with all
-+subsequent lines indented two spaces, and ending with a lone
-+close-brace or close-bracket.  Groups may be nested, increasing the
-+required indentation of the lines within the nested group to two
-+spaces per nesting level.
--Unlike ungrouped patterns, grouped patterns are allowed to overlap.
--Conflicts are resolved by selecting the patterns in order.  If all
--of the fixedbits for a pattern match, its translate function will
--be called.  If the translate function returns false, then subsequent
--patterns within the group will be matched.
-+Patterns within overlap groups are allowed to overlap.  Conflicts are
-+resolved by selecting the patterns in order.  If all of the fixedbits
-+for a pattern match, its translate function will be called.  If the
-+translate function returns false, then subsequent patterns within the
-+group will be matched.
-+
-+Patterns within no-overlap groups are not allowed to overlap, just
-+the same as ungrouped patterns.  Thus no-overlap groups are intended
-+to be nested inside overlap groups.
- The following example from PA-RISC shows specialization of the *or*
- instruction::
-@@ -XXX,XX +XXX,XX @@ instruction::
- When the *cf* field is zero, the instruction has no side effects,
- and may be specialized.  When the *rt* field is zero, the output
- is discarded and so the instruction has no effect.  When the *rt2*
--field is zero, the operation is ``reg[rt] | 0`` and so encodes
-+field is zero, the operation is ``reg[r1] | 0`` and so encodes
- the canonical register copy operation.
- The output from the generator might look like::
---
-.20.1

-[PULL 2/2] target/arm: Fix decode of LDRA[AB] instructions
+[PULL 1/1] target/arm/gdbstub: Only advertise M-profile features if TCG available
-From: Peter Collingbourne <pcc@google.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-These instructions use zero as the discriminator, not SP.
+Cortex-M profile is only emulable from TCG accelerator. Restrict
 the GDBstub features to its availability in order to avoid a link
 error when TCG is not enabled:
-Signed-off-by: Peter Collingbourne <pcc@google.com>
+  Undefined symbols for architecture arm64:
-Message-id: 20200804002849.30268-1-pcc@google.com
+    "_arm_v7m_get_sp_ptr", referenced from:
         _m_sysreg_get in target_arm_gdbstub.c.o
     "_arm_v7m_mrs_control", referenced from:
         _arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
   ld: symbol(s) not found for architecture arm64
   clang: error: linker command failed with exit code 1 (use -v to see invocation)
 Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20230322142902.69511-3-philmd@linaro.org
 [PMM: add #include since I cherry-picked this patch from the series]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 6 ++++--
+ target/arm/gdbstub.c | 5 +++--
-file changed, 4 insertions(+), 2 deletions(-)
+file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/target/arm/gdbstub.c
-+++ b/target/arm/translate-a64.c
++++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
+@@ -XXX,XX +XXX,XX @@
+ #include "cpu.h"
-     if (s->pauth_active) {
+ #include "exec/gdbstub.h"
-         if (use_key_a) {
+ #include "gdbstub/helpers.h"
--            gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
++#include "sysemu/tcg.h"
-+            gen_helper_autda(dirty_addr, cpu_env, dirty_addr,
+ #include "internals.h"
-+                             new_tmp_a64_zero(s));
+ #include "cpregs.h"
-         } else {
--            gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
-+            gen_helper_autdb(dirty_addr, cpu_env, dirty_addr,
+, "arm-vfp-sysregs.xml", 0);
 +                             new_tmp_a64_zero(s));
          }
      }
+-    if (cpu_isar_feature(aa32_mve, cpu)) {
 +    if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
          gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
 , "arm-m-profile-mve.xml", 0);
      }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                               arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
                               "system-registers.xml", 0);
 -    if (arm_feature(env, ARM_FEATURE_M)) {
 +    if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
          gdb_register_coprocessor(cs,
              arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
              arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
 --
-.20.1
+.34.1

Couple of last-minute things for rc3...

-- PMM

The following changes since commit d15532d91be177e7528310e0110e39f915779a99:

Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804

for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995:

target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix decode of LDRA[AB] instructions
 * docs/devel: Document decodetree no-overlap groups

----------------------------------------------------------------
Peter Collingbourne (1):
      target/arm: Fix decode of LDRA[AB] instructions

Richard Henderson (1):
      docs/devel: Document decodetree no-overlap groups

docs/devel/decodetree.rst  | 29 ++++++++++++++++++-----------
 target/arm/translate-a64.c |  6 ++++--
 2 files changed, 22 insertions(+), 13 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

When support for this feature went in, the update to the
documentation was forgotten.

Fixes: 067e8b0f45d6
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200803205708.315829-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/devel/decodetree.rst | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/devel/decodetree.rst
+++ b/docs/devel/decodetree.rst
@@ -XXX,XX +XXX,XX @@ Pattern Groups
 
 Syntax::
 
-  group    := '{' ( pat_def | group )+ '}'
+  group            := overlap_group | no_overlap_group
+  overlap_group    := '{' ( pat_def | group )+ '}'
+  no_overlap_group := '[' ( pat_def | group )+ ']'
 
-A *group* begins with a lone open-brace, with all subsequent lines
-indented two spaces, and ending with a lone close-brace.  Groups
-may be nested, increasing the required indentation of the lines
-within the nested group to two spaces per nesting level.
+A *group* begins with a lone open-brace or open-bracket, with all
+subsequent lines indented two spaces, and ending with a lone
+close-brace or close-bracket.  Groups may be nested, increasing the
+required indentation of the lines within the nested group to two
+spaces per nesting level.
 
-Unlike ungrouped patterns, grouped patterns are allowed to overlap.
-Conflicts are resolved by selecting the patterns in order.  If all
-of the fixedbits for a pattern match, its translate function will
-be called.  If the translate function returns false, then subsequent
-patterns within the group will be matched.
+Patterns within overlap groups are allowed to overlap.  Conflicts are
+resolved by selecting the patterns in order.  If all of the fixedbits
+for a pattern match, its translate function will be called.  If the
+translate function returns false, then subsequent patterns within the
+group will be matched.
+
+Patterns within no-overlap groups are not allowed to overlap, just
+the same as ungrouped patterns.  Thus no-overlap groups are intended
+to be nested inside overlap groups.
 
 The following example from PA-RISC shows specialization of the *or*
 instruction::
@@ -XXX,XX +XXX,XX @@ instruction::
 When the *cf* field is zero, the instruction has no side effects,
 and may be specialized.  When the *rt* field is zero, the output
 is discarded and so the instruction has no effect.  When the *rt2*
-field is zero, the operation is ``reg[rt] | 0`` and so encodes
+field is zero, the operation is ``reg[r1] | 0`` and so encodes
 the canonical register copy operation.
 
 The output from the generator might look like::
-- 
2.20.1

From: Peter Collingbourne <pcc@google.com>

These instructions use zero as the discriminator, not SP.

Signed-off-by: Peter Collingbourne <pcc@google.com>
Message-id: 20200804002849.30268-1-pcc@google.com
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
 
     if (s->pauth_active) {
         if (use_key_a) {
-            gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
+            gen_helper_autda(dirty_addr, cpu_env, dirty_addr,
+                             new_tmp_a64_zero(s));
         } else {
-            gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]);
+            gen_helper_autdb(dirty_addr, cpu_env, dirty_addr,
+                             new_tmp_a64_zero(s));
         }
     }
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Cortex-M profile is only emulable from TCG accelerator. Restrict
the GDBstub features to its availability in order to avoid a link
error when TCG is not enabled:

Undefined symbols for architecture arm64:
    "_arm_v7m_get_sp_ptr", referenced from:
        _m_sysreg_get in target_arm_gdbstub.c.o
    "_arm_v7m_mrs_control", referenced from:
        _arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o
  ld: symbol(s) not found for architecture arm64
  clang: error: linker command failed with exit code 1 (use -v to see invocation)

Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230322142902.69511-3-philmd@linaro.org
[PMM: add #include since I cherry-picked this patch from the series]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "exec/gdbstub.h"
 #include "gdbstub/helpers.h"
+#include "sysemu/tcg.h"
 #include "internals.h"
 #include "cpregs.h"
 
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                                      2, "arm-vfp-sysregs.xml", 0);
         }
     }
-    if (cpu_isar_feature(aa32_mve, cpu)) {
+    if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {
         gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
                                  1, "arm-m-profile-mve.xml", 0);
     }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
                              arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
                              "system-registers.xml", 0);
 
-    if (arm_feature(env, ARM_FEATURE_M)) {
+    if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {
         gdb_register_coprocessor(cs,
             arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
             arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
-- 
2.34.1